From e73d7034d8543e81be6899a66e266ecff2597362 Mon Sep 17 00:00:00 2001
From: Zane Kaminski <zanekaminski@gmail.com>
Date: Thu, 28 Dec 2023 23:12:12 -0500
Subject: [PATCH] RC

---
 CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf    |    5 +-
 .../RAM2E_LCMXO2_1200HC_tcl.html              |   51 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.alt       |   41 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr   |   52 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.bgn       |    6 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.bit       |  Bin 9265 -> 9711 bytes
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.edi       | 6972 ++++++++++-------
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.jed       | 1183 ++-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.mrp       |  356 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.pad       |  126 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.prf       |   75 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.srr       |  377 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.tw1       |   66 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1.twr       | 1298 +--
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html  |    2 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt   |   36 +-
 .../RAM2E_LCMXO2_1200HC_impl1_iotiming.html   |  140 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf | 4860 +++++++-----
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo  | 6417 +++++++++------
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html  |  290 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html  |  126 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_par.html  |   86 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt  |    6 +-
 .../RAM2E_LCMXO2_1200HC_impl1_summary.html    |    2 +-
 .../RAM2E_LCMXO2_1200HC_impl1_synplify.html   |  377 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html  |   72 +-
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html  | 1304 +--
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf    | 5427 +++++++------
 .../impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo     | 6568 +++++++++-------
 .../impl1/hdla_gen_hierarchy.html             |    8 +-
 .../impl1/ram2e_lcmxo2_1200hc_impl1.ior       |  140 +-
 CPLD/LCMXO2-1200HC/promote.xml                |    2 +-
 CPLD/LCMXO2-1200HC/reportview.xml             |    2 +-
 CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf      |    5 +-
 CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html |   37 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1.alt        |   41 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1.areasrr    |   52 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1.bgn        |    4 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1.bit        |  Bin 6447 -> 6942 bytes
 .../impl1/RAM2E_LCMXO2_640HC_impl1.edi        | 6972 ++++++++++-------
 .../impl1/RAM2E_LCMXO2_640HC_impl1.jed        |  859 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1.mrp        |  370 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1.pad        |  126 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1.prf        |   75 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1.srr        |  471 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1.tw1        |   70 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1.twr        | 1534 ++--
 .../impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html   |    8 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt    |   38 +-
 .../RAM2E_LCMXO2_640HC_impl1_iotiming.html    |  143 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf  | 4860 +++++++-----
 .../impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo   | 6419 +++++++++------
 .../impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html   |  300 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1_pad.html   |  126 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1_par.html   |  101 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt   |    8 +-
 .../RAM2E_LCMXO2_640HC_impl1_summary.html     |    6 +-
 .../RAM2E_LCMXO2_640HC_impl1_synplify.html    |  471 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html   |   76 +-
 .../impl1/RAM2E_LCMXO2_640HC_impl1_twr.html   | 1540 ++--
 .../impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf     | 5470 +++++++------
 .../impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo      | 6457 +++++++++------
 .../impl1/hdla_gen_hierarchy.html             |   14 +-
 .../impl1/ram2e_lcmxo2_640hc_impl1.ior        |  143 +-
 CPLD/LCMXO2-640HC/promote.xml                 |    2 +-
 CPLD/LCMXO2-640HC/reportview.xml              |    2 +-
 CPLD/MAXII/RAM2E.qsf                          |  108 +-
 CPLD/MAXII/output_files/RAM2E.asm.rpt         |   48 +-
 CPLD/MAXII/output_files/RAM2E.done            |    2 +-
 CPLD/MAXII/output_files/RAM2E.fit.rpt         |  584 +-
 CPLD/MAXII/output_files/RAM2E.fit.summary     |    6 +-
 CPLD/MAXII/output_files/RAM2E.flow.rpt        |   48 +-
 CPLD/MAXII/output_files/RAM2E.jdi             |    2 +-
 CPLD/MAXII/output_files/RAM2E.map.rpt         |  205 +-
 CPLD/MAXII/output_files/RAM2E.map.smsg        |    6 +-
 CPLD/MAXII/output_files/RAM2E.map.summary     |    6 +-
 CPLD/MAXII/output_files/RAM2E.pin             |   36 +-
 CPLD/MAXII/output_files/RAM2E.pof             |  Bin 7861 -> 7877 bytes
 CPLD/MAXII/output_files/RAM2E.sta.rpt         |  803 +-
 CPLD/MAXII/output_files/RAM2E.sta.summary     |   34 +-
 CPLD/MAXV/RAM2E.qsf                           |  108 +-
 CPLD/MAXV/RAM2E.qws                           |  Bin 619 -> 619 bytes
 CPLD/MAXV/output_files/RAM2E.asm.rpt          |   46 +-
 CPLD/MAXV/output_files/RAM2E.done             |    2 +-
 CPLD/MAXV/output_files/RAM2E.fit.rpt          |  596 +-
 CPLD/MAXV/output_files/RAM2E.fit.summary      |    6 +-
 CPLD/MAXV/output_files/RAM2E.flow.rpt         |   48 +-
 CPLD/MAXV/output_files/RAM2E.jdi              |    2 +-
 CPLD/MAXV/output_files/RAM2E.map.rpt          |  205 +-
 CPLD/MAXV/output_files/RAM2E.map.smsg         |    6 +-
 CPLD/MAXV/output_files/RAM2E.map.summary      |    6 +-
 CPLD/MAXV/output_files/RAM2E.pin              |   36 +-
 CPLD/MAXV/output_files/RAM2E.pof              |  Bin 7861 -> 7877 bytes
 CPLD/MAXV/output_files/RAM2E.sta.rpt          |  800 +-
 CPLD/MAXV/output_files/RAM2E.sta.summary      |   34 +-
 CPLD/RAM2E-LCMXO2.lpf                         |  118 +-
 CPLD/RAM2E-MAX.sdc                            |    4 +-
 CPLD/RAM2E.mif                                |   51 +-
 CPLD/RAM2E.qsf                                |  259 -
 CPLD/RAM2E.v                                  |   92 +-
 CPLD/UFM-LCMXO2.v                             |    5 +-
 CPLD/UFM-MAX.v                                |    3 +-
 Documentation/GW4203BDevNote.pdf              |  Bin 720747 -> 720318 bytes
 Documentation/GW4203BManual.pdf               |  Bin 1236565 -> 1236529 bytes
 104 files changed, 44355 insertions(+), 33233 deletions(-)
 delete mode 100644 CPLD/RAM2E.qsf

diff --git a/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf
index 0468376..8ce05d9 100644
--- a/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf
+++ b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf
@@ -3,9 +3,12 @@
     <Options/>
     <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
         <Options def_top="RAM2E" top="RAM2E"/>
-        <Source name="../RAM2E-LCMXO2.v" type="Verilog" type_short="Verilog">
+        <Source name="../RAM2E.v" type="Verilog" type_short="Verilog">
             <Options top_module="RAM2E"/>
         </Source>
+        <Source name="../UFM-LCMXO2.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
         <Source name="REFB.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
diff --git a/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html
index cf1147b..be4e2bb 100644
--- a/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html
+++ b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html
@@ -6,13 +6,56 @@
 -->
 </STYLE>
 </HEAD>
-<PRE><A name="pn230921045934"></A><B><U><big>pn230921045934</big></U></B>
-#Start recording tcl command: 9/21/2023 04:58:28
+<PRE><A name="pn231218062259"></A><B><U><big>pn231218062259</big></U></B>
+#Start recording tcl command: 12/5/2023 23:09:24
 #Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
 prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
-prj_run PAR -impl impl1 -task IOTiming
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+#Stop recording: 12/18/2023 06:22:59
+
+
+
+<A name="pn231226182753"></A><B><U><big>pn231226182753</big></U></B>
+#Start recording tcl command: 12/26/2023 18:26:59
+#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
+#Stop recording: 12/26/2023 18:27:53
+
+
+
+<A name="pn231226232448"></A><B><U><big>pn231226232448</big></U></B>
+#Start recording tcl command: 12/26/2023 21:40:03
+#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
+prj_run Export -impl impl1
 prj_run Export -impl impl1 -forceAll
-#Stop recording: 9/21/2023 04:59:34
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_src exclude "//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v"
+prj_src remove "//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v"
+#Stop recording: 12/26/2023 23:24:48
+
+
+
+<A name="pn231226233648"></A><B><U><big>pn231226233648</big></U></B>
+#Start recording tcl command: 12/26/2023 23:26:30
+#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 12/26/2023 23:36:48
+
+
+
+<A name="pn231226233754"></A><B><U><big>pn231226233754</big></U></B>
+#Start recording tcl command: 12/26/2023 23:36:58
+#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
+#Stop recording: 12/26/2023 23:37:54
 
 
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt
index 0f72508..6a839f5 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt
@@ -1,14 +1,12 @@
 NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
 NOTE All Rights Reserved *
-NOTE DATE CREATED: Thu Sep 21 05:35:26 2023 *
+NOTE DATE CREATED: Thu Dec 28 23:10:34 2023 *
 NOTE DESIGN NAME: RAM2E *
 NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
 NOTE PIN ASSIGNMENTS *
 NOTE PINS RD[0] : 36 : inout *
 NOTE PINS LED : 35 : out *
 NOTE PINS C14M : 62 : in *
-NOTE PINS DQMH : 49 : out *
-NOTE PINS DQML : 48 : out *
 NOTE PINS RD[7] : 43 : inout *
 NOTE PINS RD[6] : 42 : inout *
 NOTE PINS RD[5] : 41 : inout *
@@ -16,25 +14,27 @@ NOTE PINS RD[4] : 40 : inout *
 NOTE PINS RD[3] : 39 : inout *
 NOTE PINS RD[2] : 38 : inout *
 NOTE PINS RD[1] : 37 : inout *
-NOTE PINS RA[11] : 59 : out *
-NOTE PINS RA[10] : 64 : out *
-NOTE PINS RA[9] : 63 : out *
-NOTE PINS RA[8] : 65 : out *
-NOTE PINS RA[7] : 67 : out *
-NOTE PINS RA[6] : 69 : out *
-NOTE PINS RA[5] : 71 : out *
-NOTE PINS RA[4] : 75 : out *
-NOTE PINS RA[3] : 74 : out *
-NOTE PINS RA[2] : 70 : out *
-NOTE PINS RA[1] : 68 : out *
-NOTE PINS RA[0] : 66 : out *
+NOTE PINS DQMH : 49 : out *
+NOTE PINS DQML : 48 : out *
+NOTE PINS RAout[11] : 59 : out *
+NOTE PINS RAout[10] : 64 : out *
+NOTE PINS RAout[9] : 63 : out *
+NOTE PINS RAout[8] : 65 : out *
+NOTE PINS RAout[7] : 67 : out *
+NOTE PINS RAout[6] : 69 : out *
+NOTE PINS RAout[5] : 71 : out *
+NOTE PINS RAout[4] : 75 : out *
+NOTE PINS RAout[3] : 74 : out *
+NOTE PINS RAout[2] : 70 : out *
+NOTE PINS RAout[1] : 68 : out *
+NOTE PINS RAout[0] : 66 : out *
 NOTE PINS BA[1] : 60 : out *
 NOTE PINS BA[0] : 58 : out *
-NOTE PINS nRWE : 51 : out *
-NOTE PINS nCAS : 52 : out *
-NOTE PINS nRAS : 54 : out *
-NOTE PINS nCS : 57 : out *
-NOTE PINS CKE : 53 : out *
+NOTE PINS nRWEout : 51 : out *
+NOTE PINS nCASout : 52 : out *
+NOTE PINS nRASout : 54 : out *
+NOTE PINS nCSout : 57 : out *
+NOTE PINS CKEout : 53 : out *
 NOTE PINS nVOE : 10 : out *
 NOTE PINS Vout[7] : 12 : out *
 NOTE PINS Vout[6] : 14 : out *
@@ -71,7 +71,6 @@ NOTE PINS Ain[1] : 2 : in *
 NOTE PINS Ain[0] : 3 : in *
 NOTE PINS nC07X : 34 : in *
 NOTE PINS nEN80 : 82 : in *
-NOTE PINS nWE80 : 83 : in *
 NOTE PINS nWE : 29 : in *
 NOTE PINS PHI1 : 85 : in *
 NOTE CONFIGURATION MODE: NONE *
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr
index 717f690..927a5fd 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr
@@ -1,41 +1,61 @@
 ----------------------------------------------------------------------
 Report for cell RAM2E.verilog
 
-Register bits: 111 of 1280 (9%)
+Register bits: 122 of 1280 (10%)
 PIC Latch:       0
-I/O cells:       70
+I/O cells:       69
                                           Cell usage:
                                cell       count    Res Usage(%)
                                  BB        8       100.0
                               CCU2D        9       100.0
                                 EFB        1       100.0
-                            FD1P3AX       48       100.0
+                            FD1P3AX       61       100.0
                             FD1P3IX        1       100.0
-                            FD1S3AX       22       100.0
-                            FD1S3IX        4       100.0
+                            FD1S3AX       21       100.0
+                            FD1S3AY        4       100.0
+                            FD1S3IX        6       100.0
                                 GSR        1       100.0
-                                 IB       22       100.0
+                                 IB       21       100.0
                            IFS1P3DX        1       100.0
                                 INV        1       100.0
                                  OB       40       100.0
-                           OFS1P3BX        6       100.0
-                           OFS1P3DX       27       100.0
+                           OFS1P3BX        5       100.0
+                           OFS1P3DX       21       100.0
                            OFS1P3IX        2       100.0
-                           ORCALUT4      221       100.0
+                           ORCALUT4      277       100.0
+                              PFUMX        3       100.0
                                 PUR        1       100.0
-                                VHI        2       100.0
-                                VLO        2       100.0
+                                VHI        3       100.0
+                                VLO        3       100.0
 SUB MODULES 
+                          RAM2E_UFM        1       100.0
                                REFB        1       100.0
                             
-                         TOTAL           420           
+                         TOTAL           492           
 ----------------------------------------------------------------------
-Report for cell REFB.netlist
-     Instance path:  ufmefb
+Report for cell RAM2E_UFM.netlist
+     Instance path:  ram2e_ufm
                                           Cell usage:
                                cell       count    Res Usage(%)
                                 EFB        1       100.0
-                                VHI        1        50.0
-                                VLO        1        50.0
+                            FD1P3AX       30        49.2
+                            FD1P3IX        1       100.0
+                            FD1S3IX        1        16.7
+                           ORCALUT4      272        98.2
+                              PFUMX        3       100.0
+                                VHI        2        66.7
+                                VLO        2        66.7
+SUB MODULES 
+                               REFB        1       100.0
+                            
+                         TOTAL           313           
+----------------------------------------------------------------------
+Report for cell REFB.netlist
+     Instance path:  ram2e_ufm.ufmefb
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                                EFB        1       100.0
+                                VHI        1        33.3
+                                VLO        1        33.3
                             
                          TOTAL             3           
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn
index 0881a22..f295f02 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn
@@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Sep 21 05:35:21 2023
+Thu Dec 28 23:10:30 2023
 
 
 Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
@@ -81,6 +81,6 @@ UFM Utilization: General Purpose Flash Memory.
 Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
 Initialized UFM Pages:                   321 Pages (Page 190 to Page 510).
  
-Total CPU Time: 4 secs 
-Total REAL Time: 5 secs 
+Total CPU Time: 3 secs 
+Total REAL Time: 4 secs 
 Peak Memory Usage: 275 MB
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bit b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bit
index 47ca44149c567b7f41421f81f15a82f1a873b147..6ed6435046874e1cba51ec42089e1e08797fefe0 100644
GIT binary patch
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diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.edi b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.edi
index 1b6312f..d3d2367 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.edi
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.edi
@@ -4,7 +4,7 @@
   (keywordMap (keywordLevel 0))
   (status
     (written
-      (timeStamp 2023 9 21 5 34 43)
+      (timeStamp 2023 12 28 23 9 53)
       (author "Synopsys, Inc.")
       (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
      )
@@ -70,6 +70,15 @@
          )
        )
     )
+    (cell FD1S3AY (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
     (cell FD1S3AX (cellType GENERIC)
        (view PRIM (viewType NETLIST)
          (interface
@@ -155,6 +164,16 @@
          )
        )
     )
+    (cell PFUMX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port ALUT (direction INPUT))
+           (port BLUT (direction INPUT))
+           (port C0 (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
     (cell GSR (cellType GENERIC)
        (view PRIM (viewType NETLIST)
          (interface
@@ -726,248 +745,184 @@
         (property orig_inst_of (string "REFB"))
        )
     )
-    (cell RAM2E (cellType GENERIC)
-       (view verilog (viewType NETLIST)
+    (cell RAM2E_UFM (cellType GENERIC)
+       (view netlist (viewType NETLIST)
          (interface
-           (port C14M (direction INPUT))
-           (port PHI1 (direction INPUT))
-           (port LED (direction OUTPUT))
-           (port nWE (direction INPUT))
-           (port nWE80 (direction INPUT))
-           (port nEN80 (direction INPUT))
-           (port nC07X (direction INPUT))
-           (port (array (rename ain "Ain[7:0]") 8) (direction INPUT))
-           (port (array (rename din "Din[7:0]") 8) (direction INPUT))
-           (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT))
-           (port nDOE (direction OUTPUT))
-           (port (array (rename vout "Vout[7:0]") 8) (direction OUTPUT))
-           (port nVOE (direction OUTPUT))
-           (port CKE (direction OUTPUT))
-           (port nCS (direction OUTPUT))
-           (port nRAS (direction OUTPUT))
-           (port nCAS (direction OUTPUT))
-           (port nRWE (direction OUTPUT))
-           (port (array (rename ba "BA[1:0]") 2) (direction OUTPUT))
-           (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT))
-           (port (array (rename rd "RD[7:0]") 8) (direction INOUT))
-           (port DQML (direction OUTPUT))
-           (port DQMH (direction OUTPUT))
+           (port (array (rename ra_35 "RA_35[11:0]") 12) (direction OUTPUT))
+           (port (array (rename ain_c "Ain_c[7:0]") 8) (direction INPUT))
+           (port CmdTout_3_0 (direction OUTPUT))
+           (port (array (rename rwbank "RWBank[7:0]") 8) (direction INPUT))
+           (port (array (rename fs "FS[15:0]") 16) (direction INPUT))
+           (port (array (rename ra "RA[11:0]") 12) (direction INPUT))
+           (port (array (rename rc_3 "RC_3[2:1]") 2) (direction OUTPUT))
+           (port (array (rename rwbank_3 "RWBank_3[7:0]") 8) (direction OUTPUT))
+           (port (array (rename din_c "Din_c[7:0]") 8) (direction INPUT))
+           (port S_s_0_0_0 (direction OUTPUT))
+           (port (array (rename ba_4 "BA_4[1:0]") 2) (direction OUTPUT))
+           (port (array (rename cs "CS[2:0]") 3) (direction INPUT))
+           (port (array (rename cmdtout "CmdTout[2:1]") 2) (direction INPUT))
+           (port (array (rename rc "RC[2:1]") 2) (direction INPUT))
+           (port (array (rename s "S[3:0]") 4) (direction INPUT))
+           (port N_359_i (direction OUTPUT))
+           (port CmdRWMaskSet_3 (direction OUTPUT))
+           (port CmdLEDSet_3 (direction OUTPUT))
+           (port N_667 (direction OUTPUT))
+           (port N_666 (direction OUTPUT))
+           (port N_665 (direction OUTPUT))
+           (port N_664 (direction OUTPUT))
+           (port N_663 (direction OUTPUT))
+           (port N_662 (direction OUTPUT))
+           (port N_648 (direction OUTPUT))
+           (port CmdSetRWBankFFLED (direction INPUT))
+           (port CmdLEDGet (direction INPUT))
+           (port Vout3 (direction OUTPUT))
+           (port un9_VOEEN_0_a2_0_a3_0_a3_1z (direction OUTPUT))
+           (port N_263_i_1z (direction OUTPUT))
+           (port N_508 (direction OUTPUT))
+           (port RWSel_2 (direction OUTPUT))
+           (port nC07X_c (direction INPUT))
+           (port RDOE_i_1z (direction OUTPUT))
+           (port LED_c (direction OUTPUT))
+           (port Ready (direction INPUT))
+           (port nDOE_c (direction OUTPUT))
+           (port DOEEN (direction INPUT))
+           (port nEN80_c (direction INPUT))
+           (port N_360_i_1z (direction OUTPUT))
+           (port N_368_i_1z (direction OUTPUT))
+           (port N_507_i_1z (direction OUTPUT))
+           (port un2_S_2_i_0_0_o3_RNIHFHN3_1z (direction OUTPUT))
+           (port CmdLEDGet_3 (direction OUTPUT))
+           (port N_126 (direction OUTPUT))
+           (port N_362_i (direction OUTPUT))
+           (port N_369_i_1z (direction OUTPUT))
+           (port Ready3 (direction OUTPUT))
+           (port CmdSetRWBankFFLED_4 (direction OUTPUT))
+           (port N_361_i (direction OUTPUT))
+           (port N_223 (direction OUTPUT))
+           (port CmdLEDSet (direction INPUT))
+           (port CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_1z (direction OUTPUT))
+           (port CmdRWMaskSet (direction INPUT))
+           (port CmdExecMXO2_3_0_a3_0_RNI6S1P8_1z (direction OUTPUT))
+           (port N_370_i (direction OUTPUT))
+           (port nWE_c (direction INPUT))
+           (port N_358_i (direction OUTPUT))
+           (port un1_CS_0_sqmuxa_i (direction OUTPUT))
+           (port N_547_i (direction OUTPUT))
+           (port C14M_c (direction INPUT))
+           (port CO0_0 (direction INPUT))
+           (port N_187_i_1z (direction OUTPUT))
+           (port N_185_i (direction OUTPUT))
+           (port CKE_7_RNIS77M1_1z (direction OUTPUT))
+           (port N_372_i (direction OUTPUT))
+           (port S_1 (direction INPUT))
+           (port RWSel (direction INPUT))
+           (port N_201_i_1z (direction OUTPUT))
+           (port N_225_i_1z (direction OUTPUT))
+           (port BA_0_sqmuxa (direction OUTPUT))
+           (port CO0_1 (direction INPUT))
+           (port RC12 (direction OUTPUT))
+           (port N_551 (direction OUTPUT))
          )
          (contents
-          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
-          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
-          (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
-          )
-          (instance (rename S_RNII9DO1_2_1 "S_RNII9DO1_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
-          )
-          (instance (rename S_RNII9DO1_0_1 "S_RNII9DO1_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(!B+!A)))"))
-          )
-          (instance (rename wb_dati_7_0_2_RNO_3 "wb_dati_7_0_2_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)))"))
-          )
-          (instance DQML_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance (rename wb_adr_RNO_3_1 "wb_adr_RNO_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B !A))"))
-          )
-          (instance CKE_6_iv_i_0_1_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !A+C (!B !A))"))
-          )
-          (instance (rename FS_RNIOD6E_1_8 "FS_RNIOD6E_1[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B !A)))"))
-          )
-          (instance (rename wb_adr_RNO_2_1 "wb_adr_RNO_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !A+C (!B !A+B A))"))
-          )
-          (instance (rename FS_RNI9FGA_1 "FS_RNI9FGA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+A))"))
-          )
-          (instance (rename S_RNII9DO1_1 "S_RNII9DO1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance wb_rst16_i_i_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D+(C+(B+A)))"))
           )
-          (instance (rename un1_RWMask_0_sqmuxa_1_i_0_RNO_0 "un1_RWMask_0_sqmuxa_1_i_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
+          (instance (rename wb_dati_7_0_0_0_RNO_7 "wb_dati_7_0_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A))+D (B A))"))
           )
-          (instance (rename wb_dati_7_0_0_RNO_7 "wb_dati_7_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
+          (instance nRAS_s_i_0_a3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A))"))
           )
-          (instance wb_we_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A))+D (!B A))"))
+          (instance un1_RC12_i_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
           )
-          (instance wb_reqc_1_RNIRU4M1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B A)))"))
+          (instance (rename wb_dati_7_0_0_a3_3_4 "wb_dati_7_0_0_a3_3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B !A)))"))
           )
-          (instance (rename FS_RNIOD6E_0_8 "FS_RNIOD6E_0[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance (rename RA_42_0_RNO_10 "RA_42_0_RNO[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A))+D (!C (!B A)))"))
-          )
-          (instance (rename FS_RNIOD6E_8 "FS_RNIOD6E[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (!C (B A)+C (B !A)))"))
-          )
-          (instance (rename S_RNII9DO1_3_1 "S_RNII9DO1_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
-          )
-          (instance (rename FS_RNI5OOF1_15 "FS_RNI5OOF1[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename RA_35_2_0_a3_5_10 "RA_35_2_0_a3_5[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C (!B A)))"))
           )
-          (instance (rename BA_0io_RNO_0 "BA_0io_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0 "un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_0_RNO_7 "wb_dati_7_0_0_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance (rename S_s_0_0_RNO_0 "S_s_0_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C !A)"))
+          )
+          (instance CKE_7_m1_0_0_o2_RNI7FOA1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance CKE_7_m1_0_0_o2_RNIGC501 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance (rename RC_3_0_0_1 "RC_3_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A+B !A)+C (B !A))"))
+          )
+          (instance N_314_i_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(!B+!A)))"))
+          )
+          (instance nRAS_s_i_0_a3_5_RNIH7J73 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C (B A)))"))
           )
-          (instance (rename BA_0io_RNO_1 "BA_0io_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename wb_dati_7_0_0_a3_8_3 "wb_dati_7_0_0_a3_8[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance CKE_7_m1_0_0_o2_RNICM8E1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNIP4KI1_1 "S_r_i_0_o2_RNIP4KI1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C (B A)))"))
           )
-          (instance nCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B A)+D (C+(!B A)))"))
+          (instance nRAS_s_i_0_a3_5_RNIH7J73_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)))"))
           )
-          (instance wb_we_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B+A)+D (!C (!B+A)+C (!B A)))"))
+          (instance N_225_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B+!A)))"))
           )
-          (instance DOEEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (!C (B A)+C A))"))
+          (instance N_201_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B+!A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNIOGTF1_1 "S_r_i_0_o2_RNIOGTF1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C+(!B+!A)))"))
+          )
+          (instance (rename RA_35_0_0_RNO_0 "RA_35_0_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance (rename RA_35_2_0_RNO_10 "RA_35_2_0_RNO[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNIFNP81_0_2 "S_r_i_0_o2_RNIFNP81_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C A)+D (!C (!B+A)))"))
           )
           (instance wb_req_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D+(C+(B+A)))"))
           )
-          (instance (rename FS_RNIK5632_15 "FS_RNIK5632[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B !A)))"))
+          (instance CmdBitbangMXO2_RNINSM62 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (B+A))+D B)"))
           )
-          (instance DQMH_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C+(!B+!A)))"))
+          (instance wb_we_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (B+A))+D B)"))
           )
-          (instance (rename CmdTout_RNO_2 "CmdTout_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (!B A+B !A)))"))
-          )
-          (instance wb_cyc_stb_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_5_RNIC22J_4 "wb_dati_7_0_a2_5_RNIC22J[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename wb_dati_7_0_0_a3_13_RNI81UL_7 "wb_dati_7_0_0_a3_13_RNI81UL[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D (C (B A)))"))
           )
-          (instance nCS_6_u_i_a2_4_RNI3A062 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B A))"))
+          (instance CKE_7_RNIS77M1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B+A)+C A)+D A)"))
           )
-          (instance nCS_6_u_i_a2_4_RNICJKD2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
+          (instance (rename S_r_i_0_o2_RNIBAU51_1 "S_r_i_0_o2_RNIBAU51[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A))"))
           )
-          (instance wb_reqc_1_RNIEO5C1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A))"))
+          (instance N_187_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
           )
-          (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
+          (instance un1_CS_0_sqmuxa_0_0_0 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
+          (instance un1_CS_0_sqmuxa_0_0_0_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !A+C (B+!A))+D !A)"))
           )
-          (instance (rename Vout_0__CN "Vout_0_.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance PHI1reg_0io (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nRWE_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nRAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nCS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nCAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_0 "Vout_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_1 "Vout_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_2 "Vout_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_3 "Vout_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_4 "Vout_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_5 "Vout_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_6 "Vout_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_7 "Vout_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_1 "RA_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_2 "RA_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_4 "RA_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_5 "RA_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_6 "RA_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_7 "RA_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_8 "RA_0io[8]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_9 "RA_0io[9]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_10 "RA_0io[10]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_11 "RA_0io[11]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_0 "Dout_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_1 "Dout_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_2 "Dout_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_3 "Dout_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_4 "Dout_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_5 "Dout_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_6 "Dout_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_7 "Dout_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance DQML_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance DQMH_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance CKE_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename BA_0io_0 "BA_0io[0]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename BA_0io_1 "BA_0io[1]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
+          (instance un1_CS_0_sqmuxa_0_0_0_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+!A))"))
           )
           (instance wb_we (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
@@ -1009,18 +964,6 @@
           )
           (instance (rename wb_adr_7 "wb_adr[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
-          (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename S_2 "S[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename S_3 "S[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RWSel (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
           (instance (rename RWMask_0 "RWMask[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
           (instance (rename RWMask_1 "RWMask[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
@@ -1037,6 +980,3203 @@
           )
           (instance (rename RWMask_7 "RWMask[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
+          (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdSetRWBankFFChip (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdExecMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdBitbangMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename S_r_i_0_o2_RNIVM0LF_1 "S_r_i_0_o2_RNIVM0LF[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNI3VQTC_1 "S_r_i_0_o2_RNI3VQTC[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B !A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_0 "wb_adr_7_i_i[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A))+D (C A))"))
+          )
+          (instance nRAS_s_i_0_0_RNI0PC64 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance nCAS_s_i_0_a3_RNIO1UQ3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A))+D (!B !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_5 "wb_dati_7_0_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_2 "wb_dati_7_0_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_7 "wb_dati_7_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance CmdExecMXO2_3_0_a3_0_RNI6S1P8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C (B !A)+C !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_6 "wb_dati_7_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_4 "wb_dati_7_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !B)+D (!C (!B !A)+C !B))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C (!B !A)))"))
+          )
+          (instance (rename un1_RWMask_0_sqmuxa_1_i_0_0_0 "un1_RWMask_0_sqmuxa_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B A)+D (C+(!B A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_0 "wb_dati_7_0_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_1 "wb_dati_7_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C A+C (B+A)))"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A+B !A)+C B)+D (!C (B !A)+C B))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_3 "wb_dati_7_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C A+C (B+A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_4_0 "wb_adr_7_i_i_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_5_0 "wb_adr_7_i_i_5[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D C+D (C+(B !A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+!A)+C (B A))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C (!B !A)))"))
+          )
+          (instance (rename un1_LEDEN_0_sqmuxa_1_i_0_0_0 "un1_LEDEN_0_sqmuxa_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B A)+D (C+(!B A)))"))
+          )
+          (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B !A))+D (C+!A))"))
+          )
+          (instance (rename wb_dati_7_0_0_RNO_0_7 "wb_dati_7_0_0_RNO_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C (B A)+C B))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_a3_7 "wb_dati_7_0_0_0_a3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B !A+B A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_a3_6_0 "wb_adr_7_i_i_a3_6[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
+          )
+          (instance (rename RA_35_0_0_0_7 "RA_35_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance (rename RA_35_0_0_0_6 "RA_35_0_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance (rename RA_35_0_0_4 "RA_35_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance (rename RA_35_0_0_3 "RA_35_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_2_4 "wb_dati_7_0_0_a3_2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B !A)))"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C A)+D (!C (!B A)+C A))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_0_3 "wb_dati_7_0_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_6 "wb_dati_7_0_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_4 "wb_dati_7_0_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
+          )
+          (instance CKE_7_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A))"))
+          )
+          (instance CKE_7 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
+          (instance wb_cyc_stb_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C A+C (B+A))"))
+          )
+          (instance CmdExecMXO2_3_0_a3_0_RNIPG3P2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C (!B A)))"))
+          )
+          (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)+C B)+D B)"))
+          )
+          (instance nRAS_s_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A))+D !A)"))
+          )
+          (instance nCAS_s_i_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)+C !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_4 "wb_dati_7_0_0_a3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B !A))"))
+          )
+          (instance (rename RA_35_i_i_0_1 "RA_35_i_i_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B A)))"))
+          )
+          (instance (rename RA_35_0_0_2 "RA_35_0_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance (rename RA_35_0_0_5 "RA_35_0_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B A)))"))
+          )
+          (instance (rename RA_35_2_0_10 "RA_35_2_0[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance wb_we_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C (B !A)))"))
+          )
+          (instance (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C B+C (B+A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B !A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)))"))
+          )
+          (instance (rename RA_35_0_0_0_4 "RA_35_0_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
+          )
+          (instance (rename RA_35_0_0_0_0_6 "RA_35_0_0_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
+          )
+          (instance (rename RA_35_0_0_0_0_7 "RA_35_0_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
+          )
+          (instance (rename RA_35_0_0_0_3 "RA_35_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_1 "wb_dati_7_0_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_0_7 "wb_dati_7_0_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_1_0 "wb_adr_7_i_i_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A))+D C)"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C+(B A))+D (!C+(!B+A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNIFNP81_2 "S_r_i_0_o2_RNIFNP81[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C (B !A))+D (!C (!B !A)+C !A))"))
+          )
+          (instance (rename RA_35_0_0_a3_5 "RA_35_0_0_a3[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RA_35_i_i_0_a3_0_1 "RA_35_i_i_0_a3_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RA_35_0_0_a3_0_2 "RA_35_0_0_a3_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance wb_cyc_stb_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)+C !B))"))
+          )
+          (instance (rename RA_35_0_0_11 "RA_35_0_0[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C A)+D (!C (!B !A)+C (!B+A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
+          )
+          (instance CmdExecMXO2_3_0_a3_0_RNIAJ811 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)))"))
+          )
+          (instance CKE_7s2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
+          )
+          (instance (rename wb_adr_7_i_i_a3_4_0 "wb_adr_7_i_i_a3_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance (rename RA_35_0_0_9 "RA_35_0_0[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance CmdBitbangMXO2_3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance CmdSetRWBankFFLED_4_0_a8_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance Ready3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance (rename wb_adr_RNO_1_1 "wb_adr_RNO_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A))+D (C (!B+!A)))"))
+          )
+          (instance wb_we_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C (B !A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_a3_0_3 "wb_dati_7_0_0_0_a3_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance nCAS_s_i_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance SUM0_i_o2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(!B+!A))"))
+          )
+          (instance N_285_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A))"))
+          )
+          (instance N_369_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)+C (!B+!A)))"))
+          )
+          (instance (rename S_r_i_0_o2_0_RNI36E21_1 "S_r_i_0_o2_0_RNI36E21[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C !A+C (B !A)))"))
+          )
+          (instance (rename RA_35_2_0_a3_10 "RA_35_2_0_a3[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !A)+D (C (B+!A)))"))
+          )
+          (instance (rename RA_35_i_i_0_a3_1 "RA_35_i_i_0_a3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)+C (B+!A)))"))
+          )
+          (instance (rename RA_35_0_0_a3_2 "RA_35_0_0_a3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)+C (B+!A)))"))
+          )
+          (instance CmdExecMXO2_3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_9_7 "wb_dati_7_0_0_a3_9[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance CmdRWMaskSet_3_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_o2_4 "wb_dati_7_0_0_o2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B A))+D (!C (B A)+C (!B+!A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_o2_0_3 "wb_dati_7_0_0_o2_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B !A)+C (B A))+D (C (!B+!A)))"))
+          )
+          (instance CKE_7s2_0_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !A)+D (!C B+C !A))"))
+          )
+          (instance (rename BA_4_1 "BA_4[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B+!A))+D (C B))"))
+          )
+          (instance (rename BA_4_0 "BA_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B+!A))+D (C B))"))
+          )
+          (instance wb_we_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B+!A))+D (!C+(!B+!A)))"))
+          )
+          (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A)+C !B)"))
+          )
+          (instance wb_req_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C+(!B+!A)))"))
+          )
+          (instance un1_CKE75_0_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B+A)+C (!B !A+B A))+D (!C (!B+!A)+C (B+!A)))"))
+          )
+          (instance nRAS_s_i_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)))"))
+          )
+          (instance (rename S_s_0_0_0 "S_s_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+A)+D (C+(!B+A)))"))
+          )
+          (instance CmdLEDGet_3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance (rename RA_35_0_0_o2_0_5 "RA_35_0_0_o2_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)+C (!B !A))+D (!C !A+C (!B !A)))"))
+          )
+          (instance un2_S_2_i_0_0_o3_RNIHFHN3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+          )
+          (instance (rename RA_35_0_0_0_9 "RA_35_0_0_0[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B !A)+D (C+(B !A)))"))
+          )
+          (instance wb_we_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D C+D (C+(B !A)))"))
+          )
+          (instance (rename RA_35_2_0_0_10 "RA_35_2_0_0[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C A+C (B+A))"))
+          )
+          (instance (rename RA_35_0_0_0_5 "RA_35_0_0_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C !B+C (!B+!A)))"))
+          )
+          (instance (rename un1_RWMask_0_sqmuxa_1_i_0_a3_0_0_0 "un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance SUM0_i_m3_0_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
+          )
+          (instance SUM0_i_m3_0 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
+          (instance N_507_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !A)+D (!C (B+!A)+C B))"))
+          )
+          (instance N_368_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A+B !A))"))
+          )
+          (instance N_360_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !A+C (!B !A))"))
+          )
+          (instance (rename RA_35_2_0_a3_0_10 "RA_35_2_0_a3_0[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B !A)+D (!C (B !A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_9 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename RWBank_3_0_0_0 "RWBank_3_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_0_4 "RWBank_3_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_1 "RWBank_3_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_2 "RWBank_3_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_3 "RWBank_3_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_5 "RWBank_3_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_6 "RWBank_3_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_7 "RWBank_3_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C (B+A))"))
+          )
+          (instance (rename RA_35_0_0_o2_5 "RA_35_0_0_o2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)+C (B+A))+D (!C A+C (B+A)))"))
+          )
+          (instance (rename RA_35_0_0_o2_11 "RA_35_0_0_o2[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B A))+D (C+B))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_o2_1_0 "wb_adr_7_i_i_o2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B+!A))+D (!C+(!B+!A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_o2_3 "wb_dati_7_0_0_0_o2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B A))+D (!C (!B !A)+C (!B !A+B A)))"))
+          )
+          (instance (rename RC_3_0_0_2 "RC_3_0_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C !B)"))
+          )
+          (instance un1_nDOE_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(B+!A))"))
+          )
+          (instance LEDEN_RNI6G6M (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(!B+!A))"))
+          )
+          (instance RDOE_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C A)"))
+          )
+          (instance nRAS_s_i_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance (rename RA_35_2_0_a3_3_10 "RA_35_2_0_a3_3[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance SUM0_i_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C !A+C (!B !A)))"))
+          )
+          (instance (rename wb_adr_RNO_0_1 "wb_adr_RNO_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance RWSel_2_0_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)))"))
+          )
+          (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_o3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance nRAS_s_i_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(!B A+B !A)))"))
+          )
+          (instance CmdLEDGet_3_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B !A))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance CKE_7s2_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (B !A))+D (!C B))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_0_0_1 "wb_dati_7_0_0_a3_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_1_0_6 "wb_dati_7_0_0_a3_1_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C (!B A)))"))
+          )
+          (instance (rename RWMask_RNO_0 "RWMask_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_1 "RWMask_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_2 "RWMask_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_3 "RWMask_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_4 "RWMask_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_5 "RWMask_RNO[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_6 "RWMask_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance nCAS_s_i_0_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+A)+D (!C (!B+!A)+C !B))"))
+          )
+          (instance (rename wb_adr_RNO_2 "wb_adr_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename wb_adr_RNO_3 "wb_adr_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename wb_adr_RNO_7 "wb_adr_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance DQMH_4_iv_0_0_i_i_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+!A)+D (!C (!B !A)+C !B))"))
+          )
+          (instance nRAS_s_i_0_a3_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
+          )
+          (instance nRAS_s_i_0_a3_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B !A))"))
+          )
+          (instance (rename wb_adr_RNO_3_1 "wb_adr_RNO_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+!A))"))
+          )
+          (instance SUM1_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
+          )
+          (instance (rename wb_adr_RNO_2_1 "wb_adr_RNO_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+!A)+C (B A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_15_7 "wb_dati_7_0_0_a3_15[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A))"))
+          )
+          (instance nRAS_s_i_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+!A)+C !A)"))
+          )
+          (instance CKE_7s2_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance N_263_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance RA_35_2_30_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance un9_VOEEN_0_a2_0_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance Vout3_0_a3_0_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A)))"))
+          )
+          (instance (rename RWBank_3_0_0_o3_0 "RWBank_3_0_0_o3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_5_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B !A))"))
+          )
+          (instance wb_reqc_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance (rename wb_adr_RNO_4_1 "wb_adr_RNO_4[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A))"))
+          )
+          (instance Ready3_0_a3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance Ready3_0_a3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance Ready3_0_a3_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_a3_2_0_0 "wb_adr_7_i_i_a3_2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_a3_0_0 "wb_dati_7_0_0_0_a3_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B A))+D (C (!B A)))"))
+          )
+          (instance (rename wb_adr_RNO_6 "wb_adr_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !B+C A)"))
+          )
+          (instance (rename wb_adr_RNO_5 "wb_adr_RNO[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !B+C A)"))
+          )
+          (instance (rename wb_adr_RNO_4 "wb_adr_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !B+C A)"))
+          )
+          (instance LEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C (!B+A))"))
+          )
+          (instance (rename RWMask_RNO_7 "RWMask_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C (!B+A))"))
+          )
+          (instance nRAS_s_i_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A)+C (B A))"))
+          )
+          (instance wb_we_7_iv_0_0_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_i_a3_4 "RDout_i_i_a3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_7 "RDout_i_0_i_a3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_6 "RDout_i_0_i_a3[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_5 "RDout_i_0_i_a3[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_2 "RDout_i_0_i_a3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_1 "RDout_i_0_i_a3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_0 "RDout_i_0_i_a3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename CmdTout_3_0_a3_0_a3_0 "CmdTout_3_0_a3_0_a3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance wb_rst8_0_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance wb_we_7_iv_0_0_0_a3_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance (rename S_r_i_0_o2_1 "S_r_i_0_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance SUM0_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance (rename S_r_i_0_o2_2 "S_r_i_0_o2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+A)"))
+          )
+          (instance (rename S_r_i_0_o2_0_1 "S_r_i_0_o2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance (rename wb_dati_7_0_0_o2_0_7 "wb_dati_7_0_0_o2_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+!A)"))
+          )
+          (instance (rename wb_dati_7_0_0_0_o2_7 "wb_dati_7_0_0_0_o2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+A)"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_13_7 "wb_dati_7_0_0_a3_13[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance un2_S_2_i_0_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance CKE_7_m1_0_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance (rename RC_3_0_0_a3_1_1 "RC_3_0_0_a3_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_4_1_0_7 "wb_dati_7_0_0_a3_4_1_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+!A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_2_3 "wb_dati_7_0_0_a3_2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B A))"))
+          )
+          (instance (rename wb_dati_7_0_0_o3_0_2 "wb_dati_7_0_0_o3_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D B+D (!C B+C (B+A)))"))
+          )
+          (instance CKE_7_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+!A)+C !A)"))
+          )
+          (instance nRWE_s_i_0_63_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (!C+(B !A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNI62C53_1 "S_r_i_0_o2_RNI62C53[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_3_1_0 "wb_adr_7_i_i_3_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C A)+D (!C (!B !A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_3_0 "wb_adr_7_i_i_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B !A+B A)))"))
+          )
+          (instance (rename RA_35_0_0_1_0 "RA_35_0_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B+!A)+D (!C (!B+!A)))"))
+          )
+          (instance (rename RA_35_0_0_0 "RA_35_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D+(!C B+C (B+A)))"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_a3_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance wb_we_7_iv_0_0_0_a3_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance CmdExecMXO2_3_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance CmdBitbangMXO2_3_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B !A)))"))
+          )
+          (instance SUM0_i_m3_0_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+A))"))
+          )
+          (instance CmdBitbangMXO2_3_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance CmdLEDSet_3_0_a8_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B A)))"))
+          )
+          (instance CmdRWMaskSet_3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A)))"))
+          )
+          (instance CmdLEDGet_3_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A))"))
+          )
+          (instance nRAS_s_i_0_a3_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B !A)))"))
+          )
+          (instance nRAS_s_i_0_a3_0_RNIIR094 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B !A)+D (!C (!B !A)))"))
+          )
+          (instance (rename un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0 "un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)))"))
+          )
+          (instance SUM2_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(!B+!A))"))
+          )
+          (instance (rename RA_35_0_0_a3_4_7 "RA_35_0_0_a3_4[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_7_3 "wb_dati_7_0_0_a3_7[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_12_7 "wb_dati_7_0_0_a3_12[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_14_7 "wb_dati_7_0_0_a3_14[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_10_7 "wb_dati_7_0_0_a3_10[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A)))"))
+          )
+          (instance ufmefb (viewRef netlist (cellRef REFB))
+          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename S_0 "S[0]") (joined
+           (portRef (member s 3))
+           (portRef B (instanceRef un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0))
+           (portRef A (instanceRef S_r_i_0_o2_2))
+           (portRef A (instanceRef S_r_i_0_o2_1))
+           (portRef B (instanceRef wb_reqc_1_0))
+           (portRef A (instanceRef Vout3_0_a3_0_a3_0_a3))
+           (portRef A (instanceRef un9_VOEEN_0_a2_0_a3_0_a3))
+           (portRef B (instanceRef RA_35_2_30_a3_2))
+           (portRef B (instanceRef nRAS_s_i_0_a3_6))
+           (portRef C (instanceRef DQMH_4_iv_0_0_i_i_a3_0_a3))
+           (portRef B (instanceRef CKE_7s2_0_0_0))
+           (portRef B (instanceRef RA_35_2_0_a3_3_10))
+           (portRef A (instanceRef RA_35_0_0_o2_11))
+           (portRef A (instanceRef RA_35_0_0_o2_5))
+           (portRef C (instanceRef N_507_i))
+           (portRef A (instanceRef RA_35_0_0_o2_0_5))
+           (portRef A (instanceRef un1_CKE75_0_i_0))
+           (portRef D (instanceRef BA_4_0))
+           (portRef D (instanceRef BA_4_1))
+           (portRef D (instanceRef nCAS_s_i_0_a3))
+           (portRef B (instanceRef CKE_7_RNIS77M1))
+           (portRef B (instanceRef wb_req_RNO_0))
+           (portRef C (instanceRef RA_35_2_0_RNO_10))
+           (portRef B (instanceRef N_201_i))
+           (portRef B (instanceRef N_225_i))
+           (portRef D (instanceRef nRAS_s_i_0_a3_5_RNIH7J73_0))
+           (portRef B (instanceRef CKE_7_m1_0_0_o2_RNICM8E1))
+           (portRef C (instanceRef nRAS_s_i_0_a3_5_RNIH7J73))
+           (portRef D (instanceRef N_314_i_i_o3))
+           (portRef B (instanceRef CKE_7_m1_0_0_o2_RNIGC501))
+           (portRef A (instanceRef CKE_7_m1_0_0_o2_RNI7FOA1))
+           (portRef A (instanceRef S_s_0_0_RNO_0))
+           (portRef D (instanceRef RA_35_2_0_a3_5_10))
+           (portRef A (instanceRef nRAS_s_i_0_a3_4))
+           (portRef A (instanceRef wb_rst16_i_i_i_o3))
+          ))
+          (net (rename SZ0Z_1 "S[1]") (joined
+           (portRef (member s 2))
+           (portRef C (instanceRef un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0))
+           (portRef A (instanceRef un2_S_2_i_0_0_o3))
+           (portRef B (instanceRef S_r_i_0_o2_2))
+           (portRef B (instanceRef S_r_i_0_o2_1))
+           (portRef C (instanceRef wb_reqc_1_0))
+           (portRef B (instanceRef Vout3_0_a3_0_a3_0_a3))
+           (portRef B (instanceRef un9_VOEEN_0_a2_0_a3_0_a3))
+           (portRef A (instanceRef CKE_7s2_0_0_a2_1))
+           (portRef C (instanceRef nRAS_s_i_0_a3_6))
+           (portRef D (instanceRef nRAS_s_i_0_o2_0))
+           (portRef C (instanceRef RA_35_2_0_a3_3_10))
+           (portRef B (instanceRef RA_35_0_0_o2_11))
+           (portRef B (instanceRef RA_35_0_0_o2_5))
+           (portRef B (instanceRef RA_35_0_0_o2_0_5))
+           (portRef D (instanceRef S_s_0_0_0))
+           (portRef B (instanceRef un1_CKE75_0_i_0))
+           (portRef C (instanceRef CKE_7s2_0_0_o3))
+           (portRef B (instanceRef CKE_7_am))
+           (portRef C (instanceRef CKE_7_RNIS77M1))
+           (portRef C (instanceRef wb_req_RNO_0))
+           (portRef D (instanceRef N_201_i))
+           (portRef D (instanceRef N_225_i))
+           (portRef C (instanceRef nRAS_s_i_0_a3_5_RNIH7J73_0))
+           (portRef C (instanceRef CKE_7_m1_0_0_o2_RNICM8E1))
+           (portRef B (instanceRef nRAS_s_i_0_a3_5_RNIH7J73))
+           (portRef C (instanceRef N_314_i_i_o3))
+           (portRef B (instanceRef CKE_7_m1_0_0_o2_RNI7FOA1))
+           (portRef B (instanceRef S_s_0_0_RNO_0))
+           (portRef C (instanceRef RA_35_2_0_a3_5_10))
+           (portRef A (instanceRef un1_RC12_i_0_o3))
+           (portRef B (instanceRef wb_rst16_i_i_i_o3))
+          ))
+          (net (rename S_3 "S[3]") (joined
+           (portRef (member s 0))
+           (portRef C (instanceRef S_r_i_0_o2_RNI62C53_1))
+           (portRef B (instanceRef CKE_7_m1_0_0_o2))
+           (portRef B (instanceRef S_r_i_0_o2_0_1))
+           (portRef B (instanceRef RWMask_RNO_7))
+           (portRef B (instanceRef LEDEN_RNO))
+           (portRef D (instanceRef wb_reqc_1_0))
+           (portRef D (instanceRef Vout3_0_a3_0_a3_0_a3))
+           (portRef D (instanceRef un9_VOEEN_0_a2_0_a3_0_a3))
+           (portRef D (instanceRef RA_35_2_30_a3_2))
+           (portRef C (instanceRef CKE_7s2_0_0_a2_1))
+           (portRef A (instanceRef nRAS_s_i_0_o2))
+           (portRef B (instanceRef nRAS_s_i_0_a3_5))
+           (portRef D (instanceRef DQMH_4_iv_0_0_i_i_a3_0_a3))
+           (portRef B (instanceRef RWMask_RNO_6))
+           (portRef B (instanceRef RWMask_RNO_5))
+           (portRef B (instanceRef RWMask_RNO_4))
+           (portRef B (instanceRef RWMask_RNO_3))
+           (portRef B (instanceRef RWMask_RNO_2))
+           (portRef B (instanceRef RWMask_RNO_1))
+           (portRef B (instanceRef RWMask_RNO_0))
+           (portRef C (instanceRef CKE_7s2_0_0_0))
+           (portRef D (instanceRef RA_35_0_0_o2_11))
+           (portRef D (instanceRef RA_35_0_0_o2_5))
+           (portRef C (instanceRef RA_35_2_0_a3_0_10))
+           (portRef D (instanceRef N_507_i))
+           (portRef D (instanceRef RA_35_0_0_o2_0_5))
+           (portRef D (instanceRef un1_CKE75_0_i_0))
+           (portRef D (instanceRef S_r_i_0_o2_RNIFNP81_2))
+           (portRef B (instanceRef wb_cyc_stb_RNO))
+           (portRef A (instanceRef S_r_i_0_o2_RNIBAU51_1))
+           (portRef A (instanceRef S_r_i_0_o2_RNIFNP81_0_2))
+           (portRef B (instanceRef S_r_i_0_o2_RNIOGTF1_1))
+           (portRef A (instanceRef N_201_i))
+           (portRef A (instanceRef N_225_i))
+           (portRef B (instanceRef S_r_i_0_o2_RNIP4KI1_1))
+           (portRef A (instanceRef N_314_i_i_o3))
+           (portRef A (instanceRef RA_35_2_0_a3_5_10))
+           (portRef B (instanceRef un1_RC12_i_0_o3))
+           (portRef B (instanceRef nRAS_s_i_0_a3_4))
+           (portRef C (instanceRef wb_rst16_i_i_i_o3))
+          ))
+          (net (rename S_2 "S[2]") (joined
+           (portRef (member s 1))
+           (portRef A (instanceRef CKE_7_m1_0_0_o2))
+           (portRef B (instanceRef un2_S_2_i_0_0_o3))
+           (portRef A (instanceRef S_r_i_0_o2_0_1))
+           (portRef B (instanceRef wb_we_7_iv_0_0_0_a3_6))
+           (portRef B (instanceRef wb_we_7_iv_0_0_0_a3_1))
+           (portRef C (instanceRef wb_adr_RNO_4))
+           (portRef C (instanceRef wb_adr_RNO_5))
+           (portRef C (instanceRef wb_adr_RNO_6))
+           (portRef C (instanceRef Vout3_0_a3_0_a3_0_a3))
+           (portRef C (instanceRef un9_VOEEN_0_a2_0_a3_0_a3))
+           (portRef C (instanceRef RA_35_2_30_a3_2))
+           (portRef B (instanceRef CKE_7s2_0_0_a2_1))
+           (portRef A (instanceRef nRAS_s_i_0_a3_5))
+           (portRef B (instanceRef wb_adr_RNO_7))
+           (portRef B (instanceRef wb_adr_RNO_3))
+           (portRef B (instanceRef wb_adr_RNO_2))
+           (portRef B (instanceRef nRAS_s_i_0_a3_1))
+           (portRef C (instanceRef RA_35_0_0_o2_11))
+           (portRef C (instanceRef RA_35_0_0_o2_5))
+           (portRef B (instanceRef RA_35_2_0_a3_0_10))
+           (portRef C (instanceRef RA_35_0_0_o2_0_5))
+           (portRef D (instanceRef nRAS_s_i_0_a3_0))
+           (portRef C (instanceRef un1_CKE75_0_i_0))
+           (portRef D (instanceRef RA_35_2_0_a3_10))
+           (portRef C (instanceRef S_r_i_0_o2_RNIFNP81_2))
+           (portRef B (instanceRef wb_dati_7_0_0_0_0_7))
+           (portRef B (instanceRef wb_dati_7_0_0_0_1))
+           (portRef C (instanceRef wb_adr_RNO_1))
+           (portRef C (instanceRef wb_dati_7_0_0_0_4))
+           (portRef B (instanceRef wb_dati_7_0_0_0_6))
+           (portRef B (instanceRef wb_dati_7_0_0_0_0_3))
+           (portRef B (instanceRef wb_dati_7_0_0_0_0))
+           (portRef B (instanceRef wb_dati_7_0_0_2))
+           (portRef B (instanceRef wb_dati_7_0_0_5))
+           (portRef CD (instanceRef wb_req))
+           (portRef B (instanceRef S_r_i_0_o2_RNIBAU51_1))
+           (portRef D (instanceRef S_r_i_0_o2_RNIFNP81_0_2))
+           (portRef C (instanceRef S_r_i_0_o2_RNIOGTF1_1))
+           (portRef C (instanceRef N_201_i))
+           (portRef C (instanceRef N_225_i))
+           (portRef C (instanceRef S_r_i_0_o2_RNIP4KI1_1))
+           (portRef B (instanceRef N_314_i_i_o3))
+           (portRef B (instanceRef RA_35_2_0_a3_5_10))
+           (portRef C (instanceRef un1_RC12_i_0_o3))
+           (portRef C (instanceRef nRAS_s_i_0_a3_4))
+           (portRef D (instanceRef wb_rst16_i_i_i_o3))
+          ))
+          (net wb_rst16_i (joined
+           (portRef Z (instanceRef wb_rst16_i_i_i_o3))
+           (portRef C (instanceRef N_285_i))
+           (portRef C (instanceRef nCAS_s_i_0_a3_0))
+           (portRef CD (instanceRef wb_rst))
+          ))
+          (net N_876 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_15_7))
+           (portRef C (instanceRef wb_dati_7_0_0_RNO_0_7))
+           (portRef B (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0))
+           (portRef A (instanceRef wb_dati_7_0_0_0_RNO_7))
+          ))
+          (net N_807 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_12_7))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_2_3))
+           (portRef C (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_0))
+           (portRef B (instanceRef wb_dati_7_0_0_0_RNO_7))
+          ))
+          (net (rename FS_13 "FS[13]") (joined
+           (portRef (member fs 2))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_10_7))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_7_3))
+           (portRef B (instanceRef wb_dati_7_0_0_0_o2_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_a3_0_0))
+           (portRef D (instanceRef Ready3_0_a3_5))
+           (portRef C (instanceRef wb_adr_RNO_4_1))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_0_0_1))
+           (portRef B (instanceRef wb_dati_7_0_0_0_o2_3))
+           (portRef D (instanceRef wb_adr_7_i_i_o2_1_0))
+           (portRef C (instanceRef wb_req_RNO))
+           (portRef A (instanceRef wb_we_RNO))
+           (portRef A (instanceRef RA_35_0_0_0_6))
+           (portRef B (instanceRef wb_dati_7_0_0_0_a3_7))
+           (portRef B (instanceRef wb_adr_7_i_i_5_0))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_13_RNI81UL_7))
+           (portRef C (instanceRef wb_dati_7_0_0_0_0_RNO_7))
+           (portRef C (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0))
+           (portRef C (instanceRef wb_dati_7_0_0_0_RNO_7))
+          ))
+          (net (rename FS_12 "FS[12]") (joined
+           (portRef (member fs 3))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_10_7))
+           (portRef D (instanceRef wb_adr_7_i_i_3_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_2_3))
+           (portRef A (instanceRef wb_dati_7_0_0_0_o2_7))
+           (portRef C (instanceRef wb_dati_7_0_0_0_a3_0_0))
+           (portRef C (instanceRef Ready3_0_a3_5))
+           (portRef B (instanceRef wb_adr_RNO_4_1))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_1_0_6))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_0_0_1))
+           (portRef B (instanceRef wb_adr_RNO_0_1))
+           (portRef C (instanceRef RA_35_0_0_0_5))
+           (portRef B (instanceRef wb_req_RNO))
+           (portRef D (instanceRef wb_we_RNO_1))
+           (portRef A (instanceRef wb_dati_7_0_0_0_a3_0_3))
+           (portRef A (instanceRef wb_we_RNO_2))
+           (portRef C (instanceRef wb_adr_7_i_i_a3_4_0))
+           (portRef A (instanceRef wb_adr_7_i_i_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_4))
+           (portRef A (instanceRef wb_dati_7_0_0_0_a3_7))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_13_RNI81UL_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_0_RNO_7))
+           (portRef D (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0))
+           (portRef D (instanceRef wb_dati_7_0_0_0_RNO_7))
+          ))
+          (net N_604 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_RNO_7))
+           (portRef B (instanceRef wb_dati_7_0_0_0_7))
+          ))
+          (net N_784 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_4))
+           (portRef B (instanceRef RA_35_0_0_a3_4_7))
+           (portRef D (instanceRef RA_35_0_0_0_5))
+           (portRef B (instanceRef RA_35_0_0_0_9))
+           (portRef C (instanceRef nRAS_s_i_0_0))
+           (portRef C (instanceRef RA_35_0_0_RNO_0))
+          ))
+          (net N_560 (joined
+           (portRef Z (instanceRef un1_RC12_i_0_o3))
+           (portRef B (instanceRef BA_4_0))
+           (portRef B (instanceRef BA_4_1))
+          ))
+          (net (rename FS_11 "FS[11]") (joined
+           (portRef (member fs 4))
+           (portRef B (instanceRef wb_we_7_iv_0_0_0_a3_7))
+           (portRef C (instanceRef wb_adr_7_i_i_3_1_0))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_4_1_0_7))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_13_7))
+           (portRef B (instanceRef wb_dati_7_0_0_0_a3_0_0))
+           (portRef C (instanceRef wb_adr_7_i_i_a3_2_0_0))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_15_7))
+           (portRef C (instanceRef wb_adr_RNO_3_1))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_1_0_6))
+           (portRef A (instanceRef wb_adr_RNO_0_1))
+           (portRef C (instanceRef wb_adr_7_i_i_o2_1_0))
+           (portRef A (instanceRef wb_we_RNO_3))
+           (portRef A (instanceRef wb_req_RNO))
+           (portRef D (instanceRef wb_dati_7_0_0_o2_0_3))
+           (portRef D (instanceRef wb_dati_7_0_0_o2_4))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_2_4))
+           (portRef A (instanceRef RA_35_0_0_4))
+           (portRef B (instanceRef wb_adr_7_i_i_a3_6_0))
+           (portRef A (instanceRef wb_adr_7_i_i_5_0))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_8_3))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_3_4))
+          ))
+          (net (rename FS_10 "FS[10]") (joined
+           (portRef (member fs 5))
+           (portRef A (instanceRef wb_we_7_iv_0_0_0_a3_7))
+           (portRef B (instanceRef wb_adr_7_i_i_3_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_4_1_0_7))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_13_7))
+           (portRef A (instanceRef wb_dati_7_0_0_0_a3_0_0))
+           (portRef B (instanceRef wb_adr_7_i_i_a3_2_0_0))
+           (portRef A (instanceRef wb_adr_RNO_4_1))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_15_7))
+           (portRef C (instanceRef wb_adr_RNO_2_1))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_1_0_6))
+           (portRef C (instanceRef wb_we_RNO_1))
+           (portRef C (instanceRef wb_dati_7_0_0_o2_0_3))
+           (portRef C (instanceRef wb_dati_7_0_0_o2_4))
+           (portRef B (instanceRef wb_adr_7_i_i_a3_4_0))
+           (portRef A (instanceRef RA_35_0_0_3))
+           (portRef A (instanceRef wb_adr_7_i_i_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_8_3))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_3_4))
+          ))
+          (net (rename FS_9 "FS[9]") (joined
+           (portRef (member fs 6))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_14_7))
+           (portRef C (instanceRef wb_we_7_iv_0_0_0_a3_7))
+           (portRef B (instanceRef wb_adr_7_i_i_3_0))
+           (portRef B (instanceRef wb_dati_7_0_0_o2_0_7))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_15_7))
+           (portRef B (instanceRef wb_adr_RNO_2_1))
+           (portRef B (instanceRef wb_adr_RNO_3_1))
+           (portRef A (instanceRef wb_dati_7_0_0_0_o2_3))
+           (portRef B (instanceRef wb_adr_7_i_i_o2_1_0))
+           (portRef B (instanceRef wb_we_RNO_1))
+           (portRef B (instanceRef wb_dati_7_0_0_o2_0_3))
+           (portRef B (instanceRef wb_dati_7_0_0_o2_4))
+           (portRef C (instanceRef RA_35_0_0_a3_2))
+           (portRef A (instanceRef wb_adr_7_i_i_a3_4_0))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_2_4))
+           (portRef A (instanceRef wb_adr_7_i_i_a3_6_0))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_8_3))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_3_4))
+          ))
+          (net (rename FS_8 "FS[8]") (joined
+           (portRef (member fs 7))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_14_7))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_12_7))
+           (portRef D (instanceRef wb_we_7_iv_0_0_0_a3_7))
+           (portRef A (instanceRef wb_adr_7_i_i_3_0))
+           (portRef A (instanceRef wb_adr_7_i_i_3_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_o2_0_7))
+           (portRef A (instanceRef wb_adr_7_i_i_a3_2_0_0))
+           (portRef A (instanceRef wb_adr_RNO_2_1))
+           (portRef A (instanceRef wb_adr_RNO_3_1))
+           (portRef A (instanceRef wb_adr_7_i_i_o2_1_0))
+           (portRef A (instanceRef wb_we_RNO_1))
+           (portRef A (instanceRef wb_dati_7_0_0_o2_0_3))
+           (portRef A (instanceRef wb_dati_7_0_0_o2_4))
+           (portRef C (instanceRef RA_35_i_i_0_a3_1))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_2_4))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_8_3))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_3_4))
+          ))
+          (net N_873 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_3_4))
+           (portRef D (instanceRef wb_dati_7_0_0_o3_0_2))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_0_0_1))
+           (portRef B (instanceRef wb_dati_7_0_0_0_4))
+          ))
+          (net N_845 (joined
+           (portRef Z (instanceRef RA_35_2_0_a3_5_10))
+           (portRef B (instanceRef RA_35_2_0_0_10))
+           (portRef C (instanceRef RA_35_0_0_0_9))
+           (portRef B (instanceRef RA_35_0_0_11))
+          ))
+          (net wb_ack (joined
+           (portRef wb_ack (instanceRef ufmefb))
+           (portRef B (instanceRef un1_RWMask_0_sqmuxa_1_i_0_a3_0_0_0))
+           (portRef D (instanceRef wb_cyc_stb_RNO_0))
+           (portRef D (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0_0))
+           (portRef D (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0))
+           (portRef A (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0))
+          ))
+          (net (rename un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1_0 "un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0]") (joined
+           (portRef Z (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0))
+           (portRef D (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_0))
+          ))
+          (net N_206 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_o2_0_7))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_1_0_6))
+           (portRef A (instanceRef wb_dati_7_0_0_RNO_0_7))
+           (portRef A (instanceRef wb_dati_7_0_0_0_0_RNO_7))
+          ))
+          (net N_811 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_13_7))
+           (portRef C (instanceRef wb_dati_7_0_0_0_o2_3))
+           (portRef C (instanceRef wb_dati_7_0_0_0_a3_7))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_13_RNI81UL_7))
+           (portRef B (instanceRef wb_dati_7_0_0_0_0_RNO_7))
+          ))
+          (net (rename wb_dati_7_0_0_a3_8_0_7 "wb_dati_7_0_0_a3_8_0[7]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_0_RNO_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_0_7))
+          ))
+          (net N_551 (joined
+           (portRef Z (instanceRef CKE_7_m1_0_0_o2))
+           (portRef D (instanceRef un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0))
+           (portRef A (instanceRef CKE_7s2_0_0_o3))
+           (portRef D (instanceRef CKE_7_RNIS77M1))
+           (portRef D (instanceRef wb_req_RNO_0))
+           (portRef D (instanceRef RA_35_2_0_RNO_10))
+           (portRef D (instanceRef CKE_7_m1_0_0_o2_RNICM8E1))
+           (portRef C (instanceRef CKE_7_m1_0_0_o2_RNIGC501))
+           (portRef C (instanceRef CKE_7_m1_0_0_o2_RNI7FOA1))
+           (portRef C (instanceRef S_s_0_0_RNO_0))
+           (portRef N_551)
+          ))
+          (net N_643 (joined
+           (portRef Z (instanceRef S_s_0_0_RNO_0))
+           (portRef C (instanceRef S_s_0_0_0))
+          ))
+          (net RC12 (joined
+           (portRef Z (instanceRef CKE_7_m1_0_0_o2_RNI7FOA1))
+           (portRef RC12)
+          ))
+          (net (rename FS_4 "FS[4]") (joined
+           (portRef (member fs 11))
+           (portRef C (instanceRef RA_35_0_0_a3_4_7))
+           (portRef D (instanceRef nRWE_s_i_0_63_1))
+           (portRef B (instanceRef Ready3_0_a3_4))
+           (portRef D (instanceRef nCAS_s_i_0_m2))
+           (portRef B (instanceRef nRAS_s_i_0_o2_0))
+           (portRef A (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0))
+           (portRef B (instanceRef RA_35_0_0_0_5))
+           (portRef A (instanceRef RA_35_0_0_0_9))
+           (portRef A (instanceRef BA_4_0))
+           (portRef A (instanceRef BA_4_1))
+           (portRef A (instanceRef RA_35_2_0_RNO_10))
+           (portRef D (instanceRef RA_35_0_0_RNO_0))
+           (portRef A (instanceRef CKE_7_m1_0_0_o2_RNICM8E1))
+           (portRef A (instanceRef CKE_7_m1_0_0_o2_RNIGC501))
+          ))
+          (net N_792 (joined
+           (portRef Z (instanceRef CKE_7_m1_0_0_o2_RNIGC501))
+           (portRef D (instanceRef RA_35_0_0_a3_2))
+           (portRef D (instanceRef RA_35_i_i_0_a3_1))
+          ))
+          (net (rename RC_1 "RC[1]") (joined
+           (portRef (member rc 1))
+           (portRef A (instanceRef nRAS_s_i_0_a3_8))
+           (portRef C (instanceRef CKE_7_bm))
+           (portRef B (instanceRef RC_3_0_0_2))
+           (portRef B (instanceRef N_360_i))
+           (portRef A (instanceRef RC_3_0_0_1))
+          ))
+          (net CO0_1 (joined
+           (portRef CO0_1)
+           (portRef D (instanceRef nRAS_s_i_0_a3_8))
+           (portRef A (instanceRef RC_3_0_0_a3_1_1))
+           (portRef A (instanceRef RC_3_0_0_2))
+           (portRef A (instanceRef N_360_i))
+           (portRef B (instanceRef RC_3_0_0_1))
+          ))
+          (net (rename RC_2 "RC[2]") (joined
+           (portRef (member rc 0))
+           (portRef C (instanceRef nRAS_s_i_0_a3_8))
+           (portRef B (instanceRef RC_3_0_0_a3_1_1))
+           (portRef C (instanceRef RC_3_0_0_2))
+           (portRef C (instanceRef N_360_i))
+           (portRef C (instanceRef RC_3_0_0_1))
+          ))
+          (net (rename RC_3_1 "RC_3[1]") (joined
+           (portRef Z (instanceRef RC_3_0_0_1))
+           (portRef (member rc_3 1))
+          ))
+          (net N_185 (joined
+           (portRef Z (instanceRef N_314_i_i_o3))
+           (portRef C (instanceRef SUM2_0_o2))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2))
+           (portRef B (instanceRef N_187_i))
+           (portRef D (instanceRef wb_we_RNO_0))
+           (portRef D (instanceRef CmdBitbangMXO2_RNINSM62))
+          ))
+          (net N_804 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_5))
+           (portRef D (instanceRef nRAS_s_i_0_a3_0_RNIIR094))
+           (portRef A (instanceRef RA_35_2_0_a3_3_10))
+           (portRef B (instanceRef CKE_7s2_0_0_o3))
+           (portRef A (instanceRef CKE_7_am))
+           (portRef A (instanceRef nRAS_s_i_0_a3_5_RNIH7J73_0))
+           (portRef A (instanceRef nRAS_s_i_0_a3_5_RNIH7J73))
+          ))
+          (net N_285_i (joined
+           (portRef Z (instanceRef N_285_i))
+           (portRef A (instanceRef S_r_i_0_o2_RNI62C53_1))
+           (portRef A (instanceRef nRAS_s_i_0_a3_6))
+           (portRef A (instanceRef nRAS_s_i_0_a3_0))
+           (portRef A (instanceRef nCAS_s_i_0_a3_0))
+           (portRef A (instanceRef nCAS_s_i_0_a3))
+           (portRef A (instanceRef nRAS_s_i_0_0))
+           (portRef B (instanceRef nRAS_s_i_0_a3_5_RNIH7J73_0))
+           (portRef D (instanceRef nRAS_s_i_0_a3_5_RNIH7J73))
+          ))
+          (net N_872 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_5_RNIH7J73))
+           (portRef C (instanceRef nCAS_s_i_0_a3_RNIO1UQ3))
+          ))
+          (net N_849 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_8_3))
+           (portRef C (instanceRef wb_dati_7_0_0_0_3))
+           (portRef C (instanceRef wb_dati_7_0_0_1))
+           (portRef C (instanceRef wb_dati_7_0_0_6))
+          ))
+          (net BA_0_sqmuxa (joined
+           (portRef Z (instanceRef CKE_7_m1_0_0_o2_RNICM8E1))
+           (portRef BA_0_sqmuxa)
+          ))
+          (net (rename RWBank_1 "RWBank[1]") (joined
+           (portRef (member rwbank 6))
+           (portRef A (instanceRef S_r_i_0_o2_RNIP4KI1_1))
+          ))
+          (net (rename S_r_i_0_o2_1 "S_r_i_0_o2[1]") (joined
+           (portRef Z (instanceRef S_r_i_0_o2_1))
+           (portRef B (instanceRef S_r_i_0_o2_RNI62C53_1))
+           (portRef A (instanceRef RA_35_2_0_a3_0_10))
+           (portRef C (instanceRef nRAS_s_i_0_a3_0))
+           (portRef B (instanceRef RA_35_2_0_a3_10))
+           (portRef D (instanceRef S_r_i_0_o2_0_RNI36E21_1))
+           (portRef C (instanceRef S_r_i_0_o2_RNIBAU51_1))
+           (portRef D (instanceRef S_r_i_0_o2_RNIOGTF1_1))
+           (portRef D (instanceRef S_r_i_0_o2_RNIP4KI1_1))
+          ))
+          (net N_699 (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIP4KI1_1))
+           (portRef C (instanceRef un2_S_2_i_0_0_o3_RNIHFHN3))
+          ))
+          (net N_617 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_5_RNIH7J73_0))
+           (portRef C (instanceRef nRAS_s_i_0_0_RNI0PC64))
+          ))
+          (net (rename N_225_i_1z "N_225_i") (joined
+           (portRef Z (instanceRef N_225_i))
+           (portRef N_225_i_1z)
+          ))
+          (net (rename N_201_i_1z "N_201_i") (joined
+           (portRef Z (instanceRef N_201_i))
+           (portRef N_201_i_1z)
+          ))
+          (net RWSel (joined
+           (portRef RWSel)
+           (portRef B (instanceRef SUM2_0_o2))
+           (portRef B (instanceRef CmdTout_3_0_a3_0_a3_0))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_0_1))
+           (portRef C (instanceRef N_368_i))
+           (portRef D (instanceRef N_369_i))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S))
+           (portRef C0 (instanceRef un1_CS_0_sqmuxa_0_0_0))
+           (portRef A (instanceRef N_187_i))
+           (portRef C (instanceRef wb_we_RNO_0))
+           (portRef C (instanceRef CmdBitbangMXO2_RNINSM62))
+           (portRef A (instanceRef S_r_i_0_o2_RNIOGTF1_1))
+          ))
+          (net N_187 (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIOGTF1_1))
+           (portRef A (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0))
+           (portRef B (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_0))
+           (portRef B (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5))
+           (portRef B (instanceRef S_r_i_0_o2_RNI3VQTC_1))
+          ))
+          (net (rename FS_3 "FS[3]") (joined
+           (portRef (member fs 12))
+           (portRef A (instanceRef RA_35_0_0_a3_4_7))
+           (portRef C (instanceRef nRWE_s_i_0_63_1))
+           (portRef C (instanceRef nRAS_s_i_0_m3))
+           (portRef B (instanceRef Ready3_0_a3_5))
+           (portRef C (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0))
+           (portRef C (instanceRef nCAS_s_i_0_m2))
+           (portRef A (instanceRef nRAS_s_i_0_o2_0))
+           (portRef A (instanceRef RA_35_0_0_0_5))
+           (portRef A (instanceRef RA_35_0_0_a3_2))
+           (portRef A (instanceRef RA_35_i_i_0_a3_1))
+           (portRef A (instanceRef RA_35_0_0_RNO_0))
+          ))
+          (net (rename FS_1 "FS[1]") (joined
+           (portRef (member fs 14))
+           (portRef A (instanceRef nRWE_s_i_0_63_1))
+           (portRef A (instanceRef nRAS_s_i_0_m3))
+           (portRef A (instanceRef Ready3_0_a3_5))
+           (portRef A (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0))
+           (portRef A (instanceRef nCAS_s_i_0_m2))
+           (portRef B (instanceRef RA_35_2_0_RNO_10))
+           (portRef B (instanceRef RA_35_0_0_RNO_0))
+          ))
+          (net N_684 (joined
+           (portRef Z (instanceRef RA_35_0_0_RNO_0))
+           (portRef B (instanceRef RA_35_0_0_0))
+          ))
+          (net N_627 (joined
+           (portRef Z (instanceRef RA_35_2_0_RNO_10))
+           (portRef B (instanceRef RA_35_2_0_10))
+          ))
+          (net N_194 (joined
+           (portRef Z (instanceRef S_r_i_0_o2_2))
+           (portRef A (instanceRef RA_35_2_0_a3_10))
+           (portRef B (instanceRef S_r_i_0_o2_0_RNI36E21_1))
+           (portRef B (instanceRef S_r_i_0_o2_RNIFNP81_2))
+           (portRef B (instanceRef S_r_i_0_o2_RNIFNP81_0_2))
+          ))
+          (net S_1 (joined
+           (portRef S_1)
+           (portRef A (instanceRef S_s_0_0_0))
+           (portRef A (instanceRef S_r_i_0_o2_0_RNI36E21_1))
+           (portRef A (instanceRef S_r_i_0_o2_RNIFNP81_2))
+           (portRef C (instanceRef S_r_i_0_o2_RNIFNP81_0_2))
+          ))
+          (net N_372_i (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIFNP81_0_2))
+           (portRef N_372_i)
+          ))
+          (net (rename FS_15 "FS[15]") (joined
+           (portRef (member fs 0))
+           (portRef A (instanceRef un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0))
+           (portRef B (instanceRef wb_rst8_0_a3_0_a3))
+           (portRef D (instanceRef Ready3_0_a3_4))
+           (portRef A (instanceRef DQMH_4_iv_0_0_i_i_a3_0_a3))
+           (portRef A (instanceRef N_507_i))
+           (portRef B (instanceRef N_285_i))
+           (portRef A (instanceRef wb_req_RNO_0))
+          ))
+          (net wb_adr_0_sqmuxa_1_i (joined
+           (portRef Z (instanceRef wb_req_RNO_0))
+           (portRef SP (instanceRef wb_req))
+          ))
+          (net CmdBitbangMXO2 (joined
+           (portRef Q (instanceRef CmdBitbangMXO2))
+           (portRef A (instanceRef CmdBitbangMXO2_RNINSM62))
+          ))
+          (net N_777 (joined
+           (portRef Z (instanceRef un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_10_7))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_14_7))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_12_7))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_7_3))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_9_7))
+           (portRef B (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0_0))
+           (portRef B (instanceRef wb_we_RNO_0))
+           (portRef B (instanceRef CmdBitbangMXO2_RNINSM62))
+          ))
+          (net CmdBitbangMXO2_RNINSM62 (joined
+           (portRef Z (instanceRef CmdBitbangMXO2_RNINSM62))
+           (portRef SP (instanceRef wb_adr_7))
+           (portRef SP (instanceRef wb_adr_6))
+           (portRef SP (instanceRef wb_adr_5))
+           (portRef SP (instanceRef wb_adr_4))
+           (portRef SP (instanceRef wb_adr_3))
+           (portRef SP (instanceRef wb_adr_2))
+           (portRef SP (instanceRef wb_adr_1))
+           (portRef SP (instanceRef wb_adr_0))
+           (portRef SP (instanceRef wb_dati_7))
+           (portRef SP (instanceRef wb_dati_6))
+           (portRef SP (instanceRef wb_dati_5))
+           (portRef SP (instanceRef wb_dati_4))
+           (portRef SP (instanceRef wb_dati_3))
+           (portRef SP (instanceRef wb_dati_2))
+           (portRef SP (instanceRef wb_dati_1))
+           (portRef SP (instanceRef wb_dati_0))
+          ))
+          (net CmdExecMXO2 (joined
+           (portRef Q (instanceRef CmdExecMXO2))
+           (portRef C (instanceRef wb_cyc_stb_RNO))
+           (portRef B (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0))
+           (portRef A (instanceRef wb_we_RNO_0))
+          ))
+          (net wb_we_RNO_0 (joined
+           (portRef Z (instanceRef wb_we_RNO_0))
+           (portRef SP (instanceRef wb_we))
+          ))
+          (net N_856 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_14_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_a3_7))
+           (portRef D (instanceRef wb_adr_7_i_i_5_0))
+           (portRef A (instanceRef wb_dati_7_0_0_0_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_13_RNI81UL_7))
+          ))
+          (net N_757 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_13_RNI81UL_7))
+           (portRef A (instanceRef wb_dati_7_0_0_4))
+           (portRef A (instanceRef wb_dati_7_0_0_6))
+          ))
+          (net CKE_7 (joined
+           (portRef Z (instanceRef CKE_7))
+           (portRef A (instanceRef CKE_7_RNIS77M1))
+          ))
+          (net (rename CKE_7_RNIS77M1_1z "CKE_7_RNIS77M1") (joined
+           (portRef Z (instanceRef CKE_7_RNIS77M1))
+           (portRef CKE_7_RNIS77M1_1z)
+          ))
+          (net N_185_i (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIBAU51_1))
+           (portRef N_185_i)
+          ))
+          (net (rename N_187_i_1z "N_187_i") (joined
+           (portRef Z (instanceRef N_187_i))
+           (portRef SP (instanceRef CmdBitbangMXO2))
+           (portRef SP (instanceRef CmdExecMXO2))
+           (portRef SP (instanceRef CmdSetRWBankFFChip))
+           (portRef N_187_i_1z)
+          ))
+          (net un1_CS_0_sqmuxa_0_0_0_bm (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_0_bm))
+           (portRef ALUT (instanceRef un1_CS_0_sqmuxa_0_0_0))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_0_am (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_0_am))
+           (portRef BLUT (instanceRef un1_CS_0_sqmuxa_0_0_0))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_0 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_0))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2))
+          ))
+          (net N_193 (joined
+           (portRef Z (instanceRef SUM0_i_o2))
+           (portRef D (instanceRef SUM0_i_a3_1))
+           (portRef A (instanceRef S_r_i_0_o2_RNIVM0LF_1))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_0_bm))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_a3_2_2 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_2_2))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_0_bm))
+          ))
+          (net (rename Din_c_6 "Din_c[6]") (joined
+           (portRef (member din_c 1))
+           (portRef A (instanceRef CmdBitbangMXO2_3_0_a3_0))
+           (portRef A (instanceRef RDout_i_0_i_a3_6))
+           (portRef A (instanceRef wb_adr_RNO_6))
+           (portRef C (instanceRef SUM1_0_o3_0))
+           (portRef A (instanceRef RWMask_RNO_6))
+           (portRef C (instanceRef SUM0_i_a3_1))
+           (portRef A (instanceRef RWBank_3_0_6))
+           (portRef C (instanceRef CmdExecMXO2_3_0_a3_0_RNIAJ811))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_0))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_0_bm))
+          ))
+          (net (rename CS_0 "CS[0]") (joined
+           (portRef (member cs 2))
+           (portRef A (instanceRef SUM2_0_o2))
+           (portRef B (instanceRef CmdBitbangMXO2_3_0_a3_0))
+           (portRef A (instanceRef SUM0_i_a3_1))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_0))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S))
+           (portRef A (instanceRef S_r_i_0_o2_RNI3VQTC_1))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_0_bm))
+          ))
+          (net (rename CmdTout_2 "CmdTout[2]") (joined
+           (portRef (member cmdtout 0))
+           (portRef C (instanceRef N_369_i))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_0_am))
+          ))
+          (net (rename CmdTout_1 "CmdTout[1]") (joined
+           (portRef (member cmdtout 1))
+           (portRef B (instanceRef N_368_i))
+           (portRef B (instanceRef N_369_i))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_0_am))
+          ))
+          (net CO0_0 (joined
+           (portRef CO0_0)
+           (portRef A (instanceRef CmdTout_3_0_a3_0_a3_0))
+           (portRef A (instanceRef N_368_i))
+           (portRef A (instanceRef N_369_i))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_0_am))
+          ))
+          (net wb_we_RNO (joined
+           (portRef Z (instanceRef wb_we_RNO))
+           (portRef D (instanceRef wb_we))
+          ))
+          (net C14M_c (joined
+           (portRef C14M_c)
+           (portRef C14M_c (instanceRef ufmefb))
+           (portRef CK (instanceRef CmdBitbangMXO2))
+           (portRef CK (instanceRef CmdExecMXO2))
+           (portRef CK (instanceRef CmdSetRWBankFFChip))
+           (portRef CK (instanceRef LEDEN))
+           (portRef CK (instanceRef RWMask_7))
+           (portRef CK (instanceRef RWMask_6))
+           (portRef CK (instanceRef RWMask_5))
+           (portRef CK (instanceRef RWMask_4))
+           (portRef CK (instanceRef RWMask_3))
+           (portRef CK (instanceRef RWMask_2))
+           (portRef CK (instanceRef RWMask_1))
+           (portRef CK (instanceRef RWMask_0))
+           (portRef CK (instanceRef wb_adr_7))
+           (portRef CK (instanceRef wb_adr_6))
+           (portRef CK (instanceRef wb_adr_5))
+           (portRef CK (instanceRef wb_adr_4))
+           (portRef CK (instanceRef wb_adr_3))
+           (portRef CK (instanceRef wb_adr_2))
+           (portRef CK (instanceRef wb_adr_1))
+           (portRef CK (instanceRef wb_adr_0))
+           (portRef CK (instanceRef wb_cyc_stb))
+           (portRef CK (instanceRef wb_dati_7))
+           (portRef CK (instanceRef wb_dati_6))
+           (portRef CK (instanceRef wb_dati_5))
+           (portRef CK (instanceRef wb_dati_4))
+           (portRef CK (instanceRef wb_dati_3))
+           (portRef CK (instanceRef wb_dati_2))
+           (portRef CK (instanceRef wb_dati_1))
+           (portRef CK (instanceRef wb_dati_0))
+           (portRef CK (instanceRef wb_req))
+           (portRef CK (instanceRef wb_rst))
+           (portRef CK (instanceRef wb_we))
+          ))
+          (net wb_we (joined
+           (portRef Q (instanceRef wb_we))
+           (portRef wb_we (instanceRef ufmefb))
+          ))
+          (net wb_rst8 (joined
+           (portRef Z (instanceRef wb_rst8_0_a3_0_a3))
+           (portRef D (instanceRef wb_rst))
+          ))
+          (net wb_rst (joined
+           (portRef Q (instanceRef wb_rst))
+           (portRef wb_rst (instanceRef ufmefb))
+          ))
+          (net wb_reqc_i (joined
+           (portRef Z (instanceRef wb_req_RNO))
+           (portRef D (instanceRef wb_req))
+          ))
+          (net wb_req (joined
+           (portRef Q (instanceRef wb_req))
+           (portRef C (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0))
+          ))
+          (net (rename wb_dati_7_0 "wb_dati_7[0]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_0))
+           (portRef D (instanceRef wb_dati_0))
+          ))
+          (net (rename wb_dati_0 "wb_dati[0]") (joined
+           (portRef Q (instanceRef wb_dati_0))
+           (portRef (member wb_dati 7) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_1 "wb_dati_7[1]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_1))
+           (portRef D (instanceRef wb_dati_1))
+          ))
+          (net (rename wb_dati_1 "wb_dati[1]") (joined
+           (portRef Q (instanceRef wb_dati_1))
+           (portRef (member wb_dati 6) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_2 "wb_dati_7[2]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_2))
+           (portRef D (instanceRef wb_dati_2))
+          ))
+          (net (rename wb_dati_2 "wb_dati[2]") (joined
+           (portRef Q (instanceRef wb_dati_2))
+           (portRef (member wb_dati 5) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_3 "wb_dati_7[3]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_3))
+           (portRef D (instanceRef wb_dati_3))
+          ))
+          (net (rename wb_dati_3 "wb_dati[3]") (joined
+           (portRef Q (instanceRef wb_dati_3))
+           (portRef (member wb_dati 4) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_4 "wb_dati_7[4]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_4))
+           (portRef D (instanceRef wb_dati_4))
+          ))
+          (net (rename wb_dati_4 "wb_dati[4]") (joined
+           (portRef Q (instanceRef wb_dati_4))
+           (portRef (member wb_dati 3) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_5 "wb_dati_7[5]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_5))
+           (portRef D (instanceRef wb_dati_5))
+          ))
+          (net (rename wb_dati_5 "wb_dati[5]") (joined
+           (portRef Q (instanceRef wb_dati_5))
+           (portRef (member wb_dati 2) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_6 "wb_dati_7[6]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_6))
+           (portRef D (instanceRef wb_dati_6))
+          ))
+          (net (rename wb_dati_6 "wb_dati[6]") (joined
+           (portRef Q (instanceRef wb_dati_6))
+           (portRef (member wb_dati 1) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_7 "wb_dati_7[7]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_7))
+           (portRef D (instanceRef wb_dati_7))
+          ))
+          (net (rename wb_dati_7 "wb_dati[7]") (joined
+           (portRef Q (instanceRef wb_dati_7))
+           (portRef (member wb_dati 0) (instanceRef ufmefb))
+          ))
+          (net wb_cyc_stb_RNO (joined
+           (portRef Z (instanceRef wb_cyc_stb_RNO))
+           (portRef D (instanceRef wb_cyc_stb))
+          ))
+          (net (rename un1_CmdSetRWBankFFChip13_1_i_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0[0]") (joined
+           (portRef Z (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0))
+           (portRef SP (instanceRef wb_cyc_stb))
+          ))
+          (net wb_cyc_stb (joined
+           (portRef Q (instanceRef wb_cyc_stb))
+           (portRef wb_cyc_stb (instanceRef ufmefb))
+          ))
+          (net (rename wb_adr_7_i_i_0 "wb_adr_7_i_i[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_0))
+           (portRef D (instanceRef wb_adr_0))
+          ))
+          (net (rename wb_adr_0 "wb_adr[0]") (joined
+           (portRef Q (instanceRef wb_adr_0))
+           (portRef (member wb_adr 7) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_0_0))
+          ))
+          (net (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (joined
+           (portRef Z (instanceRef wb_adr_RNO_1))
+           (portRef D (instanceRef wb_adr_1))
+          ))
+          (net (rename wb_adr_1 "wb_adr[1]") (joined
+           (portRef Q (instanceRef wb_adr_1))
+           (portRef (member wb_adr 6) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_0_1))
+          ))
+          (net N_80_i (joined
+           (portRef Z (instanceRef wb_adr_RNO_2))
+           (portRef D (instanceRef wb_adr_2))
+          ))
+          (net (rename wb_adr_2 "wb_adr[2]") (joined
+           (portRef Q (instanceRef wb_adr_2))
+           (portRef (member wb_adr 5) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_2))
+          ))
+          (net N_268_i (joined
+           (portRef Z (instanceRef wb_adr_RNO_3))
+           (portRef D (instanceRef wb_adr_3))
+          ))
+          (net (rename wb_adr_3 "wb_adr[3]") (joined
+           (portRef Q (instanceRef wb_adr_3))
+           (portRef (member wb_adr 4) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_0_0_3))
+          ))
+          (net N_294 (joined
+           (portRef Z (instanceRef wb_adr_RNO_4))
+           (portRef D (instanceRef wb_adr_4))
+          ))
+          (net (rename wb_adr_4 "wb_adr[4]") (joined
+           (portRef Q (instanceRef wb_adr_4))
+           (portRef (member wb_adr 3) (instanceRef ufmefb))
+           (portRef D (instanceRef wb_dati_7_0_0_0_4))
+          ))
+          (net N_290 (joined
+           (portRef Z (instanceRef wb_adr_RNO_5))
+           (portRef D (instanceRef wb_adr_5))
+          ))
+          (net (rename wb_adr_5 "wb_adr[5]") (joined
+           (portRef Q (instanceRef wb_adr_5))
+           (portRef (member wb_adr 2) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_5))
+          ))
+          (net N_284 (joined
+           (portRef Z (instanceRef wb_adr_RNO_6))
+           (portRef D (instanceRef wb_adr_6))
+          ))
+          (net (rename wb_adr_6 "wb_adr[6]") (joined
+           (portRef Q (instanceRef wb_adr_6))
+           (portRef (member wb_adr 1) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_0_6))
+          ))
+          (net N_267_i (joined
+           (portRef Z (instanceRef wb_adr_RNO_7))
+           (portRef D (instanceRef wb_adr_7))
+          ))
+          (net (rename wb_adr_7 "wb_adr[7]") (joined
+           (portRef Q (instanceRef wb_adr_7))
+           (portRef (member wb_adr 0) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_0_0_7))
+          ))
+          (net N_309_i (joined
+           (portRef Z (instanceRef RWMask_RNO_0))
+           (portRef D (instanceRef RWMask_0))
+          ))
+          (net (rename un1_RWMask_0_sqmuxa_1_i_0_0_0 "un1_RWMask_0_sqmuxa_1_i_0_0[0]") (joined
+           (portRef Z (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0_0))
+           (portRef SP (instanceRef RWMask_7))
+           (portRef SP (instanceRef RWMask_6))
+           (portRef SP (instanceRef RWMask_5))
+           (portRef SP (instanceRef RWMask_4))
+           (portRef SP (instanceRef RWMask_3))
+           (portRef SP (instanceRef RWMask_2))
+           (portRef SP (instanceRef RWMask_1))
+           (portRef SP (instanceRef RWMask_0))
+          ))
+          (net (rename RWMask_0 "RWMask[0]") (joined
+           (portRef Q (instanceRef RWMask_0))
+           (portRef C (instanceRef RWBank_3_0_0_0))
+          ))
+          (net N_307_i (joined
+           (portRef Z (instanceRef RWMask_RNO_1))
+           (portRef D (instanceRef RWMask_1))
+          ))
+          (net (rename RWMask_1 "RWMask[1]") (joined
+           (portRef Q (instanceRef RWMask_1))
+           (portRef C (instanceRef RWBank_3_0_1))
+          ))
+          (net N_304_i (joined
+           (portRef Z (instanceRef RWMask_RNO_2))
+           (portRef D (instanceRef RWMask_2))
+          ))
+          (net (rename RWMask_2 "RWMask[2]") (joined
+           (portRef Q (instanceRef RWMask_2))
+           (portRef C (instanceRef RWBank_3_0_2))
+          ))
+          (net N_302_i (joined
+           (portRef Z (instanceRef RWMask_RNO_3))
+           (portRef D (instanceRef RWMask_3))
+          ))
+          (net (rename RWMask_3 "RWMask[3]") (joined
+           (portRef Q (instanceRef RWMask_3))
+           (portRef C (instanceRef RWBank_3_0_3))
+          ))
+          (net N_310_i (joined
+           (portRef Z (instanceRef RWMask_RNO_4))
+           (portRef D (instanceRef RWMask_4))
+          ))
+          (net (rename RWMask_4 "RWMask[4]") (joined
+           (portRef Q (instanceRef RWMask_4))
+           (portRef C (instanceRef RWBank_3_0_0_4))
+          ))
+          (net N_301_i (joined
+           (portRef Z (instanceRef RWMask_RNO_5))
+           (portRef D (instanceRef RWMask_5))
+          ))
+          (net (rename RWMask_5 "RWMask[5]") (joined
+           (portRef Q (instanceRef RWMask_5))
+           (portRef C (instanceRef RWBank_3_0_5))
+          ))
+          (net N_300_i (joined
+           (portRef Z (instanceRef RWMask_RNO_6))
+           (portRef D (instanceRef RWMask_6))
+          ))
+          (net (rename RWMask_6 "RWMask[6]") (joined
+           (portRef Q (instanceRef RWMask_6))
+           (portRef C (instanceRef RWBank_3_0_6))
+          ))
+          (net N_296 (joined
+           (portRef Z (instanceRef RWMask_RNO_7))
+           (portRef D (instanceRef RWMask_7))
+          ))
+          (net (rename RWMask_7 "RWMask[7]") (joined
+           (portRef Q (instanceRef RWMask_7))
+           (portRef C (instanceRef RWBank_3_0_7))
+          ))
+          (net N_295 (joined
+           (portRef Z (instanceRef LEDEN_RNO))
+           (portRef D (instanceRef LEDEN))
+          ))
+          (net (rename un1_LEDEN_0_sqmuxa_1_i_0_0_0 "un1_LEDEN_0_sqmuxa_1_i_0_0[0]") (joined
+           (portRef Z (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_0))
+           (portRef SP (instanceRef LEDEN))
+          ))
+          (net LEDEN (joined
+           (portRef Q (instanceRef LEDEN))
+           (portRef D (instanceRef RWBank_3_0_0_o3_0))
+           (portRef A (instanceRef LEDEN_RNI6G6M))
+          ))
+          (net CmdSetRWBankFFChip_3 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3))
+           (portRef D (instanceRef CmdSetRWBankFFChip))
+          ))
+          (net CmdSetRWBankFFChip (joined
+           (portRef Q (instanceRef CmdSetRWBankFFChip))
+           (portRef B (instanceRef RWBank_3_0_0_o3_0))
+          ))
+          (net CmdExecMXO2_3 (joined
+           (portRef Z (instanceRef CmdExecMXO2_3_0_a3))
+           (portRef D (instanceRef CmdExecMXO2))
+          ))
+          (net CmdBitbangMXO2_3 (joined
+           (portRef Z (instanceRef CmdBitbangMXO2_3_0_a3))
+           (portRef D (instanceRef CmdBitbangMXO2))
+          ))
+          (net N_215 (joined
+           (portRef Z (instanceRef SUM2_0_o2))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514))
+           (portRef A (instanceRef CmdExecMXO2_3_0_a3_0_RNI6S1P8))
+           (portRef B (instanceRef S_r_i_0_o2_RNIVM0LF_1))
+          ))
+          (net SUM0_i_4 (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNI3VQTC_1))
+           (portRef C (instanceRef S_r_i_0_o2_RNIVM0LF_1))
+          ))
+          (net N_547_i (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIVM0LF_1))
+           (portRef N_547_i)
+          ))
+          (net N_637 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2))
+          ))
+          (net un1_CS_0_sqmuxa_i (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2))
+           (portRef un1_CS_0_sqmuxa_i)
+          ))
+          (net SUM0_i_1 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95))
+           (portRef C (instanceRef S_r_i_0_o2_RNI3VQTC_1))
+          ))
+          (net SUM0_i_3 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5))
+           (portRef D (instanceRef S_r_i_0_o2_RNI3VQTC_1))
+          ))
+          (net N_793 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_10_7))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_2_4))
+           (portRef C (instanceRef wb_adr_7_i_i_a3_6_0))
+           (portRef B (instanceRef wb_dati_7_0_0_RNO_0_7))
+           (portRef B (instanceRef wb_dati_7_0_0_1))
+           (portRef C (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0_0))
+           (portRef B (instanceRef wb_dati_7_0_0_6))
+           (portRef B (instanceRef wb_adr_7_i_i_0))
+          ))
+          (net (rename wb_adr_7_i_i_4_0 "wb_adr_7_i_i_4[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_4_0))
+           (portRef C (instanceRef wb_adr_7_i_i_0))
+          ))
+          (net (rename wb_adr_7_i_i_5_0 "wb_adr_7_i_i_5[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_5_0))
+           (portRef D (instanceRef wb_adr_7_i_i_0))
+          ))
+          (net N_592 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_m3))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_a3_1_0 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S))
+          ))
+          (net N_615 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_0))
+           (portRef A (instanceRef nRAS_s_i_0_a3_0_RNIIR094))
+           (portRef A (instanceRef nRAS_s_i_0_0_RNI0PC64))
+          ))
+          (net N_616 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_1))
+           (portRef B (instanceRef nRAS_s_i_0_0_RNI0PC64))
+          ))
+          (net nRAS_s_i_0_0 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_0))
+           (portRef D (instanceRef nRAS_s_i_0_0_RNI0PC64))
+          ))
+          (net N_358_i (joined
+           (portRef Z (instanceRef nRAS_s_i_0_0_RNI0PC64))
+           (portRef N_358_i)
+          ))
+          (net N_640 (joined
+           (portRef Z (instanceRef nCAS_s_i_0_a3))
+           (portRef A (instanceRef nCAS_s_i_0_a3_RNIO1UQ3))
+          ))
+          (net N_641 (joined
+           (portRef Z (instanceRef nCAS_s_i_0_a3_0))
+           (portRef B (instanceRef nCAS_s_i_0_a3_RNIO1UQ3))
+          ))
+          (net nWE_c (joined
+           (portRef nWE_c)
+           (portRef C (instanceRef nRAS_s_i_0_o2))
+           (portRef D (instanceRef RWSel_2_0_a3_0_a3))
+           (portRef D (instanceRef RA_35_2_0_a3_3_10))
+           (portRef D (instanceRef nRAS_s_i_0_a3_1))
+           (portRef C (instanceRef RDOE_i))
+           (portRef C (instanceRef un1_nDOE_i))
+           (portRef D (instanceRef CKE_7s2_0_0_o3))
+           (portRef C (instanceRef CKE_7_am))
+           (portRef D (instanceRef nCAS_s_i_0_a3_RNIO1UQ3))
+          ))
+          (net N_370_i (joined
+           (portRef Z (instanceRef nCAS_s_i_0_a3_RNIO1UQ3))
+           (portRef N_370_i)
+          ))
+          (net N_760 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_4))
+           (portRef B (instanceRef wb_dati_7_0_0_4))
+           (portRef A (instanceRef wb_dati_7_0_0_2))
+           (portRef A (instanceRef wb_dati_7_0_0_5))
+          ))
+          (net (rename wb_dati_7_0_0_o3_0_2 "wb_dati_7_0_0_o3_0[2]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_o3_0_2))
+           (portRef D (instanceRef wb_dati_7_0_0_2))
+           (portRef D (instanceRef wb_dati_7_0_0_5))
+          ))
+          (net N_602 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_a3_7))
+           (portRef A (instanceRef wb_dati_7_0_0_0_7))
+          ))
+          (net (rename wb_dati_7_0_0_RNO_0_7 "wb_dati_7_0_0_RNO_0[7]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_RNO_0_7))
+           (portRef C (instanceRef wb_dati_7_0_0_0_7))
+          ))
+          (net (rename wb_dati_7_0_0_0_0_7 "wb_dati_7_0_0_0_0[7]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_0_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_7))
+          ))
+          (net N_886 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_m3))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5))
+           (portRef B (instanceRef CmdExecMXO2_3_0_a3_0_RNI6S1P8))
+          ))
+          (net SUM0_i_a3_4_0 (joined
+           (portRef Z (instanceRef CmdExecMXO2_3_0_a3_0_RNIAJ811))
+           (portRef D (instanceRef CmdExecMXO2_3_0_a3_0_RNIPG3P2))
+           (portRef C (instanceRef CmdExecMXO2_3_0_a3_0_RNI6S1P8))
+          ))
+          (net SUM1_0_0 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0))
+           (portRef D (instanceRef CmdExecMXO2_3_0_a3_0_RNI6S1P8))
+          ))
+          (net (rename CmdExecMXO2_3_0_a3_0_RNI6S1P8_1z "CmdExecMXO2_3_0_a3_0_RNI6S1P8") (joined
+           (portRef Z (instanceRef CmdExecMXO2_3_0_a3_0_RNI6S1P8))
+           (portRef CmdExecMXO2_3_0_a3_0_RNI6S1P8_1z)
+          ))
+          (net (rename wb_dati_7_0_0_0_6 "wb_dati_7_0_0_0[6]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_6))
+           (portRef D (instanceRef wb_dati_7_0_0_6))
+          ))
+          (net N_763 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_2_4))
+           (portRef C (instanceRef wb_dati_7_0_0_4))
+          ))
+          (net (rename wb_dati_7_0_0_0_4 "wb_dati_7_0_0_0[4]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_4))
+           (portRef D (instanceRef wb_dati_7_0_0_4))
+          ))
+          (net (rename CS_1 "CS[1]") (joined
+           (portRef (member cs 1))
+           (portRef D (instanceRef CmdBitbangMXO2_3_0_a3_0))
+           (portRef A (instanceRef SUM0_i_m3_0_bm))
+           (portRef A (instanceRef SUM0_i_o2))
+           (portRef A (instanceRef CmdExecMXO2_3_0_a3_0_RNIAJ811))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o2))
+           (portRef A (instanceRef CmdExecMXO2_3_0_a3_0_RNIPG3P2))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_m3))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5))
+          ))
+          (net N_720_tz (joined
+           (portRef Z (instanceRef CmdExecMXO2_3_0_a3_0_RNIPG3P2))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5))
+          ))
+          (net (rename CS_2 "CS[2]") (joined
+           (portRef (member cs 0))
+           (portRef C (instanceRef CmdBitbangMXO2_3_0_a3_0))
+           (portRef B (instanceRef SUM0_i_o2))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_5_1))
+           (portRef B (instanceRef CmdExecMXO2_3_0_a3_0_RNIAJ811))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_2_2))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1))
+           (portRef B (instanceRef CmdExecMXO2_3_0_a3_0_RNIPG3P2))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95))
+          ))
+          (net N_350 (joined
+           (portRef Z (instanceRef SUM0_i_o2_2))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95))
+          ))
+          (net SUM0_i_0 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95))
+          ))
+          (net CmdRWMaskSet (joined
+           (portRef CmdRWMaskSet)
+           (portRef A (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0_0))
+          ))
+          (net (rename un1_RWMask_0_sqmuxa_1_i_0_a3_0_0_0 "un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]") (joined
+           (portRef Z (instanceRef un1_RWMask_0_sqmuxa_1_i_0_a3_0_0_0))
+           (portRef D (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0_0))
+          ))
+          (net (rename wb_dati_7_0_0_0_a3_0_0 "wb_dati_7_0_0_0_a3_0[0]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_a3_0_0))
+           (portRef D (instanceRef wb_dati_7_0_0_0_0))
+          ))
+          (net N_611 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_2_3))
+           (portRef B (instanceRef wb_dati_7_0_0_o3_0_2))
+           (portRef A (instanceRef wb_dati_7_0_0_0_3))
+           (portRef A (instanceRef wb_dati_7_0_0_1))
+          ))
+          (net (rename wb_dati_7_0_0_0_1 "wb_dati_7_0_0_0[1]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_1))
+           (portRef D (instanceRef wb_dati_7_0_0_1))
+          ))
+          (net N_234 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91))
+           (portRef C (instanceRef CmdExecMXO2_3_0_a3_0_RNIPG3P2))
+           (portRef D (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_m3))
+           (portRef D (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514))
+          ))
+          (net (rename CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_1z "CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514") (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514))
+           (portRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_1z)
+          ))
+          (net N_783 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_7_3))
+           (portRef C (instanceRef wb_adr_7_i_i_3_0))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_4))
+           (portRef A (instanceRef wb_dati_7_0_0_0_4))
+           (portRef A (instanceRef wb_dati_7_0_0_0_6))
+           (portRef A (instanceRef wb_dati_7_0_0_0_0_3))
+           (portRef B (instanceRef wb_dati_7_0_0_0_3))
+          ))
+          (net (rename wb_dati_7_0_0_0_0_3 "wb_dati_7_0_0_0_0[3]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_0_3))
+           (portRef D (instanceRef wb_dati_7_0_0_0_3))
+          ))
+          (net N_634 (joined
+           (portRef Z (instanceRef wb_we_7_iv_0_0_0_a3_1))
+           (portRef C (instanceRef wb_we_RNO_3))
+           (portRef A (instanceRef wb_adr_7_i_i_4_0))
+          ))
+          (net N_753 (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_a3_4_0))
+           (portRef B (instanceRef wb_adr_7_i_i_4_0))
+          ))
+          (net (rename wb_adr_7_i_i_1_0 "wb_adr_7_i_i_1[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_1_0))
+           (portRef C (instanceRef wb_adr_7_i_i_4_0))
+          ))
+          (net (rename wb_adr_7_i_i_3_0 "wb_adr_7_i_i_3[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_3_0))
+           (portRef D (instanceRef wb_adr_7_i_i_4_0))
+          ))
+          (net N_755 (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_a3_6_0))
+           (portRef C (instanceRef wb_adr_7_i_i_5_0))
+          ))
+          (net N_345 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2))
+          ))
+          (net N_735 (joined
+           (portRef Z (instanceRef SUM0_i_a3_1))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2))
+          ))
+          (net CmdLEDSet (joined
+           (portRef CmdLEDSet)
+           (portRef A (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_0))
+          ))
+          (net (rename un1_CmdSetRWBankFFChip13_1_i_0_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_0[0]") (joined
+           (portRef Z (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0_0))
+           (portRef C (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0))
+          ))
+          (net (rename wb_dati_7_0_0_a3_6_1_3 "wb_dati_7_0_0_a3_6_1[3]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_4_1_0_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_o2_3))
+           (portRef D (instanceRef wb_dati_7_0_0_RNO_0_7))
+          ))
+          (net (rename FS_14 "FS[14]") (joined
+           (portRef (member fs 1))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_10_7))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_14_7))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_12_7))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_7_3))
+           (portRef A (instanceRef wb_we_7_iv_0_0_0_a3_6))
+           (portRef A (instanceRef wb_rst8_0_a3_0_a3))
+           (portRef B (instanceRef wb_adr_RNO_4))
+           (portRef B (instanceRef wb_adr_RNO_5))
+           (portRef B (instanceRef wb_adr_RNO_6))
+           (portRef C (instanceRef Ready3_0_a3_4))
+           (portRef A (instanceRef wb_reqc_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_9_7))
+           (portRef B (instanceRef wb_cyc_stb_RNO_0))
+           (portRef A (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0_0))
+           (portRef A (instanceRef RA_35_0_0_0_7))
+          ))
+          (net N_801 (joined
+           (portRef Z (instanceRef RA_35_0_0_a3_4_7))
+           (portRef C (instanceRef RA_35_0_0_0))
+           (portRef B (instanceRef RA_35_0_0_3))
+           (portRef B (instanceRef RA_35_0_0_4))
+           (portRef B (instanceRef RA_35_0_0_0_6))
+           (portRef B (instanceRef RA_35_0_0_0_7))
+          ))
+          (net (rename RA_35_0_0_0_0_7 "RA_35_0_0_0_0[7]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_0_7))
+           (portRef C (instanceRef RA_35_0_0_0_7))
+          ))
+          (net (rename RA_35_7 "RA_35[7]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_7))
+           (portRef (member ra_35 4))
+          ))
+          (net (rename RA_35_0_0_0_0_6 "RA_35_0_0_0_0[6]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_0_6))
+           (portRef C (instanceRef RA_35_0_0_0_6))
+          ))
+          (net (rename RA_35_6 "RA_35[6]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_6))
+           (portRef (member ra_35 5))
+          ))
+          (net (rename RA_35_0_0_0_4 "RA_35_0_0_0[4]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_4))
+           (portRef C (instanceRef RA_35_0_0_4))
+          ))
+          (net (rename RA_35_4 "RA_35[4]") (joined
+           (portRef Z (instanceRef RA_35_0_0_4))
+           (portRef (member ra_35 7))
+          ))
+          (net (rename RA_35_0_0_0_3 "RA_35_0_0_0[3]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_3))
+           (portRef C (instanceRef RA_35_0_0_3))
+          ))
+          (net (rename RA_35_3 "RA_35[3]") (joined
+           (portRef Z (instanceRef RA_35_0_0_3))
+           (portRef (member ra_35 8))
+          ))
+          (net (rename wb_dati_7_0_0_0_a3_0_3 "wb_dati_7_0_0_0_a3_0[3]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_a3_0_3))
+           (portRef D (instanceRef wb_dati_7_0_0_0_0_3))
+          ))
+          (net (rename wb_dati_7_0_0_a3_1_6 "wb_dati_7_0_0_a3_1[6]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_1_0_6))
+           (portRef D (instanceRef wb_dati_7_0_0_0_6))
+          ))
+          (net CKE_7_am (joined
+           (portRef Z (instanceRef CKE_7_am))
+           (portRef BLUT (instanceRef CKE_7))
+          ))
+          (net CKE_7_bm (joined
+           (portRef Z (instanceRef CKE_7_bm))
+           (portRef ALUT (instanceRef CKE_7))
+          ))
+          (net CKE_7_sm0 (joined
+           (portRef Z (instanceRef CKE_7s2_0_0))
+           (portRef C0 (instanceRef CKE_7))
+          ))
+          (net N_687 (joined
+           (portRef Z (instanceRef wb_cyc_stb_RNO_0))
+           (portRef A (instanceRef wb_cyc_stb_RNO))
+          ))
+          (net (rename un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0]") (joined
+           (portRef Z (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0))
+           (portRef C (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0_0))
+          ))
+          (net N_256 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_o2_0))
+           (portRef B (instanceRef nRAS_s_i_0_0))
+          ))
+          (net N_890 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_8))
+           (portRef C (instanceRef nCAS_s_i_0_a3))
+           (portRef D (instanceRef nRAS_s_i_0_0))
+          ))
+          (net N_220 (joined
+           (portRef Z (instanceRef CKE_7s2_0_0_o3))
+           (portRef A (instanceRef CKE_7s2_0_0))
+           (portRef B (instanceRef nCAS_s_i_0_a3))
+          ))
+          (net N_196 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_o2_4))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_4))
+          ))
+          (net (rename Ain_c_1 "Ain_c[1]") (joined
+           (portRef (member ain_c 6))
+           (portRef A (instanceRef RA_35_i_i_0_1))
+          ))
+          (net N_182 (joined
+           (portRef Z (instanceRef RA_35_0_0_o2_5))
+           (portRef B (instanceRef RA_35_0_0_1_0))
+           (portRef B (instanceRef RA_35_0_0_0_3))
+           (portRef B (instanceRef RA_35_0_0_0_0_7))
+           (portRef B (instanceRef RA_35_0_0_0_0_6))
+           (portRef B (instanceRef RA_35_0_0_0_4))
+           (portRef B (instanceRef RA_35_0_0_5))
+           (portRef B (instanceRef RA_35_0_0_2))
+           (portRef B (instanceRef RA_35_i_i_0_1))
+          ))
+          (net N_659 (joined
+           (portRef Z (instanceRef RA_35_i_i_0_a3_1))
+           (portRef C (instanceRef RA_35_i_i_0_1))
+          ))
+          (net N_660 (joined
+           (portRef Z (instanceRef RA_35_i_i_0_a3_0_1))
+           (portRef D (instanceRef RA_35_i_i_0_1))
+          ))
+          (net N_223 (joined
+           (portRef Z (instanceRef RA_35_i_i_0_1))
+           (portRef N_223)
+          ))
+          (net (rename Ain_c_2 "Ain_c[2]") (joined
+           (portRef (member ain_c 5))
+           (portRef A (instanceRef RA_35_0_0_2))
+          ))
+          (net N_679 (joined
+           (portRef Z (instanceRef RA_35_0_0_a3_2))
+           (portRef C (instanceRef RA_35_0_0_2))
+          ))
+          (net N_680 (joined
+           (portRef Z (instanceRef RA_35_0_0_a3_0_2))
+           (portRef D (instanceRef RA_35_0_0_2))
+          ))
+          (net (rename RA_35_2 "RA_35[2]") (joined
+           (portRef Z (instanceRef RA_35_0_0_2))
+           (portRef (member ra_35 9))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_o2 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o2))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_0))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_a3_0_1 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_0_1))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_0))
+          ))
+          (net (rename Ain_c_5 "Ain_c[5]") (joined
+           (portRef (member ain_c 2))
+           (portRef A (instanceRef RA_35_0_0_5))
+          ))
+          (net N_621 (joined
+           (portRef Z (instanceRef RA_35_0_0_a3_5))
+           (portRef C (instanceRef RA_35_0_0_5))
+          ))
+          (net (rename RA_35_0_0_0_5 "RA_35_0_0_0[5]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_5))
+           (portRef D (instanceRef RA_35_0_0_5))
+          ))
+          (net (rename RA_35_5 "RA_35[5]") (joined
+           (portRef Z (instanceRef RA_35_0_0_5))
+           (portRef (member ra_35 6))
+          ))
+          (net N_624 (joined
+           (portRef Z (instanceRef RA_35_2_0_a3_10))
+           (portRef A (instanceRef RA_35_2_0_10))
+          ))
+          (net N_628 (joined
+           (portRef Z (instanceRef RA_35_2_0_a3_3_10))
+           (portRef C (instanceRef RA_35_2_0_10))
+          ))
+          (net (rename RA_35_2_0_0_10 "RA_35_2_0_0[10]") (joined
+           (portRef Z (instanceRef RA_35_2_0_0_10))
+           (portRef D (instanceRef RA_35_2_0_10))
+          ))
+          (net (rename RA_35_10 "RA_35[10]") (joined
+           (portRef Z (instanceRef RA_35_2_0_10))
+           (portRef (member ra_35 1))
+          ))
+          (net N_208 (joined
+           (portRef Z (instanceRef wb_we_RNO_1))
+           (portRef B (instanceRef wb_we_RNO))
+          ))
+          (net N_799 (joined
+           (portRef Z (instanceRef wb_we_7_iv_0_0_0_a3_6))
+           (portRef D (instanceRef wb_adr_RNO_0_1))
+           (portRef D (instanceRef wb_we_RNO_3))
+           (portRef B (instanceRef wb_we_RNO_2))
+           (portRef C (instanceRef wb_adr_RNO_1_1))
+           (portRef C (instanceRef wb_we_RNO))
+          ))
+          (net wb_we_7_iv_0_0_3_0_1 (joined
+           (portRef Z (instanceRef wb_we_RNO_2))
+           (portRef D (instanceRef wb_we_RNO))
+          ))
+          (net (rename Din_c_1 "Din_c[1]") (joined
+           (portRef (member din_c 6))
+           (portRef B (instanceRef CmdRWMaskSet_3_0_a3))
+           (portRef B (instanceRef CmdLEDSet_3_0_a8_0_a3))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0_0))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91))
+           (portRef A (instanceRef RDout_i_0_i_a3_1))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_5_1))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0))
+           (portRef A (instanceRef RWMask_RNO_1))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o3_0))
+           (portRef A (instanceRef RWBank_3_0_1))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_9))
+           (portRef C0 (instanceRef SUM0_i_m3_0))
+           (portRef A (instanceRef CmdLEDGet_3_0_a3))
+           (portRef A (instanceRef CmdSetRWBankFFLED_4_0_a8_0_a3))
+           (portRef A (instanceRef CmdBitbangMXO2_3_0_a3))
+           (portRef A (instanceRef wb_adr_RNO_1))
+          ))
+          (net N_768 (joined
+           (portRef Z (instanceRef wb_adr_RNO_0_1))
+           (portRef B (instanceRef wb_adr_RNO_1))
+          ))
+          (net wb_adr_7_5_41_0_1 (joined
+           (portRef Z (instanceRef wb_adr_RNO_1_1))
+           (portRef D (instanceRef wb_adr_RNO_1))
+          ))
+          (net (rename Din_c_4 "Din_c[4]") (joined
+           (portRef (member din_c 3))
+           (portRef C (instanceRef CmdLEDGet_3_0_a3_1))
+           (portRef D (instanceRef CmdRWMaskSet_3_0_a3))
+           (portRef D (instanceRef CmdLEDSet_3_0_a8_0_a3))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0_0))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o3))
+           (portRef A (instanceRef RDout_i_i_a3_4))
+           (portRef A (instanceRef wb_adr_RNO_4))
+           (portRef A (instanceRef RWMask_RNO_4))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_0_1))
+           (portRef A (instanceRef RWBank_3_0_0_4))
+           (portRef B (instanceRef SUM0_i_o2_2))
+           (portRef B (instanceRef CmdSetRWBankFFLED_4_0_a8_0_a3))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1))
+          ))
+          (net N_212 (joined
+           (portRef Z (instanceRef SUM1_0_o3_0))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1))
+          ))
+          (net N_850 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_9))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o2))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1))
+          ))
+          (net (rename Din_c_0 "Din_c[0]") (joined
+           (portRef (member din_c 7))
+           (portRef A (instanceRef CmdLEDGet_3_0_a3_1))
+           (portRef B (instanceRef CmdBitbangMXO2_3_0_a3_1))
+           (portRef D (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0_0))
+           (portRef A (instanceRef RDout_i_0_i_a3_0))
+           (portRef A (instanceRef wb_we_7_iv_0_0_0_a3_1))
+           (portRef A (instanceRef LEDEN_RNO))
+           (portRef A (instanceRef SUM1_0_o3_0))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0))
+           (portRef A (instanceRef RWMask_RNO_0))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_0_1))
+           (portRef B (instanceRef SUM0_i_a3_1))
+           (portRef A (instanceRef RWBank_3_0_0_0))
+           (portRef A (instanceRef CmdRWMaskSet_3_0_a3_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_2_2))
+          ))
+          (net N_243 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o3_0))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_2_2))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_o3 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o3))
+           (portRef A (instanceRef CmdBitbangMXO2_3_0_a3_1))
+           (portRef B (instanceRef CmdExecMXO2_3_0_a3_0))
+           (portRef D (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_2_2))
+          ))
+          (net (rename Ain_c_4 "Ain_c[4]") (joined
+           (portRef (member ain_c 3))
+           (portRef A (instanceRef RA_35_0_0_0_4))
+          ))
+          (net N_186 (joined
+           (portRef Z (instanceRef RA_35_0_0_o2_0_5))
+           (portRef C (instanceRef RA_35_0_0_1_0))
+           (portRef A (instanceRef RA_35_0_0_a3_0_2))
+           (portRef A (instanceRef RA_35_i_i_0_a3_0_1))
+           (portRef A (instanceRef RA_35_0_0_a3_5))
+           (portRef C (instanceRef RA_35_0_0_0_3))
+           (portRef C (instanceRef RA_35_0_0_0_0_7))
+           (portRef C (instanceRef RA_35_0_0_0_0_6))
+           (portRef C (instanceRef RA_35_0_0_0_4))
+          ))
+          (net (rename RA_4 "RA[4]") (joined
+           (portRef (member ra 7))
+           (portRef D (instanceRef RA_35_0_0_0_4))
+          ))
+          (net (rename Ain_c_6 "Ain_c[6]") (joined
+           (portRef (member ain_c 1))
+           (portRef A (instanceRef RA_35_0_0_0_0_6))
+          ))
+          (net (rename RA_6 "RA[6]") (joined
+           (portRef (member ra 5))
+           (portRef D (instanceRef RA_35_0_0_0_0_6))
+          ))
+          (net (rename Ain_c_7 "Ain_c[7]") (joined
+           (portRef (member ain_c 0))
+           (portRef A (instanceRef RA_35_0_0_0_0_7))
+          ))
+          (net (rename RA_7 "RA[7]") (joined
+           (portRef (member ra 4))
+           (portRef D (instanceRef RA_35_0_0_0_0_7))
+          ))
+          (net (rename Ain_c_3 "Ain_c[3]") (joined
+           (portRef (member ain_c 4))
+           (portRef A (instanceRef RA_35_0_0_0_3))
+          ))
+          (net (rename RA_3 "RA[3]") (joined
+           (portRef (member ra 8))
+           (portRef B (instanceRef RWSel_2_0_a3_0_a3))
+           (portRef D (instanceRef RA_35_0_0_0_3))
+          ))
+          (net N_781 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_9_7))
+           (portRef C (instanceRef wb_dati_7_0_0_o3_0_2))
+           (portRef D (instanceRef wb_adr_7_i_i_a3_4_0))
+           (portRef C (instanceRef wb_adr_7_i_i_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_0_0_7))
+           (portRef A (instanceRef wb_dati_7_0_0_0_1))
+          ))
+          (net (rename wb_dati_7_0_0_a3_0_0_1 "wb_dati_7_0_0_a3_0_0[1]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_0_0_1))
+           (portRef D (instanceRef wb_dati_7_0_0_0_1))
+          ))
+          (net N_565 (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_o2_1_0))
+           (portRef B (instanceRef wb_adr_7_i_i_1_0))
+          ))
+          (net (rename wb_adr_7_i_i_a3_2_0_0 "wb_adr_7_i_i_a3_2_0[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_a3_2_0_0))
+           (portRef D (instanceRef wb_adr_7_i_i_1_0))
+          ))
+          (net (rename Din_c_7 "Din_c[7]") (joined
+           (portRef (member din_c 0))
+           (portRef B (instanceRef CmdLEDGet_3_0_a3_1))
+           (portRef C (instanceRef CmdRWMaskSet_3_0_a3))
+           (portRef C (instanceRef CmdLEDSet_3_0_a8_0_a3))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o3))
+           (portRef A (instanceRef RDout_i_0_i_a3_7))
+           (portRef A (instanceRef RWMask_RNO_7))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_5_1))
+           (portRef A (instanceRef wb_adr_RNO_7))
+           (portRef A (instanceRef RWBank_3_0_7))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_9))
+           (portRef C (instanceRef SUM0_i_m3_0_am))
+           (portRef C (instanceRef CmdSetRWBankFFLED_4_0_a8_0_a3))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R))
+          ))
+          (net N_361_i (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIFNP81_2))
+           (portRef N_361_i)
+          ))
+          (net (rename RA_5 "RA[5]") (joined
+           (portRef (member ra 6))
+           (portRef B (instanceRef RA_35_0_0_a3_5))
+          ))
+          (net (rename RA_1 "RA[1]") (joined
+           (portRef (member ra 10))
+           (portRef B (instanceRef RA_35_i_i_0_a3_0_1))
+          ))
+          (net (rename RA_2 "RA[2]") (joined
+           (portRef (member ra 9))
+           (portRef B (instanceRef RA_35_0_0_a3_0_2))
+          ))
+          (net (rename FS_0 "FS[0]") (joined
+           (portRef (member fs 15))
+           (portRef A (instanceRef Ready3_0_a3_3))
+           (portRef A (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0))
+           (portRef A (instanceRef N_285_i))
+           (portRef A (instanceRef wb_cyc_stb_RNO_0))
+          ))
+          (net N_336 (joined
+           (portRef Z (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0))
+           (portRef B (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0))
+           (portRef C (instanceRef wb_cyc_stb_RNO_0))
+          ))
+          (net N_242 (joined
+           (portRef Z (instanceRef RA_35_0_0_o2_11))
+           (portRef A (instanceRef RA_35_0_0_9))
+           (portRef A (instanceRef RA_35_0_0_11))
+          ))
+          (net (rename RA_11 "RA[11]") (joined
+           (portRef (member ra 0))
+           (portRef C (instanceRef RA_35_0_0_11))
+          ))
+          (net (rename RWBank_4 "RWBank[4]") (joined
+           (portRef (member rwbank 3))
+           (portRef D (instanceRef RA_35_0_0_11))
+          ))
+          (net (rename RA_35_11 "RA_35[11]") (joined
+           (portRef Z (instanceRef RA_35_0_0_11))
+           (portRef (member ra_35 0))
+          ))
+          (net N_190 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o2))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_a3_5_1 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_5_1))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o2))
+          ))
+          (net N_851 (joined
+           (portRef Z (instanceRef CmdExecMXO2_3_0_a3_0))
+           (portRef B (instanceRef CmdExecMXO2_3_0_a3))
+           (portRef D (instanceRef CmdExecMXO2_3_0_a3_0_RNIAJ811))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0))
+          ))
+          (net N_817 (joined
+           (portRef Z (instanceRef CKE_7s2_0_0_a2_1))
+           (portRef B (instanceRef nRAS_s_i_0_a3_8))
+           (portRef A (instanceRef CKE_7_bm))
+           (portRef B (instanceRef CKE_7s2_0_0))
+          ))
+          (net CKE_7s2_0_0_0 (joined
+           (portRef Z (instanceRef CKE_7s2_0_0_0))
+           (portRef C (instanceRef CKE_7s2_0_0))
+          ))
+          (net (rename RA_9 "RA[9]") (joined
+           (portRef (member ra 2))
+           (portRef B (instanceRef RA_35_0_0_9))
+          ))
+          (net (rename RA_35_0_0_0_9 "RA_35_0_0_0[9]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_9))
+           (portRef C (instanceRef RA_35_0_0_9))
+          ))
+          (net (rename RA_35_9 "RA_35[9]") (joined
+           (portRef Z (instanceRef RA_35_0_0_9))
+           (portRef (member ra_35 2))
+          ))
+          (net (rename Din_c_2 "Din_c[2]") (joined
+           (portRef (member din_c 5))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0_0))
+           (portRef A (instanceRef RDout_i_0_i_a3_2))
+           (portRef B (instanceRef SUM1_0_o3_0))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0))
+           (portRef A (instanceRef wb_adr_RNO_2))
+           (portRef A (instanceRef RWMask_RNO_2))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_0_1))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o3_0))
+           (portRef A (instanceRef RWBank_3_0_2))
+           (portRef B (instanceRef CmdLEDGet_3_0_a3))
+           (portRef B (instanceRef CmdRWMaskSet_3_0_a3_0))
+           (portRef A (instanceRef SUM0_i_o2_2))
+           (portRef B (instanceRef CmdBitbangMXO2_3_0_a3))
+          ))
+          (net N_800 (joined
+           (portRef Z (instanceRef CmdBitbangMXO2_3_0_a3_0))
+           (portRef C (instanceRef CmdLEDGet_3_0_a3_0))
+           (portRef A (instanceRef CmdExecMXO2_3_0_a3))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3))
+           (portRef C (instanceRef CmdBitbangMXO2_3_0_a3))
+          ))
+          (net CmdBitbangMXO2_3_0_a3_1 (joined
+           (portRef Z (instanceRef CmdBitbangMXO2_3_0_a3_1))
+           (portRef D (instanceRef CmdBitbangMXO2_3_0_a3))
+          ))
+          (net CmdSetRWBankFFChip_3_0_a8_0_a3_0 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0_0))
+           (portRef D (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3))
+          ))
+          (net N_883 (joined
+           (portRef Z (instanceRef CmdRWMaskSet_3_0_a3_0))
+           (portRef A (instanceRef CmdRWMaskSet_3_0_a3))
+           (portRef A (instanceRef CmdLEDSet_3_0_a8_0_a3))
+           (portRef D (instanceRef CmdSetRWBankFFLED_4_0_a8_0_a3))
+          ))
+          (net CmdSetRWBankFFLED_4 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFLED_4_0_a8_0_a3))
+           (portRef CmdSetRWBankFFLED_4)
+          ))
+          (net N_885 (joined
+           (portRef Z (instanceRef wb_we_7_iv_0_0_0_a3_7))
+           (portRef A (instanceRef un1_RWMask_0_sqmuxa_1_i_0_a3_0_0_0))
+           (portRef C (instanceRef wb_we_RNO_2))
+           (portRef A (instanceRef Ready3_0_a3))
+          ))
+          (net Ready3_0_a3_3 (joined
+           (portRef Z (instanceRef Ready3_0_a3_3))
+           (portRef B (instanceRef Ready3_0_a3))
+          ))
+          (net Ready3_0_a3_4 (joined
+           (portRef Z (instanceRef Ready3_0_a3_4))
+           (portRef C (instanceRef Ready3_0_a3))
+          ))
+          (net Ready3_0_a3_5 (joined
+           (portRef Z (instanceRef Ready3_0_a3_5))
+           (portRef D (instanceRef Ready3_0_a3))
+          ))
+          (net Ready3 (joined
+           (portRef Z (instanceRef Ready3_0_a3))
+           (portRef Ready3)
+          ))
+          (net N_184 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_o2_7))
+           (portRef A (instanceRef wb_dati_7_0_0_o3_0_2))
+           (portRef B (instanceRef wb_we_RNO_3))
+           (portRef A (instanceRef wb_adr_RNO_1_1))
+          ))
+          (net N_204 (joined
+           (portRef Z (instanceRef wb_adr_RNO_3_1))
+           (portRef B (instanceRef wb_adr_RNO_1_1))
+          ))
+          (net wb_adr_7_5_41_a3_3_0 (joined
+           (portRef Z (instanceRef wb_adr_RNO_4_1))
+           (portRef D (instanceRef wb_adr_RNO_1_1))
+          ))
+          (net wb_we_7_iv_0_0_3_0_0 (joined
+           (portRef Z (instanceRef wb_we_RNO_3))
+           (portRef D (instanceRef wb_we_RNO_2))
+          ))
+          (net N_595 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_o2_0_3))
+           (portRef B (instanceRef wb_dati_7_0_0_0_a3_0_3))
+          ))
+          (net N_254 (joined
+           (portRef Z (instanceRef nCAS_s_i_0_m2))
+           (portRef B (instanceRef nCAS_s_i_0_a3_0))
+          ))
+          (net N_338 (joined
+           (portRef Z (instanceRef SUM0_i_m3_0))
+           (portRef C (instanceRef SUM0_i_o2_2))
+          ))
+          (net (rename N_369_i_1z "N_369_i") (joined
+           (portRef Z (instanceRef N_369_i))
+           (portRef N_369_i_1z)
+          ))
+          (net N_271 (joined
+           (portRef Z (instanceRef S_r_i_0_o2_0_1))
+           (portRef B (instanceRef S_s_0_0_0))
+           (portRef C (instanceRef S_r_i_0_o2_0_RNI36E21_1))
+          ))
+          (net N_362_i (joined
+           (portRef Z (instanceRef S_r_i_0_o2_0_RNI36E21_1))
+           (portRef N_362_i)
+          ))
+          (net (rename RA_10 "RA[10]") (joined
+           (portRef (member ra 1))
+           (portRef C (instanceRef RA_35_2_0_a3_10))
+          ))
+          (net (rename FS_5 "FS[5]") (joined
+           (portRef (member fs 10))
+           (portRef B (instanceRef Ready3_0_a3_3))
+           (portRef B (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0))
+           (portRef B (instanceRef RA_35_i_i_0_a3_1))
+          ))
+          (net (rename FS_6 "FS[6]") (joined
+           (portRef (member fs 9))
+           (portRef C (instanceRef Ready3_0_a3_3))
+           (portRef D (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0))
+           (portRef B (instanceRef RA_35_0_0_a3_2))
+          ))
+          (net N_847 (joined
+           (portRef Z (instanceRef CmdLEDGet_3_0_a3_0))
+           (portRef C (instanceRef CmdLEDGet_3_0_a3))
+           (portRef C (instanceRef CmdRWMaskSet_3_0_a3_0))
+          ))
+          (net (rename RWBank_6 "RWBank[6]") (joined
+           (portRef (member rwbank 1))
+           (portRef C (instanceRef BA_4_1))
+          ))
+          (net (rename BA_4_1 "BA_4[1]") (joined
+           (portRef Z (instanceRef BA_4_1))
+           (portRef (member ba_4 0))
+          ))
+          (net (rename RWBank_5 "RWBank[5]") (joined
+           (portRef (member rwbank 2))
+           (portRef C (instanceRef BA_4_0))
+          ))
+          (net (rename BA_4_0 "BA_4[0]") (joined
+           (portRef Z (instanceRef BA_4_0))
+           (portRef (member ba_4 1))
+          ))
+          (net wb_reqc_1 (joined
+           (portRef Z (instanceRef wb_reqc_1_0))
+           (portRef D (instanceRef wb_req_RNO))
+          ))
+          (net N_126 (joined
+           (portRef Z (instanceRef un1_CKE75_0_i_0))
+           (portRef N_126)
+          ))
+          (net N_226 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_o2))
+           (portRef B (instanceRef nRAS_s_i_0_a3_0))
+          ))
+          (net (rename S_s_0_0_0 "S_s_0_0[0]") (joined
+           (portRef Z (instanceRef S_s_0_0_0))
+           (portRef S_s_0_0_0)
+          ))
+          (net CmdLEDGet_3_0_a3_1 (joined
+           (portRef Z (instanceRef CmdLEDGet_3_0_a3_1))
+           (portRef D (instanceRef CmdLEDGet_3_0_a3))
+          ))
+          (net CmdLEDGet_3 (joined
+           (portRef Z (instanceRef CmdLEDGet_3_0_a3))
+           (portRef CmdLEDGet_3)
+          ))
+          (net N_221 (joined
+           (portRef Z (instanceRef un2_S_2_i_0_0_o3))
+           (portRef A (instanceRef CKE_7s2_0_0_0))
+           (portRef A (instanceRef un2_S_2_i_0_0_o3_RNIHFHN3))
+          ))
+          (net N_698 (joined
+           (portRef Z (instanceRef RA_35_2_30_a3_2))
+           (portRef B (instanceRef un2_S_2_i_0_0_o3_RNIHFHN3))
+          ))
+          (net (rename RA_8 "RA[8]") (joined
+           (portRef (member ra 3))
+           (portRef D (instanceRef un2_S_2_i_0_0_o3_RNIHFHN3))
+          ))
+          (net (rename un2_S_2_i_0_0_o3_RNIHFHN3_1z "un2_S_2_i_0_0_o3_RNIHFHN3") (joined
+           (portRef Z (instanceRef un2_S_2_i_0_0_o3_RNIHFHN3))
+           (portRef un2_S_2_i_0_0_o3_RNIHFHN3_1z)
+          ))
+          (net (rename RWBank_2 "RWBank[2]") (joined
+           (portRef (member rwbank 5))
+           (portRef D (instanceRef RA_35_0_0_0_9))
+          ))
+          (net N_625 (joined
+           (portRef Z (instanceRef RA_35_2_0_a3_0_10))
+           (portRef A (instanceRef RA_35_2_0_0_10))
+          ))
+          (net (rename RWBankZ0Z_3 "RWBank[3]") (joined
+           (portRef (member rwbank 4))
+           (portRef C (instanceRef RA_35_2_0_0_10))
+          ))
+          (net (rename Din_c_3 "Din_c[3]") (joined
+           (portRef (member din_c 4))
+           (portRef C (instanceRef SUM0_i_m3_0_bm))
+           (portRef D (instanceRef CmdBitbangMXO2_3_0_a3_1))
+           (portRef D (instanceRef CmdExecMXO2_3_0_a3_0))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3))
+           (portRef A (instanceRef N_263_i))
+           (portRef A (instanceRef wb_adr_RNO_3))
+           (portRef A (instanceRef RWMask_RNO_3))
+           (portRef A (instanceRef CmdLEDGet_3_0_a3_0))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o3_0))
+           (portRef A (instanceRef RWBank_3_0_3))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_9))
+           (portRef A (instanceRef SUM0_i_m3_0_am))
+          ))
+          (net (rename Din_c_5 "Din_c[5]") (joined
+           (portRef (member din_c 2))
+           (portRef B (instanceRef SUM0_i_m3_0_bm))
+           (portRef C (instanceRef CmdBitbangMXO2_3_0_a3_1))
+           (portRef C (instanceRef CmdExecMXO2_3_0_a3_0))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3))
+           (portRef A (instanceRef RDout_i_0_i_a3_5))
+           (portRef A (instanceRef wb_adr_RNO_5))
+           (portRef A (instanceRef RWMask_RNO_5))
+           (portRef B (instanceRef CmdLEDGet_3_0_a3_0))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o3_0))
+           (portRef A (instanceRef RWBank_3_0_5))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_9))
+           (portRef B (instanceRef SUM0_i_m3_0_am))
+          ))
+          (net SUM0_i_m3_0_am (joined
+           (portRef Z (instanceRef SUM0_i_m3_0_am))
+           (portRef BLUT (instanceRef SUM0_i_m3_0))
+          ))
+          (net SUM0_i_m3_0_bm (joined
+           (portRef Z (instanceRef SUM0_i_m3_0_bm))
+           (portRef ALUT (instanceRef SUM0_i_m3_0))
+          ))
+          (net (rename RWBank_0 "RWBank[0]") (joined
+           (portRef (member rwbank 7))
+           (portRef B (instanceRef DQMH_4_iv_0_0_i_i_a3_0_a3))
+           (portRef B (instanceRef N_507_i))
+          ))
+          (net (rename N_507_i_1z "N_507_i") (joined
+           (portRef Z (instanceRef N_507_i))
+           (portRef N_507_i_1z)
+          ))
+          (net (rename N_368_i_1z "N_368_i") (joined
+           (portRef Z (instanceRef N_368_i))
+           (portRef N_368_i_1z)
+          ))
+          (net (rename N_360_i_1z "N_360_i") (joined
+           (portRef Z (instanceRef N_360_i))
+           (portRef N_360_i_1z)
+          ))
+          (net nEN80_c (joined
+           (portRef nEN80_c)
+           (portRef B (instanceRef nRAS_s_i_0_o2))
+           (portRef C (instanceRef nRAS_s_i_0_a3_5))
+           (portRef D (instanceRef CKE_7s2_0_0_0))
+           (portRef C (instanceRef nRAS_s_i_0_a3_1))
+           (portRef B (instanceRef RDOE_i))
+           (portRef C (instanceRef LEDEN_RNI6G6M))
+           (portRef B (instanceRef un1_nDOE_i))
+           (portRef D (instanceRef RA_35_2_0_a3_0_10))
+          ))
+          (net N_188 (joined
+           (portRef Z (instanceRef RWBank_3_0_0_o3_0))
+           (portRef B (instanceRef RWBank_3_0_7))
+           (portRef B (instanceRef RWBank_3_0_6))
+           (portRef B (instanceRef RWBank_3_0_5))
+           (portRef B (instanceRef RWBank_3_0_3))
+           (portRef B (instanceRef RWBank_3_0_2))
+           (portRef B (instanceRef RWBank_3_0_1))
+           (portRef B (instanceRef RWBank_3_0_0_4))
+           (portRef B (instanceRef RWBank_3_0_0_0))
+          ))
+          (net (rename RWBank_3_0 "RWBank_3[0]") (joined
+           (portRef Z (instanceRef RWBank_3_0_0_0))
+           (portRef (member rwbank_3 7))
+          ))
+          (net (rename RWBank_3_4 "RWBank_3[4]") (joined
+           (portRef Z (instanceRef RWBank_3_0_0_4))
+           (portRef (member rwbank_3 3))
+          ))
+          (net (rename RWBank_3_1 "RWBank_3[1]") (joined
+           (portRef Z (instanceRef RWBank_3_0_1))
+           (portRef (member rwbank_3 6))
+          ))
+          (net (rename RWBank_3_2 "RWBank_3[2]") (joined
+           (portRef Z (instanceRef RWBank_3_0_2))
+           (portRef (member rwbank_3 5))
+          ))
+          (net (rename RWBank_3_3 "RWBank_3[3]") (joined
+           (portRef Z (instanceRef RWBank_3_0_3))
+           (portRef (member rwbank_3 4))
+          ))
+          (net (rename RWBank_3_5 "RWBank_3[5]") (joined
+           (portRef Z (instanceRef RWBank_3_0_5))
+           (portRef (member rwbank_3 2))
+          ))
+          (net (rename RWBank_3_6 "RWBank_3[6]") (joined
+           (portRef Z (instanceRef RWBank_3_0_6))
+           (portRef (member rwbank_3 1))
+          ))
+          (net (rename RWBank_3_7 "RWBank_3[7]") (joined
+           (portRef Z (instanceRef RWBank_3_0_7))
+           (portRef (member rwbank_3 0))
+          ))
+          (net N_553 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_o2_3))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_2_3))
+          ))
+          (net (rename RC_3_2 "RC_3[2]") (joined
+           (portRef Z (instanceRef RC_3_0_0_2))
+           (portRef (member rc_3 0))
+          ))
+          (net DOEEN (joined
+           (portRef DOEEN)
+           (portRef A (instanceRef un1_nDOE_i))
+          ))
+          (net nDOE_c (joined
+           (portRef Z (instanceRef un1_nDOE_i))
+           (portRef nDOE_c)
+          ))
+          (net Ready (joined
+           (portRef Ready)
+           (portRef B (instanceRef RDout_i_0_i_a3_0))
+           (portRef B (instanceRef RDout_i_0_i_a3_1))
+           (portRef B (instanceRef RDout_i_0_i_a3_2))
+           (portRef B (instanceRef RDout_i_0_i_a3_5))
+           (portRef B (instanceRef RDout_i_0_i_a3_6))
+           (portRef B (instanceRef RDout_i_0_i_a3_7))
+           (portRef B (instanceRef RDout_i_i_a3_4))
+           (portRef B (instanceRef N_263_i))
+           (portRef A (instanceRef RDOE_i))
+           (portRef B (instanceRef LEDEN_RNI6G6M))
+          ))
+          (net LED_c (joined
+           (portRef Z (instanceRef LEDEN_RNI6G6M))
+           (portRef LED_c)
+          ))
+          (net (rename RDOE_i_1z "RDOE_i") (joined
+           (portRef Z (instanceRef RDOE_i))
+           (portRef RDOE_i_1z)
+          ))
+          (net N_866 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_6))
+           (portRef C (instanceRef nRAS_s_i_0_a3_0_RNIIR094))
+           (portRef A (instanceRef nRAS_s_i_0_a3_1))
+          ))
+          (net N_241_i (joined
+           (portRef Z (instanceRef wb_adr_RNO_2_1))
+           (portRef C (instanceRef wb_adr_RNO_0_1))
+          ))
+          (net (rename RA_0 "RA[0]") (joined
+           (portRef (member ra 11))
+           (portRef D (instanceRef RA_35_0_0_1_0))
+           (portRef A (instanceRef RWSel_2_0_a3_0_a3))
+          ))
+          (net nC07X_c (joined
+           (portRef nC07X_c)
+           (portRef C (instanceRef RWSel_2_0_a3_0_a3))
+          ))
+          (net RWSel_2 (joined
+           (portRef Z (instanceRef RWSel_2_0_a3_0_a3))
+           (portRef RWSel_2)
+          ))
+          (net (rename FS_7 "FS[7]") (joined
+           (portRef (member fs 8))
+           (portRef A (instanceRef RA_35_0_0_0))
+           (portRef D (instanceRef Ready3_0_a3_3))
+           (portRef C (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0))
+          ))
+          (net (rename un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0]") (joined
+           (portRef Z (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0))
+           (portRef D (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0))
+          ))
+          (net N_250 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_m3))
+           (portRef C (instanceRef nRAS_s_i_0_o2_0))
+          ))
+          (net (rename wb_dato_0 "wb_dato[0]") (joined
+           (portRef (member wb_dato 7) (instanceRef ufmefb))
+           (portRef C (instanceRef LEDEN_RNO))
+           (portRef C (instanceRef RWMask_RNO_0))
+          ))
+          (net (rename wb_dato_1 "wb_dato[1]") (joined
+           (portRef (member wb_dato 6) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_1))
+          ))
+          (net (rename wb_dato_2 "wb_dato[2]") (joined
+           (portRef (member wb_dato 5) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_2))
+          ))
+          (net (rename wb_dato_3 "wb_dato[3]") (joined
+           (portRef (member wb_dato 4) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_3))
+          ))
+          (net (rename wb_dato_4 "wb_dato[4]") (joined
+           (portRef (member wb_dato 3) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_4))
+          ))
+          (net (rename wb_dato_5 "wb_dato[5]") (joined
+           (portRef (member wb_dato 2) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_5))
+          ))
+          (net (rename wb_dato_6 "wb_dato[6]") (joined
+           (portRef (member wb_dato 1) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_6))
+          ))
+          (net (rename FS_2 "FS[2]") (joined
+           (portRef (member fs 13))
+           (portRef B (instanceRef nRWE_s_i_0_63_1))
+           (portRef B (instanceRef nRAS_s_i_0_m3))
+           (portRef A (instanceRef Ready3_0_a3_4))
+           (portRef B (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0))
+           (portRef B (instanceRef nCAS_s_i_0_m2))
+          ))
+          (net N_508 (joined
+           (portRef Z (instanceRef DQMH_4_iv_0_0_i_i_a3_0_a3))
+           (portRef N_508)
+          ))
+          (net N_814 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0))
+           (portRef A (instanceRef CmdExecMXO2_3_0_a3_0))
+          ))
+          (net (rename N_263_i_1z "N_263_i") (joined
+           (portRef Z (instanceRef N_263_i))
+           (portRef N_263_i_1z)
+          ))
+          (net (rename RWBank_7 "RWBank[7]") (joined
+           (portRef (member rwbank 0))
+           (portRef A (instanceRef RA_35_2_30_a3_2))
+          ))
+          (net (rename un9_VOEEN_0_a2_0_a3_0_a3_1z "un9_VOEEN_0_a2_0_a3_0_a3") (joined
+           (portRef Z (instanceRef un9_VOEEN_0_a2_0_a3_0_a3))
+           (portRef un9_VOEEN_0_a2_0_a3_0_a3_1z)
+          ))
+          (net Vout3 (joined
+           (portRef Z (instanceRef Vout3_0_a3_0_a3_0_a3))
+           (portRef Vout3)
+          ))
+          (net CmdLEDGet (joined
+           (portRef CmdLEDGet)
+           (portRef A (instanceRef RWBank_3_0_0_o3_0))
+          ))
+          (net CmdSetRWBankFFLED (joined
+           (portRef CmdSetRWBankFFLED)
+           (portRef C (instanceRef RWBank_3_0_0_o3_0))
+          ))
+          (net (rename wb_dato_7 "wb_dato[7]") (joined
+           (portRef (member wb_dato 0) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_7))
+          ))
+          (net N_648 (joined
+           (portRef Z (instanceRef RDout_i_i_a3_4))
+           (portRef N_648)
+          ))
+          (net N_662 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_7))
+           (portRef N_662)
+          ))
+          (net N_663 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_6))
+           (portRef N_663)
+          ))
+          (net N_664 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_5))
+           (portRef N_664)
+          ))
+          (net N_665 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_2))
+           (portRef N_665)
+          ))
+          (net N_666 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_1))
+           (portRef N_666)
+          ))
+          (net N_667 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_0))
+           (portRef N_667)
+          ))
+          (net (rename CmdTout_3_0 "CmdTout_3[0]") (joined
+           (portRef Z (instanceRef CmdTout_3_0_a3_0_a3_0))
+           (portRef CmdTout_3_0)
+          ))
+          (net N_821 (joined
+           (portRef Z (instanceRef RC_3_0_0_a3_1_1))
+           (portRef B (instanceRef CKE_7_bm))
+          ))
+          (net nRWE_s_i_0_63_1 (joined
+           (portRef Z (instanceRef nRWE_s_i_0_63_1))
+           (portRef D (instanceRef S_r_i_0_o2_RNI62C53_1))
+          ))
+          (net (rename S_r_i_0_o2_RNI62C53_1 "S_r_i_0_o2_RNI62C53[1]") (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNI62C53_1))
+           (portRef B (instanceRef nRAS_s_i_0_a3_0_RNIIR094))
+          ))
+          (net (rename wb_adr_7_i_i_3_1_0 "wb_adr_7_i_i_3_1[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_3_1_0))
+           (portRef D (instanceRef wb_adr_7_i_i_3_0))
+          ))
+          (net (rename Ain_c_0 "Ain_c[0]") (joined
+           (portRef (member ain_c 7))
+           (portRef A (instanceRef RA_35_0_0_1_0))
+          ))
+          (net (rename RA_35_0_0_1_0 "RA_35_0_0_1[0]") (joined
+           (portRef Z (instanceRef RA_35_0_0_1_0))
+           (portRef D (instanceRef RA_35_0_0_0))
+          ))
+          (net (rename RA_35_0 "RA_35[0]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0))
+           (portRef (member ra_35 11))
+          ))
+          (net CmdLEDSet_3 (joined
+           (portRef Z (instanceRef CmdLEDSet_3_0_a8_0_a3))
+           (portRef CmdLEDSet_3)
+          ))
+          (net CmdRWMaskSet_3 (joined
+           (portRef Z (instanceRef CmdRWMaskSet_3_0_a3))
+           (portRef CmdRWMaskSet_3)
+          ))
+          (net N_359_i (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_0_RNIIR094))
+           (portRef N_359_i)
+          ))
+         )
+        (property orig_inst_of (string "RAM2E_UFM"))
+       )
+    )
+    (cell RAM2E (cellType GENERIC)
+       (view verilog (viewType NETLIST)
+         (interface
+           (port C14M (direction INPUT))
+           (port PHI1 (direction INPUT))
+           (port LED (direction OUTPUT))
+           (port nWE (direction INPUT))
+           (port nWE80 (direction INPUT))
+           (port nEN80 (direction INPUT))
+           (port nC07X (direction INPUT))
+           (port (array (rename ain "Ain[7:0]") 8) (direction INPUT))
+           (port (array (rename din "Din[7:0]") 8) (direction INPUT))
+           (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT))
+           (port nDOE (direction OUTPUT))
+           (port (array (rename vout "Vout[7:0]") 8) (direction OUTPUT))
+           (port nVOE (direction OUTPUT))
+           (port CKEout (direction OUTPUT))
+           (port nCSout (direction OUTPUT))
+           (port nRASout (direction OUTPUT))
+           (port nCASout (direction OUTPUT))
+           (port nRWEout (direction OUTPUT))
+           (port (array (rename ba "BA[1:0]") 2) (direction OUTPUT))
+           (port (array (rename raout "RAout[11:0]") 12) (direction OUTPUT))
+           (port DQML (direction OUTPUT))
+           (port DQMH (direction OUTPUT))
+           (port (array (rename rd "RD[7:0]") 8) (direction INOUT))
+         )
+         (contents
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
+          )
+          (instance DOEEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !A+C (!B !A))"))
+          )
+          (instance VOEEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !A+C (!B !A))"))
+          )
+          (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance (rename nCASout_CN "nCASout.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance PHI1r_0io (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance nRWEout_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance nRASout_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance nCASout_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_0 "Vout_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_1 "Vout_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_2 "Vout_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_3 "Vout_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_4 "Vout_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_5 "Vout_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_6 "Vout_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_7 "Vout_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_0 "RAout_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_1 "RAout_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_2 "RAout_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_3 "RAout_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_4 "RAout_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_5 "RAout_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_6 "RAout_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_7 "RAout_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_8 "RAout_0io[8]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_9 "RAout_0io[9]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_10 "RAout_0io[10]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_11 "RAout_0io[11]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance DQML_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance DQMH_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance CKEout_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename BA_0io_0 "BA_0io[0]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename BA_0io_1 "BA_0io[1]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance nRWE (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nRAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nCAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance VOEEN (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename S_2 "S[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename S_3 "S[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RWSel (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
           (instance (rename RWBank_0 "RWBank[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
           (instance (rename RWBank_1 "RWBank[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
@@ -1053,11 +4193,35 @@
           )
           (instance (rename RWBank_7 "RWBank[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
+          (instance (rename RC_0 "RC[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RC_1 "RC[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RC_2 "RC[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
           (instance (rename RA_0 "RA[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
+          (instance (rename RA_1 "RA[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_2 "RA[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
           (instance (rename RA_3 "RA[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
-          (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          (instance (rename RA_4 "RA[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_5 "RA[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_6 "RA[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_7 "RA[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_8 "RA[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_9 "RA[9]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_10 "RA[10]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_11 "RA[11]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
           (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
           )
@@ -1091,7 +4255,7 @@
           )
           (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
           )
-          (instance DOEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          (instance DOEEN (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
           )
           (instance (rename CmdTout_0 "CmdTout[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
@@ -1099,8 +4263,6 @@
           )
           (instance (rename CmdTout_2 "CmdTout[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
-          (instance CmdSetRWBankFFMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
           (instance CmdSetRWBankFFLED (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
           (instance CmdRWMaskSet (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
@@ -1109,18 +4271,14 @@
           )
           (instance CmdLEDGet (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
-          (instance CmdExecMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdBitbangMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
           (instance (rename CS_0 "CS[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
           )
           (instance (rename CS_1 "CS[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
           )
           (instance (rename CS_2 "CS[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
           )
-          (instance DQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance DQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance CKE (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
           (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
           (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
           (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
@@ -1129,25 +4287,27 @@
           (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
           (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
           (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance DQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance DQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_11 "RAout_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_10 "RAout_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_9 "RAout_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_8 "RAout_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_7 "RAout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_6 "RAout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_5 "RAout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_4 "RAout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_3 "RAout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_2 "RAout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_1 "RAout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_0 "RAout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance (rename BA_pad_1 "BA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance (rename BA_pad_0 "BA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance CKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nRWEout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nCASout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nRASout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nCSout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance CKEout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance nVOE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance (rename Vout_pad_7 "Vout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance (rename Vout_pad_6 "Vout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
@@ -1184,573 +4344,17 @@
           (instance (rename Ain_pad_0 "Ain_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
           (instance nC07X_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
           (instance nEN80_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance nWE80_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
           (instance nWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
           (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance PHI1_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
           )
           (instance C14M_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance un1_CS_0_sqmuxa_0_0_2_RNIQS7F (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C !B)+D (!C (!B !A)))"))
-          )
-          (instance nCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C+(!B+A))+D A)"))
-          )
-          (instance nRWE_r_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C+(!B+A)))"))
-          )
-          (instance nCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance nRAS_2_iv_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A)+C !A)"))
-          )
-          (instance (rename wb_dati_7_0_5 "wb_dati_7_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C A+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_2 "wb_dati_7_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C A+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_7 "wb_dati_7_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance (rename wb_adr_7_0_0 "wb_adr_7_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C B+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_6 "wb_dati_7_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B A))"))
-          )
-          (instance (rename wb_dati_7_0_4 "wb_dati_7_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_3 "wb_dati_7_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+A))"))
-          )
-          (instance (rename RA_42_0_10 "RA_42_0[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C B+C (B+!A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D C+D (C+(B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance (rename CS_RNO_2 "CS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C (!B A+B !A))"))
-          )
-          (instance nCS_6_u_i_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_1 "wb_dati_7_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C A+C (B+A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D C+D (C+(B A)))"))
-          )
-          (instance (rename wb_dati_7_0_1_6 "wb_dati_7_0_1[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B+A)+D (C+(B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_2_3 "wb_dati_7_0_2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A))+D (B !A))"))
-          )
-          (instance (rename wb_adr_7_0_4_0 "wb_adr_7_0_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance (rename CS_RNO_0 "CS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A+B A)+C A)"))
-          )
-          (instance CmdSetRWBankFFLED_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance CmdExecMXO2_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D (C B))"))
-          )
-          (instance CmdRWMaskSet_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D (C B))"))
-          )
-          (instance CmdBitbangMXO2_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D (C B))"))
-          )
-          (instance CmdLEDSet_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename un1_LEDEN_0_sqmuxa_1_i_0_0 "un1_LEDEN_0_sqmuxa_1_i_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
-          )
-          (instance wb_cyc_stb_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C (B+A))"))
-          )
-          (instance (rename un1_RWMask_0_sqmuxa_1_i_0_0 "un1_RWMask_0_sqmuxa_1_i_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
-          )
-          (instance (rename wb_dati_7_0_0 "wb_dati_7_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
-          )
-          (instance (rename wb_adr_7_0_a2_0_0 "wb_adr_7_0_a2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B+A)+C B))"))
-          )
-          (instance (rename wb_dati_7_0_a2_4 "wb_dati_7_0_a2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A))+D (B !A))"))
-          )
-          (instance (rename wb_dati_7_0_RNO_7 "wb_dati_7_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D C)"))
-          )
-          (instance (rename wb_dati_7_0_a2_3_4 "wb_dati_7_0_a2_3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_7 "wb_dati_7_0_a2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)+C (B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B !A))"))
-          )
-          (instance (rename wb_dati_7_0_o2_0_2 "wb_dati_7_0_o2_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_0_3 "wb_dati_7_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
-          )
-          (instance (rename wb_dati_7_0_0_4 "wb_dati_7_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
-          )
-          (instance DQML_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B+!A)+D (!C !B+C (!B+!A)))"))
-          )
-          (instance CmdSetRWBankFFMXO2_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D (C B))"))
-          )
-          (instance CmdSetRWBankFFLED_4_u_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance CmdLEDGet_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D (C B))"))
-          )
-          (instance (rename wb_dati_7_0_a2_5_4 "wb_dati_7_0_a2_5[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B A))"))
-          )
-          (instance nCS_6_u_i_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance CKE_6_iv_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D A)"))
-          )
-          (instance wb_we_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C (B !A)))"))
-          )
-          (instance (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C B+C (B+A)))"))
-          )
-          (instance (rename wb_adr_7_0_a2_2_0 "wb_adr_7_0_a2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_6 "wb_dati_7_0_a2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A+B A)))"))
-          )
-          (instance (rename un1_LEDEN13_2_i_0_0 "un1_LEDEN13_2_i_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B+A)+D (C+(B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_1_7 "wb_dati_7_0_a2_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A)))"))
-          )
-          (instance (rename wb_adr_7_0_a2_1_0 "wb_adr_7_0_a2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B+!A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_1 "wb_dati_7_0_a2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance Ready_0_sqmuxa_0_a2_6_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance CmdLEDSet_4_u_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_4_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance (rename wb_dati_7_0_0_1 "wb_dati_7_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_0_7 "wb_dati_7_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
-          )
-          (instance (rename wb_adr_7_0_0_0 "wb_adr_7_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))"))
-          )
-          (instance (rename wb_adr_7_0_1_0 "wb_adr_7_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A))+D B)"))
-          )
-          (instance (rename S_RNO_2 "S_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)+C (B !A))+D (!C (!B !A)+C !A))"))
-          )
-          (instance (rename un1_LEDEN13_2_i_a2_0_0 "un1_LEDEN13_2_i_a2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D (C !B))"))
-          )
-          (instance (rename S_RNII9DO1_1_1 "S_RNII9DO1_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A+B A)+C (B A))+D (!C (!B A)+C B))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_1_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance (rename wb_adr_RNO_1_1 "wb_adr_RNO_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A))+D (!C A+C (!B A)))"))
-          )
-          (instance wb_we_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
-          )
-          (instance wb_we_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B+A)))"))
-          )
-          (instance CmdBitbangMXO2_RNI8CSO1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B+A)))"))
-          )
-          (instance (rename RA_0io_RNO_8 "RA_0io_RNO[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B !A)+D (C !A))"))
-          )
-          (instance (rename RA_0io_RNO_9 "RA_0io_RNO[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C !B+C (!B A)))"))
-          )
-          (instance (rename S_RNO_1 "S_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)+C !A))"))
-          )
-          (instance (rename S_RNO_3 "S_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D !A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C (!B A)))"))
-          )
-          (instance CmdSetRWBankFFLED_4_u_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance wb_req_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance CKE_6_iv_i_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B A)))"))
-          )
-          (instance (rename un1_LEDEN13_2_i_o2_2_0 "un1_LEDEN13_2_i_o2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance (rename S_s_0_0 "S_s_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C A+C (!B+A)))"))
-          )
-          (instance (rename CS_RNO_0_2 "CS_RNO_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance CKE_6_iv_i_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C B+C (!B A))+D (!C+(!B A)))"))
-          )
-          (instance Ready_0_sqmuxa_0_a2_6_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance nCS_6_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)+C (!B !A))+D (!C (!B A)))"))
-          )
-          (instance (rename wb_adr_7_0_a2_0_0_0 "wb_adr_7_0_a2_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D (!C (!B A)+C !B))"))
-          )
-          (instance (rename CmdTout_RNO_1 "CmdTout_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A+B !A))"))
-          )
-          (instance (rename RA_RNO_3 "RA_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_0io_RNO_4 "RA_0io_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_0io_RNO_6 "RA_0io_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_0io_RNO_7 "RA_0io_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_RNO_0 "RA_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_0io_RNO_1 "RA_0io_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_0io_RNO_2 "RA_0io_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B !A))"))
-          )
-          (instance (rename RWBank_5_0_4 "RWBank_5_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C+(!B+!A)))"))
-          )
-          (instance nCAS_s_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance (rename wb_dati_7_0_o2_1 "wb_dati_7_0_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D (!C (B A)))"))
-          )
-          (instance (rename RWBank_5_0_2 "RWBank_5_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename RWBank_5_0_3 "RWBank_5_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename RWBank_5_0_5 "RWBank_5_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename RWBank_5_0_6 "RWBank_5_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename RWBank_5_0_0_7 "RWBank_5_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C (B+A))"))
-          )
-          (instance (rename RWBank_5_0_1 "RWBank_5_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename RWBank_5_0_0 "RWBank_5_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance nRWE_r_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B A)+D (!C (!B A)+C !B))"))
-          )
-          (instance nDOE_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C+(B+!A))"))
-          )
-          (instance (rename RA_0io_RNO_11 "RA_0io_RNO[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
-          )
-          (instance RWSel_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)))"))
-          )
-          (instance wb_we_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
-          )
-          (instance nCS_6_u_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A)))"))
-          )
-          (instance (rename wb_adr_RNO_0_1 "wb_adr_RNO_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_15 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_1_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B !A)))"))
-          )
-          (instance (rename S_s_0_1_0 "S_s_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C !A)+D (!C !A+C (B+!A)))"))
-          )
-          (instance CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B !A))"))
-          )
-          (instance CmdLEDGet_4_u_0_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_2_0_1 "wb_dati_7_0_a2_2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance (rename un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0 "un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_1_0_0 "wb_dati_7_0_a2_1_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)+C (!B A)))"))
-          )
-          (instance (rename RWMask_RNO_6 "RWMask_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_5 "RWMask_RNO[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_4 "RWMask_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_3 "RWMask_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_2 "RWMask_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_1 "RWMask_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_0 "RWMask_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename un1_wb_adr_0_sqmuxa_2_0_1_0 "un1_wb_adr_0_sqmuxa_2_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+!A)+D (!C+!B))"))
-          )
-          (instance (rename wb_adr_RNO_2 "wb_adr_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename wb_adr_RNO_3 "wb_adr_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename wb_adr_RNO_7 "wb_adr_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance wb_req_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance (rename RA_42_i_o2_8 "RA_42_i_o2[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C+(B+A))"))
-          )
-          (instance nRAS_2_iv_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A)+C (!B !A))"))
-          )
-          (instance Vout3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A)))"))
-          )
-          (instance (rename RA_42_3_0_5 "RA_42_3_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B+A)+C A)"))
-          )
-          (instance (rename wb_dati_7_0_a2_0_2_7 "wb_dati_7_0_a2_0_2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B+!A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_0_0_6 "wb_dati_7_0_a2_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A))"))
-          )
-          (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+!A)"))
-          )
-          (instance nWE80_pad_RNI3ICD (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance (rename RWBank_5_0_o2_0 "RWBank_5_0_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+          (instance nVOE_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+A)"))
           )
           (instance (rename SZ0Z_1 "S_1") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(C (!B A))"))
           )
-          (instance un1_CS_0_sqmuxa_0_0_a2_1_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
-          )
-          (instance (rename wb_adr_7_0_a2_5_0_0 "wb_adr_7_0_a2_5_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A))"))
-          )
-          (instance CmdBitbangMXO2_4_u_0_0_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B !A))"))
-          )
-          (instance Ready_0_sqmuxa_0_a2_6_a2_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance nCS_6_u_i_a2_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)))"))
-          )
-          (instance (rename wb_adr_RNO_4 "wb_adr_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !B+C A)"))
-          )
-          (instance (rename wb_adr_RNO_6 "wb_adr_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !B+C A)"))
-          )
-          (instance (rename wb_adr_RNO_5 "wb_adr_RNO[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !B+C A)"))
-          )
-          (instance LEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C (!B+A))"))
-          )
-          (instance (rename RWMask_RNO_7 "RWMask_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C (!B+A))"))
-          )
-          (instance (rename CmdTout_3_0_a2_0 "CmdTout_3_0_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_12 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_13 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance nCS_6_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance (rename un1_LEDEN13_2_i_o2_0 "un1_LEDEN13_2_i_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance (rename wb_adr_7_0_o2_0 "wb_adr_7_0_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance (rename S_RNINI6S_1 "S_RNINI6S[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance (rename S_r_i_o2_1 "S_r_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance (rename FS_RNI9Q57_13 "FS_RNI9Q57[13]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+A)"))
-          )
-          (instance (rename wb_adr_7_0_o2_2_0 "wb_adr_7_0_o2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance (rename FS_RNIJ9MH_14 "FS_RNIJ9MH[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance (rename wb_dati_7_0_a2_1_0 "wb_dati_7_0_a2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance wb_rst8_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance wb_reqc_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance CmdBitbangMXO2_4_u_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_16 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_17 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance un1_nCS61_1_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
-          )
-          (instance (rename FS_RNI6JJA_8 "FS_RNI6JJA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C+(!B+!A))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance (rename CS_RNO_1 "CS_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C (!B !A+B A)+C A))"))
-          )
-          (instance (rename wb_dati_7_0_a2_5_1 "wb_dati_7_0_a2_5[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B !A))"))
-          )
-          (instance nCS_6_u_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(!B !A)))"))
-          )
-          (instance (rename un1_LEDEN13_2_i_a2_0 "un1_LEDEN13_2_i_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_2_0 "wb_dati_7_0_a2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B !A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_6_1 "wb_dati_7_0_a2_6[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A))"))
-          )
           (instance (rename FS_s_0_15 "FS_s_0[15]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
            (property INIT0 (string "0x5002"))
            (property INJECT1_1 (string "NO"))
@@ -1805,674 +4409,206 @@
            (property INJECT1_0 (string "NO"))
            (property INIT1 (string "0x300A"))
           )
-          (instance ufmefb (viewRef netlist (cellRef REFB))
+          (instance ram2e_ufm (viewRef netlist (cellRef RAM2E_UFM))
           )
-          (net wb_rst (joined
-           (portRef Q (instanceRef wb_rst))
-           (portRef wb_rst (instanceRef ufmefb))
-          ))
-          (net wb_cyc_stb (joined
-           (portRef Q (instanceRef wb_cyc_stb))
-           (portRef wb_cyc_stb (instanceRef ufmefb))
-          ))
-          (net wb_we (joined
-           (portRef Q (instanceRef wb_we))
-           (portRef wb_we (instanceRef ufmefb))
-          ))
-          (net (rename wb_adr_0 "wb_adr[0]") (joined
-           (portRef Q (instanceRef wb_adr_0))
-           (portRef (member wb_adr 7) (instanceRef ufmefb))
-           (portRef C (instanceRef wb_dati_7_0_0))
-          ))
-          (net (rename wb_adr_1 "wb_adr[1]") (joined
-           (portRef Q (instanceRef wb_adr_1))
-           (portRef (member wb_adr 6) (instanceRef ufmefb))
-           (portRef C (instanceRef wb_dati_7_0_0_1))
-          ))
-          (net (rename wb_adr_2 "wb_adr[2]") (joined
-           (portRef Q (instanceRef wb_adr_2))
-           (portRef (member wb_adr 5) (instanceRef ufmefb))
-           (portRef C (instanceRef wb_dati_7_0_2))
-          ))
-          (net (rename wb_adr_3 "wb_adr[3]") (joined
-           (portRef Q (instanceRef wb_adr_3))
-           (portRef (member wb_adr 4) (instanceRef ufmefb))
-           (portRef D (instanceRef wb_dati_7_0_0_3))
-          ))
-          (net (rename wb_adr_4 "wb_adr[4]") (joined
-           (portRef Q (instanceRef wb_adr_4))
-           (portRef (member wb_adr 3) (instanceRef ufmefb))
-           (portRef D (instanceRef wb_dati_7_0_0_4))
-          ))
-          (net (rename wb_adr_5 "wb_adr[5]") (joined
-           (portRef Q (instanceRef wb_adr_5))
-           (portRef (member wb_adr 2) (instanceRef ufmefb))
-           (portRef C (instanceRef wb_dati_7_0_5))
-          ))
-          (net (rename wb_adr_6 "wb_adr[6]") (joined
-           (portRef Q (instanceRef wb_adr_6))
-           (portRef (member wb_adr 1) (instanceRef ufmefb))
-           (portRef D (instanceRef wb_dati_7_0_1_6))
-          ))
-          (net (rename wb_adr_7 "wb_adr[7]") (joined
-           (portRef Q (instanceRef wb_adr_7))
-           (portRef (member wb_adr 0) (instanceRef ufmefb))
-           (portRef C (instanceRef wb_dati_7_0_0_7))
-          ))
-          (net (rename wb_dati_0 "wb_dati[0]") (joined
-           (portRef Q (instanceRef wb_dati_0))
-           (portRef (member wb_dati 7) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_1 "wb_dati[1]") (joined
-           (portRef Q (instanceRef wb_dati_1))
-           (portRef (member wb_dati 6) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_2 "wb_dati[2]") (joined
-           (portRef Q (instanceRef wb_dati_2))
-           (portRef (member wb_dati 5) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_3 "wb_dati[3]") (joined
-           (portRef Q (instanceRef wb_dati_3))
-           (portRef (member wb_dati 4) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_4 "wb_dati[4]") (joined
-           (portRef Q (instanceRef wb_dati_4))
-           (portRef (member wb_dati 3) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_5 "wb_dati[5]") (joined
-           (portRef Q (instanceRef wb_dati_5))
-           (portRef (member wb_dati 2) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_6 "wb_dati[6]") (joined
-           (portRef Q (instanceRef wb_dati_6))
-           (portRef (member wb_dati 1) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_7 "wb_dati[7]") (joined
-           (portRef Q (instanceRef wb_dati_7))
-           (portRef (member wb_dati 0) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dato_0 "wb_dato[0]") (joined
-           (portRef (member wb_dato 7) (instanceRef ufmefb))
-           (portRef C (instanceRef LEDEN_RNO))
-           (portRef C (instanceRef RWMask_RNO_0))
-          ))
-          (net (rename wb_dato_1 "wb_dato[1]") (joined
-           (portRef (member wb_dato 6) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_1))
-          ))
-          (net (rename wb_dato_2 "wb_dato[2]") (joined
-           (portRef (member wb_dato 5) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_2))
-          ))
-          (net (rename wb_dato_3 "wb_dato[3]") (joined
-           (portRef (member wb_dato 4) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_3))
-          ))
-          (net (rename wb_dato_4 "wb_dato[4]") (joined
-           (portRef (member wb_dato 3) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_4))
-          ))
-          (net (rename wb_dato_5 "wb_dato[5]") (joined
-           (portRef (member wb_dato 2) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_5))
-          ))
-          (net (rename wb_dato_6 "wb_dato[6]") (joined
-           (portRef (member wb_dato 1) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_6))
-          ))
-          (net (rename wb_dato_7 "wb_dato[7]") (joined
-           (portRef (member wb_dato 0) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_7))
-          ))
-          (net wb_ack (joined
-           (portRef wb_ack (instanceRef ufmefb))
-           (portRef A (instanceRef un1_LEDEN13_2_i_a2_0))
-           (portRef B (instanceRef un1_LEDEN13_2_i_o2_0))
-           (portRef D (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0))
-           (portRef C (instanceRef wb_cyc_stb_RNO_0))
-           (portRef A (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0))
-          ))
-          (net (rename S_2 "S[2]") (joined
-           (portRef Q (instanceRef S_2))
-           (portRef B (instanceRef FS_RNIJ9MH_14))
-           (portRef A (instanceRef S_r_i_o2_1))
-           (portRef C (instanceRef wb_adr_RNO_5))
-           (portRef C (instanceRef wb_adr_RNO_6))
-           (portRef C (instanceRef wb_adr_RNO_4))
-           (portRef C (instanceRef nCS_6_u_i_a2_1_0))
-           (portRef C (instanceRef Vout3_0_a2))
-           (portRef B (instanceRef nRAS_2_iv_0_a2_0))
-           (portRef B (instanceRef RA_42_i_o2_8))
-           (portRef B (instanceRef wb_adr_RNO_7))
-           (portRef B (instanceRef wb_adr_RNO_3))
-           (portRef B (instanceRef wb_adr_RNO_2))
-           (portRef C (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0))
-           (portRef C (instanceRef S_s_0_1_0))
-           (portRef B (instanceRef RA_0io_RNO_11))
-           (portRef B (instanceRef nCS_6_u_i_0))
-           (portRef B (instanceRef CKE_6_iv_i_0_1))
-           (portRef C (instanceRef S_RNO_3))
-           (portRef B (instanceRef RA_0io_RNO_9))
-           (portRef B (instanceRef CmdBitbangMXO2_RNI8CSO1))
-           (portRef B (instanceRef wb_we_RNO_0))
-           (portRef D (instanceRef wb_we_RNO_2))
-           (portRef C (instanceRef S_RNII9DO1_1_1))
-           (portRef C (instanceRef S_RNO_2))
-           (portRef C (instanceRef wb_adr_7_0_0_0))
-           (portRef B (instanceRef wb_dati_7_0_0_7))
-           (portRef B (instanceRef wb_dati_7_0_0_1))
-           (portRef C (instanceRef wb_adr_RNO_1))
-           (portRef C (instanceRef wb_dati_7_0_0_4))
-           (portRef C (instanceRef wb_dati_7_0_0_3))
-           (portRef B (instanceRef wb_dati_7_0_0))
-           (portRef C (instanceRef wb_dati_7_0_1_6))
-           (portRef B (instanceRef wb_dati_7_0_2))
-           (portRef B (instanceRef wb_dati_7_0_5))
-           (portRef CD (instanceRef wb_req))
-           (portRef C (instanceRef wb_reqc_1_RNIEO5C1))
-           (portRef D (instanceRef wb_req_RNO_0))
-           (portRef B (instanceRef DOEEN_RNO))
-           (portRef C (instanceRef BA_0io_RNO_1))
-           (portRef C (instanceRef BA_0io_RNO_0))
-           (portRef D (instanceRef FS_RNI5OOF1_15))
-           (portRef C (instanceRef S_RNII9DO1_3_1))
-           (portRef C (instanceRef RA_42_0_RNO_10))
-           (portRef B (instanceRef wb_reqc_1_RNIRU4M1))
-           (portRef B (instanceRef S_RNII9DO1_1))
-           (portRef B (instanceRef DQML_0io_RNO_0))
-           (portRef A (instanceRef S_RNII9DO1_0_1))
-           (portRef B (instanceRef S_RNII9DO1_2_1))
-          ))
-          (net RWSel (joined
-           (portRef Q (instanceRef RWSel))
-           (portRef C (instanceRef un1_LEDEN13_2_i_a2_0))
-           (portRef B (instanceRef CmdTout_3_0_a2_0))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_7))
-           (portRef B (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_5))
-           (portRef C (instanceRef CmdTout_RNO_1))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_2))
-           (portRef D (instanceRef CmdLEDGet_4_u_0_0_0))
-           (portRef D (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_1))
-           (portRef C (instanceRef CmdLEDSet_4_u_0_0_0))
-           (portRef D (instanceRef CmdBitbangMXO2_4_u_0_0_0))
-           (portRef D (instanceRef CmdRWMaskSet_4_u_0_0_0))
-           (portRef D (instanceRef CmdExecMXO2_4_u_0_0_0))
-           (portRef C (instanceRef CmdSetRWBankFFLED_4_u_0_0_0))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_0))
-           (portRef D (instanceRef CmdTout_RNO_2))
-           (portRef A (instanceRef wb_reqc_1_RNIRU4M1))
+          (net un9_VOEEN_0_a2_0_a3_0_a3 (joined
+           (portRef un9_VOEEN_0_a2_0_a3_0_a3_1z (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef RWSel))
           ))
           (net (rename S_0 "S[0]") (joined
            (portRef Q (instanceRef S_0))
-           (portRef A (instanceRef wb_reqc_1))
-           (portRef A (instanceRef S_RNINI6S_1))
-           (portRef B (instanceRef nCS_6_u_i_a2_1_0))
-           (portRef B (instanceRef RA_42_3_0_5))
-           (portRef A (instanceRef Vout3_0_a2))
-           (portRef A (instanceRef S_s_0_1_0))
-           (portRef B (instanceRef nCS_6_u_i_a2_0))
-           (portRef C (instanceRef nRWE_r_0))
-           (portRef B (instanceRef RA_0io_RNO_2))
-           (portRef B (instanceRef RA_0io_RNO_1))
-           (portRef B (instanceRef RA_RNO_0))
-           (portRef B (instanceRef RA_0io_RNO_7))
-           (portRef B (instanceRef RA_0io_RNO_6))
-           (portRef B (instanceRef RA_0io_RNO_4))
-           (portRef B (instanceRef RA_RNO_3))
-           (portRef B (instanceRef S_s_0_0))
-           (portRef D (instanceRef RA_0io_RNO_8))
-           (portRef A (instanceRef S_RNII9DO1_1_1))
-           (portRef C (instanceRef nRAS_2_iv_i))
-           (portRef C (instanceRef DQMH_0io_RNO))
-           (portRef D (instanceRef DOEEN_RNO))
-           (portRef C (instanceRef nCAS_0io_RNO_0))
-           (portRef A (instanceRef S_RNII9DO1_3_1))
-           (portRef A (instanceRef RA_42_0_RNO_10))
-           (portRef D (instanceRef S_RNII9DO1_1))
-           (portRef C (instanceRef CKE_6_iv_i_0_1_RNO))
-           (portRef D (instanceRef DQML_0io_RNO_0))
-           (portRef D (instanceRef S_RNII9DO1_0_1))
-           (portRef D (instanceRef S_RNII9DO1_2_1))
+           (portRef (member s 3) (instanceRef ram2e_ufm))
+           (portRef C (instanceRef VOEEN_RNO))
+           (portRef C (instanceRef DOEEN_RNO))
           ))
           (net (rename S_1 "S[1]") (joined
            (portRef Q (instanceRef S_1))
-           (portRef B (instanceRef wb_reqc_1))
-           (portRef B (instanceRef S_RNINI6S_1))
-           (portRef B (instanceRef Vout3_0_a2))
-           (portRef A (instanceRef nRAS_2_iv_0_a2_0))
-           (portRef A (instanceRef RA_42_i_o2_8))
-           (portRef B (instanceRef S_s_0_1_0))
-           (portRef C (instanceRef nCS_6_u_i_a2_0))
-           (portRef A (instanceRef nCS_6_u_i_0))
-           (portRef C (instanceRef S_s_0_0))
-           (portRef B (instanceRef S_RNII9DO1_1_1))
-           (portRef C (instanceRef DOEEN_RNO))
-           (portRef D (instanceRef BA_0io_RNO_1))
-           (portRef D (instanceRef BA_0io_RNO_0))
-           (portRef D (instanceRef S_RNII9DO1_3_1))
-           (portRef D (instanceRef RA_42_0_RNO_10))
-           (portRef C (instanceRef S_RNII9DO1_1))
-           (portRef B (instanceRef CKE_6_iv_i_0_1_RNO))
-           (portRef C (instanceRef DQML_0io_RNO_0))
-           (portRef C (instanceRef S_RNII9DO1_0_1))
-           (portRef C (instanceRef S_RNII9DO1_2_1))
+           (portRef (member s 2) (instanceRef ram2e_ufm))
+           (portRef B (instanceRef VOEEN_RNO))
+           (portRef B (instanceRef DOEEN_RNO))
+          ))
+          (net (rename S_2 "S[2]") (joined
+           (portRef Q (instanceRef S_2))
+           (portRef (member s 1) (instanceRef ram2e_ufm))
+           (portRef A (instanceRef DOEEN_RNO))
           ))
           (net (rename S_3 "S[3]") (joined
            (portRef Q (instanceRef S_3))
-           (portRef B (instanceRef S_r_i_o2_1))
-           (portRef B (instanceRef RWMask_RNO_7))
-           (portRef B (instanceRef LEDEN_RNO))
-           (portRef D (instanceRef nCS_6_u_i_a2_1_0))
-           (portRef C (instanceRef RA_42_3_0_5))
-           (portRef D (instanceRef Vout3_0_a2))
-           (portRef C (instanceRef nRAS_2_iv_0_a2_0))
-           (portRef C (instanceRef RA_42_i_o2_8))
-           (portRef D (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0))
-           (portRef B (instanceRef RWMask_RNO_0))
-           (portRef B (instanceRef RWMask_RNO_1))
-           (portRef B (instanceRef RWMask_RNO_2))
-           (portRef B (instanceRef RWMask_RNO_3))
-           (portRef B (instanceRef RWMask_RNO_4))
-           (portRef B (instanceRef RWMask_RNO_5))
-           (portRef B (instanceRef RWMask_RNO_6))
-           (portRef D (instanceRef S_s_0_1_0))
-           (portRef D (instanceRef nCS_6_u_i_a2_0))
-           (portRef C (instanceRef RA_0io_RNO_11))
-           (portRef C (instanceRef RA_0io_RNO_2))
-           (portRef C (instanceRef RA_0io_RNO_1))
-           (portRef C (instanceRef RA_RNO_0))
-           (portRef C (instanceRef RA_0io_RNO_7))
-           (portRef C (instanceRef RA_0io_RNO_6))
-           (portRef C (instanceRef RA_0io_RNO_4))
-           (portRef C (instanceRef RA_RNO_3))
-           (portRef C (instanceRef nCS_6_u_i_0))
-           (portRef C (instanceRef CKE_6_iv_i_0_1))
-           (portRef C (instanceRef wb_req_RNO))
-           (portRef D (instanceRef S_RNO_3))
-           (portRef C (instanceRef RA_0io_RNO_9))
-           (portRef D (instanceRef S_RNII9DO1_1_1))
-           (portRef D (instanceRef S_RNO_2))
-           (portRef D (instanceRef CKE_6_iv_i_0))
-           (portRef C (instanceRef wb_cyc_stb_RNO))
-           (portRef B (instanceRef wb_reqc_1_RNIEO5C1))
-           (portRef C (instanceRef wb_req_RNO_0))
-           (portRef A (instanceRef DOEEN_RNO))
-           (portRef B (instanceRef BA_0io_RNO_1))
-           (portRef B (instanceRef BA_0io_RNO_0))
-           (portRef C (instanceRef FS_RNI5OOF1_15))
-           (portRef B (instanceRef S_RNII9DO1_3_1))
-           (portRef B (instanceRef RA_42_0_RNO_10))
-           (portRef C (instanceRef wb_reqc_1_RNIRU4M1))
-           (portRef A (instanceRef S_RNII9DO1_1))
-           (portRef A (instanceRef DQML_0io_RNO_0))
-           (portRef B (instanceRef S_RNII9DO1_0_1))
-           (portRef A (instanceRef S_RNII9DO1_2_1))
+           (portRef (member s 0) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef DOEEN))
+           (portRef A (instanceRef VOEEN_RNO))
           ))
           (net (rename FS_0 "FS[0]") (joined
            (portRef Q (instanceRef FS_0))
+           (portRef (member fs 15) (instanceRef ram2e_ufm))
            (portRef A1 (instanceRef FS_cry_0_0))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0))
-           (portRef A (instanceRef un1_LEDEN13_2_i_a2_0_0))
-           (portRef A (instanceRef nCS_6_u_i_a2_4))
-           (portRef B (instanceRef wb_cyc_stb_RNO_0))
-          ))
-          (net (rename FS_8 "FS[8]") (joined
-           (portRef Q (instanceRef FS_8))
-           (portRef A1 (instanceRef FS_cry_0_7))
-           (portRef A (instanceRef wb_dati_7_0_a2_2_0))
-           (portRef C (instanceRef FS_RNI6JJA_8))
-           (portRef A (instanceRef wb_adr_7_0_o2_2_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_0_0_6))
-           (portRef A (instanceRef wb_dati_7_0_a2_0_2_7))
-           (portRef A (instanceRef wb_adr_7_0_1_0))
-           (portRef A (instanceRef wb_adr_7_0_a2_2_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_3_4))
-           (portRef D (instanceRef wb_we_RNO_1))
-           (portRef D (instanceRef FS_RNIOD6E_8))
-           (portRef B (instanceRef FS_RNIOD6E_0_8))
-           (portRef C (instanceRef wb_adr_RNO_2_1))
-           (portRef B (instanceRef FS_RNIOD6E_1_8))
-           (portRef B (instanceRef wb_dati_7_0_2_RNO_3))
-          ))
-          (net (rename FS_9 "FS[9]") (joined
-           (portRef Q (instanceRef FS_9))
-           (portRef A0 (instanceRef FS_cry_0_9))
-           (portRef B (instanceRef FS_RNI6JJA_8))
-           (portRef B (instanceRef wb_adr_7_0_o2_2_0))
-           (portRef A (instanceRef wb_adr_7_0_a2_5_0_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_0_0_6))
-           (portRef B (instanceRef wb_dati_7_0_a2_0_2_7))
-           (portRef A (instanceRef wb_dati_7_0_a2_1_0_0))
-           (portRef A (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0))
-           (portRef A (instanceRef wb_dati_7_0_o2_1))
-           (portRef A (instanceRef wb_dati_7_0_a2_1_7))
-           (portRef B (instanceRef wb_adr_7_0_a2_2_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_5_4))
-           (portRef B (instanceRef wb_dati_7_0_a2_3_4))
-           (portRef A (instanceRef wb_dati_7_0_RNO_7))
-           (portRef A (instanceRef wb_adr_7_0_a2_0_0))
-           (portRef C (instanceRef wb_we_RNO_1))
-           (portRef C (instanceRef FS_RNIOD6E_8))
-           (portRef C (instanceRef FS_RNIOD6E_0_8))
-           (portRef B (instanceRef wb_adr_RNO_2_1))
-           (portRef A (instanceRef FS_RNIOD6E_1_8))
-           (portRef A (instanceRef wb_dati_7_0_2_RNO_3))
-          ))
-          (net (rename FS_10 "FS[10]") (joined
-           (portRef Q (instanceRef FS_10))
-           (portRef A1 (instanceRef FS_cry_0_9))
-           (portRef A (instanceRef wb_dati_7_0_a2_1_0))
-           (portRef A (instanceRef wb_adr_7_0_o2_0))
-           (portRef B (instanceRef wb_adr_7_0_a2_5_0_0))
-           (portRef C (instanceRef wb_dati_7_0_a2_0_2_7))
-           (portRef A (instanceRef wb_we_RNO_4))
-           (portRef B (instanceRef wb_dati_7_0_o2_1))
-           (portRef A (instanceRef wb_dati_7_0_a2_6))
-           (portRef A (instanceRef wb_dati_7_0_a2_7))
-           (portRef B (instanceRef wb_adr_7_0_a2_0_0))
-           (portRef D (instanceRef wb_dati_7_0_a2_5_RNIC22J_4))
-           (portRef B (instanceRef wb_we_RNO_1))
-           (portRef B (instanceRef FS_RNIOD6E_8))
-           (portRef A (instanceRef FS_RNIOD6E_0_8))
-           (portRef D (instanceRef wb_dati_7_0_0_RNO_7))
-           (portRef D (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0))
-           (portRef A (instanceRef wb_adr_RNO_2_1))
-           (portRef D (instanceRef FS_RNIOD6E_1_8))
-           (portRef C (instanceRef wb_adr_RNO_3_1))
-           (portRef D (instanceRef wb_dati_7_0_2_RNO_3))
-          ))
-          (net (rename FS_11 "FS[11]") (joined
-           (portRef Q (instanceRef FS_11))
-           (portRef A0 (instanceRef FS_cry_0_11))
-           (portRef A (instanceRef FS_RNI6JJA_8))
-           (portRef B (instanceRef wb_adr_7_0_o2_0))
-           (portRef C (instanceRef wb_dati_7_0_a2_0_0_6))
-           (portRef D (instanceRef wb_dati_7_0_a2_0_2_7))
-           (portRef A (instanceRef wb_req_RNO_1))
-           (portRef B (instanceRef wb_dati_7_0_a2_1_0_0))
-           (portRef A (instanceRef wb_adr_RNO_0_1))
-           (portRef C (instanceRef wb_dati_7_0_o2_1))
-           (portRef A (instanceRef wb_adr_7_0_a2_0_0_0))
-           (portRef A (instanceRef wb_adr_7_0_a2_1_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_5_4))
-           (portRef C (instanceRef wb_dati_7_0_a2_3_4))
-           (portRef C (instanceRef wb_adr_7_0_a2_0_0))
-           (portRef A (instanceRef FS_RNIOD6E_8))
-           (portRef D (instanceRef FS_RNIOD6E_0_8))
-           (portRef B (instanceRef wb_we_RNO_3))
-           (portRef C (instanceRef FS_RNIOD6E_1_8))
-           (portRef C (instanceRef wb_dati_7_0_2_RNO_3))
-          ))
-          (net (rename FS_12 "FS[12]") (joined
-           (portRef Q (instanceRef FS_12))
-           (portRef A1 (instanceRef FS_cry_0_11))
-           (portRef A (instanceRef wb_dati_7_0_a2_6_1))
-           (portRef B (instanceRef wb_dati_7_0_a2_1_0))
-           (portRef A (instanceRef FS_RNI9Q57_13))
-           (portRef C (instanceRef wb_adr_7_0_a2_5_0_0))
-           (portRef B (instanceRef wb_req_RNO_1))
-           (portRef A (instanceRef wb_dati_7_0_a2_2_0_1))
-           (portRef B (instanceRef wb_adr_RNO_0_1))
-           (portRef B (instanceRef wb_we_RNO_4))
-           (portRef B (instanceRef wb_adr_7_0_a2_0_0_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_1))
-           (portRef B (instanceRef wb_adr_7_0_a2_1_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_6))
-           (portRef B (instanceRef wb_dati_7_0_a2_7))
-           (portRef A (instanceRef wb_dati_7_0_a2_4))
-           (portRef A (instanceRef wb_dati_7_0_2_3))
-           (portRef C (instanceRef wb_dati_7_0_a2_5_RNIC22J_4))
-           (portRef A (instanceRef wb_we_RNO_1))
-           (portRef D (instanceRef wb_we_RNO_3))
-           (portRef C (instanceRef wb_dati_7_0_0_RNO_7))
-           (portRef C (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0))
-           (portRef B (instanceRef wb_adr_RNO_3_1))
-          ))
-          (net (rename FS_13 "FS[13]") (joined
-           (portRef Q (instanceRef FS_13))
-           (portRef A0 (instanceRef FS_cry_0_13))
-           (portRef C (instanceRef wb_dati_7_0_a2_6_1))
-           (portRef B (instanceRef FS_RNI9Q57_13))
-           (portRef C (instanceRef wb_req_RNO_1))
-           (portRef C (instanceRef wb_dati_7_0_a2_1_0_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_2_0_1))
-           (portRef D (instanceRef wb_dati_7_0_o2_1))
-           (portRef C (instanceRef wb_adr_7_0_a2_0_0_0))
-           (portRef A (instanceRef CKE_6_iv_i_a2_3))
-           (portRef A (instanceRef wb_we_RNO))
-           (portRef C (instanceRef wb_dati_7_0_a2_7))
-           (portRef A (instanceRef wb_adr_7_0_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_5_RNIC22J_4))
-           (portRef A (instanceRef FS_RNIK5632_15))
-           (portRef C (instanceRef wb_we_RNO_3))
-           (portRef B (instanceRef wb_dati_7_0_0_RNO_7))
-           (portRef A (instanceRef wb_adr_RNO_3_1))
-          ))
-          (net (rename FS_15 "FS[15]") (joined
-           (portRef Q (instanceRef FS_15))
-           (portRef A0 (instanceRef FS_s_0_15))
-           (portRef B (instanceRef wb_dati_7_0_a2_2_0))
-           (portRef C (instanceRef wb_dati_7_0_a2_5_1))
-           (portRef B (instanceRef wb_rst8_0_a2))
-           (portRef A (instanceRef nCS_6_u_i_a2_1_0))
-           (portRef A (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0))
-           (portRef B (instanceRef CKE_6_iv_i_0))
-           (portRef C (instanceRef nCS_6_u_i_a2_4_RNI3A062))
-           (portRef B (instanceRef FS_RNIK5632_15))
-           (portRef A (instanceRef wb_req_RNO_0))
-           (portRef A (instanceRef FS_RNI5OOF1_15))
-          ))
-          (net PHI1reg (joined
-           (portRef Q (instanceRef PHI1reg_0io))
-           (portRef B (instanceRef SZ0Z_1))
-          ))
-          (net (rename FS_14 "FS[14]") (joined
-           (portRef Q (instanceRef FS_14))
-           (portRef A1 (instanceRef FS_cry_0_13))
-           (portRef D (instanceRef wb_dati_7_0_a2_2_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_5_1))
-           (portRef A (instanceRef wb_rst8_0_a2))
-           (portRef A (instanceRef FS_RNIJ9MH_14))
-           (portRef A (instanceRef un1_LEDEN13_2_i_o2_0))
-           (portRef B (instanceRef wb_adr_RNO_5))
-           (portRef B (instanceRef wb_adr_RNO_6))
-           (portRef B (instanceRef wb_adr_RNO_4))
-           (portRef B (instanceRef CKE_6_iv_i_a2_3))
-           (portRef A (instanceRef wb_req_RNO))
-           (portRef D (instanceRef wb_cyc_stb_RNO_0))
-           (portRef D (instanceRef FS_RNIK5632_15))
-          ))
-          (net (rename FS_6 "FS[6]") (joined
-           (portRef Q (instanceRef FS_6))
-           (portRef A1 (instanceRef FS_cry_0_5))
-           (portRef A (instanceRef un1_LEDEN13_2_i_o2_2_0))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a2_6_a2))
-           (portRef B (instanceRef nCS_6_u_i_a2_4))
-          ))
-          (net (rename FS_2 "FS[2]") (joined
-           (portRef Q (instanceRef FS_2))
-           (portRef A1 (instanceRef FS_cry_0_1))
-           (portRef C (instanceRef un1_nCS61_1_0_a2_0))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0))
-           (portRef B (instanceRef FS_RNI9FGA_1))
           ))
           (net (rename FS_1 "FS[1]") (joined
            (portRef Q (instanceRef FS_1))
+           (portRef (member fs 14) (instanceRef ram2e_ufm))
            (portRef A0 (instanceRef FS_cry_0_1))
-           (portRef D (instanceRef un1_nCS61_1_0_a2_0))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0))
-           (portRef C (instanceRef FS_RNI9FGA_1))
+          ))
+          (net (rename FS_2 "FS[2]") (joined
+           (portRef Q (instanceRef FS_2))
+           (portRef (member fs 13) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_1))
           ))
           (net (rename FS_3 "FS[3]") (joined
            (portRef Q (instanceRef FS_3))
+           (portRef (member fs 12) (instanceRef ram2e_ufm))
            (portRef A0 (instanceRef FS_cry_0_3))
-           (portRef B (instanceRef un1_nCS61_1_0_a2_0))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4))
-           (portRef A (instanceRef FS_RNI9FGA_1))
-          ))
-          (net (rename FS_7 "FS[7]") (joined
-           (portRef Q (instanceRef FS_7))
-           (portRef A0 (instanceRef FS_cry_0_7))
-           (portRef B (instanceRef un1_LEDEN13_2_i_o2_2_0))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a2_6_a2))
-           (portRef C (instanceRef nCS_6_u_i_a2_4))
-          ))
-          (net (rename FS_5 "FS[5]") (joined
-           (portRef Q (instanceRef FS_5))
-           (portRef A0 (instanceRef FS_cry_0_5))
-           (portRef B (instanceRef nCS_6_u_i_o2))
-           (portRef A (instanceRef un1_nCS61_1_0_a2_0))
-           (portRef B (instanceRef nCS_6_u_i_o2_0))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4))
           ))
           (net (rename FS_4 "FS[4]") (joined
            (portRef Q (instanceRef FS_4))
+           (portRef (member fs 11) (instanceRef ram2e_ufm))
            (portRef A1 (instanceRef FS_cry_0_3))
-           (portRef D (instanceRef nCS_6_u_i_o2))
-           (portRef A (instanceRef nCS_6_u_i_o2_0))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0))
-           (portRef A (instanceRef nCAS_s_i_o2))
-           (portRef A (instanceRef nRWE_r_0_RNO))
           ))
-          (net (rename RWBank_6 "RWBank[6]") (joined
-           (portRef Q (instanceRef RWBank_6))
-           (portRef C (instanceRef DQML_0io_RNO))
-           (portRef A (instanceRef DQMH_0io_RNO))
+          (net (rename FS_5 "FS[5]") (joined
+           (portRef Q (instanceRef FS_5))
+           (portRef (member fs 10) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_cry_0_5))
           ))
-          (net (rename RWMask_0 "RWMask[0]") (joined
-           (portRef Q (instanceRef RWMask_0))
-           (portRef C (instanceRef RWBank_5_0_0))
+          (net (rename FS_6 "FS[6]") (joined
+           (portRef Q (instanceRef FS_6))
+           (portRef (member fs 9) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_5))
           ))
-          (net (rename RWMask_1 "RWMask[1]") (joined
-           (portRef Q (instanceRef RWMask_1))
-           (portRef C (instanceRef RWBank_5_0_1))
+          (net (rename FS_7 "FS[7]") (joined
+           (portRef Q (instanceRef FS_7))
+           (portRef (member fs 8) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_cry_0_7))
           ))
-          (net (rename RWMask_2 "RWMask[2]") (joined
-           (portRef Q (instanceRef RWMask_2))
-           (portRef C (instanceRef RWBank_5_0_2))
+          (net (rename FS_8 "FS[8]") (joined
+           (portRef Q (instanceRef FS_8))
+           (portRef (member fs 7) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_7))
           ))
-          (net (rename RWMask_3 "RWMask[3]") (joined
-           (portRef Q (instanceRef RWMask_3))
-           (portRef C (instanceRef RWBank_5_0_3))
+          (net (rename FS_9 "FS[9]") (joined
+           (portRef Q (instanceRef FS_9))
+           (portRef (member fs 6) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_cry_0_9))
           ))
-          (net (rename RWMask_4 "RWMask[4]") (joined
-           (portRef Q (instanceRef RWMask_4))
-           (portRef C (instanceRef RWBank_5_0_4))
+          (net (rename FS_10 "FS[10]") (joined
+           (portRef Q (instanceRef FS_10))
+           (portRef (member fs 5) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_9))
           ))
-          (net (rename RWMask_5 "RWMask[5]") (joined
-           (portRef Q (instanceRef RWMask_5))
-           (portRef C (instanceRef RWBank_5_0_5))
+          (net (rename FS_11 "FS[11]") (joined
+           (portRef Q (instanceRef FS_11))
+           (portRef (member fs 4) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_cry_0_11))
           ))
-          (net (rename RWMask_6 "RWMask[6]") (joined
-           (portRef Q (instanceRef RWMask_6))
-           (portRef C (instanceRef RWBank_5_0_6))
+          (net (rename FS_12 "FS[12]") (joined
+           (portRef Q (instanceRef FS_12))
+           (portRef (member fs 3) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_11))
+          ))
+          (net (rename FS_13 "FS[13]") (joined
+           (portRef Q (instanceRef FS_13))
+           (portRef (member fs 2) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_cry_0_13))
+          ))
+          (net (rename FS_14 "FS[14]") (joined
+           (portRef Q (instanceRef FS_14))
+           (portRef (member fs 1) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_13))
+          ))
+          (net (rename FS_15 "FS[15]") (joined
+           (portRef Q (instanceRef FS_15))
+           (portRef (member fs 0) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_s_0_15))
           ))
           (net (rename CS_0 "CS[0]") (joined
            (portRef Q (instanceRef CS_0))
-           (portRef D (instanceRef CS_RNO_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_10))
-           (portRef A (instanceRef CS_RNO_0_2))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_1))
-           (portRef A (instanceRef CS_RNO_0))
+           (portRef (member cs 2) (instanceRef ram2e_ufm))
           ))
           (net (rename CS_1 "CS[1]") (joined
            (portRef Q (instanceRef CS_1))
-           (portRef A (instanceRef CS_RNO_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_15))
-           (portRef A (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_4))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_0))
-           (portRef A (instanceRef CS_RNO_2))
+           (portRef (member cs 1) (instanceRef ram2e_ufm))
           ))
           (net (rename CS_2 "CS[2]") (joined
            (portRef Q (instanceRef CS_2))
-           (portRef B (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o2_0))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_0))
-           (portRef B (instanceRef CS_RNO_2))
-          ))
-          (net CmdExecMXO2 (joined
-           (portRef Q (instanceRef CmdExecMXO2))
-           (portRef B (instanceRef un1_LEDEN13_2_i_a2_0))
-           (portRef A (instanceRef wb_we_RNO_0))
-           (portRef A (instanceRef wb_cyc_stb_RNO))
-           (portRef A (instanceRef CmdExecMXO2_4_u_0_0_0))
-          ))
-          (net DOEEN (joined
-           (portRef Q (instanceRef DOEEN))
-           (portRef A (instanceRef nDOE_pad_RNO))
-          ))
-          (net LEDEN (joined
-           (portRef Q (instanceRef LEDEN))
-           (portRef D (instanceRef RWBank_5_0_o2_0))
-           (portRef A (instanceRef LED_pad_RNO))
-          ))
-          (net CmdLEDGet (joined
-           (portRef Q (instanceRef CmdLEDGet))
-           (portRef A (instanceRef RWBank_5_0_o2_0))
-           (portRef A (instanceRef CmdLEDGet_4_u_0_0_0))
-          ))
-          (net CO0_1 (joined
-           (portRef Q (instanceRef CmdTout_0))
-           (portRef A (instanceRef CmdTout_3_0_a2_0))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_5))
-           (portRef A (instanceRef CmdTout_RNO_1))
-           (portRef C (instanceRef CmdTout_RNO_2))
-          ))
-          (net (rename CmdTout_1 "CmdTout[1]") (joined
-           (portRef Q (instanceRef CmdTout_1))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_5))
-           (portRef B (instanceRef CmdTout_RNO_1))
-           (portRef B (instanceRef CmdTout_RNO_2))
-          ))
-          (net (rename CmdTout_2 "CmdTout[2]") (joined
-           (portRef Q (instanceRef CmdTout_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_5))
-           (portRef A (instanceRef CmdTout_RNO_2))
-          ))
-          (net (rename SZ0Z_1 "S_1") (joined
-           (portRef Z (instanceRef SZ0Z_1))
-           (portRef A (instanceRef S_s_0_0))
-           (portRef A (instanceRef S_RNO_3))
-           (portRef A (instanceRef S_RNO_1))
-           (portRef A (instanceRef S_RNO_2))
+           (portRef (member cs 0) (instanceRef ram2e_ufm))
           ))
           (net Ready (joined
            (portRef Q (instanceRef Ready))
+           (portRef Ready (instanceRef ram2e_ufm))
            (portRef C (instanceRef SZ0Z_1))
            (portRef B (instanceRef Ready_RNO))
           ))
-          (net wb_rst8 (joined
-           (portRef Z (instanceRef wb_rst8_0_a2))
-           (portRef D (instanceRef wb_rst))
+          (net RWSel (joined
+           (portRef Q (instanceRef RWSel))
+           (portRef RWSel (instanceRef ram2e_ufm))
           ))
-          (net nCS61 (joined
-           (portRef Z (instanceRef S_RNII9DO1_3_1))
-           (portRef D (instanceRef DQML_0io_RNO))
-           (portRef D (instanceRef nRWE_r_0_RNO))
-           (portRef SP (instanceRef RWSel))
+          (net CmdRWMaskSet (joined
+           (portRef Q (instanceRef CmdRWMaskSet))
+           (portRef CmdRWMaskSet (instanceRef ram2e_ufm))
           ))
-          (net RWSel_2 (joined
-           (portRef Z (instanceRef RWSel_2))
-           (portRef D (instanceRef RWSel))
+          (net CmdLEDSet (joined
+           (portRef Q (instanceRef CmdLEDSet))
+           (portRef CmdLEDSet (instanceRef ram2e_ufm))
           ))
-          (net (rename RWMask_7 "RWMask[7]") (joined
-           (portRef Q (instanceRef RWMask_7))
-           (portRef C (instanceRef RWBank_5_0_0_7))
+          (net PHI1r (joined
+           (portRef Q (instanceRef PHI1r_0io))
+           (portRef B (instanceRef SZ0Z_1))
+          ))
+          (net (rename RC_1 "RC[1]") (joined
+           (portRef Q (instanceRef RC_1))
+           (portRef (member rc 1) (instanceRef ram2e_ufm))
+          ))
+          (net (rename RC_2 "RC[2]") (joined
+           (portRef Q (instanceRef RC_2))
+           (portRef (member rc 0) (instanceRef ram2e_ufm))
+          ))
+          (net CO0_1 (joined
+           (portRef Q (instanceRef RC_0))
+           (portRef CO0_1 (instanceRef ram2e_ufm))
+          ))
+          (net (rename RA_3 "RA[3]") (joined
+           (portRef Q (instanceRef RA_3))
+           (portRef (member ra 8) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_3))
+          ))
+          (net (rename RWBank_0 "RWBank[0]") (joined
+           (portRef Q (instanceRef RWBank_0))
+           (portRef (member rwbank 7) (instanceRef ram2e_ufm))
+          ))
+          (net CO0_0 (joined
+           (portRef Q (instanceRef CmdTout_0))
+           (portRef CO0_0 (instanceRef ram2e_ufm))
+          ))
+          (net (rename CmdTout_1 "CmdTout[1]") (joined
+           (portRef Q (instanceRef CmdTout_1))
+           (portRef (member cmdtout 1) (instanceRef ram2e_ufm))
+          ))
+          (net (rename CmdTout_2 "CmdTout[2]") (joined
+           (portRef Q (instanceRef CmdTout_2))
+           (portRef (member cmdtout 0) (instanceRef ram2e_ufm))
+          ))
+          (net CmdLEDGet (joined
+           (portRef Q (instanceRef CmdLEDGet))
+           (portRef CmdLEDGet (instanceRef ram2e_ufm))
+          ))
+          (net (rename SZ0Z_1 "S_1") (joined
+           (portRef Z (instanceRef SZ0Z_1))
+           (portRef S_1 (instanceRef ram2e_ufm))
+          ))
+          (net DOEEN (joined
+           (portRef Q (instanceRef DOEEN))
+           (portRef DOEEN (instanceRef ram2e_ufm))
+          ))
+          (net VOEEN (joined
+           (portRef Q (instanceRef VOEEN))
+           (portRef B (instanceRef nVOE_pad_RNO))
+          ))
+          (net RC12 (joined
+           (portRef RC12 (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef RC_2))
+           (portRef SP (instanceRef RC_1))
+           (portRef SP (instanceRef RC_0))
           ))
           (net Vout3 (joined
-           (portRef Z (instanceRef Vout3_0_a2))
+           (portRef Vout3 (instanceRef ram2e_ufm))
            (portRef SP (instanceRef Vout_0io_7))
            (portRef SP (instanceRef Vout_0io_6))
            (portRef SP (instanceRef Vout_0io_5))
@@ -2481,721 +4617,308 @@
            (portRef SP (instanceRef Vout_0io_2))
            (portRef SP (instanceRef Vout_0io_1))
            (portRef SP (instanceRef Vout_0io_0))
-           (portRef A (instanceRef nCAS_0io_RNO_0))
+          ))
+          (net RWSel_2 (joined
+           (portRef RWSel_2 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RWSel))
+          ))
+          (net (rename RA_0 "RA[0]") (joined
+           (portRef Q (instanceRef RA_0))
+           (portRef (member ra 11) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_0))
           ))
           (net CmdSetRWBankFFLED (joined
            (portRef Q (instanceRef CmdSetRWBankFFLED))
-           (portRef B (instanceRef RWBank_5_0_o2_0))
-           (portRef A (instanceRef CmdSetRWBankFFLED_4_u_0_0_0))
+           (portRef CmdSetRWBankFFLED (instanceRef ram2e_ufm))
           ))
-          (net CmdSetRWBankFFMXO2 (joined
-           (portRef Q (instanceRef CmdSetRWBankFFMXO2))
-           (portRef C (instanceRef RWBank_5_0_o2_0))
-           (portRef A (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0))
+          (net Ready3 (joined
+           (portRef Ready3 (instanceRef ram2e_ufm))
+           (portRef A (instanceRef Ready_RNO))
           ))
-          (net wb_req (joined
-           (portRef Q (instanceRef wb_req))
-           (portRef D (instanceRef un1_LEDEN13_2_i_a2_0_0))
+          (net BA_0_sqmuxa (joined
+           (portRef BA_0_sqmuxa (instanceRef ram2e_ufm))
+           (portRef CD (instanceRef BA_0io_1))
+           (portRef CD (instanceRef BA_0io_0))
           ))
-          (net LEDEN13 (joined
-           (portRef Z (instanceRef wb_reqc_1_RNIRU4M1))
-           (portRef B (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0))
-           (portRef B (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0))
-           (portRef SP (instanceRef RWBank_7))
-           (portRef SP (instanceRef RWBank_6))
-           (portRef SP (instanceRef RWBank_5))
-           (portRef SP (instanceRef RWBank_4))
-           (portRef SP (instanceRef RWBank_3))
-           (portRef SP (instanceRef RWBank_2))
-           (portRef SP (instanceRef RWBank_1))
-           (portRef SP (instanceRef RWBank_0))
-          ))
-          (net (rename RWBank_5_0 "RWBank_5[0]") (joined
-           (portRef Z (instanceRef RWBank_5_0_0))
+          (net (rename RWBank_3_0 "RWBank_3[0]") (joined
+           (portRef (member rwbank_3 7) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_0))
           ))
-          (net (rename RWBank_5_1 "RWBank_5[1]") (joined
-           (portRef Z (instanceRef RWBank_5_0_1))
+          (net (rename RWBank_3_1 "RWBank_3[1]") (joined
+           (portRef (member rwbank_3 6) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_1))
           ))
-          (net (rename RWBank_5_2 "RWBank_5[2]") (joined
-           (portRef Z (instanceRef RWBank_5_0_2))
+          (net (rename RWBank_3_2 "RWBank_3[2]") (joined
+           (portRef (member rwbank_3 5) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_2))
           ))
-          (net (rename RWBank_5_3 "RWBank_5[3]") (joined
-           (portRef Z (instanceRef RWBank_5_0_3))
+          (net (rename RWBank_3_3 "RWBank_3[3]") (joined
+           (portRef (member rwbank_3 4) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_3))
           ))
-          (net (rename RWBank_5_5 "RWBank_5[5]") (joined
-           (portRef Z (instanceRef RWBank_5_0_5))
+          (net (rename RWBank_3_4 "RWBank_3[4]") (joined
+           (portRef (member rwbank_3 3) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RWBank_4))
+          ))
+          (net (rename RWBank_3_5 "RWBank_3[5]") (joined
+           (portRef (member rwbank_3 2) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_5))
           ))
-          (net (rename RWBank_5_6 "RWBank_5[6]") (joined
-           (portRef Z (instanceRef RWBank_5_0_6))
+          (net (rename RWBank_3_6 "RWBank_3[6]") (joined
+           (portRef (member rwbank_3 1) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_6))
           ))
-          (net (rename RWBank_5_7 "RWBank_5[7]") (joined
-           (portRef Z (instanceRef RWBank_5_0_0_7))
+          (net (rename RWBank_3_7 "RWBank_3[7]") (joined
+           (portRef (member rwbank_3 0) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_7))
           ))
-          (net (rename RWBank_0 "RWBank[0]") (joined
-           (portRef Q (instanceRef RWBank_0))
-           (portRef B (instanceRef RA_0io_RNO_8))
+          (net CmdSetRWBankFFLED_4 (joined
+           (portRef CmdSetRWBankFFLED_4 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CmdSetRWBankFFLED))
+          ))
+          (net CmdLEDGet_3 (joined
+           (portRef CmdLEDGet_3 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CmdLEDGet))
+          ))
+          (net CmdLEDSet_3 (joined
+           (portRef CmdLEDSet_3 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CmdLEDSet))
+          ))
+          (net CmdRWMaskSet_3 (joined
+           (portRef CmdRWMaskSet_3 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CmdRWMaskSet))
+          ))
+          (net (rename CmdTout_3_0 "CmdTout_3[0]") (joined
+           (portRef CmdTout_3_0 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CmdTout_0))
           ))
           (net (rename RWBank_1 "RWBank[1]") (joined
            (portRef Q (instanceRef RWBank_1))
-           (portRef A (instanceRef RA_0io_RNO_9))
+           (portRef (member rwbank 6) (instanceRef ram2e_ufm))
           ))
           (net (rename RWBank_2 "RWBank[2]") (joined
            (portRef Q (instanceRef RWBank_2))
-           (portRef C (instanceRef RA_42_0_10))
+           (portRef (member rwbank 5) (instanceRef ram2e_ufm))
           ))
           (net (rename RWBank_3 "RWBank[3]") (joined
            (portRef Q (instanceRef RWBank_3))
-           (portRef A (instanceRef RA_0io_RNO_11))
+           (portRef (member rwbank 4) (instanceRef ram2e_ufm))
           ))
           (net (rename RWBank_4 "RWBank[4]") (joined
            (portRef Q (instanceRef RWBank_4))
-           (portRef A (instanceRef BA_0io_RNO_0))
+           (portRef (member rwbank 3) (instanceRef ram2e_ufm))
           ))
           (net (rename RWBank_5 "RWBank[5]") (joined
            (portRef Q (instanceRef RWBank_5))
-           (portRef A (instanceRef BA_0io_RNO_1))
+           (portRef (member rwbank 2) (instanceRef ram2e_ufm))
+          ))
+          (net (rename RWBank_6 "RWBank[6]") (joined
+           (portRef Q (instanceRef RWBank_6))
+           (portRef (member rwbank 1) (instanceRef ram2e_ufm))
           ))
           (net (rename RWBank_7 "RWBank[7]") (joined
            (portRef Q (instanceRef RWBank_7))
-           (portRef C (instanceRef RA_0io_RNO_8))
-          ))
-          (net CmdLEDSet (joined
-           (portRef Q (instanceRef CmdLEDSet))
-           (portRef A (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0))
-           (portRef A (instanceRef CmdLEDSet_4_u_0_0_0))
-          ))
-          (net CmdRWMaskSet (joined
-           (portRef Q (instanceRef CmdRWMaskSet))
-           (portRef A (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0))
-           (portRef A (instanceRef CmdRWMaskSet_4_u_0_0_0))
-          ))
-          (net CmdBitbangMXO2 (joined
-           (portRef Q (instanceRef CmdBitbangMXO2))
-           (portRef A (instanceRef CmdBitbangMXO2_RNI8CSO1))
-           (portRef A (instanceRef CmdBitbangMXO2_4_u_0_0_0))
-          ))
-          (net nCAS_0_sqmuxa (joined
-           (portRef Z (instanceRef nCS_6_u_i_a2_4_RNICJKD2))
-           (portRef B (instanceRef nRWE_r_0))
-           (portRef D (instanceRef RA_42_0_10))
-           (portRef A (instanceRef nCAS_0io_RNO))
-          ))
-          (net Ready_0_sqmuxa (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_6_a2))
-           (portRef A (instanceRef Ready_RNO))
+           (portRef (member rwbank 0) (instanceRef ram2e_ufm))
           ))
           (net (rename BA_4_0 "BA_4[0]") (joined
-           (portRef Z (instanceRef BA_0io_RNO_0))
+           (portRef (member ba_4 1) (instanceRef ram2e_ufm))
            (portRef D (instanceRef BA_0io_0))
           ))
           (net (rename BA_4_1 "BA_4[1]") (joined
-           (portRef Z (instanceRef BA_0io_RNO_1))
+           (portRef (member ba_4 0) (instanceRef ram2e_ufm))
            (portRef D (instanceRef BA_0io_1))
           ))
-          (net (rename RA_42_11 "RA_42[11]") (joined
-           (portRef Z (instanceRef RA_0io_RNO_11))
-           (portRef D (instanceRef RA_0io_11))
+          (net (rename RA_1 "RA[1]") (joined
+           (portRef Q (instanceRef RA_1))
+           (portRef (member ra 10) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_1))
           ))
-          (net nRWE_r_0 (joined
-           (portRef Z (instanceRef nRWE_r_0))
-           (portRef D (instanceRef nRWE_0io))
+          (net (rename RA_2 "RA[2]") (joined
+           (portRef Q (instanceRef RA_2))
+           (portRef (member ra 9) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_2))
           ))
-          (net (rename S_s_0_0 "S_s_0[0]") (joined
-           (portRef Z (instanceRef S_s_0_0))
+          (net (rename RA_4 "RA[4]") (joined
+           (portRef Q (instanceRef RA_4))
+           (portRef (member ra 7) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_4))
+          ))
+          (net (rename RA_5 "RA[5]") (joined
+           (portRef Q (instanceRef RA_5))
+           (portRef (member ra 6) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_5))
+          ))
+          (net (rename RA_6 "RA[6]") (joined
+           (portRef Q (instanceRef RA_6))
+           (portRef (member ra 5) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_6))
+          ))
+          (net (rename RA_7 "RA[7]") (joined
+           (portRef Q (instanceRef RA_7))
+           (portRef (member ra 4) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_7))
+          ))
+          (net (rename RA_8 "RA[8]") (joined
+           (portRef Q (instanceRef RA_8))
+           (portRef (member ra 3) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_8))
+          ))
+          (net (rename RA_9 "RA[9]") (joined
+           (portRef Q (instanceRef RA_9))
+           (portRef (member ra 2) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_9))
+          ))
+          (net (rename RA_10 "RA[10]") (joined
+           (portRef Q (instanceRef RA_10))
+           (portRef (member ra 1) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_10))
+          ))
+          (net (rename RA_11 "RA[11]") (joined
+           (portRef Q (instanceRef RA_11))
+           (portRef (member ra 0) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_11))
+          ))
+          (net CKE (joined
+           (portRef Q (instanceRef CKE))
+           (portRef D (instanceRef CKEout_0io))
+          ))
+          (net nRWE (joined
+           (portRef Q (instanceRef nRWE))
+           (portRef D (instanceRef nRWEout_0io))
+          ))
+          (net nCAS (joined
+           (portRef Q (instanceRef nCAS))
+           (portRef D (instanceRef nCASout_0io))
+          ))
+          (net nRAS (joined
+           (portRef Q (instanceRef nRAS))
+           (portRef D (instanceRef nRASout_0io))
+          ))
+          (net (rename S_s_0_0_0 "S_s_0_0[0]") (joined
+           (portRef S_s_0_0_0 (instanceRef ram2e_ufm))
            (portRef D (instanceRef S_0))
           ))
-          (net (rename wb_dati_7_0 "wb_dati_7[0]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0))
-           (portRef D (instanceRef wb_dati_0))
+          (net CmdExecMXO2_3_0_a3_0_RNI6S1P8 (joined
+           (portRef CmdExecMXO2_3_0_a3_0_RNI6S1P8_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CS_1))
           ))
-          (net (rename wb_dati_7_1 "wb_dati_7[1]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_1))
-           (portRef D (instanceRef wb_dati_1))
+          (net CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 (joined
+           (portRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CS_2))
           ))
-          (net (rename wb_dati_7_2 "wb_dati_7[2]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_2))
-           (portRef D (instanceRef wb_dati_2))
+          (net (rename RA_35_0 "RA_35[0]") (joined
+           (portRef (member ra_35 11) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_0))
           ))
-          (net (rename wb_dati_7_3 "wb_dati_7[3]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_3))
-           (portRef D (instanceRef wb_dati_3))
+          (net (rename RA_35_2 "RA_35[2]") (joined
+           (portRef (member ra_35 9) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_2))
           ))
-          (net (rename wb_dati_7_4 "wb_dati_7[4]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_4))
-           (portRef D (instanceRef wb_dati_4))
+          (net (rename RA_35_3 "RA_35[3]") (joined
+           (portRef (member ra_35 8) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_3))
           ))
-          (net (rename wb_dati_7_5 "wb_dati_7[5]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_5))
-           (portRef D (instanceRef wb_dati_5))
+          (net (rename RA_35_4 "RA_35[4]") (joined
+           (portRef (member ra_35 7) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_4))
           ))
-          (net (rename wb_dati_7_6 "wb_dati_7[6]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_6))
-           (portRef D (instanceRef wb_dati_6))
+          (net (rename RA_35_5 "RA_35[5]") (joined
+           (portRef (member ra_35 6) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_5))
           ))
-          (net (rename wb_dati_7_7 "wb_dati_7[7]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_7))
-           (portRef D (instanceRef wb_dati_7))
+          (net (rename RA_35_6 "RA_35[6]") (joined
+           (portRef (member ra_35 5) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_6))
           ))
-          (net (rename wb_adr_7_0 "wb_adr_7[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_0))
-           (portRef D (instanceRef wb_adr_0))
+          (net (rename RA_35_7 "RA_35[7]") (joined
+           (portRef (member ra_35 4) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_7))
           ))
-          (net (rename RA_42_3_0_5 "RA_42_3_0[5]") (joined
-           (portRef Z (instanceRef RA_42_3_0_5))
-           (portRef D (instanceRef RA_0io_5))
+          (net (rename RA_35_9 "RA_35[9]") (joined
+           (portRef (member ra_35 2) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_9))
           ))
-          (net (rename RA_42_10 "RA_42[10]") (joined
-           (portRef Z (instanceRef RA_42_0_10))
-           (portRef D (instanceRef RA_0io_10))
+          (net (rename RA_35_10 "RA_35[10]") (joined
+           (portRef (member ra_35 1) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_10))
           ))
-          (net CmdLEDGet_4 (joined
-           (portRef Z (instanceRef CmdLEDGet_4_u_0_0_0))
-           (portRef D (instanceRef CmdLEDGet))
+          (net (rename RA_35_11 "RA_35[11]") (joined
+           (portRef (member ra_35 0) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_11))
           ))
-          (net (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (joined
-           (portRef Z (instanceRef wb_adr_RNO_1))
-           (portRef D (instanceRef wb_adr_1))
+          (net un2_S_2_i_0_0_o3_RNIHFHN3 (joined
+           (portRef un2_S_2_i_0_0_o3_RNIHFHN3_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_8))
           ))
-          (net wb_we_RNO (joined
-           (portRef Z (instanceRef wb_we_RNO))
-           (portRef D (instanceRef wb_we))
-          ))
-          (net wb_cyc_stb_RNO (joined
-           (portRef Z (instanceRef wb_cyc_stb_RNO))
-           (portRef D (instanceRef wb_cyc_stb))
-          ))
-          (net (rename S_RNII9DO1_1_1 "S_RNII9DO1_1[1]") (joined
-           (portRef Z (instanceRef S_RNII9DO1_1_1))
+          (net N_126 (joined
+           (portRef N_126 (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef RA_11))
+           (portRef SP (instanceRef RA_10))
+           (portRef SP (instanceRef RA_9))
+           (portRef SP (instanceRef RA_8))
+           (portRef SP (instanceRef RA_7))
+           (portRef SP (instanceRef RA_6))
+           (portRef SP (instanceRef RA_5))
+           (portRef SP (instanceRef RA_4))
            (portRef SP (instanceRef RA_3))
+           (portRef SP (instanceRef RA_2))
+           (portRef SP (instanceRef RA_1))
            (portRef SP (instanceRef RA_0))
-           (portRef SP (instanceRef RA_0io_7))
-           (portRef SP (instanceRef RA_0io_6))
-           (portRef SP (instanceRef RA_0io_5))
-           (portRef SP (instanceRef RA_0io_4))
-           (portRef SP (instanceRef RA_0io_2))
-           (portRef SP (instanceRef RA_0io_1))
           ))
-          (net N_88 (joined
-           (portRef Z (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0))
-           (portRef SP (instanceRef RWMask_7))
-           (portRef SP (instanceRef RWMask_6))
-           (portRef SP (instanceRef RWMask_5))
-           (portRef SP (instanceRef RWMask_4))
-           (portRef SP (instanceRef RWMask_3))
-           (portRef SP (instanceRef RWMask_2))
-           (portRef SP (instanceRef RWMask_1))
-           (portRef SP (instanceRef RWMask_0))
+          (net N_223 (joined
+           (portRef N_223 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_1))
           ))
-          (net N_104 (joined
-           (portRef Z (instanceRef un1_LEDEN13_2_i_0_0))
-           (portRef SP (instanceRef wb_cyc_stb))
+          (net N_508 (joined
+           (portRef N_508 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef DQMH_0io))
           ))
-          (net (rename un1_LEDEN_0_sqmuxa_1_i_0_0 "un1_LEDEN_0_sqmuxa_1_i_0[0]") (joined
-           (portRef Z (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0))
-           (portRef SP (instanceRef LEDEN))
+          (net N_648 (joined
+           (portRef N_648 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_4))
           ))
-          (net CKE_6_iv_i_0 (joined
-           (portRef Z (instanceRef CKE_6_iv_i_0))
-           (portRef D (instanceRef CKE_0io))
+          (net N_662 (joined
+           (portRef N_662 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_7))
           ))
-          (net (rename S_RNII9DO1_1 "S_RNII9DO1[1]") (joined
-           (portRef Z (instanceRef S_RNII9DO1_1))
-           (portRef C (instanceRef wb_dati_7_0_a2_2_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_5_1))
-           (portRef B (instanceRef DQML_0io_RNO))
-           (portRef CD (instanceRef wb_rst))
-           (portRef B (instanceRef nCS_6_u_i_a2_4_RNI3A062))
-           (portRef B (instanceRef DQMH_0io_RNO))
-           (portRef C (instanceRef FS_RNIK5632_15))
+          (net N_663 (joined
+           (portRef N_663 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_6))
           ))
-          (net (rename S_RNII9DO1_0_1 "S_RNII9DO1_0[1]") (joined
-           (portRef Z (instanceRef S_RNII9DO1_0_1))
-           (portRef D (instanceRef un1_LEDEN13_2_i_a2_0))
-           (portRef B (instanceRef CS_RNO_1))
-           (portRef C (instanceRef CS_RNO_0_2))
-           (portRef C (instanceRef CS_RNO_0))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_3))
+          (net N_664 (joined
+           (portRef N_664 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_5))
           ))
-          (net N_285 (joined
-           (portRef Z (instanceRef RWMask_RNO_7))
-           (portRef D (instanceRef RWMask_7))
+          (net N_665 (joined
+           (portRef N_665 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_2))
           ))
-          (net LEDEN_RNO (joined
-           (portRef Z (instanceRef LEDEN_RNO))
-           (portRef D (instanceRef LEDEN))
+          (net N_666 (joined
+           (portRef N_666 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_1))
           ))
-          (net N_295 (joined
-           (portRef Z (instanceRef wb_adr_RNO_5))
-           (portRef D (instanceRef wb_adr_5))
+          (net N_667 (joined
+           (portRef N_667 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_0))
           ))
-          (net N_296 (joined
-           (portRef Z (instanceRef wb_adr_RNO_6))
-           (portRef D (instanceRef wb_adr_6))
+          (net CKE_7_RNIS77M1 (joined
+           (portRef CKE_7_RNIS77M1_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CKE))
           ))
-          (net N_294 (joined
-           (portRef Z (instanceRef wb_adr_RNO_4))
-           (portRef D (instanceRef wb_adr_4))
+          (net N_551 (joined
+           (portRef N_551 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef VOEEN))
           ))
-          (net CmdLEDSet_4 (joined
-           (portRef Z (instanceRef CmdLEDSet_4_u_0_0_0))
-           (portRef D (instanceRef CmdLEDSet))
+          (net (rename RC_3_1 "RC_3[1]") (joined
+           (portRef (member rc_3 1) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RC_1))
           ))
-          (net CmdBitbangMXO2_4 (joined
-           (portRef Z (instanceRef CmdBitbangMXO2_4_u_0_0_0))
-           (portRef D (instanceRef CmdBitbangMXO2))
-          ))
-          (net CmdRWMaskSet_4 (joined
-           (portRef Z (instanceRef CmdRWMaskSet_4_u_0_0_0))
-           (portRef D (instanceRef CmdRWMaskSet))
-          ))
-          (net (rename RWBank_5_4 "RWBank_5[4]") (joined
-           (portRef Z (instanceRef RWBank_5_0_4))
-           (portRef D (instanceRef RWBank_4))
-          ))
-          (net CmdExecMXO2_4 (joined
-           (portRef Z (instanceRef CmdExecMXO2_4_u_0_0_0))
-           (portRef D (instanceRef CmdExecMXO2))
-          ))
-          (net CmdSetRWBankFFMXO2_4 (joined
-           (portRef Z (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0))
-           (portRef D (instanceRef CmdSetRWBankFFMXO2))
-          ))
-          (net CmdSetRWBankFFLED_4 (joined
-           (portRef Z (instanceRef CmdSetRWBankFFLED_4_u_0_0_0))
-           (portRef D (instanceRef CmdSetRWBankFFLED))
-          ))
-          (net (rename CmdTout_3_0 "CmdTout_3[0]") (joined
-           (portRef Z (instanceRef CmdTout_3_0_a2_0))
-           (portRef D (instanceRef CmdTout_0))
-          ))
-          (net N_637 (joined
-           (portRef Z (instanceRef CS_RNO_0_2))
-           (portRef C (instanceRef CS_RNO_2))
-          ))
-          (net N_466 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_7))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_10))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_2))
-          ))
-          (net N_474 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_10))
-           (portRef C (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F))
-          ))
-          (net N_477 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_11))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_2))
-          ))
-          (net N_478 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_12))
-           (portRef D (instanceRef CmdLEDGet_4_u_0_0_a2_0_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_2))
-          ))
-          (net N_616 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_13))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o2_0))
-          ))
-          (net N_629 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_17))
-           (portRef C (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0))
-           (portRef B (instanceRef CmdExecMXO2_4_u_0_0_0))
-          ))
-          (net N_461 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_5))
-           (portRef C (instanceRef CS_RNO_1))
-           (portRef B (instanceRef CS_RNO_0_2))
-           (portRef B (instanceRef CS_RNO_0))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_3))
-          ))
-          (net N_401 (joined
-           (portRef Z (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_0))
-           (portRef B (instanceRef CmdSetRWBankFFLED_4_u_0_0_0))
-          ))
-          (net N_591 (joined
-           (portRef Z (instanceRef RWBank_5_0_o2_0))
-           (portRef B (instanceRef RWBank_5_0_0))
-           (portRef B (instanceRef RWBank_5_0_1))
-           (portRef B (instanceRef RWBank_5_0_0_7))
-           (portRef B (instanceRef RWBank_5_0_6))
-           (portRef B (instanceRef RWBank_5_0_5))
-           (portRef B (instanceRef RWBank_5_0_3))
-           (portRef B (instanceRef RWBank_5_0_2))
-           (portRef B (instanceRef RWBank_5_0_4))
-          ))
-          (net N_279 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o2_0))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_2))
-          ))
-          (net N_623 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_15))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o2_0))
-          ))
-          (net N_327 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_1))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_0))
-          ))
-          (net N_328 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_2))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_3))
-          ))
-          (net N_330 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_3))
-          ))
-          (net N_476 (joined
-           (portRef Z (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_1))
-           (portRef A (instanceRef CmdBitbangMXO2_4_u_0_0_a2_1))
-           (portRef C (instanceRef CmdLEDSet_4_u_0_0_a2_0))
-           (portRef C (instanceRef CmdLEDGet_4_u_0_0_0))
-           (portRef C (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_0))
-           (portRef C (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0))
-          ))
-          (net N_626 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_16))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_2))
-           (portRef D (instanceRef CmdLEDSet_4_u_0_0_a2_0))
-           (portRef D (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_0))
-           (portRef B (instanceRef CmdRWMaskSet_4_u_0_0_0))
-          ))
-          (net N_643 (joined
-           (portRef Z (instanceRef CmdBitbangMXO2_4_u_0_0_a2_1))
-           (portRef C (instanceRef CmdBitbangMXO2_4_u_0_0_0))
-           (portRef C (instanceRef CmdRWMaskSet_4_u_0_0_0))
-           (portRef C (instanceRef CmdExecMXO2_4_u_0_0_0))
-          ))
-          (net N_605 (joined
-           (portRef Z (instanceRef CmdLEDSet_4_u_0_0_a2_0))
-           (portRef B (instanceRef CmdLEDSet_4_u_0_0_0))
-          ))
-          (net N_255 (joined
-           (portRef Z (instanceRef RA_42_i_o2_8))
-           (portRef A (instanceRef RA_0io_RNO_8))
-           (portRef A (instanceRef RA_42_0_10))
-           (portRef D (instanceRef DQMH_0io_RNO))
-          ))
-          (net N_575 (joined
-           (portRef Z (instanceRef S_RNINI6S_1))
-           (portRef B (instanceRef S_RNO_3))
-           (portRef C (instanceRef S_RNO_1))
-           (portRef B (instanceRef S_RNO_2))
-          ))
-          (net N_397 (joined
-           (portRef Z (instanceRef wb_req_RNO_1))
-           (portRef B (instanceRef wb_req_RNO))
-          ))
-          (net N_635 (joined
-           (portRef Z (instanceRef nRAS_2_iv_0_a2_0))
-           (portRef B (instanceRef nRAS_2_iv_i))
-           (portRef D (instanceRef nCAS_0io_RNO_0))
-          ))
-          (net N_449 (joined
-           (portRef Z (instanceRef FS_RNI5OOF1_15))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4))
-           (portRef C (instanceRef un1_LEDEN13_2_i_a2_0_0))
-           (portRef C (instanceRef un1_LEDEN13_2_i_0_0))
-           (portRef D (instanceRef nCS_6_u_i_a2_4_RNICJKD2))
-          ))
-          (net N_633 (joined
-           (portRef Z (instanceRef un1_nCS61_1_0_a2_0))
-           (portRef C (instanceRef nCS_6_u_i_o2))
-           (portRef B (instanceRef nCAS_s_i_o2))
-           (portRef B (instanceRef nRWE_r_0_RNO))
-          ))
-          (net N_264 (joined
-           (portRef Z (instanceRef FS_RNI9FGA_1))
-           (portRef A (instanceRef nCS_6_u_i_o2))
-           (portRef D (instanceRef un1_LEDEN13_2_i_o2_2_0))
-           (portRef A (instanceRef nCS_6_u_i_a2_4_RNICJKD2))
-          ))
-          (net N_559_1 (joined
-           (portRef Z (instanceRef nCS_6_u_i_1))
-           (portRef A (instanceRef nRAS_2_iv_i))
-           (portRef A (instanceRef nCS_0io_RNO))
-          ))
-          (net N_429 (joined
-           (portRef Z (instanceRef nCS_6_u_i_a2_0))
-           (portRef A (instanceRef nCS_6_u_i_1))
-          ))
-          (net N_640 (joined
-           (portRef Z (instanceRef nCS_6_u_i_a2_4_RNI3A062))
-           (portRef C (instanceRef nRWE_r_0_RNO))
-           (portRef C (instanceRef nCAS_0io_RNO))
-          ))
-          (net N_336 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_1))
-           (portRef A (instanceRef wb_dati_7_0_o2_0_2))
-           (portRef A (instanceRef wb_dati_7_0_1))
-           (portRef A (instanceRef wb_dati_7_0_3))
-          ))
-          (net N_565 (joined
-           (portRef Z (instanceRef wb_dati_7_0_o2_1))
-           (portRef C (instanceRef wb_dati_7_0_a2_1))
-          ))
-          (net N_484 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_2_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_1))
-           (portRef B (instanceRef wb_dati_7_0_a2_1_7))
-           (portRef C (instanceRef wb_dati_7_0_a2_5_4))
-           (portRef A (instanceRef wb_dati_7_0_0))
-           (portRef C (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0))
-          ))
-          (net N_634 (joined
-           (portRef Z (instanceRef FS_RNIOD6E_1_8))
-           (portRef C (instanceRef wb_dati_7_0_a2_2_0_1))
-           (portRef B (instanceRef wb_dati_7_0_0_4))
-           (portRef D (instanceRef wb_dati_7_0_o2_0_2))
-          ))
-          (net N_452 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_5_1))
-           (portRef B (instanceRef wb_dati_7_0_a2_6_1))
-           (portRef B (instanceRef wb_adr_7_0_1_0))
-           (portRef B (instanceRef wb_adr_7_0_0_0))
-           (portRef A (instanceRef wb_dati_7_0_0_7))
-           (portRef A (instanceRef wb_dati_7_0_0_1))
-           (portRef B (instanceRef wb_dati_7_0_o2_0_2))
-          ))
-          (net N_365 (joined
-           (portRef Z (instanceRef un1_LEDEN13_2_i_a2_0_0))
-           (portRef B (instanceRef un1_LEDEN13_2_i_0_0))
-          ))
-          (net N_300 (joined
-           (portRef Z (instanceRef un1_LEDEN13_2_i_o2_2_0))
-           (portRef B (instanceRef un1_LEDEN13_2_i_a2_0_0))
-           (portRef A (instanceRef wb_cyc_stb_RNO_0))
-          ))
-          (net N_377 (joined
-           (portRef Z (instanceRef wb_adr_7_0_a2_1_0))
-           (portRef A (instanceRef wb_adr_7_0_4_0))
-          ))
-          (net N_455 (joined
-           (portRef Z (instanceRef FS_RNIK5632_15))
-           (portRef C (instanceRef wb_adr_7_0_a2_1_0))
-           (portRef C (instanceRef wb_dati_7_0_a2_6))
-           (portRef C (instanceRef wb_adr_7_0_a2_2_0))
-           (portRef A (instanceRef wb_dati_7_0_0_4))
-           (portRef A (instanceRef wb_dati_7_0_0_3))
-           (portRef B (instanceRef wb_dati_7_0_a2_4))
-           (portRef C (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0))
-           (portRef B (instanceRef wb_dati_7_0_2_3))
-          ))
-          (net N_562 (joined
-           (portRef Z (instanceRef wb_adr_7_0_o2_2_0))
-           (portRef D (instanceRef wb_adr_7_0_a2_0_0_0))
-           (portRef D (instanceRef wb_adr_7_0_a2_1_0))
-          ))
-          (net N_579 (joined
-           (portRef Z (instanceRef wb_adr_7_0_o2_0))
-           (portRef C (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0))
-           (portRef C (instanceRef wb_adr_7_0_1_0))
-           (portRef D (instanceRef wb_dati_7_0_a2_1_7))
-           (portRef D (instanceRef wb_adr_7_0_a2_2_0))
-           (portRef B (instanceRef wb_dati_7_0_RNO_7))
-          ))
-          (net N_388 (joined
-           (portRef Z (instanceRef wb_adr_RNO_0_1))
-           (portRef B (instanceRef wb_adr_RNO_1))
-          ))
-          (net N_265_i (joined
-           (portRef Z (instanceRef wb_adr_RNO_2_1))
-           (portRef C (instanceRef wb_adr_RNO_0_1))
-          ))
-          (net N_475 (joined
-           (portRef Z (instanceRef FS_RNIJ9MH_14))
-           (portRef D (instanceRef wb_adr_RNO_0_1))
-           (portRef C (instanceRef wb_we_RNO_4))
-           (portRef A (instanceRef wb_adr_RNO_1_1))
-           (portRef B (instanceRef wb_we_RNO))
-           (portRef A (instanceRef wb_we_RNO_3))
-          ))
-          (net N_577 (joined
-           (portRef Z (instanceRef FS_RNI6JJA_8))
-           (portRef D (instanceRef wb_we_RNO_4))
-           (portRef D (instanceRef CKE_6_iv_i_a2_3))
-           (portRef C (instanceRef wb_adr_RNO_1_1))
-           (portRef B (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0))
-          ))
-          (net N_569 (joined
-           (portRef Z (instanceRef FS_RNI9Q57_13))
-           (portRef B (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0))
-           (portRef B (instanceRef wb_adr_RNO_1_1))
-           (portRef C (instanceRef wb_dati_7_0_a2_1_7))
-           (portRef C (instanceRef wb_dati_7_0_o2_0_2))
-          ))
-          (net N_584 (joined
-           (portRef Z (instanceRef wb_we_RNO_1))
-           (portRef C (instanceRef wb_we_RNO))
-          ))
-          (net N_393 (joined
-           (portRef Z (instanceRef wb_we_RNO_3))
-           (portRef B (instanceRef wb_we_RNO_2))
-          ))
-          (net N_422 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_7))
-           (portRef A (instanceRef wb_dati_7_0_7))
-          ))
-          (net N_642 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_5_4))
-           (portRef D (instanceRef wb_dati_7_0_a2_7))
-           (portRef C (instanceRef wb_adr_7_0_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_5_RNIC22J_4))
-          ))
-          (net N_424 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_1_7))
-           (portRef B (instanceRef wb_dati_7_0_7))
-          ))
-          (net N_254 (joined
-           (portRef Z (instanceRef nCS_6_u_i_o2_0))
-           (portRef A (instanceRef nCS_6_u_i_a2_0))
-           (portRef C (instanceRef un1_LEDEN13_2_i_o2_2_0))
-           (portRef B (instanceRef nCS_6_u_i_a2_4_RNICJKD2))
-           (portRef B (instanceRef nCAS_0io_RNO_0))
-          ))
-          (net N_489 (joined
-           (portRef Z (instanceRef CKE_6_iv_i_a2_3))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a2_6_a2))
-           (portRef C (instanceRef CKE_6_iv_i_0))
-           (portRef D (instanceRef nCS_6_u_i_a2_4))
-          ))
-          (net N_567 (joined
-           (portRef Z (instanceRef nCAS_s_i_o2))
-           (portRef B (instanceRef nCAS_0io_RNO))
-          ))
-          (net N_639 (joined
-           (portRef Z (instanceRef RA_42_0_RNO_10))
-           (portRef B (instanceRef RA_42_0_10))
-          ))
-          (net N_364 (joined
-           (portRef Z (instanceRef un1_LEDEN13_2_i_a2_0))
-           (portRef A (instanceRef un1_LEDEN13_2_i_0_0))
-          ))
-          (net N_456 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_1_0))
-           (portRef D (instanceRef wb_dati_7_0_a2_1_0_0))
-           (portRef C (instanceRef CKE_6_iv_i_a2_3))
-          ))
-          (net N_349 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_3_4))
-           (portRef C (instanceRef wb_dati_7_0_4))
-          ))
-          (net N_621 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_6_1))
-           (portRef D (instanceRef wb_dati_7_0_a2_3_4))
-           (portRef C (instanceRef wb_dati_7_0_RNO_7))
-           (portRef D (instanceRef wb_adr_7_0_a2_0_0))
-           (portRef B (instanceRef wb_dati_7_0_1))
-           (portRef A (instanceRef wb_dati_7_0_6))
-          ))
-          (net N_351 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_6))
-           (portRef B (instanceRef wb_dati_7_0_1_6))
-          ))
-          (net N_378 (joined
-           (portRef Z (instanceRef wb_adr_7_0_a2_2_0))
-           (portRef B (instanceRef wb_adr_7_0_4_0))
-          ))
-          (net N_394 (joined
-           (portRef Z (instanceRef wb_we_RNO_4))
-           (portRef C (instanceRef wb_we_RNO_2))
-          ))
-          (net N_628 (joined
-           (portRef Z (instanceRef nCS_6_u_i_a2_4))
-           (portRef C (instanceRef nCS_6_u_i_1))
-           (portRef C (instanceRef nCS_6_u_i_a2_4_RNICJKD2))
-           (portRef A (instanceRef nCS_6_u_i_a2_4_RNI3A062))
-          ))
-          (net N_570 (joined
-           (portRef Z (instanceRef nCS_6_u_i_o2))
-           (portRef B (instanceRef nCS_6_u_i_1))
-          ))
-          (net N_345 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_4))
-           (portRef A (instanceRef wb_dati_7_0_4))
-           (portRef A (instanceRef wb_dati_7_0_2))
-           (portRef A (instanceRef wb_dati_7_0_5))
-          ))
-          (net N_346 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_5_RNIC22J_4))
-           (portRef A (instanceRef wb_dati_7_0_1_6))
-           (portRef B (instanceRef wb_dati_7_0_4))
-          ))
-          (net (rename un1_wb_adr_0_sqmuxa_2_1_0 "un1_wb_adr_0_sqmuxa_2_1[0]") (joined
-           (portRef Z (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0))
-           (portRef C (instanceRef CmdBitbangMXO2_RNI8CSO1))
-           (portRef C (instanceRef wb_we_RNO_0))
-          ))
-          (net N_376 (joined
-           (portRef Z (instanceRef wb_adr_7_0_a2_0_0))
-           (portRef B (instanceRef wb_adr_7_0_0))
-          ))
-          (net N_586 (joined
-           (portRef Z (instanceRef un1_LEDEN13_2_i_o2_0))
-           (portRef D (instanceRef un1_LEDEN13_2_i_0_0))
-          ))
-          (net N_627 (joined
-           (portRef Z (instanceRef FS_RNIOD6E_0_8))
-           (portRef B (instanceRef wb_dati_7_0_0_3))
-           (portRef C (instanceRef wb_dati_7_0_a2_4))
-           (portRef C (instanceRef wb_dati_7_0_1))
-           (portRef B (instanceRef wb_dati_7_0_6))
-          ))
-          (net N_644 (joined
-           (portRef Z (instanceRef FS_RNIOD6E_8))
-           (portRef D (instanceRef wb_dati_7_0_a2_4))
-           (portRef C (instanceRef wb_dati_7_0_2_3))
-          ))
-          (net N_572 (joined
-           (portRef Z (instanceRef S_r_i_o2_1))
-           (portRef B (instanceRef S_RNO_1))
-          ))
-          (net N_395 (joined
-           (portRef Z (instanceRef wb_cyc_stb_RNO_0))
-           (portRef B (instanceRef wb_cyc_stb_RNO))
-          ))
-          (net (rename wb_dati_7_0_RNO_7 "wb_dati_7_0_RNO[7]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_RNO_7))
-           (portRef C (instanceRef wb_dati_7_0_7))
-          ))
-          (net (rename wb_dati_7_0_a2_0_1_7 "wb_dati_7_0_a2_0_1[7]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_0_2_7))
-           (portRef D (instanceRef wb_dati_7_0_RNO_7))
-          ))
-          (net (rename wb_dati_7_0_a2_0_6 "wb_dati_7_0_a2_0[6]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_0_0_6))
-           (portRef D (instanceRef wb_dati_7_0_a2_6))
-           (portRef A (instanceRef wb_dati_7_0_0_RNO_7))
-          ))
-          (net N_576_i (joined
-           (portRef Z (instanceRef S_RNII9DO1_2_1))
-           (portRef SP (instanceRef CmdBitbangMXO2))
-           (portRef SP (instanceRef CmdExecMXO2))
-           (portRef SP (instanceRef CmdLEDGet))
-           (portRef SP (instanceRef CmdLEDSet))
-           (portRef SP (instanceRef CmdRWMaskSet))
-           (portRef SP (instanceRef CmdSetRWBankFFLED))
-           (portRef SP (instanceRef CmdSetRWBankFFMXO2))
-           (portRef SP (instanceRef CmdTout_2))
-           (portRef SP (instanceRef CmdTout_1))
-           (portRef SP (instanceRef CmdTout_0))
-           (portRef SP (instanceRef Dout_0io_7))
-           (portRef SP (instanceRef Dout_0io_6))
-           (portRef SP (instanceRef Dout_0io_5))
-           (portRef SP (instanceRef Dout_0io_4))
-           (portRef SP (instanceRef Dout_0io_3))
-           (portRef SP (instanceRef Dout_0io_2))
-           (portRef SP (instanceRef Dout_0io_1))
-           (portRef SP (instanceRef Dout_0io_0))
+          (net (rename RC_3_2 "RC_3[2]") (joined
+           (portRef (member rc_3 0) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RC_2))
           ))
           (net RDOE_i (joined
-           (portRef Z (instanceRef nWE80_pad_RNI3ICD))
+           (portRef RDOE_i_1z (instanceRef ram2e_ufm))
            (portRef T (instanceRef RD_pad_0))
            (portRef T (instanceRef RD_pad_1))
            (portRef T (instanceRef RD_pad_2))
@@ -3205,174 +4928,69 @@
            (portRef T (instanceRef RD_pad_6))
            (portRef T (instanceRef RD_pad_7))
           ))
-          (net N_6_i (joined
-           (portRef Z (instanceRef DOEEN_RNO))
-           (portRef D (instanceRef DOEEN))
+          (net N_263_i (joined
+           (portRef N_263_i_1z (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_3))
           ))
-          (net N_358_i (joined
-           (portRef Z (instanceRef DQMH_0io_RNO))
-           (portRef D (instanceRef DQMH_0io))
+          (net N_370_i (joined
+           (portRef N_370_i (instanceRef ram2e_ufm))
+           (portRef D (instanceRef nCAS))
           ))
-          (net N_28_i (joined
-           (portRef Z (instanceRef DQML_0io_RNO))
-           (portRef D (instanceRef DQML_0io))
+          (net N_359_i (joined
+           (portRef N_359_i (instanceRef ram2e_ufm))
+           (portRef D (instanceRef nRWE))
           ))
-          (net N_129_i (joined
-           (portRef Z (instanceRef S_RNO_3))
+          (net N_372_i (joined
+           (portRef N_372_i (instanceRef ram2e_ufm))
            (portRef D (instanceRef S_3))
           ))
-          (net N_131_i (joined
-           (portRef Z (instanceRef S_RNO_2))
+          (net N_361_i (joined
+           (portRef N_361_i (instanceRef ram2e_ufm))
            (portRef D (instanceRef S_2))
           ))
-          (net N_133_i (joined
-           (portRef Z (instanceRef S_RNO_1))
+          (net N_362_i (joined
+           (portRef N_362_i (instanceRef ram2e_ufm))
            (portRef D (instanceRef S_1))
           ))
-          (net N_561_i (joined
-           (portRef Z (instanceRef nCAS_0io_RNO))
-           (portRef D (instanceRef nCAS_0io))
-          ))
-          (net nRAS_2_iv_i (joined
-           (portRef Z (instanceRef nRAS_2_iv_i))
-           (portRef D (instanceRef nRAS_0io))
-          ))
-          (net N_559_i (joined
-           (portRef Z (instanceRef nCS_0io_RNO))
-           (portRef D (instanceRef nCS_0io))
-          ))
-          (net N_553_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_2))
-           (portRef D (instanceRef RA_0io_2))
-          ))
-          (net N_558_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_1))
-           (portRef D (instanceRef RA_0io_1))
-          ))
-          (net N_127_i (joined
-           (portRef Z (instanceRef RA_RNO_0))
-           (portRef D (instanceRef RA_0))
-          ))
-          (net N_59_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_9))
-           (portRef D (instanceRef RA_0io_9))
-          ))
-          (net N_49_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_8))
-           (portRef D (instanceRef RA_0io_8))
-          ))
-          (net N_549_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_7))
-           (portRef D (instanceRef RA_0io_7))
-          ))
-          (net N_550_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_6))
-           (portRef D (instanceRef RA_0io_6))
-          ))
-          (net N_551_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_4))
-           (portRef D (instanceRef RA_0io_4))
-          ))
-          (net N_552_i (joined
-           (portRef Z (instanceRef RA_RNO_3))
-           (portRef D (instanceRef RA_3))
-          ))
-          (net N_510_i (joined
-           (portRef Z (instanceRef CS_RNO_2))
-           (portRef D (instanceRef CS_2))
+          (net N_358_i (joined
+           (portRef N_358_i (instanceRef ram2e_ufm))
+           (portRef D (instanceRef nRAS))
           ))
           (net un1_CS_0_sqmuxa_i (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F))
+           (portRef un1_CS_0_sqmuxa_i (instanceRef ram2e_ufm))
            (portRef CD (instanceRef CS_2))
            (portRef CD (instanceRef CS_1))
            (portRef CD (instanceRef CS_0))
           ))
-          (net N_511_i (joined
-           (portRef Z (instanceRef CS_RNO_1))
-           (portRef D (instanceRef CS_1))
-          ))
-          (net N_504_i (joined
-           (portRef Z (instanceRef CS_RNO_0))
+          (net N_547_i (joined
+           (portRef N_547_i (instanceRef ram2e_ufm))
            (portRef D (instanceRef CS_0))
           ))
-          (net N_556_i (joined
-           (portRef Z (instanceRef CmdTout_RNO_2))
+          (net N_360_i (joined
+           (portRef N_360_i_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RC_0))
+          ))
+          (net N_369_i (joined
+           (portRef N_369_i_1z (instanceRef ram2e_ufm))
            (portRef D (instanceRef CmdTout_2))
           ))
-          (net N_555_i (joined
-           (portRef Z (instanceRef CmdTout_RNO_1))
+          (net N_368_i (joined
+           (portRef N_368_i_1z (instanceRef ram2e_ufm))
            (portRef D (instanceRef CmdTout_1))
           ))
-          (net wb_adr_0_sqmuxa_i (joined
-           (portRef Z (instanceRef wb_req_RNO_0))
-           (portRef SP (instanceRef wb_req))
+          (net N_225_i (joined
+           (portRef N_225_i_1z (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef BA_0io_1))
+           (portRef SP (instanceRef BA_0io_0))
           ))
-          (net (rename un1_wb_adr_0_sqmuxa_2_i_0 "un1_wb_adr_0_sqmuxa_2_i[0]") (joined
-           (portRef Z (instanceRef CmdBitbangMXO2_RNI8CSO1))
-           (portRef SP (instanceRef wb_adr_7))
-           (portRef SP (instanceRef wb_adr_6))
-           (portRef SP (instanceRef wb_adr_5))
-           (portRef SP (instanceRef wb_adr_4))
-           (portRef SP (instanceRef wb_adr_3))
-           (portRef SP (instanceRef wb_adr_2))
-           (portRef SP (instanceRef wb_adr_1))
-           (portRef SP (instanceRef wb_adr_0))
-           (portRef SP (instanceRef wb_dati_7))
-           (portRef SP (instanceRef wb_dati_6))
-           (portRef SP (instanceRef wb_dati_5))
-           (portRef SP (instanceRef wb_dati_4))
-           (portRef SP (instanceRef wb_dati_3))
-           (portRef SP (instanceRef wb_dati_2))
-           (portRef SP (instanceRef wb_dati_1))
-           (portRef SP (instanceRef wb_dati_0))
+          (net N_201_i (joined
+           (portRef N_201_i_1z (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef DQMH_0io))
+           (portRef SP (instanceRef DQML_0io))
           ))
-          (net (rename un1_wb_cyc_stb_0_sqmuxa_1_i_0 "un1_wb_cyc_stb_0_sqmuxa_1_i[0]") (joined
-           (portRef Z (instanceRef wb_we_RNO_0))
-           (portRef SP (instanceRef wb_we))
-          ))
-          (net N_39_i (joined
-           (portRef Z (instanceRef wb_adr_RNO_7))
-           (portRef D (instanceRef wb_adr_7))
-          ))
-          (net N_41_i (joined
-           (portRef Z (instanceRef wb_adr_RNO_3))
-           (portRef D (instanceRef wb_adr_3))
-          ))
-          (net N_43_i (joined
-           (portRef Z (instanceRef wb_adr_RNO_2))
-           (portRef D (instanceRef wb_adr_2))
-          ))
-          (net N_292_i (joined
-           (portRef Z (instanceRef RWMask_RNO_0))
-           (portRef D (instanceRef RWMask_0))
-          ))
-          (net N_291_i (joined
-           (portRef Z (instanceRef RWMask_RNO_1))
-           (portRef D (instanceRef RWMask_1))
-          ))
-          (net N_290_i (joined
-           (portRef Z (instanceRef RWMask_RNO_2))
-           (portRef D (instanceRef RWMask_2))
-          ))
-          (net N_289_i (joined
-           (portRef Z (instanceRef RWMask_RNO_3))
-           (portRef D (instanceRef RWMask_3))
-          ))
-          (net N_288_i (joined
-           (portRef Z (instanceRef RWMask_RNO_4))
-           (portRef D (instanceRef RWMask_4))
-          ))
-          (net N_287_i (joined
-           (portRef Z (instanceRef RWMask_RNO_5))
-           (portRef D (instanceRef RWMask_5))
-          ))
-          (net N_286_i (joined
-           (portRef Z (instanceRef RWMask_RNO_6))
-           (portRef D (instanceRef RWMask_6))
-          ))
-          (net un1_nCS61_1_i (joined
-           (portRef Z (instanceRef nRWE_r_0_RNO))
-           (portRef A (instanceRef nRWE_r_0))
+          (net N_507_i (joined
+           (portRef N_507_i_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef DQML_0io))
           ))
           (net (rename FS_cry_0 "FS_cry[0]") (joined
            (portRef COUT (instanceRef FS_cry_0_0))
@@ -3470,205 +5088,6 @@
            (portRef S0 (instanceRef FS_s_0_15))
            (portRef D (instanceRef FS_15))
           ))
-          (net wb_reqc_i (joined
-           (portRef Z (instanceRef wb_req_RNO))
-           (portRef D (instanceRef wb_req))
-          ))
-          (net wb_reqc_1 (joined
-           (portRef Z (instanceRef wb_reqc_1))
-           (portRef D (instanceRef RA_0io_RNO_11))
-           (portRef D (instanceRef CKE_6_iv_i_0_1))
-           (portRef D (instanceRef wb_req_RNO))
-           (portRef D (instanceRef S_RNO_1))
-           (portRef D (instanceRef RA_0io_RNO_9))
-           (portRef D (instanceRef CmdBitbangMXO2_RNI8CSO1))
-           (portRef D (instanceRef wb_we_RNO_0))
-           (portRef A (instanceRef wb_reqc_1_RNIEO5C1))
-           (portRef B (instanceRef wb_req_RNO_0))
-           (portRef B (instanceRef FS_RNI5OOF1_15))
-           (portRef D (instanceRef wb_reqc_1_RNIRU4M1))
-          ))
-          (net CKE_6_iv_i_a2_0 (joined
-           (portRef Z (instanceRef CKE_6_iv_i_0_1_RNO))
-           (portRef A (instanceRef CKE_6_iv_i_0_1))
-          ))
-          (net wb_adr_7_5_214_a2_2_0 (joined
-           (portRef Z (instanceRef wb_adr_RNO_3_1))
-           (portRef D (instanceRef wb_adr_RNO_1_1))
-          ))
-          (net DQML_s_i_a2_0 (joined
-           (portRef Z (instanceRef DQML_0io_RNO_0))
-           (portRef A (instanceRef DQML_0io_RNO))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_2_2 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_2_4 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_2))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_1_2 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_1_4 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_1))
-          ))
-          (net (rename S_s_0_1_0 "S_s_0_1[0]") (joined
-           (portRef Z (instanceRef S_s_0_1_0))
-           (portRef D (instanceRef S_s_0_0))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_1 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_2))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_3_0 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_0))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_3_2 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_4_2 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_4_4 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_4))
-          ))
-          (net CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0 (joined
-           (portRef Z (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0))
-           (portRef B (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0))
-          ))
-          (net wb_adr_7_5_214_0_1 (joined
-           (portRef Z (instanceRef wb_adr_RNO_1_1))
-           (portRef D (instanceRef wb_adr_RNO_1))
-          ))
-          (net CmdLEDGet_4_u_0_0_a2_0_2 (joined
-           (portRef Z (instanceRef CmdLEDGet_4_u_0_0_a2_0_2))
-           (portRef B (instanceRef CmdLEDGet_4_u_0_0_0))
-          ))
-          (net wb_we_7_iv_0_0_0_1 (joined
-           (portRef Z (instanceRef wb_we_RNO_2))
-           (portRef D (instanceRef wb_we_RNO))
-          ))
-          (net (rename wb_adr_7_0_a2_5_0_0 "wb_adr_7_0_a2_5_0[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_a2_5_0_0))
-           (portRef D (instanceRef wb_adr_7_0_1_0))
-          ))
-          (net (rename wb_adr_7_0_a2_0_0 "wb_adr_7_0_a2_0[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_a2_0_0_0))
-           (portRef D (instanceRef wb_adr_7_0_0_0))
-          ))
-          (net (rename wb_dati_7_0_a2_4_0_7 "wb_dati_7_0_a2_4_0[7]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0_RNO_7))
-           (portRef D (instanceRef wb_dati_7_0_0_7))
-          ))
-          (net (rename wb_dati_7_0_a2_2_0_1 "wb_dati_7_0_a2_2_0[1]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_2_0_1))
-           (portRef D (instanceRef wb_dati_7_0_0_1))
-          ))
-          (net CmdBitbangMXO2_4_u_0_0_a2_0_1 (joined
-           (portRef Z (instanceRef CmdBitbangMXO2_4_u_0_0_a2_0_1))
-           (portRef B (instanceRef CmdBitbangMXO2_4_u_0_0_0))
-          ))
-          (net CKE_6_iv_i_0_1 (joined
-           (portRef Z (instanceRef CKE_6_iv_i_0_1))
-           (portRef A (instanceRef CKE_6_iv_i_0))
-          ))
-          (net (rename un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0 "un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0]") (joined
-           (portRef Z (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0))
-           (portRef D (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0))
-          ))
-          (net (rename wb_dati_7_0_a2_1_0 "wb_dati_7_0_a2_1[0]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_1_0_0))
-           (portRef D (instanceRef wb_dati_7_0_0))
-          ))
-          (net (rename un1_RWMask_0_sqmuxa_1_i_a2_0_1_0 "un1_RWMask_0_sqmuxa_1_i_a2_0_1[0]") (joined
-           (portRef Z (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0))
-           (portRef D (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0))
-          ))
-          (net Ready_0_sqmuxa_0_a2_6_a2_2 (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4))
-          ))
-          (net Ready_0_sqmuxa_0_a2_6_a2_4 (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a2_6_a2))
-          ))
-          (net nCS_6_u_i_a2_1 (joined
-           (portRef Z (instanceRef nCS_6_u_i_a2_1_0))
-           (portRef D (instanceRef nCS_6_u_i_1))
-          ))
-          (net (rename wb_dati_7_0_a2_2_1_3 "wb_dati_7_0_a2_2_1[3]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_2_RNO_3))
-           (portRef D (instanceRef wb_dati_7_0_2_3))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_0 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_0))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_2))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_2 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_2))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_3 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_3))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F))
-          ))
-          (net (rename wb_dati_7_0_0_1 "wb_dati_7_0_0[1]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0_1))
-           (portRef D (instanceRef wb_dati_7_0_1))
-          ))
-          (net (rename wb_dati_7_0_o2_0_2 "wb_dati_7_0_o2_0[2]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_o2_0_2))
-           (portRef D (instanceRef wb_dati_7_0_2))
-           (portRef D (instanceRef wb_dati_7_0_5))
-          ))
-          (net nCAS_s_i_tz_0 (joined
-           (portRef Z (instanceRef nCAS_0io_RNO_0))
-           (portRef D (instanceRef nCAS_0io_RNO))
-          ))
-          (net (rename wb_dati_7_0_1_6 "wb_dati_7_0_1[6]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_1_6))
-           (portRef C (instanceRef wb_dati_7_0_6))
-          ))
-          (net (rename wb_dati_7_0_0_7 "wb_dati_7_0_0[7]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0_7))
-           (portRef D (instanceRef wb_dati_7_0_7))
-          ))
-          (net (rename wb_dati_7_0_0_3 "wb_dati_7_0_0[3]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0_3))
-           (portRef B (instanceRef wb_dati_7_0_3))
-          ))
-          (net (rename wb_dati_7_0_2_3 "wb_dati_7_0_2[3]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_2_3))
-           (portRef C (instanceRef wb_dati_7_0_3))
-          ))
-          (net nCS_6_u_i_0 (joined
-           (portRef Z (instanceRef nCS_6_u_i_0))
-           (portRef B (instanceRef nCS_0io_RNO))
-          ))
-          (net (rename wb_adr_7_0_0_0 "wb_adr_7_0_0[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_0_0))
-           (portRef C (instanceRef wb_adr_7_0_4_0))
-          ))
-          (net (rename wb_adr_7_0_1_0 "wb_adr_7_0_1[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_1_0))
-           (portRef D (instanceRef wb_adr_7_0_4_0))
-          ))
-          (net (rename wb_adr_7_0_4_0 "wb_adr_7_0_4[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_4_0))
-           (portRef D (instanceRef wb_adr_7_0_0))
-          ))
-          (net (rename wb_dati_7_0_0_4 "wb_dati_7_0_0[4]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0_4))
-           (portRef D (instanceRef wb_dati_7_0_4))
-          ))
           (net (rename FS_cry_0_S0_0 "FS_cry_0_S0[0]") (joined
            (portRef S0 (instanceRef FS_cry_0_0))
           ))
@@ -3678,42 +5097,45 @@
           (net (rename FS_s_0_COUT_15 "FS_s_0_COUT[15]") (joined
            (portRef COUT (instanceRef FS_s_0_15))
           ))
-          (net (rename Dout_0__CN "Dout_0_.CN") (joined
-           (portRef Z (instanceRef Vout_0__CN))
-           (portRef SCLK (instanceRef Dout_0io_7))
-           (portRef SCLK (instanceRef Dout_0io_6))
-           (portRef SCLK (instanceRef Dout_0io_5))
-           (portRef SCLK (instanceRef Dout_0io_4))
-           (portRef SCLK (instanceRef Dout_0io_3))
-           (portRef SCLK (instanceRef Dout_0io_2))
-           (portRef SCLK (instanceRef Dout_0io_1))
-           (portRef SCLK (instanceRef Dout_0io_0))
-           (portRef SCLK (instanceRef Vout_0io_7))
-           (portRef SCLK (instanceRef Vout_0io_6))
-           (portRef SCLK (instanceRef Vout_0io_5))
-           (portRef SCLK (instanceRef Vout_0io_4))
-           (portRef SCLK (instanceRef Vout_0io_3))
-           (portRef SCLK (instanceRef Vout_0io_2))
-           (portRef SCLK (instanceRef Vout_0io_1))
-           (portRef SCLK (instanceRef Vout_0io_0))
+          (net (rename CKEout_CN "CKEout.CN") (joined
+           (portRef Z (instanceRef nCASout_CN))
+           (portRef SCLK (instanceRef CKEout_0io))
+           (portRef SCLK (instanceRef RAout_0io_11))
+           (portRef SCLK (instanceRef RAout_0io_10))
+           (portRef SCLK (instanceRef RAout_0io_9))
+           (portRef SCLK (instanceRef RAout_0io_8))
+           (portRef SCLK (instanceRef RAout_0io_7))
+           (portRef SCLK (instanceRef RAout_0io_6))
+           (portRef SCLK (instanceRef RAout_0io_5))
+           (portRef SCLK (instanceRef RAout_0io_4))
+           (portRef SCLK (instanceRef RAout_0io_3))
+           (portRef SCLK (instanceRef RAout_0io_2))
+           (portRef SCLK (instanceRef RAout_0io_1))
+           (portRef SCLK (instanceRef RAout_0io_0))
+           (portRef SCLK (instanceRef nCASout_0io))
+           (portRef SCLK (instanceRef nRASout_0io))
+           (portRef SCLK (instanceRef nRWEout_0io))
           ))
           (net VCC (joined
            (portRef Z (instanceRef VCC))
            (portRef B0 (instanceRef FS_cry_0_0))
-           (portRef SP (instanceRef BA_0io_1))
-           (portRef SP (instanceRef BA_0io_0))
-           (portRef SP (instanceRef CKE_0io))
-           (portRef SP (instanceRef DQMH_0io))
-           (portRef SP (instanceRef DQML_0io))
-           (portRef SP (instanceRef RA_0io_11))
-           (portRef SP (instanceRef RA_0io_10))
-           (portRef SP (instanceRef RA_0io_9))
-           (portRef SP (instanceRef RA_0io_8))
-           (portRef SP (instanceRef nCAS_0io))
-           (portRef SP (instanceRef nCS_0io))
-           (portRef SP (instanceRef nRAS_0io))
-           (portRef SP (instanceRef nRWE_0io))
-           (portRef SP (instanceRef PHI1reg_0io))
+           (portRef SP (instanceRef CKEout_0io))
+           (portRef SP (instanceRef RAout_0io_11))
+           (portRef SP (instanceRef RAout_0io_10))
+           (portRef SP (instanceRef RAout_0io_9))
+           (portRef SP (instanceRef RAout_0io_8))
+           (portRef SP (instanceRef RAout_0io_7))
+           (portRef SP (instanceRef RAout_0io_6))
+           (portRef SP (instanceRef RAout_0io_5))
+           (portRef SP (instanceRef RAout_0io_4))
+           (portRef SP (instanceRef RAout_0io_3))
+           (portRef SP (instanceRef RAout_0io_2))
+           (portRef SP (instanceRef RAout_0io_1))
+           (portRef SP (instanceRef RAout_0io_0))
+           (portRef SP (instanceRef nCASout_0io))
+           (portRef SP (instanceRef nRASout_0io))
+           (portRef SP (instanceRef nRWEout_0io))
+           (portRef SP (instanceRef PHI1r_0io))
            (portRef GSR (instanceRef GSR_INST))
           ))
           (net GND (joined
@@ -3773,27 +5195,22 @@
            (portRef D0 (instanceRef FS_s_0_15))
            (portRef C0 (instanceRef FS_s_0_15))
            (portRef B0 (instanceRef FS_s_0_15))
-           (portRef CD (instanceRef CKE_0io))
+           (portRef I (instanceRef nCSout_pad))
+           (portRef CD (instanceRef CKEout_0io))
            (portRef PD (instanceRef DQMH_0io))
            (portRef PD (instanceRef DQML_0io))
-           (portRef CD (instanceRef Dout_0io_7))
-           (portRef CD (instanceRef Dout_0io_6))
-           (portRef CD (instanceRef Dout_0io_5))
-           (portRef CD (instanceRef Dout_0io_4))
-           (portRef CD (instanceRef Dout_0io_3))
-           (portRef CD (instanceRef Dout_0io_2))
-           (portRef CD (instanceRef Dout_0io_1))
-           (portRef CD (instanceRef Dout_0io_0))
-           (portRef CD (instanceRef RA_0io_11))
-           (portRef CD (instanceRef RA_0io_10))
-           (portRef CD (instanceRef RA_0io_9))
-           (portRef CD (instanceRef RA_0io_8))
-           (portRef CD (instanceRef RA_0io_7))
-           (portRef CD (instanceRef RA_0io_6))
-           (portRef CD (instanceRef RA_0io_5))
-           (portRef CD (instanceRef RA_0io_4))
-           (portRef CD (instanceRef RA_0io_2))
-           (portRef CD (instanceRef RA_0io_1))
+           (portRef CD (instanceRef RAout_0io_11))
+           (portRef CD (instanceRef RAout_0io_10))
+           (portRef CD (instanceRef RAout_0io_9))
+           (portRef CD (instanceRef RAout_0io_8))
+           (portRef CD (instanceRef RAout_0io_7))
+           (portRef CD (instanceRef RAout_0io_6))
+           (portRef CD (instanceRef RAout_0io_5))
+           (portRef CD (instanceRef RAout_0io_4))
+           (portRef CD (instanceRef RAout_0io_3))
+           (portRef CD (instanceRef RAout_0io_2))
+           (portRef CD (instanceRef RAout_0io_1))
+           (portRef CD (instanceRef RAout_0io_0))
            (portRef CD (instanceRef Vout_0io_7))
            (portRef CD (instanceRef Vout_0io_6))
            (portRef CD (instanceRef Vout_0io_5))
@@ -3802,25 +5219,22 @@
            (portRef CD (instanceRef Vout_0io_2))
            (portRef CD (instanceRef Vout_0io_1))
            (portRef CD (instanceRef Vout_0io_0))
-           (portRef PD (instanceRef nCAS_0io))
-           (portRef PD (instanceRef nCS_0io))
-           (portRef PD (instanceRef nRAS_0io))
-           (portRef PD (instanceRef nRWE_0io))
-           (portRef CD (instanceRef PHI1reg_0io))
+           (portRef PD (instanceRef nCASout_0io))
+           (portRef PD (instanceRef nRASout_0io))
+           (portRef PD (instanceRef nRWEout_0io))
+           (portRef CD (instanceRef PHI1r_0io))
           ))
           (net C14M_c (joined
            (portRef O (instanceRef C14M_pad))
-           (portRef C14M_c (instanceRef ufmefb))
+           (portRef C14M_c (instanceRef ram2e_ufm))
+           (portRef CK (instanceRef CKE))
            (portRef CK (instanceRef CS_2))
            (portRef CK (instanceRef CS_1))
            (portRef CK (instanceRef CS_0))
-           (portRef CK (instanceRef CmdBitbangMXO2))
-           (portRef CK (instanceRef CmdExecMXO2))
            (portRef CK (instanceRef CmdLEDGet))
            (portRef CK (instanceRef CmdLEDSet))
            (portRef CK (instanceRef CmdRWMaskSet))
            (portRef CK (instanceRef CmdSetRWBankFFLED))
-           (portRef CK (instanceRef CmdSetRWBankFFMXO2))
            (portRef CK (instanceRef CmdTout_2))
            (portRef CK (instanceRef CmdTout_1))
            (portRef CK (instanceRef CmdTout_0))
@@ -3841,9 +5255,21 @@
            (portRef CK (instanceRef FS_2))
            (portRef CK (instanceRef FS_1))
            (portRef CK (instanceRef FS_0))
-           (portRef CK (instanceRef LEDEN))
+           (portRef CK (instanceRef RA_11))
+           (portRef CK (instanceRef RA_10))
+           (portRef CK (instanceRef RA_9))
+           (portRef CK (instanceRef RA_8))
+           (portRef CK (instanceRef RA_7))
+           (portRef CK (instanceRef RA_6))
+           (portRef CK (instanceRef RA_5))
+           (portRef CK (instanceRef RA_4))
            (portRef CK (instanceRef RA_3))
+           (portRef CK (instanceRef RA_2))
+           (portRef CK (instanceRef RA_1))
            (portRef CK (instanceRef RA_0))
+           (portRef CK (instanceRef RC_2))
+           (portRef CK (instanceRef RC_1))
+           (portRef CK (instanceRef RC_0))
            (portRef CK (instanceRef RWBank_7))
            (portRef CK (instanceRef RWBank_6))
            (portRef CK (instanceRef RWBank_5))
@@ -3852,61 +5278,30 @@
            (portRef CK (instanceRef RWBank_2))
            (portRef CK (instanceRef RWBank_1))
            (portRef CK (instanceRef RWBank_0))
-           (portRef CK (instanceRef RWMask_7))
-           (portRef CK (instanceRef RWMask_6))
-           (portRef CK (instanceRef RWMask_5))
-           (portRef CK (instanceRef RWMask_4))
-           (portRef CK (instanceRef RWMask_3))
-           (portRef CK (instanceRef RWMask_2))
-           (portRef CK (instanceRef RWMask_1))
-           (portRef CK (instanceRef RWMask_0))
            (portRef CK (instanceRef RWSel))
            (portRef CK (instanceRef Ready))
            (portRef CK (instanceRef S_3))
            (portRef CK (instanceRef S_2))
            (portRef CK (instanceRef S_1))
            (portRef CK (instanceRef S_0))
-           (portRef CK (instanceRef wb_adr_7))
-           (portRef CK (instanceRef wb_adr_6))
-           (portRef CK (instanceRef wb_adr_5))
-           (portRef CK (instanceRef wb_adr_4))
-           (portRef CK (instanceRef wb_adr_3))
-           (portRef CK (instanceRef wb_adr_2))
-           (portRef CK (instanceRef wb_adr_1))
-           (portRef CK (instanceRef wb_adr_0))
-           (portRef CK (instanceRef wb_cyc_stb))
-           (portRef CK (instanceRef wb_dati_7))
-           (portRef CK (instanceRef wb_dati_6))
-           (portRef CK (instanceRef wb_dati_5))
-           (portRef CK (instanceRef wb_dati_4))
-           (portRef CK (instanceRef wb_dati_3))
-           (portRef CK (instanceRef wb_dati_2))
-           (portRef CK (instanceRef wb_dati_1))
-           (portRef CK (instanceRef wb_dati_0))
-           (portRef CK (instanceRef wb_req))
-           (portRef CK (instanceRef wb_rst))
-           (portRef CK (instanceRef wb_we))
+           (portRef CK (instanceRef VOEEN))
+           (portRef CK (instanceRef nCAS))
+           (portRef CK (instanceRef nRAS))
+           (portRef CK (instanceRef nRWE))
            (portRef SCLK (instanceRef BA_0io_1))
            (portRef SCLK (instanceRef BA_0io_0))
-           (portRef SCLK (instanceRef CKE_0io))
            (portRef SCLK (instanceRef DQMH_0io))
            (portRef SCLK (instanceRef DQML_0io))
-           (portRef SCLK (instanceRef RA_0io_11))
-           (portRef SCLK (instanceRef RA_0io_10))
-           (portRef SCLK (instanceRef RA_0io_9))
-           (portRef SCLK (instanceRef RA_0io_8))
-           (portRef SCLK (instanceRef RA_0io_7))
-           (portRef SCLK (instanceRef RA_0io_6))
-           (portRef SCLK (instanceRef RA_0io_5))
-           (portRef SCLK (instanceRef RA_0io_4))
-           (portRef SCLK (instanceRef RA_0io_2))
-           (portRef SCLK (instanceRef RA_0io_1))
-           (portRef SCLK (instanceRef nCAS_0io))
-           (portRef SCLK (instanceRef nCS_0io))
-           (portRef SCLK (instanceRef nRAS_0io))
-           (portRef SCLK (instanceRef nRWE_0io))
-           (portRef SCLK (instanceRef PHI1reg_0io))
-           (portRef A (instanceRef Vout_0__CN))
+           (portRef SCLK (instanceRef Vout_0io_7))
+           (portRef SCLK (instanceRef Vout_0io_6))
+           (portRef SCLK (instanceRef Vout_0io_5))
+           (portRef SCLK (instanceRef Vout_0io_4))
+           (portRef SCLK (instanceRef Vout_0io_3))
+           (portRef SCLK (instanceRef Vout_0io_2))
+           (portRef SCLK (instanceRef Vout_0io_1))
+           (portRef SCLK (instanceRef Vout_0io_0))
+           (portRef SCLK (instanceRef PHI1r_0io))
+           (portRef A (instanceRef nCASout_CN))
           ))
           (net C14M (joined
            (portRef C14M)
@@ -3915,15 +5310,15 @@
           (net PHI1_c (joined
            (portRef O (instanceRef PHI1_pad))
            (portRef A (instanceRef SZ0Z_1))
-           (portRef I (instanceRef nVOE_pad))
-           (portRef D (instanceRef PHI1reg_0io))
+           (portRef A (instanceRef nVOE_pad_RNO))
+           (portRef D (instanceRef PHI1r_0io))
           ))
           (net PHI1 (joined
            (portRef PHI1)
            (portRef I (instanceRef PHI1_pad))
           ))
           (net LED_c (joined
-           (portRef Z (instanceRef LED_pad_RNO))
+           (portRef LED_c (instanceRef ram2e_ufm))
            (portRef I (instanceRef LED_pad))
           ))
           (net LED (joined
@@ -3932,29 +5327,18 @@
           ))
           (net nWE_c (joined
            (portRef O (instanceRef nWE_pad))
-           (portRef D (instanceRef RWSel_2))
-           (portRef C (instanceRef nDOE_pad_RNO))
+           (portRef nWE_c (instanceRef ram2e_ufm))
           ))
           (net nWE (joined
            (portRef nWE)
            (portRef I (instanceRef nWE_pad))
           ))
-          (net nWE80_c (joined
-           (portRef O (instanceRef nWE80_pad))
-           (portRef B (instanceRef nWE80_pad_RNI3ICD))
-           (portRef D (instanceRef nRWE_r_0))
-          ))
           (net nWE80 (joined
            (portRef nWE80)
-           (portRef I (instanceRef nWE80_pad))
           ))
           (net nEN80_c (joined
            (portRef O (instanceRef nEN80_pad))
-           (portRef A (instanceRef nWE80_pad_RNI3ICD))
-           (portRef B (instanceRef LED_pad_RNO))
-           (portRef B (instanceRef nDOE_pad_RNO))
-           (portRef D (instanceRef nCS_6_u_i_0))
-           (portRef A (instanceRef CKE_6_iv_i_0_1_RNO))
+           (portRef nEN80_c (instanceRef ram2e_ufm))
           ))
           (net nEN80 (joined
            (portRef nEN80)
@@ -3962,7 +5346,7 @@
           ))
           (net nC07X_c (joined
            (portRef O (instanceRef nC07X_pad))
-           (portRef C (instanceRef RWSel_2))
+           (portRef nC07X_c (instanceRef ram2e_ufm))
           ))
           (net nC07X (joined
            (portRef nC07X)
@@ -3970,7 +5354,7 @@
           ))
           (net (rename Ain_c_0 "Ain_c[0]") (joined
            (portRef O (instanceRef Ain_pad_0))
-           (portRef A (instanceRef RA_RNO_0))
+           (portRef (member ain_c 7) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_0 "Ain[0]") (joined
            (portRef (member ain 7))
@@ -3978,7 +5362,7 @@
           ))
           (net (rename Ain_c_1 "Ain_c[1]") (joined
            (portRef O (instanceRef Ain_pad_1))
-           (portRef A (instanceRef RA_0io_RNO_1))
+           (portRef (member ain_c 6) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_1 "Ain[1]") (joined
            (portRef (member ain 6))
@@ -3986,7 +5370,7 @@
           ))
           (net (rename Ain_c_2 "Ain_c[2]") (joined
            (portRef O (instanceRef Ain_pad_2))
-           (portRef A (instanceRef RA_0io_RNO_2))
+           (portRef (member ain_c 5) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_2 "Ain[2]") (joined
            (portRef (member ain 5))
@@ -3994,7 +5378,7 @@
           ))
           (net (rename Ain_c_3 "Ain_c[3]") (joined
            (portRef O (instanceRef Ain_pad_3))
-           (portRef A (instanceRef RA_RNO_3))
+           (portRef (member ain_c 4) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_3 "Ain[3]") (joined
            (portRef (member ain 4))
@@ -4002,7 +5386,7 @@
           ))
           (net (rename Ain_c_4 "Ain_c[4]") (joined
            (portRef O (instanceRef Ain_pad_4))
-           (portRef A (instanceRef RA_0io_RNO_4))
+           (portRef (member ain_c 3) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_4 "Ain[4]") (joined
            (portRef (member ain 3))
@@ -4010,7 +5394,7 @@
           ))
           (net (rename Ain_c_5 "Ain_c[5]") (joined
            (portRef O (instanceRef Ain_pad_5))
-           (portRef A (instanceRef RA_42_3_0_5))
+           (portRef (member ain_c 2) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_5 "Ain[5]") (joined
            (portRef (member ain 2))
@@ -4018,7 +5402,7 @@
           ))
           (net (rename Ain_c_6 "Ain_c[6]") (joined
            (portRef O (instanceRef Ain_pad_6))
-           (portRef A (instanceRef RA_0io_RNO_6))
+           (portRef (member ain_c 1) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_6 "Ain[6]") (joined
            (portRef (member ain 1))
@@ -4026,7 +5410,7 @@
           ))
           (net (rename Ain_c_7 "Ain_c[7]") (joined
            (portRef O (instanceRef Ain_pad_7))
-           (portRef A (instanceRef RA_0io_RNO_7))
+           (portRef (member ain_c 0) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_7 "Ain[7]") (joined
            (portRef (member ain 0))
@@ -4034,20 +5418,7 @@
           ))
           (net (rename Din_c_0 "Din_c[0]") (joined
            (portRef O (instanceRef Din_pad_0))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_0))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_17))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_16))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_13))
-           (portRef A (instanceRef LEDEN_RNO))
-           (portRef A (instanceRef CmdBitbangMXO2_4_u_0_0_a2_0_1))
-           (portRef A (instanceRef RWMask_RNO_0))
-           (portRef A (instanceRef CmdLEDGet_4_u_0_0_a2_0_2))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_2))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_15))
-           (portRef A (instanceRef RWBank_5_0_0))
-           (portRef A (instanceRef wb_we_RNO_2))
-           (portRef A (instanceRef wb_adr_7_0_0_0))
-           (portRef I (instanceRef RD_pad_0))
+           (portRef (member din_c 7) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_0 "Din[0]") (joined
            (portRef (member din 7))
@@ -4055,20 +5426,7 @@
           ))
           (net (rename Din_c_1 "Din_c[1]") (joined
            (portRef O (instanceRef Din_pad_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_0))
-           (portRef C (instanceRef CmdBitbangMXO2_4_u_0_0_a2_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_11))
-           (portRef A (instanceRef RWMask_RNO_1))
-           (portRef B (instanceRef CmdLEDGet_4_u_0_0_a2_0_2))
-           (portRef A (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_15))
-           (portRef A (instanceRef RWBank_5_0_1))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o2_0))
-           (portRef A (instanceRef CmdLEDSet_4_u_0_0_a2_0))
-           (portRef A (instanceRef wb_adr_RNO_1))
-           (portRef A (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_0))
-           (portRef I (instanceRef RD_pad_1))
+           (portRef (member din_c 6) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_1 "Din[1]") (joined
            (portRef (member din 6))
@@ -4076,17 +5434,7 @@
           ))
           (net (rename Din_c_2 "Din_c[2]") (joined
            (portRef O (instanceRef Din_pad_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_0))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_17))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_16))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_13))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_12))
-           (portRef B (instanceRef CmdBitbangMXO2_4_u_0_0_a2_0_1))
-           (portRef A (instanceRef wb_adr_RNO_2))
-           (portRef A (instanceRef RWMask_RNO_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_15))
-           (portRef A (instanceRef RWBank_5_0_2))
-           (portRef I (instanceRef RD_pad_2))
+           (portRef (member din_c 5) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_2 "Din[2]") (joined
            (portRef (member din 5))
@@ -4094,17 +5442,7 @@
           ))
           (net (rename Din_c_3 "Din_c[3]") (joined
            (portRef O (instanceRef Din_pad_3))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_0))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_17))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_16))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_12))
-           (portRef C (instanceRef CmdBitbangMXO2_4_u_0_0_a2_0_1))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6))
-           (portRef A (instanceRef wb_adr_RNO_3))
-           (portRef A (instanceRef RWMask_RNO_3))
-           (portRef A (instanceRef RWBank_5_0_3))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4))
-           (portRef I (instanceRef RD_pad_3))
+           (portRef (member din_c 4) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_3 "Din[3]") (joined
            (portRef (member din 4))
@@ -4112,19 +5450,7 @@
           ))
           (net (rename Din_c_4 "Din_c[4]") (joined
            (portRef O (instanceRef Din_pad_4))
-           (portRef B (instanceRef CmdBitbangMXO2_4_u_0_0_a2_1))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_11))
-           (portRef A (instanceRef wb_adr_RNO_4))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6))
-           (portRef A (instanceRef RWMask_RNO_4))
-           (portRef C (instanceRef CmdLEDGet_4_u_0_0_a2_0_2))
-           (portRef B (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_2))
-           (portRef A (instanceRef RWBank_5_0_4))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2))
-           (portRef B (instanceRef CmdLEDSet_4_u_0_0_a2_0))
-           (portRef B (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_0))
-           (portRef I (instanceRef RD_pad_4))
+           (portRef (member din_c 3) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_4 "Din[4]") (joined
            (portRef (member din 3))
@@ -4132,14 +5458,7 @@
           ))
           (net (rename Din_c_5 "Din_c[5]") (joined
            (portRef O (instanceRef Din_pad_5))
-           (portRef A (instanceRef wb_adr_RNO_5))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_7))
-           (portRef A (instanceRef RWMask_RNO_5))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_2))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_2))
-           (portRef A (instanceRef RWBank_5_0_5))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_2))
-           (portRef I (instanceRef RD_pad_5))
+           (portRef (member din_c 2) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_5 "Din[5]") (joined
            (portRef (member din 2))
@@ -4147,15 +5466,7 @@
           ))
           (net (rename Din_c_6 "Din_c[6]") (joined
            (portRef O (instanceRef Din_pad_6))
-           (portRef A (instanceRef wb_adr_RNO_6))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6))
-           (portRef A (instanceRef RWMask_RNO_6))
-           (portRef A (instanceRef RWBank_5_0_6))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_10))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_1))
-           (portRef I (instanceRef RD_pad_6))
+           (portRef (member din_c 1) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_6 "Din[6]") (joined
            (portRef (member din 1))
@@ -4163,85 +5474,46 @@
           ))
           (net (rename Din_c_7 "Din_c[7]") (joined
            (portRef O (instanceRef Din_pad_7))
-           (portRef A (instanceRef RWMask_RNO_7))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_7))
-           (portRef A (instanceRef wb_adr_RNO_7))
-           (portRef A (instanceRef RWBank_5_0_0_7))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_2))
-           (portRef I (instanceRef RD_pad_7))
+           (portRef (member din_c 0) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_7 "Din[7]") (joined
            (portRef (member din 0))
            (portRef I (instanceRef Din_pad_7))
           ))
-          (net (rename Dout_c_0 "Dout_c[0]") (joined
-           (portRef Q (instanceRef Dout_0io_0))
-           (portRef I (instanceRef Dout_pad_0))
-          ))
           (net (rename Dout_0 "Dout[0]") (joined
            (portRef O (instanceRef Dout_pad_0))
            (portRef (member dout 7))
           ))
-          (net (rename Dout_c_1 "Dout_c[1]") (joined
-           (portRef Q (instanceRef Dout_0io_1))
-           (portRef I (instanceRef Dout_pad_1))
-          ))
           (net (rename Dout_1 "Dout[1]") (joined
            (portRef O (instanceRef Dout_pad_1))
            (portRef (member dout 6))
           ))
-          (net (rename Dout_c_2 "Dout_c[2]") (joined
-           (portRef Q (instanceRef Dout_0io_2))
-           (portRef I (instanceRef Dout_pad_2))
-          ))
           (net (rename Dout_2 "Dout[2]") (joined
            (portRef O (instanceRef Dout_pad_2))
            (portRef (member dout 5))
           ))
-          (net (rename Dout_c_3 "Dout_c[3]") (joined
-           (portRef Q (instanceRef Dout_0io_3))
-           (portRef I (instanceRef Dout_pad_3))
-          ))
           (net (rename Dout_3 "Dout[3]") (joined
            (portRef O (instanceRef Dout_pad_3))
            (portRef (member dout 4))
           ))
-          (net (rename Dout_c_4 "Dout_c[4]") (joined
-           (portRef Q (instanceRef Dout_0io_4))
-           (portRef I (instanceRef Dout_pad_4))
-          ))
           (net (rename Dout_4 "Dout[4]") (joined
            (portRef O (instanceRef Dout_pad_4))
            (portRef (member dout 3))
           ))
-          (net (rename Dout_c_5 "Dout_c[5]") (joined
-           (portRef Q (instanceRef Dout_0io_5))
-           (portRef I (instanceRef Dout_pad_5))
-          ))
           (net (rename Dout_5 "Dout[5]") (joined
            (portRef O (instanceRef Dout_pad_5))
            (portRef (member dout 2))
           ))
-          (net (rename Dout_c_6 "Dout_c[6]") (joined
-           (portRef Q (instanceRef Dout_0io_6))
-           (portRef I (instanceRef Dout_pad_6))
-          ))
           (net (rename Dout_6 "Dout[6]") (joined
            (portRef O (instanceRef Dout_pad_6))
            (portRef (member dout 1))
           ))
-          (net (rename Dout_c_7 "Dout_c[7]") (joined
-           (portRef Q (instanceRef Dout_0io_7))
-           (portRef I (instanceRef Dout_pad_7))
-          ))
           (net (rename Dout_7 "Dout[7]") (joined
            (portRef O (instanceRef Dout_pad_7))
            (portRef (member dout 0))
           ))
           (net nDOE_c (joined
-           (portRef Z (instanceRef nDOE_pad_RNO))
+           (portRef nDOE_c (instanceRef ram2e_ufm))
            (portRef I (instanceRef nDOE_pad))
           ))
           (net nDOE (joined
@@ -4312,49 +5584,49 @@
            (portRef O (instanceRef Vout_pad_7))
            (portRef (member vout 0))
           ))
+          (net nVOE_c (joined
+           (portRef Z (instanceRef nVOE_pad_RNO))
+           (portRef I (instanceRef nVOE_pad))
+          ))
           (net nVOE (joined
            (portRef O (instanceRef nVOE_pad))
            (portRef nVOE)
           ))
-          (net CKE_c (joined
-           (portRef Q (instanceRef CKE_0io))
-           (portRef I (instanceRef CKE_pad))
+          (net CKEout_c (joined
+           (portRef Q (instanceRef CKEout_0io))
+           (portRef I (instanceRef CKEout_pad))
           ))
-          (net CKE (joined
-           (portRef O (instanceRef CKE_pad))
-           (portRef CKE)
+          (net CKEout (joined
+           (portRef O (instanceRef CKEout_pad))
+           (portRef CKEout)
           ))
-          (net nCS_c (joined
-           (portRef Q (instanceRef nCS_0io))
-           (portRef I (instanceRef nCS_pad))
+          (net nCSout (joined
+           (portRef O (instanceRef nCSout_pad))
+           (portRef nCSout)
           ))
-          (net nCS (joined
-           (portRef O (instanceRef nCS_pad))
-           (portRef nCS)
+          (net nRASout_c (joined
+           (portRef Q (instanceRef nRASout_0io))
+           (portRef I (instanceRef nRASout_pad))
           ))
-          (net nRAS_c (joined
-           (portRef Q (instanceRef nRAS_0io))
-           (portRef I (instanceRef nRAS_pad))
+          (net nRASout (joined
+           (portRef O (instanceRef nRASout_pad))
+           (portRef nRASout)
           ))
-          (net nRAS (joined
-           (portRef O (instanceRef nRAS_pad))
-           (portRef nRAS)
+          (net nCASout_c (joined
+           (portRef Q (instanceRef nCASout_0io))
+           (portRef I (instanceRef nCASout_pad))
           ))
-          (net nCAS_c (joined
-           (portRef Q (instanceRef nCAS_0io))
-           (portRef I (instanceRef nCAS_pad))
+          (net nCASout (joined
+           (portRef O (instanceRef nCASout_pad))
+           (portRef nCASout)
           ))
-          (net nCAS (joined
-           (portRef O (instanceRef nCAS_pad))
-           (portRef nCAS)
+          (net nRWEout_c (joined
+           (portRef Q (instanceRef nRWEout_0io))
+           (portRef I (instanceRef nRWEout_pad))
           ))
-          (net nRWE_c (joined
-           (portRef Q (instanceRef nRWE_0io))
-           (portRef I (instanceRef nRWE_pad))
-          ))
-          (net nRWE (joined
-           (portRef O (instanceRef nRWE_pad))
-           (portRef nRWE)
+          (net nRWEout (joined
+           (portRef O (instanceRef nRWEout_pad))
+           (portRef nRWEout)
           ))
           (net (rename BA_c_0 "BA_c[0]") (joined
            (portRef Q (instanceRef BA_0io_0))
@@ -4372,175 +5644,101 @@
            (portRef O (instanceRef BA_pad_1))
            (portRef (member ba 0))
           ))
-          (net (rename RA_c_0 "RA_c[0]") (joined
-           (portRef Q (instanceRef RA_0))
-           (portRef A (instanceRef RWSel_2))
-           (portRef I (instanceRef RA_pad_0))
+          (net (rename RAout_c_0 "RAout_c[0]") (joined
+           (portRef Q (instanceRef RAout_0io_0))
+           (portRef I (instanceRef RAout_pad_0))
           ))
-          (net (rename RA_0 "RA[0]") (joined
-           (portRef O (instanceRef RA_pad_0))
-           (portRef (member ra 11))
+          (net (rename RAout_0 "RAout[0]") (joined
+           (portRef O (instanceRef RAout_pad_0))
+           (portRef (member raout 11))
           ))
-          (net (rename RA_c_1 "RA_c[1]") (joined
-           (portRef Q (instanceRef RA_0io_1))
-           (portRef I (instanceRef RA_pad_1))
+          (net (rename RAout_c_1 "RAout_c[1]") (joined
+           (portRef Q (instanceRef RAout_0io_1))
+           (portRef I (instanceRef RAout_pad_1))
           ))
-          (net (rename RA_1 "RA[1]") (joined
-           (portRef O (instanceRef RA_pad_1))
-           (portRef (member ra 10))
+          (net (rename RAout_1 "RAout[1]") (joined
+           (portRef O (instanceRef RAout_pad_1))
+           (portRef (member raout 10))
           ))
-          (net (rename RA_c_2 "RA_c[2]") (joined
-           (portRef Q (instanceRef RA_0io_2))
-           (portRef I (instanceRef RA_pad_2))
+          (net (rename RAout_c_2 "RAout_c[2]") (joined
+           (portRef Q (instanceRef RAout_0io_2))
+           (portRef I (instanceRef RAout_pad_2))
           ))
-          (net (rename RA_2 "RA[2]") (joined
-           (portRef O (instanceRef RA_pad_2))
-           (portRef (member ra 9))
+          (net (rename RAout_2 "RAout[2]") (joined
+           (portRef O (instanceRef RAout_pad_2))
+           (portRef (member raout 9))
           ))
-          (net (rename RA_c_3 "RA_c[3]") (joined
-           (portRef Q (instanceRef RA_3))
-           (portRef B (instanceRef RWSel_2))
-           (portRef I (instanceRef RA_pad_3))
+          (net (rename RAout_c_3 "RAout_c[3]") (joined
+           (portRef Q (instanceRef RAout_0io_3))
+           (portRef I (instanceRef RAout_pad_3))
           ))
-          (net (rename RA_3 "RA[3]") (joined
-           (portRef O (instanceRef RA_pad_3))
-           (portRef (member ra 8))
+          (net (rename RAout_3 "RAout[3]") (joined
+           (portRef O (instanceRef RAout_pad_3))
+           (portRef (member raout 8))
           ))
-          (net (rename RA_c_4 "RA_c[4]") (joined
-           (portRef Q (instanceRef RA_0io_4))
-           (portRef I (instanceRef RA_pad_4))
+          (net (rename RAout_c_4 "RAout_c[4]") (joined
+           (portRef Q (instanceRef RAout_0io_4))
+           (portRef I (instanceRef RAout_pad_4))
           ))
-          (net (rename RA_4 "RA[4]") (joined
-           (portRef O (instanceRef RA_pad_4))
-           (portRef (member ra 7))
+          (net (rename RAout_4 "RAout[4]") (joined
+           (portRef O (instanceRef RAout_pad_4))
+           (portRef (member raout 7))
           ))
-          (net (rename RA_c_5 "RA_c[5]") (joined
-           (portRef Q (instanceRef RA_0io_5))
-           (portRef I (instanceRef RA_pad_5))
+          (net (rename RAout_c_5 "RAout_c[5]") (joined
+           (portRef Q (instanceRef RAout_0io_5))
+           (portRef I (instanceRef RAout_pad_5))
           ))
-          (net (rename RA_5 "RA[5]") (joined
-           (portRef O (instanceRef RA_pad_5))
-           (portRef (member ra 6))
+          (net (rename RAout_5 "RAout[5]") (joined
+           (portRef O (instanceRef RAout_pad_5))
+           (portRef (member raout 6))
           ))
-          (net (rename RA_c_6 "RA_c[6]") (joined
-           (portRef Q (instanceRef RA_0io_6))
-           (portRef I (instanceRef RA_pad_6))
+          (net (rename RAout_c_6 "RAout_c[6]") (joined
+           (portRef Q (instanceRef RAout_0io_6))
+           (portRef I (instanceRef RAout_pad_6))
           ))
-          (net (rename RA_6 "RA[6]") (joined
-           (portRef O (instanceRef RA_pad_6))
-           (portRef (member ra 5))
+          (net (rename RAout_6 "RAout[6]") (joined
+           (portRef O (instanceRef RAout_pad_6))
+           (portRef (member raout 5))
           ))
-          (net (rename RA_c_7 "RA_c[7]") (joined
-           (portRef Q (instanceRef RA_0io_7))
-           (portRef I (instanceRef RA_pad_7))
+          (net (rename RAout_c_7 "RAout_c[7]") (joined
+           (portRef Q (instanceRef RAout_0io_7))
+           (portRef I (instanceRef RAout_pad_7))
           ))
-          (net (rename RA_7 "RA[7]") (joined
-           (portRef O (instanceRef RA_pad_7))
-           (portRef (member ra 4))
+          (net (rename RAout_7 "RAout[7]") (joined
+           (portRef O (instanceRef RAout_pad_7))
+           (portRef (member raout 4))
           ))
-          (net (rename RA_c_8 "RA_c[8]") (joined
-           (portRef Q (instanceRef RA_0io_8))
-           (portRef I (instanceRef RA_pad_8))
+          (net (rename RAout_c_8 "RAout_c[8]") (joined
+           (portRef Q (instanceRef RAout_0io_8))
+           (portRef I (instanceRef RAout_pad_8))
           ))
-          (net (rename RA_8 "RA[8]") (joined
-           (portRef O (instanceRef RA_pad_8))
-           (portRef (member ra 3))
+          (net (rename RAout_8 "RAout[8]") (joined
+           (portRef O (instanceRef RAout_pad_8))
+           (portRef (member raout 3))
           ))
-          (net (rename RA_c_9 "RA_c[9]") (joined
-           (portRef Q (instanceRef RA_0io_9))
-           (portRef I (instanceRef RA_pad_9))
+          (net (rename RAout_c_9 "RAout_c[9]") (joined
+           (portRef Q (instanceRef RAout_0io_9))
+           (portRef I (instanceRef RAout_pad_9))
           ))
-          (net (rename RA_9 "RA[9]") (joined
-           (portRef O (instanceRef RA_pad_9))
-           (portRef (member ra 2))
+          (net (rename RAout_9 "RAout[9]") (joined
+           (portRef O (instanceRef RAout_pad_9))
+           (portRef (member raout 2))
           ))
-          (net (rename RA_c_10 "RA_c[10]") (joined
-           (portRef Q (instanceRef RA_0io_10))
-           (portRef I (instanceRef RA_pad_10))
+          (net (rename RAout_c_10 "RAout_c[10]") (joined
+           (portRef Q (instanceRef RAout_0io_10))
+           (portRef I (instanceRef RAout_pad_10))
           ))
-          (net (rename RA_10 "RA[10]") (joined
-           (portRef O (instanceRef RA_pad_10))
-           (portRef (member ra 1))
+          (net (rename RAout_10 "RAout[10]") (joined
+           (portRef O (instanceRef RAout_pad_10))
+           (portRef (member raout 1))
           ))
-          (net (rename RA_c_11 "RA_c[11]") (joined
-           (portRef Q (instanceRef RA_0io_11))
-           (portRef I (instanceRef RA_pad_11))
+          (net (rename RAout_c_11 "RAout_c[11]") (joined
+           (portRef Q (instanceRef RAout_0io_11))
+           (portRef I (instanceRef RAout_pad_11))
           ))
-          (net (rename RA_11 "RA[11]") (joined
-           (portRef O (instanceRef RA_pad_11))
-           (portRef (member ra 0))
-          ))
-          (net (rename RD_in_0 "RD_in[0]") (joined
-           (portRef O (instanceRef RD_pad_0))
-           (portRef D (instanceRef Dout_0io_0))
-           (portRef D (instanceRef Vout_0io_0))
-          ))
-          (net (rename RD_0 "RD[0]") (joined
-           (portRef B (instanceRef RD_pad_0))
-           (portRef (member rd 7))
-          ))
-          (net (rename RD_in_1 "RD_in[1]") (joined
-           (portRef O (instanceRef RD_pad_1))
-           (portRef D (instanceRef Dout_0io_1))
-           (portRef D (instanceRef Vout_0io_1))
-          ))
-          (net (rename RD_1 "RD[1]") (joined
-           (portRef B (instanceRef RD_pad_1))
-           (portRef (member rd 6))
-          ))
-          (net (rename RD_in_2 "RD_in[2]") (joined
-           (portRef O (instanceRef RD_pad_2))
-           (portRef D (instanceRef Dout_0io_2))
-           (portRef D (instanceRef Vout_0io_2))
-          ))
-          (net (rename RD_2 "RD[2]") (joined
-           (portRef B (instanceRef RD_pad_2))
-           (portRef (member rd 5))
-          ))
-          (net (rename RD_in_3 "RD_in[3]") (joined
-           (portRef O (instanceRef RD_pad_3))
-           (portRef D (instanceRef Dout_0io_3))
-           (portRef D (instanceRef Vout_0io_3))
-          ))
-          (net (rename RD_3 "RD[3]") (joined
-           (portRef B (instanceRef RD_pad_3))
-           (portRef (member rd 4))
-          ))
-          (net (rename RD_in_4 "RD_in[4]") (joined
-           (portRef O (instanceRef RD_pad_4))
-           (portRef D (instanceRef Dout_0io_4))
-           (portRef D (instanceRef Vout_0io_4))
-          ))
-          (net (rename RD_4 "RD[4]") (joined
-           (portRef B (instanceRef RD_pad_4))
-           (portRef (member rd 3))
-          ))
-          (net (rename RD_in_5 "RD_in[5]") (joined
-           (portRef O (instanceRef RD_pad_5))
-           (portRef D (instanceRef Dout_0io_5))
-           (portRef D (instanceRef Vout_0io_5))
-          ))
-          (net (rename RD_5 "RD[5]") (joined
-           (portRef B (instanceRef RD_pad_5))
-           (portRef (member rd 2))
-          ))
-          (net (rename RD_in_6 "RD_in[6]") (joined
-           (portRef O (instanceRef RD_pad_6))
-           (portRef D (instanceRef Dout_0io_6))
-           (portRef D (instanceRef Vout_0io_6))
-          ))
-          (net (rename RD_6 "RD[6]") (joined
-           (portRef B (instanceRef RD_pad_6))
-           (portRef (member rd 1))
-          ))
-          (net (rename RD_in_7 "RD_in[7]") (joined
-           (portRef O (instanceRef RD_pad_7))
-           (portRef D (instanceRef Dout_0io_7))
-           (portRef D (instanceRef Vout_0io_7))
-          ))
-          (net (rename RD_7 "RD[7]") (joined
-           (portRef B (instanceRef RD_pad_7))
-           (portRef (member rd 0))
+          (net (rename RAout_11 "RAout[11]") (joined
+           (portRef O (instanceRef RAout_pad_11))
+           (portRef (member raout 0))
           ))
           (net DQML_c (joined
            (portRef Q (instanceRef DQML_0io))
@@ -4558,14 +5756,110 @@
            (portRef O (instanceRef DQMH_pad))
            (portRef DQMH)
           ))
-          (net N_876_0 (joined
+          (net (rename RD_in_0 "RD_in[0]") (joined
+           (portRef O (instanceRef RD_pad_0))
+           (portRef I (instanceRef Dout_pad_0))
+           (portRef D (instanceRef Vout_0io_0))
+          ))
+          (net (rename RD_0 "RD[0]") (joined
+           (portRef B (instanceRef RD_pad_0))
+           (portRef (member rd 7))
+          ))
+          (net (rename RD_in_1 "RD_in[1]") (joined
+           (portRef O (instanceRef RD_pad_1))
+           (portRef I (instanceRef Dout_pad_1))
+           (portRef D (instanceRef Vout_0io_1))
+          ))
+          (net (rename RD_1 "RD[1]") (joined
+           (portRef B (instanceRef RD_pad_1))
+           (portRef (member rd 6))
+          ))
+          (net (rename RD_in_2 "RD_in[2]") (joined
+           (portRef O (instanceRef RD_pad_2))
+           (portRef I (instanceRef Dout_pad_2))
+           (portRef D (instanceRef Vout_0io_2))
+          ))
+          (net (rename RD_2 "RD[2]") (joined
+           (portRef B (instanceRef RD_pad_2))
+           (portRef (member rd 5))
+          ))
+          (net (rename RD_in_3 "RD_in[3]") (joined
+           (portRef O (instanceRef RD_pad_3))
+           (portRef I (instanceRef Dout_pad_3))
+           (portRef D (instanceRef Vout_0io_3))
+          ))
+          (net (rename RD_3 "RD[3]") (joined
+           (portRef B (instanceRef RD_pad_3))
+           (portRef (member rd 4))
+          ))
+          (net (rename RD_in_4 "RD_in[4]") (joined
+           (portRef O (instanceRef RD_pad_4))
+           (portRef I (instanceRef Dout_pad_4))
+           (portRef D (instanceRef Vout_0io_4))
+          ))
+          (net (rename RD_4 "RD[4]") (joined
+           (portRef B (instanceRef RD_pad_4))
+           (portRef (member rd 3))
+          ))
+          (net (rename RD_in_5 "RD_in[5]") (joined
+           (portRef O (instanceRef RD_pad_5))
+           (portRef I (instanceRef Dout_pad_5))
+           (portRef D (instanceRef Vout_0io_5))
+          ))
+          (net (rename RD_5 "RD[5]") (joined
+           (portRef B (instanceRef RD_pad_5))
+           (portRef (member rd 2))
+          ))
+          (net (rename RD_in_6 "RD_in[6]") (joined
+           (portRef O (instanceRef RD_pad_6))
+           (portRef I (instanceRef Dout_pad_6))
+           (portRef D (instanceRef Vout_0io_6))
+          ))
+          (net (rename RD_6 "RD[6]") (joined
+           (portRef B (instanceRef RD_pad_6))
+           (portRef (member rd 1))
+          ))
+          (net (rename RD_in_7 "RD_in[7]") (joined
+           (portRef O (instanceRef RD_pad_7))
+           (portRef I (instanceRef Dout_pad_7))
+           (portRef D (instanceRef Vout_0io_7))
+          ))
+          (net (rename RD_7 "RD[7]") (joined
+           (portRef B (instanceRef RD_pad_7))
+           (portRef (member rd 0))
+          ))
+          (net N_1080_0 (joined
+           (portRef Z (instanceRef DOEEN_RNO))
+           (portRef CD (instanceRef DOEEN))
+          ))
+          (net N_1026_0 (joined
            (portRef Z (instanceRef Ready_RNO))
            (portRef D (instanceRef Ready))
           ))
-          (net N_566_i (joined
-           (portRef Z (instanceRef wb_reqc_1_RNIEO5C1))
-           (portRef CD (instanceRef BA_0io_1))
-           (portRef CD (instanceRef BA_0io_0))
+          (net N_1078_0 (joined
+           (portRef Z (instanceRef VOEEN_RNO))
+           (portRef CD (instanceRef VOEEN))
+          ))
+          (net N_187_i (joined
+           (portRef N_187_i_1z (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef CmdLEDGet))
+           (portRef SP (instanceRef CmdLEDSet))
+           (portRef SP (instanceRef CmdRWMaskSet))
+           (portRef SP (instanceRef CmdSetRWBankFFLED))
+           (portRef SP (instanceRef RWBank_7))
+           (portRef SP (instanceRef RWBank_6))
+           (portRef SP (instanceRef RWBank_5))
+           (portRef SP (instanceRef RWBank_4))
+           (portRef SP (instanceRef RWBank_3))
+           (portRef SP (instanceRef RWBank_2))
+           (portRef SP (instanceRef RWBank_1))
+           (portRef SP (instanceRef RWBank_0))
+          ))
+          (net N_185_i (joined
+           (portRef N_185_i (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef CmdTout_2))
+           (portRef SP (instanceRef CmdTout_1))
+           (portRef SP (instanceRef CmdTout_0))
           ))
           (net N_1 (joined
            (portRef CIN (instanceRef FS_cry_0_0))
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.jed b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.jed
index 0dfa0e2..d2f5e23 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.jed
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.jed
@@ -2,7 +2,7 @@
 NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
 NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
 NOTE All Rights Reserved.*
-NOTE DATE CREATED:	Thu Sep 21 05:35:22 2023*
+NOTE DATE CREATED:	Thu Dec 28 23:10:30 2023*
 NOTE DESIGN NAME:	RAM2E_LCMXO2_1200HC_impl1.ncd*
 NOTE DEVICE NAME:	LCMXO2-1200HC-4TQFP100*
 NOTE JEDEC FILE STATUS:	Final   Version 1.95*
@@ -10,8 +10,6 @@ NOTE PIN ASSIGNMENTS*
 NOTE PINS RD[0] : 36 : inout*
 NOTE PINS LED : 35 : out*
 NOTE PINS C14M : 62 : in*
-NOTE PINS DQMH : 49 : out*
-NOTE PINS DQML : 48 : out*
 NOTE PINS RD[7] : 43 : inout*
 NOTE PINS RD[6] : 42 : inout*
 NOTE PINS RD[5] : 41 : inout*
@@ -19,25 +17,27 @@ NOTE PINS RD[4] : 40 : inout*
 NOTE PINS RD[3] : 39 : inout*
 NOTE PINS RD[2] : 38 : inout*
 NOTE PINS RD[1] : 37 : inout*
-NOTE PINS RA[11] : 59 : out*
-NOTE PINS RA[10] : 64 : out*
-NOTE PINS RA[9] : 63 : out*
-NOTE PINS RA[8] : 65 : out*
-NOTE PINS RA[7] : 67 : out*
-NOTE PINS RA[6] : 69 : out*
-NOTE PINS RA[5] : 71 : out*
-NOTE PINS RA[4] : 75 : out*
-NOTE PINS RA[3] : 74 : out*
-NOTE PINS RA[2] : 70 : out*
-NOTE PINS RA[1] : 68 : out*
-NOTE PINS RA[0] : 66 : out*
+NOTE PINS DQMH : 49 : out*
+NOTE PINS DQML : 48 : out*
+NOTE PINS RAout[11] : 59 : out*
+NOTE PINS RAout[10] : 64 : out*
+NOTE PINS RAout[9] : 63 : out*
+NOTE PINS RAout[8] : 65 : out*
+NOTE PINS RAout[7] : 67 : out*
+NOTE PINS RAout[6] : 69 : out*
+NOTE PINS RAout[5] : 71 : out*
+NOTE PINS RAout[4] : 75 : out*
+NOTE PINS RAout[3] : 74 : out*
+NOTE PINS RAout[2] : 70 : out*
+NOTE PINS RAout[1] : 68 : out*
+NOTE PINS RAout[0] : 66 : out*
 NOTE PINS BA[1] : 60 : out*
 NOTE PINS BA[0] : 58 : out*
-NOTE PINS nRWE : 51 : out*
-NOTE PINS nCAS : 52 : out*
-NOTE PINS nRAS : 54 : out*
-NOTE PINS nCS : 57 : out*
-NOTE PINS CKE : 53 : out*
+NOTE PINS nRWEout : 51 : out*
+NOTE PINS nCASout : 52 : out*
+NOTE PINS nRASout : 54 : out*
+NOTE PINS nCSout : 57 : out*
+NOTE PINS CKEout : 53 : out*
 NOTE PINS nVOE : 10 : out*
 NOTE PINS Vout[7] : 12 : out*
 NOTE PINS Vout[6] : 14 : out*
@@ -74,7 +74,6 @@ NOTE PINS Ain[1] : 2 : in*
 NOTE PINS Ain[0] : 3 : in*
 NOTE PINS nC07X : 34 : in*
 NOTE PINS nEN80 : 82 : in*
-NOTE PINS nWE80 : 83 : in*
 NOTE PINS nWE : 29 : in*
 NOTE PINS PHI1 : 85 : in*
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 *
 NOTE END CONFIG DATA*
-L71296
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@@ -2776,10 +2775,10 @@ L302720
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 *
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 NOTE User Electronic Signature Data*
 UH00000000*
-B0F1
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diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.mrp b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.mrp
index 17ee0c9..601f775 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.mrp
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.mrp
@@ -15,24 +15,24 @@ Target Vendor:  LATTICE
 Target Device:  LCMXO2-1200HCTQFP100
 Target Performance:   4
 Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  09/21/23  05:34:46
+Mapped on:  12/28/23  23:09:57
 
 Design Summary
 --------------
 
-   Number of registers:    111 out of  1520 (7%)
-      PFU registers:           75 out of  1280 (6%)
-      PIO registers:           36 out of   240 (15%)
-   Number of SLICEs:       120 out of   640 (19%)
-      SLICEs as Logic/ROM:    120 out of   640 (19%)
+   Number of registers:    122 out of  1520 (8%)
+      PFU registers:           93 out of  1280 (7%)
+      PIO registers:           29 out of   240 (12%)
+   Number of SLICEs:       148 out of   640 (23%)
+      SLICEs as Logic/ROM:    148 out of   640 (23%)
       SLICEs as RAM:            0 out of   480 (0%)
       SLICEs as Carry:          9 out of   640 (1%)
-   Number of LUT4s:        239 out of  1280 (19%)
-      Number used as logic LUTs:        221
+   Number of LUT4s:        296 out of  1280 (23%)
+      Number used as logic LUTs:        278
       Number used as distributed RAM:     0
       Number used as ripple logic:       18
       Number used as shift registers:     0
-   Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
+   Number of PIO sites used: 69 + 4(JTAG) out of 80 (91%)
    Number of block RAMs:  0 out of 7 (0%)
    Number of GSRs:        0 out of 1 (0%)
    EFB used :        Yes
@@ -58,64 +58,82 @@ Design Summary
       2. Number of logic LUT4s does not include count of distributed RAM and
      ripple logic.
    Number of clocks:  1
-     Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
-   Number of Clock Enables:  11
+     Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M )
+   Number of Clock Enables:  14
 
                                     Page 1
 
 
 
 
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
 
 Design Summary (cont)
 ---------------------
-     Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
-     Net N_576_i: 17 loads, 9 LSLICEs
-     Net LEDEN13: 4 loads, 4 LSLICEs
-     Net nCS61: 1 loads, 1 LSLICEs
+     Net N_225_i: 2 loads, 0 LSLICEs
+     Net N_201_i: 2 loads, 0 LSLICEs
+     Net N_187_i: 11 loads, 11 LSLICEs
+     Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
+     Net RC12: 2 loads, 2 LSLICEs
+     Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs
+     Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs
+     Net N_185_i: 2 loads, 2 LSLICEs
+     Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs
+     Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs
+     Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs
+     Net N_126: 6 loads, 6 LSLICEs
+     Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs
      Net Vout3: 8 loads, 0 LSLICEs
-     Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
-     Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
-     Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
-     Net N_104: 1 loads, 1 LSLICEs
-     Net N_88: 4 loads, 4 LSLICEs
-     Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
-   Number of LSRs:  5
+   Number of LSRs:  7
      Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
+     Net BA_0_sqmuxa: 2 loads, 0 LSLICEs
      Net S[2]: 1 loads, 1 LSLICEs
-     Net N_566_i: 2 loads, 0 LSLICEs
-     Net wb_rst: 1 loads, 0 LSLICEs
-     Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
+     Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
+     Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs
+     Net N_1080_0: 1 loads, 1 LSLICEs
+     Net N_1078_0: 1 loads, 1 LSLICEs
    Number of nets driven by tri-state buffers:  0
    Top 10 highest fanout non-clock nets:
-     Net S[2]: 48 loads
-     Net S[3]: 48 loads
-     Net S[0]: 30 loads
-     Net FS[12]: 22 loads
-     Net FS[9]: 21 loads
-     Net S[1]: 21 loads
-     Net FS[10]: 20 loads
-     Net FS[11]: 19 loads
-     Net RWSel: 19 loads
-     Net FS[13]: 17 loads
+     Net S[2]: 50 loads
+     Net S[3]: 45 loads
+     Net S[0]: 37 loads
+     Net S[1]: 34 loads
+     Net FS[12]: 24 loads
+     Net FS[11]: 22 loads
+     Net FS[10]: 19 loads
+     Net FS[13]: 19 loads
+     Net FS[9]: 19 loads
+     Net FS[8]: 18 loads
 
 
 
 
-   Number of warnings:  1
+   Number of warnings:  3
    Number of errors:    0
      
 
 Design Errors/Warnings
 ----------------------
 
+WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(93): Semantic
+     error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
+     "nWE80" does not exist in the design. This preference has been disabled.
 WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
      temporarily disable certain features of the device including Power
      Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
      Functionality is restored after the Flash Memory (UFM/Configuration)
      Interface is disabled using Disable Configuration Interface command 0x26
      followed by Bypass command 0xFF. 
+WARNING - map: IO buffer missing for top level port nWE80...logic will be
+     discarded.
+
+                                    Page 2
+
+
+
+
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
+
 
 IO (PIO) Attributes
 -------------------
@@ -126,24 +144,10 @@ IO (PIO) Attributes
 +---------------------+-----------+-----------+------------+
 | RD[0]               | BIDIR     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-
-                                    Page 2
-
-
-
-
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
-
-IO (PIO) Attributes (cont)
---------------------------
 | LED                 | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | C14M                | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| DQML                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
 | RD[7]               | BIDIR     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | RD[6]               | BIDIR     | LVCMOS33  |            |
@@ -158,39 +162,35 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | RD[1]               | BIDIR     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| RA[11]              | OUTPUT    | LVCMOS33  | OUT        |
+| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[10]              | OUTPUT    | LVCMOS33  | OUT        |
+| DQML                | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[9]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[11]           | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[8]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[10]           | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[7]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[9]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[6]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[8]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[5]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[7]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[4]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[6]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[3]               | OUTPUT    | LVCMOS33  |            |
+| RAout[5]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[2]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[4]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[1]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[3]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[0]               | OUTPUT    | LVCMOS33  |            |
+| RAout[2]            | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RAout[1]            | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RAout[0]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | BA[1]               | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| BA[0]               | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nRWE                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nCAS                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nRAS                | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 
                                     Page 3
@@ -198,13 +198,21 @@ IO (PIO) Attributes (cont)
 
 
 
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
 
 IO (PIO) Attributes (cont)
 --------------------------
-| nCS                 | OUTPUT    | LVCMOS33  | OUT        |
+| BA[0]               | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| CKE                 | OUTPUT    | LVCMOS33  | OUT        |
+| nRWEout             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nCASout             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRASout             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nCSout              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| CKEout              | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | nVOE                | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -226,21 +234,21 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | nDOE                | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[7]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[7]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[6]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[6]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[5]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[5]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[4]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[4]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[3]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[3]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[2]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[2]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[1]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[1]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[0]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[0]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Din[7]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -250,6 +258,16 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | Din[4]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
+
+                                    Page 4
+
+
+
+
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
+
+IO (PIO) Attributes (cont)
+--------------------------
 | Din[3]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Din[2]              | INPUT     | LVCMOS33  |            |
@@ -258,16 +276,6 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | Din[0]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-
-                                    Page 4
-
-
-
-
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
-
-IO (PIO) Attributes (cont)
---------------------------
 | Ain[7]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Ain[6]              | INPUT     | LVCMOS33  |            |
@@ -288,8 +296,6 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | nEN80               | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| nWE80               | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
 | nWE                 | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | PHI1                | INPUT     | LVCMOS33  | IN         |
@@ -299,77 +305,84 @@ Removed logic
 -------------
 
 Block GSR_INST undriven or does not drive anything - clipped.
-Signal Dout_0_.CN was merged into signal C14M_c
-Signal GND undriven or does not drive anything - clipped.
-Signal ufmefb/VCC undriven or does not drive anything - clipped.
-Signal ufmefb/GND undriven or does not drive anything - clipped.
+Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
+Block ram2e_ufm/GND undriven or does not drive anything - clipped.
+Signal CKEout.CN was merged into signal C14M_c
+Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
 Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
 Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
-Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
-Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
-Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
-Signal ufmefb/TCOC undriven or does not drive anything - clipped.
-Signal ufmefb/TCINT undriven or does not drive anything - clipped.
-Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
-Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
 
                                     Page 5
 
 
 
 
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
 
 Removed logic (cont)
 --------------------
-Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
-Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
-Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
+     
+Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
+     
+Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
 Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
 Signal N_1 undriven or does not drive anything - clipped.
-Block Vout_0_.CN was optimized away.
-Block GND was optimized away.
-Block ufmefb/VCC was optimized away.
-Block ufmefb/GND was optimized away.
+Block nCASout.CN was optimized away.
+Block ram2e_ufm/ufmefb/VCC was optimized away.
+Block ram2e_ufm/ufmefb/GND was optimized away.
 
      
 
@@ -377,8 +390,18 @@ Embedded Functional Block Connection Summary
 --------------------------------------------
 
    Desired WISHBONE clock frequency: 14.4 MHz
+
+                                    Page 6
+
+
+
+
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
+
+Embedded Functional Block Connection Summary (cont)
+---------------------------------------------------
    Clock source:                     C14M_c
-   Reset source:                     wb_rst
+   Reset source:                     ram2e_ufm/wb_rst
    Functions mode:
       I2C #1 (Primary) Function:     DISABLED
       I2C #2 (Secondary) Function:   DISABLED
@@ -390,16 +413,6 @@ Embedded Functional Block Connection Summary
       PLL1 Connection:               DISABLED
    I2C Function Summary:
    --------------------
-
-                                    Page 6
-
-
-
-
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
-
-Embedded Functional Block Connection Summary (cont)
----------------------------------------------------
       None
    SPI Function Summary:
    --------------------
@@ -424,7 +437,7 @@ Embedded Functional Block Connection Summary (cont)
 ASIC Components
 ---------------
 
-Instance Name: ufmefb/EFBInst_0
+Instance Name: ram2e_ufm/ufmefb/EFBInst_0
          Type: EFB
 
 Run Time and Memory Usage
@@ -432,23 +445,10 @@ Run Time and Memory Usage
 
    Total CPU Time: 1 secs  
    Total REAL Time: 0 secs  
-   Peak Memory Usage: 63 MB
+   Peak Memory Usage: 64 MB
         
 
 
-
-
-
-
-
-
-
-
-
-
-
-
-
 
 
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.pad b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.pad
index 403e6ba..ce4877b 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.pad
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.pad
@@ -6,7 +6,7 @@ Performance Grade:      4
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.44
 
-Thu Sep 21 05:34:59 2023
+Thu Dec 28 23:10:10 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -23,7 +23,7 @@ Pinout by Port Name:
 | BA[0]     | 58/1     | LVCMOS33_OUT  | PR9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | BA[1]     | 60/1     | LVCMOS33_OUT  | PR8C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | C14M      | 62/1     | LVCMOS33_IN   | PR5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| CKE       | 53/1     | LVCMOS33_OUT  | PR9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| CKEout    | 53/1     | LVCMOS33_OUT  | PR9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | DQMH      | 49/2     | LVCMOS33_OUT  | PB20D |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | DQML      | 48/2     | LVCMOS33_OUT  | PB20C |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | Din[0]    | 96/0     | LVCMOS33_IN   | PT10B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
@@ -34,28 +34,28 @@ Pinout by Port Name:
 | Din[5]    | 99/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 | Din[6]    | 88/0     | LVCMOS33_IN   | PT12A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 | Din[7]    | 87/0     | LVCMOS33_IN   | PT12B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL10D |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL10C |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL9B  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6C  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | LED       | 35/2     | LVCMOS33_OUT  | PB9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | PHI1      | 85/0     | LVCMOS33_IN   | PT12D |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| RA[0]     | 66/1     | LVCMOS33_OUT  | PR4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[10]    | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[11]    | 59/1     | LVCMOS33_OUT  | PR8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[1]     | 68/1     | LVCMOS33_OUT  | PR4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[2]     | 70/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[3]     | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[4]     | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[5]     | 71/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[6]     | 69/1     | LVCMOS33_OUT  | PR4A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[7]     | 67/1     | LVCMOS33_OUT  | PR4C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[8]     | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[9]     | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[0]  | 66/1     | LVCMOS33_OUT  | PR4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[10] | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[11] | 59/1     | LVCMOS33_OUT  | PR8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[1]  | 68/1     | LVCMOS33_OUT  | PR4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[2]  | 70/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[3]  | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[4]  | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[5]  | 71/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[6]  | 69/1     | LVCMOS33_OUT  | PR4A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[7]  | 67/1     | LVCMOS33_OUT  | PR4C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[8]  | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[9]  | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | RD[0]     | 36/2     | LVCMOS33_BIDI | PB11C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[1]     | 37/2     | LVCMOS33_BIDI | PB11D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[2]     | 38/2     | LVCMOS33_BIDI | PB11A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
@@ -73,15 +73,14 @@ Pinout by Port Name:
 | Vout[6]   | 14/3     | LVCMOS33_OUT  | PL5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | Vout[7]   | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nC07X     | 34/2     | LVCMOS33_IN   | PB9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nCAS      | 52/1     | LVCMOS33_OUT  | PR10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nCS       | 57/1     | LVCMOS33_OUT  | PR9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nCASout   | 52/1     | LVCMOS33_OUT  | PR10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nCSout    | 57/1     | LVCMOS33_OUT  | PR9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nDOE      | 20/3     | LVCMOS33_OUT  | PL9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nEN80     | 82/0     | LVCMOS33_IN   | PT15C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nRAS      | 54/1     | LVCMOS33_OUT  | PR9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nRWE      | 51/1     | LVCMOS33_OUT  | PR10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRASout   | 54/1     | LVCMOS33_OUT  | PR9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWEout   | 51/1     | LVCMOS33_OUT  | PR10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nVOE      | 10/3     | LVCMOS33_OUT  | PL4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nWE       | 29/2     | LVCMOS33_IN   | PB6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nWE80     | 83/0     | LVCMOS33_IN   | PT15B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
 
 Vccio by Bank:
@@ -144,33 +143,33 @@ Pinout by Pin Number:
 | 47/2     |     unused, PULL:DOWN |            |               | PB18D |               |           |           |
 | 48/2     | DQML                  | LOCATED    | LVCMOS33_OUT  | PB20C | SN            |           |           |
 | 49/2     | DQMH                  | LOCATED    | LVCMOS33_OUT  | PB20D | SI/SISPI      |           |           |
-| 51/1     | nRWE                  | LOCATED    | LVCMOS33_OUT  | PR10D | DQ1           |           |           |
-| 52/1     | nCAS                  | LOCATED    | LVCMOS33_OUT  | PR10C | DQ1           |           |           |
-| 53/1     | CKE                   | LOCATED    | LVCMOS33_OUT  | PR9D  | DQ1           |           |           |
-| 54/1     | nRAS                  | LOCATED    | LVCMOS33_OUT  | PR9C  | DQ1           |           |           |
-| 57/1     | nCS                   | LOCATED    | LVCMOS33_OUT  | PR9B  | DQ1           |           |           |
+| 51/1     | nRWEout               | LOCATED    | LVCMOS33_OUT  | PR10D | DQ1           |           |           |
+| 52/1     | nCASout               | LOCATED    | LVCMOS33_OUT  | PR10C | DQ1           |           |           |
+| 53/1     | CKEout                | LOCATED    | LVCMOS33_OUT  | PR9D  | DQ1           |           |           |
+| 54/1     | nRASout               | LOCATED    | LVCMOS33_OUT  | PR9C  | DQ1           |           |           |
+| 57/1     | nCSout                | LOCATED    | LVCMOS33_OUT  | PR9B  | DQ1           |           |           |
 | 58/1     | BA[0]                 | LOCATED    | LVCMOS33_OUT  | PR9A  | DQ1           |           |           |
-| 59/1     | RA[11]                | LOCATED    | LVCMOS33_OUT  | PR8D  | DQ1           |           |           |
+| 59/1     | RAout[11]             | LOCATED    | LVCMOS33_OUT  | PR8D  | DQ1           |           |           |
 | 60/1     | BA[1]                 | LOCATED    | LVCMOS33_OUT  | PR8C  | DQ1           |           |           |
 | 61/1     |     unused, PULL:DOWN |            |               | PR8A  | DQS1          |           |           |
 | 62/1     | C14M                  | LOCATED    | LVCMOS33_IN   | PR5D  | PCLKC1_0/DQ0  |           |           |
-| 63/1     | RA[9]                 | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0/DQ0  |           |           |
-| 64/1     | RA[10]                | LOCATED    | LVCMOS33_OUT  | PR5B  | DQS0N         |           |           |
-| 65/1     | RA[8]                 | LOCATED    | LVCMOS33_OUT  | PR5A  | DQS0          |           |           |
-| 66/1     | RA[0]                 | LOCATED    | LVCMOS33_OUT  | PR4D  | DQ0           |           |           |
-| 67/1     | RA[7]                 | LOCATED    | LVCMOS33_OUT  | PR4C  | DQ0           |           |           |
-| 68/1     | RA[1]                 | LOCATED    | LVCMOS33_OUT  | PR4B  | DQ0           |           |           |
-| 69/1     | RA[6]                 | LOCATED    | LVCMOS33_OUT  | PR4A  | DQ0           |           |           |
-| 70/1     | RA[2]                 | LOCATED    | LVCMOS33_OUT  | PR3B  | DQ0           |           |           |
-| 71/1     | RA[5]                 | LOCATED    | LVCMOS33_OUT  | PR3A  | DQ0           |           |           |
-| 74/1     | RA[3]                 | LOCATED    | LVCMOS33_OUT  | PR2B  | DQ0           |           |           |
-| 75/1     | RA[4]                 | LOCATED    | LVCMOS33_OUT  | PR2A  | DQ0           |           |           |
+| 63/1     | RAout[9]              | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | RAout[10]             | LOCATED    | LVCMOS33_OUT  | PR5B  | DQS0N         |           |           |
+| 65/1     | RAout[8]              | LOCATED    | LVCMOS33_OUT  | PR5A  | DQS0          |           |           |
+| 66/1     | RAout[0]              | LOCATED    | LVCMOS33_OUT  | PR4D  | DQ0           |           |           |
+| 67/1     | RAout[7]              | LOCATED    | LVCMOS33_OUT  | PR4C  | DQ0           |           |           |
+| 68/1     | RAout[1]              | LOCATED    | LVCMOS33_OUT  | PR4B  | DQ0           |           |           |
+| 69/1     | RAout[6]              | LOCATED    | LVCMOS33_OUT  | PR4A  | DQ0           |           |           |
+| 70/1     | RAout[2]              | LOCATED    | LVCMOS33_OUT  | PR3B  | DQ0           |           |           |
+| 71/1     | RAout[5]              | LOCATED    | LVCMOS33_OUT  | PR3A  | DQ0           |           |           |
+| 74/1     | RAout[3]              | LOCATED    | LVCMOS33_OUT  | PR2B  | DQ0           |           |           |
+| 75/1     | RAout[4]              | LOCATED    | LVCMOS33_OUT  | PR2A  | DQ0           |           |           |
 | 76/0     |     unused, PULL:DOWN |            |               | PT17D | DONE          |           |           |
 | 77/0     |     unused, PULL:DOWN |            |               | PT17C | INITN         |           |           |
 | 78/0     | Ain[4]                | LOCATED    | LVCMOS33_IN   | PT16C |               |           |           |
 | 81/0     |     unused, PULL:DOWN |            |               | PT15D | PROGRAMN      |           |           |
 | 82/0     | nEN80                 | LOCATED    | LVCMOS33_IN   | PT15C | JTAGENB       |           |           |
-| 83/0     | nWE80                 | LOCATED    | LVCMOS33_IN   | PT15B |               |           |           |
+| 83/0     |     unused, PULL:DOWN |            |               | PT15B |               |           |           |
 | 84/0     | Ain[5]                | LOCATED    | LVCMOS33_IN   | PT15A |               |           |           |
 | 85/0     | PHI1                  | LOCATED    | LVCMOS33_IN   | PT12D | SDA/PCLKC0_0  |           |           |
 | 86/0     | Ain[6]                | LOCATED    | LVCMOS33_IN   | PT12C | SCL/PCLKT0_0  |           |           |
@@ -241,7 +240,7 @@ LOCATE  COMP  "Ain[7]"  SITE  "8";
 LOCATE  COMP  "BA[0]"  SITE  "58";
 LOCATE  COMP  "BA[1]"  SITE  "60";
 LOCATE  COMP  "C14M"  SITE  "62";
-LOCATE  COMP  "CKE"  SITE  "53";
+LOCATE  COMP  "CKEout"  SITE  "53";
 LOCATE  COMP  "DQMH"  SITE  "49";
 LOCATE  COMP  "DQML"  SITE  "48";
 LOCATE  COMP  "Din[0]"  SITE  "96";
@@ -262,18 +261,18 @@ LOCATE  COMP  "Dout[6]"  SITE  "31";
 LOCATE  COMP  "Dout[7]"  SITE  "32";
 LOCATE  COMP  "LED"  SITE  "35";
 LOCATE  COMP  "PHI1"  SITE  "85";
-LOCATE  COMP  "RA[0]"  SITE  "66";
-LOCATE  COMP  "RA[10]"  SITE  "64";
-LOCATE  COMP  "RA[11]"  SITE  "59";
-LOCATE  COMP  "RA[1]"  SITE  "68";
-LOCATE  COMP  "RA[2]"  SITE  "70";
-LOCATE  COMP  "RA[3]"  SITE  "74";
-LOCATE  COMP  "RA[4]"  SITE  "75";
-LOCATE  COMP  "RA[5]"  SITE  "71";
-LOCATE  COMP  "RA[6]"  SITE  "69";
-LOCATE  COMP  "RA[7]"  SITE  "67";
-LOCATE  COMP  "RA[8]"  SITE  "65";
-LOCATE  COMP  "RA[9]"  SITE  "63";
+LOCATE  COMP  "RAout[0]"  SITE  "66";
+LOCATE  COMP  "RAout[10]"  SITE  "64";
+LOCATE  COMP  "RAout[11]"  SITE  "59";
+LOCATE  COMP  "RAout[1]"  SITE  "68";
+LOCATE  COMP  "RAout[2]"  SITE  "70";
+LOCATE  COMP  "RAout[3]"  SITE  "74";
+LOCATE  COMP  "RAout[4]"  SITE  "75";
+LOCATE  COMP  "RAout[5]"  SITE  "71";
+LOCATE  COMP  "RAout[6]"  SITE  "69";
+LOCATE  COMP  "RAout[7]"  SITE  "67";
+LOCATE  COMP  "RAout[8]"  SITE  "65";
+LOCATE  COMP  "RAout[9]"  SITE  "63";
 LOCATE  COMP  "RD[0]"  SITE  "36";
 LOCATE  COMP  "RD[1]"  SITE  "37";
 LOCATE  COMP  "RD[2]"  SITE  "38";
@@ -291,15 +290,14 @@ LOCATE  COMP  "Vout[5]"  SITE  "16";
 LOCATE  COMP  "Vout[6]"  SITE  "14";
 LOCATE  COMP  "Vout[7]"  SITE  "12";
 LOCATE  COMP  "nC07X"  SITE  "34";
-LOCATE  COMP  "nCAS"  SITE  "52";
-LOCATE  COMP  "nCS"  SITE  "57";
+LOCATE  COMP  "nCASout"  SITE  "52";
+LOCATE  COMP  "nCSout"  SITE  "57";
 LOCATE  COMP  "nDOE"  SITE  "20";
 LOCATE  COMP  "nEN80"  SITE  "82";
-LOCATE  COMP  "nRAS"  SITE  "54";
-LOCATE  COMP  "nRWE"  SITE  "51";
+LOCATE  COMP  "nRASout"  SITE  "54";
+LOCATE  COMP  "nRWEout"  SITE  "51";
 LOCATE  COMP  "nVOE"  SITE  "10";
 LOCATE  COMP  "nWE"  SITE  "29";
-LOCATE  COMP  "nWE80"  SITE  "83";
 
 
 
@@ -311,5 +309,5 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Sep 21 05:35:04 2023
+Thu Dec 28 23:10:13 2023
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.prf b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.prf
index 77b562e..d59bddc 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.prf
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.prf
@@ -1,12 +1,10 @@
 SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:34:47 2023
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:09:58 2023
 
 SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
 LOCATE COMP "RD[0]" SITE "36" ;
 LOCATE COMP "LED" SITE "35" ;
 LOCATE COMP "C14M" SITE "62" ;
-LOCATE COMP "DQMH" SITE "49" ;
-LOCATE COMP "DQML" SITE "48" ;
 LOCATE COMP "RD[7]" SITE "43" ;
 LOCATE COMP "RD[6]" SITE "42" ;
 LOCATE COMP "RD[5]" SITE "41" ;
@@ -14,25 +12,27 @@ LOCATE COMP "RD[4]" SITE "40" ;
 LOCATE COMP "RD[3]" SITE "39" ;
 LOCATE COMP "RD[2]" SITE "38" ;
 LOCATE COMP "RD[1]" SITE "37" ;
-LOCATE COMP "RA[11]" SITE "59" ;
-LOCATE COMP "RA[10]" SITE "64" ;
-LOCATE COMP "RA[9]" SITE "63" ;
-LOCATE COMP "RA[8]" SITE "65" ;
-LOCATE COMP "RA[7]" SITE "67" ;
-LOCATE COMP "RA[6]" SITE "69" ;
-LOCATE COMP "RA[5]" SITE "71" ;
-LOCATE COMP "RA[4]" SITE "75" ;
-LOCATE COMP "RA[3]" SITE "74" ;
-LOCATE COMP "RA[2]" SITE "70" ;
-LOCATE COMP "RA[1]" SITE "68" ;
-LOCATE COMP "RA[0]" SITE "66" ;
+LOCATE COMP "DQMH" SITE "49" ;
+LOCATE COMP "DQML" SITE "48" ;
+LOCATE COMP "RAout[11]" SITE "59" ;
+LOCATE COMP "RAout[10]" SITE "64" ;
+LOCATE COMP "RAout[9]" SITE "63" ;
+LOCATE COMP "RAout[8]" SITE "65" ;
+LOCATE COMP "RAout[7]" SITE "67" ;
+LOCATE COMP "RAout[6]" SITE "69" ;
+LOCATE COMP "RAout[5]" SITE "71" ;
+LOCATE COMP "RAout[4]" SITE "75" ;
+LOCATE COMP "RAout[3]" SITE "74" ;
+LOCATE COMP "RAout[2]" SITE "70" ;
+LOCATE COMP "RAout[1]" SITE "68" ;
+LOCATE COMP "RAout[0]" SITE "66" ;
 LOCATE COMP "BA[1]" SITE "60" ;
 LOCATE COMP "BA[0]" SITE "58" ;
-LOCATE COMP "nRWE" SITE "51" ;
-LOCATE COMP "nCAS" SITE "52" ;
-LOCATE COMP "nRAS" SITE "54" ;
-LOCATE COMP "nCS" SITE "57" ;
-LOCATE COMP "CKE" SITE "53" ;
+LOCATE COMP "nRWEout" SITE "51" ;
+LOCATE COMP "nCASout" SITE "52" ;
+LOCATE COMP "nRASout" SITE "54" ;
+LOCATE COMP "nCSout" SITE "57" ;
+LOCATE COMP "CKEout" SITE "53" ;
 LOCATE COMP "nVOE" SITE "10" ;
 LOCATE COMP "Vout[7]" SITE "12" ;
 LOCATE COMP "Vout[6]" SITE "14" ;
@@ -69,7 +69,6 @@ LOCATE COMP "Ain[1]" SITE "2" ;
 LOCATE COMP "Ain[0]" SITE "3" ;
 LOCATE COMP "nC07X" SITE "34" ;
 LOCATE COMP "nEN80" SITE "82" ;
-LOCATE COMP "nWE80" SITE "83" ;
 LOCATE COMP "nWE" SITE "29" ;
 LOCATE COMP "PHI1" SITE "85" ;
 FREQUENCY PORT "C14M" 14.300000 MHz ;
@@ -79,7 +78,7 @@ BLOCK ASYNCPATHS ;
 OUTPUT PORT "LED" LOAD 100.000000 pF ;
 OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
 OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
-OUTPUT PORT "CKE" LOAD 5.000000 pF ;
+OUTPUT PORT "CKEout" LOAD 5.000000 pF ;
 OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
 OUTPUT PORT "DQML" LOAD 5.000000 pF ;
 OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
@@ -90,18 +89,18 @@ OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
 OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
 OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
 OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
-OUTPUT PORT "RA[0]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[1]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[2]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[3]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[4]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[5]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[6]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[7]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[8]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[9]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[10]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[11]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ;
 OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
@@ -110,11 +109,11 @@ OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
-OUTPUT PORT "nCAS" LOAD 5.000000 pF ;
-OUTPUT PORT "nCS" LOAD 5.000000 pF ;
+OUTPUT PORT "nCASout" LOAD 5.000000 pF ;
+OUTPUT PORT "nCSout" LOAD 5.000000 pF ;
 OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
-OUTPUT PORT "nRAS" LOAD 5.000000 pF ;
-OUTPUT PORT "nRWE" LOAD 5.000000 pF ;
+OUTPUT PORT "nRASout" LOAD 5.000000 pF ;
+OUTPUT PORT "nRWEout" LOAD 5.000000 pF ;
 OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
 OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
 OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.srr b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.srr
index 626b27a..e38710a 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.srr
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.srr
@@ -3,7 +3,7 @@
 #OS: Windows 8 6.2
 #Hostname: ZANEMACWIN11
 
-# Thu Sep 21 05:34:34 2023
+# Thu Dec 28 23:09:45 2023
 
 #Implementation: impl1
 
@@ -48,45 +48,50 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
+@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
+@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
 @I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
 Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
 Selecting top level module RAM2E
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
 Running optimization stage 1 on VHI .......
-Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
 Running optimization stage 1 on VLO .......
-Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
 Running optimization stage 1 on EFB .......
 Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
 @N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
 Running optimization stage 1 on REFB .......
 Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
+@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
+Running optimization stage 1 on RAM2E_UFM .......
+Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
 Running optimization stage 1 on RAM2E .......
 Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
 Running optimization stage 2 on RAM2E .......
+@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
 Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Running optimization stage 2 on RAM2E_UFM .......
+@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
+Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
 Running optimization stage 2 on REFB .......
-Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
 Running optimization stage 2 on EFB .......
-Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
 Running optimization stage 2 on VLO .......
-Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
 Running optimization stage 2 on VHI .......
-Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
 
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB)
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:34 2023
+# Thu Dec 28 23:09:45 2023
 
 ###########################################################]
 ###########################################################[
@@ -113,7 +118,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:34 2023
+# Thu Dec 28 23:09:46 2023
 
 ###########################################################]
 
@@ -123,12 +128,12 @@ For a summary of runtime and memory usage for all design units, please see file:
 
 @END
 
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:34 2023
+# Thu Dec 28 23:09:46 2023
 
 ###########################################################]
 ###########################################################[
@@ -156,10 +161,10 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:36 2023
+# Thu Dec 28 23:09:47 2023
 
 ###########################################################]
-# Thu Sep 21 05:34:36 2023
+# Thu Dec 28 23:09:47 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -178,10 +183,10 @@ Implementation : impl1
 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 141MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
 
 Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
 @L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt 
@@ -190,10 +195,10 @@ See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
 
 
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
 
 
 Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
@@ -201,46 +206,45 @@ Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00
 
 Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
 
-@N: FX493 |Applying initial value "0" on instance PHI1reg.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance DOEEN.
-@N: FX493 |Applying initial value "0" on instance RWSel.
-@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
-@N: FX493 |Applying initial value "1" on instance DQMH.
-@N: FX493 |Applying initial value "0" on instance Ready.
 @N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 @N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
+@N: FX493 |Applying initial value "0" on instance PHI1r.
+@N: FX493 |Applying initial value "0" on instance RWSel.
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
 @N: FX493 |Applying initial value "0" on instance CmdLEDGet.
 @N: FX493 |Applying initial value "0" on instance CmdLEDSet.
 @N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
 @N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
-@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "0000" on instance S[3:0].
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "1" on instance DQMH.
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
 @N: FX493 |Applying initial value "1" on instance DQML.
-@N: FX493 |Applying initial value "0" on instance CKE.
-@N: FX493 |Applying initial value "1" on instance nCS.
-@N: FX493 |Applying initial value "1" on instance nRAS.
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "0000" on instance S[3:0].
+@N: FX493 |Applying initial value "1" on instance CKE.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+@N: FX493 |Applying initial value "1" on instance nRWEout.
 @N: FX493 |Applying initial value "1" on instance nCAS.
+@N: FX493 |Applying initial value "1" on instance nCASout.
+@N: FX493 |Applying initial value "1" on instance nRAS.
+@N: FX493 |Applying initial value "1" on instance nRASout.
 
-Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 @N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E 
 
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
 
 
 
@@ -250,7 +254,7 @@ Clock Summary
           Start      Requested     Requested     Clock        Clock                Clock
 Level     Clock      Frequency     Period        Type         Group                Load 
 ----------------------------------------------------------------------------------------
-0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     111  
+0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     122  
                                                                                         
 0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
 ========================================================================================
@@ -263,7 +267,7 @@ Clock Load Summary
            Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin     
 Clock      Load      Pin            Seq Example     Seq Example       Comb Example      
 ----------------------------------------------------------------------------------------
-C14M       111       C14M(port)     wb_rst.C        -                 un1_C14M.I[0](inv)
+C14M       122       C14M(port)     DOEEN.C         -                 un1_C14M.I[0](inv)
                                                                                         
 System     0         -              -               -                 -                 
 ========================================================================================
@@ -280,14 +284,14 @@ For details review file gcc_ICG_report.rpt
 
 #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
 
-1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
+1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
 0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
 =========================== Non-Gated/Non-Generated Clocks ============================
 Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
 ---------------------------------------------------------------------------------------
-@KP:ckid0_0       C14M                port                   111        nCAS           
+@KP:ckid0_0       C14M                port                   122        nRAS           
 =======================================================================================
 
 
@@ -308,11 +312,11 @@ Pre-mapping successful!
 
 At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
 
-Process took 0h:00m:02s realtime, 0h:00m:01s cputime
-# Thu Sep 21 05:34:38 2023
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Thu Dec 28 23:09:49 2023
 
 ###########################################################]
-# Thu Sep 21 05:34:38 2023
+# Thu Dec 28 23:09:49 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -331,97 +335,97 @@ Implementation : impl1
 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
 
 
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
 
 
 Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
 
 
 
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 179MB peak: 179MB)
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
 
-@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
-@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
 
-Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
 
-@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
+@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 
 Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
 Available hyper_sources - for debug and ip models
 	None Found
 
 
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
 
 
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
 
 
-Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
 
 
-Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
 
 Pass		 CPU time		Worst Slack		Luts / Registers
 ------------------------------------------------------------
-   1		0h:00m:02s		    29.35ns		 222 /       111
+   1		0h:00m:02s		    33.71ns		 284 /       122
 
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
 
 @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
 
-Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
 
 
-Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
 
 Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
 
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB)
 
 Writing EDIF Netlist and constraint files
 @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
 
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
 
 
-Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
 
 
-Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
+Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB)
 
 @W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
 @N: MT615 |Found clock C14M with period 69.84ns 
 
 
 ##### START OF TIMING REPORT #####[
-# Timing report written on Thu Sep 21 05:34:44 2023
+# Timing report written on Thu Dec 28 23:09:54 2023
 #
 
 
@@ -441,12 +445,12 @@ Performance Summary
 *******************
 
 
-Worst slack in design: 31.782
+Worst slack in design: 33.707
 
                    Requested     Estimated     Requested     Estimated                Clock        Clock           
 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
 -------------------------------------------------------------------------------------------------------------------
-C14M               14.3 MHz      131.4 MHz     69.841        7.610         31.782     declared     default_clkgroup
+C14M               14.3 MHz      128.0 MHz     69.841        7.813         33.707     declared     default_clkgroup
 System             100.0 MHz     NA            10.000        NA            67.088     system       system_clkgroup 
 ===================================================================================================================
 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
@@ -464,7 +468,7 @@ Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  sl
 ----------------------------------------------------------------------------------------------------------
 System    C14M    |  69.841      67.088  |  No paths    -      |  No paths    -       |  No paths    -    
 C14M      System  |  69.841      68.797  |  No paths    -      |  No paths    -       |  No paths    -    
-C14M      C14M    |  69.841      62.231  |  No paths    -      |  34.920      31.782  |  No paths    -    
+C14M      C14M    |  69.841      62.028  |  No paths    -      |  34.920      33.707  |  No paths    -    
 ==========================================================================================================
  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
@@ -487,41 +491,41 @@ Detailed Report for Clock: C14M
 Starting Points with Worst Slack
 ********************************
 
-             Starting                                     Arrival           
-Instance     Reference     Type        Pin     Net        Time        Slack 
-             Clock                                                          
-----------------------------------------------------------------------------
-S[2]         C14M          FD1S3AX     Q       S[2]       1.350       31.782
-S[3]         C14M          FD1S3AX     Q       S[3]       1.350       31.782
-S[0]         C14M          FD1S3AX     Q       S[0]       1.312       31.820
-S[1]         C14M          FD1S3AX     Q       S[1]       1.280       31.852
-FS[9]        C14M          FD1S3AX     Q       FS[9]      1.284       62.425
-FS[11]       C14M          FD1S3AX     Q       FS[11]     1.276       62.433
-FS[8]        C14M          FD1S3AX     Q       FS[8]      1.260       62.449
-FS[12]       C14M          FD1S3AX     Q       FS[12]     1.288       62.525
-FS[10]       C14M          FD1S3AX     Q       FS[10]     1.280       62.533
-RWSel        C14M          FD1P3AX     Q       RWSel      1.276       63.482
-============================================================================
+             Starting                                    Arrival           
+Instance     Reference     Type        Pin     Net       Time        Slack 
+             Clock                                                         
+---------------------------------------------------------------------------
+RA[0]        C14M          FD1P3AX     Q       RA[0]     1.108       33.707
+RA[3]        C14M          FD1P3AX     Q       RA[3]     1.108       33.707
+RA[1]        C14M          FD1P3AX     Q       RA[1]     1.044       33.771
+RA[2]        C14M          FD1P3AX     Q       RA[2]     1.044       33.771
+RA[4]        C14M          FD1P3AX     Q       RA[4]     1.044       33.771
+RA[5]        C14M          FD1P3AX     Q       RA[5]     1.044       33.771
+RA[6]        C14M          FD1P3AX     Q       RA[6]     1.044       33.771
+RA[7]        C14M          FD1P3AX     Q       RA[7]     1.044       33.771
+RA[8]        C14M          FD1P3AX     Q       RA[8]     1.044       33.771
+RA[9]        C14M          FD1P3AX     Q       RA[9]     1.044       33.771
+===========================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-                Starting                                       Required           
-Instance        Reference     Type         Pin     Net         Time         Slack 
-                Clock                                                             
-----------------------------------------------------------------------------------
-Dout_0io[0]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[1]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[2]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[3]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[4]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[5]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[6]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[7]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Vout_0io[0]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
-Vout_0io[1]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
-==================================================================================
+                 Starting                                     Required           
+Instance         Reference     Type         Pin     Net       Time         Slack 
+                 Clock                                                           
+---------------------------------------------------------------------------------
+RAout_0io[0]     C14M          OFS1P3DX     D       RA[0]     34.815       33.707
+RAout_0io[3]     C14M          OFS1P3DX     D       RA[3]     34.815       33.707
+RAout_0io[1]     C14M          OFS1P3DX     D       RA[1]     34.815       33.771
+RAout_0io[2]     C14M          OFS1P3DX     D       RA[2]     34.815       33.771
+RAout_0io[4]     C14M          OFS1P3DX     D       RA[4]     34.815       33.771
+RAout_0io[5]     C14M          OFS1P3DX     D       RA[5]     34.815       33.771
+RAout_0io[6]     C14M          OFS1P3DX     D       RA[6]     34.815       33.771
+RAout_0io[7]     C14M          OFS1P3DX     D       RA[7]     34.815       33.771
+RAout_0io[8]     C14M          OFS1P3DX     D       RA[8]     34.815       33.771
+RAout_0io[9]     C14M          OFS1P3DX     D       RA[9]     34.815       33.771
+=================================================================================
 
 
 
@@ -531,30 +535,27 @@ Worst Path Information
 
 Path information for path number 1: 
       Requested Period:                      34.920
-    - Setup time:                            0.472
+    - Setup time:                            0.106
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         34.449
+    = Required time:                         34.815
 
-    - Propagation time:                      2.667
+    - Propagation time:                      1.108
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     31.782
+    = Slack (critical) :                     33.707
 
-    Number of logic level(s):                1
-    Starting point:                          S[2] / Q
-    Ending point:                            Dout_0io[0] / SP
+    Number of logic level(s):                0
+    Starting point:                          RA[0] / Q
+    Ending point:                            RAout_0io[0] / D
     The start point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
     The end   point is clocked by            C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
 
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-S[2]                FD1S3AX      Q        Out     1.350     1.350 r     -         
-S[2]                Net          -        -       -         -           48        
-S_RNII9DO1_2[1]     ORCALUT4     B        In      0.000     1.350 r     -         
-S_RNII9DO1_2[1]     ORCALUT4     Z        Out     1.317     2.667 r     -         
-N_576_i             Net          -        -       -         -           18        
-Dout_0io[0]         OFS1P3DX     SP       In      0.000     2.667 r     -         
-==================================================================================
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+RA[0]              FD1P3AX      Q        Out     1.108     1.108 r     -         
+RA[0]              Net          -        -       -         -           3         
+RAout_0io[0]       OFS1P3DX     D        In      0.000     1.108 r     -         
+=================================================================================
 
 
 
@@ -568,40 +569,40 @@ Detailed Report for Clock: System
 Starting Points with Worst Slack
 ********************************
 
-                     Starting                                          Arrival           
-Instance             Reference     Type     Pin         Net            Time        Slack 
-                     Clock                                                               
------------------------------------------------------------------------------------------
-ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
-ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
-=========================================================================================
+                               Starting                                          Arrival           
+Instance                       Reference     Type     Pin         Net            Time        Slack 
+                               Clock                                                               
+---------------------------------------------------------------------------------------------------
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
+===================================================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-               Starting                                                          Required           
-Instance       Reference     Type        Pin     Net                             Time         Slack 
-               Clock                                                                                
-----------------------------------------------------------------------------------------------------
-RWMask[0]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[1]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[2]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[3]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[4]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[5]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[6]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[7]      System        FD1P3AX     SP      N_88                            69.369       67.088
-LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0[0]     69.369       67.736
-wb_cyc_stb     System        FD1P3AX     SP      N_104                           69.369       67.736
-====================================================================================================
+                         Starting                                                                  Required           
+Instance                 Reference     Type        Pin     Net                                     Time         Slack 
+                         Clock                                                                                        
+----------------------------------------------------------------------------------------------------------------------
+ram2e_ufm.RWMask[0]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[1]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[2]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[3]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[4]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[5]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[6]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[7]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0_0[0]           69.369       67.736
+ram2e_ufm.wb_cyc_stb     System        FD1P3AX     SP      un1_CmdSetRWBankFFChip13_1_i_0_0[0]     69.369       67.736
+======================================================================================================================
 
 
 
@@ -621,24 +622,24 @@ Path information for path number 1:
     = Slack (non-critical) :                 67.088
 
     Number of logic level(s):                2
-    Starting point:                          ufmefb.EFBInst_0 / WBACKO
-    Ending point:                            RWMask[0] / SP
+    Starting point:                          ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
+    Ending point:                            ram2e_ufm.RWMask[0] / SP
     The start point is clocked by            System [rising]
     The end   point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
 
-Instance / Net                                     Pin        Pin               Arrival     No. of    
-Name                                  Type         Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
-ufmefb.EFBInst_0                      EFB          WBACKO     Out     0.000     0.000 r     -         
-wb_ack                                Net          -          -       -         -           5         
-un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     A          In      0.000     0.000 r     -         
-un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     Z          Out     1.017     1.017 r     -         
-un1_RWMask_0_sqmuxa_1_i_a2_0_1[0]     Net          -          -       -         -           1         
-un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
-un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
-N_88                                  Net          -          -       -         -           8         
-RWMask[0]                             FD1P3AX      SP         In      0.000     2.282 r     -         
-======================================================================================================
+Instance / Net                                                 Pin        Pin               Arrival     No. of    
+Name                                              Type         Name       Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------------------------------------
+ram2e_ufm.ufmefb.EFBInst_0                        EFB          WBACKO     Out     0.000     0.000 r     -         
+wb_ack                                            Net          -          -       -         -           5         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     B          In      0.000     0.000 r     -         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     Z          Out     1.017     1.017 r     -         
+un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]               Net          -          -       -         -           1         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
+un1_RWMask_0_sqmuxa_1_i_0_0[0]                    Net          -          -       -         -           8         
+ram2e_ufm.RWMask[0]                               FD1P3AX      SP         In      0.000     2.282 r     -         
+==================================================================================================================
 
 
 
@@ -646,45 +647,47 @@ RWMask[0]                             FD1P3AX      SP         In      0.000
 
 Timing exceptions that could not be applied
 
-Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
 
 
-Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
 
 ---------------------------------------
 Resource Usage Report
 Part: lcmxo2_1200hc-4
 
-Register bits: 111 of 1280 (9%)
+Register bits: 122 of 1280 (10%)
 PIC Latch:       0
-I/O cells:       70
+I/O cells:       69
 
 
 Details:
 BB:             8
 CCU2D:          9
 EFB:            1
-FD1P3AX:        48
+FD1P3AX:        61
 FD1P3IX:        1
-FD1S3AX:        22
-FD1S3IX:        4
+FD1S3AX:        21
+FD1S3AY:        4
+FD1S3IX:        6
 GSR:            1
-IB:             22
+IB:             21
 IFS1P3DX:       1
 INV:            1
 OB:             40
-OFS1P3BX:       6
-OFS1P3DX:       27
+OFS1P3BX:       5
+OFS1P3DX:       21
 OFS1P3IX:       2
-ORCALUT4:       221
+ORCALUT4:       277
+PFUMX:          3
 PUR:            1
-VHI:            2
-VLO:            2
+VHI:            3
+VLO:            3
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 211MB)
+At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 79MB peak: 217MB)
 
-Process took 0h:00m:06s realtime, 0h:00m:04s cputime
-# Thu Sep 21 05:34:44 2023
+Process took 0h:00m:04s realtime, 0h:00m:04s cputime
+# Thu Dec 28 23:09:54 2023
 
 ###########################################################]
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.tw1 b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.tw1
index 1bc2dae..57ce527 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.tw1
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.tw1
@@ -13,7 +13,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:34:48 2023
+Thu Dec 28 23:09:59 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -38,48 +38,48 @@ BLOCK RESETPATHS
 
 ================================================================================
 Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 58.471ns
+Passed: The following path meets requirements by 58.937ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              11.306ns  (30.3% logic, 69.7% route), 7 logic levels.
+   Delay:              10.827ns  (31.6% logic, 68.4% route), 7 logic levels.
 
  Constraint Details:
 
-     11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
-      0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns
 
  Physical Path Details:
 
-      Data path SLICE_3 to nRWE_MGIOL:
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452    SLICE_3.CLK to     SLICE_3.Q0 SLICE_3 (from C14M_c)
-ROUTE        19   e 1.234     SLICE_3.Q0 to    SLICE_64.A1 FS[11]
-CTOF_DEL    ---     0.495    SLICE_64.A1 to    SLICE_64.F1 SLICE_64
-ROUTE         4   e 1.234    SLICE_64.F1 to    SLICE_97.D0 N_577
-CTOF_DEL    ---     0.495    SLICE_97.D0 to    SLICE_97.F0 SLICE_97
-ROUTE         3   e 1.234    SLICE_97.F0 to    SLICE_75.D1 N_489
-CTOF_DEL    ---     0.495    SLICE_75.D1 to    SLICE_75.F1 SLICE_75
-ROUTE         3   e 0.480    SLICE_75.F1 to    SLICE_75.A0 N_628
-CTOF_DEL    ---     0.495    SLICE_75.A0 to    SLICE_75.F0 SLICE_75
-ROUTE         2   e 1.234    SLICE_75.F0 to    SLICE_71.C1 N_640
-CTOF_DEL    ---     0.495    SLICE_71.C1 to    SLICE_71.F1 SLICE_71
-ROUTE         1   e 1.234    SLICE_71.F1 to   SLICE_115.A0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495   SLICE_115.A0 to   SLICE_115.F0 SLICE_115
-ROUTE         1   e 1.234   SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
+REG_DEL     ---     0.452   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from C14M_c)
+ROUTE        50   e 1.234    SLICE_34.Q0 to    SLICE_35.A0 S[2]
+CTOF_DEL    ---     0.495    SLICE_35.A0 to    SLICE_35.F0 SLICE_35
+ROUTE         7   e 1.234    SLICE_35.F0 to *m/SLICE_80.D1 N_551
+CTOF_DEL    ---     0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
+ROUTE         8   e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
+ROUTE         5   e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
+ROUTE         1   e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
+CTOF_DEL    ---     0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
+ROUTE         1   e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
+ROUTE         1   e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   11.306   (30.3% logic, 69.7% route), 7 logic levels.
+                   10.827   (31.6% logic, 68.4% route), 7 logic levels.
 
-Report:   87.268MHz is the maximum frequency for this preference.
+Report:   90.967MHz is the maximum frequency for this preference.
 
 Report Summary
 --------------
@@ -87,7 +87,7 @@ Report Summary
 Preference                              |   Constraint|       Actual|Levels
 ----------------------------------------------------------------------------
                                         |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   87.268 MHz|   7  
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   90.967 MHz|   7  
                                         |             |             |
 ----------------------------------------------------------------------------
 
@@ -100,7 +100,7 @@ Clock Domains Analysis
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -110,11 +110,11 @@ Timing summary (Setup):
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:34:49 2023
+Thu Dec 28 23:09:59 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -139,7 +139,7 @@ BLOCK RESETPATHS
 
 ================================================================================
 Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
@@ -164,7 +164,7 @@ Passed: The following path meets requirements by 0.447ns
 
    Name    Fanout   Delay (ns)          Site               Resource
 REG_DEL     ---     0.133    SLICE_0.CLK to     SLICE_0.Q1 SLICE_0 (from C14M_c)
-ROUTE         5   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
+ROUTE         6   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
 CTOF_DEL    ---     0.101     SLICE_0.A1 to     SLICE_0.F1 SLICE_0
 ROUTE         1   e 0.001     SLICE_0.F1 to    SLICE_0.DI1 FS_s[0] (to C14M_c)
                   --------
@@ -189,7 +189,7 @@ Clock Domains Analysis
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -199,7 +199,7 @@ Timing summary (Hold):
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.twr b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.twr
index 3ace311..c62d1d2 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.twr
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.twr
@@ -13,7 +13,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:35:07 2023
+Thu Dec 28 23:10:17 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -38,516 +38,548 @@ BLOCK RESETPATHS
 
 ================================================================================
 Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 57.121ns
+Passed: The following path meets requirements by 58.069ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[8]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              12.829ns  (26.7% logic, 73.3% route), 7 logic levels.
+   Delay:              11.695ns  (29.3% logic, 70.7% route), 7 logic levels.
 
  Constraint Details:
 
-     12.829ns physical path delay SLICE_5 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.121ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9A.CLK to       R5C9A.Q1 SLICE_5 (from C14M_c)
-ROUTE        15     2.743       R5C9A.Q1 to       R4C7B.B1 FS[8]
-CTOF_DEL    ---     0.495       R4C7B.B1 to       R4C7B.F1 SLICE_64
-ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
-CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
-ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
-CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
-ROUTE         3     0.453      R4C11C.F1 to      R4C11C.C0 N_628
-CTOF_DEL    ---     0.495      R4C11C.C0 to      R4C11C.F0 SLICE_75
-ROUTE         2     0.652      R4C11C.F0 to      R5C11B.D1 N_640
-CTOF_DEL    ---     0.495      R5C11B.D1 to      R5C11B.F1 SLICE_71
-ROUTE         1     1.023      R5C11B.F1 to      R5C13A.B0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495      R5C13A.B0 to      R5C13A.F0 SLICE_115
-ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   12.829   (26.7% logic, 73.3% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R5C9A.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
-                  --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.346ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        wb_dati[6]  (to C14M_c +)
-
-   Delay:              12.418ns  (27.6% logic, 72.4% route), 7 logic levels.
-
- Constraint Details:
-
-     12.418ns physical path delay SLICE_33 to SLICE_43 meets
+     11.695ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
       0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.346ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.069ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to SLICE_43:
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     3.112      R3C11C.Q0 to      R5C12C.B0 S[0]
-CTOF_DEL    ---     0.495      R5C12C.B0 to      R5C12C.F0 SLICE_47
-ROUTE         7     2.060      R5C12C.F0 to       R3C7C.C1 S_RNII9DO1[1]
-CTOF_DEL    ---     0.495       R3C7C.C1 to       R3C7C.F1 SLICE_86
-ROUTE         5     1.174       R3C7C.F1 to       R4C5A.D1 N_484
-CTOF_DEL    ---     0.495       R4C5A.D1 to       R4C5A.F1 SLICE_74
-ROUTE         3     0.984       R4C5A.F1 to       R4C5A.A0 N_642
-CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 SLICE_74
-ROUTE         2     0.665       R4C5A.F0 to       R4C5C.A0 N_346
-CTOF_DEL    ---     0.495       R4C5C.A0 to       R4C5C.F0 SLICE_84
-ROUTE         1     1.001       R4C5C.F0 to       R3C5D.B0 wb_dati_7_0_1[6]
-CTOF_DEL    ---     0.495       R3C5D.B0 to       R3C5D.F0 SLICE_43
-ROUTE         1     0.000       R3C5D.F0 to      R3C5D.DI0 wb_dati_7[6] (to C14M_c)
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
+ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
+CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.755       R3C6C.F1 to       R2C7D.A0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R2C7D.A0 to       R2C7D.F0 ram2e_ufm/SLICE_99
+ROUTE         1     1.023       R2C7D.F0 to       R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0]
+CTOF_DEL    ---     0.495       R3C7A.B0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   12.418   (27.6% logic, 72.4% route), 7 logic levels.
+                   11.695   (29.3% logic, 70.7% route), 7 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_33:
+      Source Clock Path C14M to SLICE_34:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_43:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R3C5D.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 57.382ns
+Passed: The following path meets requirements by 58.138ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[8]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              12.568ns  (23.3% logic, 76.7% route), 6 logic levels.
+   Delay:              11.626ns  (29.4% logic, 70.6% route), 7 logic levels.
 
  Constraint Details:
 
-     12.568ns physical path delay SLICE_5 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.382ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9A.CLK to       R5C9A.Q1 SLICE_5 (from C14M_c)
-ROUTE        15     2.743       R5C9A.Q1 to       R4C7B.B1 FS[8]
-CTOF_DEL    ---     0.495       R4C7B.B1 to       R4C7B.F1 SLICE_64
-ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
-CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
-ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
-CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
-ROUTE         3     1.040      R4C11C.F1 to      R5C11D.B0 N_628
-CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_76
-ROUTE         3     1.322      R5C11D.F0 to      R5C13A.A0 nCAS_0_sqmuxa
-CTOF_DEL    ---     0.495      R5C13A.A0 to      R5C13A.F0 SLICE_115
-ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   12.568   (23.3% logic, 76.7% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R5C9A.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
-                  --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.636ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[9]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
-
-   Delay:              12.314ns  (27.8% logic, 72.2% route), 7 logic levels.
-
- Constraint Details:
-
-     12.314ns physical path delay SLICE_4 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.636ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_4 (from C14M_c)
-ROUTE        21     2.228       R5C9B.Q0 to       R4C7B.A1 FS[9]
-CTOF_DEL    ---     0.495       R4C7B.A1 to       R4C7B.F1 SLICE_64
-ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
-CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
-ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
-CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
-ROUTE         3     0.453      R4C11C.F1 to      R4C11C.C0 N_628
-CTOF_DEL    ---     0.495      R4C11C.C0 to      R4C11C.F0 SLICE_75
-ROUTE         2     0.652      R4C11C.F0 to      R5C11B.D1 N_640
-CTOF_DEL    ---     0.495      R5C11B.D1 to      R5C11B.F1 SLICE_71
-ROUTE         1     1.023      R5C11B.F1 to      R5C13A.B0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495      R5C13A.B0 to      R5C13A.F0 SLICE_115
-ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   12.314   (27.8% logic, 72.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R5C9B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
-                  --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.645ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        wb_adr[0]  (to C14M_c +)
-
-   Delay:              12.119ns  (24.2% logic, 75.8% route), 6 logic levels.
-
- Constraint Details:
-
-     12.119ns physical path delay SLICE_33 to SLICE_35 meets
+     11.626ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
       0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.645ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.138ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to SLICE_35:
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     3.112      R3C11C.Q0 to      R5C12C.B0 S[0]
-CTOF_DEL    ---     0.495      R5C12C.B0 to      R5C12C.F0 SLICE_47
-ROUTE         7     2.060      R5C12C.F0 to       R4C7C.C1 S_RNII9DO1[1]
-CTOF_DEL    ---     0.495       R4C7C.C1 to       R4C7C.F1 SLICE_56
-ROUTE         6     2.374       R4C7C.F1 to       R5C7D.A0 N_452
-CTOF_DEL    ---     0.495       R5C7D.A0 to       R5C7D.F0 SLICE_92
-ROUTE         1     0.645       R5C7D.F0 to       R5C5A.D0 wb_adr_7_0_0[0]
-CTOF_DEL    ---     0.495       R5C5A.D0 to       R5C5A.F0 SLICE_85
-ROUTE         1     1.001       R5C5A.F0 to       R4C5B.B0 wb_adr_7_0_4[0]
-CTOF_DEL    ---     0.495       R4C5B.B0 to       R4C5B.F0 SLICE_35
-ROUTE         1     0.000       R4C5B.F0 to      R4C5B.DI0 wb_adr_7[0] (to C14M_c)
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
+ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
+CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.962       R3C6C.F1 to       R3C7C.C0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R3C7C.C0 to       R3C7C.F0 ram2e_ufm/SLICE_126
+ROUTE         1     0.747       R3C7C.F0 to       R3C7A.C0 ram2e_ufm/N_753
+CTOF_DEL    ---     0.495       R3C7A.C0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   12.119   (24.2% logic, 75.8% route), 6 logic levels.
+                   11.626   (29.4% logic, 70.6% route), 7 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_33:
+      Source Clock Path C14M to SLICE_34:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_35:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R4C5B.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 57.783ns
+Passed: The following path meets requirements by 58.247ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[7]  (to C14M_c +)
 
-   Delay:              12.167ns  (28.1% logic, 71.9% route), 7 logic levels.
+   Delay:              11.517ns  (25.4% logic, 74.6% route), 6 logic levels.
 
  Constraint Details:
 
-     12.167ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     11.517ns physical path delay SLICE_34 to ram2e_ufm/SLICE_55 meets
      69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.783ns
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.247ns
 
  Physical Path Details:
 
-      Data path SLICE_3 to nRWE_MGIOL:
+      Data path SLICE_34 to ram2e_ufm/SLICE_55:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9C.CLK to       R5C9C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.081       R5C9C.Q0 to       R4C7B.C1 FS[11]
-CTOF_DEL    ---     0.495       R4C7B.C1 to       R4C7B.F1 SLICE_64
-ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
-CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
-ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
-CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
-ROUTE         3     0.453      R4C11C.F1 to      R4C11C.C0 N_628
-CTOF_DEL    ---     0.495      R4C11C.C0 to      R4C11C.F0 SLICE_75
-ROUTE         2     0.652      R4C11C.F0 to      R5C11B.D1 N_640
-CTOF_DEL    ---     0.495      R5C11B.D1 to      R5C11B.F1 SLICE_71
-ROUTE         1     1.023      R5C11B.F1 to      R5C13A.B0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495      R5C13A.B0 to      R5C13A.F0 SLICE_115
-ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
+ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
+CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.631      R5C10B.F1 to       R3C6A.A1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 ram2e_ufm/SLICE_81
+ROUTE         4     1.963       R3C6A.F1 to      R3C10A.C0 ram2e_ufm/N_856
+CTOF_DEL    ---     0.495      R3C10A.C0 to      R3C10A.F0 ram2e_ufm/SLICE_131
+ROUTE         1     1.535      R3C10A.F0 to       R3C6B.B1 ram2e_ufm/N_602
+CTOF_DEL    ---     0.495       R3C6B.B1 to       R3C6B.F1 ram2e_ufm/SLICE_55
+ROUTE         1     0.000       R3C6B.F1 to      R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c)
                   --------
-                   12.167   (28.1% logic, 71.9% route), 7 logic levels.
+                   11.517   (25.4% logic, 74.6% route), 6 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_3:
+      Source Clock Path C14M to SLICE_34:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R5C9C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to nRWE_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_55:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R3C6B.CLK C14M_c
                   --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+Passed: The following path meets requirements by 58.444ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              11.320ns  (30.2% logic, 69.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.320ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.444ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.097      R5C13B.Q1 to      R5C11D.B0 S[3]
+CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.755       R3C6C.F1 to       R2C7D.A0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R2C7D.A0 to       R2C7D.F0 ram2e_ufm/SLICE_99
+ROUTE         1     1.023       R2C7D.F0 to       R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0]
+CTOF_DEL    ---     0.495       R3C7A.B0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   11.320   (30.2% logic, 69.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.513ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              11.251ns  (30.4% logic, 69.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.251ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.513ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.097      R5C13B.Q1 to      R5C11D.B0 S[3]
+CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.962       R3C6C.F1 to       R3C7C.C0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R3C7C.C0 to       R3C7C.F0 ram2e_ufm/SLICE_126
+ROUTE         1     0.747       R3C7C.F0 to       R3C7A.C0 ram2e_ufm/N_753
+CTOF_DEL    ---     0.495       R3C7A.C0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   11.251   (30.4% logic, 69.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.525ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
    Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        Dout_0io[0]  (to C14M_c -)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+   Delay:              11.239ns  (26.0% logic, 74.0% route), 6 logic levels.
 
  Constraint Details:
 
-      6.181ns physical path delay SLICE_33 to Dout[0]_MGIOL meets
-     34.965ns delay constraint less
-     -0.173ns skew and
-      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+     11.239ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.525ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to Dout[0]_MGIOL:
+      Data path SLICE_33 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
-CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
-ROUTE        17     2.710      R7C12C.F1 to     IOL_B6B.CE N_576_i (to C14M_c)
+REG_DEL     ---     0.452     R5C13D.CLK to      R5C13D.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.500      R5C13D.Q0 to      R5C10B.C1 S[0]
+CTOF_DEL    ---     0.495      R5C10B.C1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.755       R3C6C.F1 to       R2C7D.A0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R2C7D.A0 to       R2C7D.F0 ram2e_ufm/SLICE_99
+ROUTE         1     1.023       R2C7D.F0 to       R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0]
+CTOF_DEL    ---     0.495       R3C7A.B0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+                   11.239   (26.0% logic, 74.0% route), 6 logic levels.
 
  Clock Skew Details: 
 
       Source Clock Path C14M to SLICE_33:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13D.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to Dout[0]_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to    IOL_B6B.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
                   --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+Passed: The following path meets requirements by 58.594ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
    Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        Dout_0io[1]  (to C14M_c -)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+   Delay:              11.170ns  (26.2% logic, 73.8% route), 6 logic levels.
 
  Constraint Details:
 
-      6.181ns physical path delay SLICE_33 to Dout[1]_MGIOL meets
-     34.965ns delay constraint less
-     -0.173ns skew and
-      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+     11.170ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.594ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to Dout[1]_MGIOL:
+      Data path SLICE_33 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
-CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
-ROUTE        17     2.710      R7C12C.F1 to     IOL_B4C.CE N_576_i (to C14M_c)
+REG_DEL     ---     0.452     R5C13D.CLK to      R5C13D.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.500      R5C13D.Q0 to      R5C10B.C1 S[0]
+CTOF_DEL    ---     0.495      R5C10B.C1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.962       R3C6C.F1 to       R3C7C.C0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R3C7C.C0 to       R3C7C.F0 ram2e_ufm/SLICE_126
+ROUTE         1     0.747       R3C7C.F0 to       R3C7A.C0 ram2e_ufm/N_753
+CTOF_DEL    ---     0.495       R3C7A.C0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+                   11.170   (26.2% logic, 73.8% route), 6 logic levels.
 
  Clock Skew Details: 
 
       Source Clock Path C14M to SLICE_33:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13D.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to Dout[1]_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to    IOL_B4C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
                   --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+Passed: The following path meets requirements by 58.622ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[7]  (to C14M_c +)
+
+   Delay:              11.142ns  (26.3% logic, 73.7% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.142ns physical path delay SLICE_34 to ram2e_ufm/SLICE_55 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.622ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.097      R5C13B.Q1 to      R5C11D.B0 S[3]
+CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.631      R5C10B.F1 to       R3C6A.A1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 ram2e_ufm/SLICE_81
+ROUTE         4     1.963       R3C6A.F1 to      R3C10A.C0 ram2e_ufm/N_856
+CTOF_DEL    ---     0.495      R3C10A.C0 to      R3C10A.F0 ram2e_ufm/SLICE_131
+ROUTE         1     1.535      R3C10A.F0 to       R3C6B.B1 ram2e_ufm/N_602
+CTOF_DEL    ---     0.495       R3C6B.B1 to       R3C6B.F1 ram2e_ufm/SLICE_55
+ROUTE         1     0.000       R3C6B.F1 to      R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c)
+                  --------
+                   11.142   (26.3% logic, 73.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to      R3C6B.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.703ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
    Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        Dout_0io[2]  (to C14M_c -)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[7]  (to C14M_c +)
 
-   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+   Delay:              11.061ns  (22.0% logic, 78.0% route), 5 logic levels.
 
  Constraint Details:
 
-      6.181ns physical path delay SLICE_33 to Dout[2]_MGIOL meets
-     34.965ns delay constraint less
-     -0.173ns skew and
-      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+     11.061ns physical path delay SLICE_33 to ram2e_ufm/SLICE_55 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.703ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to Dout[2]_MGIOL:
+      Data path SLICE_33 to ram2e_ufm/SLICE_55:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
-CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
-ROUTE        17     2.710      R7C12C.F1 to    IOL_L10D.CE N_576_i (to C14M_c)
+REG_DEL     ---     0.452     R5C13D.CLK to      R5C13D.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.500      R5C13D.Q0 to      R5C10B.C1 S[0]
+CTOF_DEL    ---     0.495      R5C10B.C1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.631      R5C10B.F1 to       R3C6A.A1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 ram2e_ufm/SLICE_81
+ROUTE         4     1.963       R3C6A.F1 to      R3C10A.C0 ram2e_ufm/N_856
+CTOF_DEL    ---     0.495      R3C10A.C0 to      R3C10A.F0 ram2e_ufm/SLICE_131
+ROUTE         1     1.535      R3C10A.F0 to       R3C6B.B1 ram2e_ufm/N_602
+CTOF_DEL    ---     0.495       R3C6B.B1 to       R3C6B.F1 ram2e_ufm/SLICE_55
+ROUTE         1     0.000       R3C6B.F1 to      R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c)
                   --------
-                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+                   11.061   (22.0% logic, 78.0% route), 5 logic levels.
 
  Clock Skew Details: 
 
       Source Clock Path C14M to SLICE_33:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13D.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to Dout[2]_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_55:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to   IOL_L10D.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R3C6B.CLK C14M_c
                   --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+Passed: The following path meets requirements by 58.866ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        Dout_0io[3]  (to C14M_c -)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+   Delay:              10.898ns  (31.4% logic, 68.6% route), 7 logic levels.
 
  Constraint Details:
 
-      6.181ns physical path delay SLICE_33 to Dout[3]_MGIOL meets
-     34.965ns delay constraint less
-     -0.173ns skew and
-      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+     10.898ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.866ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to Dout[3]_MGIOL:
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
-CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
-ROUTE        17     2.710      R7C12C.F1 to     IOL_B4D.CE N_576_i (to C14M_c)
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
+ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
+CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     3.058      R5C10B.F1 to       R3C5D.A1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C5D.A1 to       R3C5D.F1 ram2e_ufm/SLICE_89
+ROUTE         6     0.348       R3C5D.F1 to       R3C5C.D1 ram2e_ufm/N_783
+CTOF_DEL    ---     0.495       R3C5C.D1 to       R3C5C.F1 ram2e_ufm/SLICE_68
+ROUTE         1     0.986       R3C5C.F1 to       R3C7A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
+CTOF_DEL    ---     0.495       R3C7A.A0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+                   10.898   (31.4% logic, 68.6% route), 7 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_33:
+      Source Clock Path C14M to SLICE_34:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to Dout[3]_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to    IOL_B4D.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
                   --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-Report:   78.070MHz is the maximum frequency for this preference.
+Report:   84.310MHz is the maximum frequency for this preference.
 
 Report Summary
 --------------
@@ -555,7 +587,7 @@ Report Summary
 Preference                              |   Constraint|       Actual|Levels
 ----------------------------------------------------------------------------
                                         |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   78.070 MHz|   7  
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   84.310 MHz|   7  
                                         |             |             |
 ----------------------------------------------------------------------------
 
@@ -568,7 +600,7 @@ Clock Domains Analysis
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -578,11 +610,11 @@ Timing summary (Setup):
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:35:07 2023
+Thu Dec 28 23:10:17 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -607,92 +639,49 @@ BLOCK RESETPATHS
 
 ================================================================================
 Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 0.333ns
+Passed: The following path meets requirements by 0.342ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              wb_adr[2]  (from C14M_c +)
-   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
+   Source:         FF         Q              ram2e_ufm/wb_dati[6]  (from C14M_c +)
+   Destination:    EFB        Port           ram2e_ufm/ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
 
-   Delay:               0.306ns  (43.5% logic, 56.5% route), 1 logic levels.
+   Delay:               0.305ns  (43.6% logic, 56.4% route), 1 logic levels.
 
  Constraint Details:
 
-      0.306ns physical path delay SLICE_36 to ufmefb/EFBInst_0 meets
-     -0.081ns WBADRI_HLD and
+      0.305ns physical path delay ram2e_ufm/SLICE_55 to ram2e_ufm/ufmefb/EFBInst_0 meets
+     -0.091ns WBDATI_HLD and
       0.000ns delay constraint less
-     -0.054ns skew requirement (totaling -0.027ns) by 0.333ns
+     -0.054ns skew requirement (totaling -0.037ns) by 0.342ns
 
  Physical Path Details:
 
-      Data path SLICE_36 to ufmefb/EFBInst_0:
+      Data path ram2e_ufm/SLICE_55 to ram2e_ufm/ufmefb/EFBInst_0:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C5C.CLK to       R2C5C.Q0 SLICE_36 (from C14M_c)
-ROUTE         2     0.173       R2C5C.Q0 to    EFB.WBADRI2 wb_adr[2] (to C14M_c)
+REG_DEL     ---     0.133      R3C6B.CLK to       R3C6B.Q0 ram2e_ufm/SLICE_55 (from C14M_c)
+ROUTE         1     0.172       R3C6B.Q0 to    EFB.WBDATI6 ram2e_ufm/wb_dati[6] (to C14M_c)
                   --------
-                    0.306   (43.5% logic, 56.5% route), 1 logic levels.
+                    0.305   (43.6% logic, 56.4% route), 1 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_36:
+      Source Clock Path C14M to ram2e_ufm/SLICE_55:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R2C5C.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to      R3C6B.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to ufmefb/EFBInst_0:
+      Destination Clock Path C14M to ram2e_ufm/ufmefb/EFBInst_0:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.722       62.PADDI to     EFB.WBCLKI C14M_c
-                  --------
-                    1.722   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.358ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              wb_adr[3]  (from C14M_c +)
-   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
-
-   Delay:               0.307ns  (43.3% logic, 56.7% route), 1 logic levels.
-
- Constraint Details:
-
-      0.307ns physical path delay SLICE_36 to ufmefb/EFBInst_0 meets
-     -0.105ns WBADRI_HLD and
-      0.000ns delay constraint less
-     -0.054ns skew requirement (totaling -0.051ns) by 0.358ns
-
- Physical Path Details:
-
-      Data path SLICE_36 to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C5C.CLK to       R2C5C.Q1 SLICE_36 (from C14M_c)
-ROUTE         2     0.174       R2C5C.Q1 to    EFB.WBADRI3 wb_adr[3] (to C14M_c)
-                  --------
-                    0.307   (43.3% logic, 56.7% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_36:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R2C5C.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.722       62.PADDI to     EFB.WBCLKI C14M_c
+ROUTE        89     1.722       62.PADDI to     EFB.WBCLKI C14M_c
                   --------
                     1.722   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -701,43 +690,43 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              CmdBitbangMXO2  (from C14M_c +)
-   Destination:    FF         Data in        CmdBitbangMXO2  (to C14M_c +)
+   Source:         FF         Q              FS[15]  (from C14M_c +)
+   Destination:    FF         Data in        FS[15]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
  Constraint Details:
 
-      0.366ns physical path delay SLICE_12 to SLICE_12 meets
+      0.366ns physical path delay SLICE_1 to SLICE_1 meets
      -0.013ns DIN_HLD and
       0.000ns delay constraint less
       0.000ns skew requirement (totaling -0.013ns) by 0.379ns
 
  Physical Path Details:
 
-      Data path SLICE_12 to SLICE_12:
+      Data path SLICE_1 to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C7D.CLK to       R4C7D.Q0 SLICE_12 (from C14M_c)
-ROUTE         2     0.132       R4C7D.Q0 to       R4C7D.A0 CmdBitbangMXO2
-CTOF_DEL    ---     0.101       R4C7D.A0 to       R4C7D.F0 SLICE_12
-ROUTE         1     0.000       R4C7D.F0 to      R4C7D.DI0 CmdBitbangMXO2_4 (to C14M_c)
+REG_DEL     ---     0.133     R2C12A.CLK to      R2C12A.Q0 SLICE_1 (from C14M_c)
+ROUTE         9     0.132      R2C12A.Q0 to      R2C12A.A0 FS[15]
+CTOF_DEL    ---     0.101      R2C12A.A0 to      R2C12A.F0 SLICE_1
+ROUTE         1     0.000      R2C12A.F0 to     R2C12A.DI0 FS_s[15] (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_12:
+      Source Clock Path C14M to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R4C7D.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R2C12A.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_12:
+      Destination Clock Path C14M to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R4C7D.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R2C12A.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -746,233 +735,8 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              CmdExecMXO2  (from C14M_c +)
-   Destination:    FF         Data in        CmdExecMXO2  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_13 to SLICE_13 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_13 to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C7A.CLK to       R5C7A.Q0 SLICE_13 (from C14M_c)
-ROUTE         4     0.132       R5C7A.Q0 to       R5C7A.A0 CmdExecMXO2
-CTOF_DEL    ---     0.101       R5C7A.A0 to       R5C7A.F0 SLICE_13
-ROUTE         1     0.000       R5C7A.F0 to      R5C7A.DI0 CmdExecMXO2_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R5C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R5C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdLEDGet  (from C14M_c +)
-   Destination:    FF         Data in        CmdLEDGet  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_14 to SLICE_14 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R7C8A.CLK to       R7C8A.Q0 SLICE_14 (from C14M_c)
-ROUTE         2     0.132       R7C8A.Q0 to       R7C8A.A0 CmdLEDGet
-CTOF_DEL    ---     0.101       R7C8A.A0 to       R7C8A.F0 SLICE_14
-ROUTE         1     0.000       R7C8A.F0 to      R7C8A.DI0 CmdLEDGet_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R7C8A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R7C8A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdLEDSet  (from C14M_c +)
-   Destination:    FF         Data in        CmdLEDSet  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_15 to SLICE_15 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_15 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C7A.CLK to       R3C7A.Q0 SLICE_15 (from C14M_c)
-ROUTE         2     0.132       R3C7A.Q0 to       R3C7A.A0 CmdLEDSet
-CTOF_DEL    ---     0.101       R3C7A.A0 to       R3C7A.F0 SLICE_15
-ROUTE         1     0.000       R3C7A.F0 to      R3C7A.DI0 CmdLEDSet_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R3C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R3C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdRWMaskSet  (from C14M_c +)
-   Destination:    FF         Data in        CmdRWMaskSet  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_16 to SLICE_16 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_16 to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C7A.CLK to       R4C7A.Q0 SLICE_16 (from C14M_c)
-ROUTE         2     0.132       R4C7A.Q0 to       R4C7A.A0 CmdRWMaskSet
-CTOF_DEL    ---     0.101       R4C7A.A0 to       R4C7A.F0 SLICE_16
-ROUTE         1     0.000       R4C7A.F0 to      R4C7A.DI0 CmdRWMaskSet_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R4C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R4C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdSetRWBankFFLED  (from C14M_c +)
-   Destination:    FF         Data in        CmdSetRWBankFFLED  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_17 to SLICE_17 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_17 to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8B.CLK to       R3C8B.Q0 SLICE_17 (from C14M_c)
-ROUTE         2     0.132       R3C8B.Q0 to       R3C8B.A0 CmdSetRWBankFFLED
-CTOF_DEL    ---     0.101       R3C8B.A0 to       R3C8B.F0 SLICE_17
-ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 CmdSetRWBankFFLED_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R3C8B.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R3C8B.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdSetRWBankFFMXO2  (from C14M_c +)
-   Destination:    FF         Data in        CmdSetRWBankFFMXO2  (to C14M_c +)
+   Source:         FF         Q              CmdTout[2]  (from C14M_c +)
+   Destination:    FF         Data in        CmdTout[2]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -988,10 +752,10 @@ Passed: The following path meets requirements by 0.379ns
       Data path SLICE_18 to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R7C7A.CLK to       R7C7A.Q0 SLICE_18 (from C14M_c)
-ROUTE         2     0.132       R7C7A.Q0 to       R7C7A.A0 CmdSetRWBankFFMXO2
-CTOF_DEL    ---     0.101       R7C7A.A0 to       R7C7A.F0 SLICE_18
-ROUTE         1     0.000       R7C7A.F0 to      R7C7A.DI0 CmdSetRWBankFFMXO2_4 (to C14M_c)
+REG_DEL     ---     0.133     R8C11A.CLK to      R8C11A.Q1 SLICE_18 (from C14M_c)
+ROUTE         2     0.132      R8C11A.Q1 to      R8C11A.A1 CmdTout[2]
+CTOF_DEL    ---     0.101      R8C11A.A1 to      R8C11A.F1 SLICE_18
+ROUTE         1     0.000      R8C11A.F1 to     R8C11A.DI1 N_369_i (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -1000,14 +764,14 @@ ROUTE         1     0.000       R7C7A.F0 to      R7C7A.DI0 CmdSetRWBankFFMXO2_4
       Source Clock Path C14M to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R7C7A.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
       Destination Clock Path C14M to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R7C7A.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -1016,8 +780,53 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[14]  (from C14M_c +)
-   Destination:    FF         Data in        FS[14]  (to C14M_c +)
+   Source:         FF         Q              CmdTout[1]  (from C14M_c +)
+   Destination:    FF         Data in        CmdTout[1]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_18 to SLICE_18 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C11A.CLK to      R8C11A.Q0 SLICE_18 (from C14M_c)
+ROUTE         3     0.132      R8C11A.Q0 to      R8C11A.A0 CmdTout[1]
+CTOF_DEL    ---     0.101      R8C11A.A0 to      R8C11A.F0 SLICE_18
+ROUTE         1     0.000      R8C11A.F0 to     R8C11A.DI0 N_368_i (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[13]  (from C14M_c +)
+   Destination:    FF         Data in        FS[13]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -1033,10 +842,10 @@ Passed: The following path meets requirements by 0.379ns
       Data path SLICE_2 to SLICE_2:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q1 SLICE_2 (from C14M_c)
-ROUTE        13     0.132       R5C9D.Q1 to       R5C9D.A1 FS[14]
-CTOF_DEL    ---     0.101       R5C9D.A1 to       R5C9D.F1 SLICE_2
-ROUTE         1     0.000       R5C9D.F1 to      R5C9D.DI1 FS_s[14] (to C14M_c)
+REG_DEL     ---     0.133     R2C11D.CLK to      R2C11D.Q0 SLICE_2 (from C14M_c)
+ROUTE        19     0.132      R2C11D.Q0 to      R2C11D.A0 FS[13]
+CTOF_DEL    ---     0.101      R2C11D.A0 to      R2C11D.F0 SLICE_2
+ROUTE         1     0.000      R2C11D.F0 to     R2C11D.DI0 FS_s[13] (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -1045,14 +854,239 @@ ROUTE         1     0.000       R5C9D.F1 to      R5C9D.DI1 FS_s[14] (to C14M_c)
       Source Clock Path C14M to SLICE_2:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R5C9D.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R2C11D.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
       Destination Clock Path C14M to SLICE_2:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R5C9D.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R2C11D.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA[9]  (from C14M_c +)
+   Destination:    FF         Data in        RA[9]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_24 to SLICE_24 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_24 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11C.CLK to      R5C11C.Q1 SLICE_24 (from C14M_c)
+ROUTE         2     0.132      R5C11C.Q1 to      R5C11C.A1 RA[9]
+CTOF_DEL    ---     0.101      R5C11C.A1 to      R5C11C.F1 SLICE_24
+ROUTE         1     0.000      R5C11C.F1 to     R5C11C.DI1 RA_35[9] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA[8]  (from C14M_c +)
+   Destination:    FF         Data in        RA[8]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_24 to SLICE_24 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_24 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11C.CLK to      R5C11C.Q0 SLICE_24 (from C14M_c)
+ROUTE         2     0.132      R5C11C.Q0 to      R5C11C.A0 RA[8]
+CTOF_DEL    ---     0.101      R5C11C.A0 to      R5C11C.F0 SLICE_24
+ROUTE         1     0.000      R5C11C.F0 to     R5C11C.DI0 un2_S_2_i_0_0_o3_RNIHFHN3 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA[11]  (from C14M_c +)
+   Destination:    FF         Data in        RA[11]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_25 to SLICE_25 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_25 to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C12D.CLK to      R5C12D.Q1 SLICE_25 (from C14M_c)
+ROUTE         2     0.132      R5C12D.Q1 to      R5C12D.A1 RA[11]
+CTOF_DEL    ---     0.101      R5C12D.A1 to      R5C12D.F1 SLICE_25
+ROUTE         1     0.000      R5C12D.F1 to     R5C12D.DI1 RA_35[11] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C12D.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C12D.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RC[2]  (from C14M_c +)
+   Destination:    FF         Data in        RC[2]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_26 to SLICE_26 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_26 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C15C.CLK to      R4C15C.Q1 SLICE_26 (from C14M_c)
+ROUTE         5     0.132      R4C15C.Q1 to      R4C15C.A1 RC[2]
+CTOF_DEL    ---     0.101      R4C15C.A1 to      R4C15C.F1 SLICE_26
+ROUTE         1     0.000      R4C15C.F1 to     R4C15C.DI1 RC_3[2] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R4C15C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R4C15C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[12]  (from C14M_c +)
+   Destination:    FF         Data in        FS[12]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_3 to SLICE_3 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R2C11C.CLK to      R2C11C.Q1 SLICE_3 (from C14M_c)
+ROUTE        24     0.132      R2C11C.Q1 to      R2C11C.A1 FS[12]
+CTOF_DEL    ---     0.101      R2C11C.A1 to      R2C11C.F1 SLICE_3
+ROUTE         1     0.000      R2C11C.F1 to     R2C11C.DI1 FS_s[12] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R2C11C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R2C11C.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -1075,7 +1109,7 @@ Clock Domains Analysis
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -1085,7 +1119,7 @@ Timing summary (Hold):
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html
index 0b84c6b..c11c0a6 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html
@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Sep 21 05:35:17 2023
+Thu Dec 28 23:10:25 2023
 
 
 Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt
index 723be7e..eddc036 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt
@@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
 
 Implementation : impl1
 
-# Written on Thu Sep 21 05:34:38 2023
+# Written on Thu Dec 28 23:09:49 2023
 
 ##### DESIGN INFO #######################################################
 
@@ -58,7 +58,7 @@ p:Ain[6]
 p:Ain[7]
 p:BA[0]
 p:BA[1]
-p:CKE
+p:CKEout
 p:DQMH
 p:DQML
 p:Din[0]
@@ -79,18 +79,18 @@ p:Dout[6]
 p:Dout[7]
 p:LED
 p:PHI1
-p:RA[0]
-p:RA[1]
-p:RA[2]
-p:RA[3]
-p:RA[4]
-p:RA[5]
-p:RA[6]
-p:RA[7]
-p:RA[8]
-p:RA[9]
-p:RA[10]
-p:RA[11]
+p:RAout[0]
+p:RAout[1]
+p:RAout[2]
+p:RAout[3]
+p:RAout[4]
+p:RAout[5]
+p:RAout[6]
+p:RAout[7]
+p:RAout[8]
+p:RAout[9]
+p:RAout[10]
+p:RAout[11]
 p:RD[0] (bidir end point)
 p:RD[0] (bidir start point)
 p:RD[1] (bidir end point)
@@ -116,12 +116,12 @@ p:Vout[5]
 p:Vout[6]
 p:Vout[7]
 p:nC07X
-p:nCAS
-p:nCS
+p:nCASout
+p:nCSout
 p:nDOE
 p:nEN80
-p:nRAS
-p:nRWE
+p:nRASout
+p:nRWEout
 p:nVOE
 p:nWE
 p:nWE80
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_iotiming.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_iotiming.html
index bdf948f..98a9852 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_iotiming.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_iotiming.html
@@ -38,7 +38,7 @@ Performance Hardware Data Status:   Final          Version 34.4.
 // Package: TQFP100
 // ncd File: ram2e_lcmxo2_1200hc_impl1.ncd
 // Version: Diamond (64-bit) 3.12.1.454
-// Written on Thu Sep 21 05:35:11 2023
+// Written on Thu Dec 28 23:10:20 2023
 // M: Minimum Performance Grade
 // iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
 
@@ -50,82 +50,80 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
 
 Port   Clock Edge  Setup Performance_Grade  Hold Performance_Grade
 ----------------------------------------------------------------------
-Ain[0] C14M  R    -0.231      M       2.350     4
-Ain[1] C14M  R     1.429      4       0.543     4
-Ain[2] C14M  R     1.518      4       0.412     4
-Ain[3] C14M  R    -0.231      M       2.350     4
-Ain[4] C14M  R     0.212      4       1.560     4
-Ain[5] C14M  R     0.742      4       1.110     4
-Ain[6] C14M  R     0.469      4       1.329     4
-Ain[7] C14M  R     1.416      4       0.531     4
-Din[0] C14M  R     8.327      4       1.958     4
-Din[1] C14M  R     5.826      4       2.521     4
-Din[2] C14M  R     6.539      4       2.135     4
-Din[3] C14M  R     5.849      4       2.648     4
-Din[4] C14M  R     7.061      4       2.095     4
-Din[5] C14M  R     6.295      4       2.894     4
-Din[6] C14M  R     4.991      4       2.892     4
-Din[7] C14M  R     6.416      4       2.971     4
-PHI1   C14M  R     1.151      4       4.842     4
-RD[0]  C14M  F    -0.266      M       3.107     4
-RD[1]  C14M  F    -0.248      M       3.183     4
-RD[2]  C14M  F    -0.105      M       2.610     4
-RD[3]  C14M  F    -0.243      M       3.107     4
-RD[4]  C14M  F     0.103      4       2.201     4
-RD[5]  C14M  F    -0.092      M       2.192     4
-RD[6]  C14M  F    -0.084      M       1.756     4
-RD[7]  C14M  F    -0.092      M       2.661     4
-nC07X  C14M  R    -0.316      M       2.625     4
-nEN80  C14M  R     5.220      4       0.032     M
-nWE    C14M  R    -0.093      M       2.033     4
-nWE80  C14M  R     1.630      4       0.329     6
+Ain[0] C14M  R     0.163      4       1.694     4
+Ain[1] C14M  R    -0.150      M       2.217     4
+Ain[2] C14M  R    -0.080      M       2.156     4
+Ain[3] C14M  R     0.466      4       1.338     4
+Ain[4] C14M  R     0.215      4       1.597     4
+Ain[5] C14M  R    -0.331      M       2.651     4
+Ain[6] C14M  R     0.065      M       1.882     4
+Ain[7] C14M  R     0.284      4       1.683     4
+Din[0] C14M  R     6.887      4       2.257     4
+Din[1] C14M  R     8.753      4       2.907     4
+Din[2] C14M  R     6.379      4       2.740     4
+Din[3] C14M  R     7.129      4       1.402     4
+Din[4] C14M  R     6.869      4       2.791     4
+Din[5] C14M  R     6.514      4       2.334     4
+Din[6] C14M  R     6.735      4       1.914     4
+Din[7] C14M  R     8.094      4       1.968     4
+PHI1   C14M  R     1.557      4       4.842     4
+RD[0]  C14M  R    -0.266      M       2.342     4
+RD[1]  C14M  R    -0.248      M       2.283     4
+RD[2]  C14M  R    -0.407      M       2.610     4
+RD[3]  C14M  R    -0.243      M       2.193     4
+RD[4]  C14M  R    -0.246      M       2.201     4
+RD[5]  C14M  R    -0.243      M       2.193     4
+RD[6]  C14M  R    -0.087      M       1.756     4
+RD[7]  C14M  R    -0.092      M       1.769     4
+nC07X  C14M  R    -0.320      M       2.703     4
+nEN80  C14M  R     4.607      4       1.925     4
+nWE    C14M  R     4.609      4       2.010     4
 
 
 // Clock to Output Delay
 
-Port    Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+Port      Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
 ------------------------------------------------------------------------
-BA[0]   C14M  R    10.424         4        3.355          M
-BA[1]   C14M  R    10.424         4        3.355          M
-CKE     C14M  R    10.424         4        3.355          M
-DQMH    C14M  R    10.404         4        3.362          M
-DQML    C14M  R    10.404         4        3.362          M
-Dout[0] C14M  F    10.750         4        3.634          M
-Dout[1] C14M  F    10.750         4        3.634          M
-Dout[2] C14M  F    10.739         4        3.628          M
-Dout[3] C14M  F    10.750         4        3.634          M
-Dout[4] C14M  F    10.739         4        3.628          M
-Dout[5] C14M  F    10.739         4        3.628          M
-Dout[6] C14M  F    10.750         4        3.634          M
-Dout[7] C14M  F    10.750         4        3.634          M
-LED     C14M  R    21.299         4        8.576          M
-RA[0]   C14M  R    12.236         4        3.758          M
-RA[10]  C14M  R    10.490         4        3.360          M
-RA[11]  C14M  R    10.424         4        3.355          M
-RA[1]   C14M  R    10.490         4        3.360          M
-RA[2]   C14M  R    10.490         4        3.360          M
-RA[3]   C14M  R    11.808         4        3.656          M
-RA[4]   C14M  R    10.490         4        3.360          M
-RA[5]   C14M  R    10.490         4        3.360          M
-RA[6]   C14M  R    10.490         4        3.360          M
-RA[7]   C14M  R    10.490         4        3.360          M
-RA[8]   C14M  R    10.490         4        3.360          M
-RA[9]   C14M  R    10.490         4        3.360          M
-Vout[0] C14M  F    11.348         4        3.872          M
-Vout[1] C14M  F    11.434         4        3.871          M
-Vout[2] C14M  F    11.348         4        3.872          M
-Vout[3] C14M  F    11.434         4        3.871          M
-Vout[4] C14M  F    11.348         4        3.872          M
-Vout[5] C14M  F    11.348         4        3.872          M
-Vout[6] C14M  F    11.434         4        3.871          M
-Vout[7] C14M  F    11.434         4        3.871          M
-nCAS    C14M  R    10.424         4        3.355          M
-nCS     C14M  R    10.424         4        3.355          M
-nDOE    C14M  R    14.217         4        4.353          M
-nRAS    C14M  R    10.424         4        3.355          M
-nRWE    C14M  R    10.424         4        3.355          M
+BA[0]     C14M  R    10.424         4        3.355          M
+BA[1]     C14M  R    10.424         4        3.355          M
+CKEout    C14M  F    10.424         4        3.355          M
+DQMH      C14M  R    10.404         4        3.362          M
+DQML      C14M  R    10.404         4        3.362          M
+LED       C14M  R    22.936         4        8.890          M
+RAout[0]  C14M  F    10.490         4        3.360          M
+RAout[10] C14M  F    10.490         4        3.360          M
+RAout[11] C14M  F    10.424         4        3.355          M
+RAout[1]  C14M  F    10.490         4        3.360          M
+RAout[2]  C14M  F    10.490         4        3.360          M
+RAout[3]  C14M  F    10.490         4        3.360          M
+RAout[4]  C14M  F    10.490         4        3.360          M
+RAout[5]  C14M  F    10.490         4        3.360          M
+RAout[6]  C14M  F    10.490         4        3.360          M
+RAout[7]  C14M  F    10.490         4        3.360          M
+RAout[8]  C14M  F    10.490         4        3.360          M
+RAout[9]  C14M  F    10.490         4        3.360          M
+RD[0]     C14M  R    13.733         4        3.707          M
+RD[1]     C14M  R    13.745         4        3.707          M
+RD[2]     C14M  R    14.285         4        3.790          M
+RD[3]     C14M  R    13.348         4        3.790          M
+RD[4]     C14M  R    14.450         4        3.952          M
+RD[5]     C14M  R    14.480         4        3.952          M
+RD[6]     C14M  R    14.784         4        3.952          M
+RD[7]     C14M  R    14.247         4        3.952          M
+Vout[0]   C14M  R    11.348         4        3.872          M
+Vout[1]   C14M  R    11.434         4        3.871          M
+Vout[2]   C14M  R    11.348         4        3.872          M
+Vout[3]   C14M  R    11.434         4        3.871          M
+Vout[4]   C14M  R    11.348         4        3.872          M
+Vout[5]   C14M  R    11.348         4        3.872          M
+Vout[6]   C14M  R    11.434         4        3.871          M
+Vout[7]   C14M  R    11.434         4        3.871          M
+nCASout   C14M  F    10.424         4        3.355          M
+nDOE      C14M  R    13.929         4        4.309          M
+nRASout   C14M  F    10.424         4        3.355          M
+nRWEout   C14M  F    10.424         4        3.355          M
+nVOE      C14M  R    13.926         4        4.281          M
 WARNING: you must also run trce with hold speed: 4
-WARNING: you must also run trce with hold speed: 6
 WARNING: you must also run trce with setup speed: M
 
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf
index 865c239..492a1c7 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf
@@ -1,7 +1,7 @@
 (DELAYFILE
   (SDFVERSION "3.0")
   (DESIGN "RAM2E")
-  (DATE "Thu Sep 21 05:34:51 2023")
+  (DATE "Thu Dec 28 23:10:01 2023")
   (VENDOR "Lattice")
   (PROGRAM "ldbanno")
   (VERSION "Diamond (64-bit) 3.12.1.454")
@@ -233,9 +233,30 @@
     (INSTANCE SLICE_9)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_10")
+    (INSTANCE SLICE_10)
+    (DELAY
+      (ABSOLUTE
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -251,14 +272,37 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_10")
-    (INSTANCE SLICE_10)
+    (CELLTYPE "SLICE_11")
+    (INSTANCE SLICE_11)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_12")
+    (INSTANCE SLICE_12)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -279,13 +323,15 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_11")
-    (INSTANCE SLICE_11)
+    (CELLTYPE "SLICE_13")
+    (INSTANCE SLICE_13)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -303,60 +349,11 @@
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
   )
-  (CELL
-    (CELLTYPE "SLICE_12")
-    (INSTANCE SLICE_12)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_13")
-    (INSTANCE SLICE_13)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
   (CELL
     (CELLTYPE "SLICE_14")
     (INSTANCE SLICE_14)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -381,10 +378,10 @@
     (INSTANCE SLICE_15)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -405,6 +402,7 @@
     (INSTANCE SLICE_16)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -427,30 +425,6 @@
   (CELL
     (CELLTYPE "SLICE_17")
     (INSTANCE SLICE_17)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_18")
-    (INSTANCE SLICE_18)
     (DELAY
       (ABSOLUTE
         (IOPATH C1 F1 (367:431:495)(367:431:495))
@@ -473,8 +447,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19)
+    (CELLTYPE "SLICE_18")
+    (INSTANCE SLICE_18)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -498,6 +472,29 @@
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
   )
+  (CELL
+    (CELLTYPE "SLICE_19")
+    (INSTANCE SLICE_19)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
+      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (4000:4000:4000))
+      (WIDTH (negedge LSR) (4000:4000:4000))
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
   (CELL
     (CELLTYPE "SLICE_20")
     (INSTANCE SLICE_20)
@@ -512,10 +509,13 @@
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -530,13 +530,16 @@
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
@@ -550,6 +553,7 @@
     (INSTANCE SLICE_22)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -603,6 +607,7 @@
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -625,9 +630,11 @@
     (INSTANCE SLICE_25)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -775,6 +782,7 @@
     (INSTANCE SLICE_31)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -877,20 +885,18 @@
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
     )
     (TIMINGCHECK
+      (WIDTH (posedge LSR) (4000:4000:4000))
+      (WIDTH (negedge LSR) (4000:4000:4000))
       (WIDTH (posedge CLK) (1250:1250:1250))
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
@@ -900,18 +906,19 @@
     (INSTANCE SLICE_36)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -923,20 +930,19 @@
     (INSTANCE SLICE_37)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -948,6 +954,127 @@
     (INSTANCE SLICE_38)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_39")
+    (INSTANCE ram2e_ufm\/SLICE_39)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_40")
+    (INSTANCE ram2e_ufm\/SLICE_40)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_41")
+    (INSTANCE ram2e_ufm\/SLICE_41)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_42")
+    (INSTANCE ram2e_ufm\/SLICE_42)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_43")
+    (INSTANCE ram2e_ufm\/SLICE_43)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -968,11 +1095,10 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39)
+    (CELLTYPE "ram2e_ufm_SLICE_44")
+    (INSTANCE ram2e_ufm\/SLICE_44)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -980,9 +1106,11 @@
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
@@ -992,8 +1120,58 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_40")
-    (INSTANCE SLICE_40)
+    (CELLTYPE "ram2e_ufm_SLICE_45")
+    (INSTANCE ram2e_ufm\/SLICE_45)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_46")
+    (INSTANCE ram2e_ufm\/SLICE_46)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_47")
+    (INSTANCE ram2e_ufm\/SLICE_47)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1019,14 +1197,36 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41)
+    (CELLTYPE "ram2e_ufm_SLICE_48")
+    (INSTANCE ram2e_ufm\/SLICE_48)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_49")
+    (INSTANCE ram2e_ufm\/SLICE_49)
     (DELAY
       (ABSOLUTE
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1045,8 +1245,56 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42)
+    (CELLTYPE "ram2e_ufm_SLICE_50")
+    (INSTANCE ram2e_ufm\/SLICE_50)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_51")
+    (INSTANCE ram2e_ufm\/SLICE_51)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_52")
+    (INSTANCE ram2e_ufm\/SLICE_52)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1072,14 +1320,15 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43)
+    (CELLTYPE "ram2e_ufm_SLICE_53")
+    (INSTANCE ram2e_ufm\/SLICE_53)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1098,10 +1347,65 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44)
+    (CELLTYPE "ram2e_ufm_SLICE_54")
+    (INSTANCE ram2e_ufm\/SLICE_54)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_55")
+    (INSTANCE ram2e_ufm\/SLICE_55)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_56")
+    (INSTANCE ram2e_ufm\/SLICE_56)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -1125,10 +1429,12 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_45")
-    (INSTANCE SLICE_45)
+    (CELLTYPE "ram2e_ufm_SLICE_57")
+    (INSTANCE ram2e_ufm\/SLICE_57)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -1148,8 +1454,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_46")
-    (INSTANCE SLICE_46)
+    (CELLTYPE "ram2e_ufm_SLICE_58")
+    (INSTANCE ram2e_ufm\/SLICE_58)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1173,8 +1479,54 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_47")
-    (INSTANCE SLICE_47)
+    (CELLTYPE "ram2e_ufm_SUM0_i_m3_0_SLICE_59")
+    (INSTANCE ram2e_ufm\/SUM0_i_m3_0\/SLICE_59)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60")
+    (INSTANCE ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_CKE_7_SLICE_61")
+    (INSTANCE ram2e_ufm\/CKE_7\/SLICE_61)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_62")
+    (INSTANCE ram2e_ufm\/SLICE_62)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1189,8 +1541,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_48")
-    (INSTANCE SLICE_48)
+    (CELLTYPE "ram2e_ufm_SLICE_63")
+    (INSTANCE ram2e_ufm\/SLICE_63)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1205,8 +1557,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_49")
-    (INSTANCE SLICE_49)
+    (CELLTYPE "ram2e_ufm_SLICE_64")
+    (INSTANCE ram2e_ufm\/SLICE_64)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_65")
+    (INSTANCE ram2e_ufm\/SLICE_65)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1221,8 +1588,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50)
+    (CELLTYPE "ram2e_ufm_SLICE_66")
+    (INSTANCE ram2e_ufm\/SLICE_66)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1237,8 +1604,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51)
+    (CELLTYPE "ram2e_ufm_SLICE_67")
+    (INSTANCE ram2e_ufm\/SLICE_67)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_68")
+    (INSTANCE ram2e_ufm\/SLICE_68)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1253,8 +1635,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52)
+    (CELLTYPE "ram2e_ufm_SLICE_69")
+    (INSTANCE ram2e_ufm\/SLICE_69)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1269,8 +1651,52 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_53")
-    (INSTANCE SLICE_53)
+    (CELLTYPE "ram2e_ufm_SLICE_70")
+    (INSTANCE ram2e_ufm\/SLICE_70)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_71")
+    (INSTANCE ram2e_ufm\/SLICE_71)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_72")
+    (INSTANCE ram2e_ufm\/SLICE_72)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_73")
+    (INSTANCE ram2e_ufm\/SLICE_73)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1285,8 +1711,81 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_54")
-    (INSTANCE SLICE_54)
+    (CELLTYPE "ram2e_ufm_SLICE_74")
+    (INSTANCE ram2e_ufm\/SLICE_74)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_75")
+    (INSTANCE ram2e_ufm\/SLICE_75)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_76")
+    (INSTANCE ram2e_ufm\/SLICE_76)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_77")
+    (INSTANCE ram2e_ufm\/SLICE_77)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_78")
+    (INSTANCE ram2e_ufm\/SLICE_78)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_79")
+    (INSTANCE ram2e_ufm\/SLICE_79)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1301,8 +1800,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55)
+    (CELLTYPE "ram2e_ufm_SLICE_80")
+    (INSTANCE ram2e_ufm\/SLICE_80)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1317,22 +1816,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57)
+    (CELLTYPE "ram2e_ufm_SLICE_81")
+    (INSTANCE ram2e_ufm\/SLICE_81)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1347,8 +1832,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58)
+    (CELLTYPE "ram2e_ufm_SLICE_82")
+    (INSTANCE ram2e_ufm\/SLICE_82)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1363,8 +1848,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59)
+    (CELLTYPE "ram2e_ufm_SLICE_83")
+    (INSTANCE ram2e_ufm\/SLICE_83)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_84")
+    (INSTANCE ram2e_ufm\/SLICE_84)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1379,126 +1879,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_65")
-    (INSTANCE SLICE_65)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68)
+    (CELLTYPE "ram2e_ufm_SLICE_85")
+    (INSTANCE ram2e_ufm\/SLICE_85)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1513,8 +1895,66 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69)
+    (CELLTYPE "ram2e_ufm_SLICE_86")
+    (INSTANCE ram2e_ufm\/SLICE_86)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_87")
+    (INSTANCE ram2e_ufm\/SLICE_87)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_88")
+    (INSTANCE ram2e_ufm\/SLICE_88)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_89")
+    (INSTANCE ram2e_ufm\/SLICE_89)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_90")
+    (INSTANCE ram2e_ufm\/SLICE_90)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1529,8 +1969,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70)
+    (CELLTYPE "ram2e_ufm_SLICE_91")
+    (INSTANCE ram2e_ufm\/SLICE_91)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1545,8 +1985,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71)
+    (CELLTYPE "ram2e_ufm_SLICE_92")
+    (INSTANCE ram2e_ufm\/SLICE_92)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1561,8 +2001,37 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72)
+    (CELLTYPE "ram2e_ufm_SLICE_93")
+    (INSTANCE ram2e_ufm\/SLICE_93)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_94")
+    (INSTANCE ram2e_ufm\/SLICE_94)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_95")
+    (INSTANCE ram2e_ufm\/SLICE_95)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1577,8 +2046,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73)
+    (CELLTYPE "ram2e_ufm_SLICE_96")
+    (INSTANCE ram2e_ufm\/SLICE_96)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1593,8 +2062,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74)
+    (CELLTYPE "ram2e_ufm_SLICE_97")
+    (INSTANCE ram2e_ufm\/SLICE_97)
     (DELAY
       (ABSOLUTE
         (IOPATH C1 F1 (367:431:495)(367:431:495))
@@ -1608,23 +2077,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76)
+    (CELLTYPE "ram2e_ufm_SLICE_98")
+    (INSTANCE ram2e_ufm\/SLICE_98)
     (DELAY
       (ABSOLUTE
         (IOPATH B1 F1 (367:431:495)(367:431:495))
@@ -1637,8 +2091,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77)
+    (CELLTYPE "ram2e_ufm_SLICE_99")
+    (INSTANCE ram2e_ufm\/SLICE_99)
     (DELAY
       (ABSOLUTE
         (IOPATH C1 F1 (367:431:495)(367:431:495))
@@ -1652,50 +2106,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81)
+    (CELLTYPE "ram2e_ufm_SLICE_100")
+    (INSTANCE ram2e_ufm\/SLICE_100)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1710,8 +2122,93 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82)
+    (CELLTYPE "ram2e_ufm_SLICE_101")
+    (INSTANCE ram2e_ufm\/SLICE_101)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_102")
+    (INSTANCE ram2e_ufm\/SLICE_102)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_103")
+    (INSTANCE ram2e_ufm\/SLICE_103)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_104")
+    (INSTANCE ram2e_ufm\/SLICE_104)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_105")
+    (INSTANCE ram2e_ufm\/SLICE_105)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_106")
+    (INSTANCE ram2e_ufm\/SLICE_106)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_107")
+    (INSTANCE ram2e_ufm\/SLICE_107)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1726,8 +2223,140 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83)
+    (CELLTYPE "ram2e_ufm_SLICE_108")
+    (INSTANCE ram2e_ufm\/SLICE_108)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_109")
+    (INSTANCE ram2e_ufm\/SLICE_109)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_110")
+    (INSTANCE ram2e_ufm\/SLICE_110)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_111")
+    (INSTANCE ram2e_ufm\/SLICE_111)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_112")
+    (INSTANCE ram2e_ufm\/SLICE_112)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_113")
+    (INSTANCE ram2e_ufm\/SLICE_113)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_114")
+    (INSTANCE ram2e_ufm\/SLICE_114)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_115")
+    (INSTANCE ram2e_ufm\/SLICE_115)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_116")
+    (INSTANCE ram2e_ufm\/SLICE_116)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_117")
+    (INSTANCE ram2e_ufm\/SLICE_117)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1742,8 +2371,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84)
+    (CELLTYPE "ram2e_ufm_SLICE_118")
+    (INSTANCE ram2e_ufm\/SLICE_118)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1758,8 +2387,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85)
+    (CELLTYPE "ram2e_ufm_SLICE_119")
+    (INSTANCE ram2e_ufm\/SLICE_119)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1774,8 +2403,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86)
+    (CELLTYPE "ram2e_ufm_SLICE_120")
+    (INSTANCE ram2e_ufm\/SLICE_120)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1790,81 +2419,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92)
+    (CELLTYPE "ram2e_ufm_SLICE_121")
+    (INSTANCE ram2e_ufm\/SLICE_121)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1879,8 +2435,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93)
+    (CELLTYPE "ram2e_ufm_SLICE_122")
+    (INSTANCE ram2e_ufm\/SLICE_122)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1895,8 +2451,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94)
+    (CELLTYPE "ram2e_ufm_SLICE_123")
+    (INSTANCE ram2e_ufm\/SLICE_123)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_124")
+    (INSTANCE ram2e_ufm\/SLICE_124)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1911,8 +2482,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_95")
-    (INSTANCE SLICE_95)
+    (CELLTYPE "ram2e_ufm_SLICE_125")
+    (INSTANCE ram2e_ufm\/SLICE_125)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1927,80 +2498,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_96")
-    (INSTANCE SLICE_96)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_97")
-    (INSTANCE SLICE_97)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_98")
-    (INSTANCE SLICE_98)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_99")
-    (INSTANCE SLICE_99)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_100")
-    (INSTANCE SLICE_100)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_101")
-    (INSTANCE SLICE_101)
+    (CELLTYPE "ram2e_ufm_SLICE_126")
+    (INSTANCE ram2e_ufm\/SLICE_126)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2015,8 +2514,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_102")
-    (INSTANCE SLICE_102)
+    (CELLTYPE "ram2e_ufm_SLICE_127")
+    (INSTANCE ram2e_ufm\/SLICE_127)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2031,8 +2530,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_103")
-    (INSTANCE SLICE_103)
+    (CELLTYPE "ram2e_ufm_SLICE_128")
+    (INSTANCE ram2e_ufm\/SLICE_128)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_129")
+    (INSTANCE ram2e_ufm\/SLICE_129)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2047,8 +2561,22 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_104")
-    (INSTANCE SLICE_104)
+    (CELLTYPE "ram2e_ufm_SLICE_130")
+    (INSTANCE ram2e_ufm\/SLICE_130)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_131")
+    (INSTANCE ram2e_ufm\/SLICE_131)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2063,8 +2591,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_105")
-    (INSTANCE SLICE_105)
+    (CELLTYPE "ram2e_ufm_SLICE_132")
+    (INSTANCE ram2e_ufm\/SLICE_132)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2079,41 +2607,14 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_106")
-    (INSTANCE SLICE_106)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_107")
-    (INSTANCE SLICE_107)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_108")
-    (INSTANCE SLICE_108)
+    (CELLTYPE "ram2e_ufm_SLICE_133")
+    (INSTANCE ram2e_ufm\/SLICE_133)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -2121,8 +2622,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_109")
-    (INSTANCE SLICE_109)
+    (CELLTYPE "ram2e_ufm_SLICE_134")
+    (INSTANCE ram2e_ufm\/SLICE_134)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2137,8 +2638,152 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_110")
-    (INSTANCE SLICE_110)
+    (CELLTYPE "ram2e_ufm_SLICE_135")
+    (INSTANCE ram2e_ufm\/SLICE_135)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_136")
+    (INSTANCE ram2e_ufm\/SLICE_136)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_137")
+    (INSTANCE ram2e_ufm\/SLICE_137)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_138")
+    (INSTANCE SLICE_138)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_139")
+    (INSTANCE SLICE_139)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_140")
+    (INSTANCE ram2e_ufm\/SLICE_140)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_141")
+    (INSTANCE ram2e_ufm\/SLICE_141)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_142")
+    (INSTANCE ram2e_ufm\/SLICE_142)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_143")
+    (INSTANCE ram2e_ufm\/SLICE_143)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_144")
+    (INSTANCE ram2e_ufm\/SLICE_144)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_145")
+    (INSTANCE ram2e_ufm\/SLICE_145)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_146")
+    (INSTANCE ram2e_ufm\/SLICE_146)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2153,125 +2798,14 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_111")
-    (INSTANCE SLICE_111)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_112")
-    (INSTANCE SLICE_112)
+    (CELLTYPE "ram2e_ufm_SLICE_147")
+    (INSTANCE ram2e_ufm\/SLICE_147)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_113")
-    (INSTANCE SLICE_113)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_114")
-    (INSTANCE SLICE_114)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_115")
-    (INSTANCE SLICE_115)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_116")
-    (INSTANCE SLICE_116)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_117")
-    (INSTANCE SLICE_117)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_118")
-    (INSTANCE SLICE_118)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_119")
-    (INSTANCE SLICE_119)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
       )
@@ -2315,56 +2849,6 @@
       (WIDTH (negedge C14M) (3330:3330:3330))
     )
   )
-  (CELL
-    (CELLTYPE "DQMH")
-    (INSTANCE DQMH_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO DQMH (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "DQMH_MGIOL")
-    (INSTANCE DQMH_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "DQML")
-    (INSTANCE DQML_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO DQML (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "DQML_MGIOL")
-    (INSTANCE DQML_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
   (CELL
     (CELLTYPE "RD_7_")
     (INSTANCE RD\[7\]_I)
@@ -2478,117 +2962,17 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_11_")
-    (INSTANCE RA\[11\]_I)
+    (CELLTYPE "DQMH")
+    (INSTANCE DQMH_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA11 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO DQMH (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_11__MGIOL")
-    (INSTANCE RA\[11\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_")
-    (INSTANCE RA\[10\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA10 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10__MGIOL")
-    (INSTANCE RA\[10\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_")
-    (INSTANCE RA\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA9 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9__MGIOL")
-    (INSTANCE RA\[9\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_")
-    (INSTANCE RA\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA8 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8__MGIOL")
-    (INSTANCE RA\[8\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_")
-    (INSTANCE RA\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA7 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7__MGIOL")
-    (INSTANCE RA\[7\]_MGIOL)
+    (CELLTYPE "DQMH_MGIOL")
+    (INSTANCE DQMH_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
@@ -2604,17 +2988,17 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_6_")
-    (INSTANCE RA\[6\]_I)
+    (CELLTYPE "DQML")
+    (INSTANCE DQML_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA6 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO DQML (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_6__MGIOL")
-    (INSTANCE RA\[6\]_MGIOL)
+    (CELLTYPE "DQML_MGIOL")
+    (INSTANCE DQML_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
@@ -2630,127 +3014,305 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_5_")
-    (INSTANCE RA\[5\]_I)
+    (CELLTYPE "RAout_11_")
+    (INSTANCE RAout\[11\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA5 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO RAout11 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_5__MGIOL")
-    (INSTANCE RA\[5\]_MGIOL)
+    (CELLTYPE "RAout_11__MGIOL")
+    (INSTANCE RAout\[11\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_4_")
-    (INSTANCE RA\[4\]_I)
+    (CELLTYPE "RAout_10_")
+    (INSTANCE RAout\[10\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA4 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO RAout10 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_4__MGIOL")
-    (INSTANCE RA\[4\]_MGIOL)
+    (CELLTYPE "RAout_10__MGIOL")
+    (INSTANCE RAout\[10\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_3_")
-    (INSTANCE RA\[3\]_I)
+    (CELLTYPE "RAout_9_")
+    (INSTANCE RAout\[9\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH PADDO RA3 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO RAout9 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_2_")
-    (INSTANCE RA\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA2 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2__MGIOL")
-    (INSTANCE RA\[2\]_MGIOL)
+    (CELLTYPE "RAout_9__MGIOL")
+    (INSTANCE RAout\[9\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_1_")
-    (INSTANCE RA\[1\]_I)
+    (CELLTYPE "RAout_8_")
+    (INSTANCE RAout\[8\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA1 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO RAout8 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_1__MGIOL")
-    (INSTANCE RA\[1\]_MGIOL)
+    (CELLTYPE "RAout_8__MGIOL")
+    (INSTANCE RAout\[8\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_7_")
+    (INSTANCE RAout\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout7 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_7__MGIOL")
+    (INSTANCE RAout\[7\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_0_")
-    (INSTANCE RA\[0\]_I)
+    (CELLTYPE "RAout_6_")
+    (INSTANCE RAout\[6\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH PADDO RA0 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO RAout6 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
+  (CELL
+    (CELLTYPE "RAout_6__MGIOL")
+    (INSTANCE RAout\[6\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_5_")
+    (INSTANCE RAout\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout5 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_5__MGIOL")
+    (INSTANCE RAout\[5\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_4_")
+    (INSTANCE RAout\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout4 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_4__MGIOL")
+    (INSTANCE RAout\[4\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_3_")
+    (INSTANCE RAout\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout3 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_3__MGIOL")
+    (INSTANCE RAout\[3\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_2_")
+    (INSTANCE RAout\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout2 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_2__MGIOL")
+    (INSTANCE RAout\[2\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_1_")
+    (INSTANCE RAout\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout1 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_1__MGIOL")
+    (INSTANCE RAout\[1\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_0_")
+    (INSTANCE RAout\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout0 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_0__MGIOL")
+    (INSTANCE RAout\[0\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
   (CELL
     (CELLTYPE "BA_1_")
     (INSTANCE BA\[1\]_I)
@@ -2770,6 +3332,7 @@
     )
     (TIMINGCHECK
       (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
       (SETUPHOLD LSR (posedge CLK) (100:100:100)(-90:-90:-90))
     )
     (TIMINGCHECK
@@ -2796,6 +3359,7 @@
     )
     (TIMINGCHECK
       (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
       (SETUPHOLD LSR (posedge CLK) (100:100:100)(-90:-90:-90))
     )
     (TIMINGCHECK
@@ -2804,128 +3368,112 @@
     )
   )
   (CELL
-    (CELLTYPE "nRWE")
-    (INSTANCE nRWE_I)
+    (CELLTYPE "nRWEout")
+    (INSTANCE nRWEout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nRWE (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO nRWEout (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "nRWE_MGIOL")
-    (INSTANCE nRWE_MGIOL)
+    (CELLTYPE "nRWEout_MGIOL")
+    (INSTANCE nRWEout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nCAS")
-    (INSTANCE nCAS_I)
+    (CELLTYPE "nCASout")
+    (INSTANCE nCASout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nCAS (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO nCASout (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "nCAS_MGIOL")
-    (INSTANCE nCAS_MGIOL)
+    (CELLTYPE "nCASout_MGIOL")
+    (INSTANCE nCASout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nRAS")
-    (INSTANCE nRAS_I)
+    (CELLTYPE "nRASout")
+    (INSTANCE nRASout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nRAS (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO nRASout (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "nRAS_MGIOL")
-    (INSTANCE nRAS_MGIOL)
+    (CELLTYPE "nRASout_MGIOL")
+    (INSTANCE nRASout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nCS")
-    (INSTANCE nCS_I)
+    (CELLTYPE "nCSout")
+    (INSTANCE nCSout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nCS (2927:3031:3136)(2927:3031:3136))
+        (IOPATH PADDO nCSout (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "nCS_MGIOL")
-    (INSTANCE nCS_MGIOL)
+    (CELLTYPE "CKEout")
+    (INSTANCE CKEout_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO CKEout (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "CKEout_MGIOL")
+    (INSTANCE CKEout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
-  )
-  (CELL
-    (CELLTYPE "CKE")
-    (INSTANCE CKE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO CKE (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "CKE_MGIOL")
-    (INSTANCE CKE_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
     )
   )
   (CELL
@@ -2955,12 +3503,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -2981,12 +3529,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3007,12 +3555,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3033,12 +3581,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3059,12 +3607,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3085,12 +3633,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3111,12 +3659,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3137,12 +3685,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3159,209 +3707,73 @@
     (INSTANCE Dout\[7\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout7 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout7 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_7__MGIOL")
-    (INSTANCE Dout\[7\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_6_")
     (INSTANCE Dout\[6\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout6 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout6 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_6__MGIOL")
-    (INSTANCE Dout\[6\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_5_")
     (INSTANCE Dout\[5\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout5 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout5 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_5__MGIOL")
-    (INSTANCE Dout\[5\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_4_")
     (INSTANCE Dout\[4\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout4 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout4 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_4__MGIOL")
-    (INSTANCE Dout\[4\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_3_")
     (INSTANCE Dout\[3\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout3 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout3 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_3__MGIOL")
-    (INSTANCE Dout\[3\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_2_")
     (INSTANCE Dout\[2\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout2 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout2 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_2__MGIOL")
-    (INSTANCE Dout\[2\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_1_")
     (INSTANCE Dout\[1\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout1 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout1 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_1__MGIOL")
-    (INSTANCE Dout\[1\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_0_")
     (INSTANCE Dout\[0\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout0 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout0 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_0__MGIOL")
-    (INSTANCE Dout\[0\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Din_7_")
     (INSTANCE Din\[7\]_I)
@@ -3596,19 +4008,6 @@
       (WIDTH (negedge nEN80) (3330:3330:3330))
     )
   )
-  (CELL
-    (CELLTYPE "nWE80")
-    (INSTANCE nWE80_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nWE80 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nWE80) (3330:3330:3330))
-      (WIDTH (negedge nWE80) (3330:3330:3330))
-    )
-  )
   (CELL
     (CELLTYPE "nWE")
     (INSTANCE nWE_I)
@@ -3653,7 +4052,7 @@
   )
   (CELL
     (CELLTYPE "EFB_Buffer_Block")
-    (INSTANCE ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20)
+    (INSTANCE ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20)
     (DELAY
       (ABSOLUTE
         (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278))
@@ -3700,10 +4099,11 @@
     (DELAY
       (ABSOLUTE
         (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_39/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_52/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_75/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_119/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_51/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_69/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_105/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_108/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_146/A0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0))
@@ -3744,33 +4144,46 @@
         (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_39/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_46/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_39/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_40/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_41/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_42/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_43/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_44/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_45/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_46/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_47/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_48/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_49/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_50/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_51/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_52/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_53/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_54/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_55/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_56/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_57/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_58/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI DQMH_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI DQML_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[11\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[10\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[9\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[8\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[7\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[6\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[5\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[4\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[2\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[11\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[10\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[9\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[8\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[7\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[6\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[5\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[4\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[3\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[2\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[0\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI BA\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI BA\[0\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI nRWE_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI nCAS_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI nRAS_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI nCS_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI CKE_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI nRWEout_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI nCASout_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI nRASout_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI CKEout_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI Vout\[7\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI Vout\[6\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI Vout\[5\]_MGIOL/CLK (0:0:0)(0:0:0))
@@ -3779,1057 +4192,1300 @@
         (INTERCONNECT C14M_I/PADDI Vout\[2\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI Vout\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI Vout\[0\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[7\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[6\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[5\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[4\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[3\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[2\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[0\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI PHI1_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (0:0:0)(0:0:0))
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin 
+          (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_45/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_51/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_53/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_56/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_72/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_73/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_75/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_83/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_86/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_103/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 SLICE_9/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_69/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_80/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_105/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/A0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_37/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_37/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_38/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_39/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_44/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_45/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_45/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_56/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_66/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_73/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_86/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_97/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 SLICE_23/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_50/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_51/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_56/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_66/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_70/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_81/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_85/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_89/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_98/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_109/A1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_35/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_44/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_46/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_56/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_60/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_61/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_65/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_66/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_73/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_74/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_88/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_90/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_92/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_97/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_108/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_116/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 SLICE_23/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_56/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_58/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_64/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_70/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_75/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_76/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_81/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_85/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_89/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_97/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_103/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_111/B0 (0:0:0)(0:0:0))
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+        (INTERCONNECT SLICE_31/F1 SLICE_21/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_140/F1 SLICE_21/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_134/F0 SLICE_21/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT Ain\[2\]_I/PADDI SLICE_21/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_21/F1 SLICE_21/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0))
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-        (INTERCONNECT SLICE_21/Q0 SLICE_117/D1 (0:0:0)(0:0:0))
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-        (INTERCONNECT Ain\[0\]_I/PADDI SLICE_22/A0 (0:0:0)(0:0:0))
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         (INTERCONNECT SLICE_22/F1 SLICE_22/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0))
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-        (INTERCONNECT SLICE_27/Q0 SLICE_23/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_22/Q0 ram2e_ufm\/SLICE_95/D0 (0:0:0)(0:0:0))
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+        (INTERCONNECT ram2e_ufm\/SLICE_132/F0 SLICE_23/C1 (0:0:0)(0:0:0))
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         (INTERCONNECT SLICE_23/F1 SLICE_23/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0))
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-        (INTERCONNECT SLICE_28/Q0 SLICE_24/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_23/Q0 ram2e_ufm\/SLICE_96/D0 (0:0:0)(0:0:0))
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+        (INTERCONNECT SLICE_23/Q1 ram2e_ufm\/SLICE_132/D0 (0:0:0)(0:0:0))
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+        (INTERCONNECT ram2e_ufm\/SLICE_146/F1 SLICE_24/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_24/Q1 SLICE_24/B1 (0:0:0)(0:0:0))
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+        (INTERCONNECT ram2e_ufm\/SLICE_121/F0 SLICE_24/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F0 SLICE_25/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_24/Q0 SLICE_24/D0 (0:0:0)(0:0:0))
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+        (INTERCONNECT ram2e_ufm\/SLICE_78/F0 SLICE_24/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_127/F0 SLICE_24/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_115/F1 SLICE_24/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_115/F1 ram2e_ufm\/SLICE_115/A0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_24/F1 SLICE_24/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_24/Q0 SLICE_69/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_24/Q1 SLICE_103/A1 (0:0:0)(0:0:0))
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-        (INTERCONNECT SLICE_29/Q0 SLICE_25/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29/Q0 SLICE_25/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_25/Q1 SLICE_25/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_25/Q1 RAout\[11\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F0 SLICE_25/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F0 ram2e_ufm\/SLICE_74/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F0 ram2e_ufm\/SLICE_146/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F1 SLICE_25/D0 (0:0:0)(0:0:0))
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+        (INTERCONNECT ram2e_ufm\/SLICE_129/F0 SLICE_25/B0 (0:0:0)(0:0:0))
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         (INTERCONNECT SLICE_25/F1 SLICE_25/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0))
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-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_49/B1 (0:0:0)(0:0:0))
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-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_81/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_87/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_91/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_25/Q0 ram2e_ufm\/SLICE_106/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_25/Q0 RAout\[10\]_MGIOL/OPOS (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_26/F1 SLICE_26/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_26/Q0 SLICE_47/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_26/Q0 SLICE_59/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_26/Q1 SLICE_96/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO1 SLICE_27/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_43/Q1 SLICE_27/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_27/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_27/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_29/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_29/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/B0 (0:0:0)(0:0:0))
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         (INTERCONNECT SLICE_27/F1 SLICE_27/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0))
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-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO3 SLICE_28/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO2 SLICE_28/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_27/Q1 ram2e_ufm\/SLICE_78/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_44/Q1 SLICE_28/C1 (0:0:0)(0:0:0))
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         (INTERCONNECT SLICE_28/F1 SLICE_28/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_28/F0 SLICE_28/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO5 SLICE_29/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO4 SLICE_29/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_28/Q0 ram2e_ufm\/SLICE_146/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_28/Q1 ram2e_ufm\/SLICE_74/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_45/Q1 SLICE_29/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_45/Q0 SLICE_29/C0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_29/F1 SLICE_29/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO7 SLICE_30/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO6 SLICE_30/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29/Q1 ram2e_ufm\/SLICE_72/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_46/Q1 SLICE_30/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_46/Q0 SLICE_30/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_30/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_40/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_42/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_46/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_50/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/C1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_62/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_65/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_82/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_83/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_144/A0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT nWE_I/PADDI SLICE_31/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30/Q0 ram2e_ufm\/SLICE_129/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30/Q1 ram2e_ufm\/SLICE_127/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Ain\[3\]_I/PADDI SLICE_31/A1 (0:0:0)(0:0:0))
         (INTERCONNECT nWE_I/PADDI SLICE_31/D0 (0:0:0)(0:0:0))
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-        (INTERCONNECT nEN80_I/PADDI SLICE_79/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT nEN80_I/PADDI SLICE_106/A0 (0:0:0)(0:0:0))
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-        (INTERCONNECT nEN80_I/PADDI SLICE_117/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT nWE_I/PADDI SLICE_36/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/CKE_7\/SLICE_61/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_92/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_112/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_113/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_136/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_136/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_137/C1 (0:0:0)(0:0:0))
         (INTERCONNECT nC07X_I/PADDI SLICE_31/C0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0))
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-        (INTERCONNECT SLICE_97/F0 SLICE_75/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_127/F1 SLICE_31/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_131/F1 SLICE_32/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_57/F1 SLICE_32/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_146/F0 SLICE_32/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_110/F1 SLICE_32/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_110/F1 ram2e_ufm\/SLICE_58/C1 (0:0:0)(0:0:0))
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+        (INTERCONNECT SLICE_32/Q0 SLICE_32/B0 (0:0:0)(0:0:0))
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+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_137/B0 (0:0:0)(0:0:0))
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+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT PHI1_I/PADDI SLICE_139/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI1_I/PADDI SLICE_139/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI1_I/PADDI PHI1_MGIOL/DI (0:0:0)(0:0:0))
+        (INTERCONNECT PHI1_MGIOL/IN SLICE_139/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_139/F1 nVOE_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_141/F0 RD\[3\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_141/F1 RD\[0\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_142/F0 RD\[4\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_143/F0 RD\[7\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_143/F1 RD\[1\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_144/F0 RD\[6\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_144/F1 RD\[2\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F0 RD\[5\]_I/PADDO (0:0:0)(0:0:0))
         (INTERCONNECT RD\[0\]_I/PADDI Vout\[0\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0))
         (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[9\]_MGIOL/IOLDO RA\[9\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[8\]_MGIOL/IOLDO RA\[8\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[7\]_MGIOL/IOLDO RA\[7\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[6\]_MGIOL/IOLDO RA\[6\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[5\]_MGIOL/IOLDO RA\[5\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[4\]_MGIOL/IOLDO RA\[4\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[2\]_MGIOL/IOLDO RA\[2\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[1\]_MGIOL/IOLDO RA\[1\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[11\]_MGIOL/IOLDO RAout\[11\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[10\]_MGIOL/IOLDO RAout\[10\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[9\]_MGIOL/IOLDO RAout\[9\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[8\]_MGIOL/IOLDO RAout\[8\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[7\]_MGIOL/IOLDO RAout\[7\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[6\]_MGIOL/IOLDO RAout\[6\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[5\]_MGIOL/IOLDO RAout\[5\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[4\]_MGIOL/IOLDO RAout\[4\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[3\]_MGIOL/IOLDO RAout\[3\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[2\]_MGIOL/IOLDO RAout\[2\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[1\]_MGIOL/IOLDO RAout\[1\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[0\]_MGIOL/IOLDO RAout\[0\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nCAS_MGIOL/IOLDO nCAS_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRAS_MGIOL/IOLDO nRAS_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nCS_MGIOL/IOLDO nCS_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT CKE_MGIOL/IOLDO CKE_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT nRWEout_MGIOL/IOLDO nRWEout_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT nCASout_MGIOL/IOLDO nCASout_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT nRASout_MGIOL/IOLDO nRASout_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT CKEout_MGIOL/IOLDO CKEout_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (0:0:0)(0:0:0))
@@ -4838,14 +5494,6 @@
         (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[7\]_MGIOL/IOLDO Dout\[7\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[6\]_MGIOL/IOLDO Dout\[6\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[5\]_MGIOL/IOLDO Dout\[5\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[4\]_MGIOL/IOLDO Dout\[4\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[3\]_MGIOL/IOLDO Dout\[3\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[2\]_MGIOL/IOLDO Dout\[2\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[1\]_MGIOL/IOLDO Dout\[1\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[0\]_MGIOL/IOLDO Dout\[0\]_I/IOLDO (0:0:0)(0:0:0))
       )
     )
   )
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo
index 2a9bbde..753bfe9 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo
@@ -2,8 +2,8 @@
 // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
 
 // ldbanno -n Verilog -o RAM2E_LCMXO2_1200HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd 
-// Netlist created on Thu Sep 21 05:34:46 2023
-// Netlist written on Thu Sep 21 05:34:51 2023
+// Netlist created on Thu Dec 28 23:09:57 2023
+// Netlist written on Thu Dec 28 23:10:01 2023
 // Design is for device LCMXO2-1200HC
 // Design is for package TQFP100
 // Design is for performance grade 4
@@ -11,7 +11,8 @@
 `timescale 1 ns / 1 ps
 
 module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, 
-               Vout, nVOE, CKE, nCS, nRAS, nCAS, nRWE, BA, RA, RD, DQML, DQMH );
+               Vout, nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout, BA, 
+               RAout, DQML, DQMH, RD );
   input  C14M, PHI1, nWE, nWE80, nEN80, nC07X;
   input  [7:0] Ain;
   input  [7:0] Din;
@@ -19,9 +20,9 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   output [7:0] Dout;
   output nDOE;
   output [7:0] Vout;
-  output nVOE, CKE, nCS, nRAS, nCAS, nRWE;
+  output nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout;
   output [1:0] BA;
-  output [11:0] RA;
+  output [11:0] RAout;
   output DQML, DQMH;
   inout  [7:0] RD;
   wire   \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , 
@@ -30,77 +31,141 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
          \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , 
          \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , 
          \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , 
-         \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , Ready, 
-         PHI1reg, PHI1_c, RWSel, CO0_1, \CmdTout_3[0] , N_576_i, S_1, \CS[0] , 
-         N_461, \S_RNII9DO1_0[1] , \CS[1] , N_511_i, N_504_i, 
-         un1_CS_0_sqmuxa_i, N_637, \CS[2] , N_510_i, \Din_c[3] , \Din_c[2] , 
-         \Din_c[0] , N_643, CmdBitbangMXO2_4_u_0_0_a2_0_1, CmdBitbangMXO2, 
-         CmdBitbangMXO2_4, \Din_c[7] , \Din_c[5] , N_629, CmdExecMXO2, 
-         CmdExecMXO2_4, N_466, N_478, \Din_c[4] , \Din_c[1] , N_476, 
-         CmdLEDGet_4_u_0_0_a2_0_2, CmdLEDGet, CmdLEDGet_4, N_626, N_605, 
-         CmdLEDSet, CmdLEDSet_4, CmdRWMaskSet, CmdRWMaskSet_4, N_401, 
-         CmdSetRWBankFFLED, CmdSetRWBankFFLED_4, N_474, 
-         CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0, CmdSetRWBankFFMXO2, 
-         CmdSetRWBankFFMXO2_4, \CmdTout[1] , \CmdTout[2] , N_556_i, N_555_i, 
-         \S[0] , \S[1] , \S[2] , \S[3] , N_6_i, DOEEN, \Ain_c[1] , 
-         \wb_dato[0] , LEDEN_RNO, \un1_LEDEN_0_sqmuxa_1_i_0[0] , LEDEN, 
-         N_558_i, \Ain_c[3] , \Ain_c[0] , N_552_i, N_127_i, \S_RNII9DO1_1[1] , 
-         \RA_c[0] , \RA_c[3] , \RWMask[1] , N_591, \RWMask[0] , \RWBank_5[1] , 
-         \RWBank_5[0] , LEDEN13, \RWBank[0] , \RWBank[1] , \RWMask[3] , 
-         \RWMask[2] , \RWBank_5[3] , \RWBank_5[2] , \RWBank[2] , \RWBank[3] , 
-         \RWMask[5] , \RWMask[4] , \RWBank_5[5] , \RWBank_5[4] , \RWBank[4] , 
-         \RWBank[5] , \RWMask[7] , \RWMask[6] , \Din_c[6] , \RWBank_5[7] , 
-         \RWBank_5[6] , \RWBank[6] , \RWBank[7] , \wb_dato[1] , N_291_i, 
-         N_292_i, N_88, \wb_dato[3] , \wb_dato[2] , N_289_i, N_290_i, 
-         \wb_dato[5] , \wb_dato[4] , N_287_i, N_288_i, \wb_dato[7] , 
-         \wb_dato[6] , N_285, N_286_i, nWE_c, nEN80_c, nC07X_c, RWSel_2, nCS61, 
-         nDOE_c, Ready_0_sqmuxa_0_a2_6_a2_4, N_489, Ready_0_sqmuxa, N_876_0, 
-         wb_reqc_1, N_575, N_572, \S_s_0_1[0] , N_133_i, \S_s_0[0] , N_129_i, 
-         N_131_i, wb_adr_7_5_214_0_1, N_388, \wb_adr_7_0_4[0] , N_642, N_376, 
-         \wb_adr_RNO[1] , \wb_adr_7[0] , \un1_wb_adr_0_sqmuxa_2_i[0] , 
-         \wb_adr[0] , \wb_adr[1] , N_41_i, N_43_i, \wb_adr[2] , \wb_adr[3] , 
-         N_295, N_294, \wb_adr[4] , \wb_adr[5] , N_39_i, N_296, \wb_adr[6] , 
-         \wb_adr[7] , wb_ack, N_300, N_395, wb_cyc_stb_RNO, N_104, wb_cyc_stb, 
-         \wb_dati_7_0_0[1] , N_627, N_621, N_336, \wb_dati_7_0_a2_1[0] , N_484, 
-         \wb_dati_7[1] , \wb_dati_7[0] , \wb_dati[0] , \wb_dati[1] , 
-         \wb_dati_7_0_2[3] , \wb_dati_7_0_0[3] , \wb_dati_7_0_o2_0[2] , N_345, 
-         \wb_dati_7[3] , \wb_dati_7[2] , \wb_dati[2] , \wb_dati[3] , 
-         \wb_dati_7_0_0[4] , N_349, N_346, \wb_dati_7[5] , \wb_dati_7[4] , 
-         \wb_dati[4] , \wb_dati[5] , \wb_dati_7_0_0[7] , \wb_dati_7_0_RNO[7] , 
-         N_424, N_422, \wb_dati_7_0_1[6] , \wb_dati_7[7] , \wb_dati_7[6] , 
-         \wb_dati[6] , \wb_dati[7] , N_397, wb_reqc_i, wb_adr_0_sqmuxa_i, 
-         wb_req, wb_rst8, \S_RNII9DO1[1] , wb_rst, N_586, wb_we_7_iv_0_0_0_1, 
-         N_584, N_475, wb_we_RNO, \un1_wb_cyc_stb_0_sqmuxa_1_i[0] , wb_we, 
-         N_255, N_358_i, N_635, N_254, Vout3, nCAS_s_i_tz_0, 
-         un1_CS_0_sqmuxa_0_0_a2_1_4, N_327, un1_CS_0_sqmuxa_0_0_0, 
-         \wb_dati_7_0_a2_0_1[7] , N_579, CKE_6_iv_i_a2_0, CKE_6_iv_i_0_1, 
-         CKE_6_iv_i_0, N_449, N_365, N_364, \un1_wb_adr_0_sqmuxa_2_1[0] , 
-         N_623, N_616, N_279, N_633, N_264, N_570, N_452, 
-         \wb_dati_7_0_a2_2_1[3] , N_644, N_455, DQML_s_i_a2_0, N_28_i, 
-         wb_adr_7_5_214_a2_2_0, N_577, N_569, N_634, \wb_dati_7_0_a2_2_0[1] , 
-         N_265_i, \un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] , \wb_dati_7_0_a2_0[6] , 
-         \wb_dati_7_0_a2_4_0[7] , N_393, nCAS_0_sqmuxa, N_639, \RA_42[10] , 
-         N_640, un1_nCS61_1_i, Ready_0_sqmuxa_0_a2_6_a2_2, N_562, N_377, N_628, 
-         un1_CS_0_sqmuxa_0_0_a2_3_2, un1_CS_0_sqmuxa_0_0_3, 
-         un1_CS_0_sqmuxa_0_0_2, N_567, N_561_i, nCS_6_u_i_0, N_559_1, N_559_i, 
-         nRAS_2_iv_i, un1_CS_0_sqmuxa_0_0_a2_1, N_330, N_328, nCS_6_u_i_a2_1, 
-         N_429, N_351, \wb_adr_7_0_a2_5_0[0] , \wb_adr_7_0_1[0] , 
-         \wb_adr_7_0_0[0] , N_378, \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] , 
-         un1_CS_0_sqmuxa_0_0_a2_4_2, un1_CS_0_sqmuxa_0_0_a2_4_4, N_565, 
-         un1_CS_0_sqmuxa_0_0_a2_2_2, un1_CS_0_sqmuxa_0_0_a2_2_4, 
-         \wb_adr_7_0_a2_0[0] , un1_CS_0_sqmuxa_0_0_a2_1_2, 
-         un1_CS_0_sqmuxa_0_0_a2_3_0, N_394, N_49_i, N_456, N_477, N_566_i, 
-         \BA_4[0] , \RA_42[11] , \BA_4[1] , N_59_i, \Ain_c[5] , \Ain_c[4] , 
-         N_551_i, \RA_42_3_0[5] , \Ain_c[6] , N_550_i, \Ain_c[2] , \Ain_c[7] , 
-         N_549_i, N_553_i, nWE80_c, nRWE_r_0, RDOE_i, LED_c, \RD_in[0] , 
-         DQMH_c, DQML_c, \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , 
-         \RD_in[3] , \RD_in[2] , \RD_in[1] , \RA_c[11] , \RA_c[10] , \RA_c[9] , 
-         \RA_c[8] , \RA_c[7] , \RA_c[6] , \RA_c[5] , \RA_c[4] , \RA_c[2] , 
-         \RA_c[1] , \BA_c[1] , \BA_c[0] , nRWE_c, nCAS_c, nRAS_c, nCS_c, CKE_c, 
+         \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_551, 
+         \S[1] , \S[0] , \ram2e_ufm/CKE_7 , CKE_7_RNIS77M1, CKE, 
+         \ram2e_ufm/wb_adr_0_sqmuxa_1_i , RWSel, CO0_0, \CmdTout_3[0] , 
+         N_185_i, GND, \RC[2] , CO0_1, \RC[1] , N_360_i, RC12, 
+         \ram2e_ufm/N_821 , \ram2e_ufm/SUM1_0_0 , \ram2e_ufm/SUM0_i_a3_4_0 , 
+         \ram2e_ufm/N_886 , \ram2e_ufm/N_215 , \ram2e_ufm/SUM0_i_4 , \CS[2] , 
+         \CS[1] , CmdExecMXO2_3_0_a3_0_RNI6S1P8, N_547_i, un1_CS_0_sqmuxa_i, 
+         \CS[0] , \ram2e_ufm/N_234 , CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514, 
+         \ram2e_ufm/N_800 , \Din_c[5] , \Din_c[3] , 
+         \ram2e_ufm/CmdLEDGet_3_0_a3_1 , \ram2e_ufm/N_847 , \Din_c[2] , 
+         \Din_c[1] , CmdLEDGet_3, N_187_i, CmdLEDGet, \Din_c[7] , \Din_c[4] , 
+         \ram2e_ufm/N_883 , CmdLEDSet_3, CmdLEDSet, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 , CmdRWMaskSet_3, CmdRWMaskSet, 
+         \ram2e_ufm/N_850 , \Din_c[0] , CmdSetRWBankFFLED_4, CmdSetRWBankFFLED, 
+         \CmdTout[2] , \CmdTout[1] , N_369_i, N_368_i, \RA[1] , 
+         \ram2e_ufm/N_186 , \S[3] , N_1080_0, \ram2e_ufm/N_660 , DOEEN, 
+         \ram2e_ufm/N_193 , \ram2e_ufm/N_659 , \ram2e_ufm/N_182 , \Ain_c[1] , 
+         \ram2e_ufm/RA_35_0_0_1[0] , \ram2e_ufm/N_801 , \ram2e_ufm/N_684 , 
+         N_223, \RA_35[0] , N_126, \RA[0] , \ram2e_ufm/RA_35_0_0_0[3] , 
+         \ram2e_ufm/N_680 , \ram2e_ufm/N_679 , \Ain_c[2] , \RA_35[3] , 
+         \RA_35[2] , \RA[2] , \RA[3] , \ram2e_ufm/RA_35_0_0_0[5] , 
+         \ram2e_ufm/N_621 , \Ain_c[5] , \ram2e_ufm/RA_35_0_0_0[4] , \RA_35[5] , 
+         \RA_35[4] , \RA[4] , \RA[5] , \ram2e_ufm/RA_35_0_0_0_0[7] , 
+         \ram2e_ufm/RA_35_0_0_0_0[6] , \RA_35[7] , \RA_35[6] , \RA[6] , 
+         \RA[7] , \ram2e_ufm/RA_35_0_0_0[9] , \RA[9] , \ram2e_ufm/N_242 , 
+         \RA[8] , \ram2e_ufm/N_699 , \ram2e_ufm/N_698 , \ram2e_ufm/N_221 , 
+         \RA_35[9] , un2_S_2_i_0_0_o3_RNIHFHN3, \RWBank[4] , \RA[11] , 
+         \ram2e_ufm/N_845 , \ram2e_ufm/RA_35_2_0_0[10] , \ram2e_ufm/N_628 , 
+         \ram2e_ufm/N_627 , \ram2e_ufm/N_624 , \RA_35[11] , \RA_35[10] , 
+         \RA[10] , \RC_3[2] , \RC_3[1] , \ram2e_ufm/RWMask[1] , 
+         \ram2e_ufm/N_188 , \ram2e_ufm/RWMask[0] , \RWBank_3[1] , 
+         \RWBank_3[0] , \RWBank[0] , \RWBank[1] , \ram2e_ufm/RWMask[3] , 
+         \ram2e_ufm/RWMask[2] , \RWBank_3[3] , \RWBank_3[2] , \RWBank[2] , 
+         \RWBank[3] , \ram2e_ufm/RWMask[5] , \ram2e_ufm/RWMask[4] , 
+         \RWBank_3[5] , \RWBank_3[4] , \RWBank[5] , \ram2e_ufm/RWMask[7] , 
+         \ram2e_ufm/RWMask[6] , \Din_c[6] , \RWBank_3[7] , \RWBank_3[6] , 
+         \RWBank[6] , \RWBank[7] , \Ain_c[3] , nWE_c, nC07X_c, RWSel_2, 
+         un9_VOEEN_0_a2_0_a3_0_a3, \ram2e_ufm/Ready3_0_a3_5 , 
+         \ram2e_ufm/Ready3_0_a3_4 , \ram2e_ufm/Ready3_0_a3_3 , 
+         \ram2e_ufm/N_885 , Ready, Ready3, N_1026_0, \ram2e_ufm/S_r_i_0_o2[1] , 
+         \ram2e_ufm/N_271 , \ram2e_ufm/N_194 , S_1, \ram2e_ufm/N_643 , N_362_i, 
+         \S_s_0_0[0] , \S[2] , N_372_i, N_361_i, N_1078_0, VOEEN, BA_0_sqmuxa, 
+         \ram2e_ufm/N_285_i , \ram2e_ufm/N_804 , \ram2e_ufm/N_872 , 
+         \ram2e_ufm/N_641 , \ram2e_ufm/N_640 , N_370_i, nCAS, 
+         \ram2e_ufm/nRAS_s_i_0_0 , \ram2e_ufm/N_617 , \ram2e_ufm/N_616 , 
+         \ram2e_ufm/N_615 , N_358_i, nRAS, \ram2e_ufm/N_226 , 
+         \ram2e_ufm/N_866 , \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] , N_359_i, nRWE, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 , 
+         \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 , \ram2e_ufm/CmdBitbangMXO2_3 , 
+         \ram2e_ufm/CmdBitbangMXO2 , \ram2e_ufm/N_851 , 
+         \ram2e_ufm/CmdExecMXO2_3 , \ram2e_ufm/CmdExecMXO2 , 
+         \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 , \ram2e_ufm/N_190 , 
+         \ram2e_ufm/CmdSetRWBankFFChip_3 , \ram2e_ufm/CmdSetRWBankFFChip , 
+         \ram2e_ufm/wb_dato[0] , \ram2e_ufm/N_295 , 
+         \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] , \ram2e_ufm/LEDEN , 
+         \ram2e_ufm/N_212 , \ram2e_ufm/wb_dato[1] , \ram2e_ufm/N_307_i , 
+         \ram2e_ufm/N_309_i , \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] , 
+         \ram2e_ufm/wb_dato[3] , \ram2e_ufm/wb_dato[2] , \ram2e_ufm/N_302_i , 
+         \ram2e_ufm/N_304_i , \ram2e_ufm/wb_dato[5] , \ram2e_ufm/wb_dato[4] , 
+         \ram2e_ufm/N_301_i , \ram2e_ufm/N_310_i , \ram2e_ufm/wb_dato[7] , 
+         \ram2e_ufm/wb_dato[6] , \ram2e_ufm/N_296 , \ram2e_ufm/N_300_i , 
+         \ram2e_ufm/wb_adr_7_5_41_0_1 , \ram2e_ufm/N_768 , 
+         \ram2e_ufm/wb_adr_7_i_i_5[0] , \ram2e_ufm/wb_adr_7_i_i_4[0] , 
+         \ram2e_ufm/N_793 , \ram2e_ufm/wb_adr_RNO[1] , 
+         \ram2e_ufm/wb_adr_7_i_i[0] , \ram2e_ufm/CmdBitbangMXO2_RNINSM62 , 
+         \ram2e_ufm/wb_adr[0] , \ram2e_ufm/wb_adr[1] , \ram2e_ufm/N_268_i , 
+         \ram2e_ufm/N_80_i , \ram2e_ufm/wb_adr[2] , \ram2e_ufm/wb_adr[3] , 
+         \ram2e_ufm/N_290 , \ram2e_ufm/N_294 , \ram2e_ufm/wb_adr[4] , 
+         \ram2e_ufm/wb_adr[5] , \ram2e_ufm/N_267_i , \ram2e_ufm/N_284 , 
+         \ram2e_ufm/wb_adr[6] , \ram2e_ufm/wb_adr[7] , \ram2e_ufm/wb_ack , 
+         \ram2e_ufm/N_336 , \ram2e_ufm/N_687 , \ram2e_ufm/wb_cyc_stb_RNO , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] , 
+         \ram2e_ufm/wb_cyc_stb , \ram2e_ufm/wb_dati_7_0_0_0[1] , 
+         \ram2e_ufm/N_849 , \ram2e_ufm/N_611 , 
+         \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] , \ram2e_ufm/N_856 , 
+         \ram2e_ufm/wb_dati_7[1] , \ram2e_ufm/wb_dati_7[0] , 
+         \ram2e_ufm/wb_dati[0] , \ram2e_ufm/wb_dati[1] , 
+         \ram2e_ufm/wb_dati_7_0_0_0_0[3] , \ram2e_ufm/N_783 , 
+         \ram2e_ufm/wb_dati_7_0_0_o3_0[2] , \ram2e_ufm/N_760 , 
+         \ram2e_ufm/wb_dati_7[3] , \ram2e_ufm/wb_dati_7[2] , 
+         \ram2e_ufm/wb_dati[2] , \ram2e_ufm/wb_dati[3] , 
+         \ram2e_ufm/wb_dati_7_0_0_0[4] , \ram2e_ufm/N_763 , \ram2e_ufm/N_757 , 
+         \ram2e_ufm/wb_dati_7[5] , \ram2e_ufm/wb_dati_7[4] , 
+         \ram2e_ufm/wb_dati[4] , \ram2e_ufm/wb_dati[5] , 
+         \ram2e_ufm/wb_dati_7_0_0_0_0[7] , \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] , 
+         \ram2e_ufm/N_604 , \ram2e_ufm/N_602 , \ram2e_ufm/wb_dati_7_0_0_0[6] , 
+         \ram2e_ufm/wb_dati_7[7] , \ram2e_ufm/wb_dati_7[6] , 
+         \ram2e_ufm/wb_dati[6] , \ram2e_ufm/wb_dati[7] , \ram2e_ufm/wb_reqc_1 , 
+         \ram2e_ufm/wb_reqc_i , \ram2e_ufm/wb_req , \ram2e_ufm/wb_rst8 , 
+         \ram2e_ufm/wb_rst16_i , \ram2e_ufm/wb_rst , 
+         \ram2e_ufm/wb_we_7_iv_0_0_3_0_0 , \ram2e_ufm/N_799 , 
+         \ram2e_ufm/wb_we_7_iv_0_0_3_0_1 , \ram2e_ufm/N_208 , 
+         \ram2e_ufm/wb_we_RNO , \ram2e_ufm/wb_we_RNO_0 , \ram2e_ufm/wb_we , 
+         \ram2e_ufm/N_338 , \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 , \ram2e_ufm/N_817 , 
+         \ram2e_ufm/CKE_7_sm0 , \ram2e_ufm/N_720_tz , \ram2e_ufm/SUM0_i_0 , 
+         \ram2e_ufm/N_350 , \ram2e_ufm/SUM0_i_3 , \ram2e_ufm/SUM0_i_1 , 
+         \ram2e_ufm/N_187 , \ram2e_ufm/N_755 , \ram2e_ufm/N_735 , 
+         \ram2e_ufm/N_345 , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] , 
+         \ram2e_ufm/N_777 , \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] , 
+         \ram2e_ufm/N_250 , \ram2e_ufm/N_256 , \ram2e_ufm/wb_adr_7_i_i_3_1[0] , 
+         \ram2e_ufm/wb_adr_7_i_i_3[0] , \ram2e_ufm/N_254 , \ram2e_ufm/N_807 , 
+         \ram2e_ufm/N_876 , \ram2e_ufm/N_784 , \ram2e_ufm/N_560 , \BA_4[0] , 
+         \ram2e_ufm/N_873 , \ram2e_ufm/N_781 , \ram2e_ufm/N_184 , 
+         \ram2e_ufm/N_625 , \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] , 
+         \ram2e_ufm/N_811 , \ram2e_ufm/N_206 , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] , \ram2e_ufm/N_185 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S , \ram2e_ufm/N_637 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 , \ram2e_ufm/N_592 , 
+         \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] , 
+         \ram2e_ufm/wb_adr_7_i_i_1[0] , \ram2e_ufm/N_753 , \ram2e_ufm/N_634 , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] , 
+         \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_1[6] , \ram2e_ufm/N_890 , 
+         \ram2e_ufm/N_220 , \ram2e_ufm/N_196 , \ram2e_ufm/N_243 , \Ain_c[4] , 
+         \Ain_c[6] , \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] , 
+         \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] , \ram2e_ufm/N_565 , 
+         \ram2e_ufm/CKE_7s2_0_0_0 , \ram2e_ufm/wb_adr_7_5_41_a3_3_0 , 
+         \ram2e_ufm/N_204 , \ram2e_ufm/N_595 , \ram2e_ufm/nRWE_s_i_0_63_1 , 
+         \ram2e_ufm/N_792 , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] , 
+         \ram2e_ufm/N_553 , nEN80_c, \ram2e_ufm/N_241_i , \ram2e_ufm/N_814 , 
+         N_225_i, N_201_i, N_507_i, N_508, Vout3, \BA_4[1] , \Ain_c[0] , 
+         \Ain_c[7] , nDOE_c, LED_c, RDOE_i, PHI1_c, PHI1r, nVOE_c, N_263_i, 
+         N_667, N_648, N_662, N_666, N_663, N_665, N_664, \RD_in[0] , 
+         \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , 
+         \RD_in[2] , \RD_in[1] , DQMH_c, DQML_c, \RAout_c[11] , \RAout_c[10] , 
+         \RAout_c[9] , \RAout_c[8] , \RAout_c[7] , \RAout_c[6] , \RAout_c[5] , 
+         \RAout_c[4] , \RAout_c[3] , \RAout_c[2] , \RAout_c[1] , \RAout_c[0] , 
+         \BA_c[1] , \BA_c[0] , nRWEout_c, nCASout_c, nRASout_c, CKEout_c, 
          \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] , 
-         \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , \Dout_c[7] , \Dout_c[6] , 
-         \Dout_c[5] , \Dout_c[4] , \Dout_c[3] , \Dout_c[2] , \Dout_c[1] , 
-         \Dout_c[0] , VCCI;
+         \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , VCCI;
 
   SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), 
     .Q1(\FS[0] ), .FCO(\FS_cry[0] ));
@@ -127,426 +192,679 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), 
     .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), 
     .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
-  SLICE_9 SLICE_9( .C1(Ready), .B1(PHI1reg), .A1(PHI1_c), .B0(RWSel), 
-    .A0(CO0_1), .DI0(\CmdTout_3[0] ), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(\CmdTout_3[0] ), .Q0(CO0_1), .F1(S_1));
-  SLICE_10 SLICE_10( .D1(\CS[0] ), .C1(N_461), .B1(\S_RNII9DO1_0[1] ), 
-    .A1(\CS[1] ), .C0(\S_RNII9DO1_0[1] ), .B0(N_461), .A0(\CS[0] ), 
-    .DI1(N_511_i), .DI0(N_504_i), .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), 
-    .F0(N_504_i), .Q0(\CS[0] ), .F1(N_511_i), .Q1(\CS[1] ));
-  SLICE_11 SLICE_11( .C1(\S_RNII9DO1_0[1] ), .B1(N_461), .A1(\CS[0] ), 
-    .C0(N_637), .B0(\CS[2] ), .A0(\CS[1] ), .DI0(N_510_i), 
-    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_510_i), .Q0(\CS[2] ), 
-    .F1(N_637));
-  SLICE_12 SLICE_12( .C1(\Din_c[3] ), .B1(\Din_c[2] ), .A1(\Din_c[0] ), 
-    .D0(RWSel), .C0(N_643), .B0(CmdBitbangMXO2_4_u_0_0_a2_0_1), 
-    .A0(CmdBitbangMXO2), .DI0(CmdBitbangMXO2_4), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(CmdBitbangMXO2_4), .Q0(CmdBitbangMXO2), 
-    .F1(CmdBitbangMXO2_4_u_0_0_a2_0_1));
-  SLICE_13 SLICE_13( .C1(RWSel), .B1(\Din_c[7] ), .A1(\Din_c[5] ), .D0(RWSel), 
-    .C0(N_643), .B0(N_629), .A0(CmdExecMXO2), .DI0(CmdExecMXO2_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdExecMXO2_4), .Q0(CmdExecMXO2), 
-    .F1(N_466));
-  SLICE_14 SLICE_14( .D1(N_478), .C1(\Din_c[4] ), .B1(\Din_c[1] ), 
-    .A1(\Din_c[0] ), .D0(RWSel), .C0(N_476), .B0(CmdLEDGet_4_u_0_0_a2_0_2), 
-    .A0(CmdLEDGet), .DI0(CmdLEDGet_4), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(CmdLEDGet_4), .Q0(CmdLEDGet), .F1(CmdLEDGet_4_u_0_0_a2_0_2));
-  SLICE_15 SLICE_15( .D1(N_626), .C1(N_476), .B1(\Din_c[4] ), .A1(\Din_c[1] ), 
-    .C0(RWSel), .B0(N_605), .A0(CmdLEDSet), .DI0(CmdLEDSet_4), .CE(N_576_i), 
-    .CLK(C14M_c), .F0(CmdLEDSet_4), .Q0(CmdLEDSet), .F1(N_605));
-  SLICE_16 SLICE_16( .C1(\Din_c[1] ), .B1(\Din_c[4] ), .A1(N_476), .D0(RWSel), 
-    .C0(N_643), .B0(N_626), .A0(CmdRWMaskSet), .DI0(CmdRWMaskSet_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdRWMaskSet_4), .Q0(CmdRWMaskSet), 
-    .F1(N_643));
-  SLICE_17 SLICE_17( .D1(N_626), .C1(N_476), .B1(\Din_c[4] ), .A1(\Din_c[1] ), 
-    .C0(RWSel), .B0(N_401), .A0(CmdSetRWBankFFLED), .DI0(CmdSetRWBankFFLED_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdSetRWBankFFLED_4), 
-    .Q0(CmdSetRWBankFFLED), .F1(N_401));
-  SLICE_18 SLICE_18( .C1(N_474), .B1(\CS[2] ), .A1(\CS[1] ), .D0(RWSel), 
-    .C0(N_476), .B0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), 
-    .A0(CmdSetRWBankFFMXO2), .DI0(CmdSetRWBankFFMXO2_4), .CE(N_576_i), 
-    .CLK(C14M_c), .F0(CmdSetRWBankFFMXO2_4), .Q0(CmdSetRWBankFFMXO2), 
-    .F1(N_476));
-  SLICE_19 SLICE_19( .D1(RWSel), .C1(CO0_1), .B1(\CmdTout[1] ), 
-    .A1(\CmdTout[2] ), .C0(RWSel), .B0(\CmdTout[1] ), .A0(CO0_1), 
-    .DI1(N_556_i), .DI0(N_555_i), .CE(N_576_i), .CLK(C14M_c), .F0(N_555_i), 
-    .Q0(\CmdTout[1] ), .F1(N_556_i), .Q1(\CmdTout[2] ));
-  SLICE_20 SLICE_20( .D1(\S[0] ), .C1(\S[1] ), .B1(\S[2] ), .A1(\S[3] ), 
-    .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), .DI0(N_6_i), 
-    .CLK(C14M_c), .F0(N_6_i), .Q0(DOEEN), .F1(N_576_i));
-  SLICE_21 SLICE_21( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[1] ), 
-    .C0(\wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), .DI0(LEDEN_RNO), 
-    .CE(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .CLK(C14M_c), .F0(LEDEN_RNO), 
-    .Q0(LEDEN), .F1(N_558_i));
-  SLICE_22 SLICE_22( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[3] ), .C0(\S[3] ), 
-    .B0(\S[0] ), .A0(\Ain_c[0] ), .DI1(N_552_i), .DI0(N_127_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c), .F0(N_127_i), .Q0(\RA_c[0] ), 
-    .F1(N_552_i), .Q1(\RA_c[3] ));
-  SLICE_23 SLICE_23( .C1(\RWMask[1] ), .B1(N_591), .A1(\Din_c[1] ), 
-    .C0(\RWMask[0] ), .B0(N_591), .A0(\Din_c[0] ), .DI1(\RWBank_5[1] ), 
-    .DI0(\RWBank_5[0] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[0] ), 
-    .Q0(\RWBank[0] ), .F1(\RWBank_5[1] ), .Q1(\RWBank[1] ));
-  SLICE_24 SLICE_24( .C1(\RWMask[3] ), .B1(N_591), .A1(\Din_c[3] ), 
-    .C0(\RWMask[2] ), .B0(N_591), .A0(\Din_c[2] ), .DI1(\RWBank_5[3] ), 
-    .DI0(\RWBank_5[2] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[2] ), 
-    .Q0(\RWBank[2] ), .F1(\RWBank_5[3] ), .Q1(\RWBank[3] ));
-  SLICE_25 SLICE_25( .C1(\RWMask[5] ), .B1(N_591), .A1(\Din_c[5] ), 
-    .C0(\RWMask[4] ), .B0(N_591), .A0(\Din_c[4] ), .DI1(\RWBank_5[5] ), 
-    .DI0(\RWBank_5[4] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[4] ), 
-    .Q0(\RWBank[4] ), .F1(\RWBank_5[5] ), .Q1(\RWBank[5] ));
-  SLICE_26 SLICE_26( .C1(\RWMask[7] ), .B1(N_591), .A1(\Din_c[7] ), 
-    .C0(\RWMask[6] ), .B0(N_591), .A0(\Din_c[6] ), .DI1(\RWBank_5[7] ), 
-    .DI0(\RWBank_5[6] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[6] ), 
-    .Q0(\RWBank[6] ), .F1(\RWBank_5[7] ), .Q1(\RWBank[7] ));
-  SLICE_27 SLICE_27( .C1(\wb_dato[1] ), .B1(\S[3] ), .A1(\Din_c[1] ), 
-    .C0(\wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), .DI1(N_291_i), 
-    .DI0(N_292_i), .CE(N_88), .CLK(C14M_c), .F0(N_292_i), .Q0(\RWMask[0] ), 
-    .F1(N_291_i), .Q1(\RWMask[1] ));
-  SLICE_28 SLICE_28( .C1(\wb_dato[3] ), .B1(\S[3] ), .A1(\Din_c[3] ), 
-    .C0(\wb_dato[2] ), .B0(\S[3] ), .A0(\Din_c[2] ), .DI1(N_289_i), 
-    .DI0(N_290_i), .CE(N_88), .CLK(C14M_c), .F0(N_290_i), .Q0(\RWMask[2] ), 
-    .F1(N_289_i), .Q1(\RWMask[3] ));
-  SLICE_29 SLICE_29( .C1(\wb_dato[5] ), .B1(\S[3] ), .A1(\Din_c[5] ), 
-    .C0(\wb_dato[4] ), .B0(\S[3] ), .A0(\Din_c[4] ), .DI1(N_287_i), 
-    .DI0(N_288_i), .CE(N_88), .CLK(C14M_c), .F0(N_288_i), .Q0(\RWMask[4] ), 
-    .F1(N_287_i), .Q1(\RWMask[5] ));
-  SLICE_30 SLICE_30( .C1(\wb_dato[7] ), .B1(\S[3] ), .A1(\Din_c[7] ), 
-    .C0(\wb_dato[6] ), .B0(\S[3] ), .A0(\Din_c[6] ), .DI1(N_285), 
-    .DI0(N_286_i), .CE(N_88), .CLK(C14M_c), .F0(N_286_i), .Q0(\RWMask[6] ), 
-    .F1(N_285), .Q1(\RWMask[7] ));
-  SLICE_31 SLICE_31( .C1(nWE_c), .B1(nEN80_c), .A1(DOEEN), .D0(nWE_c), 
-    .C0(nC07X_c), .B0(\RA_c[3] ), .A0(\RA_c[0] ), .DI0(RWSel_2), .CE(nCS61), 
-    .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(nDOE_c));
-  SLICE_32 SLICE_32( .D1(Ready_0_sqmuxa_0_a2_6_a2_4), .C1(N_489), .B1(\FS[7] ), 
-    .A1(\FS[6] ), .B0(Ready), .A0(Ready_0_sqmuxa), .DI0(N_876_0), .CLK(C14M_c), 
-    .F0(N_876_0), .Q0(Ready), .F1(Ready_0_sqmuxa));
-  SLICE_33 SLICE_33( .D1(wb_reqc_1), .C1(N_575), .B1(N_572), .A1(S_1), 
-    .D0(\S_s_0_1[0] ), .C0(\S[1] ), .B0(\S[0] ), .A0(S_1), .DI1(N_133_i), 
-    .DI0(\S_s_0[0] ), .CLK(C14M_c), .F0(\S_s_0[0] ), .Q0(\S[0] ), .F1(N_133_i), 
-    .Q1(\S[1] ));
-  SLICE_34 SLICE_34( .D1(\S[3] ), .C1(\S[2] ), .B1(N_575), .A1(S_1), 
-    .D0(\S[3] ), .C0(\S[2] ), .B0(N_575), .A0(S_1), .DI1(N_129_i), 
-    .DI0(N_131_i), .CLK(C14M_c), .F0(N_131_i), .Q0(\S[2] ), .F1(N_129_i), 
-    .Q1(\S[3] ));
-  SLICE_35 SLICE_35( .D1(wb_adr_7_5_214_0_1), .C1(\S[2] ), .B1(N_388), 
-    .A1(\Din_c[1] ), .D0(\wb_adr_7_0_4[0] ), .C0(N_642), .B0(N_376), 
-    .A0(\FS[13] ), .DI1(\wb_adr_RNO[1] ), .DI0(\wb_adr_7[0] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_adr_7[0] ), 
-    .Q0(\wb_adr[0] ), .F1(\wb_adr_RNO[1] ), .Q1(\wb_adr[1] ));
-  SLICE_36 SLICE_36( .B1(\S[2] ), .A1(\Din_c[3] ), .B0(\S[2] ), 
-    .A0(\Din_c[2] ), .DI1(N_41_i), .DI0(N_43_i), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_43_i), 
-    .Q0(\wb_adr[2] ), .F1(N_41_i), .Q1(\wb_adr[3] ));
-  SLICE_37 SLICE_37( .C1(\S[2] ), .B1(\FS[14] ), .A1(\Din_c[5] ), .C0(\S[2] ), 
-    .B0(\FS[14] ), .A0(\Din_c[4] ), .DI1(N_295), .DI0(N_294), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_294), 
-    .Q0(\wb_adr[4] ), .F1(N_295), .Q1(\wb_adr[5] ));
-  SLICE_38 SLICE_38( .B1(\S[2] ), .A1(\Din_c[7] ), .C0(\S[2] ), .B0(\FS[14] ), 
-    .A0(\Din_c[6] ), .DI1(N_39_i), .DI0(N_296), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_296), 
-    .Q0(\wb_adr[6] ), .F1(N_39_i), .Q1(\wb_adr[7] ));
-  SLICE_39 SLICE_39( .D1(\FS[14] ), .C1(wb_ack), .B1(\FS[0] ), .A1(N_300), 
-    .C0(\S[3] ), .B0(N_395), .A0(CmdExecMXO2), .DI0(wb_cyc_stb_RNO), 
-    .CE(N_104), .CLK(C14M_c), .F0(wb_cyc_stb_RNO), .Q0(wb_cyc_stb), .F1(N_395));
-  SLICE_40 SLICE_40( .D1(\wb_dati_7_0_0[1] ), .C1(N_627), .B1(N_621), 
-    .A1(N_336), .D0(\wb_dati_7_0_a2_1[0] ), .C0(\wb_adr[0] ), .B0(\S[2] ), 
-    .A0(N_484), .DI1(\wb_dati_7[1] ), .DI0(\wb_dati_7[0] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[0] ), 
-    .Q0(\wb_dati[0] ), .F1(\wb_dati_7[1] ), .Q1(\wb_dati[1] ));
-  SLICE_41 SLICE_41( .C1(\wb_dati_7_0_2[3] ), .B1(\wb_dati_7_0_0[3] ), 
-    .A1(N_336), .D0(\wb_dati_7_0_o2_0[2] ), .C0(\wb_adr[2] ), .B0(\S[2] ), 
-    .A0(N_345), .DI1(\wb_dati_7[3] ), .DI0(\wb_dati_7[2] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[2] ), 
-    .Q0(\wb_dati[2] ), .F1(\wb_dati_7[3] ), .Q1(\wb_dati[3] ));
-  SLICE_42 SLICE_42( .D1(\wb_dati_7_0_o2_0[2] ), .C1(\wb_adr[5] ), .B1(\S[2] ), 
-    .A1(N_345), .D0(\wb_dati_7_0_0[4] ), .C0(N_349), .B0(N_346), .A0(N_345), 
-    .DI1(\wb_dati_7[5] ), .DI0(\wb_dati_7[4] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[4] ), 
-    .Q0(\wb_dati[4] ), .F1(\wb_dati_7[5] ), .Q1(\wb_dati[5] ));
-  SLICE_43 SLICE_43( .D1(\wb_dati_7_0_0[7] ), .C1(\wb_dati_7_0_RNO[7] ), 
-    .B1(N_424), .A1(N_422), .C0(\wb_dati_7_0_1[6] ), .B0(N_627), .A0(N_621), 
-    .DI1(\wb_dati_7[7] ), .DI0(\wb_dati_7[6] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[6] ), 
-    .Q0(\wb_dati[6] ), .F1(\wb_dati_7[7] ), .Q1(\wb_dati[7] ));
-  SLICE_44 SLICE_44( .C1(\FS[13] ), .B1(\FS[12] ), .A1(\FS[11] ), 
-    .D0(wb_reqc_1), .C0(\S[3] ), .B0(N_397), .A0(\FS[14] ), .DI0(wb_reqc_i), 
-    .CE(wb_adr_0_sqmuxa_i), .LSR(\S[2] ), .CLK(C14M_c), .F0(wb_reqc_i), 
-    .Q0(wb_req), .F1(N_397));
-  SLICE_45 SLICE_45( .B1(wb_ack), .A1(\FS[14] ), .B0(\FS[15] ), .A0(\FS[14] ), 
-    .DI0(wb_rst8), .LSR(\S_RNII9DO1[1] ), .CLK(C14M_c), .F0(wb_rst8), 
-    .Q0(wb_rst), .F1(N_586));
-  SLICE_46 SLICE_46( .D1(\FS[8] ), .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[12] ), 
-    .D0(wb_we_7_iv_0_0_0_1), .C0(N_584), .B0(N_475), .A0(\FS[13] ), 
-    .DI0(wb_we_RNO), .CE(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), .CLK(C14M_c), 
-    .F0(wb_we_RNO), .Q0(wb_we), .F1(N_584));
-  SLICE_47 SLICE_47( .D1(N_255), .C1(\S[0] ), .B1(\S_RNII9DO1[1] ), 
-    .A1(\RWBank[6] ), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), 
-    .F0(\S_RNII9DO1[1] ), .F1(N_358_i));
-  SLICE_48 SLICE_48( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[1] ), .A1(\S[0] ), 
-    .D0(N_635), .C0(\S[0] ), .B0(N_254), .A0(Vout3), .F0(nCAS_s_i_tz_0), 
-    .F1(Vout3));
-  SLICE_49 SLICE_49( .D1(un1_CS_0_sqmuxa_0_0_a2_1_4), .C1(RWSel), 
-    .B1(\Din_c[6] ), .A1(\CS[0] ), .D0(RWSel), .C0(N_327), .B0(\CS[2] ), 
-    .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_0), .F1(N_327));
-  SLICE_50 SLICE_50( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[9] ), .A1(\FS[8] ), 
-    .D0(\wb_dati_7_0_a2_0_1[7] ), .C0(N_621), .B0(N_579), .A0(\FS[9] ), 
-    .F0(\wb_dati_7_0_RNO[7] ), .F1(\wb_dati_7_0_a2_0_1[7] ));
-  SLICE_51 SLICE_51( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), 
-    .A1(CKE_6_iv_i_a2_0), .D0(\S[3] ), .C0(N_489), .B0(\FS[15] ), 
-    .A0(CKE_6_iv_i_0_1), .F0(CKE_6_iv_i_0), .F1(CKE_6_iv_i_0_1));
-  SLICE_52 SLICE_52( .D1(wb_req), .C1(N_449), .B1(N_300), .A1(\FS[0] ), 
-    .D0(N_586), .C0(N_449), .B0(N_365), .A0(N_364), .F0(N_104), .F1(N_365));
-  SLICE_53 SLICE_53( .D1(\S[3] ), .C1(\S[2] ), .B1(RWSel), .A1(\FS[15] ), 
-    .D0(wb_reqc_1), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .B0(\S[2] ), 
-    .A0(CmdExecMXO2), .F0(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), 
-    .F1(\un1_wb_adr_0_sqmuxa_2_1[0] ));
-  SLICE_54 SLICE_54( .D1(\Din_c[2] ), .C1(\Din_c[1] ), .B1(\Din_c[0] ), 
-    .A1(\CS[1] ), .D0(N_623), .C0(N_616), .B0(\Din_c[1] ), .A0(\CS[2] ), 
-    .F0(N_279), .F1(N_623));
-  SLICE_55 SLICE_55( .D1(\FS[4] ), .C1(N_633), .B1(\FS[5] ), .A1(N_264), 
-    .D0(\FS[1] ), .C0(\FS[2] ), .B0(\FS[3] ), .A0(\FS[5] ), .F0(N_633), 
-    .F1(N_570));
-  SLICE_56 SLICE_56( .C1(\FS[15] ), .B1(\S_RNII9DO1[1] ), .A1(\FS[14] ), 
-    .C0(\FS[13] ), .B0(N_452), .A0(\FS[12] ), .F0(N_621), .F1(N_452));
-  SLICE_57 SLICE_57( .D1(\S_RNII9DO1_0[1] ), .C1(RWSel), .B1(CmdExecMXO2), 
-    .A1(wb_ack), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[3] ), .A0(\S[2] ), 
-    .F0(\S_RNII9DO1_0[1] ), .F1(N_364));
-  SLICE_58 SLICE_58( .D1(\wb_dati_7_0_a2_2_1[3] ), .C1(N_644), .B1(N_455), 
-    .A1(\FS[12] ), .D0(\FS[10] ), .C0(\FS[11] ), .B0(\FS[8] ), .A0(\FS[9] ), 
-    .F0(\wb_dati_7_0_a2_2_1[3] ), .F1(\wb_dati_7_0_2[3] ));
-  SLICE_59 SLICE_59( .D1(nCS61), .C1(\RWBank[6] ), .B1(\S_RNII9DO1[1] ), 
-    .A1(DQML_s_i_a2_0), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), 
-    .F0(DQML_s_i_a2_0), .F1(N_28_i));
-  SLICE_60 SLICE_60( .D1(wb_adr_7_5_214_a2_2_0), .C1(N_577), .B1(N_569), 
-    .A1(N_475), .C0(\FS[10] ), .B0(\FS[12] ), .A0(\FS[13] ), 
-    .F0(wb_adr_7_5_214_a2_2_0), .F1(wb_adr_7_5_214_0_1));
-  SLICE_61 SLICE_61( .C1(N_634), .B1(\FS[13] ), .A1(\FS[12] ), .D0(\FS[10] ), 
-    .C0(\FS[11] ), .B0(\FS[8] ), .A0(\FS[9] ), .F0(N_634), 
-    .F1(\wb_dati_7_0_a2_2_0[1] ));
-  SLICE_62 SLICE_62( .D1(N_475), .C1(N_265_i), .B1(\FS[12] ), .A1(\FS[11] ), 
-    .C0(\FS[8] ), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_265_i), .F1(N_388));
-  SLICE_63 SLICE_63( .D1(N_264), .C1(N_254), .B1(\FS[7] ), .A1(\FS[6] ), 
-    .C0(\FS[1] ), .B0(\FS[2] ), .A0(\FS[3] ), .F0(N_264), .F1(N_300));
-  SLICE_64 SLICE_64( .C1(\FS[8] ), .B1(\FS[9] ), .A1(\FS[11] ), .D0(\FS[10] ), 
-    .C0(\FS[12] ), .B0(N_577), .A0(wb_ack), 
-    .F0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .F1(N_577));
-  SLICE_65 SLICE_65( .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[10] ), 
-    .C0(\FS[12] ), .B0(\FS[13] ), .A0(\wb_dati_7_0_a2_0[6] ), 
-    .F0(\wb_dati_7_0_a2_4_0[7] ), .F1(\wb_dati_7_0_a2_0[6] ));
-  SLICE_66 SLICE_66( .B1(\S[2] ), .A1(\FS[14] ), .D0(\FS[12] ), .C0(\FS[13] ), 
-    .B0(\FS[11] ), .A0(N_475), .F0(N_393), .F1(N_475));
-  SLICE_67 SLICE_67( .B1(\S[1] ), .A1(\S[0] ), .D0(wb_reqc_1), .C0(\S[3] ), 
-    .B0(\S[2] ), .A0(RWSel), .F0(LEDEN13), .F1(wb_reqc_1));
-  SLICE_68 SLICE_68( .D1(\wb_adr[3] ), .C1(\S[2] ), .B1(N_627), .A1(N_455), 
-    .D0(\FS[11] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[10] ), .F0(N_627), 
-    .F1(\wb_dati_7_0_0[3] ));
-  SLICE_69 SLICE_69( .D1(nCAS_0_sqmuxa), .C1(\RWBank[2] ), .B1(N_639), 
-    .A1(N_255), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), .F0(N_639), 
-    .F1(\RA_42[10] ));
-  SLICE_70 SLICE_70( .D1(N_644), .C1(N_627), .B1(N_455), .A1(\FS[12] ), 
-    .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), .F0(N_644), 
-    .F1(N_345));
-  SLICE_71 SLICE_71( .D1(nCS61), .C1(N_640), .B1(N_633), .A1(\FS[4] ), 
-    .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), .F0(nCS61), 
-    .F1(un1_nCS61_1_i));
-  SLICE_72 SLICE_72( .D1(Ready_0_sqmuxa_0_a2_6_a2_2), .C1(N_449), .B1(\FS[5] ), 
-    .A1(\FS[3] ), .D0(\S[2] ), .C0(\S[3] ), .B0(wb_reqc_1), .A0(\FS[15] ), 
-    .F0(N_449), .F1(Ready_0_sqmuxa_0_a2_6_a2_4));
-  SLICE_73 SLICE_73( .D1(N_562), .C1(N_455), .B1(\FS[12] ), .A1(\FS[11] ), 
-    .D0(\FS[14] ), .C0(\S_RNII9DO1[1] ), .B0(\FS[15] ), .A0(\FS[13] ), 
-    .F0(N_455), .F1(N_377));
-  SLICE_74 SLICE_74( .C1(N_484), .B1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[10] ), 
-    .C0(\FS[12] ), .B0(\FS[13] ), .A0(N_642), .F0(N_346), .F1(N_642));
-  SLICE_75 SLICE_75( .D1(N_489), .C1(\FS[7] ), .B1(\FS[6] ), .A1(\FS[0] ), 
-    .C0(\FS[15] ), .B0(\S_RNII9DO1[1] ), .A0(N_628), .F0(N_640), .F1(N_628));
-  SLICE_76 SLICE_76( .B1(\FS[5] ), .A1(\FS[4] ), .D0(N_449), .C0(N_628), 
-    .B0(N_254), .A0(N_264), .F0(nCAS_0_sqmuxa), .F1(N_254));
-  SLICE_77 SLICE_77( .C1(N_466), .B1(\Din_c[6] ), .A1(\CS[0] ), 
-    .D0(un1_CS_0_sqmuxa_0_0_a2_3_2), .C0(un1_CS_0_sqmuxa_0_0_3), 
-    .B0(un1_CS_0_sqmuxa_0_0_2), .A0(N_474), .F0(un1_CS_0_sqmuxa_i), .F1(N_474));
-  SLICE_78 SLICE_78( .B1(N_633), .A1(\FS[4] ), .D0(nCAS_s_i_tz_0), .C0(N_640), 
-    .B0(N_567), .A0(nCAS_0_sqmuxa), .F0(N_561_i), .F1(N_567));
-  SLICE_79 SLICE_79( .D1(nEN80_c), .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), 
-    .B0(nCS_6_u_i_0), .A0(N_559_1), .F0(N_559_i), .F1(nCS_6_u_i_0));
-  SLICE_80 SLICE_80( .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), .C0(\S[0] ), 
-    .B0(N_635), .A0(N_559_1), .F0(nRAS_2_iv_i), .F1(N_635));
-  SLICE_81 SLICE_81( .D1(\Din_c[6] ), .C1(\Din_c[4] ), .B1(\Din_c[3] ), 
-    .A1(\CS[0] ), .D0(un1_CS_0_sqmuxa_0_0_a2_1), .C0(un1_CS_0_sqmuxa_0_0_0), 
-    .B0(N_466), .A0(N_279), .F0(un1_CS_0_sqmuxa_0_0_2), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_1));
-  SLICE_82 SLICE_82( .D1(RWSel), .C1(\CmdTout[2] ), .B1(\CmdTout[1] ), 
-    .A1(CO0_1), .D0(\S_RNII9DO1_0[1] ), .C0(N_461), .B0(N_330), .A0(N_328), 
-    .F0(un1_CS_0_sqmuxa_0_0_3), .F1(N_461));
-  SLICE_83 SLICE_83( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[0] ), .A1(\FS[15] ), 
-    .D0(nCS_6_u_i_a2_1), .C0(N_628), .B0(N_570), .A0(N_429), .F0(N_559_1), 
-    .F1(nCS_6_u_i_a2_1));
-  SLICE_84 SLICE_84( .D1(\wb_dati_7_0_a2_0[6] ), .C1(N_455), .B1(\FS[12] ), 
-    .A1(\FS[10] ), .D0(\wb_adr[6] ), .C0(\S[2] ), .B0(N_351), .A0(N_346), 
-    .F0(\wb_dati_7_0_1[6] ), .F1(N_351));
-  SLICE_85 SLICE_85( .D1(\wb_adr_7_0_a2_5_0[0] ), .C1(N_579), .B1(N_452), 
-    .A1(\FS[8] ), .D0(\wb_adr_7_0_1[0] ), .C0(\wb_adr_7_0_0[0] ), .B0(N_378), 
-    .A0(N_377), .F0(\wb_adr_7_0_4[0] ), .F1(\wb_adr_7_0_1[0] ));
-  SLICE_86 SLICE_86( .D1(\FS[14] ), .C1(\S_RNII9DO1[1] ), .B1(\FS[15] ), 
-    .A1(\FS[8] ), .D0(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ), .C0(N_484), 
-    .B0(LEDEN13), .A0(CmdLEDSet), .F0(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), 
-    .F1(N_484));
-  SLICE_87 SLICE_87( .D1(un1_CS_0_sqmuxa_0_0_a2_4_2), .C1(RWSel), 
-    .B1(\Din_c[6] ), .A1(\CS[0] ), .C0(un1_CS_0_sqmuxa_0_0_a2_4_4), 
-    .B0(\CS[2] ), .A0(\CS[1] ), .F0(N_330), .F1(un1_CS_0_sqmuxa_0_0_a2_4_4));
-  SLICE_88 SLICE_88( .B1(\FS[13] ), .A1(\FS[12] ), .D0(N_634), .C0(N_569), 
-    .B0(N_452), .A0(N_336), .F0(\wb_dati_7_0_o2_0[2] ), .F1(N_569));
-  SLICE_89 SLICE_89( .B1(\FS[11] ), .A1(\FS[10] ), .D0(N_579), .C0(N_455), 
-    .B0(\FS[9] ), .A0(\FS[8] ), .F0(N_378), .F1(N_579));
-  SLICE_90 SLICE_90( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), 
-    .C0(N_565), .B0(N_484), .A0(\FS[12] ), .F0(N_336), .F1(N_565));
-  SLICE_91 SLICE_91( .D1(un1_CS_0_sqmuxa_0_0_a2_2_2), .C1(\Din_c[6] ), 
-    .B1(\CS[2] ), .A1(\CS[0] ), .C0(un1_CS_0_sqmuxa_0_0_a2_2_4), .B0(RWSel), 
-    .A0(\Din_c[7] ), .F0(N_328), .F1(un1_CS_0_sqmuxa_0_0_a2_2_4));
-  SLICE_92 SLICE_92( .D1(N_562), .C1(\FS[13] ), .B1(\FS[12] ), .A1(\FS[11] ), 
-    .D0(\wb_adr_7_0_a2_0[0] ), .C0(\S[2] ), .B0(N_452), .A0(\Din_c[0] ), 
-    .F0(\wb_adr_7_0_0[0] ), .F1(\wb_adr_7_0_a2_0[0] ));
-  SLICE_93 SLICE_93( .D1(N_616), .C1(\Din_c[5] ), .B1(\Din_c[4] ), 
-    .A1(\Din_c[1] ), .D0(un1_CS_0_sqmuxa_0_0_a2_1_2), .C0(\Din_c[7] ), 
-    .B0(\Din_c[3] ), .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_a2_1_4), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_1_2));
-  SLICE_94 SLICE_94( .D1(\Din_c[3] ), .C1(\Din_c[2] ), .B1(\Din_c[0] ), 
-    .A1(\Din_c[1] ), .D0(un1_CS_0_sqmuxa_0_0_a2_3_0), .C0(\Din_c[4] ), 
-    .B0(\CS[2] ), .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_a2_3_2), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_3_0));
-  SLICE_95 SLICE_95( .D1(N_577), .C1(N_475), .B1(\FS[12] ), .A1(\FS[10] ), 
-    .D0(\S[2] ), .C0(N_394), .B0(N_393), .A0(\Din_c[0] ), 
-    .F0(wb_we_7_iv_0_0_0_1), .F1(N_394));
-  SLICE_96 SLICE_96( .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), .D0(\S[0] ), 
-    .C0(\RWBank[7] ), .B0(\RWBank[0] ), .A0(N_255), .F0(N_49_i), .F1(N_255));
-  SLICE_97 SLICE_97( .B1(\FS[12] ), .A1(\FS[10] ), .D0(N_577), .C0(N_456), 
-    .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_489), .F1(N_456));
-  SLICE_98 SLICE_98( .C1(\Din_c[2] ), .B1(\Din_c[3] ), .A1(\Din_c[0] ), 
-    .D0(N_626), .C0(N_477), .B0(\Din_c[7] ), .A0(\Din_c[5] ), 
-    .F0(un1_CS_0_sqmuxa_0_0_a2_4_2), .F1(N_626));
-  SLICE_99 SLICE_99( .B1(\Din_c[3] ), .A1(\Din_c[2] ), .D0(N_478), .C0(N_477), 
-    .B0(\Din_c[5] ), .A0(\Din_c[0] ), .F0(un1_CS_0_sqmuxa_0_0_a2_2_2), 
-    .F1(N_478));
-  SLICE_100 SLICE_100( .C1(\Din_c[0] ), .B1(\Din_c[2] ), .A1(\Din_c[3] ), 
-    .C0(N_629), .B0(\Din_c[4] ), .A0(\Din_c[1] ), 
-    .F0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), .F1(N_629));
-  SLICE_101 SLICE_101( .D1(\S[2] ), .C1(\S[3] ), .B1(\S[1] ), .A1(\S[0] ), 
-    .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), .A0(\S[0] ), .F0(\S_RNII9DO1_1[1] ), 
-    .F1(N_566_i));
-  SLICE_102 SLICE_102( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[1] ), .A1(\S[0] ), 
-    .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\RWBank[4] ), .F0(\BA_4[0] ), 
-    .F1(\S_s_0_1[0] ));
-  SLICE_103 SLICE_103( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), 
-    .A1(\RWBank[3] ), .D0(\S[2] ), .C0(\S[3] ), .B0(wb_reqc_1), .A0(\FS[15] ), 
-    .F0(wb_adr_0_sqmuxa_i), .F1(\RA_42[11] ));
-  SLICE_104 SLICE_104( .D1(N_621), .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[8] ), 
-    .D0(N_621), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[9] ), .F0(N_376), 
-    .F1(N_349));
-  SLICE_105 SLICE_105( .D1(wb_ack), .C1(N_579), .B1(N_569), .A1(\FS[9] ), 
-    .D0(N_579), .C0(N_569), .B0(N_484), .A0(\FS[9] ), .F0(N_424), 
-    .F1(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ));
-  SLICE_106 SLICE_106( .B1(\S[1] ), .A1(\S[0] ), .C0(\S[0] ), .B0(\S[1] ), 
-    .A0(nEN80_c), .F0(CKE_6_iv_i_a2_0), .F1(N_575));
-  SLICE_107 SLICE_107( .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), 
-    .B0(\S[3] ), .A0(\RWBank[5] ), .F0(\BA_4[1] ), .F1(N_572));
-  SLICE_108 SLICE_108( .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), .D0(N_642), 
-    .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ), .F0(N_422), 
-    .F1(\wb_adr_7_0_a2_5_0[0] ));
-  SLICE_109 SLICE_109( .D1(\wb_dati_7_0_a2_4_0[7] ), .C1(\wb_adr[7] ), 
-    .B1(\S[2] ), .A1(N_452), .D0(\wb_dati_7_0_a2_2_0[1] ), .C0(\wb_adr[1] ), 
-    .B0(\S[2] ), .A0(N_452), .F0(\wb_dati_7_0_0[1] ), .F1(\wb_dati_7_0_0[7] ));
-  SLICE_110 SLICE_110( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), 
-    .A1(\RWBank[1] ), .D0(wb_reqc_1), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), 
-    .B0(\S[2] ), .A0(CmdBitbangMXO2), .F0(\un1_wb_adr_0_sqmuxa_2_i[0] ), 
-    .F1(N_59_i));
-  SLICE_111 SLICE_111( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[5] ), .C0(\S[3] ), 
-    .B0(\S[0] ), .A0(\Ain_c[4] ), .F0(N_551_i), .F1(\RA_42_3_0[5] ));
-  SLICE_112 SLICE_112( .D1(\S[3] ), .C1(\S[1] ), .B1(\S[0] ), .A1(N_254), 
-    .C0(\S[3] ), .B0(\S[0] ), .A0(\Ain_c[6] ), .F0(N_550_i), .F1(N_429));
-  SLICE_113 SLICE_113( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[2] ), .C0(\S[3] ), 
-    .B0(\S[0] ), .A0(\Ain_c[7] ), .F0(N_549_i), .F1(N_553_i));
-  SLICE_114 SLICE_114( .D1(\wb_adr[4] ), .C1(\S[2] ), .B1(N_634), .A1(N_455), 
-    .D0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .C0(N_455), .B0(LEDEN13), 
-    .A0(CmdRWMaskSet), .F0(N_88), .F1(\wb_dati_7_0_0[4] ));
-  SLICE_115 SLICE_115( .B1(nWE80_c), .A1(nEN80_c), .D0(nWE80_c), .C0(\S[0] ), 
-    .B0(nCAS_0_sqmuxa), .A0(un1_nCS61_1_i), .F0(nRWE_r_0), .F1(RDOE_i));
-  SLICE_116 SLICE_116( .B1(\FS[9] ), .A1(\FS[8] ), .D0(N_456), .C0(\FS[13] ), 
-    .B0(\FS[11] ), .A0(\FS[9] ), .F0(\wb_dati_7_0_a2_1[0] ), .F1(N_562));
-  SLICE_117 SLICE_117( .D1(LEDEN), .C1(CmdSetRWBankFFMXO2), 
-    .B1(CmdSetRWBankFFLED), .A1(CmdLEDGet), .B0(nEN80_c), .A0(LEDEN), 
-    .F0(LED_c), .F1(N_591));
-  SLICE_118 SLICE_118( .B1(\Din_c[4] ), .A1(\Din_c[1] ), .B0(\Din_c[2] ), 
-    .A0(\Din_c[0] ), .F0(N_616), .F1(N_477));
-  SLICE_119 SLICE_119( .D0(\FS[4] ), .C0(\FS[2] ), .B0(\FS[1] ), .A0(\FS[0] ), 
-    .F0(Ready_0_sqmuxa_0_a2_6_a2_2));
-  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(\Din_c[0] ), 
+  SLICE_9 SLICE_9( .D1(N_551), .C1(\S[1] ), .B1(\S[0] ), .A1(\FS[15] ), 
+    .D0(N_551), .C0(\S[1] ), .B0(\S[0] ), .A0(\ram2e_ufm/CKE_7 ), 
+    .DI0(CKE_7_RNIS77M1), .CLK(C14M_c), .F0(CKE_7_RNIS77M1), .Q0(CKE), 
+    .F1(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ));
+  SLICE_10 SLICE_10( .B0(RWSel), .A0(CO0_0), .DI0(\CmdTout_3[0] ), 
+    .CE(N_185_i), .CLK(C14M_c), .F0(\CmdTout_3[0] ), .Q0(CO0_0), .F1(GND));
+  SLICE_11 SLICE_11( .B1(\RC[2] ), .A1(CO0_1), .C0(\RC[2] ), .B0(\RC[1] ), 
+    .A0(CO0_1), .DI0(N_360_i), .CE(RC12), .CLK(C14M_c), .F0(N_360_i), 
+    .Q0(CO0_1), .F1(\ram2e_ufm/N_821 ));
+  SLICE_12 SLICE_12( .D1(\ram2e_ufm/SUM1_0_0 ), .C1(\ram2e_ufm/SUM0_i_a3_4_0 ), 
+    .B1(\ram2e_ufm/N_886 ), .A1(\ram2e_ufm/N_215 ), .D0(\ram2e_ufm/SUM0_i_4 ), 
+    .C0(\ram2e_ufm/N_215 ), .B0(\CS[2] ), .A0(\CS[1] ), 
+    .DI1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .DI0(N_547_i), 
+    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_547_i), .Q0(\CS[0] ), 
+    .F1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .Q1(\CS[1] ));
+  SLICE_13 SLICE_13( .D1(\ram2e_ufm/N_234 ), .C1(\ram2e_ufm/N_215 ), 
+    .B1(\CS[2] ), .A1(\CS[1] ), .D0(\ram2e_ufm/N_234 ), .C0(\ram2e_ufm/N_215 ), 
+    .B0(\CS[2] ), .A0(\CS[1] ), .DI0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), 
+    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), 
+    .F0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), .Q0(\CS[2] ), 
+    .F1(\ram2e_ufm/SUM1_0_0 ));
+  SLICE_14 SLICE_14( .C1(\ram2e_ufm/N_800 ), .B1(\Din_c[5] ), .A1(\Din_c[3] ), 
+    .D0(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ), .C0(\ram2e_ufm/N_847 ), 
+    .B0(\Din_c[2] ), .A0(\Din_c[1] ), .DI0(CmdLEDGet_3), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(CmdLEDGet_3), .Q0(CmdLEDGet), .F1(\ram2e_ufm/N_847 ));
+  SLICE_15 SLICE_15( .C1(\Din_c[7] ), .B1(\Din_c[1] ), .A1(\CS[2] ), 
+    .D0(\Din_c[4] ), .C0(\Din_c[7] ), .B0(\Din_c[1] ), .A0(\ram2e_ufm/N_883 ), 
+    .DI0(CmdLEDSet_3), .CE(N_187_i), .CLK(C14M_c), .F0(CmdLEDSet_3), 
+    .Q0(CmdLEDSet), .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ));
+  SLICE_16 SLICE_16( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[3] ), 
+    .A1(\Din_c[1] ), .D0(\Din_c[4] ), .C0(\Din_c[7] ), .B0(\Din_c[1] ), 
+    .A0(\ram2e_ufm/N_883 ), .DI0(CmdRWMaskSet_3), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(CmdRWMaskSet_3), .Q0(CmdRWMaskSet), .F1(\ram2e_ufm/N_850 ));
+  SLICE_17 SLICE_17( .C1(\ram2e_ufm/N_847 ), .B1(\Din_c[2] ), .A1(\Din_c[0] ), 
+    .D0(\ram2e_ufm/N_883 ), .C0(\Din_c[7] ), .B0(\Din_c[4] ), .A0(\Din_c[1] ), 
+    .DI0(CmdSetRWBankFFLED_4), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(CmdSetRWBankFFLED_4), .Q0(CmdSetRWBankFFLED), .F1(\ram2e_ufm/N_883 ));
+  SLICE_18 SLICE_18( .D1(RWSel), .C1(\CmdTout[2] ), .B1(\CmdTout[1] ), 
+    .A1(CO0_0), .C0(RWSel), .B0(\CmdTout[1] ), .A0(CO0_0), .DI1(N_369_i), 
+    .DI0(N_368_i), .CE(N_185_i), .CLK(C14M_c), .F0(N_368_i), .Q0(\CmdTout[1] ), 
+    .F1(N_369_i), .Q1(\CmdTout[2] ));
+  SLICE_19 SLICE_19( .B1(\CS[2] ), .A1(\CS[1] ), .B0(\RA[1] ), 
+    .A0(\ram2e_ufm/N_186 ), .M0(\S[3] ), .LSR(N_1080_0), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_660 ), .Q0(DOEEN), .F1(\ram2e_ufm/N_193 ));
+  SLICE_20 SLICE_20( .D1(\ram2e_ufm/N_660 ), .C1(\ram2e_ufm/N_659 ), 
+    .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[1] ), .D0(\ram2e_ufm/RA_35_0_0_1[0] ), 
+    .C0(\ram2e_ufm/N_801 ), .B0(\ram2e_ufm/N_684 ), .A0(\FS[7] ), .DI1(N_223), 
+    .DI0(\RA_35[0] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[0] ), .Q0(\RA[0] ), 
+    .F1(N_223), .Q1(\RA[1] ));
+  SLICE_21 SLICE_21( .C1(\ram2e_ufm/RA_35_0_0_0[3] ), .B1(\ram2e_ufm/N_801 ), 
+    .A1(\FS[10] ), .D0(\ram2e_ufm/N_680 ), .C0(\ram2e_ufm/N_679 ), 
+    .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[2] ), .DI1(\RA_35[3] ), 
+    .DI0(\RA_35[2] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[2] ), .Q0(\RA[2] ), 
+    .F1(\RA_35[3] ), .Q1(\RA[3] ));
+  SLICE_22 SLICE_22( .D1(\ram2e_ufm/RA_35_0_0_0[5] ), .C1(\ram2e_ufm/N_621 ), 
+    .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[5] ), .C0(\ram2e_ufm/RA_35_0_0_0[4] ), 
+    .B0(\ram2e_ufm/N_801 ), .A0(\FS[11] ), .DI1(\RA_35[5] ), .DI0(\RA_35[4] ), 
+    .CE(N_126), .CLK(C14M_c), .F0(\RA_35[4] ), .Q0(\RA[4] ), .F1(\RA_35[5] ), 
+    .Q1(\RA[5] ));
+  SLICE_23 SLICE_23( .C1(\ram2e_ufm/RA_35_0_0_0_0[7] ), .B1(\ram2e_ufm/N_801 ), 
+    .A1(\FS[14] ), .C0(\ram2e_ufm/RA_35_0_0_0_0[6] ), .B0(\ram2e_ufm/N_801 ), 
+    .A0(\FS[13] ), .DI1(\RA_35[7] ), .DI0(\RA_35[6] ), .CE(N_126), 
+    .CLK(C14M_c), .F0(\RA_35[6] ), .Q0(\RA[6] ), .F1(\RA_35[7] ), .Q1(\RA[7] ));
+  SLICE_24 SLICE_24( .C1(\ram2e_ufm/RA_35_0_0_0[9] ), .B1(\RA[9] ), 
+    .A1(\ram2e_ufm/N_242 ), .D0(\RA[8] ), .C0(\ram2e_ufm/N_699 ), 
+    .B0(\ram2e_ufm/N_698 ), .A0(\ram2e_ufm/N_221 ), .DI1(\RA_35[9] ), 
+    .DI0(un2_S_2_i_0_0_o3_RNIHFHN3), .CE(N_126), .CLK(C14M_c), 
+    .F0(un2_S_2_i_0_0_o3_RNIHFHN3), .Q0(\RA[8] ), .F1(\RA_35[9] ), 
+    .Q1(\RA[9] ));
+  SLICE_25 SLICE_25( .D1(\RWBank[4] ), .C1(\RA[11] ), .B1(\ram2e_ufm/N_845 ), 
+    .A1(\ram2e_ufm/N_242 ), .D0(\ram2e_ufm/RA_35_2_0_0[10] ), 
+    .C0(\ram2e_ufm/N_628 ), .B0(\ram2e_ufm/N_627 ), .A0(\ram2e_ufm/N_624 ), 
+    .DI1(\RA_35[11] ), .DI0(\RA_35[10] ), .CE(N_126), .CLK(C14M_c), 
+    .F0(\RA_35[10] ), .Q0(\RA[10] ), .F1(\RA_35[11] ), .Q1(\RA[11] ));
+  SLICE_26 SLICE_26( .C1(\RC[2] ), .B1(\RC[1] ), .A1(CO0_1), .C0(\RC[2] ), 
+    .B0(CO0_1), .A0(\RC[1] ), .DI1(\RC_3[2] ), .DI0(\RC_3[1] ), .CE(RC12), 
+    .CLK(C14M_c), .F0(\RC_3[1] ), .Q0(\RC[1] ), .F1(\RC_3[2] ), .Q1(\RC[2] ));
+  SLICE_27 SLICE_27( .C1(\ram2e_ufm/RWMask[1] ), .B1(\ram2e_ufm/N_188 ), 
+    .A1(\Din_c[1] ), .C0(\ram2e_ufm/RWMask[0] ), .B0(\ram2e_ufm/N_188 ), 
+    .A0(\Din_c[0] ), .DI1(\RWBank_3[1] ), .DI0(\RWBank_3[0] ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\RWBank_3[0] ), .Q0(\RWBank[0] ), .F1(\RWBank_3[1] ), 
+    .Q1(\RWBank[1] ));
+  SLICE_28 SLICE_28( .C1(\ram2e_ufm/RWMask[3] ), .B1(\ram2e_ufm/N_188 ), 
+    .A1(\Din_c[3] ), .C0(\ram2e_ufm/RWMask[2] ), .B0(\ram2e_ufm/N_188 ), 
+    .A0(\Din_c[2] ), .DI1(\RWBank_3[3] ), .DI0(\RWBank_3[2] ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\RWBank_3[2] ), .Q0(\RWBank[2] ), .F1(\RWBank_3[3] ), 
+    .Q1(\RWBank[3] ));
+  SLICE_29 SLICE_29( .C1(\ram2e_ufm/RWMask[5] ), .B1(\ram2e_ufm/N_188 ), 
+    .A1(\Din_c[5] ), .C0(\ram2e_ufm/RWMask[4] ), .B0(\ram2e_ufm/N_188 ), 
+    .A0(\Din_c[4] ), .DI1(\RWBank_3[5] ), .DI0(\RWBank_3[4] ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\RWBank_3[4] ), .Q0(\RWBank[4] ), .F1(\RWBank_3[5] ), 
+    .Q1(\RWBank[5] ));
+  SLICE_30 SLICE_30( .C1(\ram2e_ufm/RWMask[7] ), .B1(\ram2e_ufm/N_188 ), 
+    .A1(\Din_c[7] ), .C0(\ram2e_ufm/RWMask[6] ), .B0(\ram2e_ufm/N_188 ), 
+    .A0(\Din_c[6] ), .DI1(\RWBank_3[7] ), .DI0(\RWBank_3[6] ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\RWBank_3[6] ), .Q0(\RWBank[6] ), .F1(\RWBank_3[7] ), 
+    .Q1(\RWBank[7] ));
+  SLICE_31 SLICE_31( .D1(\RA[3] ), .C1(\ram2e_ufm/N_186 ), 
+    .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[3] ), .D0(nWE_c), .C0(nC07X_c), 
+    .B0(\RA[3] ), .A0(\RA[0] ), .DI0(RWSel_2), .CE(un9_VOEEN_0_a2_0_a3_0_a3), 
+    .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(\ram2e_ufm/RA_35_0_0_0[3] ));
+  SLICE_32 SLICE_32( .D1(\ram2e_ufm/Ready3_0_a3_5 ), 
+    .C1(\ram2e_ufm/Ready3_0_a3_4 ), .B1(\ram2e_ufm/Ready3_0_a3_3 ), 
+    .A1(\ram2e_ufm/N_885 ), .B0(Ready), .A0(Ready3), .DI0(N_1026_0), 
+    .CLK(C14M_c), .F0(N_1026_0), .Q0(Ready), .F1(Ready3));
+  SLICE_33 SLICE_33( .D1(\ram2e_ufm/S_r_i_0_o2[1] ), .C1(\ram2e_ufm/N_271 ), 
+    .B1(\ram2e_ufm/N_194 ), .A1(S_1), .D0(\S[1] ), .C0(\ram2e_ufm/N_643 ), 
+    .B0(\ram2e_ufm/N_271 ), .A0(S_1), .DI1(N_362_i), .DI0(\S_s_0_0[0] ), 
+    .CLK(C14M_c), .F0(\S_s_0_0[0] ), .Q0(\S[0] ), .F1(N_362_i), .Q1(\S[1] ));
+  SLICE_34 SLICE_34( .D1(\S[2] ), .C1(S_1), .B1(\ram2e_ufm/N_194 ), 
+    .A1(\S[3] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\ram2e_ufm/N_194 ), .A0(S_1), 
+    .DI1(N_372_i), .DI0(N_361_i), .CLK(C14M_c), .F0(N_361_i), .Q0(\S[2] ), 
+    .F1(N_372_i), .Q1(\S[3] ));
+  SLICE_35 SLICE_35( .D1(N_551), .C1(\S[1] ), .B1(\S[0] ), .A1(\FS[4] ), 
+    .B0(\S[3] ), .A0(\S[2] ), .DI0(N_551), .LSR(N_1078_0), .CLK(C14M_c), 
+    .F0(N_551), .Q0(VOEEN), .F1(BA_0_sqmuxa));
+  SLICE_36 SLICE_36( .D1(\ram2e_ufm/N_285_i ), .C1(\S[0] ), .B1(\S[1] ), 
+    .A1(\ram2e_ufm/N_804 ), .D0(nWE_c), .C0(\ram2e_ufm/N_872 ), 
+    .B0(\ram2e_ufm/N_641 ), .A0(\ram2e_ufm/N_640 ), .DI0(N_370_i), 
+    .CLK(C14M_c), .F0(N_370_i), .Q0(nCAS), .F1(\ram2e_ufm/N_872 ));
+  SLICE_37 SLICE_37( .D1(\S[0] ), .C1(\S[1] ), .B1(\ram2e_ufm/N_285_i ), 
+    .A1(\ram2e_ufm/N_804 ), .D0(\ram2e_ufm/nRAS_s_i_0_0 ), 
+    .C0(\ram2e_ufm/N_617 ), .B0(\ram2e_ufm/N_616 ), .A0(\ram2e_ufm/N_615 ), 
+    .DI0(N_358_i), .CLK(C14M_c), .F0(N_358_i), .Q0(nRAS), 
+    .F1(\ram2e_ufm/N_617 ));
+  SLICE_38 SLICE_38( .D1(\S[2] ), .C1(\ram2e_ufm/S_r_i_0_o2[1] ), 
+    .B1(\ram2e_ufm/N_226 ), .A1(\ram2e_ufm/N_285_i ), .D0(\ram2e_ufm/N_804 ), 
+    .C0(\ram2e_ufm/N_866 ), .B0(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ), 
+    .A0(\ram2e_ufm/N_615 ), .DI0(N_359_i), .CLK(C14M_c), .F0(N_359_i), 
+    .Q0(nRWE), .F1(\ram2e_ufm/N_615 ));
+  ram2e_ufm_SLICE_39 \ram2e_ufm/SLICE_39 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ), 
+    .B1(\Din_c[0] ), .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), 
+    .D0(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ), .C0(\ram2e_ufm/N_800 ), 
+    .B0(\Din_c[2] ), .A0(\Din_c[1] ), .DI0(\ram2e_ufm/CmdBitbangMXO2_3 ), 
+    .CE(N_187_i), .CLK(C14M_c), .F0(\ram2e_ufm/CmdBitbangMXO2_3 ), 
+    .Q0(\ram2e_ufm/CmdBitbangMXO2 ), .F1(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ));
+  ram2e_ufm_SLICE_40 \ram2e_ufm/SLICE_40 ( .D1(\CS[1] ), .C1(\CS[2] ), 
+    .B1(\CS[0] ), .A1(\Din_c[6] ), .B0(\ram2e_ufm/N_851 ), 
+    .A0(\ram2e_ufm/N_800 ), .DI0(\ram2e_ufm/CmdExecMXO2_3 ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/CmdExecMXO2_3 ), .Q0(\ram2e_ufm/CmdExecMXO2 ), 
+    .F1(\ram2e_ufm/N_800 ));
+  ram2e_ufm_SLICE_41 \ram2e_ufm/SLICE_41 ( .D1(\Din_c[0] ), .C1(\Din_c[1] ), 
+    .B1(\Din_c[2] ), .A1(\Din_c[4] ), 
+    .D0(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ), .C0(\ram2e_ufm/N_800 ), 
+    .B0(\ram2e_ufm/N_190 ), .A0(\Din_c[7] ), 
+    .DI0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .Q0(\ram2e_ufm/CmdSetRWBankFFChip ), 
+    .F1(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ));
+  ram2e_ufm_SLICE_42 \ram2e_ufm/SLICE_42 ( .C1(\Din_c[6] ), .B1(\Din_c[2] ), 
+    .A1(\Din_c[0] ), .C0(\ram2e_ufm/wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), 
+    .DI0(\ram2e_ufm/N_295 ), .CE(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_295 ), .Q0(\ram2e_ufm/LEDEN ), 
+    .F1(\ram2e_ufm/N_212 ));
+  ram2e_ufm_SLICE_43 \ram2e_ufm/SLICE_43 ( .C1(\ram2e_ufm/wb_dato[1] ), 
+    .B1(\S[3] ), .A1(\Din_c[1] ), .C0(\ram2e_ufm/wb_dato[0] ), .B0(\S[3] ), 
+    .A0(\Din_c[0] ), .DI1(\ram2e_ufm/N_307_i ), .DI0(\ram2e_ufm/N_309_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_309_i ), .Q0(\ram2e_ufm/RWMask[0] ), 
+    .F1(\ram2e_ufm/N_307_i ), .Q1(\ram2e_ufm/RWMask[1] ));
+  ram2e_ufm_SLICE_44 \ram2e_ufm/SLICE_44 ( .C1(\ram2e_ufm/wb_dato[3] ), 
+    .B1(\S[3] ), .A1(\Din_c[3] ), .C0(\ram2e_ufm/wb_dato[2] ), .B0(\S[3] ), 
+    .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_302_i ), .DI0(\ram2e_ufm/N_304_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_304_i ), .Q0(\ram2e_ufm/RWMask[2] ), 
+    .F1(\ram2e_ufm/N_302_i ), .Q1(\ram2e_ufm/RWMask[3] ));
+  ram2e_ufm_SLICE_45 \ram2e_ufm/SLICE_45 ( .C1(\ram2e_ufm/wb_dato[5] ), 
+    .B1(\S[3] ), .A1(\Din_c[5] ), .C0(\ram2e_ufm/wb_dato[4] ), .B0(\S[3] ), 
+    .A0(\Din_c[4] ), .DI1(\ram2e_ufm/N_301_i ), .DI0(\ram2e_ufm/N_310_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_310_i ), .Q0(\ram2e_ufm/RWMask[4] ), 
+    .F1(\ram2e_ufm/N_301_i ), .Q1(\ram2e_ufm/RWMask[5] ));
+  ram2e_ufm_SLICE_46 \ram2e_ufm/SLICE_46 ( .C1(\ram2e_ufm/wb_dato[7] ), 
+    .B1(\S[3] ), .A1(\Din_c[7] ), .C0(\ram2e_ufm/wb_dato[6] ), .B0(\S[3] ), 
+    .A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_296 ), .DI0(\ram2e_ufm/N_300_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_300_i ), .Q0(\ram2e_ufm/RWMask[6] ), 
+    .F1(\ram2e_ufm/N_296 ), .Q1(\ram2e_ufm/RWMask[7] ));
+  ram2e_ufm_SLICE_47 \ram2e_ufm/SLICE_47 ( .D1(\ram2e_ufm/wb_adr_7_5_41_0_1 ), 
+    .C1(\S[2] ), .B1(\ram2e_ufm/N_768 ), .A1(\Din_c[1] ), 
+    .D0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), 
+    .B0(\ram2e_ufm/N_793 ), .A0(\FS[10] ), .DI1(\ram2e_ufm/wb_adr_RNO[1] ), 
+    .DI0(\ram2e_ufm/wb_adr_7_i_i[0] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i[0] ), .Q0(\ram2e_ufm/wb_adr[0] ), 
+    .F1(\ram2e_ufm/wb_adr_RNO[1] ), .Q1(\ram2e_ufm/wb_adr[1] ));
+  ram2e_ufm_SLICE_48 \ram2e_ufm/SLICE_48 ( .B1(\S[2] ), .A1(\Din_c[3] ), 
+    .B0(\S[2] ), .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_268_i ), 
+    .DI0(\ram2e_ufm/N_80_i ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_80_i ), .Q0(\ram2e_ufm/wb_adr[2] ), 
+    .F1(\ram2e_ufm/N_268_i ), .Q1(\ram2e_ufm/wb_adr[3] ));
+  ram2e_ufm_SLICE_49 \ram2e_ufm/SLICE_49 ( .C1(\S[2] ), .B1(\FS[14] ), 
+    .A1(\Din_c[5] ), .C0(\S[2] ), .B0(\FS[14] ), .A0(\Din_c[4] ), 
+    .DI1(\ram2e_ufm/N_290 ), .DI0(\ram2e_ufm/N_294 ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_294 ), .Q0(\ram2e_ufm/wb_adr[4] ), .F1(\ram2e_ufm/N_290 ), 
+    .Q1(\ram2e_ufm/wb_adr[5] ));
+  ram2e_ufm_SLICE_50 \ram2e_ufm/SLICE_50 ( .B1(\S[2] ), .A1(\Din_c[7] ), 
+    .C0(\S[2] ), .B0(\FS[14] ), .A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_267_i ), 
+    .DI0(\ram2e_ufm/N_284 ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_284 ), .Q0(\ram2e_ufm/wb_adr[6] ), 
+    .F1(\ram2e_ufm/N_267_i ), .Q1(\ram2e_ufm/wb_adr[7] ));
+  ram2e_ufm_SLICE_51 \ram2e_ufm/SLICE_51 ( .D1(\ram2e_ufm/wb_ack ), 
+    .C1(\ram2e_ufm/N_336 ), .B1(\FS[14] ), .A1(\FS[0] ), 
+    .C0(\ram2e_ufm/CmdExecMXO2 ), .B0(\S[3] ), .A0(\ram2e_ufm/N_687 ), 
+    .DI0(\ram2e_ufm/wb_cyc_stb_RNO ), 
+    .CE(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_cyc_stb_RNO ), .Q0(\ram2e_ufm/wb_cyc_stb ), 
+    .F1(\ram2e_ufm/N_687 ));
+  ram2e_ufm_SLICE_52 \ram2e_ufm/SLICE_52 ( .D1(\ram2e_ufm/wb_dati_7_0_0_0[1] ), 
+    .C1(\ram2e_ufm/N_849 ), .B1(\ram2e_ufm/N_793 ), .A1(\ram2e_ufm/N_611 ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ), .C0(\ram2e_ufm/wb_adr[0] ), 
+    .B0(\S[2] ), .A0(\ram2e_ufm/N_856 ), .DI1(\ram2e_ufm/wb_dati_7[1] ), 
+    .DI0(\ram2e_ufm/wb_dati_7[0] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[0] ), .Q0(\ram2e_ufm/wb_dati[0] ), 
+    .F1(\ram2e_ufm/wb_dati_7[1] ), .Q1(\ram2e_ufm/wb_dati[1] ));
+  ram2e_ufm_SLICE_53 \ram2e_ufm/SLICE_53 ( 
+    .D1(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .C1(\ram2e_ufm/N_849 ), 
+    .B1(\ram2e_ufm/N_783 ), .A1(\ram2e_ufm/N_611 ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C0(\ram2e_ufm/wb_adr[2] ), 
+    .B0(\S[2] ), .A0(\ram2e_ufm/N_760 ), .DI1(\ram2e_ufm/wb_dati_7[3] ), 
+    .DI0(\ram2e_ufm/wb_dati_7[2] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[2] ), .Q0(\ram2e_ufm/wb_dati[2] ), 
+    .F1(\ram2e_ufm/wb_dati_7[3] ), .Q1(\ram2e_ufm/wb_dati[3] ));
+  ram2e_ufm_SLICE_54 \ram2e_ufm/SLICE_54 ( 
+    .D1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C1(\ram2e_ufm/wb_adr[5] ), 
+    .B1(\S[2] ), .A1(\ram2e_ufm/N_760 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0[4] ), 
+    .C0(\ram2e_ufm/N_763 ), .B0(\ram2e_ufm/N_760 ), .A0(\ram2e_ufm/N_757 ), 
+    .DI1(\ram2e_ufm/wb_dati_7[5] ), .DI0(\ram2e_ufm/wb_dati_7[4] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_dati_7[4] ), .Q0(\ram2e_ufm/wb_dati[4] ), 
+    .F1(\ram2e_ufm/wb_dati_7[5] ), .Q1(\ram2e_ufm/wb_dati[5] ));
+  ram2e_ufm_SLICE_55 \ram2e_ufm/SLICE_55 ( 
+    .D1(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), 
+    .C1(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), .B1(\ram2e_ufm/N_604 ), 
+    .A1(\ram2e_ufm/N_602 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), 
+    .C0(\ram2e_ufm/N_849 ), .B0(\ram2e_ufm/N_793 ), .A0(\ram2e_ufm/N_757 ), 
+    .DI1(\ram2e_ufm/wb_dati_7[7] ), .DI0(\ram2e_ufm/wb_dati_7[6] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_dati_7[6] ), .Q0(\ram2e_ufm/wb_dati[6] ), 
+    .F1(\ram2e_ufm/wb_dati_7[7] ), .Q1(\ram2e_ufm/wb_dati[7] ));
+  ram2e_ufm_SLICE_56 \ram2e_ufm/SLICE_56 ( .D1(\S[3] ), .C1(\S[1] ), 
+    .B1(\S[0] ), .A1(\FS[14] ), .D0(\ram2e_ufm/wb_reqc_1 ), .C0(\FS[13] ), 
+    .B0(\FS[12] ), .A0(\FS[11] ), .DI0(\ram2e_ufm/wb_reqc_i ), 
+    .CE(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ), .LSR(\S[2] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_reqc_i ), .Q0(\ram2e_ufm/wb_req ), 
+    .F1(\ram2e_ufm/wb_reqc_1 ));
+  ram2e_ufm_SLICE_57 \ram2e_ufm/SLICE_57 ( .D1(\FS[15] ), .C1(\FS[14] ), 
+    .B1(\FS[4] ), .A1(\FS[2] ), .B0(\FS[15] ), .A0(\FS[14] ), 
+    .DI0(\ram2e_ufm/wb_rst8 ), .LSR(\ram2e_ufm/wb_rst16_i ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_rst8 ), .Q0(\ram2e_ufm/wb_rst ), 
+    .F1(\ram2e_ufm/Ready3_0_a3_4 ));
+  ram2e_ufm_SLICE_58 \ram2e_ufm/SLICE_58 ( 
+    .D1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), .C1(\ram2e_ufm/N_885 ), 
+    .B1(\ram2e_ufm/N_799 ), .A1(\FS[12] ), 
+    .D0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ), .C0(\ram2e_ufm/N_799 ), 
+    .B0(\ram2e_ufm/N_208 ), .A0(\FS[13] ), .DI0(\ram2e_ufm/wb_we_RNO ), 
+    .CE(\ram2e_ufm/wb_we_RNO_0 ), .CLK(C14M_c), .F0(\ram2e_ufm/wb_we_RNO ), 
+    .Q0(\ram2e_ufm/wb_we ), .F1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ));
+  ram2e_ufm_SUM0_i_m3_0_SLICE_59 \ram2e_ufm/SUM0_i_m3_0/SLICE_59 ( 
+    .C1(\CS[1] ), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .C0(\Din_c[7] ), 
+    .B0(\Din_c[5] ), .A0(\Din_c[3] ), .M0(\Din_c[1] ), 
+    .OFX0(\ram2e_ufm/N_338 ));
+  ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 
+    \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60 ( .D1(\CS[0] ), .C1(\Din_c[6] ), 
+    .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), .A1(\ram2e_ufm/N_193 ), 
+    .C0(CO0_0), .B0(\CmdTout[1] ), .A0(\CmdTout[2] ), .M0(RWSel), 
+    .OFX0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ));
+  ram2e_ufm_CKE_7_SLICE_61 \ram2e_ufm/CKE_7/SLICE_61 ( .C1(\RC[1] ), 
+    .B1(\ram2e_ufm/N_821 ), .A1(\ram2e_ufm/N_817 ), .C0(nWE_c), .B0(\S[1] ), 
+    .A0(\ram2e_ufm/N_804 ), .M0(\ram2e_ufm/CKE_7_sm0 ), 
+    .OFX0(\ram2e_ufm/CKE_7 ));
+  ram2e_ufm_SLICE_62 \ram2e_ufm/SLICE_62 ( .D1(\ram2e_ufm/N_851 ), 
+    .C1(\Din_c[6] ), .B1(\CS[2] ), .A1(\CS[1] ), 
+    .D0(\ram2e_ufm/SUM0_i_a3_4_0 ), .C0(\ram2e_ufm/N_234 ), .B0(\CS[2] ), 
+    .A0(\CS[1] ), .F0(\ram2e_ufm/N_720_tz ), .F1(\ram2e_ufm/SUM0_i_a3_4_0 ));
+  ram2e_ufm_SLICE_63 \ram2e_ufm/SLICE_63 ( .D1(\ram2e_ufm/SUM0_i_0 ), 
+    .C1(\ram2e_ufm/N_350 ), .B1(\CS[2] ), .A1(\CS[0] ), 
+    .D0(\ram2e_ufm/SUM0_i_3 ), .C0(\ram2e_ufm/SUM0_i_1 ), 
+    .B0(\ram2e_ufm/N_187 ), .A0(\CS[0] ), .F0(\ram2e_ufm/SUM0_i_4 ), 
+    .F1(\ram2e_ufm/SUM0_i_1 ));
+  ram2e_ufm_SLICE_64 \ram2e_ufm/SLICE_64 ( .C1(\ram2e_ufm/N_793 ), 
+    .B1(\FS[11] ), .A1(\FS[9] ), .D0(\ram2e_ufm/N_856 ), 
+    .C0(\ram2e_ufm/N_755 ), .B0(\FS[13] ), .A0(\FS[11] ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .F1(\ram2e_ufm/N_755 ));
+  ram2e_ufm_SLICE_65 \ram2e_ufm/SLICE_65 ( .D1(\ram2e_ufm/N_193 ), 
+    .C1(\Din_c[6] ), .B1(\Din_c[0] ), .A1(\CS[0] ), .D0(\ram2e_ufm/N_735 ), 
+    .C0(\ram2e_ufm/N_345 ), .B0(\CS[1] ), .A0(\CS[0] ), 
+    .F0(\ram2e_ufm/SUM0_i_0 ), .F1(\ram2e_ufm/N_735 ));
+  ram2e_ufm_SLICE_66 \ram2e_ufm/SLICE_66 ( .D1(\ram2e_ufm/wb_ack ), 
+    .C1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), 
+    .B1(\ram2e_ufm/N_777 ), .A1(\FS[14] ), .D0(\ram2e_ufm/wb_ack ), 
+    .C0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ), 
+    .B0(\ram2e_ufm/CmdExecMXO2 ), .A0(\ram2e_ufm/N_187 ), 
+    .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), 
+    .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ));
+  ram2e_ufm_SLICE_67 \ram2e_ufm/SLICE_67 ( .C1(\FS[3] ), .B1(\FS[2] ), 
+    .A1(\FS[1] ), .D0(\S[1] ), .C0(\ram2e_ufm/N_250 ), .B0(\FS[4] ), 
+    .A0(\FS[3] ), .F0(\ram2e_ufm/N_256 ), .F1(\ram2e_ufm/N_250 ));
+  ram2e_ufm_SLICE_68 \ram2e_ufm/SLICE_68 ( 
+    .D1(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .C1(\ram2e_ufm/N_783 ), .B1(\FS[9] ), 
+    .A1(\FS[8] ), .D0(\FS[12] ), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[8] ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .F1(\ram2e_ufm/wb_adr_7_i_i_3[0] ));
+  ram2e_ufm_SLICE_69 \ram2e_ufm/SLICE_69 ( .D1(\ram2e_ufm/N_254 ), 
+    .C1(\ram2e_ufm/wb_rst16_i ), .B1(\FS[15] ), .A1(\FS[0] ), .D0(\S[2] ), 
+    .C0(\S[3] ), .B0(\S[1] ), .A0(\S[0] ), .F0(\ram2e_ufm/wb_rst16_i ), 
+    .F1(\ram2e_ufm/N_641 ));
+  ram2e_ufm_SLICE_70 \ram2e_ufm/SLICE_70 ( .C1(\FS[14] ), 
+    .B1(\ram2e_ufm/N_777 ), .A1(\FS[8] ), .D0(\FS[12] ), .C0(\FS[13] ), 
+    .B0(\ram2e_ufm/N_807 ), .A0(\ram2e_ufm/N_876 ), .F0(\ram2e_ufm/N_604 ), 
+    .F1(\ram2e_ufm/N_807 ));
+  ram2e_ufm_SLICE_71 \ram2e_ufm/SLICE_71 ( .C1(\FS[4] ), 
+    .B1(\ram2e_ufm/N_784 ), .A1(\FS[3] ), .C0(\S[2] ), .B0(\S[3] ), 
+    .A0(\S[0] ), .F0(\ram2e_ufm/N_784 ), .F1(\ram2e_ufm/N_801 ));
+  ram2e_ufm_SLICE_72 \ram2e_ufm/SLICE_72 ( .D1(\S[0] ), .C1(\RWBank[5] ), 
+    .B1(\ram2e_ufm/N_560 ), .A1(\FS[4] ), .C0(\S[2] ), .B0(\S[3] ), 
+    .A0(\S[1] ), .F0(\ram2e_ufm/N_560 ), .F1(\BA_4[0] ));
+  ram2e_ufm_SLICE_73 \ram2e_ufm/SLICE_73 ( .D1(\ram2e_ufm/N_873 ), 
+    .C1(\ram2e_ufm/N_781 ), .B1(\ram2e_ufm/N_611 ), .A1(\ram2e_ufm/N_184 ), 
+    .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), 
+    .F0(\ram2e_ufm/N_873 ), .F1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ));
+  ram2e_ufm_SLICE_74 \ram2e_ufm/SLICE_74 ( .C1(\RWBank[3] ), 
+    .B1(\ram2e_ufm/N_845 ), .A1(\ram2e_ufm/N_625 ), .D0(\S[0] ), .C0(\S[1] ), 
+    .B0(\S[2] ), .A0(\S[3] ), .F0(\ram2e_ufm/N_845 ), 
+    .F1(\ram2e_ufm/RA_35_2_0_0[10] ));
+  ram2e_ufm_SLICE_75 \ram2e_ufm/SLICE_75 ( .C1(\FS[11] ), .B1(\FS[10] ), 
+    .A1(\FS[9] ), .D0(\FS[12] ), .C0(\FS[13] ), .B0(\ram2e_ufm/N_876 ), 
+    .A0(\ram2e_ufm/wb_ack ), 
+    .F0(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), 
+    .F1(\ram2e_ufm/N_876 ));
+  ram2e_ufm_SLICE_76 \ram2e_ufm/SLICE_76 ( .B1(\FS[11] ), .A1(\FS[10] ), 
+    .D0(\FS[12] ), .C0(\FS[13] ), .B0(\ram2e_ufm/N_811 ), 
+    .A0(\ram2e_ufm/N_206 ), .F0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), 
+    .F1(\ram2e_ufm/N_811 ));
+  ram2e_ufm_SLICE_77 \ram2e_ufm/SLICE_77 ( .C1(\ram2e_ufm/N_185 ), .B1(RWSel), 
+    .A1(\CS[0] ), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), 
+    .F0(\ram2e_ufm/N_185 ), .F1(\ram2e_ufm/N_215 ));
+  ram2e_ufm_SLICE_78 \ram2e_ufm/SLICE_78 ( .B1(\S[1] ), .A1(\S[0] ), 
+    .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\RWBank[1] ), 
+    .F0(\ram2e_ufm/N_699 ), .F1(\ram2e_ufm/S_r_i_0_o2[1] ));
+  ram2e_ufm_SLICE_79 \ram2e_ufm/SLICE_79 ( 
+    .D1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), 
+    .C1(\ram2e_ufm/N_807 ), .B1(\ram2e_ufm/N_187 ), .A1(CmdLEDSet), 
+    .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(RWSel), 
+    .F0(\ram2e_ufm/N_187 ), .F1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ));
+  ram2e_ufm_SLICE_80 \ram2e_ufm/SLICE_80 ( .D1(N_551), .C1(\S[1] ), 
+    .B1(\S[0] ), .A1(\FS[15] ), .D0(\ram2e_ufm/N_185 ), .C0(RWSel), 
+    .B0(\ram2e_ufm/N_777 ), .A0(\ram2e_ufm/CmdBitbangMXO2 ), 
+    .F0(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .F1(\ram2e_ufm/N_777 ));
+  ram2e_ufm_SLICE_81 \ram2e_ufm/SLICE_81 ( .D1(\FS[8] ), 
+    .C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), .A1(\FS[9] ), .D0(\FS[12] ), 
+    .C0(\FS[13] ), .B0(\ram2e_ufm/N_811 ), .A0(\ram2e_ufm/N_856 ), 
+    .F0(\ram2e_ufm/N_757 ), .F1(\ram2e_ufm/N_856 ));
+  ram2e_ufm_SLICE_82 \ram2e_ufm/SLICE_82 ( 
+    .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ), 
+    .C1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .B1(\Din_c[6] ), .A1(\CS[0] ), 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ), 
+    .C0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), 
+    .B0(\ram2e_ufm/N_637 ), .A0(\ram2e_ufm/N_185 ), .F0(un1_CS_0_sqmuxa_i), 
+    .F1(\ram2e_ufm/N_637 ));
+  ram2e_ufm_SLICE_83 \ram2e_ufm/SLICE_83 ( .C1(\ram2e_ufm/N_851 ), 
+    .B1(\Din_c[6] ), .A1(\CS[2] ), .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ), 
+    .C0(RWSel), .B0(\ram2e_ufm/N_592 ), .A0(\CS[0] ), 
+    .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ));
+  ram2e_ufm_SLICE_84 \ram2e_ufm/SLICE_84 ( .D1(\ram2e_ufm/N_850 ), 
+    .C1(\ram2e_ufm/N_212 ), .B1(\Din_c[4] ), .A1(\CS[2] ), 
+    .D0(\ram2e_ufm/N_886 ), .C0(\ram2e_ufm/N_720_tz ), .B0(\ram2e_ufm/N_187 ), 
+    .A0(\CS[1] ), .F0(\ram2e_ufm/SUM0_i_3 ), .F1(\ram2e_ufm/N_886 ));
+  ram2e_ufm_SLICE_85 \ram2e_ufm/SLICE_85 ( .D1(\FS[13] ), 
+    .C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), .A1(\FS[12] ), 
+    .D0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), 
+    .C0(\ram2e_ufm/N_793 ), .B0(\ram2e_ufm/N_187 ), .A0(CmdRWMaskSet), 
+    .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .F1(\ram2e_ufm/N_793 ));
+  ram2e_ufm_SLICE_86 \ram2e_ufm/SLICE_86 ( .B1(\S[2] ), .A1(\Din_c[0] ), 
+    .D0(\ram2e_ufm/wb_adr_7_i_i_3[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), 
+    .B0(\ram2e_ufm/N_753 ), .A0(\ram2e_ufm/N_634 ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), .F1(\ram2e_ufm/N_634 ));
+  ram2e_ufm_SLICE_87 \ram2e_ufm/SLICE_87 ( 
+    .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C1(\ram2e_ufm/N_212 ), 
+    .B1(\ram2e_ufm/N_190 ), .A1(\Din_c[1] ), .C0(\ram2e_ufm/N_886 ), 
+    .B0(\ram2e_ufm/N_234 ), .A0(\CS[1] ), .F0(\ram2e_ufm/N_592 ), 
+    .F1(\ram2e_ufm/N_234 ));
+  ram2e_ufm_SLICE_88 \ram2e_ufm/SLICE_88 ( .B1(\FS[11] ), .A1(\FS[10] ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\ram2e_ufm/N_876 ), 
+    .B0(\ram2e_ufm/N_793 ), .A0(\ram2e_ufm/N_206 ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ));
+  ram2e_ufm_SLICE_89 \ram2e_ufm/SLICE_89 ( .C1(\FS[14] ), 
+    .B1(\ram2e_ufm/N_777 ), .A1(\FS[13] ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .C0(\ram2e_ufm/wb_adr[3] ), 
+    .B0(\S[2] ), .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), 
+    .F1(\ram2e_ufm/N_783 ));
+  ram2e_ufm_SLICE_90 \ram2e_ufm/SLICE_90 ( .D1(\ram2e_ufm/N_206 ), 
+    .C1(\FS[12] ), .B1(\FS[11] ), .A1(\FS[10] ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ), .C0(\ram2e_ufm/wb_adr[6] ), 
+    .B0(\S[2] ), .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ));
+  ram2e_ufm_SLICE_91 \ram2e_ufm/SLICE_91 ( .D1(CO0_1), .C1(\RC[2] ), 
+    .B1(\ram2e_ufm/N_817 ), .A1(\RC[1] ), .D0(\ram2e_ufm/N_890 ), 
+    .C0(\ram2e_ufm/N_784 ), .B0(\ram2e_ufm/N_256 ), .A0(\ram2e_ufm/N_285_i ), 
+    .F0(\ram2e_ufm/nRAS_s_i_0_0 ), .F1(\ram2e_ufm/N_890 ));
+  ram2e_ufm_SLICE_92 \ram2e_ufm/SLICE_92 ( .D1(nWE_c), .C1(\S[1] ), 
+    .B1(\ram2e_ufm/N_804 ), .A1(N_551), .D0(\S[0] ), .C0(\ram2e_ufm/N_890 ), 
+    .B0(\ram2e_ufm/N_220 ), .A0(\ram2e_ufm/N_285_i ), .F0(\ram2e_ufm/N_640 ), 
+    .F1(\ram2e_ufm/N_220 ));
+  ram2e_ufm_SLICE_93 \ram2e_ufm/SLICE_93 ( .D1(\FS[11] ), .C1(\FS[10] ), 
+    .B1(\FS[9] ), .A1(\FS[8] ), .C0(\ram2e_ufm/N_783 ), .B0(\ram2e_ufm/N_196 ), 
+    .A0(\FS[12] ), .F0(\ram2e_ufm/N_760 ), .F1(\ram2e_ufm/N_196 ));
+  ram2e_ufm_SLICE_94 \ram2e_ufm/SLICE_94 ( .B1(\Din_c[7] ), .A1(\Din_c[4] ), 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C0(\ram2e_ufm/N_243 ), 
+    .B0(\Din_c[0] ), .A0(\CS[2] ), .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ));
+  ram2e_ufm_SLICE_95 \ram2e_ufm/SLICE_95 ( .D1(\S[3] ), .C1(\S[2] ), 
+    .B1(\S[1] ), .A1(\S[0] ), .D0(\RA[4] ), .C0(\ram2e_ufm/N_186 ), 
+    .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[4] ), .F0(\ram2e_ufm/RA_35_0_0_0[4] ), 
+    .F1(\ram2e_ufm/N_182 ));
+  ram2e_ufm_SLICE_96 \ram2e_ufm/SLICE_96 ( .D1(\S[3] ), .C1(\S[2] ), 
+    .B1(\S[1] ), .A1(\S[0] ), .D0(\RA[6] ), .C0(\ram2e_ufm/N_186 ), 
+    .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[6] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[6] ), 
+    .F1(\ram2e_ufm/N_186 ));
+  ram2e_ufm_SLICE_97 \ram2e_ufm/SLICE_97 ( .C1(\ram2e_ufm/N_873 ), 
+    .B1(\FS[13] ), .A1(\FS[12] ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ), 
+    .C0(\ram2e_ufm/wb_adr[1] ), .B0(\S[2] ), .A0(\ram2e_ufm/N_781 ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0[1] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ));
+  ram2e_ufm_SLICE_98 \ram2e_ufm/SLICE_98 ( .B1(\ram2e_ufm/N_777 ), 
+    .A1(\FS[14] ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), 
+    .C0(\ram2e_ufm/wb_adr[7] ), .B0(\S[2] ), .A0(\ram2e_ufm/N_781 ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), .F1(\ram2e_ufm/N_781 ));
+  ram2e_ufm_SLICE_99 \ram2e_ufm/SLICE_99 ( .C1(\FS[11] ), .B1(\FS[10] ), 
+    .A1(\FS[8] ), .D0(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ), 
+    .C0(\ram2e_ufm/N_781 ), .B0(\ram2e_ufm/N_565 ), .A0(\FS[12] ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), 
+    .F1(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ));
+  ram2e_ufm_SLICE_100 \ram2e_ufm/SLICE_100 ( .D1(\Din_c[5] ), .C1(\Din_c[3] ), 
+    .B1(\Din_c[2] ), .A1(\Din_c[1] ), .D0(\ram2e_ufm/N_243 ), .C0(\Din_c[7] ), 
+    .B0(\Din_c[4] ), .A0(\CS[2] ), .F0(\ram2e_ufm/N_345 ), 
+    .F1(\ram2e_ufm/N_243 ));
+  ram2e_ufm_SLICE_101 \ram2e_ufm/SLICE_101 ( .B1(\Din_c[5] ), .A1(\Din_c[3] ), 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ), .C0(\ram2e_ufm/N_850 ), 
+    .B0(\ram2e_ufm/N_190 ), .A0(\CS[1] ), 
+    .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .F1(\ram2e_ufm/N_190 ));
+  ram2e_ufm_SLICE_102 \ram2e_ufm/SLICE_102 ( .C1(\S[3] ), .B1(\S[2] ), 
+    .A1(\S[1] ), .C0(\ram2e_ufm/CKE_7s2_0_0_0 ), .B0(\ram2e_ufm/N_817 ), 
+    .A0(\ram2e_ufm/N_220 ), .F0(\ram2e_ufm/CKE_7_sm0 ), .F1(\ram2e_ufm/N_817 ));
+  ram2e_ufm_SLICE_103 \ram2e_ufm/SLICE_103 ( .B1(\FS[13] ), .A1(\FS[12] ), 
+    .D0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), .C0(\ram2e_ufm/N_799 ), 
+    .B0(\ram2e_ufm/N_204 ), .A0(\ram2e_ufm/N_184 ), 
+    .F0(\ram2e_ufm/wb_adr_7_5_41_0_1 ), .F1(\ram2e_ufm/N_184 ));
+  ram2e_ufm_SLICE_104 \ram2e_ufm/SLICE_104 ( .D1(\FS[11] ), .C1(\FS[10] ), 
+    .B1(\FS[9] ), .A1(\FS[8] ), .B0(\ram2e_ufm/N_595 ), .A0(\FS[12] ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .F1(\ram2e_ufm/N_595 ));
+  ram2e_ufm_SLICE_105 \ram2e_ufm/SLICE_105 ( .D1(\ram2e_ufm/nRWE_s_i_0_63_1 ), 
+    .C1(\S[3] ), .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\ram2e_ufm/N_285_i ), 
+    .C0(\ram2e_ufm/wb_rst16_i ), .B0(\FS[15] ), .A0(\FS[0] ), 
+    .F0(\ram2e_ufm/N_285_i ), .F1(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ));
+  ram2e_ufm_SLICE_106 \ram2e_ufm/SLICE_106 ( .B1(\S[1] ), .A1(\S[0] ), 
+    .D0(\S[2] ), .C0(\RA[10] ), .B0(\ram2e_ufm/S_r_i_0_o2[1] ), 
+    .A0(\ram2e_ufm/N_194 ), .F0(\ram2e_ufm/N_624 ), .F1(\ram2e_ufm/N_194 ));
+  ram2e_ufm_SLICE_107 \ram2e_ufm/SLICE_107 ( .D1(\S[0] ), .C1(\FS[4] ), 
+    .B1(\S[3] ), .A1(\S[2] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[8] ), 
+    .B0(\FS[5] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_659 ), .F1(\ram2e_ufm/N_792 ));
+  ram2e_ufm_SLICE_108 \ram2e_ufm/SLICE_108 ( 
+    .D1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ), .C1(\FS[7] ), 
+    .B1(\FS[5] ), .A1(\FS[4] ), .C0(\ram2e_ufm/wb_req ), 
+    .B0(\ram2e_ufm/N_336 ), .A0(\FS[0] ), 
+    .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), 
+    .F1(\ram2e_ufm/N_336 ));
+  ram2e_ufm_SLICE_109 \ram2e_ufm/SLICE_109 ( .B1(\S[2] ), .A1(\FS[14] ), 
+    .D0(\ram2e_ufm/N_799 ), .C0(\ram2e_ufm/N_634 ), .B0(\ram2e_ufm/N_184 ), 
+    .A0(\FS[11] ), .F0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), 
+    .F1(\ram2e_ufm/N_799 ));
+  ram2e_ufm_SLICE_110 \ram2e_ufm/SLICE_110 ( .D1(\FS[8] ), .C1(\FS[9] ), 
+    .B1(\FS[11] ), .A1(\FS[10] ), .B0(\ram2e_ufm/wb_ack ), 
+    .A0(\ram2e_ufm/N_885 ), 
+    .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), 
+    .F1(\ram2e_ufm/N_885 ));
+  ram2e_ufm_SLICE_111 \ram2e_ufm/SLICE_111 ( .C1(\ram2e_ufm/N_807 ), 
+    .B1(\ram2e_ufm/N_553 ), .A1(\FS[12] ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\ram2e_ufm/N_811 ), 
+    .B0(\FS[13] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_553 ), 
+    .F1(\ram2e_ufm/N_611 ));
+  ram2e_ufm_SLICE_112 \ram2e_ufm/SLICE_112 ( .C1(\S[1] ), .B1(\S[0] ), 
+    .A1(\ram2e_ufm/N_285_i ), .D0(nWE_c), .C0(nEN80_c), .B0(\S[2] ), 
+    .A0(\ram2e_ufm/N_866 ), .F0(\ram2e_ufm/N_616 ), .F1(\ram2e_ufm/N_866 ));
+  ram2e_ufm_SLICE_113 \ram2e_ufm/SLICE_113 ( .C1(nEN80_c), .B1(\S[3] ), 
+    .A1(\S[2] ), .D0(nWE_c), .C0(\S[1] ), .B0(\S[0] ), .A0(\ram2e_ufm/N_804 ), 
+    .F0(\ram2e_ufm/N_628 ), .F1(\ram2e_ufm/N_804 ));
+  ram2e_ufm_SLICE_114 \ram2e_ufm/SLICE_114 ( .C1(\FS[10] ), .B1(\FS[9] ), 
+    .A1(\FS[8] ), .D0(\ram2e_ufm/N_799 ), .C0(\ram2e_ufm/N_241_i ), 
+    .B0(\FS[12] ), .A0(\FS[11] ), .F0(\ram2e_ufm/N_768 ), 
+    .F1(\ram2e_ufm/N_241_i ));
+  ram2e_ufm_SLICE_115 \ram2e_ufm/SLICE_115 ( .B1(\S[2] ), .A1(\S[1] ), 
+    .D0(nEN80_c), .C0(\S[3] ), .B0(\S[0] ), .A0(\ram2e_ufm/N_221 ), 
+    .F0(\ram2e_ufm/CKE_7s2_0_0_0 ), .F1(\ram2e_ufm/N_221 ));
+  ram2e_ufm_SLICE_116 \ram2e_ufm/SLICE_116 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ), 
+    .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .A1(\ram2e_ufm/N_814 ), 
+    .C0(\Din_c[2] ), .B0(\Din_c[1] ), .A0(\Din_c[0] ), .F0(\ram2e_ufm/N_814 ), 
+    .F1(\ram2e_ufm/N_851 ));
+  ram2e_ufm_SLICE_117 \ram2e_ufm/SLICE_117 ( .D1(\S[1] ), .C1(\S[0] ), 
+    .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[0] ), 
+    .A0(\S[3] ), .F0(N_225_i), .F1(\ram2e_ufm/N_643 ));
+  ram2e_ufm_SLICE_118 \ram2e_ufm/SLICE_118 ( .D1(\S[1] ), .C1(\S[0] ), 
+    .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[0] ), 
+    .A0(\S[3] ), .F0(N_201_i), .F1(RC12));
+  ram2e_ufm_SLICE_119 \ram2e_ufm/SLICE_119 ( .D1(\S[2] ), .C1(\S[3] ), 
+    .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), 
+    .A0(\S[0] ), .F0(N_126), .F1(N_185_i));
+  ram2e_ufm_SLICE_120 \ram2e_ufm/SLICE_120 ( .D1(\S[3] ), .C1(\S[0] ), 
+    .B1(\RWBank[0] ), .A1(\FS[15] ), .D0(\S[3] ), .C0(\S[0] ), 
+    .B0(\RWBank[0] ), .A0(\FS[15] ), .F0(N_507_i), .F1(N_508));
+  ram2e_ufm_SLICE_121 \ram2e_ufm/SLICE_121 ( .D1(\S[3] ), .C1(\S[2] ), 
+    .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), 
+    .A0(\S[0] ), .F0(\ram2e_ufm/N_242 ), .F1(Vout3));
+  ram2e_ufm_SLICE_122 \ram2e_ufm/SLICE_122 ( .D1(\FS[4] ), .C1(\FS[3] ), 
+    .B1(\FS[2] ), .A1(\FS[1] ), .D0(\FS[4] ), .C0(\FS[3] ), .B0(\FS[2] ), 
+    .A0(\FS[1] ), .F0(\ram2e_ufm/N_254 ), .F1(\ram2e_ufm/nRWE_s_i_0_63_1 ));
+  ram2e_ufm_SLICE_123 \ram2e_ufm/SLICE_123 ( .C1(\FS[11] ), .B1(\FS[9] ), 
+    .A1(\FS[8] ), .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[10] ), 
+    .F0(\ram2e_ufm/N_849 ), .F1(\ram2e_ufm/N_204 ));
+  ram2e_ufm_SLICE_124 \ram2e_ufm/SLICE_124 ( .D1(\ram2e_ufm/N_784 ), 
+    .C1(\FS[12] ), .B1(\FS[4] ), .A1(\FS[3] ), .D0(\FS[4] ), 
+    .C0(\ram2e_ufm/N_784 ), .B0(\FS[1] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_684 ), 
+    .F1(\ram2e_ufm/RA_35_0_0_0[5] ));
+  ram2e_ufm_SLICE_125 \ram2e_ufm/SLICE_125 ( .D1(\FS[13] ), .C1(\FS[11] ), 
+    .B1(\FS[9] ), .A1(\FS[8] ), .D0(\ram2e_ufm/N_793 ), .C0(\FS[11] ), 
+    .B0(\FS[9] ), .A0(\FS[8] ), .F0(\ram2e_ufm/N_763 ), .F1(\ram2e_ufm/N_565 ));
+  ram2e_ufm_SLICE_126 \ram2e_ufm/SLICE_126 ( .D1(\FS[12] ), .C1(\FS[10] ), 
+    .B1(\FS[9] ), .A1(\FS[8] ), .D0(\ram2e_ufm/N_781 ), .C0(\FS[12] ), 
+    .B0(\FS[10] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_753 ), 
+    .F1(\ram2e_ufm/N_208 ));
+  ram2e_ufm_SLICE_127 \ram2e_ufm/SLICE_127 ( .D1(\S[3] ), .C1(\S[2] ), 
+    .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[0] ), 
+    .A0(\RWBank[7] ), .F0(\ram2e_ufm/N_698 ), .F1(un9_VOEEN_0_a2_0_a3_0_a3));
+  ram2e_ufm_SLICE_128 \ram2e_ufm/SLICE_128 ( .D1(\FS[13] ), .C1(\FS[12] ), 
+    .B1(\FS[11] ), .A1(\FS[10] ), .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ), 
+    .F0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ));
+  ram2e_ufm_SLICE_129 \ram2e_ufm/SLICE_129 ( .D1(\S[0] ), .C1(\RWBank[6] ), 
+    .B1(\ram2e_ufm/N_560 ), .A1(\FS[4] ), .D0(N_551), .C0(\S[0] ), 
+    .B0(\FS[1] ), .A0(\FS[4] ), .F0(\ram2e_ufm/N_627 ), .F1(\BA_4[1] ));
+  ram2e_ufm_SLICE_130 \ram2e_ufm/SLICE_130 ( .B1(\ram2e_ufm/N_185 ), 
+    .A1(RWSel), .D0(\ram2e_ufm/N_185 ), .C0(RWSel), .B0(\ram2e_ufm/N_777 ), 
+    .A0(\ram2e_ufm/CmdExecMXO2 ), .F0(\ram2e_ufm/wb_we_RNO_0 ), .F1(N_187_i));
+  ram2e_ufm_SLICE_131 \ram2e_ufm/SLICE_131 ( .D1(\FS[13] ), .C1(\FS[12] ), 
+    .B1(\FS[3] ), .A1(\FS[1] ), .D0(\ram2e_ufm/N_856 ), .C0(\ram2e_ufm/N_811 ), 
+    .B0(\FS[13] ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_602 ), 
+    .F1(\ram2e_ufm/Ready3_0_a3_5 ));
+  ram2e_ufm_SLICE_132 \ram2e_ufm/SLICE_132 ( .D1(\RA[0] ), 
+    .C1(\ram2e_ufm/N_186 ), .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[0] ), 
+    .D0(\RA[7] ), .C0(\ram2e_ufm/N_186 ), .B0(\ram2e_ufm/N_182 ), 
+    .A0(\Ain_c[7] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[7] ), 
+    .F1(\ram2e_ufm/RA_35_0_0_1[0] ));
+  ram2e_ufm_SLICE_133 \ram2e_ufm/SLICE_133 ( .D1(RWSel), .C1(\Din_c[4] ), 
+    .B1(\Din_c[2] ), .A1(\Din_c[0] ), .C0(\ram2e_ufm/N_338 ), .B0(\Din_c[4] ), 
+    .A0(\Din_c[2] ), .F0(\ram2e_ufm/N_350 ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ));
+  ram2e_ufm_SLICE_134 \ram2e_ufm/SLICE_134 ( .D1(\FS[6] ), .C1(\FS[3] ), 
+    .B1(\FS[2] ), .A1(\FS[1] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[9] ), 
+    .B0(\FS[6] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_679 ), 
+    .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ));
+  ram2e_ufm_SLICE_135 \ram2e_ufm/SLICE_135 ( .B1(\S[3] ), .A1(\S[2] ), 
+    .D0(nEN80_c), .C0(\S[3] ), .B0(\S[2] ), .A0(\ram2e_ufm/S_r_i_0_o2[1] ), 
+    .F0(\ram2e_ufm/N_625 ), .F1(\ram2e_ufm/N_271 ));
+  ram2e_ufm_SLICE_136 \ram2e_ufm/SLICE_136 ( .C1(nWE_c), .B1(nEN80_c), 
+    .A1(\S[3] ), .C0(nWE_c), .B0(nEN80_c), .A0(DOEEN), .F0(nDOE_c), 
+    .F1(\ram2e_ufm/N_226 ));
+  ram2e_ufm_SLICE_137 \ram2e_ufm/SLICE_137 ( .C1(nWE_c), .B1(nEN80_c), 
+    .A1(Ready), .C0(nEN80_c), .B0(Ready), .A0(\ram2e_ufm/LEDEN ), .F0(LED_c), 
+    .F1(RDOE_i));
+  SLICE_138 SLICE_138( .C1(\S[0] ), .B1(\S[1] ), .A1(\S[3] ), .C0(\S[0] ), 
+    .B0(\S[1] ), .A0(\S[2] ), .F0(N_1080_0), .F1(N_1078_0));
+  SLICE_139 SLICE_139( .B1(VOEEN), .A1(PHI1_c), .C0(Ready), .B0(PHI1r), 
+    .A0(PHI1_c), .F0(S_1), .F1(nVOE_c));
+  ram2e_ufm_SLICE_140 \ram2e_ufm/SLICE_140 ( .B1(\RA[2] ), 
+    .A1(\ram2e_ufm/N_186 ), .B0(\RA[5] ), .A0(\ram2e_ufm/N_186 ), 
+    .F0(\ram2e_ufm/N_621 ), .F1(\ram2e_ufm/N_680 ));
+  ram2e_ufm_SLICE_141 \ram2e_ufm/SLICE_141 ( .B1(Ready), .A1(\Din_c[0] ), 
+    .B0(Ready), .A0(\Din_c[3] ), .F0(N_263_i), .F1(N_667));
+  ram2e_ufm_SLICE_142 \ram2e_ufm/SLICE_142 ( .C1(\Din_c[4] ), .B1(\Din_c[7] ), 
+    .A1(\Din_c[0] ), .B0(Ready), .A0(\Din_c[4] ), .F0(N_648), 
+    .F1(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ));
+  ram2e_ufm_SLICE_143 \ram2e_ufm/SLICE_143 ( .B1(Ready), .A1(\Din_c[1] ), 
+    .B0(Ready), .A0(\Din_c[7] ), .F0(N_662), .F1(N_666));
+  ram2e_ufm_SLICE_144 \ram2e_ufm/SLICE_144 ( .B1(Ready), .A1(\Din_c[2] ), 
+    .B0(Ready), .A0(\Din_c[6] ), .F0(N_663), .F1(N_665));
+  ram2e_ufm_SLICE_145 \ram2e_ufm/SLICE_145 ( .D1(\ram2e_ufm/wb_adr[4] ), 
+    .C1(\S[2] ), .B1(\ram2e_ufm/N_873 ), .A1(\ram2e_ufm/N_783 ), .B0(\FS[9] ), 
+    .A0(\FS[8] ), .F0(\ram2e_ufm/N_206 ), .F1(\ram2e_ufm/wb_dati_7_0_0_0[4] ));
+  ram2e_ufm_SLICE_146 \ram2e_ufm/SLICE_146 ( .D1(\RWBank[2] ), 
+    .C1(\ram2e_ufm/N_845 ), .B1(\ram2e_ufm/N_784 ), .A1(\FS[4] ), .D0(\FS[7] ), 
+    .C0(\FS[6] ), .B0(\FS[5] ), .A0(\FS[0] ), .F0(\ram2e_ufm/Ready3_0_a3_3 ), 
+    .F1(\ram2e_ufm/RA_35_0_0_0[9] ));
+  ram2e_ufm_SLICE_147 \ram2e_ufm/SLICE_147 ( .D1(\ram2e_ufm/LEDEN ), 
+    .C1(CmdSetRWBankFFLED), .B1(\ram2e_ufm/CmdSetRWBankFFChip ), 
+    .A1(CmdLEDGet), .B0(Ready), .A0(\Din_c[5] ), .F0(N_664), 
+    .F1(\ram2e_ufm/N_188 ));
+  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(N_667), 
     .RD0(RD[0]));
   LED LED_I( .PADDO(LED_c), .LED(LED));
   C14M C14M_I( .PADDI(C14M_c), .C14M(C14M));
-  DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH));
-  DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_358_i), .CLK(C14M_c));
-  DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML));
-  DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_28_i), .CLK(C14M_c));
-  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(\Din_c[7] ), 
+  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(N_662), 
     .RD7(RD[7]));
-  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(\Din_c[6] ), 
+  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(N_663), 
     .RD6(RD[6]));
-  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(\Din_c[5] ), 
+  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(N_664), 
     .RD5(RD[5]));
-  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(\Din_c[4] ), 
+  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(N_648), 
     .RD4(RD[4]));
-  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(\Din_c[3] ), 
+  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(N_263_i), 
     .RD3(RD[3]));
-  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(\Din_c[2] ), 
+  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(N_665), 
     .RD2(RD[2]));
-  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(\Din_c[1] ), 
+  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(N_666), 
     .RD1(RD[1]));
-  RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11]));
-  RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(\RA_42[11] ), 
+  DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH));
+  DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_508), .CE(N_201_i), 
     .CLK(C14M_c));
-  RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10]));
-  RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(\RA_42[10] ), 
+  DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML));
+  DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_507_i), .CE(N_201_i), 
+    .CLK(C14M_c));
+  RAout_11_ \RAout[11]_I ( .IOLDO(\RAout_c[11] ), .RAout11(RAout[11]));
+  RAout_11__MGIOL \RAout[11]_MGIOL ( .IOLDO(\RAout_c[11] ), .OPOS(\RA[11] ), 
+    .CLK(C14M_c));
+  RAout_10_ \RAout[10]_I ( .IOLDO(\RAout_c[10] ), .RAout10(RAout[10]));
+  RAout_10__MGIOL \RAout[10]_MGIOL ( .IOLDO(\RAout_c[10] ), .OPOS(\RA[10] ), 
+    .CLK(C14M_c));
+  RAout_9_ \RAout[9]_I ( .IOLDO(\RAout_c[9] ), .RAout9(RAout[9]));
+  RAout_9__MGIOL \RAout[9]_MGIOL ( .IOLDO(\RAout_c[9] ), .OPOS(\RA[9] ), 
+    .CLK(C14M_c));
+  RAout_8_ \RAout[8]_I ( .IOLDO(\RAout_c[8] ), .RAout8(RAout[8]));
+  RAout_8__MGIOL \RAout[8]_MGIOL ( .IOLDO(\RAout_c[8] ), .OPOS(\RA[8] ), 
+    .CLK(C14M_c));
+  RAout_7_ \RAout[7]_I ( .IOLDO(\RAout_c[7] ), .RAout7(RAout[7]));
+  RAout_7__MGIOL \RAout[7]_MGIOL ( .IOLDO(\RAout_c[7] ), .OPOS(\RA[7] ), 
+    .CLK(C14M_c));
+  RAout_6_ \RAout[6]_I ( .IOLDO(\RAout_c[6] ), .RAout6(RAout[6]));
+  RAout_6__MGIOL \RAout[6]_MGIOL ( .IOLDO(\RAout_c[6] ), .OPOS(\RA[6] ), 
+    .CLK(C14M_c));
+  RAout_5_ \RAout[5]_I ( .IOLDO(\RAout_c[5] ), .RAout5(RAout[5]));
+  RAout_5__MGIOL \RAout[5]_MGIOL ( .IOLDO(\RAout_c[5] ), .OPOS(\RA[5] ), 
+    .CLK(C14M_c));
+  RAout_4_ \RAout[4]_I ( .IOLDO(\RAout_c[4] ), .RAout4(RAout[4]));
+  RAout_4__MGIOL \RAout[4]_MGIOL ( .IOLDO(\RAout_c[4] ), .OPOS(\RA[4] ), 
+    .CLK(C14M_c));
+  RAout_3_ \RAout[3]_I ( .IOLDO(\RAout_c[3] ), .RAout3(RAout[3]));
+  RAout_3__MGIOL \RAout[3]_MGIOL ( .IOLDO(\RAout_c[3] ), .OPOS(\RA[3] ), 
+    .CLK(C14M_c));
+  RAout_2_ \RAout[2]_I ( .IOLDO(\RAout_c[2] ), .RAout2(RAout[2]));
+  RAout_2__MGIOL \RAout[2]_MGIOL ( .IOLDO(\RAout_c[2] ), .OPOS(\RA[2] ), 
+    .CLK(C14M_c));
+  RAout_1_ \RAout[1]_I ( .IOLDO(\RAout_c[1] ), .RAout1(RAout[1]));
+  RAout_1__MGIOL \RAout[1]_MGIOL ( .IOLDO(\RAout_c[1] ), .OPOS(\RA[1] ), 
+    .CLK(C14M_c));
+  RAout_0_ \RAout[0]_I ( .IOLDO(\RAout_c[0] ), .RAout0(RAout[0]));
+  RAout_0__MGIOL \RAout[0]_MGIOL ( .IOLDO(\RAout_c[0] ), .OPOS(\RA[0] ), 
     .CLK(C14M_c));
-  RA_9_ \RA[9]_I ( .IOLDO(\RA_c[9] ), .RA9(RA[9]));
-  RA_9__MGIOL \RA[9]_MGIOL ( .IOLDO(\RA_c[9] ), .OPOS(N_59_i), .CLK(C14M_c));
-  RA_8_ \RA[8]_I ( .IOLDO(\RA_c[8] ), .RA8(RA[8]));
-  RA_8__MGIOL \RA[8]_MGIOL ( .IOLDO(\RA_c[8] ), .OPOS(N_49_i), .CLK(C14M_c));
-  RA_7_ \RA[7]_I ( .IOLDO(\RA_c[7] ), .RA7(RA[7]));
-  RA_7__MGIOL \RA[7]_MGIOL ( .IOLDO(\RA_c[7] ), .OPOS(N_549_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_6_ \RA[6]_I ( .IOLDO(\RA_c[6] ), .RA6(RA[6]));
-  RA_6__MGIOL \RA[6]_MGIOL ( .IOLDO(\RA_c[6] ), .OPOS(N_550_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_5_ \RA[5]_I ( .IOLDO(\RA_c[5] ), .RA5(RA[5]));
-  RA_5__MGIOL \RA[5]_MGIOL ( .IOLDO(\RA_c[5] ), .OPOS(\RA_42_3_0[5] ), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_4_ \RA[4]_I ( .IOLDO(\RA_c[4] ), .RA4(RA[4]));
-  RA_4__MGIOL \RA[4]_MGIOL ( .IOLDO(\RA_c[4] ), .OPOS(N_551_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
-  RA_2_ \RA[2]_I ( .IOLDO(\RA_c[2] ), .RA2(RA[2]));
-  RA_2__MGIOL \RA[2]_MGIOL ( .IOLDO(\RA_c[2] ), .OPOS(N_553_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_1_ \RA[1]_I ( .IOLDO(\RA_c[1] ), .RA1(RA[1]));
-  RA_1__MGIOL \RA[1]_MGIOL ( .IOLDO(\RA_c[1] ), .OPOS(N_558_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
   BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1]));
-  BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), 
-    .LSR(N_566_i), .CLK(C14M_c));
+  BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), .CE(N_225_i), 
+    .LSR(BA_0_sqmuxa), .CLK(C14M_c));
   BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0]));
-  BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), 
-    .LSR(N_566_i), .CLK(C14M_c));
-  nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE));
-  nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(nRWE_r_0), .CLK(C14M_c));
-  nCAS nCAS_I( .IOLDO(nCAS_c), .nCAS(nCAS));
-  nCAS_MGIOL nCAS_MGIOL( .IOLDO(nCAS_c), .OPOS(N_561_i), .CLK(C14M_c));
-  nRAS nRAS_I( .IOLDO(nRAS_c), .nRAS(nRAS));
-  nRAS_MGIOL nRAS_MGIOL( .IOLDO(nRAS_c), .OPOS(nRAS_2_iv_i), .CLK(C14M_c));
-  nCS nCS_I( .IOLDO(nCS_c), .nCS(nCS));
-  nCS_MGIOL nCS_MGIOL( .IOLDO(nCS_c), .OPOS(N_559_i), .CLK(C14M_c));
-  CKE CKE_I( .IOLDO(CKE_c), .CKE(CKE));
-  CKE_MGIOL CKE_MGIOL( .IOLDO(CKE_c), .OPOS(CKE_6_iv_i_0), .CLK(C14M_c));
-  nVOE nVOE_I( .PADDO(PHI1_c), .nVOE(nVOE));
+  BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), .CE(N_225_i), 
+    .LSR(BA_0_sqmuxa), .CLK(C14M_c));
+  nRWEout nRWEout_I( .IOLDO(nRWEout_c), .nRWEout(nRWEout));
+  nRWEout_MGIOL nRWEout_MGIOL( .IOLDO(nRWEout_c), .OPOS(nRWE), .CLK(C14M_c));
+  nCASout nCASout_I( .IOLDO(nCASout_c), .nCASout(nCASout));
+  nCASout_MGIOL nCASout_MGIOL( .IOLDO(nCASout_c), .OPOS(nCAS), .CLK(C14M_c));
+  nRASout nRASout_I( .IOLDO(nRASout_c), .nRASout(nRASout));
+  nRASout_MGIOL nRASout_MGIOL( .IOLDO(nRASout_c), .OPOS(nRAS), .CLK(C14M_c));
+  nCSout nCSout_I( .PADDO(GND), .nCSout(nCSout));
+  CKEout CKEout_I( .IOLDO(CKEout_c), .CKEout(CKEout));
+  CKEout_MGIOL CKEout_MGIOL( .IOLDO(CKEout_c), .OPOS(CKE), .CLK(C14M_c));
+  nVOE nVOE_I( .PADDO(nVOE_c), .nVOE(nVOE));
   Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7]));
   Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), 
     .CE(Vout3), .CLK(C14M_c));
@@ -572,30 +890,14 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), 
     .CE(Vout3), .CLK(C14M_c));
   nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE));
-  Dout_7_ \Dout[7]_I ( .IOLDO(\Dout_c[7] ), .Dout7(Dout[7]));
-  Dout_7__MGIOL \Dout[7]_MGIOL ( .IOLDO(\Dout_c[7] ), .OPOS(\RD_in[7] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_6_ \Dout[6]_I ( .IOLDO(\Dout_c[6] ), .Dout6(Dout[6]));
-  Dout_6__MGIOL \Dout[6]_MGIOL ( .IOLDO(\Dout_c[6] ), .OPOS(\RD_in[6] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_5_ \Dout[5]_I ( .IOLDO(\Dout_c[5] ), .Dout5(Dout[5]));
-  Dout_5__MGIOL \Dout[5]_MGIOL ( .IOLDO(\Dout_c[5] ), .OPOS(\RD_in[5] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_4_ \Dout[4]_I ( .IOLDO(\Dout_c[4] ), .Dout4(Dout[4]));
-  Dout_4__MGIOL \Dout[4]_MGIOL ( .IOLDO(\Dout_c[4] ), .OPOS(\RD_in[4] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_3_ \Dout[3]_I ( .IOLDO(\Dout_c[3] ), .Dout3(Dout[3]));
-  Dout_3__MGIOL \Dout[3]_MGIOL ( .IOLDO(\Dout_c[3] ), .OPOS(\RD_in[3] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_2_ \Dout[2]_I ( .IOLDO(\Dout_c[2] ), .Dout2(Dout[2]));
-  Dout_2__MGIOL \Dout[2]_MGIOL ( .IOLDO(\Dout_c[2] ), .OPOS(\RD_in[2] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_1_ \Dout[1]_I ( .IOLDO(\Dout_c[1] ), .Dout1(Dout[1]));
-  Dout_1__MGIOL \Dout[1]_MGIOL ( .IOLDO(\Dout_c[1] ), .OPOS(\RD_in[1] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_0_ \Dout[0]_I ( .IOLDO(\Dout_c[0] ), .Dout0(Dout[0]));
-  Dout_0__MGIOL \Dout[0]_MGIOL ( .IOLDO(\Dout_c[0] ), .OPOS(\RD_in[0] ), 
-    .CE(N_576_i), .CLK(C14M_c));
+  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
+  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
+  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
+  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
+  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
+  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
+  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
+  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
   Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
   Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
   Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
@@ -614,21 +916,25 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0]));
   nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X));
   nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80));
-  nWE80 nWE80_I( .PADDI(nWE80_c), .nWE80(nWE80));
   nWE nWE_I( .PADDI(nWE_c), .nWE(nWE));
   PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1));
-  PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1reg));
-  ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), .WBRSTI(wb_rst), 
-    .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), 
-    .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), 
-    .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), 
-    .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), 
-    .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), 
-    .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), 
-    .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), 
-    .WBDATO2(\wb_dato[2] ), .WBDATO3(\wb_dato[3] ), .WBDATO4(\wb_dato[4] ), 
-    .WBDATO5(\wb_dato[5] ), .WBDATO6(\wb_dato[6] ), .WBDATO7(\wb_dato[7] ), 
-    .WBACKO(wb_ack));
+  PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1r));
+  ram2e_ufm_ufmefb_EFBInst_0 \ram2e_ufm/ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), 
+    .WBRSTI(\ram2e_ufm/wb_rst ), .WBCYCI(\ram2e_ufm/wb_cyc_stb ), 
+    .WBSTBI(\ram2e_ufm/wb_cyc_stb ), .WBWEI(\ram2e_ufm/wb_we ), 
+    .WBADRI0(\ram2e_ufm/wb_adr[0] ), .WBADRI1(\ram2e_ufm/wb_adr[1] ), 
+    .WBADRI2(\ram2e_ufm/wb_adr[2] ), .WBADRI3(\ram2e_ufm/wb_adr[3] ), 
+    .WBADRI4(\ram2e_ufm/wb_adr[4] ), .WBADRI5(\ram2e_ufm/wb_adr[5] ), 
+    .WBADRI6(\ram2e_ufm/wb_adr[6] ), .WBADRI7(\ram2e_ufm/wb_adr[7] ), 
+    .WBDATI0(\ram2e_ufm/wb_dati[0] ), .WBDATI1(\ram2e_ufm/wb_dati[1] ), 
+    .WBDATI2(\ram2e_ufm/wb_dati[2] ), .WBDATI3(\ram2e_ufm/wb_dati[3] ), 
+    .WBDATI4(\ram2e_ufm/wb_dati[4] ), .WBDATI5(\ram2e_ufm/wb_dati[5] ), 
+    .WBDATI6(\ram2e_ufm/wb_dati[6] ), .WBDATI7(\ram2e_ufm/wb_dati[7] ), 
+    .WBDATO0(\ram2e_ufm/wb_dato[0] ), .WBDATO1(\ram2e_ufm/wb_dato[1] ), 
+    .WBDATO2(\ram2e_ufm/wb_dato[2] ), .WBDATO3(\ram2e_ufm/wb_dato[3] ), 
+    .WBDATO4(\ram2e_ufm/wb_dato[4] ), .WBDATO5(\ram2e_ufm/wb_dato[5] ), 
+    .WBDATO6(\ram2e_ufm/wb_dato[6] ), .WBDATO7(\ram2e_ufm/wb_dato[7] ), 
+    .WBACKO(\ram2e_ufm/wb_ack ));
   VHI VHI_INST( .Z(VCCI));
   PUR PUR_INST( .PUR(VCCI));
   GSR GSR_INST( .GSR(VCCI));
@@ -939,20 +1245,62 @@ module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
 
 endmodule
 
-module SLICE_9 ( input C1, B1, A1, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
+module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut4 \ram2e_ufm/wb_req_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40003 \ram2e_ufm/CKE_7_RNIS77M1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0004 CKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut4 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40003 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAAAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_10 ( input B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut4 S_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40005 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40003 \CmdTout_3_0_a2[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  lut40006 \ram2e_ufm/CmdTout_3_0_a3_0_a3[0] ( .A(A0), .B(B0), .C(GNDI), 
+    .D(GNDI), .Z(F0));
   vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
@@ -964,27 +1312,59 @@ module SLICE_9 ( input C1, B1, A1, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
 
 endmodule
 
-module lut4 ( input A, B, C, D, output Z );
+module lut40005 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40003 ( input A, B, C, D, output Z );
+module lut40006 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly;
+module SLICE_11 ( input B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40004 \CS_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40005 \CS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40006 \ram2e_ufm/RC_3_0_0_a3_1[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre0006 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
+  lut40007 \ram2e_ufm/N_360_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \RC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40007 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_12 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly;
+
+  lut40008 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNI6S1P8 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40009 \ram2e_ufm/S_r_i_0_o2_RNIVM0LF[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0010 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre0006 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+  vmuxregsre0010 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
 
   specify
@@ -992,6 +1372,7 @@ module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK,
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1008,37 +1389,40 @@ module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK,
 
 endmodule
 
-module lut40004 ( input A, B, C, D, output Z );
+module lut40008 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hA9AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40005 ( input A, B, C, D, output Z );
+module lut40009 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h00F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q );
+module vmuxregsre0010 ( input D0, D1, SD, SP, CK, LSR, output Q );
 
   FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module SLICE_11 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
+module SLICE_13 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
 
-  lut40007 \CS_RNO_0[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40008 \CS_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0006 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+  lut40011 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 ( .A(A1), 
+    .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40012 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0010 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1053,138 +1437,34 @@ module SLICE_11 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0,
 
 endmodule
 
-module lut40007 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40008 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h6C6C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_12 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40009 CmdBitbangMXO2_4_u_0_0_a2_0_1( .A(A1), .B(B1), .C(C1), .D(GNDI), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40010 CmdBitbangMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdBitbangMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40009 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40010 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_13 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40011 un1_CS_0_sqmuxa_0_0_a2_7( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40010 CmdExecMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdExecMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
 module lut40011 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40012 CmdLEDGet_4_u_0_0_a2_0_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40010 CmdLEDGet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hA2A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40012 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hC4C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_15 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
+module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
     Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40013 CmdLEDSet_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40014 CmdLEDSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40013 \ram2e_ufm/CmdLEDGet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40014 \ram2e_ufm/CmdLEDGet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1199,23 +1479,24 @@ endmodule
 
 module lut40013 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40014 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_16 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
+module SLICE_15 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
     Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40007 CmdBitbangMXO2_4_u_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(GNDI), 
-    .Z(F1));
+  lut40013 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40010 CmdRWMaskSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40015 \ram2e_ufm/CmdLEDSet_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
@@ -1236,24 +1517,30 @@ module SLICE_16 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
-module SLICE_17 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+module lut40015 ( input A, B, C, D, output Z );
 
-  lut40015 CmdSetRWBankFFLED_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), 
-    .Z(F1));
-  lut40014 CmdSetRWBankFFLED_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_16 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40017 \ram2e_ufm/CmdRWMaskSet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
-    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1266,21 +1553,26 @@ module SLICE_17 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40015 ( input A, B, C, D, output Z );
+module lut40016 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_18 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
+module lut40017 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_17 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
     Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40011 CmdSetRWBankFFLED_4_u_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+  lut40018 \ram2e_ufm/CmdRWMaskSet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
     .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40010 CmdSetRWBankFFMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
-  vmuxregsre CmdSetRWBankFFMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+  lut40019 \ram2e_ufm/CmdSetRWBankFFLED_4_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
     .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
@@ -1301,12 +1593,22 @@ module SLICE_18 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
-module SLICE_19 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output 
+module lut40018 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40019 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output 
     F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40016 \CmdTout_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40017 \CmdTout_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40020 \ram2e_ufm/N_369_i ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40021 \ram2e_ufm/N_368_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
   vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
@@ -1333,26 +1635,65 @@ module SLICE_19 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output
 
 endmodule
 
-module lut40016 ( input A, B, C, D, output Z );
+module lut40020 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h006A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0078) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40017 ( input A, B, C, D, output Z );
+module lut40021 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h0606) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+module SLICE_19 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, M0_dly, CLK_dly, LSR_dly;
 
-  lut40018 \S_RNII9DO1_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40019 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre DOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  lut40022 \ram2e_ufm/SUM0_i_o2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/RA_35_i_i_0_a3_0[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre0010 DOEEN( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40022 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40023 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40024 \ram2e_ufm/RA_35_i_i_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40025 \ram2e_ufm/RA_35_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \RA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -1364,42 +1705,8 @@ module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40018 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40019 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hA888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_21 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40020 \RA_0io_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40021 LEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
     $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
@@ -1408,30 +1715,68 @@ module SLICE_21 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
 
 endmodule
 
-module lut40020 ( input A, B, C, D, output Z );
+module lut40024 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40021 ( input A, B, C, D, output Z );
+module lut40025 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hECFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_22 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
+module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40020 \RA_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40026 \ram2e_ufm/RA_35_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40020 \RA_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40024 \ram2e_ufm/RA_35_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
   vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40026 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_22 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40024 \ram2e_ufm/RA_35_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40026 \ram2e_ufm/RA_35_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \RA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -1453,9 +1798,160 @@ module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40014 \RWBank_5_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40026 \ram2e_ufm/RA_35_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40014 \RWBank_5_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40026 \ram2e_ufm/RA_35_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre \RA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40026 \ram2e_ufm/RA_35_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40027 \ram2e_ufm/un2_S_2_i_0_0_o3_RNIHFHN3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre \RA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40027 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_25 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40028 \ram2e_ufm/RA_35_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut4 \ram2e_ufm/RA_35_2_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \RA[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \RA[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40028 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_26 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40029 \ram2e_ufm/RC_3_0_0[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40030 \ram2e_ufm/RC_3_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \RC[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RC[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40029 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h3838) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40030 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4646) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_27 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40031 \ram2e_ufm/RWBank_3_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40031 \ram2e_ufm/RWBank_3_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
   vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1480,13 +1976,18 @@ module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module SLICE_24 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+module lut40031 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_28 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40014 \RWBank_5_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40031 \ram2e_ufm/RWBank_3_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40014 \RWBank_5_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40031 \ram2e_ufm/RWBank_3_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
   vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1511,13 +2012,14 @@ module SLICE_24 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module SLICE_25 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40014 \RWBank_5_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40031 \ram2e_ufm/RWBank_3_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40014 \RWBank_5_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40031 \ram2e_ufm/RWBank_3_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
   vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1542,13 +2044,13 @@ module SLICE_25 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module SLICE_26 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40022 \RWBank_5_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40032 \ram2e_ufm/RWBank_3_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40014 \RWBank_5_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40031 \ram2e_ufm/RWBank_3_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
   vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1573,152 +2075,25 @@ module SLICE_26 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40022 ( input A, B, C, D, output Z );
+module lut40032 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_27 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40023 \RWMask_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 \RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40023 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h7474) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_28 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40023 \RWMask_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 \RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40023 \RWMask_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 \RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40021 \RWMask_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 \RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40024 nDOE_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40025 RWSel_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40033 \ram2e_ufm/RA_35_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40034 \ram2e_ufm/RWSel_2_0_a3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
   vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -1735,12 +2110,12 @@ module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40024 ( input A, B, C, D, output Z );
+module lut40033 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40025 ( input A, B, C, D, output Z );
+module lut40034 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
@@ -1748,8 +2123,8 @@ endmodule
 module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly;
 
-  lut40026 Ready_0_sqmuxa_0_a2_6_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40027 Ready_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  lut40035 \ram2e_ufm/Ready3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40036 Ready_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
   vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
@@ -1770,12 +2145,12 @@ module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
 
 endmodule
 
-module lut40026 ( input A, B, C, D, output Z );
+module lut40035 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40027 ( input A, B, C, D, output Z );
+module lut40036 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
@@ -1784,8 +2159,9 @@ module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
     F0, Q0, F1, Q1 );
   wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
 
-  lut40028 \S_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40029 \S_s_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40037 \ram2e_ufm/S_r_i_0_o2_0_RNI36E21[1] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40038 \ram2e_ufm/S_s_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
   vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1812,22 +2188,24 @@ module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
 
 endmodule
 
-module lut40028 ( input A, B, C, D, output Z );
+module lut40037 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h5100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40029 ( input A, B, C, D, output Z );
+module lut40038 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFBA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFBFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output 
     F0, Q0, F1, Q1 );
   wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
 
-  lut40030 \S_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40031 \S_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40039 \ram2e_ufm/S_r_i_0_o2_RNIFNP81_0[2] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40040 \ram2e_ufm/S_r_i_0_o2_RNIFNP81[2] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
   vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1854,354 +2232,62 @@ module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
 
 endmodule
 
-module lut40030 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5510) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40031 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40032 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40032 \wb_adr_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40032 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_36 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40033 \wb_adr_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40033 \wb_adr_RNO[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40033 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_37 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40034 \wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40034 \wb_adr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40034 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_38 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40033 \wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40034 \wb_adr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_39 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40035 wb_cyc_stb_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40022 wb_cyc_stb_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40035 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h000E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40036 \wb_dati_7_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40037 \wb_dati_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40036 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40037 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_41 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40038 \wb_dati_7_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40036 \wb_dati_7_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40038 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40036 \wb_dati_7_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 \wb_dati_7_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
 module lut40039 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_43 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40039 \wb_dati_7_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40040 \wb_dati_7_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0B0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40040 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_44 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output 
-    F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
+module SLICE_35 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
 
-  lut40011 wb_req_RNO_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40016 \ram2e_ufm/CKE_7_m1_0_0_o2_RNICM8E1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40036 \ram2e_ufm/CKE_7_m1_0_0_o2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40041 wb_req_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0006 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre0010 VOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40041 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40042 \ram2e_ufm/nCAS_s_i_0_a3_RNIO1UQ3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0004 nCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -2211,10 +2297,6 @@ module SLICE_44 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge LSR, 0:0:0);
-    $width (negedge LSR, 0:0:0);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
@@ -2223,43 +2305,93 @@ endmodule
 
 module lut40041 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_45 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
+module lut40042 ( input A, B, C, D, output Z );
 
-  lut40027 \un1_LEDEN13_2_i_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40003 wb_rst8_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre0006 wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  ROM16X1A #(16'h1101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40034 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40016 \ram2e_ufm/nRAS_s_i_0_0_RNI0PC64 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0004 nRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge LSR, 0:0:0);
-    $width (negedge LSR, 0:0:0);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
-module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
+module SLICE_38 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40043 \ram2e_ufm/nRAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40044 \ram2e_ufm/nRAS_s_i_0_a3_0_RNIIR094 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre0004 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40043 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40044 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_39 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
   wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40042 wb_we_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40043 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  lut40045 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40019 \ram2e_ufm/CmdBitbangMXO2_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/CmdBitbangMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
 
@@ -2281,122 +2413,254 @@ module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
 
 endmodule
 
-module lut40042 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40043 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40044 DQMH_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 \S_RNII9DO1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40044 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40045 Vout3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40046 nCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
 module lut40045 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_40 ( input D1, C1, B1, A1, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40014 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40023 \ram2e_ufm/CmdExecMXO2_3_0_a3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/CmdExecMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40046 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0_0 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40014 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/CmdSetRWBankFFChip ( .D0(VCCI), .D1(DI0_dly), 
+    .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40046 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_42 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40015 un1_CS_0_sqmuxa_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40047 un1_CS_0_sqmuxa_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40047 \ram2e_ufm/SUM1_0_o3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40048 \ram2e_ufm/LEDEN_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/LEDEN ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40047 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40048 \wb_dati_7_0_a2_0_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40049 \wb_dati_7_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40048 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0D00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_43 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40049 \ram2e_ufm/RWMask_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 \ram2e_ufm/RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40049 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7474) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_44 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40050 CKE_6_iv_i_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40051 CKE_6_iv_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40049 \ram2e_ufm/RWMask_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 \ram2e_ufm/RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_45 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40049 \ram2e_ufm/RWMask_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 \ram2e_ufm/RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_46 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40048 \ram2e_ufm/RWMask_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 \ram2e_ufm/RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40050 \ram2e_ufm/wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40024 \ram2e_ufm/wb_adr_7_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2407,53 +2671,174 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40050 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2F2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_48 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40023 \ram2e_ufm/wb_adr_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/wb_adr_RNO[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_49 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40051 \ram2e_ufm/wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40051 \ram2e_ufm/wb_adr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40051 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_50 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40052 \un1_LEDEN13_2_i_a2_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40053 \un1_LEDEN13_2_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40023 \ram2e_ufm/wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40051 \ram2e_ufm/wb_adr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_51 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40052 \ram2e_ufm/wb_cyc_stb_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40053 \ram2e_ufm/wb_cyc_stb_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_cyc_stb ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40052 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40053 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40054 \un1_wb_adr_0_sqmuxa_2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+  lut40054 \ram2e_ufm/wb_dati_7_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
     .Z(F1));
-  lut40055 wb_we_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40055 \ram2e_ufm/wb_dati_7_0_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2464,24 +2849,41 @@ module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40054 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3FF5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40055 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40056 un1_CS_0_sqmuxa_0_0_a2_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40057 un1_CS_0_sqmuxa_0_0_o2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40054 \ram2e_ufm/wb_dati_7_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40054 \ram2e_ufm/wb_dati_7_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2492,24 +2894,161 @@ module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40054 \ram2e_ufm/wb_dati_7_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut4 \ram2e_ufm/wb_dati_7_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut4 \ram2e_ufm/wb_dati_7_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40054 \ram2e_ufm/wb_dati_7_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, 
+    CLK, output F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
+
+  lut4 \ram2e_ufm/wb_reqc_1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40056 \ram2e_ufm/wb_req_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0010 \ram2e_ufm/wb_req ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40056 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40057 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_57 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40035 \ram2e_ufm/Ready3_0_a3_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40006 \ram2e_ufm/wb_rst8_0_a3_0_a3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre0010 \ram2e_ufm/wb_rst ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
 
-  ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40058 nCS_6_u_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40018 un1_nCS61_1_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40057 \ram2e_ufm/wb_we_RNO_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40057 \ram2e_ufm/wb_we_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_we ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2520,98 +3059,154 @@ module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40057 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SUM0_i_m3_0_SLICE_59 ( input C1, B1, A1, C0, B0, A0, M0, 
+    output OFX0 );
+  wire   GNDI, 
+         \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 , 
+         \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ;
+
+  lut40058 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), 
+    .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40059 \ram2e_ufm/SUM0_i_m3_0/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ));
+  selmux2 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K0K1MUX ( 
+    .D0(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ), 
+    .D1(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ), 
+    .SD(M0), .Z(OFX0));
+
+  specify
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40058 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFF1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_56 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40059 \wb_dati_7_0_a2_5[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40060 \wb_dati_7_0_a2_6[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40059 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module selmux2 ( input D0, D1, SD, output Z );
+
+  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
+endmodule
+
+module ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 ( input D1, C1, B1, A1, C0, B0, 
+    A0, M0, output OFX0 );
+  wire   
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 
+         , GNDI, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 
+         ;
+
+  lut40060 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), 
+    .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 )
+    );
+  lut40061 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE ( .A(A0), .B(B0), .C(C0), 
+    .D(GNDI), 
+    .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 )
+    );
+  gnd DRIVEGND( .PWR0(GNDI));
+  selmux2 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K0K1MUX ( 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 )
+    , 
+    .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 )
+    , .SD(M0), .Z(OFX0));
+
+  specify
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40060 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40061 \un1_LEDEN13_2_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40062 \S_RNII9DO1_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h55D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40061 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40062 ( input A, B, C, D, output Z );
+module ram2e_ufm_CKE_7_SLICE_61 ( input C1, B1, A1, C0, B0, A0, M0, output 
+    OFX0 );
+  wire   GNDI, \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 , 
+         \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ;
 
-  ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40063 \wb_dati_7_0_2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40025 \wb_dati_7_0_2_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40062 \ram2e_ufm/CKE_7/SLICE_61_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40063 \ram2e_ufm/CKE_7/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ));
+  selmux2 \ram2e_ufm/CKE_7/SLICE_61_K0K1MUX ( 
+    .D0(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ), 
+    .D1(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ), .SD(M0), 
+    .Z(OFX0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module lut40063 ( input A, B, C, D, output Z );
+module lut40062 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h4440) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5D5D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40063 ( input A, B, C, D, output Z );
 
-  lut40064 DQML_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40065 DQML_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40043 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIAJ811 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40064 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIPG3P2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2628,26 +3223,23 @@ endmodule
 
 module lut40064 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h7377) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40065 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_60 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40066 \wb_adr_RNO_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40009 \wb_adr_RNO_3[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40065 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40066 \ram2e_ufm/S_r_i_0_o2_RNI3VQTC[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -2655,17 +3247,24 @@ module SLICE_60 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40066 ( input A, B, C, D, output Z );
+module lut40065 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2A20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_61 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40066 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40011 \wb_dati_7_0_a2_2_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40067 \ram2e_ufm/wb_adr_7_i_i_a3_6[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40067 \FS_RNIOD6E_1[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40068 \ram2e_ufm/wb_adr_7_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
@@ -2681,50 +3280,27 @@ endmodule
 
 module lut40067 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_62 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40068 \wb_adr_RNO_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40069 \wb_adr_RNO_2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40068 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40069 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'h9595) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40039 \un1_LEDEN13_2_i_o2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40038 \FS_RNI9FGA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40069 \ram2e_ufm/SUM0_i_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40065 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -2732,15 +3308,21 @@ module SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module lut40069 ( input A, B, C, D, output Z );
 
-  lut40070 \FS_RNI6JJA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40013 \un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
+  ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40070 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40071 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -2754,59 +3336,23 @@ endmodule
 
 module lut40070 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_65 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40007 \wb_dati_7_0_a2_0_0[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40026 \wb_dati_7_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_66 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40003 \FS_RNIJ9MH[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40071 wb_we_RNO_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40071 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF5F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_67 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40027 wb_reqc_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  lut40072 \ram2e_ufm/nRAS_s_i_0_m3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40072 wb_reqc_1_RNIRU4M1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40073 \ram2e_ufm/nRAS_s_i_0_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -2819,36 +3365,21 @@ endmodule
 
 module lut40072 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40073 \wb_dati_7_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40015 \FS_RNIOD6E_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40073 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFF6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40074 \RA_42_0[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40075 \RA_42_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40074 \ram2e_ufm/wb_adr_7_i_i_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40075 \ram2e_ufm/wb_adr_7_i_i_3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2865,18 +3396,19 @@ endmodule
 
 module lut40074 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40075 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0208) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h01A1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40063 \wb_dati_7_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40076 \FS_RNIOD6E[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40076 \ram2e_ufm/nCAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut4 \ram2e_ufm/wb_rst16_i_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2893,16 +3425,19 @@ endmodule
 
 module lut40076 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h4888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_70 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40077 nRWE_r_0_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40018 \S_RNII9DO1_3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40077 \ram2e_ufm/wb_dati_7_0_0_a3_12[7] ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40078 \ram2e_ufm/wb_dati_7_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -2916,120 +3451,27 @@ endmodule
 
 module lut40077 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40026 Ready_0_sqmuxa_0_a2_6_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40025 \FS_RNI5OOF1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40078 \wb_adr_7_0_a2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40067 \FS_RNIK5632[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40078 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_71 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut4 \wb_dati_7_0_a2_5[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40013 \ram2e_ufm/RA_35_0_0_a3_4[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40026 \wb_dati_7_0_a2_5_RNIC22J[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40079 \ram2e_ufm/nRAS_s_i_0_a3_4 ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
     .Z(F0));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_75 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40015 nCS_6_u_i_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut4 nCS_6_u_i_a2_4_RNI3A062( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40027 nCS_6_u_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40065 nCS_6_u_i_a2_4_RNICJKD2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40009 un1_CS_0_sqmuxa_0_0_a2_10( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40079 un1_CS_0_sqmuxa_0_0_2_RNIQS7F( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -3039,20 +3481,22 @@ endmodule
 
 module lut40079 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0103) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40027 nCAS_s_i_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  lut40080 \ram2e_ufm/BA_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40047 \ram2e_ufm/un1_RC12_i_0_o3 ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40080 nCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -3062,21 +3506,24 @@ endmodule
 
 module lut40080 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hC0D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_79 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40081 nCS_6_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40003 nCS_0io_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40081 \ram2e_ufm/wb_dati_7_0_0_o3_0[2] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40082 \ram2e_ufm/wb_dati_7_0_0_a3_3[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
@@ -3085,44 +3532,24 @@ endmodule
 
 module lut40081 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0212) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_80 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40082 nRAS_2_iv_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40083 nRAS_2_iv_i( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40082 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1212) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40083 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40018 un1_CS_0_sqmuxa_0_0_a2_1_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40047 un1_CS_0_sqmuxa_0_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40053 \ram2e_ufm/RA_35_2_0_0[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40034 \ram2e_ufm/RA_35_2_0_a3_5[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -3134,13 +3561,60 @@ module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40084 un1_CS_0_sqmuxa_0_0_a2_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 un1_CS_0_sqmuxa_0_0_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40079 \ram2e_ufm/wb_dati_7_0_0_a3_15[7] ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40015 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0] ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40083 \ram2e_ufm/wb_dati_7_0_0_a3_13[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40019 \ram2e_ufm/wb_dati_7_0_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40083 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40084 \ram2e_ufm/SUM2_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40085 \ram2e_ufm/N_314_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -3154,17 +3628,24 @@ endmodule
 
 module lut40084 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40085 ( input A, B, C, D, output Z );
 
-  lut40025 nCS_6_u_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40085 nCS_6_u_i_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40036 \ram2e_ufm/S_r_i_0_o2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40041 \ram2e_ufm/S_r_i_0_o2_RNIP4KI1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3175,15 +3656,13 @@ module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40085 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_79 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40086 \wb_dati_7_0_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40053 \wb_dati_7_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40086 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40087 \ram2e_ufm/S_r_i_0_o2_RNIOGTF1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3200,36 +3679,20 @@ endmodule
 
 module lut40086 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40087 \wb_adr_7_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 \wb_adr_7_0_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40087 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCC08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40067 \wb_dati_7_0_a2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40073 \un1_LEDEN_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40034 \ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40088 \ram2e_ufm/CmdBitbangMXO2_RNINSM62 ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
 
   specify
@@ -3245,56 +3708,22 @@ module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40013 un1_CS_0_sqmuxa_0_0_a2_4_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40059 un1_CS_0_sqmuxa_0_0_a2_4( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40088 \FS_RNI9Q57[13] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40085 \wb_dati_7_0_o2_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
 module lut40088 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_89 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40027 \wb_adr_7_0_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40065 \wb_adr_7_0_a2_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40017 \ram2e_ufm/wb_dati_7_0_0_a3_14[7] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40035 \ram2e_ufm/wb_dati_7_0_0_a3_13_RNI81UL[7] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3305,18 +3734,41 @@ module SLICE_89 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40089 \wb_dati_7_0_o2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40011 \wb_dati_7_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40019 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_83 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40067 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40089 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -3326,32 +3778,16 @@ endmodule
 
 module lut40089 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_91 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40015 un1_CS_0_sqmuxa_0_0_a2_2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40011 un1_CS_0_sqmuxa_0_0_a2_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40090 \wb_adr_7_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40091 \wb_adr_7_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40082 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40090 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3368,63 +3804,90 @@ endmodule
 
 module lut40090 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h3130) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40017 \ram2e_ufm/wb_dati_7_0_0_a3_10[7] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40086 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_86 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40023 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_1 ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut4 \ram2e_ufm/wb_adr_7_i_i_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40091 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40092 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_m3 ( .A(A0), .B(B0), .C(C0), 
+    .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40091 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40092 un1_CS_0_sqmuxa_0_0_a2_1_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40068 un1_CS_0_sqmuxa_0_0_a2_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40092 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8D8D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40026 un1_CS_0_sqmuxa_0_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40065 un1_CS_0_sqmuxa_0_0_a2_3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40093 \ram2e_ufm/wb_dati_7_0_0_a3_4_1_0[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40094 \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40056 wb_we_RNO_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40093 wb_we_RNO_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3437,15 +3900,22 @@ endmodule
 
 module lut40093 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40094 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hC8C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_89 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40094 \RA_42_i_o2[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40077 \ram2e_ufm/wb_dati_7_0_0_a3_7[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40095 \RA_0io_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40055 \ram2e_ufm/wb_dati_7_0_0_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
@@ -3459,24 +3929,17 @@ module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40094 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'hEFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40095 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_97 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40033 \wb_dati_7_0_a2_1[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40072 CKE_6_iv_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40095 \ram2e_ufm/wb_dati_7_0_0_a3_1_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40055 \ram2e_ufm/wb_dati_7_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3487,14 +3950,19 @@ module SLICE_97 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_98 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module lut40095 ( input A, B, C, D, output Z );
 
-  lut40096 un1_CS_0_sqmuxa_0_0_a2_16( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40065 un1_CS_0_sqmuxa_0_0_a2_4_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'h0021) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40096 \ram2e_ufm/nRAS_s_i_0_a3_8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40097 \ram2e_ufm/nRAS_s_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -3508,127 +3976,57 @@ endmodule
 
 module lut40096 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_99 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40003 un1_CS_0_sqmuxa_0_0_a2_12( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40013 un1_CS_0_sqmuxa_0_0_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_100 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40011 un1_CS_0_sqmuxa_0_0_a2_17( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40009 CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), 
-    .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40097 wb_reqc_1_RNIEO5C1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40098 \S_RNII9DO1_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40097 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40098 \ram2e_ufm/CKE_7s2_0_0_o3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40099 \ram2e_ufm/nCAS_s_i_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40098 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hC289) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40099 \S_s_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40018 \BA_0io_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h5C50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40099 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hD550) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_93 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40056 \RA_0io_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 wb_req_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40100 \ram2e_ufm/wb_dati_7_0_0_o2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40013 \ram2e_ufm/wb_dati_7_0_0_a3[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40065 \wb_dati_7_0_a2_3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40100 \wb_adr_7_0_a2_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -3638,18 +4036,19 @@ endmodule
 
 module lut40100 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40101 \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
-    .Z(F1));
-  lut40045 \wb_dati_7_0_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40101 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40041 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3662,44 +4061,18 @@ endmodule
 
 module lut40101 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_106 ( input B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40102 \S_RNINI6S[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40103 CKE_6_iv_i_0_1_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40102 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40103 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_107 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40102 \S_r_i_o2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40018 \BA_0io_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40102 \ram2e_ufm/RA_35_0_0_o2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40033 \ram2e_ufm/RA_35_0_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3710,12 +4083,45 @@ module SLICE_107 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_108 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40102 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hEAE8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40103 \ram2e_ufm/RA_35_0_0_o2_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40033 \ram2e_ufm/RA_35_0_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40103 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1512) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_97 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40007 \wb_adr_7_0_a2_5_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40104 \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40104 \wb_dati_7_0_a2[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40055 \ram2e_ufm/wb_dati_7_0_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
@@ -3731,17 +4137,19 @@ endmodule
 
 module lut40104 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_98 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40037 \wb_dati_7_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40037 \wb_dati_7_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40093 \ram2e_ufm/wb_dati_7_0_0_a3_9[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40055 \ram2e_ufm/wb_dati_7_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3752,13 +4160,16 @@ module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_99 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40105 \RA_0io_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40055 CmdBitbangMXO2_RNI8CSO1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40105 \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40106 \ram2e_ufm/wb_adr_7_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -3772,79 +4183,21 @@ endmodule
 
 module lut40105 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0023) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_111 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40106 \RA_42_3_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40020 \RA_0io_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40106 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hABAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_112 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40107 nCS_6_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40020 \RA_0io_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40107 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40020 \RA_0io_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40020 \RA_0io_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40073 \wb_dati_7_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40073 \un1_RWMask_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
+  lut4 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40107 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3859,12 +4212,19 @@ module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40107 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hBF8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_101 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40027 nWE80_pad_RNI3ICD( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  lut40022 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3 ( .A(A1), .B(B1), 
+    .C(GNDI), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40108 nRWE_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40108 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (B1 => F1) = (0:0:0,0:0:0);
@@ -3879,15 +4239,35 @@ endmodule
 
 module lut40108 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hB1A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_116 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_102 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40102 \wb_adr_7_0_o2_2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  lut40077 \ram2e_ufm/CKE_7s2_0_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40109 \wb_dati_7_0_a2_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40047 \ram2e_ufm/CKE_7s2_0_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_103 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40101 \ram2e_ufm/wb_dati_7_0_0_0_o2[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40109 \ram2e_ufm/wb_adr_RNO_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (B1 => F1) = (0:0:0,0:0:0);
@@ -3902,14 +4282,16 @@ endmodule
 
 module lut40109 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_117 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_104 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40093 \RWBank_5_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40110 LED_pad_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  lut40110 \ram2e_ufm/wb_dati_7_0_0_o2_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40093 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ( .A(A0), .B(B0), .C(GNDI), 
+    .D(GNDI), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
@@ -3925,16 +4307,870 @@ endmodule
 
 module lut40110 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_118 ( input B1, A1, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_105 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40003 un1_CS_0_sqmuxa_0_0_a2_11( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+  lut40016 \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40111 \ram2e_ufm/N_285_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40111 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_106 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40022 \ram2e_ufm/S_r_i_0_o2[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
     .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40033 un1_CS_0_sqmuxa_0_0_a2_13( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+  lut40112 \ram2e_ufm/RA_35_2_0_a3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40112 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hD050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_107 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40113 \ram2e_ufm/CKE_7_m1_0_0_o2_RNIGC501 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40114 \ram2e_ufm/RA_35_i_i_0_a3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40113 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40114 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hD800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_108 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut4 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40115 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ( .A(A0), 
+    .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40115 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h3131) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_109 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40006 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_6 ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40068 \ram2e_ufm/wb_we_RNO_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_110 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40035 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_7 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40023 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ( .A(A0), .B(B0), 
+    .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_111 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40104 \ram2e_ufm/wb_dati_7_0_0_a3_2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40116 \ram2e_ufm/wb_dati_7_0_0_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40116 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h9180) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_112 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40018 \ram2e_ufm/nRAS_s_i_0_a3_6 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40117 \ram2e_ufm/nRAS_s_i_0_a3_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40117 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_113 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40077 \ram2e_ufm/nRAS_s_i_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40014 \ram2e_ufm/RA_35_2_0_a3_3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_114 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40118 \ram2e_ufm/wb_adr_RNO_2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40117 \ram2e_ufm/wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40118 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8787) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40036 \ram2e_ufm/un2_S_2_i_0_0_o3 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40119 \ram2e_ufm/CKE_7s2_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40119 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0C4C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_116 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40014 \ram2e_ufm/CmdExecMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40067 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ( .A(A0), .B(B0), 
+    .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_117 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40120 \ram2e_ufm/S_s_0_0_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40121 \ram2e_ufm/N_225_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40120 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0F0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40121 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_118 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40113 \ram2e_ufm/CKE_7_m1_0_0_o2_RNI7FOA1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40122 \ram2e_ufm/N_201_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40122 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_119 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40123 \ram2e_ufm/S_r_i_0_o2_RNIBAU51[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40124 \ram2e_ufm/un1_CKE75_0_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40123 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40124 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hD79B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_120 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40125 \ram2e_ufm/DQMH_4_iv_0_0_i_i_a3_0_a3 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40126 \ram2e_ufm/N_507_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40125 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h31F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40126 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hCD05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_121 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40127 \ram2e_ufm/Vout3_0_a3_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40128 \ram2e_ufm/RA_35_0_0_o2[11] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40127 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40128 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFCF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_122 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40129 \ram2e_ufm/nRWE_s_i_0_63_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40130 \ram2e_ufm/nCAS_s_i_0_m2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40129 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4FFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40130 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h37FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_123 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40131 \ram2e_ufm/wb_adr_RNO_3[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40019 \ram2e_ufm/wb_dati_7_0_0_a3_8[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40131 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_124 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40132 \ram2e_ufm/RA_35_0_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40035 \ram2e_ufm/RA_35_0_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40132 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_125 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40133 \ram2e_ufm/wb_adr_7_i_i_o2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40045 \ram2e_ufm/wb_dati_7_0_0_a3_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40133 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7F70) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_126 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40134 \ram2e_ufm/wb_we_RNO_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40117 \ram2e_ufm/wb_adr_7_i_i_a3_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40134 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7F07) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_127 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40117 \ram2e_ufm/un9_VOEEN_0_a2_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40046 \ram2e_ufm/RA_35_2_30_a3_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_128 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40135 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40136 \ram2e_ufm/wb_adr_RNO_4[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40135 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h2080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40136 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40080 \ram2e_ufm/BA_4[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40016 \ram2e_ufm/RA_35_2_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_130 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40083 \ram2e_ufm/N_187_i ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40088 \ram2e_ufm/wb_we_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_131 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40035 \ram2e_ufm/Ready3_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40137 \ram2e_ufm/wb_dati_7_0_0_0_a3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40137 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_132 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40138 \ram2e_ufm/RA_35_0_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40033 \ram2e_ufm/RA_35_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40138 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_133 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40035 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40084 \ram2e_ufm/SUM0_i_o2_2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_134 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut4 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40114 \ram2e_ufm/RA_35_0_0_a3[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_135 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40022 \ram2e_ufm/S_r_i_0_o2_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40139 \ram2e_ufm/RA_35_2_0_a3_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40139 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_136 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40140 \ram2e_ufm/nRAS_s_i_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40141 \ram2e_ufm/un1_nDOE_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40140 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5757) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40141 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_137 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40142 \ram2e_ufm/RDOE_i ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40084 \ram2e_ufm/LEDEN_RNI6G6M ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40142 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_138 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40007 VOEEN_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40007 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_139 ( input B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40101 nVOE_pad_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40067 S_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_140 ( input B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40023 \ram2e_ufm/RA_35_0_0_a3_0[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/RA_35_0_0_a3[5] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
     .Z(F0));
 
   specify
@@ -3946,12 +5182,114 @@ module SLICE_118 ( input B1, A1, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_119 ( input D0, C0, B0, A0, output F0 );
+module ram2e_ufm_SLICE_141 ( input B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40026 Ready_0_sqmuxa_0_a2_6_a2_2_0( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/N_263_i ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_142 ( input C1, B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40136 \ram2e_ufm/CmdLEDGet_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/RDout_i_i_a3[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
     .Z(F0));
 
   specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_143 ( input B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[7] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_144 ( input B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_145 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40033 \ram2e_ufm/wb_dati_7_0_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40143 \ram2e_ufm/wb_dati_7_0_0_o2_0[7] ( .A(A0), .B(B0), .C(GNDI), 
+    .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40143 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_146 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40144 \ram2e_ufm/RA_35_0_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40035 \ram2e_ufm/Ready3_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -3960,6 +5298,31 @@ module SLICE_119 ( input D0, C0, B0, A0, output F0 );
 
 endmodule
 
+module lut40144 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_147 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40027 \ram2e_ufm/RWBank_3_0_0_o3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[5] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
 module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
 
   xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
@@ -3982,7 +5345,7 @@ endmodule
 
 module LED ( input PADDO, output LED );
 
-  xo2iobuf0111 LED_pad( .I(PADDO), .PAD(LED));
+  xo2iobuf0145 LED_pad( .I(PADDO), .PAD(LED));
 
   specify
     (PADDO => LED) = (0:0:0,0:0:0);
@@ -3990,14 +5353,14 @@ module LED ( input PADDO, output LED );
 
 endmodule
 
-module xo2iobuf0111 ( input I, output PAD );
+module xo2iobuf0145 ( input I, output PAD );
 
   OB INST5( .I(I), .O(PAD));
 endmodule
 
 module C14M ( output PADDI, input C14M );
 
-  xo2iobuf0112 C14M_pad( .Z(PADDI), .PAD(C14M));
+  xo2iobuf0146 C14M_pad( .Z(PADDI), .PAD(C14M));
 
   specify
     (C14M => PADDI) = (0:0:0,0:0:0);
@@ -4007,71 +5370,11 @@ module C14M ( output PADDI, input C14M );
 
 endmodule
 
-module xo2iobuf0112 ( output Z, input PAD );
+module xo2iobuf0146 ( output Z, input PAD );
 
   IB INST1( .I(PAD), .O(Z));
 endmodule
 
-module DQMH ( input IOLDO, output DQMH );
-
-  xo2iobuf0111 DQMH_pad( .I(IOLDO), .PAD(DQMH));
-
-  specify
-    (IOLDO => DQMH) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module DQMH_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre DQMH_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module mfflsre ( input D0, SP, CK, LSR, output Q );
-
-  FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module DQML ( input IOLDO, output DQML );
-
-  xo2iobuf0111 DQML_pad( .I(IOLDO), .PAD(DQML));
-
-  specify
-    (IOLDO => DQML) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module DQML_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre DQML_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
 module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
 
   xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
@@ -4170,305 +5473,416 @@ module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
 
 endmodule
 
-module RA_11_ ( input IOLDO, output RA11 );
+module DQMH ( input IOLDO, output DQMH );
 
-  xo2iobuf0111 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));
+  xo2iobuf0145 DQMH_pad( .I(IOLDO), .PAD(DQMH));
 
   specify
-    (IOLDO => RA11) = (0:0:0,0:0:0);
+    (IOLDO => DQMH) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_11__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module DQMH_MGIOL ( output IOLDO, input OPOS, CE, CLK );
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \RA_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre DQMH_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), 
     .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
-module mfflsre0113 ( input D0, SP, CK, LSR, output Q );
+module mfflsre ( input D0, SP, CK, LSR, output Q );
+
+  FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module DQML ( input IOLDO, output DQML );
+
+  xo2iobuf0145 DQML_pad( .I(IOLDO), .PAD(DQML));
+
+  specify
+    (IOLDO => DQML) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module DQML_MGIOL ( output IOLDO, input OPOS, CE, CLK );
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+
+  mfflsre DQML_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), 
+    .Q(IOLDO));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_11_ ( input IOLDO, output RAout11 );
+
+  xo2iobuf0145 \RAout_pad[11] ( .I(IOLDO), .PAD(RAout11));
+
+  specify
+    (IOLDO => RAout11) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_11__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0147 \RAout_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+  endspecify
+
+endmodule
+
+module mfflsre0147 ( input D0, SP, CK, LSR, output Q );
 
   FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module RA_10_ ( input IOLDO, output RA10 );
+module inverter ( input I, output Z );
 
-  xo2iobuf0111 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));
+  INV INST1( .A(I), .Z(Z));
+endmodule
+
+module RAout_10_ ( input IOLDO, output RAout10 );
+
+  xo2iobuf0145 \RAout_pad[10] ( .I(IOLDO), .PAD(RAout10));
 
   specify
-    (IOLDO => RA10) = (0:0:0,0:0:0);
+    (IOLDO => RAout10) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_10__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_10__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0147 \RAout_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_9_ ( input IOLDO, output RA9 );
+module RAout_9_ ( input IOLDO, output RAout9 );
 
-  xo2iobuf0111 \RA_pad[9] ( .I(IOLDO), .PAD(RA9));
+  xo2iobuf0145 \RAout_pad[9] ( .I(IOLDO), .PAD(RAout9));
 
   specify
-    (IOLDO => RA9) = (0:0:0,0:0:0);
+    (IOLDO => RAout9) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_9__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_9__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0147 \RAout_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_8_ ( input IOLDO, output RA8 );
+module RAout_8_ ( input IOLDO, output RAout8 );
 
-  xo2iobuf0111 \RA_pad[8] ( .I(IOLDO), .PAD(RA8));
+  xo2iobuf0145 \RAout_pad[8] ( .I(IOLDO), .PAD(RAout8));
 
   specify
-    (IOLDO => RA8) = (0:0:0,0:0:0);
+    (IOLDO => RAout8) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_8__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_8__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0147 \RAout_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_7_ ( input IOLDO, output RA7 );
+module RAout_7_ ( input IOLDO, output RAout7 );
 
-  xo2iobuf0111 \RA_pad[7] ( .I(IOLDO), .PAD(RA7));
+  xo2iobuf0145 \RAout_pad[7] ( .I(IOLDO), .PAD(RAout7));
 
   specify
-    (IOLDO => RA7) = (0:0:0,0:0:0);
+    (IOLDO => RAout7) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_7__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_6_ ( input IOLDO, output RA6 );
+module RAout_6_ ( input IOLDO, output RAout6 );
 
-  xo2iobuf0111 \RA_pad[6] ( .I(IOLDO), .PAD(RA6));
+  xo2iobuf0145 \RAout_pad[6] ( .I(IOLDO), .PAD(RAout6));
 
   specify
-    (IOLDO => RA6) = (0:0:0,0:0:0);
+    (IOLDO => RAout6) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_6__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_5_ ( input IOLDO, output RA5 );
+module RAout_5_ ( input IOLDO, output RAout5 );
 
-  xo2iobuf0111 \RA_pad[5] ( .I(IOLDO), .PAD(RA5));
+  xo2iobuf0145 \RAout_pad[5] ( .I(IOLDO), .PAD(RAout5));
 
   specify
-    (IOLDO => RA5) = (0:0:0,0:0:0);
+    (IOLDO => RAout5) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_5__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_4_ ( input IOLDO, output RA4 );
+module RAout_4_ ( input IOLDO, output RAout4 );
 
-  xo2iobuf0111 \RA_pad[4] ( .I(IOLDO), .PAD(RA4));
+  xo2iobuf0145 \RAout_pad[4] ( .I(IOLDO), .PAD(RAout4));
 
   specify
-    (IOLDO => RA4) = (0:0:0,0:0:0);
+    (IOLDO => RAout4) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_4__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_3_ ( input PADDO, output RA3 );
+module RAout_3_ ( input IOLDO, output RAout3 );
 
-  xo2iobuf0111 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
+  xo2iobuf0145 \RAout_pad[3] ( .I(IOLDO), .PAD(RAout3));
 
   specify
-    (PADDO => RA3) = (0:0:0,0:0:0);
+    (IOLDO => RAout3) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_2_ ( input IOLDO, output RA2 );
+module RAout_3__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  xo2iobuf0111 \RA_pad[2] ( .I(IOLDO), .PAD(RA2));
-
-  specify
-    (IOLDO => RA2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \RA_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_1_ ( input IOLDO, output RA1 );
+module RAout_2_ ( input IOLDO, output RAout2 );
 
-  xo2iobuf0111 \RA_pad[1] ( .I(IOLDO), .PAD(RA1));
+  xo2iobuf0145 \RAout_pad[2] ( .I(IOLDO), .PAD(RAout2));
 
   specify
-    (IOLDO => RA1) = (0:0:0,0:0:0);
+    (IOLDO => RAout2) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_2__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_0_ ( input PADDO, output RA0 );
+module RAout_1_ ( input IOLDO, output RAout1 );
 
-  xo2iobuf0111 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
+  xo2iobuf0145 \RAout_pad[1] ( .I(IOLDO), .PAD(RAout1));
 
   specify
-    (PADDO => RA0) = (0:0:0,0:0:0);
+    (IOLDO => RAout1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_1__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0147 \RAout_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+  endspecify
+
+endmodule
+
+module RAout_0_ ( input IOLDO, output RAout0 );
+
+  xo2iobuf0145 \RAout_pad[0] ( .I(IOLDO), .PAD(RAout0));
+
+  specify
+    (IOLDO => RAout0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_0__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0147 \RAout_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
 module BA_1_ ( input IOLDO, output BA1 );
 
-  xo2iobuf0111 \BA_pad[1] ( .I(IOLDO), .PAD(BA1));
+  xo2iobuf0145 \BA_pad[1] ( .I(IOLDO), .PAD(BA1));
 
   specify
     (IOLDO => BA1) = (0:0:0,0:0:0);
@@ -4476,16 +5890,16 @@ module BA_1_ ( input IOLDO, output BA1 );
 
 endmodule
 
-module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
-  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;
+module BA_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK );
+  wire   OPOS_dly, CLK_dly, CE_dly, LSR_dly;
 
-  mfflsre0114 \BA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), 
+  mfflsre0148 \BA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(LSR_dly), .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
@@ -4493,7 +5907,7 @@ module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
 
 endmodule
 
-module mfflsre0114 ( input D0, SP, CK, LSR, output Q );
+module mfflsre0148 ( input D0, SP, CK, LSR, output Q );
 
   FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
@@ -4501,7 +5915,7 @@ endmodule
 
 module BA_0_ ( input IOLDO, output BA0 );
 
-  xo2iobuf0111 \BA_pad[0] ( .I(IOLDO), .PAD(BA0));
+  xo2iobuf0145 \BA_pad[0] ( .I(IOLDO), .PAD(BA0));
 
   specify
     (IOLDO => BA0) = (0:0:0,0:0:0);
@@ -4509,16 +5923,16 @@ module BA_0_ ( input IOLDO, output BA0 );
 
 endmodule
 
-module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
-  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;
+module BA_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK );
+  wire   OPOS_dly, CLK_dly, CE_dly, LSR_dly;
 
-  mfflsre0114 \BA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), 
+  mfflsre0148 \BA_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(LSR_dly), .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
@@ -4526,144 +5940,131 @@ module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
 
 endmodule
 
-module nRWE ( input IOLDO, output nRWE );
+module nRWEout ( input IOLDO, output nRWEout );
 
-  xo2iobuf0111 nRWE_pad( .I(IOLDO), .PAD(nRWE));
+  xo2iobuf0145 nRWEout_pad( .I(IOLDO), .PAD(nRWEout));
 
   specify
-    (IOLDO => nRWE) = (0:0:0,0:0:0);
+    (IOLDO => nRWEout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nRWE_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nRWEout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nRWEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nCAS ( input IOLDO, output nCAS );
+module nCASout ( input IOLDO, output nCASout );
 
-  xo2iobuf0111 nCAS_pad( .I(IOLDO), .PAD(nCAS));
+  xo2iobuf0145 nCASout_pad( .I(IOLDO), .PAD(nCASout));
 
   specify
-    (IOLDO => nCAS) = (0:0:0,0:0:0);
+    (IOLDO => nCASout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nCAS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nCASout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nCASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nRAS ( input IOLDO, output nRAS );
+module nRASout ( input IOLDO, output nRASout );
 
-  xo2iobuf0111 nRAS_pad( .I(IOLDO), .PAD(nRAS));
+  xo2iobuf0145 nRASout_pad( .I(IOLDO), .PAD(nRASout));
 
   specify
-    (IOLDO => nRAS) = (0:0:0,0:0:0);
+    (IOLDO => nRASout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nRAS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nRASout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nRASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nCS ( input IOLDO, output nCS );
+module nCSout ( input PADDO, output nCSout );
 
-  xo2iobuf0111 nCS_pad( .I(IOLDO), .PAD(nCS));
+  xo2iobuf0145 nCSout_pad( .I(PADDO), .PAD(nCSout));
 
   specify
-    (IOLDO => nCS) = (0:0:0,0:0:0);
+    (PADDO => nCSout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nCS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module CKEout ( input IOLDO, output CKEout );
 
-  mfflsre nCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  xo2iobuf0145 CKEout_pad( .I(IOLDO), .PAD(CKEout));
+
+  specify
+    (IOLDO => CKEout) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module CKEout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0147 CKEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module CKE ( input IOLDO, output CKE );
-
-  xo2iobuf0111 CKE_pad( .I(IOLDO), .PAD(CKE));
-
-  specify
-    (IOLDO => CKE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module CKE_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre0113 CKE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
 module nVOE ( input PADDO, output nVOE );
 
-  xo2iobuf0111 nVOE_pad( .I(PADDO), .PAD(nVOE));
+  xo2iobuf0145 nVOE_pad( .I(PADDO), .PAD(nVOE));
 
   specify
     (PADDO => nVOE) = (0:0:0,0:0:0);
@@ -4673,7 +6074,7 @@ endmodule
 
 module Vout_7_ ( input IOLDO, output Vout7 );
 
-  xo2iobuf0111 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7));
+  xo2iobuf0145 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7));
 
   specify
     (IOLDO => Vout7) = (0:0:0,0:0:0);
@@ -4682,31 +6083,25 @@ module Vout_7_ ( input IOLDO, output Vout7 );
 endmodule
 
 module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
-module inverter ( input I, output Z );
-
-  INV INST1( .A(I), .Z(Z));
-endmodule
-
 module Vout_6_ ( input IOLDO, output Vout6 );
 
-  xo2iobuf0111 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6));
+  xo2iobuf0145 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6));
 
   specify
     (IOLDO => Vout6) = (0:0:0,0:0:0);
@@ -4715,26 +6110,25 @@ module Vout_6_ ( input IOLDO, output Vout6 );
 endmodule
 
 module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_5_ ( input IOLDO, output Vout5 );
 
-  xo2iobuf0111 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5));
+  xo2iobuf0145 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5));
 
   specify
     (IOLDO => Vout5) = (0:0:0,0:0:0);
@@ -4743,26 +6137,25 @@ module Vout_5_ ( input IOLDO, output Vout5 );
 endmodule
 
 module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_4_ ( input IOLDO, output Vout4 );
 
-  xo2iobuf0111 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4));
+  xo2iobuf0145 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4));
 
   specify
     (IOLDO => Vout4) = (0:0:0,0:0:0);
@@ -4771,26 +6164,25 @@ module Vout_4_ ( input IOLDO, output Vout4 );
 endmodule
 
 module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_3_ ( input IOLDO, output Vout3 );
 
-  xo2iobuf0111 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3));
+  xo2iobuf0145 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3));
 
   specify
     (IOLDO => Vout3) = (0:0:0,0:0:0);
@@ -4799,26 +6191,25 @@ module Vout_3_ ( input IOLDO, output Vout3 );
 endmodule
 
 module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_2_ ( input IOLDO, output Vout2 );
 
-  xo2iobuf0111 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2));
+  xo2iobuf0145 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2));
 
   specify
     (IOLDO => Vout2) = (0:0:0,0:0:0);
@@ -4827,26 +6218,25 @@ module Vout_2_ ( input IOLDO, output Vout2 );
 endmodule
 
 module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_1_ ( input IOLDO, output Vout1 );
 
-  xo2iobuf0111 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1));
+  xo2iobuf0145 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1));
 
   specify
     (IOLDO => Vout1) = (0:0:0,0:0:0);
@@ -4855,26 +6245,25 @@ module Vout_1_ ( input IOLDO, output Vout1 );
 endmodule
 
 module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_0_ ( input IOLDO, output Vout0 );
 
-  xo2iobuf0111 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0));
+  xo2iobuf0145 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0));
 
   specify
     (IOLDO => Vout0) = (0:0:0,0:0:0);
@@ -4883,26 +6272,25 @@ module Vout_0_ ( input IOLDO, output Vout0 );
 endmodule
 
 module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module nDOE ( input PADDO, output nDOE );
 
-  xo2iobuf0111 nDOE_pad( .I(PADDO), .PAD(nDOE));
+  xo2iobuf0145 nDOE_pad( .I(PADDO), .PAD(nDOE));
 
   specify
     (PADDO => nDOE) = (0:0:0,0:0:0);
@@ -4910,238 +6298,89 @@ module nDOE ( input PADDO, output nDOE );
 
 endmodule
 
-module Dout_7_ ( input IOLDO, output Dout7 );
+module Dout_7_ ( input PADDO, output Dout7 );
 
-  xo2iobuf0115 \Dout_pad[7] ( .I(IOLDO), .PAD(Dout7));
+  xo2iobuf0145 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
 
   specify
-    (IOLDO => Dout7) = (0:0:0,0:0:0);
+    (PADDO => Dout7) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module xo2iobuf0115 ( input I, output PAD );
+module Dout_6_ ( input PADDO, output Dout6 );
 
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module Dout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \Dout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0145 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout6) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_6_ ( input IOLDO, output Dout6 );
+module Dout_5_ ( input PADDO, output Dout5 );
 
-  xo2iobuf0115 \Dout_pad[6] ( .I(IOLDO), .PAD(Dout6));
+  xo2iobuf0145 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
 
   specify
-    (IOLDO => Dout6) = (0:0:0,0:0:0);
+    (PADDO => Dout5) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_4_ ( input PADDO, output Dout4 );
 
-  mfflsre0113 \Dout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0145 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout4) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_5_ ( input IOLDO, output Dout5 );
+module Dout_3_ ( input PADDO, output Dout3 );
 
-  xo2iobuf0115 \Dout_pad[5] ( .I(IOLDO), .PAD(Dout5));
+  xo2iobuf0145 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
 
   specify
-    (IOLDO => Dout5) = (0:0:0,0:0:0);
+    (PADDO => Dout3) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_2_ ( input PADDO, output Dout2 );
 
-  mfflsre0113 \Dout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0145 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout2) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_4_ ( input IOLDO, output Dout4 );
+module Dout_1_ ( input PADDO, output Dout1 );
 
-  xo2iobuf0115 \Dout_pad[4] ( .I(IOLDO), .PAD(Dout4));
+  xo2iobuf0145 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
 
   specify
-    (IOLDO => Dout4) = (0:0:0,0:0:0);
+    (PADDO => Dout1) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_0_ ( input PADDO, output Dout0 );
 
-  mfflsre0113 \Dout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0145 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_3_ ( input IOLDO, output Dout3 );
-
-  xo2iobuf0115 \Dout_pad[3] ( .I(IOLDO), .PAD(Dout3));
-
-  specify
-    (IOLDO => Dout3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \Dout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_2_ ( input IOLDO, output Dout2 );
-
-  xo2iobuf0115 \Dout_pad[2] ( .I(IOLDO), .PAD(Dout2));
-
-  specify
-    (IOLDO => Dout2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \Dout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_1_ ( input IOLDO, output Dout1 );
-
-  xo2iobuf0115 \Dout_pad[1] ( .I(IOLDO), .PAD(Dout1));
-
-  specify
-    (IOLDO => Dout1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \Dout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_0_ ( input IOLDO, output Dout0 );
-
-  xo2iobuf0115 \Dout_pad[0] ( .I(IOLDO), .PAD(Dout0));
-
-  specify
-    (IOLDO => Dout0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \Dout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module Din_7_ ( output PADDI, input Din7 );
 
-  xo2iobuf0112 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
+  xo2iobuf0146 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
 
   specify
     (Din7 => PADDI) = (0:0:0,0:0:0);
@@ -5153,7 +6392,7 @@ endmodule
 
 module Din_6_ ( output PADDI, input Din6 );
 
-  xo2iobuf0112 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
+  xo2iobuf0146 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
 
   specify
     (Din6 => PADDI) = (0:0:0,0:0:0);
@@ -5165,7 +6404,7 @@ endmodule
 
 module Din_5_ ( output PADDI, input Din5 );
 
-  xo2iobuf0112 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
+  xo2iobuf0146 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
 
   specify
     (Din5 => PADDI) = (0:0:0,0:0:0);
@@ -5177,7 +6416,7 @@ endmodule
 
 module Din_4_ ( output PADDI, input Din4 );
 
-  xo2iobuf0112 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
+  xo2iobuf0146 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
 
   specify
     (Din4 => PADDI) = (0:0:0,0:0:0);
@@ -5189,7 +6428,7 @@ endmodule
 
 module Din_3_ ( output PADDI, input Din3 );
 
-  xo2iobuf0112 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
+  xo2iobuf0146 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
 
   specify
     (Din3 => PADDI) = (0:0:0,0:0:0);
@@ -5201,7 +6440,7 @@ endmodule
 
 module Din_2_ ( output PADDI, input Din2 );
 
-  xo2iobuf0112 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
+  xo2iobuf0146 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
 
   specify
     (Din2 => PADDI) = (0:0:0,0:0:0);
@@ -5213,7 +6452,7 @@ endmodule
 
 module Din_1_ ( output PADDI, input Din1 );
 
-  xo2iobuf0112 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
+  xo2iobuf0146 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
 
   specify
     (Din1 => PADDI) = (0:0:0,0:0:0);
@@ -5225,7 +6464,7 @@ endmodule
 
 module Din_0_ ( output PADDI, input Din0 );
 
-  xo2iobuf0112 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
+  xo2iobuf0146 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
 
   specify
     (Din0 => PADDI) = (0:0:0,0:0:0);
@@ -5237,7 +6476,7 @@ endmodule
 
 module Ain_7_ ( output PADDI, input Ain7 );
 
-  xo2iobuf0112 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7));
+  xo2iobuf0146 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7));
 
   specify
     (Ain7 => PADDI) = (0:0:0,0:0:0);
@@ -5249,7 +6488,7 @@ endmodule
 
 module Ain_6_ ( output PADDI, input Ain6 );
 
-  xo2iobuf0112 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6));
+  xo2iobuf0146 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6));
 
   specify
     (Ain6 => PADDI) = (0:0:0,0:0:0);
@@ -5261,7 +6500,7 @@ endmodule
 
 module Ain_5_ ( output PADDI, input Ain5 );
 
-  xo2iobuf0112 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5));
+  xo2iobuf0146 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5));
 
   specify
     (Ain5 => PADDI) = (0:0:0,0:0:0);
@@ -5273,7 +6512,7 @@ endmodule
 
 module Ain_4_ ( output PADDI, input Ain4 );
 
-  xo2iobuf0112 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4));
+  xo2iobuf0146 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4));
 
   specify
     (Ain4 => PADDI) = (0:0:0,0:0:0);
@@ -5285,7 +6524,7 @@ endmodule
 
 module Ain_3_ ( output PADDI, input Ain3 );
 
-  xo2iobuf0112 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3));
+  xo2iobuf0146 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3));
 
   specify
     (Ain3 => PADDI) = (0:0:0,0:0:0);
@@ -5297,7 +6536,7 @@ endmodule
 
 module Ain_2_ ( output PADDI, input Ain2 );
 
-  xo2iobuf0112 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2));
+  xo2iobuf0146 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2));
 
   specify
     (Ain2 => PADDI) = (0:0:0,0:0:0);
@@ -5309,7 +6548,7 @@ endmodule
 
 module Ain_1_ ( output PADDI, input Ain1 );
 
-  xo2iobuf0112 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1));
+  xo2iobuf0146 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1));
 
   specify
     (Ain1 => PADDI) = (0:0:0,0:0:0);
@@ -5321,7 +6560,7 @@ endmodule
 
 module Ain_0_ ( output PADDI, input Ain0 );
 
-  xo2iobuf0112 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0));
+  xo2iobuf0146 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0));
 
   specify
     (Ain0 => PADDI) = (0:0:0,0:0:0);
@@ -5333,7 +6572,7 @@ endmodule
 
 module nC07X ( output PADDI, input nC07X );
 
-  xo2iobuf0112 nC07X_pad( .Z(PADDI), .PAD(nC07X));
+  xo2iobuf0146 nC07X_pad( .Z(PADDI), .PAD(nC07X));
 
   specify
     (nC07X => PADDI) = (0:0:0,0:0:0);
@@ -5345,7 +6584,7 @@ endmodule
 
 module nEN80 ( output PADDI, input nEN80 );
 
-  xo2iobuf0112 nEN80_pad( .Z(PADDI), .PAD(nEN80));
+  xo2iobuf0146 nEN80_pad( .Z(PADDI), .PAD(nEN80));
 
   specify
     (nEN80 => PADDI) = (0:0:0,0:0:0);
@@ -5355,21 +6594,9 @@ module nEN80 ( output PADDI, input nEN80 );
 
 endmodule
 
-module nWE80 ( output PADDI, input nWE80 );
-
-  xo2iobuf0112 nWE80_pad( .Z(PADDI), .PAD(nWE80));
-
-  specify
-    (nWE80 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nWE80, 0:0:0);
-    $width (negedge nWE80, 0:0:0);
-  endspecify
-
-endmodule
-
 module nWE ( output PADDI, input nWE );
 
-  xo2iobuf0112 nWE_pad( .Z(PADDI), .PAD(nWE));
+  xo2iobuf0146 nWE_pad( .Z(PADDI), .PAD(nWE));
 
   specify
     (nWE => PADDI) = (0:0:0,0:0:0);
@@ -5381,7 +6608,7 @@ endmodule
 
 module PHI1 ( output PADDI, input PHI1 );
 
-  xo2iobuf0112 PHI1_pad( .Z(PADDI), .PAD(PHI1));
+  xo2iobuf0146 PHI1_pad( .Z(PADDI), .PAD(PHI1));
 
   specify
     (PHI1 => PADDI) = (0:0:0,0:0:0);
@@ -5394,7 +6621,7 @@ endmodule
 module PHI1_MGIOL ( input DI, CLK, output IN );
   wire   VCCI, GNDI, DI_dly, CLK_dly;
 
-  smuxlregsre PHI1reg_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  smuxlregsre PHI1r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
     .Q(IN));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
@@ -5414,14 +6641,14 @@ module smuxlregsre ( input D0, SP, CK, LSR, output Q );
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, 
-    WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, 
-    WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output 
-    WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, 
-    WBACKO );
+module ram2e_ufm_ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, 
+    WBWEI, WBADRI0, WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, 
+    WBADRI7, WBDATI0, WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, 
+    WBDATI7, output WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, 
+    WBDATO6, WBDATO7, WBACKO );
   wire   VCCI, GNDI;
 
-  EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), 
+  EFB_B \ram2e_ufm/ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), 
     .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), 
     .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), 
     .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html
index 9a7029b..7a61ca2 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html
@@ -23,23 +23,23 @@ Target Vendor:  LATTICE
 Target Device:  LCMXO2-1200HCTQFP100
 Target Performance:   4
 Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  09/21/23  05:34:46
+Mapped on:  12/28/23  23:09:57
 
 
 <A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
-   Number of registers:    111 out of  1520 (7%)
-      PFU registers:           75 out of  1280 (6%)
-      PIO registers:           36 out of   240 (15%)
-   Number of SLICEs:       120 out of   640 (19%)
-      SLICEs as Logic/ROM:    120 out of   640 (19%)
+   Number of registers:    122 out of  1520 (8%)
+      PFU registers:           93 out of  1280 (7%)
+      PIO registers:           29 out of   240 (12%)
+   Number of SLICEs:       148 out of   640 (23%)
+      SLICEs as Logic/ROM:    148 out of   640 (23%)
       SLICEs as RAM:            0 out of   480 (0%)
       SLICEs as Carry:          9 out of   640 (1%)
-   Number of LUT4s:        239 out of  1280 (19%)
-      Number used as logic LUTs:        221
+   Number of LUT4s:        296 out of  1280 (23%)
+      Number used as logic LUTs:        278
       Number used as distributed RAM:     0
       Number used as ripple logic:       18
       Number used as shift registers:     0
-   Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
+   Number of PIO sites used: 69 + 4(JTAG) out of 80 (91%)
    Number of block RAMs:  0 out of 7 (0%)
    Number of GSRs:        0 out of 1 (0%)
    EFB used :        Yes
@@ -65,43 +65,48 @@ Mapped on:  09/21/23  05:34:46
       2. Number of logic LUT4s does not include count of distributed RAM and
      ripple logic.
    Number of clocks:  1
-     Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
-   Number of Clock Enables:  11
+     Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M )
+   Number of Clock Enables:  14
 
-     Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
-     Net N_576_i: 17 loads, 9 LSLICEs
-     Net LEDEN13: 4 loads, 4 LSLICEs
-     Net nCS61: 1 loads, 1 LSLICEs
+     Net N_225_i: 2 loads, 0 LSLICEs
+     Net N_201_i: 2 loads, 0 LSLICEs
+     Net N_187_i: 11 loads, 11 LSLICEs
+     Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
+     Net RC12: 2 loads, 2 LSLICEs
+     Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs
+     Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs
+     Net N_185_i: 2 loads, 2 LSLICEs
+     Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs
+     Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs
+     Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs
+     Net N_126: 6 loads, 6 LSLICEs
+     Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs
      Net Vout3: 8 loads, 0 LSLICEs
-     Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
-     Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
-     Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
-     Net N_104: 1 loads, 1 LSLICEs
-     Net N_88: 4 loads, 4 LSLICEs
-     Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
-   Number of LSRs:  5
+   Number of LSRs:  7
      Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
+     Net BA_0_sqmuxa: 2 loads, 0 LSLICEs
      Net S[2]: 1 loads, 1 LSLICEs
-     Net N_566_i: 2 loads, 0 LSLICEs
-     Net wb_rst: 1 loads, 0 LSLICEs
-     Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
+     Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
+     Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs
+     Net N_1080_0: 1 loads, 1 LSLICEs
+     Net N_1078_0: 1 loads, 1 LSLICEs
    Number of nets driven by tri-state buffers:  0
    Top 10 highest fanout non-clock nets:
-     Net S[2]: 48 loads
-     Net S[3]: 48 loads
-     Net S[0]: 30 loads
-     Net FS[12]: 22 loads
-     Net FS[9]: 21 loads
-     Net S[1]: 21 loads
-     Net FS[10]: 20 loads
-     Net FS[11]: 19 loads
-     Net RWSel: 19 loads
-     Net FS[13]: 17 loads
+     Net S[2]: 50 loads
+     Net S[3]: 45 loads
+     Net S[0]: 37 loads
+     Net S[1]: 34 loads
+     Net FS[12]: 24 loads
+     Net FS[11]: 22 loads
+     Net FS[10]: 19 loads
+     Net FS[13]: 19 loads
+     Net FS[9]: 19 loads
+     Net FS[8]: 18 loads
 
 
 
 
-   Number of warnings:  1
+   Number of warnings:  3
    Number of errors:    0
      
 
@@ -110,12 +115,18 @@ Mapped on:  09/21/23  05:34:46
 
 <A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
 
+WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(93): Semantic
+     error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
+     "nWE80" does not exist in the design. This preference has been disabled.
 WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
      temporarily disable certain features of the device including Power
      Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
      Functionality is restored after the Flash Memory (UFM/Configuration)
      Interface is disabled using Disable Configuration Interface command 0x26
      followed by Bypass command 0xFF. 
+WARNING - map: IO buffer missing for top level port nWE80...logic will be
+     discarded.
+
 
 
 
@@ -127,15 +138,10 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | RD[0]               | BIDIR     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-
 | LED                 | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | C14M                | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| DQML                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
 | RD[7]               | BIDIR     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | RD[6]               | BIDIR     | LVCMOS33  |            |
@@ -150,44 +156,48 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | RD[1]               | BIDIR     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| RA[11]              | OUTPUT    | LVCMOS33  | OUT        |
+| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[10]              | OUTPUT    | LVCMOS33  | OUT        |
+| DQML                | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[9]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[11]           | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[8]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[10]           | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[7]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[9]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[6]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[8]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[5]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[7]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[4]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[6]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[3]               | OUTPUT    | LVCMOS33  |            |
+| RAout[5]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[2]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[4]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[1]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[3]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[0]               | OUTPUT    | LVCMOS33  |            |
+| RAout[2]            | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RAout[1]            | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RAout[0]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | BA[1]               | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
+
 | BA[0]               | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| nRWE                | OUTPUT    | LVCMOS33  | OUT        |
+| nRWEout             | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| nCAS                | OUTPUT    | LVCMOS33  | OUT        |
+| nCASout             | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| nRAS                | OUTPUT    | LVCMOS33  | OUT        |
+| nRASout             | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-
-| nCS                 | OUTPUT    | LVCMOS33  | OUT        |
+| nCSout              | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| CKE                 | OUTPUT    | LVCMOS33  | OUT        |
+| CKEout              | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | nVOE                | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -209,21 +219,21 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | nDOE                | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[7]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[7]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[6]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[6]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[5]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[5]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[4]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[4]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[3]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[3]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[2]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[2]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[1]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[1]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[0]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[0]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Din[7]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -233,6 +243,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | Din[4]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
+
 | Din[3]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Din[2]              | INPUT     | LVCMOS33  |            |
@@ -241,7 +252,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | Din[0]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-
 | Ain[7]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Ain[6]              | INPUT     | LVCMOS33  |            |
@@ -262,8 +272,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | nEN80               | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| nWE80               | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
 | nWE                 | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | PHI1                | INPUT     | LVCMOS33  | IN         |
@@ -274,68 +282,75 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 <A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
 
 Block GSR_INST undriven or does not drive anything - clipped.
-Signal Dout_0_.CN was merged into signal C14M_c
-Signal GND undriven or does not drive anything - clipped.
-Signal ufmefb/VCC undriven or does not drive anything - clipped.
-Signal ufmefb/GND undriven or does not drive anything - clipped.
+Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
+Block ram2e_ufm/GND undriven or does not drive anything - clipped.
+Signal CKEout.CN was merged into signal C14M_c
+Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
 Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
 Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
-Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
-Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
-Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
-Signal ufmefb/TCOC undriven or does not drive anything - clipped.
-Signal ufmefb/TCINT undriven or does not drive anything - clipped.
-Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
-Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
 
-Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
-Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
-Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
+     
+Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
+     
+Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
 Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
 Signal N_1 undriven or does not drive anything - clipped.
-Block Vout_0_.CN was optimized away.
-Block GND was optimized away.
-Block ufmefb/VCC was optimized away.
-Block ufmefb/GND was optimized away.
+Block nCASout.CN was optimized away.
+Block ram2e_ufm/ufmefb/VCC was optimized away.
+Block ram2e_ufm/ufmefb/GND was optimized away.
 
      
 
@@ -344,8 +359,9 @@ Block ufmefb/GND was optimized away.
 <A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
 
    Desired WISHBONE clock frequency: 14.4 MHz
+
    Clock source:                     C14M_c
-   Reset source:                     wb_rst
+   Reset source:                     ram2e_ufm/wb_rst
    Functions mode:
       I2C #1 (Primary) Function:     DISABLED
       I2C #2 (Secondary) Function:   DISABLED
@@ -357,7 +373,6 @@ Block ufmefb/GND was optimized away.
       PLL1 Connection:               DISABLED
    I2C Function Summary:
    --------------------
-
       None
    SPI Function Summary:
    --------------------
@@ -384,7 +399,7 @@ Block ufmefb/GND was optimized away.
 <A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
 ---------------
 
-Instance Name: ufmefb/EFBInst_0
+Instance Name: ram2e_ufm/ufmefb/EFBInst_0
          Type: EFB
 
 
@@ -394,7 +409,7 @@ Instance Name: ufmefb/EFBInst_0
 
    Total CPU Time: 1 secs  
    Total REAL Time: 0 secs  
-   Peak Memory Usage: 63 MB
+   Peak Memory Usage: 64 MB
         
 
 
@@ -402,19 +417,6 @@ Instance Name: ufmefb/EFBInst_0
 
 
 
-
-
-
-
-
-
-
-
-
-
-
-
-
 
 
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html
index 81a51b2..226fada 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html
@@ -14,7 +14,7 @@ Performance Grade:      4
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.44
 
-Thu Sep 21 05:34:59 2023
+Thu Dec 28 23:10:10 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -31,7 +31,7 @@ Pinout by Port Name:
 | BA[0]     | 58/1     | LVCMOS33_OUT  | PR9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | BA[1]     | 60/1     | LVCMOS33_OUT  | PR8C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | C14M      | 62/1     | LVCMOS33_IN   | PR5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| CKE       | 53/1     | LVCMOS33_OUT  | PR9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| CKEout    | 53/1     | LVCMOS33_OUT  | PR9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | DQMH      | 49/2     | LVCMOS33_OUT  | PB20D |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | DQML      | 48/2     | LVCMOS33_OUT  | PB20C |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | Din[0]    | 96/0     | LVCMOS33_IN   | PT10B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
@@ -42,28 +42,28 @@ Pinout by Port Name:
 | Din[5]    | 99/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 | Din[6]    | 88/0     | LVCMOS33_IN   | PT12A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 | Din[7]    | 87/0     | LVCMOS33_IN   | PT12B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL10D |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL10C |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL9B  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6C  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | LED       | 35/2     | LVCMOS33_OUT  | PB9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | PHI1      | 85/0     | LVCMOS33_IN   | PT12D |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| RA[0]     | 66/1     | LVCMOS33_OUT  | PR4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[10]    | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[11]    | 59/1     | LVCMOS33_OUT  | PR8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[1]     | 68/1     | LVCMOS33_OUT  | PR4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[2]     | 70/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[3]     | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[4]     | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[5]     | 71/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[6]     | 69/1     | LVCMOS33_OUT  | PR4A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[7]     | 67/1     | LVCMOS33_OUT  | PR4C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[8]     | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[9]     | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[0]  | 66/1     | LVCMOS33_OUT  | PR4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[10] | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[11] | 59/1     | LVCMOS33_OUT  | PR8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[1]  | 68/1     | LVCMOS33_OUT  | PR4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[2]  | 70/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[3]  | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[4]  | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[5]  | 71/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[6]  | 69/1     | LVCMOS33_OUT  | PR4A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[7]  | 67/1     | LVCMOS33_OUT  | PR4C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[8]  | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[9]  | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | RD[0]     | 36/2     | LVCMOS33_BIDI | PB11C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[1]     | 37/2     | LVCMOS33_BIDI | PB11D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[2]     | 38/2     | LVCMOS33_BIDI | PB11A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
@@ -81,15 +81,14 @@ Pinout by Port Name:
 | Vout[6]   | 14/3     | LVCMOS33_OUT  | PL5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | Vout[7]   | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nC07X     | 34/2     | LVCMOS33_IN   | PB9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nCAS      | 52/1     | LVCMOS33_OUT  | PR10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nCS       | 57/1     | LVCMOS33_OUT  | PR9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nCASout   | 52/1     | LVCMOS33_OUT  | PR10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nCSout    | 57/1     | LVCMOS33_OUT  | PR9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nDOE      | 20/3     | LVCMOS33_OUT  | PL9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nEN80     | 82/0     | LVCMOS33_IN   | PT15C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nRAS      | 54/1     | LVCMOS33_OUT  | PR9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nRWE      | 51/1     | LVCMOS33_OUT  | PR10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRASout   | 54/1     | LVCMOS33_OUT  | PR9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWEout   | 51/1     | LVCMOS33_OUT  | PR10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nVOE      | 10/3     | LVCMOS33_OUT  | PL4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nWE       | 29/2     | LVCMOS33_IN   | PB6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nWE80     | 83/0     | LVCMOS33_IN   | PT15B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
 
 Vccio by Bank:
@@ -153,33 +152,33 @@ Vccio by Bank:
 | 47/2     |     unused, PULL:DOWN |            |               | PB18D |               |           |           |
 | 48/2     | DQML                  | LOCATED    | LVCMOS33_OUT  | PB20C | SN            |           |           |
 | 49/2     | DQMH                  | LOCATED    | LVCMOS33_OUT  | PB20D | SI/SISPI      |           |           |
-| 51/1     | nRWE                  | LOCATED    | LVCMOS33_OUT  | PR10D | DQ1           |           |           |
-| 52/1     | nCAS                  | LOCATED    | LVCMOS33_OUT  | PR10C | DQ1           |           |           |
-| 53/1     | CKE                   | LOCATED    | LVCMOS33_OUT  | PR9D  | DQ1           |           |           |
-| 54/1     | nRAS                  | LOCATED    | LVCMOS33_OUT  | PR9C  | DQ1           |           |           |
-| 57/1     | nCS                   | LOCATED    | LVCMOS33_OUT  | PR9B  | DQ1           |           |           |
+| 51/1     | nRWEout               | LOCATED    | LVCMOS33_OUT  | PR10D | DQ1           |           |           |
+| 52/1     | nCASout               | LOCATED    | LVCMOS33_OUT  | PR10C | DQ1           |           |           |
+| 53/1     | CKEout                | LOCATED    | LVCMOS33_OUT  | PR9D  | DQ1           |           |           |
+| 54/1     | nRASout               | LOCATED    | LVCMOS33_OUT  | PR9C  | DQ1           |           |           |
+| 57/1     | nCSout                | LOCATED    | LVCMOS33_OUT  | PR9B  | DQ1           |           |           |
 | 58/1     | BA[0]                 | LOCATED    | LVCMOS33_OUT  | PR9A  | DQ1           |           |           |
-| 59/1     | RA[11]                | LOCATED    | LVCMOS33_OUT  | PR8D  | DQ1           |           |           |
+| 59/1     | RAout[11]             | LOCATED    | LVCMOS33_OUT  | PR8D  | DQ1           |           |           |
 | 60/1     | BA[1]                 | LOCATED    | LVCMOS33_OUT  | PR8C  | DQ1           |           |           |
 | 61/1     |     unused, PULL:DOWN |            |               | PR8A  | DQS1          |           |           |
 | 62/1     | C14M                  | LOCATED    | LVCMOS33_IN   | PR5D  | PCLKC1_0/DQ0  |           |           |
-| 63/1     | RA[9]                 | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0/DQ0  |           |           |
-| 64/1     | RA[10]                | LOCATED    | LVCMOS33_OUT  | PR5B  | DQS0N         |           |           |
-| 65/1     | RA[8]                 | LOCATED    | LVCMOS33_OUT  | PR5A  | DQS0          |           |           |
-| 66/1     | RA[0]                 | LOCATED    | LVCMOS33_OUT  | PR4D  | DQ0           |           |           |
-| 67/1     | RA[7]                 | LOCATED    | LVCMOS33_OUT  | PR4C  | DQ0           |           |           |
-| 68/1     | RA[1]                 | LOCATED    | LVCMOS33_OUT  | PR4B  | DQ0           |           |           |
-| 69/1     | RA[6]                 | LOCATED    | LVCMOS33_OUT  | PR4A  | DQ0           |           |           |
-| 70/1     | RA[2]                 | LOCATED    | LVCMOS33_OUT  | PR3B  | DQ0           |           |           |
-| 71/1     | RA[5]                 | LOCATED    | LVCMOS33_OUT  | PR3A  | DQ0           |           |           |
-| 74/1     | RA[3]                 | LOCATED    | LVCMOS33_OUT  | PR2B  | DQ0           |           |           |
-| 75/1     | RA[4]                 | LOCATED    | LVCMOS33_OUT  | PR2A  | DQ0           |           |           |
+| 63/1     | RAout[9]              | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | RAout[10]             | LOCATED    | LVCMOS33_OUT  | PR5B  | DQS0N         |           |           |
+| 65/1     | RAout[8]              | LOCATED    | LVCMOS33_OUT  | PR5A  | DQS0          |           |           |
+| 66/1     | RAout[0]              | LOCATED    | LVCMOS33_OUT  | PR4D  | DQ0           |           |           |
+| 67/1     | RAout[7]              | LOCATED    | LVCMOS33_OUT  | PR4C  | DQ0           |           |           |
+| 68/1     | RAout[1]              | LOCATED    | LVCMOS33_OUT  | PR4B  | DQ0           |           |           |
+| 69/1     | RAout[6]              | LOCATED    | LVCMOS33_OUT  | PR4A  | DQ0           |           |           |
+| 70/1     | RAout[2]              | LOCATED    | LVCMOS33_OUT  | PR3B  | DQ0           |           |           |
+| 71/1     | RAout[5]              | LOCATED    | LVCMOS33_OUT  | PR3A  | DQ0           |           |           |
+| 74/1     | RAout[3]              | LOCATED    | LVCMOS33_OUT  | PR2B  | DQ0           |           |           |
+| 75/1     | RAout[4]              | LOCATED    | LVCMOS33_OUT  | PR2A  | DQ0           |           |           |
 | 76/0     |     unused, PULL:DOWN |            |               | PT17D | DONE          |           |           |
 | 77/0     |     unused, PULL:DOWN |            |               | PT17C | INITN         |           |           |
 | 78/0     | Ain[4]                | LOCATED    | LVCMOS33_IN   | PT16C |               |           |           |
 | 81/0     |     unused, PULL:DOWN |            |               | PT15D | PROGRAMN      |           |           |
 | 82/0     | nEN80                 | LOCATED    | LVCMOS33_IN   | PT15C | JTAGENB       |           |           |
-| 83/0     | nWE80                 | LOCATED    | LVCMOS33_IN   | PT15B |               |           |           |
+| 83/0     |     unused, PULL:DOWN |            |               | PT15B |               |           |           |
 | 84/0     | Ain[5]                | LOCATED    | LVCMOS33_IN   | PT15A |               |           |           |
 | 85/0     | PHI1                  | LOCATED    | LVCMOS33_IN   | PT12D | SDA/PCLKC0_0  |           |           |
 | 86/0     | Ain[6]                | LOCATED    | LVCMOS33_IN   | PT12C | SCL/PCLKT0_0  |           |           |
@@ -250,7 +249,7 @@ LOCATE  COMP  "Ain[7]"  SITE  "8";
 LOCATE  COMP  "BA[0]"  SITE  "58";
 LOCATE  COMP  "BA[1]"  SITE  "60";
 LOCATE  COMP  "C14M"  SITE  "62";
-LOCATE  COMP  "CKE"  SITE  "53";
+LOCATE  COMP  "CKEout"  SITE  "53";
 LOCATE  COMP  "DQMH"  SITE  "49";
 LOCATE  COMP  "DQML"  SITE  "48";
 LOCATE  COMP  "Din[0]"  SITE  "96";
@@ -271,18 +270,18 @@ LOCATE  COMP  "Dout[6]"  SITE  "31";
 LOCATE  COMP  "Dout[7]"  SITE  "32";
 LOCATE  COMP  "LED"  SITE  "35";
 LOCATE  COMP  "PHI1"  SITE  "85";
-LOCATE  COMP  "RA[0]"  SITE  "66";
-LOCATE  COMP  "RA[10]"  SITE  "64";
-LOCATE  COMP  "RA[11]"  SITE  "59";
-LOCATE  COMP  "RA[1]"  SITE  "68";
-LOCATE  COMP  "RA[2]"  SITE  "70";
-LOCATE  COMP  "RA[3]"  SITE  "74";
-LOCATE  COMP  "RA[4]"  SITE  "75";
-LOCATE  COMP  "RA[5]"  SITE  "71";
-LOCATE  COMP  "RA[6]"  SITE  "69";
-LOCATE  COMP  "RA[7]"  SITE  "67";
-LOCATE  COMP  "RA[8]"  SITE  "65";
-LOCATE  COMP  "RA[9]"  SITE  "63";
+LOCATE  COMP  "RAout[0]"  SITE  "66";
+LOCATE  COMP  "RAout[10]"  SITE  "64";
+LOCATE  COMP  "RAout[11]"  SITE  "59";
+LOCATE  COMP  "RAout[1]"  SITE  "68";
+LOCATE  COMP  "RAout[2]"  SITE  "70";
+LOCATE  COMP  "RAout[3]"  SITE  "74";
+LOCATE  COMP  "RAout[4]"  SITE  "75";
+LOCATE  COMP  "RAout[5]"  SITE  "71";
+LOCATE  COMP  "RAout[6]"  SITE  "69";
+LOCATE  COMP  "RAout[7]"  SITE  "67";
+LOCATE  COMP  "RAout[8]"  SITE  "65";
+LOCATE  COMP  "RAout[9]"  SITE  "63";
 LOCATE  COMP  "RD[0]"  SITE  "36";
 LOCATE  COMP  "RD[1]"  SITE  "37";
 LOCATE  COMP  "RD[2]"  SITE  "38";
@@ -300,15 +299,14 @@ LOCATE  COMP  "Vout[5]"  SITE  "16";
 LOCATE  COMP  "Vout[6]"  SITE  "14";
 LOCATE  COMP  "Vout[7]"  SITE  "12";
 LOCATE  COMP  "nC07X"  SITE  "34";
-LOCATE  COMP  "nCAS"  SITE  "52";
-LOCATE  COMP  "nCS"  SITE  "57";
+LOCATE  COMP  "nCASout"  SITE  "52";
+LOCATE  COMP  "nCSout"  SITE  "57";
 LOCATE  COMP  "nDOE"  SITE  "20";
 LOCATE  COMP  "nEN80"  SITE  "82";
-LOCATE  COMP  "nRAS"  SITE  "54";
-LOCATE  COMP  "nRWE"  SITE  "51";
+LOCATE  COMP  "nRASout"  SITE  "54";
+LOCATE  COMP  "nRWEout"  SITE  "51";
 LOCATE  COMP  "nVOE"  SITE  "10";
 LOCATE  COMP  "nWE"  SITE  "29";
-LOCATE  COMP  "nWE80"  SITE  "83";
 
 
 
@@ -320,7 +318,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Sep 21 05:35:04 2023
+Thu Dec 28 23:10:13 2023
 
 
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html
index e56b9bc..745393f 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html
@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Sep 21 05:34:51 2023
+Thu Dec 28 23:10:01 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
 RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
@@ -26,7 +26,7 @@ Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            57.121       0            0.333        0            15           Completed
+5_1   *      0            58.069       0            0.342        0            15           Completed
 * : Design saved.
 
 Total (real) run time for 1-seed: 15 secs 
@@ -36,7 +36,7 @@ par done!
 Note: user must run &apos;Trace&apos; for timing closure signoff.
 
 Lattice Place and Route Report for Design &quot;RAM2E_LCMXO2_1200HC_impl1_map.ncd&quot;
-Thu Sep 21 05:34:51 2023
+Thu Dec 28 23:10:01 2023
 
 
 <A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
@@ -63,43 +63,43 @@ Ignore Preference Error(s):  True
 
 <A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
 
-   PIO (prelim)   70+4(JTAG)/108     69% used
-                  70+4(JTAG)/80      93% bonded
-   IOLOGIC           36/108          33% used
+   PIO (prelim)   69+4(JTAG)/108     68% used
+                  69+4(JTAG)/80      91% bonded
+   IOLOGIC           29/108          26% used
 
-   SLICE            120/640          18% used
+   SLICE            148/640          23% used
 
    EFB                1/1           100% used
 
 
-Number of Signals: 395
-Number of Connections: 1126
+Number of Signals: 459
+Number of Connections: 1330
 
 Pin Constraint Summary:
-   70 out of 70 pins locked (100% locked).
+   69 out of 69 pins locked (100% locked).
 
 The following 1 signal is selected to use the primary clock routing resources:
-    C14M_c (driver: C14M, clk load #: 84)
+    C14M_c (driver: C14M, clk load #: 89)
 
 WARNING - par: Signal &quot;C14M_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;C14M&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 
 The following 1 signal is selected to use the secondary clock routing resources:
-    N_576_i (driver: SLICE_20, clk load #: 0, sr load #: 0, ce load #: 17)
+    N_187_i (driver: ram2e_ufm/SLICE_130, clk load #: 0, sr load #: 0, ce load #: 11)
 
 No signal is selected as Global Set/Reset.
 Starting Placer Phase 0.
 ........
-Finished Placer Phase 0.  REAL time: 2 secs 
+Finished Placer Phase 0.  REAL time: 3 secs 
 
 Starting Placer Phase 1.
-..................
-Placer score = 78271.
+....................
+Placer score = 82860.
 Finished Placer Phase 1.  REAL time: 8 secs 
 
 Starting Placer Phase 2.
 .
-Placer score =  77117
-Finished Placer Phase 2.  REAL time: 8 secs 
+Placer score =  82610
+Finished Placer Phase 2.  REAL time: 9 secs 
 
 
 
@@ -113,8 +113,8 @@ Global Clock Resources:
   DCC        : 0 out of 8 (0%)
 
 Global Clocks:
-  PRIMARY &quot;C14M_c&quot; from comp &quot;C14M&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 84
-  SECONDARY &quot;N_576_i&quot; from F1 on comp &quot;SLICE_20&quot; on site &quot;R7C12C&quot;, clk load = 0, ce load = 17, sr load = 0
+  PRIMARY &quot;C14M_c&quot; from comp &quot;C14M&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 89
+  SECONDARY &quot;N_187_i&quot; from F1 on comp &quot;ram2e_ufm/SLICE_130&quot; on site &quot;R7C12C&quot;, clk load = 0, ce load = 11, sr load = 0
 
   PRIMARY  : 1 out of 8 (12%)
   SECONDARY: 1 out of 8 (12%)
@@ -126,16 +126,16 @@ Edge Clocks:
 
 
 I/O Usage Summary (final):
-   70 + 4(JTAG) out of 108 (68.5%) PIO sites used.
-   70 + 4(JTAG) out of 80 (92.5%) bonded PIO sites used.
-   Number of PIO comps: 70; differential: 0.
+   69 + 4(JTAG) out of 108 (67.6%) PIO sites used.
+   69 + 4(JTAG) out of 80 (91.3%) bonded PIO sites used.
+   Number of PIO comps: 69; differential: 0.
    Number of Vref pins used: 0.
 
 I/O Bank Usage Summary:
 +----------+----------------+------------+-----------+
 | I/O Bank | Usage          | Bank Vccio | Bank Vref |
 +----------+----------------+------------+-----------+
-| 0        | 12 / 19 ( 63%) | 3.3V       | -         |
+| 0        | 11 / 19 ( 57%) | 3.3V       | -         |
 | 1        | 20 / 21 ( 95%) | 3.3V       | -         |
 | 2        | 18 / 20 ( 90%) | 3.3V       | -         |
 | 3        | 20 / 20 (100%) | 3.3V       | -         |
@@ -145,13 +145,13 @@ Total placer CPU time: 7 secs
 
 Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
 
-0 connections routed; 1126 unrouted.
+0 connections routed; 1330 unrouted.
 Starting router resource preassignment
 WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
 
 Completed router resource preassignment. Real time: 13 secs 
 
-Start NBR router at 05:35:04 09/21/23
+Start NBR router at 23:10:14 12/28/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -166,32 +166,32 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:35:05 09/21/23
+Start NBR special constraint process at 23:10:14 12/28/23
 
-Start NBR section for initial routing at 05:35:05 09/21/23
+Start NBR section for initial routing at 23:10:14 12/28/23
 Level 4, iteration 1
-13(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack&lt;setup&gt;: 57.121ns/0.000ns; real time: 14 secs 
+19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: 58.075ns/0.000ns; real time: 14 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:35:05 09/21/23
+Start NBR section for normal routing at 23:10:15 12/28/23
 Level 4, iteration 1
-4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack&lt;setup&gt;: 57.121ns/0.000ns; real time: 14 secs 
+3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: 58.069ns/0.000ns; real time: 14 secs 
 Level 4, iteration 2
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack&lt;setup&gt;: 57.121ns/0.000ns; real time: 14 secs 
+Estimated worst slack/total negative slack&lt;setup&gt;: 58.069ns/0.000ns; real time: 14 secs 
 
-Start NBR section for setup/hold timing optimization with effort level 3 at 05:35:05 09/21/23
+Start NBR section for setup/hold timing optimization with effort level 3 at 23:10:15 12/28/23
 
-Start NBR section for re-routing at 05:35:05 09/21/23
+Start NBR section for re-routing at 23:10:15 12/28/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack&lt;setup&gt;: 57.121ns/0.000ns; real time: 14 secs 
+Estimated worst slack/total negative slack&lt;setup&gt;: 58.069ns/0.000ns; real time: 14 secs 
 
-Start NBR section for post-routing at 05:35:05 09/21/23
+Start NBR section for post-routing at 23:10:15 12/28/23
 
 End NBR router with 0 unrouted connection
 
@@ -199,17 +199,17 @@ NBR Summary
 -----------
   Number of unrouted connections : 0 (0.00%)
   Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack&lt;setup&gt; : 57.121ns
+  Estimated worst slack&lt;setup&gt; : 58.069ns
   Timing score&lt;setup&gt; : 0
 -----------
 Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
 
 
 
-Total CPU time 14 secs 
+Total CPU time 13 secs 
 Total REAL time: 15 secs 
 Completely routed.
-End of route.  1126 routed (100.00%); 0 unrouted.
+End of route.  1330 routed (100.00%); 0 unrouted.
 
 Hold time timing score: 0, hold timing errors: 0
 
@@ -223,13 +223,13 @@ All signals are completely routed.
 
 PAR_SUMMARY::Run status = Completed
 PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack&lt;setup/&lt;ns&gt;&gt; = 57.121
+PAR_SUMMARY::Worst  slack&lt;setup/&lt;ns&gt;&gt; = 58.069
 PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
-PAR_SUMMARY::Worst  slack&lt;hold /&lt;ns&gt;&gt; = 0.333
+PAR_SUMMARY::Worst  slack&lt;hold /&lt;ns&gt;&gt; = 0.342
 PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 15 secs 
+Total CPU  time to completion: 14 secs 
 Total REAL time to completion: 15 secs 
 
 par done!
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt
index 9586c36..400c070 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt
@@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
 
 Implementation : impl1
 
-# Written on Thu Sep 21 05:34:37 2023
+# Written on Thu Dec 28 23:09:48 2023
 
 ##### FILES SYNTAX CHECKED ##############################################
 Constraint File(s):      "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
@@ -33,7 +33,7 @@ Clock Summary
           Start      Requested     Requested     Clock        Clock                Clock
 Level     Clock      Frequency     Period        Type         Group                Load 
 ----------------------------------------------------------------------------------------
-0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     111  
+0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     122  
                                                                                         
 0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
 ========================================================================================
@@ -45,7 +45,7 @@ Clock Load Summary
            Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin     
 Clock      Load      Pin            Seq Example     Seq Example       Comb Example      
 ----------------------------------------------------------------------------------------
-C14M       111       C14M(port)     wb_rst.C        -                 un1_C14M.I[0](inv)
+C14M       122       C14M(port)     DOEEN.C         -                 un1_C14M.I[0](inv)
                                                                                         
 System     0         -              -               -                 -                 
 ========================================================================================
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html
index 03c1e47..fd74f38 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html
@@ -62,7 +62,7 @@
 </TR>
 <TR>
 <TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
-<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/09/21 05:35:26</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/12/28 23:10:34</SPAN></TD>
 </TR>
 <TR>
 <TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html
index 9195ff3..1f2c0a9 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html
@@ -12,7 +12,7 @@
 #OS: Windows 8 6.2
 #Hostname: ZANEMACWIN11
 
-# Thu Sep 21 05:34:34 2023
+# Thu Dec 28 23:09:45 2023
 
 #Implementation: impl1
 
@@ -57,45 +57,50 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
+@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
+@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
 @I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
 Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
 Selecting top level module RAM2E
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
 Running optimization stage 1 on VHI .......
-Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
 Running optimization stage 1 on VLO .......
-Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
 Running optimization stage 1 on EFB .......
 Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
 @N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
 Running optimization stage 1 on REFB .......
 Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
+@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
+Running optimization stage 1 on RAM2E_UFM .......
+Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
 Running optimization stage 1 on RAM2E .......
 Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
 Running optimization stage 2 on RAM2E .......
+@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
 Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Running optimization stage 2 on RAM2E_UFM .......
+@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
+Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
 Running optimization stage 2 on REFB .......
-Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
 Running optimization stage 2 on EFB .......
-Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
 Running optimization stage 2 on VLO .......
-Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
 Running optimization stage 2 on VHI .......
-Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
 
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB)
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:34 2023
+# Thu Dec 28 23:09:45 2023
 
 ###########################################################]
 ###########################################################[
@@ -122,7 +127,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:34 2023
+# Thu Dec 28 23:09:46 2023
 
 ###########################################################]
 
@@ -132,12 +137,12 @@ For a summary of runtime and memory usage for all design units, please see file:
 
 @END
 
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:34 2023
+# Thu Dec 28 23:09:46 2023
 
 ###########################################################]
 ###########################################################[
@@ -165,10 +170,10 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:36 2023
+# Thu Dec 28 23:09:47 2023
 
 ###########################################################]
-# Thu Sep 21 05:34:36 2023
+# Thu Dec 28 23:09:47 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -187,10 +192,10 @@ Implementation : impl1
 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 141MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
 
 Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
 @L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt 
@@ -199,10 +204,10 @@ See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
 
 
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
 
 
 Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
@@ -210,46 +215,45 @@ Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00
 
 Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
 
-@N: FX493 |Applying initial value "0" on instance PHI1reg.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance DOEEN.
-@N: FX493 |Applying initial value "0" on instance RWSel.
-@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
-@N: FX493 |Applying initial value "1" on instance DQMH.
-@N: FX493 |Applying initial value "0" on instance Ready.
 @N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 @N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
+@N: FX493 |Applying initial value "0" on instance PHI1r.
+@N: FX493 |Applying initial value "0" on instance RWSel.
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
 @N: FX493 |Applying initial value "0" on instance CmdLEDGet.
 @N: FX493 |Applying initial value "0" on instance CmdLEDSet.
 @N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
 @N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
-@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "0000" on instance S[3:0].
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "1" on instance DQMH.
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
 @N: FX493 |Applying initial value "1" on instance DQML.
-@N: FX493 |Applying initial value "0" on instance CKE.
-@N: FX493 |Applying initial value "1" on instance nCS.
-@N: FX493 |Applying initial value "1" on instance nRAS.
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "0000" on instance S[3:0].
+@N: FX493 |Applying initial value "1" on instance CKE.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+@N: FX493 |Applying initial value "1" on instance nRWEout.
 @N: FX493 |Applying initial value "1" on instance nCAS.
+@N: FX493 |Applying initial value "1" on instance nCASout.
+@N: FX493 |Applying initial value "1" on instance nRAS.
+@N: FX493 |Applying initial value "1" on instance nRASout.
 
-Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
 @N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E 
 
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
 
 
 
@@ -259,7 +263,7 @@ Clock Summary
           Start      Requested     Requested     Clock        Clock                Clock
 Level     Clock      Frequency     Period        Type         Group                Load 
 ----------------------------------------------------------------------------------------
-0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     111  
+0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     122  
                                                                                         
 0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
 ========================================================================================
@@ -272,7 +276,7 @@ Clock Load Summary
            Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin     
 Clock      Load      Pin            Seq Example     Seq Example       Comb Example      
 ----------------------------------------------------------------------------------------
-C14M       111       C14M(port)     wb_rst.C        -                 un1_C14M.I[0](inv)
+C14M       122       C14M(port)     DOEEN.C         -                 un1_C14M.I[0](inv)
                                                                                         
 System     0         -              -               -                 -                 
 ========================================================================================
@@ -289,14 +293,14 @@ For details review file gcc_ICG_report.rpt
 
 #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
 
-1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
+1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
 0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
 =========================== Non-Gated/Non-Generated Clocks ============================
 Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
 ---------------------------------------------------------------------------------------
-@KP:ckid0_0       C14M                port                   111        nCAS           
+@KP:ckid0_0       C14M                port                   122        nRAS           
 =======================================================================================
 
 
@@ -317,11 +321,11 @@ Pre-mapping successful!
 
 At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
 
-Process took 0h:00m:02s realtime, 0h:00m:01s cputime
-# Thu Sep 21 05:34:38 2023
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Thu Dec 28 23:09:49 2023
 
 ###########################################################]
-# Thu Sep 21 05:34:38 2023
+# Thu Dec 28 23:09:49 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -340,97 +344,97 @@ Implementation : impl1
 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
 
 
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
 
 
 Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
 
 
 
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 179MB peak: 179MB)
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
 
-@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
-@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
 
-Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
 
-@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
+@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 
 Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
 Available hyper_sources - for debug and ip models
 	None Found
 
 
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
 
 
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
 
 
-Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
 
 
-Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
 
 Pass		 CPU time		Worst Slack		Luts / Registers
 ------------------------------------------------------------
-   1		0h:00m:02s		    29.35ns		 222 /       111
+   1		0h:00m:02s		    33.71ns		 284 /       122
 
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
 
 @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
 
-Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
 
 
-Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
 
 Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
 
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB)
 
 Writing EDIF Netlist and constraint files
 @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
 
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
 
 
-Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
 
 
-Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
+Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB)
 
 @W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
 @N: MT615 |Found clock C14M with period 69.84ns 
 
 
 ##### START OF TIMING REPORT #####[
-# Timing report written on Thu Sep 21 05:34:44 2023
+# Timing report written on Thu Dec 28 23:09:54 2023
 #
 
 
@@ -450,12 +454,12 @@ Performance Summary
 *******************
 
 
-Worst slack in design: 31.782
+Worst slack in design: 33.707
 
                    Requested     Estimated     Requested     Estimated                Clock        Clock           
 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
 -------------------------------------------------------------------------------------------------------------------
-C14M               14.3 MHz      131.4 MHz     69.841        7.610         31.782     declared     default_clkgroup
+C14M               14.3 MHz      128.0 MHz     69.841        7.813         33.707     declared     default_clkgroup
 System             100.0 MHz     NA            10.000        NA            67.088     system       system_clkgroup 
 ===================================================================================================================
 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
@@ -473,7 +477,7 @@ Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  sl
 ----------------------------------------------------------------------------------------------------------
 System    C14M    |  69.841      67.088  |  No paths    -      |  No paths    -       |  No paths    -    
 C14M      System  |  69.841      68.797  |  No paths    -      |  No paths    -       |  No paths    -    
-C14M      C14M    |  69.841      62.231  |  No paths    -      |  34.920      31.782  |  No paths    -    
+C14M      C14M    |  69.841      62.028  |  No paths    -      |  34.920      33.707  |  No paths    -    
 ==========================================================================================================
  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
@@ -496,41 +500,41 @@ Detailed Report for Clock: C14M
 Starting Points with Worst Slack
 ********************************
 
-             Starting                                     Arrival           
-Instance     Reference     Type        Pin     Net        Time        Slack 
-             Clock                                                          
-----------------------------------------------------------------------------
-S[2]         C14M          FD1S3AX     Q       S[2]       1.350       31.782
-S[3]         C14M          FD1S3AX     Q       S[3]       1.350       31.782
-S[0]         C14M          FD1S3AX     Q       S[0]       1.312       31.820
-S[1]         C14M          FD1S3AX     Q       S[1]       1.280       31.852
-FS[9]        C14M          FD1S3AX     Q       FS[9]      1.284       62.425
-FS[11]       C14M          FD1S3AX     Q       FS[11]     1.276       62.433
-FS[8]        C14M          FD1S3AX     Q       FS[8]      1.260       62.449
-FS[12]       C14M          FD1S3AX     Q       FS[12]     1.288       62.525
-FS[10]       C14M          FD1S3AX     Q       FS[10]     1.280       62.533
-RWSel        C14M          FD1P3AX     Q       RWSel      1.276       63.482
-============================================================================
+             Starting                                    Arrival           
+Instance     Reference     Type        Pin     Net       Time        Slack 
+             Clock                                                         
+---------------------------------------------------------------------------
+RA[0]        C14M          FD1P3AX     Q       RA[0]     1.108       33.707
+RA[3]        C14M          FD1P3AX     Q       RA[3]     1.108       33.707
+RA[1]        C14M          FD1P3AX     Q       RA[1]     1.044       33.771
+RA[2]        C14M          FD1P3AX     Q       RA[2]     1.044       33.771
+RA[4]        C14M          FD1P3AX     Q       RA[4]     1.044       33.771
+RA[5]        C14M          FD1P3AX     Q       RA[5]     1.044       33.771
+RA[6]        C14M          FD1P3AX     Q       RA[6]     1.044       33.771
+RA[7]        C14M          FD1P3AX     Q       RA[7]     1.044       33.771
+RA[8]        C14M          FD1P3AX     Q       RA[8]     1.044       33.771
+RA[9]        C14M          FD1P3AX     Q       RA[9]     1.044       33.771
+===========================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-                Starting                                       Required           
-Instance        Reference     Type         Pin     Net         Time         Slack 
-                Clock                                                             
-----------------------------------------------------------------------------------
-Dout_0io[0]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[1]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[2]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[3]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[4]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[5]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[6]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[7]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Vout_0io[0]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
-Vout_0io[1]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
-==================================================================================
+                 Starting                                     Required           
+Instance         Reference     Type         Pin     Net       Time         Slack 
+                 Clock                                                           
+---------------------------------------------------------------------------------
+RAout_0io[0]     C14M          OFS1P3DX     D       RA[0]     34.815       33.707
+RAout_0io[3]     C14M          OFS1P3DX     D       RA[3]     34.815       33.707
+RAout_0io[1]     C14M          OFS1P3DX     D       RA[1]     34.815       33.771
+RAout_0io[2]     C14M          OFS1P3DX     D       RA[2]     34.815       33.771
+RAout_0io[4]     C14M          OFS1P3DX     D       RA[4]     34.815       33.771
+RAout_0io[5]     C14M          OFS1P3DX     D       RA[5]     34.815       33.771
+RAout_0io[6]     C14M          OFS1P3DX     D       RA[6]     34.815       33.771
+RAout_0io[7]     C14M          OFS1P3DX     D       RA[7]     34.815       33.771
+RAout_0io[8]     C14M          OFS1P3DX     D       RA[8]     34.815       33.771
+RAout_0io[9]     C14M          OFS1P3DX     D       RA[9]     34.815       33.771
+=================================================================================
 
 
 
@@ -540,30 +544,27 @@ Worst Path Information
 
 Path information for path number 1: 
       Requested Period:                      34.920
-    - Setup time:                            0.472
+    - Setup time:                            0.106
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         34.449
+    = Required time:                         34.815
 
-    - Propagation time:                      2.667
+    - Propagation time:                      1.108
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     31.782
+    = Slack (critical) :                     33.707
 
-    Number of logic level(s):                1
-    Starting point:                          S[2] / Q
-    Ending point:                            Dout_0io[0] / SP
+    Number of logic level(s):                0
+    Starting point:                          RA[0] / Q
+    Ending point:                            RAout_0io[0] / D
     The start point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
     The end   point is clocked by            C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
 
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-S[2]                FD1S3AX      Q        Out     1.350     1.350 r     -         
-S[2]                Net          -        -       -         -           48        
-S_RNII9DO1_2[1]     ORCALUT4     B        In      0.000     1.350 r     -         
-S_RNII9DO1_2[1]     ORCALUT4     Z        Out     1.317     2.667 r     -         
-N_576_i             Net          -        -       -         -           18        
-Dout_0io[0]         OFS1P3DX     SP       In      0.000     2.667 r     -         
-==================================================================================
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+RA[0]              FD1P3AX      Q        Out     1.108     1.108 r     -         
+RA[0]              Net          -        -       -         -           3         
+RAout_0io[0]       OFS1P3DX     D        In      0.000     1.108 r     -         
+=================================================================================
 
 
 
@@ -577,40 +578,40 @@ Detailed Report for Clock: System
 Starting Points with Worst Slack
 ********************************
 
-                     Starting                                          Arrival           
-Instance             Reference     Type     Pin         Net            Time        Slack 
-                     Clock                                                               
------------------------------------------------------------------------------------------
-ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
-ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
-=========================================================================================
+                               Starting                                          Arrival           
+Instance                       Reference     Type     Pin         Net            Time        Slack 
+                               Clock                                                               
+---------------------------------------------------------------------------------------------------
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
+===================================================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-               Starting                                                          Required           
-Instance       Reference     Type        Pin     Net                             Time         Slack 
-               Clock                                                                                
-----------------------------------------------------------------------------------------------------
-RWMask[0]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[1]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[2]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[3]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[4]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[5]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[6]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[7]      System        FD1P3AX     SP      N_88                            69.369       67.088
-LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0[0]     69.369       67.736
-wb_cyc_stb     System        FD1P3AX     SP      N_104                           69.369       67.736
-====================================================================================================
+                         Starting                                                                  Required           
+Instance                 Reference     Type        Pin     Net                                     Time         Slack 
+                         Clock                                                                                        
+----------------------------------------------------------------------------------------------------------------------
+ram2e_ufm.RWMask[0]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[1]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[2]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[3]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[4]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[5]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[6]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[7]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0_0[0]           69.369       67.736
+ram2e_ufm.wb_cyc_stb     System        FD1P3AX     SP      un1_CmdSetRWBankFFChip13_1_i_0_0[0]     69.369       67.736
+======================================================================================================================
 
 
 
@@ -630,24 +631,24 @@ Path information for path number 1:
     = Slack (non-critical) :                 67.088
 
     Number of logic level(s):                2
-    Starting point:                          ufmefb.EFBInst_0 / WBACKO
-    Ending point:                            RWMask[0] / SP
+    Starting point:                          ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
+    Ending point:                            ram2e_ufm.RWMask[0] / SP
     The start point is clocked by            System [rising]
     The end   point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
 
-Instance / Net                                     Pin        Pin               Arrival     No. of    
-Name                                  Type         Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
-ufmefb.EFBInst_0                      EFB          WBACKO     Out     0.000     0.000 r     -         
-wb_ack                                Net          -          -       -         -           5         
-un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     A          In      0.000     0.000 r     -         
-un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     Z          Out     1.017     1.017 r     -         
-un1_RWMask_0_sqmuxa_1_i_a2_0_1[0]     Net          -          -       -         -           1         
-un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
-un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
-N_88                                  Net          -          -       -         -           8         
-RWMask[0]                             FD1P3AX      SP         In      0.000     2.282 r     -         
-======================================================================================================
+Instance / Net                                                 Pin        Pin               Arrival     No. of    
+Name                                              Type         Name       Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------------------------------------
+ram2e_ufm.ufmefb.EFBInst_0                        EFB          WBACKO     Out     0.000     0.000 r     -         
+wb_ack                                            Net          -          -       -         -           5         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     B          In      0.000     0.000 r     -         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     Z          Out     1.017     1.017 r     -         
+un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]               Net          -          -       -         -           1         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
+un1_RWMask_0_sqmuxa_1_i_0_0[0]                    Net          -          -       -         -           8         
+ram2e_ufm.RWMask[0]                               FD1P3AX      SP         In      0.000     2.282 r     -         
+==================================================================================================================
 
 
 
@@ -655,46 +656,48 @@ RWMask[0]                             FD1P3AX      SP         In      0.000
 
 Timing exceptions that could not be applied
 
-Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
 
 
-Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
 
 ---------------------------------------
 Resource Usage Report
 Part: lcmxo2_1200hc-4
 
-Register bits: 111 of 1280 (9%)
+Register bits: 122 of 1280 (10%)
 PIC Latch:       0
-I/O cells:       70
+I/O cells:       69
 
 
 Details:
 BB:             8
 CCU2D:          9
 EFB:            1
-FD1P3AX:        48
+FD1P3AX:        61
 FD1P3IX:        1
-FD1S3AX:        22
-FD1S3IX:        4
+FD1S3AX:        21
+FD1S3AY:        4
+FD1S3IX:        6
 GSR:            1
-IB:             22
+IB:             21
 IFS1P3DX:       1
 INV:            1
 OB:             40
-OFS1P3BX:       6
-OFS1P3DX:       27
+OFS1P3BX:       5
+OFS1P3DX:       21
 OFS1P3IX:       2
-ORCALUT4:       221
+ORCALUT4:       277
+PFUMX:          3
 PUR:            1
-VHI:            2
-VLO:            2
+VHI:            3
+VLO:            3
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 211MB)
+At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 79MB peak: 217MB)
 
-Process took 0h:00m:06s realtime, 0h:00m:04s cputime
-# Thu Sep 21 05:34:44 2023
+Process took 0h:00m:04s realtime, 0h:00m:04s cputime
+# Thu Dec 28 23:09:54 2023
 
 ###########################################################]
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html
index 8c77acf..d1f1a08 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 <A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
-Thu Sep 21 05:34:48 2023
+Thu Dec 28 23:09:59 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -41,8 +41,8 @@ Report level:    verbose report, limited to 1 item per preference
 
 <A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
 
-<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1491 items scored, 0 timing errors detected.
-Report:   87.268MHz is the maximum frequency for this preference.
+<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1611 items scored, 0 timing errors detected.
+Report:   90.967MHz is the maximum frequency for this preference.
 
 BLOCK ASYNCPATHS
 BLOCK RESETPATHS
@@ -52,48 +52,48 @@ BLOCK RESETPATHS
 
 ================================================================================
 <A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 58.471ns
+Passed: The following path meets requirements by 58.937ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              11.306ns  (30.3% logic, 69.7% route), 7 logic levels.
+   Delay:              10.827ns  (31.6% logic, 68.4% route), 7 logic levels.
 
  Constraint Details:
 
-     11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
-      0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns
 
  Physical Path Details:
 
-      Data path SLICE_3 to nRWE_MGIOL:
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452    SLICE_3.CLK to     SLICE_3.Q0 SLICE_3 (from C14M_c)
-ROUTE        19   e 1.234     SLICE_3.Q0 to    SLICE_64.A1 FS[11]
-CTOF_DEL    ---     0.495    SLICE_64.A1 to    SLICE_64.F1 SLICE_64
-ROUTE         4   e 1.234    SLICE_64.F1 to    SLICE_97.D0 N_577
-CTOF_DEL    ---     0.495    SLICE_97.D0 to    SLICE_97.F0 SLICE_97
-ROUTE         3   e 1.234    SLICE_97.F0 to    SLICE_75.D1 N_489
-CTOF_DEL    ---     0.495    SLICE_75.D1 to    SLICE_75.F1 SLICE_75
-ROUTE         3   e 0.480    SLICE_75.F1 to    SLICE_75.A0 N_628
-CTOF_DEL    ---     0.495    SLICE_75.A0 to    SLICE_75.F0 SLICE_75
-ROUTE         2   e 1.234    SLICE_75.F0 to    SLICE_71.C1 N_640
-CTOF_DEL    ---     0.495    SLICE_71.C1 to    SLICE_71.F1 SLICE_71
-ROUTE         1   e 1.234    SLICE_71.F1 to   SLICE_115.A0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495   SLICE_115.A0 to   SLICE_115.F0 SLICE_115
-ROUTE         1   e 1.234   SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
+REG_DEL     ---     0.452   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from C14M_c)
+ROUTE        50   e 1.234    SLICE_34.Q0 to    SLICE_35.A0 S[2]
+CTOF_DEL    ---     0.495    SLICE_35.A0 to    SLICE_35.F0 SLICE_35
+ROUTE         7   e 1.234    SLICE_35.F0 to *m/SLICE_80.D1 N_551
+CTOF_DEL    ---     0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
+ROUTE         8   e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
+ROUTE         5   e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
+ROUTE         1   e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
+CTOF_DEL    ---     0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
+ROUTE         1   e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
+ROUTE         1   e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   11.306   (30.3% logic, 69.7% route), 7 logic levels.
+                   10.827   (31.6% logic, 68.4% route), 7 logic levels.
 
-Report:   87.268MHz is the maximum frequency for this preference.
+Report:   90.967MHz is the maximum frequency for this preference.
 
 <A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
 --------------
@@ -101,7 +101,7 @@ Report:   87.268MHz is the maximum frequency for this preference.
 Preference                              |   Constraint|       Actual|Levels
 ----------------------------------------------------------------------------
                                         |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   87.268 MHz|   7  
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   90.967 MHz|   7  
                                         |             |             |
 ----------------------------------------------------------------------------
 
@@ -114,7 +114,7 @@ All preferences were met.
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -124,11 +124,11 @@ Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 --------------------------------------------------------------------------------
 <A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
-Thu Sep 21 05:34:49 2023
+Thu Dec 28 23:09:59 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -147,7 +147,7 @@ Report level:    verbose report, limited to 1 item per preference
 
 <A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
 
-<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1491 items scored, 0 timing errors detected.
+<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1611 items scored, 0 timing errors detected.
 
 BLOCK ASYNCPATHS
 BLOCK RESETPATHS
@@ -157,7 +157,7 @@ BLOCK RESETPATHS
 
 ================================================================================
 <A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
@@ -182,7 +182,7 @@ Passed: The following path meets requirements by 0.447ns
 
    Name    Fanout   Delay (ns)          Site               Resource
 REG_DEL     ---     0.133    SLICE_0.CLK to     SLICE_0.Q1 SLICE_0 (from C14M_c)
-ROUTE         5   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
+ROUTE         6   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
 CTOF_DEL    ---     0.101     SLICE_0.A1 to     SLICE_0.F1 SLICE_0
 ROUTE         1   e 0.001     SLICE_0.F1 to    SLICE_0.DI1 FS_s[0] (to C14M_c)
                   --------
@@ -207,7 +207,7 @@ All preferences were met.
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -217,7 +217,7 @@ Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html
index 8c6da61..2a571cc 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 <A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
-Thu Sep 21 05:35:07 2023
+Thu Dec 28 23:10:17 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -41,8 +41,8 @@ Report level:    verbose report, limited to 10 items per preference
 
 <A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
 
-<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1491 items scored, 0 timing errors detected.
-Report:   78.070MHz is the maximum frequency for this preference.
+<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1611 items scored, 0 timing errors detected.
+Report:   84.310MHz is the maximum frequency for this preference.
 
 BLOCK ASYNCPATHS
 BLOCK RESETPATHS
@@ -52,516 +52,548 @@ BLOCK RESETPATHS
 
 ================================================================================
 <A name="par_twr_pref_0_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 57.121ns
+Passed: The following path meets requirements by 58.069ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[8]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              12.829ns  (26.7% logic, 73.3% route), 7 logic levels.
+   Delay:              11.695ns  (29.3% logic, 70.7% route), 7 logic levels.
 
  Constraint Details:
 
-     12.829ns physical path delay SLICE_5 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.121ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9A.CLK to       R5C9A.Q1 SLICE_5 (from C14M_c)
-ROUTE        15     2.743       R5C9A.Q1 to       R4C7B.B1 FS[8]
-CTOF_DEL    ---     0.495       R4C7B.B1 to       R4C7B.F1 SLICE_64
-ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
-CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
-ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
-CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
-ROUTE         3     0.453      R4C11C.F1 to      R4C11C.C0 N_628
-CTOF_DEL    ---     0.495      R4C11C.C0 to      R4C11C.F0 SLICE_75
-ROUTE         2     0.652      R4C11C.F0 to      R5C11B.D1 N_640
-CTOF_DEL    ---     0.495      R5C11B.D1 to      R5C11B.F1 SLICE_71
-ROUTE         1     1.023      R5C11B.F1 to      R5C13A.B0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495      R5C13A.B0 to      R5C13A.F0 SLICE_115
-ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   12.829   (26.7% logic, 73.3% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R5C9A.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
-                  --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.346ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        wb_dati[6]  (to C14M_c +)
-
-   Delay:              12.418ns  (27.6% logic, 72.4% route), 7 logic levels.
-
- Constraint Details:
-
-     12.418ns physical path delay SLICE_33 to SLICE_43 meets
+     11.695ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
       0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.346ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.069ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to SLICE_43:
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     3.112      R3C11C.Q0 to      R5C12C.B0 S[0]
-CTOF_DEL    ---     0.495      R5C12C.B0 to      R5C12C.F0 SLICE_47
-ROUTE         7     2.060      R5C12C.F0 to       R3C7C.C1 S_RNII9DO1[1]
-CTOF_DEL    ---     0.495       R3C7C.C1 to       R3C7C.F1 SLICE_86
-ROUTE         5     1.174       R3C7C.F1 to       R4C5A.D1 N_484
-CTOF_DEL    ---     0.495       R4C5A.D1 to       R4C5A.F1 SLICE_74
-ROUTE         3     0.984       R4C5A.F1 to       R4C5A.A0 N_642
-CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 SLICE_74
-ROUTE         2     0.665       R4C5A.F0 to       R4C5C.A0 N_346
-CTOF_DEL    ---     0.495       R4C5C.A0 to       R4C5C.F0 SLICE_84
-ROUTE         1     1.001       R4C5C.F0 to       R3C5D.B0 wb_dati_7_0_1[6]
-CTOF_DEL    ---     0.495       R3C5D.B0 to       R3C5D.F0 SLICE_43
-ROUTE         1     0.000       R3C5D.F0 to      R3C5D.DI0 wb_dati_7[6] (to C14M_c)
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
+ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
+CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.755       R3C6C.F1 to       R2C7D.A0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R2C7D.A0 to       R2C7D.F0 ram2e_ufm/SLICE_99
+ROUTE         1     1.023       R2C7D.F0 to       R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0]
+CTOF_DEL    ---     0.495       R3C7A.B0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   12.418   (27.6% logic, 72.4% route), 7 logic levels.
+                   11.695   (29.3% logic, 70.7% route), 7 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_33:
+      Source Clock Path C14M to SLICE_34:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_43:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R3C5D.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 57.382ns
+Passed: The following path meets requirements by 58.138ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[8]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              12.568ns  (23.3% logic, 76.7% route), 6 logic levels.
+   Delay:              11.626ns  (29.4% logic, 70.6% route), 7 logic levels.
 
  Constraint Details:
 
-     12.568ns physical path delay SLICE_5 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.382ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9A.CLK to       R5C9A.Q1 SLICE_5 (from C14M_c)
-ROUTE        15     2.743       R5C9A.Q1 to       R4C7B.B1 FS[8]
-CTOF_DEL    ---     0.495       R4C7B.B1 to       R4C7B.F1 SLICE_64
-ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
-CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
-ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
-CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
-ROUTE         3     1.040      R4C11C.F1 to      R5C11D.B0 N_628
-CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_76
-ROUTE         3     1.322      R5C11D.F0 to      R5C13A.A0 nCAS_0_sqmuxa
-CTOF_DEL    ---     0.495      R5C13A.A0 to      R5C13A.F0 SLICE_115
-ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   12.568   (23.3% logic, 76.7% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R5C9A.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
-                  --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.636ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[9]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
-
-   Delay:              12.314ns  (27.8% logic, 72.2% route), 7 logic levels.
-
- Constraint Details:
-
-     12.314ns physical path delay SLICE_4 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.636ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_4 (from C14M_c)
-ROUTE        21     2.228       R5C9B.Q0 to       R4C7B.A1 FS[9]
-CTOF_DEL    ---     0.495       R4C7B.A1 to       R4C7B.F1 SLICE_64
-ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
-CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
-ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
-CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
-ROUTE         3     0.453      R4C11C.F1 to      R4C11C.C0 N_628
-CTOF_DEL    ---     0.495      R4C11C.C0 to      R4C11C.F0 SLICE_75
-ROUTE         2     0.652      R4C11C.F0 to      R5C11B.D1 N_640
-CTOF_DEL    ---     0.495      R5C11B.D1 to      R5C11B.F1 SLICE_71
-ROUTE         1     1.023      R5C11B.F1 to      R5C13A.B0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495      R5C13A.B0 to      R5C13A.F0 SLICE_115
-ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   12.314   (27.8% logic, 72.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R5C9B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
-                  --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.645ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        wb_adr[0]  (to C14M_c +)
-
-   Delay:              12.119ns  (24.2% logic, 75.8% route), 6 logic levels.
-
- Constraint Details:
-
-     12.119ns physical path delay SLICE_33 to SLICE_35 meets
+     11.626ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
       0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.645ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.138ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to SLICE_35:
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     3.112      R3C11C.Q0 to      R5C12C.B0 S[0]
-CTOF_DEL    ---     0.495      R5C12C.B0 to      R5C12C.F0 SLICE_47
-ROUTE         7     2.060      R5C12C.F0 to       R4C7C.C1 S_RNII9DO1[1]
-CTOF_DEL    ---     0.495       R4C7C.C1 to       R4C7C.F1 SLICE_56
-ROUTE         6     2.374       R4C7C.F1 to       R5C7D.A0 N_452
-CTOF_DEL    ---     0.495       R5C7D.A0 to       R5C7D.F0 SLICE_92
-ROUTE         1     0.645       R5C7D.F0 to       R5C5A.D0 wb_adr_7_0_0[0]
-CTOF_DEL    ---     0.495       R5C5A.D0 to       R5C5A.F0 SLICE_85
-ROUTE         1     1.001       R5C5A.F0 to       R4C5B.B0 wb_adr_7_0_4[0]
-CTOF_DEL    ---     0.495       R4C5B.B0 to       R4C5B.F0 SLICE_35
-ROUTE         1     0.000       R4C5B.F0 to      R4C5B.DI0 wb_adr_7[0] (to C14M_c)
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
+ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
+CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.962       R3C6C.F1 to       R3C7C.C0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R3C7C.C0 to       R3C7C.F0 ram2e_ufm/SLICE_126
+ROUTE         1     0.747       R3C7C.F0 to       R3C7A.C0 ram2e_ufm/N_753
+CTOF_DEL    ---     0.495       R3C7A.C0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   12.119   (24.2% logic, 75.8% route), 6 logic levels.
+                   11.626   (29.4% logic, 70.6% route), 7 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_33:
+      Source Clock Path C14M to SLICE_34:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_35:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R4C5B.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 57.783ns
+Passed: The following path meets requirements by 58.247ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[7]  (to C14M_c +)
 
-   Delay:              12.167ns  (28.1% logic, 71.9% route), 7 logic levels.
+   Delay:              11.517ns  (25.4% logic, 74.6% route), 6 logic levels.
 
  Constraint Details:
 
-     12.167ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     11.517ns physical path delay SLICE_34 to ram2e_ufm/SLICE_55 meets
      69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.783ns
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.247ns
 
  Physical Path Details:
 
-      Data path SLICE_3 to nRWE_MGIOL:
+      Data path SLICE_34 to ram2e_ufm/SLICE_55:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R5C9C.CLK to       R5C9C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.081       R5C9C.Q0 to       R4C7B.C1 FS[11]
-CTOF_DEL    ---     0.495       R4C7B.C1 to       R4C7B.F1 SLICE_64
-ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
-CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
-ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
-CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
-ROUTE         3     0.453      R4C11C.F1 to      R4C11C.C0 N_628
-CTOF_DEL    ---     0.495      R4C11C.C0 to      R4C11C.F0 SLICE_75
-ROUTE         2     0.652      R4C11C.F0 to      R5C11B.D1 N_640
-CTOF_DEL    ---     0.495      R5C11B.D1 to      R5C11B.F1 SLICE_71
-ROUTE         1     1.023      R5C11B.F1 to      R5C13A.B0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495      R5C13A.B0 to      R5C13A.F0 SLICE_115
-ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
+ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
+CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.631      R5C10B.F1 to       R3C6A.A1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 ram2e_ufm/SLICE_81
+ROUTE         4     1.963       R3C6A.F1 to      R3C10A.C0 ram2e_ufm/N_856
+CTOF_DEL    ---     0.495      R3C10A.C0 to      R3C10A.F0 ram2e_ufm/SLICE_131
+ROUTE         1     1.535      R3C10A.F0 to       R3C6B.B1 ram2e_ufm/N_602
+CTOF_DEL    ---     0.495       R3C6B.B1 to       R3C6B.F1 ram2e_ufm/SLICE_55
+ROUTE         1     0.000       R3C6B.F1 to      R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c)
                   --------
-                   12.167   (28.1% logic, 71.9% route), 7 logic levels.
+                   11.517   (25.4% logic, 74.6% route), 6 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_3:
+      Source Clock Path C14M to SLICE_34:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to      R5C9C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to nRWE_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_55:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R3C6B.CLK C14M_c
                   --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+Passed: The following path meets requirements by 58.444ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              11.320ns  (30.2% logic, 69.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.320ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.444ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.097      R5C13B.Q1 to      R5C11D.B0 S[3]
+CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.755       R3C6C.F1 to       R2C7D.A0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R2C7D.A0 to       R2C7D.F0 ram2e_ufm/SLICE_99
+ROUTE         1     1.023       R2C7D.F0 to       R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0]
+CTOF_DEL    ---     0.495       R3C7A.B0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   11.320   (30.2% logic, 69.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.513ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              11.251ns  (30.4% logic, 69.6% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.251ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.513ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.097      R5C13B.Q1 to      R5C11D.B0 S[3]
+CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.962       R3C6C.F1 to       R3C7C.C0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R3C7C.C0 to       R3C7C.F0 ram2e_ufm/SLICE_126
+ROUTE         1     0.747       R3C7C.F0 to       R3C7A.C0 ram2e_ufm/N_753
+CTOF_DEL    ---     0.495       R3C7A.C0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   11.251   (30.4% logic, 69.6% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.525ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
    Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        Dout_0io[0]  (to C14M_c -)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+   Delay:              11.239ns  (26.0% logic, 74.0% route), 6 logic levels.
 
  Constraint Details:
 
-      6.181ns physical path delay SLICE_33 to Dout[0]_MGIOL meets
-     34.965ns delay constraint less
-     -0.173ns skew and
-      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+     11.239ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.525ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to Dout[0]_MGIOL:
+      Data path SLICE_33 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
-CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
-ROUTE        17     2.710      R7C12C.F1 to     IOL_B6B.CE N_576_i (to C14M_c)
+REG_DEL     ---     0.452     R5C13D.CLK to      R5C13D.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.500      R5C13D.Q0 to      R5C10B.C1 S[0]
+CTOF_DEL    ---     0.495      R5C10B.C1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.755       R3C6C.F1 to       R2C7D.A0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R2C7D.A0 to       R2C7D.F0 ram2e_ufm/SLICE_99
+ROUTE         1     1.023       R2C7D.F0 to       R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0]
+CTOF_DEL    ---     0.495       R3C7A.B0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+                   11.239   (26.0% logic, 74.0% route), 6 logic levels.
 
  Clock Skew Details: 
 
       Source Clock Path C14M to SLICE_33:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13D.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to Dout[0]_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to    IOL_B6B.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
                   --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+Passed: The following path meets requirements by 58.594ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
    Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        Dout_0io[1]  (to C14M_c -)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+   Delay:              11.170ns  (26.2% logic, 73.8% route), 6 logic levels.
 
  Constraint Details:
 
-      6.181ns physical path delay SLICE_33 to Dout[1]_MGIOL meets
-     34.965ns delay constraint less
-     -0.173ns skew and
-      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+     11.170ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.594ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to Dout[1]_MGIOL:
+      Data path SLICE_33 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
-CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
-ROUTE        17     2.710      R7C12C.F1 to     IOL_B4C.CE N_576_i (to C14M_c)
+REG_DEL     ---     0.452     R5C13D.CLK to      R5C13D.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.500      R5C13D.Q0 to      R5C10B.C1 S[0]
+CTOF_DEL    ---     0.495      R5C10B.C1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.962       R3C6C.F1 to       R3C7C.C0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R3C7C.C0 to       R3C7C.F0 ram2e_ufm/SLICE_126
+ROUTE         1     0.747       R3C7C.F0 to       R3C7A.C0 ram2e_ufm/N_753
+CTOF_DEL    ---     0.495       R3C7A.C0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+                   11.170   (26.2% logic, 73.8% route), 6 logic levels.
 
  Clock Skew Details: 
 
       Source Clock Path C14M to SLICE_33:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13D.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to Dout[1]_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to    IOL_B4C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
                   --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+Passed: The following path meets requirements by 58.622ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[7]  (to C14M_c +)
+
+   Delay:              11.142ns  (26.3% logic, 73.7% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.142ns physical path delay SLICE_34 to ram2e_ufm/SLICE_55 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.622ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.097      R5C13B.Q1 to      R5C11D.B0 S[3]
+CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.631      R5C10B.F1 to       R3C6A.A1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 ram2e_ufm/SLICE_81
+ROUTE         4     1.963       R3C6A.F1 to      R3C10A.C0 ram2e_ufm/N_856
+CTOF_DEL    ---     0.495      R3C10A.C0 to      R3C10A.F0 ram2e_ufm/SLICE_131
+ROUTE         1     1.535      R3C10A.F0 to       R3C6B.B1 ram2e_ufm/N_602
+CTOF_DEL    ---     0.495       R3C6B.B1 to       R3C6B.F1 ram2e_ufm/SLICE_55
+ROUTE         1     0.000       R3C6B.F1 to      R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c)
+                  --------
+                   11.142   (26.3% logic, 73.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_55:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     4.865       62.PADDI to      R3C6B.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.703ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
    Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        Dout_0io[2]  (to C14M_c -)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[7]  (to C14M_c +)
 
-   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+   Delay:              11.061ns  (22.0% logic, 78.0% route), 5 logic levels.
 
  Constraint Details:
 
-      6.181ns physical path delay SLICE_33 to Dout[2]_MGIOL meets
-     34.965ns delay constraint less
-     -0.173ns skew and
-      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+     11.061ns physical path delay SLICE_33 to ram2e_ufm/SLICE_55 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.703ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to Dout[2]_MGIOL:
+      Data path SLICE_33 to ram2e_ufm/SLICE_55:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
-CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
-ROUTE        17     2.710      R7C12C.F1 to    IOL_L10D.CE N_576_i (to C14M_c)
+REG_DEL     ---     0.452     R5C13D.CLK to      R5C13D.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.500      R5C13D.Q0 to      R5C10B.C1 S[0]
+CTOF_DEL    ---     0.495      R5C10B.C1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.631      R5C10B.F1 to       R3C6A.A1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 ram2e_ufm/SLICE_81
+ROUTE         4     1.963       R3C6A.F1 to      R3C10A.C0 ram2e_ufm/N_856
+CTOF_DEL    ---     0.495      R3C10A.C0 to      R3C10A.F0 ram2e_ufm/SLICE_131
+ROUTE         1     1.535      R3C10A.F0 to       R3C6B.B1 ram2e_ufm/N_602
+CTOF_DEL    ---     0.495       R3C6B.B1 to       R3C6B.F1 ram2e_ufm/SLICE_55
+ROUTE         1     0.000       R3C6B.F1 to      R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c)
                   --------
-                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+                   11.061   (22.0% logic, 78.0% route), 5 logic levels.
 
  Clock Skew Details: 
 
       Source Clock Path C14M to SLICE_33:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13D.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to Dout[2]_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_55:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to   IOL_L10D.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R3C6B.CLK C14M_c
                   --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+Passed: The following path meets requirements by 58.866ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        Dout_0io[3]  (to C14M_c -)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+   Delay:              10.898ns  (31.4% logic, 68.6% route), 7 logic levels.
 
  Constraint Details:
 
-      6.181ns physical path delay SLICE_33 to Dout[3]_MGIOL meets
-     34.965ns delay constraint less
-     -0.173ns skew and
-      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+     10.898ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.866ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to Dout[3]_MGIOL:
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
-CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
-ROUTE        17     2.710      R7C12C.F1 to     IOL_B4D.CE N_576_i (to C14M_c)
+REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
+ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
+CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
+ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
+CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     3.058      R5C10B.F1 to       R3C5D.A1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C5D.A1 to       R3C5D.F1 ram2e_ufm/SLICE_89
+ROUTE         6     0.348       R3C5D.F1 to       R3C5C.D1 ram2e_ufm/N_783
+CTOF_DEL    ---     0.495       R3C5C.D1 to       R3C5C.F1 ram2e_ufm/SLICE_68
+ROUTE         1     0.986       R3C5C.F1 to       R3C7A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
+CTOF_DEL    ---     0.495       R3C7A.A0 to       R3C7A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+                   10.898   (31.4% logic, 68.6% route), 7 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_33:
+      Source Clock Path C14M to SLICE_34:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
                   --------
                     4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to Dout[3]_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     5.038       62.PADDI to    IOL_B4D.CLK C14M_c
+ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
                   --------
-                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
 
-Report:   78.070MHz is the maximum frequency for this preference.
+Report:   84.310MHz is the maximum frequency for this preference.
 
 <A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
 --------------
@@ -569,7 +601,7 @@ Report:   78.070MHz is the maximum frequency for this preference.
 Preference                              |   Constraint|       Actual|Levels
 ----------------------------------------------------------------------------
                                         |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   78.070 MHz|   7  
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   84.310 MHz|   7  
                                         |             |             |
 ----------------------------------------------------------------------------
 
@@ -582,7 +614,7 @@ All preferences were met.
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -592,11 +624,11 @@ Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 --------------------------------------------------------------------------------
 <A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
-Thu Sep 21 05:35:07 2023
+Thu Dec 28 23:10:17 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -615,7 +647,7 @@ Report level:    verbose report, limited to 10 items per preference
 
 <A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
 
-<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1491 items scored, 0 timing errors detected.
+<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1611 items scored, 0 timing errors detected.
 
 BLOCK ASYNCPATHS
 BLOCK RESETPATHS
@@ -625,92 +657,49 @@ BLOCK RESETPATHS
 
 ================================================================================
 <A name="par_twr_pref_1_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 0.333ns
+Passed: The following path meets requirements by 0.342ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              wb_adr[2]  (from C14M_c +)
-   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
+   Source:         FF         Q              ram2e_ufm/wb_dati[6]  (from C14M_c +)
+   Destination:    EFB        Port           ram2e_ufm/ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
 
-   Delay:               0.306ns  (43.5% logic, 56.5% route), 1 logic levels.
+   Delay:               0.305ns  (43.6% logic, 56.4% route), 1 logic levels.
 
  Constraint Details:
 
-      0.306ns physical path delay SLICE_36 to ufmefb/EFBInst_0 meets
-     -0.081ns WBADRI_HLD and
+      0.305ns physical path delay ram2e_ufm/SLICE_55 to ram2e_ufm/ufmefb/EFBInst_0 meets
+     -0.091ns WBDATI_HLD and
       0.000ns delay constraint less
-     -0.054ns skew requirement (totaling -0.027ns) by 0.333ns
+     -0.054ns skew requirement (totaling -0.037ns) by 0.342ns
 
  Physical Path Details:
 
-      Data path SLICE_36 to ufmefb/EFBInst_0:
+      Data path ram2e_ufm/SLICE_55 to ram2e_ufm/ufmefb/EFBInst_0:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C5C.CLK to       R2C5C.Q0 SLICE_36 (from C14M_c)
-ROUTE         2     0.173       R2C5C.Q0 to    EFB.WBADRI2 wb_adr[2] (to C14M_c)
+REG_DEL     ---     0.133      R3C6B.CLK to       R3C6B.Q0 ram2e_ufm/SLICE_55 (from C14M_c)
+ROUTE         1     0.172       R3C6B.Q0 to    EFB.WBDATI6 ram2e_ufm/wb_dati[6] (to C14M_c)
                   --------
-                    0.306   (43.5% logic, 56.5% route), 1 logic levels.
+                    0.305   (43.6% logic, 56.4% route), 1 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_36:
+      Source Clock Path C14M to ram2e_ufm/SLICE_55:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R2C5C.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to      R3C6B.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to ufmefb/EFBInst_0:
+      Destination Clock Path C14M to ram2e_ufm/ufmefb/EFBInst_0:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.722       62.PADDI to     EFB.WBCLKI C14M_c
-                  --------
-                    1.722   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.358ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              wb_adr[3]  (from C14M_c +)
-   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
-
-   Delay:               0.307ns  (43.3% logic, 56.7% route), 1 logic levels.
-
- Constraint Details:
-
-      0.307ns physical path delay SLICE_36 to ufmefb/EFBInst_0 meets
-     -0.105ns WBADRI_HLD and
-      0.000ns delay constraint less
-     -0.054ns skew requirement (totaling -0.051ns) by 0.358ns
-
- Physical Path Details:
-
-      Data path SLICE_36 to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C5C.CLK to       R2C5C.Q1 SLICE_36 (from C14M_c)
-ROUTE         2     0.174       R2C5C.Q1 to    EFB.WBADRI3 wb_adr[3] (to C14M_c)
-                  --------
-                    0.307   (43.3% logic, 56.7% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_36:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R2C5C.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.722       62.PADDI to     EFB.WBCLKI C14M_c
+ROUTE        89     1.722       62.PADDI to     EFB.WBCLKI C14M_c
                   --------
                     1.722   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -719,43 +708,43 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              CmdBitbangMXO2  (from C14M_c +)
-   Destination:    FF         Data in        CmdBitbangMXO2  (to C14M_c +)
+   Source:         FF         Q              FS[15]  (from C14M_c +)
+   Destination:    FF         Data in        FS[15]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
  Constraint Details:
 
-      0.366ns physical path delay SLICE_12 to SLICE_12 meets
+      0.366ns physical path delay SLICE_1 to SLICE_1 meets
      -0.013ns DIN_HLD and
       0.000ns delay constraint less
       0.000ns skew requirement (totaling -0.013ns) by 0.379ns
 
  Physical Path Details:
 
-      Data path SLICE_12 to SLICE_12:
+      Data path SLICE_1 to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C7D.CLK to       R4C7D.Q0 SLICE_12 (from C14M_c)
-ROUTE         2     0.132       R4C7D.Q0 to       R4C7D.A0 CmdBitbangMXO2
-CTOF_DEL    ---     0.101       R4C7D.A0 to       R4C7D.F0 SLICE_12
-ROUTE         1     0.000       R4C7D.F0 to      R4C7D.DI0 CmdBitbangMXO2_4 (to C14M_c)
+REG_DEL     ---     0.133     R2C12A.CLK to      R2C12A.Q0 SLICE_1 (from C14M_c)
+ROUTE         9     0.132      R2C12A.Q0 to      R2C12A.A0 FS[15]
+CTOF_DEL    ---     0.101      R2C12A.A0 to      R2C12A.F0 SLICE_1
+ROUTE         1     0.000      R2C12A.F0 to     R2C12A.DI0 FS_s[15] (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_12:
+      Source Clock Path C14M to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R4C7D.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R2C12A.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_12:
+      Destination Clock Path C14M to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R4C7D.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R2C12A.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -764,233 +753,8 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              CmdExecMXO2  (from C14M_c +)
-   Destination:    FF         Data in        CmdExecMXO2  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_13 to SLICE_13 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_13 to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C7A.CLK to       R5C7A.Q0 SLICE_13 (from C14M_c)
-ROUTE         4     0.132       R5C7A.Q0 to       R5C7A.A0 CmdExecMXO2
-CTOF_DEL    ---     0.101       R5C7A.A0 to       R5C7A.F0 SLICE_13
-ROUTE         1     0.000       R5C7A.F0 to      R5C7A.DI0 CmdExecMXO2_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R5C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_13:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R5C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdLEDGet  (from C14M_c +)
-   Destination:    FF         Data in        CmdLEDGet  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_14 to SLICE_14 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R7C8A.CLK to       R7C8A.Q0 SLICE_14 (from C14M_c)
-ROUTE         2     0.132       R7C8A.Q0 to       R7C8A.A0 CmdLEDGet
-CTOF_DEL    ---     0.101       R7C8A.A0 to       R7C8A.F0 SLICE_14
-ROUTE         1     0.000       R7C8A.F0 to      R7C8A.DI0 CmdLEDGet_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R7C8A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R7C8A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdLEDSet  (from C14M_c +)
-   Destination:    FF         Data in        CmdLEDSet  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_15 to SLICE_15 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_15 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C7A.CLK to       R3C7A.Q0 SLICE_15 (from C14M_c)
-ROUTE         2     0.132       R3C7A.Q0 to       R3C7A.A0 CmdLEDSet
-CTOF_DEL    ---     0.101       R3C7A.A0 to       R3C7A.F0 SLICE_15
-ROUTE         1     0.000       R3C7A.F0 to      R3C7A.DI0 CmdLEDSet_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R3C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R3C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdRWMaskSet  (from C14M_c +)
-   Destination:    FF         Data in        CmdRWMaskSet  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_16 to SLICE_16 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_16 to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C7A.CLK to       R4C7A.Q0 SLICE_16 (from C14M_c)
-ROUTE         2     0.132       R4C7A.Q0 to       R4C7A.A0 CmdRWMaskSet
-CTOF_DEL    ---     0.101       R4C7A.A0 to       R4C7A.F0 SLICE_16
-ROUTE         1     0.000       R4C7A.F0 to      R4C7A.DI0 CmdRWMaskSet_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R4C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R4C7A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdSetRWBankFFLED  (from C14M_c +)
-   Destination:    FF         Data in        CmdSetRWBankFFLED  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_17 to SLICE_17 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_17 to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C8B.CLK to       R3C8B.Q0 SLICE_17 (from C14M_c)
-ROUTE         2     0.132       R3C8B.Q0 to       R3C8B.A0 CmdSetRWBankFFLED
-CTOF_DEL    ---     0.101       R3C8B.A0 to       R3C8B.F0 SLICE_17
-ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 CmdSetRWBankFFLED_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R3C8B.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R3C8B.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdSetRWBankFFMXO2  (from C14M_c +)
-   Destination:    FF         Data in        CmdSetRWBankFFMXO2  (to C14M_c +)
+   Source:         FF         Q              CmdTout[2]  (from C14M_c +)
+   Destination:    FF         Data in        CmdTout[2]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -1006,10 +770,10 @@ Passed: The following path meets requirements by 0.379ns
       Data path SLICE_18 to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R7C7A.CLK to       R7C7A.Q0 SLICE_18 (from C14M_c)
-ROUTE         2     0.132       R7C7A.Q0 to       R7C7A.A0 CmdSetRWBankFFMXO2
-CTOF_DEL    ---     0.101       R7C7A.A0 to       R7C7A.F0 SLICE_18
-ROUTE         1     0.000       R7C7A.F0 to      R7C7A.DI0 CmdSetRWBankFFMXO2_4 (to C14M_c)
+REG_DEL     ---     0.133     R8C11A.CLK to      R8C11A.Q1 SLICE_18 (from C14M_c)
+ROUTE         2     0.132      R8C11A.Q1 to      R8C11A.A1 CmdTout[2]
+CTOF_DEL    ---     0.101      R8C11A.A1 to      R8C11A.F1 SLICE_18
+ROUTE         1     0.000      R8C11A.F1 to     R8C11A.DI1 N_369_i (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -1018,14 +782,14 @@ ROUTE         1     0.000       R7C7A.F0 to      R7C7A.DI0 CmdSetRWBankFFMXO2_4
       Source Clock Path C14M to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R7C7A.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
       Destination Clock Path C14M to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R7C7A.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -1034,8 +798,53 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[14]  (from C14M_c +)
-   Destination:    FF         Data in        FS[14]  (to C14M_c +)
+   Source:         FF         Q              CmdTout[1]  (from C14M_c +)
+   Destination:    FF         Data in        CmdTout[1]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_18 to SLICE_18 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C11A.CLK to      R8C11A.Q0 SLICE_18 (from C14M_c)
+ROUTE         3     0.132      R8C11A.Q0 to      R8C11A.A0 CmdTout[1]
+CTOF_DEL    ---     0.101      R8C11A.A0 to      R8C11A.F0 SLICE_18
+ROUTE         1     0.000      R8C11A.F0 to     R8C11A.DI0 N_368_i (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[13]  (from C14M_c +)
+   Destination:    FF         Data in        FS[13]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -1051,10 +860,10 @@ Passed: The following path meets requirements by 0.379ns
       Data path SLICE_2 to SLICE_2:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q1 SLICE_2 (from C14M_c)
-ROUTE        13     0.132       R5C9D.Q1 to       R5C9D.A1 FS[14]
-CTOF_DEL    ---     0.101       R5C9D.A1 to       R5C9D.F1 SLICE_2
-ROUTE         1     0.000       R5C9D.F1 to      R5C9D.DI1 FS_s[14] (to C14M_c)
+REG_DEL     ---     0.133     R2C11D.CLK to      R2C11D.Q0 SLICE_2 (from C14M_c)
+ROUTE        19     0.132      R2C11D.Q0 to      R2C11D.A0 FS[13]
+CTOF_DEL    ---     0.101      R2C11D.A0 to      R2C11D.F0 SLICE_2
+ROUTE         1     0.000      R2C11D.F0 to     R2C11D.DI0 FS_s[13] (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -1063,14 +872,239 @@ ROUTE         1     0.000       R5C9D.F1 to      R5C9D.DI1 FS_s[14] (to C14M_c)
       Source Clock Path C14M to SLICE_2:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R5C9D.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R2C11D.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
       Destination Clock Path C14M to SLICE_2:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.668       62.PADDI to      R5C9D.CLK C14M_c
+ROUTE        89     1.668       62.PADDI to     R2C11D.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA[9]  (from C14M_c +)
+   Destination:    FF         Data in        RA[9]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_24 to SLICE_24 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_24 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11C.CLK to      R5C11C.Q1 SLICE_24 (from C14M_c)
+ROUTE         2     0.132      R5C11C.Q1 to      R5C11C.A1 RA[9]
+CTOF_DEL    ---     0.101      R5C11C.A1 to      R5C11C.F1 SLICE_24
+ROUTE         1     0.000      R5C11C.F1 to     R5C11C.DI1 RA_35[9] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA[8]  (from C14M_c +)
+   Destination:    FF         Data in        RA[8]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_24 to SLICE_24 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_24 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11C.CLK to      R5C11C.Q0 SLICE_24 (from C14M_c)
+ROUTE         2     0.132      R5C11C.Q0 to      R5C11C.A0 RA[8]
+CTOF_DEL    ---     0.101      R5C11C.A0 to      R5C11C.F0 SLICE_24
+ROUTE         1     0.000      R5C11C.F0 to     R5C11C.DI0 un2_S_2_i_0_0_o3_RNIHFHN3 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA[11]  (from C14M_c +)
+   Destination:    FF         Data in        RA[11]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_25 to SLICE_25 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_25 to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C12D.CLK to      R5C12D.Q1 SLICE_25 (from C14M_c)
+ROUTE         2     0.132      R5C12D.Q1 to      R5C12D.A1 RA[11]
+CTOF_DEL    ---     0.101      R5C12D.A1 to      R5C12D.F1 SLICE_25
+ROUTE         1     0.000      R5C12D.F1 to     R5C12D.DI1 RA_35[11] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C12D.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R5C12D.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RC[2]  (from C14M_c +)
+   Destination:    FF         Data in        RC[2]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_26 to SLICE_26 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_26 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C15C.CLK to      R4C15C.Q1 SLICE_26 (from C14M_c)
+ROUTE         5     0.132      R4C15C.Q1 to      R4C15C.A1 RC[2]
+CTOF_DEL    ---     0.101      R4C15C.A1 to      R4C15C.F1 SLICE_26
+ROUTE         1     0.000      R4C15C.F1 to     R4C15C.DI1 RC_3[2] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R4C15C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R4C15C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[12]  (from C14M_c +)
+   Destination:    FF         Data in        FS[12]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_3 to SLICE_3 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R2C11C.CLK to      R2C11C.Q1 SLICE_3 (from C14M_c)
+ROUTE        24     0.132      R2C11C.Q1 to      R2C11C.A1 FS[12]
+CTOF_DEL    ---     0.101      R2C11C.A1 to      R2C11C.F1 SLICE_3
+ROUTE         1     0.000      R2C11C.F1 to     R2C11C.DI1 FS_s[12] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R2C11C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.668       62.PADDI to     R2C11C.CLK C14M_c
                   --------
                     1.668   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -1093,7 +1127,7 @@ All preferences were met.
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -1103,7 +1137,7 @@ Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf
index 0078982..e74d3da 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf
@@ -1,7 +1,7 @@
 (DELAYFILE
   (SDFVERSION "3.0")
   (DESIGN "RAM2E")
-  (DATE "Thu Sep 21 05:35:16 2023")
+  (DATE "Thu Dec 28 23:10:25 2023")
   (VENDOR "Lattice")
   (PROGRAM "ldbanno")
   (VERSION "Diamond (64-bit) 3.12.1.454")
@@ -236,7 +236,28 @@
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_10")
+    (INSTANCE SLICE_10)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
       )
@@ -251,14 +272,37 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_10")
-    (INSTANCE SLICE_10)
+    (CELLTYPE "SLICE_11")
+    (INSTANCE SLICE_11)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_12")
+    (INSTANCE SLICE_12)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -279,15 +323,17 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_11")
-    (INSTANCE SLICE_11)
+    (CELLTYPE "SLICE_13")
+    (INSTANCE SLICE_13)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
       )
@@ -303,54 +349,6 @@
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
   )
-  (CELL
-    (CELLTYPE "SLICE_12")
-    (INSTANCE SLICE_12)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_13")
-    (INSTANCE SLICE_13)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
   (CELL
     (CELLTYPE "SLICE_14")
     (INSTANCE SLICE_14)
@@ -358,7 +356,6 @@
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -382,10 +379,10 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -406,6 +403,7 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -432,7 +430,7 @@
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -456,14 +454,16 @@
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
@@ -477,23 +477,20 @@
     (INSTANCE SLICE_19)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
+      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
     )
     (TIMINGCHECK
+      (WIDTH (posedge LSR) (4000:4000:4000))
+      (WIDTH (negedge LSR) (4000:4000:4000))
       (WIDTH (posedge CLK) (1250:1250:1250))
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
@@ -512,10 +509,13 @@
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -528,15 +528,18 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
@@ -550,11 +553,12 @@
     (INSTANCE SLICE_22)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -578,7 +582,7 @@
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -603,6 +607,7 @@
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -625,10 +630,12 @@
     (INSTANCE SLICE_25)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -651,11 +658,11 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
@@ -678,9 +685,9 @@
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
@@ -700,12 +707,12 @@
     (INSTANCE SLICE_28)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
@@ -726,10 +733,10 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -751,11 +758,11 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
@@ -775,6 +782,7 @@
     (INSTANCE SLICE_31)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -877,20 +885,18 @@
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
     )
     (TIMINGCHECK
+      (WIDTH (posedge LSR) (4000:4000:4000))
+      (WIDTH (negedge LSR) (4000:4000:4000))
       (WIDTH (posedge CLK) (1250:1250:1250))
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
@@ -902,16 +908,17 @@
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -924,19 +931,18 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -949,18 +955,18 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -968,14 +974,15 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39)
+    (CELLTYPE "ram2e_ufm_SLICE_39")
+    (INSTANCE ram2e_ufm\/SLICE_39)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -992,8 +999,179 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_40")
-    (INSTANCE SLICE_40)
+    (CELLTYPE "ram2e_ufm_SLICE_40")
+    (INSTANCE ram2e_ufm\/SLICE_40)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_41")
+    (INSTANCE ram2e_ufm\/SLICE_41)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_42")
+    (INSTANCE ram2e_ufm\/SLICE_42)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_43")
+    (INSTANCE ram2e_ufm\/SLICE_43)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_44")
+    (INSTANCE ram2e_ufm\/SLICE_44)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_45")
+    (INSTANCE ram2e_ufm\/SLICE_45)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_46")
+    (INSTANCE ram2e_ufm\/SLICE_46)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_47")
+    (INSTANCE ram2e_ufm\/SLICE_47)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1019,14 +1197,36 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41)
+    (CELLTYPE "ram2e_ufm_SLICE_48")
+    (INSTANCE ram2e_ufm\/SLICE_48)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_49")
+    (INSTANCE ram2e_ufm\/SLICE_49)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1045,8 +1245,56 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42)
+    (CELLTYPE "ram2e_ufm_SLICE_50")
+    (INSTANCE ram2e_ufm\/SLICE_50)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_51")
+    (INSTANCE ram2e_ufm\/SLICE_51)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_52")
+    (INSTANCE ram2e_ufm\/SLICE_52)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1072,8 +1320,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43)
+    (CELLTYPE "ram2e_ufm_SLICE_53")
+    (INSTANCE ram2e_ufm\/SLICE_53)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1081,6 +1329,7 @@
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -1098,11 +1347,66 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44)
+    (CELLTYPE "ram2e_ufm_SLICE_54")
+    (INSTANCE ram2e_ufm\/SLICE_54)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_55")
+    (INSTANCE ram2e_ufm\/SLICE_55)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_56")
+    (INSTANCE ram2e_ufm\/SLICE_56)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -1125,13 +1429,15 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_45")
-    (INSTANCE SLICE_45)
+    (CELLTYPE "ram2e_ufm_SLICE_57")
+    (INSTANCE ram2e_ufm\/SLICE_57)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
       )
@@ -1148,8 +1454,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_46")
-    (INSTANCE SLICE_46)
+    (CELLTYPE "ram2e_ufm_SLICE_58")
+    (INSTANCE ram2e_ufm\/SLICE_58)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1173,8 +1479,54 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_47")
-    (INSTANCE SLICE_47)
+    (CELLTYPE "ram2e_ufm_SUM0_i_m3_0_SLICE_59")
+    (INSTANCE ram2e_ufm\/SUM0_i_m3_0\/SLICE_59)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH D0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60")
+    (INSTANCE ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_CKE_7_SLICE_61")
+    (INSTANCE ram2e_ufm\/CKE_7\/SLICE_61)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH D0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_62")
+    (INSTANCE ram2e_ufm\/SLICE_62)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1189,8 +1541,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_48")
-    (INSTANCE SLICE_48)
+    (CELLTYPE "ram2e_ufm_SLICE_63")
+    (INSTANCE ram2e_ufm\/SLICE_63)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1205,8 +1557,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_49")
-    (INSTANCE SLICE_49)
+    (CELLTYPE "ram2e_ufm_SLICE_64")
+    (INSTANCE ram2e_ufm\/SLICE_64)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_65")
+    (INSTANCE ram2e_ufm\/SLICE_65)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1221,8 +1588,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50)
+    (CELLTYPE "ram2e_ufm_SLICE_66")
+    (INSTANCE ram2e_ufm\/SLICE_66)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1237,8 +1604,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51)
+    (CELLTYPE "ram2e_ufm_SLICE_67")
+    (INSTANCE ram2e_ufm\/SLICE_67)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_68")
+    (INSTANCE ram2e_ufm\/SLICE_68)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1253,8 +1635,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52)
+    (CELLTYPE "ram2e_ufm_SLICE_69")
+    (INSTANCE ram2e_ufm\/SLICE_69)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1269,8 +1651,52 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_53")
-    (INSTANCE SLICE_53)
+    (CELLTYPE "ram2e_ufm_SLICE_70")
+    (INSTANCE ram2e_ufm\/SLICE_70)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_71")
+    (INSTANCE ram2e_ufm\/SLICE_71)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_72")
+    (INSTANCE ram2e_ufm\/SLICE_72)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_73")
+    (INSTANCE ram2e_ufm\/SLICE_73)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1285,8 +1711,81 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_54")
-    (INSTANCE SLICE_54)
+    (CELLTYPE "ram2e_ufm_SLICE_74")
+    (INSTANCE ram2e_ufm\/SLICE_74)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_75")
+    (INSTANCE ram2e_ufm\/SLICE_75)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_76")
+    (INSTANCE ram2e_ufm\/SLICE_76)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_77")
+    (INSTANCE ram2e_ufm\/SLICE_77)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_78")
+    (INSTANCE ram2e_ufm\/SLICE_78)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_79")
+    (INSTANCE ram2e_ufm\/SLICE_79)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1301,8 +1800,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55)
+    (CELLTYPE "ram2e_ufm_SLICE_80")
+    (INSTANCE ram2e_ufm\/SLICE_80)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1317,22 +1816,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57)
+    (CELLTYPE "ram2e_ufm_SLICE_81")
+    (INSTANCE ram2e_ufm\/SLICE_81)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1347,8 +1832,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58)
+    (CELLTYPE "ram2e_ufm_SLICE_82")
+    (INSTANCE ram2e_ufm\/SLICE_82)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1363,8 +1848,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59)
+    (CELLTYPE "ram2e_ufm_SLICE_83")
+    (INSTANCE ram2e_ufm\/SLICE_83)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_84")
+    (INSTANCE ram2e_ufm\/SLICE_84)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1379,126 +1879,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_65")
-    (INSTANCE SLICE_65)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68)
+    (CELLTYPE "ram2e_ufm_SLICE_85")
+    (INSTANCE ram2e_ufm\/SLICE_85)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1513,8 +1895,66 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69)
+    (CELLTYPE "ram2e_ufm_SLICE_86")
+    (INSTANCE ram2e_ufm\/SLICE_86)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_87")
+    (INSTANCE ram2e_ufm\/SLICE_87)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_88")
+    (INSTANCE ram2e_ufm\/SLICE_88)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_89")
+    (INSTANCE ram2e_ufm\/SLICE_89)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_90")
+    (INSTANCE ram2e_ufm\/SLICE_90)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1529,8 +1969,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70)
+    (CELLTYPE "ram2e_ufm_SLICE_91")
+    (INSTANCE ram2e_ufm\/SLICE_91)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1545,8 +1985,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71)
+    (CELLTYPE "ram2e_ufm_SLICE_92")
+    (INSTANCE ram2e_ufm\/SLICE_92)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1561,8 +2001,37 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72)
+    (CELLTYPE "ram2e_ufm_SLICE_93")
+    (INSTANCE ram2e_ufm\/SLICE_93)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_94")
+    (INSTANCE ram2e_ufm\/SLICE_94)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_95")
+    (INSTANCE ram2e_ufm\/SLICE_95)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1577,8 +2046,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73)
+    (CELLTYPE "ram2e_ufm_SLICE_96")
+    (INSTANCE ram2e_ufm\/SLICE_96)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1593,42 +2062,13 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75)
+    (CELLTYPE "ram2e_ufm_SLICE_97")
+    (INSTANCE ram2e_ufm\/SLICE_97)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -1637,8 +2077,22 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77)
+    (CELLTYPE "ram2e_ufm_SLICE_98")
+    (INSTANCE ram2e_ufm\/SLICE_98)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_99")
+    (INSTANCE ram2e_ufm\/SLICE_99)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1652,50 +2106,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81)
+    (CELLTYPE "ram2e_ufm_SLICE_100")
+    (INSTANCE ram2e_ufm\/SLICE_100)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1710,8 +2122,93 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82)
+    (CELLTYPE "ram2e_ufm_SLICE_101")
+    (INSTANCE ram2e_ufm\/SLICE_101)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_102")
+    (INSTANCE ram2e_ufm\/SLICE_102)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_103")
+    (INSTANCE ram2e_ufm\/SLICE_103)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_104")
+    (INSTANCE ram2e_ufm\/SLICE_104)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_105")
+    (INSTANCE ram2e_ufm\/SLICE_105)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_106")
+    (INSTANCE ram2e_ufm\/SLICE_106)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_107")
+    (INSTANCE ram2e_ufm\/SLICE_107)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1726,8 +2223,140 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83)
+    (CELLTYPE "ram2e_ufm_SLICE_108")
+    (INSTANCE ram2e_ufm\/SLICE_108)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_109")
+    (INSTANCE ram2e_ufm\/SLICE_109)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_110")
+    (INSTANCE ram2e_ufm\/SLICE_110)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_111")
+    (INSTANCE ram2e_ufm\/SLICE_111)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_112")
+    (INSTANCE ram2e_ufm\/SLICE_112)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_113")
+    (INSTANCE ram2e_ufm\/SLICE_113)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_114")
+    (INSTANCE ram2e_ufm\/SLICE_114)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_115")
+    (INSTANCE ram2e_ufm\/SLICE_115)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_116")
+    (INSTANCE ram2e_ufm\/SLICE_116)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_117")
+    (INSTANCE ram2e_ufm\/SLICE_117)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1742,8 +2371,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84)
+    (CELLTYPE "ram2e_ufm_SLICE_118")
+    (INSTANCE ram2e_ufm\/SLICE_118)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1758,8 +2387,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85)
+    (CELLTYPE "ram2e_ufm_SLICE_119")
+    (INSTANCE ram2e_ufm\/SLICE_119)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1774,8 +2403,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86)
+    (CELLTYPE "ram2e_ufm_SLICE_120")
+    (INSTANCE ram2e_ufm\/SLICE_120)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1790,81 +2419,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92)
+    (CELLTYPE "ram2e_ufm_SLICE_121")
+    (INSTANCE ram2e_ufm\/SLICE_121)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1879,8 +2435,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93)
+    (CELLTYPE "ram2e_ufm_SLICE_122")
+    (INSTANCE ram2e_ufm\/SLICE_122)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1895,8 +2451,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94)
+    (CELLTYPE "ram2e_ufm_SLICE_123")
+    (INSTANCE ram2e_ufm\/SLICE_123)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_124")
+    (INSTANCE ram2e_ufm\/SLICE_124)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1911,8 +2482,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_95")
-    (INSTANCE SLICE_95)
+    (CELLTYPE "ram2e_ufm_SLICE_125")
+    (INSTANCE ram2e_ufm\/SLICE_125)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1927,80 +2498,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_96")
-    (INSTANCE SLICE_96)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_97")
-    (INSTANCE SLICE_97)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_98")
-    (INSTANCE SLICE_98)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_99")
-    (INSTANCE SLICE_99)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_100")
-    (INSTANCE SLICE_100)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_101")
-    (INSTANCE SLICE_101)
+    (CELLTYPE "ram2e_ufm_SLICE_126")
+    (INSTANCE ram2e_ufm\/SLICE_126)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2015,8 +2514,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_102")
-    (INSTANCE SLICE_102)
+    (CELLTYPE "ram2e_ufm_SLICE_127")
+    (INSTANCE ram2e_ufm\/SLICE_127)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2031,8 +2530,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_103")
-    (INSTANCE SLICE_103)
+    (CELLTYPE "ram2e_ufm_SLICE_128")
+    (INSTANCE ram2e_ufm\/SLICE_128)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_129")
+    (INSTANCE ram2e_ufm\/SLICE_129)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2047,8 +2561,22 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_104")
-    (INSTANCE SLICE_104)
+    (CELLTYPE "ram2e_ufm_SLICE_130")
+    (INSTANCE ram2e_ufm\/SLICE_130)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_131")
+    (INSTANCE ram2e_ufm\/SLICE_131)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2063,8 +2591,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_105")
-    (INSTANCE SLICE_105)
+    (CELLTYPE "ram2e_ufm_SLICE_132")
+    (INSTANCE ram2e_ufm\/SLICE_132)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2079,50 +2607,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_106")
-    (INSTANCE SLICE_106)
+    (CELLTYPE "ram2e_ufm_SLICE_133")
+    (INSTANCE ram2e_ufm\/SLICE_133)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_107")
-    (INSTANCE SLICE_107)
-    (DELAY
-      (ABSOLUTE
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_108")
-    (INSTANCE SLICE_108)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
       )
     )
   )
   (CELL
-    (CELLTYPE "SLICE_109")
-    (INSTANCE SLICE_109)
+    (CELLTYPE "ram2e_ufm_SLICE_134")
+    (INSTANCE ram2e_ufm\/SLICE_134)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2137,8 +2638,152 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_110")
-    (INSTANCE SLICE_110)
+    (CELLTYPE "ram2e_ufm_SLICE_135")
+    (INSTANCE ram2e_ufm\/SLICE_135)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_136")
+    (INSTANCE ram2e_ufm\/SLICE_136)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_137")
+    (INSTANCE ram2e_ufm\/SLICE_137)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_138")
+    (INSTANCE SLICE_138)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_139")
+    (INSTANCE SLICE_139)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_140")
+    (INSTANCE ram2e_ufm\/SLICE_140)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_141")
+    (INSTANCE ram2e_ufm\/SLICE_141)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_142")
+    (INSTANCE ram2e_ufm\/SLICE_142)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_143")
+    (INSTANCE ram2e_ufm\/SLICE_143)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_144")
+    (INSTANCE ram2e_ufm\/SLICE_144)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_145")
+    (INSTANCE ram2e_ufm\/SLICE_145)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_146")
+    (INSTANCE ram2e_ufm\/SLICE_146)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2153,127 +2798,16 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_111")
-    (INSTANCE SLICE_111)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_112")
-    (INSTANCE SLICE_112)
+    (CELLTYPE "ram2e_ufm_SLICE_147")
+    (INSTANCE ram2e_ufm\/SLICE_147)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_113")
-    (INSTANCE SLICE_113)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_114")
-    (INSTANCE SLICE_114)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_115")
-    (INSTANCE SLICE_115)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_116")
-    (INSTANCE SLICE_116)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_117")
-    (INSTANCE SLICE_117)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_118")
-    (INSTANCE SLICE_118)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_119")
-    (INSTANCE SLICE_119)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
       )
     )
   )
@@ -2315,56 +2849,6 @@
       (WIDTH (negedge C14M) (3330:3330:3330))
     )
   )
-  (CELL
-    (CELLTYPE "DQMH")
-    (INSTANCE DQMH_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO DQMH (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "DQMH_MGIOL")
-    (INSTANCE DQMH_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "DQML")
-    (INSTANCE DQML_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO DQML (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "DQML_MGIOL")
-    (INSTANCE DQML_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
   (CELL
     (CELLTYPE "RD_7_")
     (INSTANCE RD\[7\]_I)
@@ -2478,117 +2962,17 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_11_")
-    (INSTANCE RA\[11\]_I)
+    (CELLTYPE "DQMH")
+    (INSTANCE DQMH_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA11 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO DQMH (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_11__MGIOL")
-    (INSTANCE RA\[11\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_")
-    (INSTANCE RA\[10\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA10 (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10__MGIOL")
-    (INSTANCE RA\[10\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_")
-    (INSTANCE RA\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA9 (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9__MGIOL")
-    (INSTANCE RA\[9\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_")
-    (INSTANCE RA\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA8 (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8__MGIOL")
-    (INSTANCE RA\[8\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_")
-    (INSTANCE RA\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA7 (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7__MGIOL")
-    (INSTANCE RA\[7\]_MGIOL)
+    (CELLTYPE "DQMH_MGIOL")
+    (INSTANCE DQMH_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
@@ -2604,17 +2988,17 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_6_")
-    (INSTANCE RA\[6\]_I)
+    (CELLTYPE "DQML")
+    (INSTANCE DQML_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA6 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO DQML (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_6__MGIOL")
-    (INSTANCE RA\[6\]_MGIOL)
+    (CELLTYPE "DQML_MGIOL")
+    (INSTANCE DQML_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
@@ -2630,127 +3014,305 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_5_")
-    (INSTANCE RA\[5\]_I)
+    (CELLTYPE "RAout_11_")
+    (INSTANCE RAout\[11\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA5 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO RAout11 (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_5__MGIOL")
-    (INSTANCE RA\[5\]_MGIOL)
+    (CELLTYPE "RAout_11__MGIOL")
+    (INSTANCE RAout\[11\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_4_")
-    (INSTANCE RA\[4\]_I)
+    (CELLTYPE "RAout_10_")
+    (INSTANCE RAout\[10\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA4 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO RAout10 (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_4__MGIOL")
-    (INSTANCE RA\[4\]_MGIOL)
+    (CELLTYPE "RAout_10__MGIOL")
+    (INSTANCE RAout\[10\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_3_")
-    (INSTANCE RA\[3\]_I)
+    (CELLTYPE "RAout_9_")
+    (INSTANCE RAout\[9\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH PADDO RA3 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO RAout9 (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_2_")
-    (INSTANCE RA\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA2 (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2__MGIOL")
-    (INSTANCE RA\[2\]_MGIOL)
+    (CELLTYPE "RAout_9__MGIOL")
+    (INSTANCE RAout\[9\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_1_")
-    (INSTANCE RA\[1\]_I)
+    (CELLTYPE "RAout_8_")
+    (INSTANCE RAout\[8\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA1 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO RAout8 (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_1__MGIOL")
-    (INSTANCE RA\[1\]_MGIOL)
+    (CELLTYPE "RAout_8__MGIOL")
+    (INSTANCE RAout\[8\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_7_")
+    (INSTANCE RAout\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout7 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_7__MGIOL")
+    (INSTANCE RAout\[7\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_0_")
-    (INSTANCE RA\[0\]_I)
+    (CELLTYPE "RAout_6_")
+    (INSTANCE RAout\[6\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH PADDO RA0 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO RAout6 (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
+  (CELL
+    (CELLTYPE "RAout_6__MGIOL")
+    (INSTANCE RAout\[6\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_5_")
+    (INSTANCE RAout\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout5 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_5__MGIOL")
+    (INSTANCE RAout\[5\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_4_")
+    (INSTANCE RAout\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout4 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_4__MGIOL")
+    (INSTANCE RAout\[4\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_3_")
+    (INSTANCE RAout\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout3 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_3__MGIOL")
+    (INSTANCE RAout\[3\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_2_")
+    (INSTANCE RAout\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout2 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_2__MGIOL")
+    (INSTANCE RAout\[2\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_1_")
+    (INSTANCE RAout\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout1 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_1__MGIOL")
+    (INSTANCE RAout\[1\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_0_")
+    (INSTANCE RAout\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout0 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_0__MGIOL")
+    (INSTANCE RAout\[0\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
   (CELL
     (CELLTYPE "BA_1_")
     (INSTANCE BA\[1\]_I)
@@ -2770,6 +3332,7 @@
     )
     (TIMINGCHECK
       (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
       (SETUPHOLD LSR (posedge CLK) (100:100:100)(-90:-90:-90))
     )
     (TIMINGCHECK
@@ -2796,6 +3359,7 @@
     )
     (TIMINGCHECK
       (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
       (SETUPHOLD LSR (posedge CLK) (100:100:100)(-90:-90:-90))
     )
     (TIMINGCHECK
@@ -2804,128 +3368,112 @@
     )
   )
   (CELL
-    (CELLTYPE "nRWE")
-    (INSTANCE nRWE_I)
+    (CELLTYPE "nRWEout")
+    (INSTANCE nRWEout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nRWE (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO nRWEout (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "nRWE_MGIOL")
-    (INSTANCE nRWE_MGIOL)
+    (CELLTYPE "nRWEout_MGIOL")
+    (INSTANCE nRWEout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nCAS")
-    (INSTANCE nCAS_I)
+    (CELLTYPE "nCASout")
+    (INSTANCE nCASout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nCAS (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO nCASout (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "nCAS_MGIOL")
-    (INSTANCE nCAS_MGIOL)
+    (CELLTYPE "nCASout_MGIOL")
+    (INSTANCE nCASout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nRAS")
-    (INSTANCE nRAS_I)
+    (CELLTYPE "nRASout")
+    (INSTANCE nRASout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nRAS (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO nRASout (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "nRAS_MGIOL")
-    (INSTANCE nRAS_MGIOL)
+    (CELLTYPE "nRASout_MGIOL")
+    (INSTANCE nRASout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nCS")
-    (INSTANCE nCS_I)
+    (CELLTYPE "nCSout")
+    (INSTANCE nCSout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nCS (3411:3517:3624)(3411:3517:3624))
+        (IOPATH PADDO nCSout (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "nCS_MGIOL")
-    (INSTANCE nCS_MGIOL)
+    (CELLTYPE "CKEout")
+    (INSTANCE CKEout_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO CKEout (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "CKEout_MGIOL")
+    (INSTANCE CKEout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
-  )
-  (CELL
-    (CELLTYPE "CKE")
-    (INSTANCE CKE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO CKE (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "CKE_MGIOL")
-    (INSTANCE CKE_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
     )
   )
   (CELL
@@ -2955,12 +3503,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -2981,12 +3529,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3007,12 +3555,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3033,12 +3581,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3059,12 +3607,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3085,12 +3633,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3111,12 +3659,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3137,12 +3685,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3159,209 +3707,73 @@
     (INSTANCE Dout\[7\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout7 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout7 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_7__MGIOL")
-    (INSTANCE Dout\[7\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_6_")
     (INSTANCE Dout\[6\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout6 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout6 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_6__MGIOL")
-    (INSTANCE Dout\[6\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_5_")
     (INSTANCE Dout\[5\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout5 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout5 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_5__MGIOL")
-    (INSTANCE Dout\[5\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_4_")
     (INSTANCE Dout\[4\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout4 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout4 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_4__MGIOL")
-    (INSTANCE Dout\[4\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_3_")
     (INSTANCE Dout\[3\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout3 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout3 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_3__MGIOL")
-    (INSTANCE Dout\[3\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_2_")
     (INSTANCE Dout\[2\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout2 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout2 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_2__MGIOL")
-    (INSTANCE Dout\[2\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_1_")
     (INSTANCE Dout\[1\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout1 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout1 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_1__MGIOL")
-    (INSTANCE Dout\[1\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_0_")
     (INSTANCE Dout\[0\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout0 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout0 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_0__MGIOL")
-    (INSTANCE Dout\[0\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Din_7_")
     (INSTANCE Din\[7\]_I)
@@ -3596,19 +4008,6 @@
       (WIDTH (negedge nEN80) (3330:3330:3330))
     )
   )
-  (CELL
-    (CELLTYPE "nWE80")
-    (INSTANCE nWE80_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nWE80 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nWE80) (3330:3330:3330))
-      (WIDTH (negedge nWE80) (3330:3330:3330))
-    )
-  )
   (CELL
     (CELLTYPE "nWE")
     (INSTANCE nWE_I)
@@ -3653,7 +4052,7 @@
   )
   (CELL
     (CELLTYPE "EFB_Buffer_Block")
-    (INSTANCE ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20)
+    (INSTANCE ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20)
     (DELAY
       (ABSOLUTE
         (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278))
@@ -3700,10 +4099,11 @@
     (DELAY
       (ABSOLUTE
         (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (481:575:669)(481:575:669))
-        (INTERCONNECT SLICE_0/Q1 SLICE_39/A1 (1010:1164:1319)(1010:1164:1319))
-        (INTERCONNECT SLICE_0/Q1 SLICE_52/A1 (1010:1164:1319)(1010:1164:1319))
-        (INTERCONNECT SLICE_0/Q1 SLICE_75/A1 (1479:1669:1860)(1479:1669:1860))
-        (INTERCONNECT SLICE_0/Q1 SLICE_119/D0 (868:965:1062)(868:965:1062))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_51/A1 (1337:1526:1716)(1337:1526:1716))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_69/D1 (1534:1686:1839)(1534:1686:1839))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_105/D0 (1534:1686:1839)(1534:1686:1839))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_108/B0 (783:913:1043)(783:913:1043))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_146/C0 (552:669:786)(552:669:786))
         (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI SLICE_0/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_1/CLK (4198:4531:4865)(4198:4531:4865))
@@ -3723,18 +4123,20 @@
         (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_9/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_11/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (4198:4531:4865)(4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_13/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_14/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_15/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_16/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_17/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (4198:4531:4865)(4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (4198:4531:4865)(4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (4198:4531:4865)(4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (4198:4531:4865)(4198:4531:4865))
@@ -3761,44 +4163,93 @@
         (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (4198:4531:4865)(4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_39/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_44/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_45/CLK (4198:4531:4865)(4198:4531:4865))
-        (INTERCONNECT C14M_I/PADDI SLICE_46/CLK (4198:4531:4865)(4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_39/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_40/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_41/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_42/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_43/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_43/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_44/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_44/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_45/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_45/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_46/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_46/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_47/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_47/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_48/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_48/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_49/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_49/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_50/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_50/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_51/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_52/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_52/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_53/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_53/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_54/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_54/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_55/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_55/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_56/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_57/CLK (4198:4531:4865)
+          (4198:4531:4865))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_58/CLK (4198:4531:4865)
+          (4198:4531:4865))
         (INTERCONNECT C14M_I/PADDI DQMH_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
         (INTERCONNECT C14M_I/PADDI DQML_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI RA\[11\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI RA\[10\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI RA\[9\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI RA\[8\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI RA\[7\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI RA\[6\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI RA\[5\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI RA\[4\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI RA\[2\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI RA\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[11\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[10\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[9\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[8\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[7\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[6\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[5\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[4\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[3\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[2\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI RAout\[0\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
         (INTERCONNECT C14M_I/PADDI BA\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
         (INTERCONNECT C14M_I/PADDI BA\[0\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI nRWE_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI nCAS_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI nRAS_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI nCS_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI CKE_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI nRWEout_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI nCASout_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI nRASout_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
+        (INTERCONNECT C14M_I/PADDI CKEout_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
         (INTERCONNECT C14M_I/PADDI Vout\[7\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
         (INTERCONNECT C14M_I/PADDI Vout\[6\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
         (INTERCONNECT C14M_I/PADDI Vout\[5\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
@@ -3807,1123 +4258,1719 @@
         (INTERCONNECT C14M_I/PADDI Vout\[2\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
         (INTERCONNECT C14M_I/PADDI Vout\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
         (INTERCONNECT C14M_I/PADDI Vout\[0\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI Dout\[7\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI Dout\[6\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI Dout\[5\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI Dout\[4\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI Dout\[3\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI Dout\[2\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI Dout\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
-        (INTERCONNECT C14M_I/PADDI Dout\[0\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
         (INTERCONNECT C14M_I/PADDI PHI1_MGIOL/CLK (4345:4691:5038)(4345:4691:5038))
         (INTERCONNECT C14M_I/PADDI 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (4345:4691:5038)
-          (4345:4691:5038))
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin 
+          (4345:4691:5038)(4345:4691:5038))
         (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (481:575:669)(481:575:669))
-        (INTERCONNECT SLICE_1/Q0 SLICE_45/D0 (807:902:998)(807:902:998))
-        (INTERCONNECT SLICE_1/Q0 SLICE_51/A0 (1017:1178:1339)(1017:1178:1339))
-        (INTERCONNECT SLICE_1/Q0 SLICE_53/A1 (1344:1540:1736)(1344:1540:1736))
-        (INTERCONNECT SLICE_1/Q0 SLICE_56/D1 (1182:1310:1438)(1182:1310:1438))
-        (INTERCONNECT SLICE_1/Q0 SLICE_72/D0 (541:603:665)(541:603:665))
-        (INTERCONNECT SLICE_1/Q0 SLICE_73/D0 (1546:1705:1865)(1546:1705:1865))
-        (INTERCONNECT SLICE_1/Q0 SLICE_75/D0 (1134:1264:1395)(1134:1264:1395))
-        (INTERCONNECT SLICE_1/Q0 SLICE_83/B1 (1376:1574:1773)(1376:1574:1773))
-        (INTERCONNECT SLICE_1/Q0 SLICE_86/D1 (1546:1705:1865)(1546:1705:1865))
-        (INTERCONNECT SLICE_1/Q0 SLICE_103/C0 (552:669:786)(552:669:786))
+        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_1/Q0 SLICE_9/C1 (998:1155:1313)(998:1155:1313))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/A1 (1562:1761:1961)(1562:1761:1961))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/A0 (1562:1761:1961)(1562:1761:1961))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_69/C1 (993:1150:1307)(993:1150:1307))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_80/B1 (1224:1394:1564)(1224:1394:1564))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_105/A0 (1192:1359:1527)(1192:1359:1527))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/C1 (998:1155:1313)(998:1155:1313))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/C0 (998:1155:1313)(998:1155:1313))
         (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_2/Q1 SLICE_37/B1 (1589:1789:1990)(1589:1789:1990))
-        (INTERCONNECT SLICE_2/Q1 SLICE_37/B0 (1589:1789:1990)(1589:1789:1990))
-        (INTERCONNECT SLICE_2/Q1 SLICE_38/C0 (1733:1953:2173)(1733:1953:2173))
-        (INTERCONNECT SLICE_2/Q1 SLICE_39/B1 (1230:1399:1569)(1230:1399:1569))
-        (INTERCONNECT SLICE_2/Q1 SLICE_44/C0 (999:1155:1312)(999:1155:1312))
-        (INTERCONNECT SLICE_2/Q1 SLICE_45/A1 (1578:1778:1978)(1578:1778:1978))
-        (INTERCONNECT SLICE_2/Q1 SLICE_45/A0 (1578:1778:1978)(1578:1778:1978))
-        (INTERCONNECT SLICE_2/Q1 SLICE_56/A1 (1578:1778:1978)(1578:1778:1978))
-        (INTERCONNECT SLICE_2/Q1 SLICE_66/A1 (2296:2558:2820)(2296:2558:2820))
-        (INTERCONNECT SLICE_2/Q1 SLICE_73/C0 (1743:1964:2185)(1743:1964:2185))
-        (INTERCONNECT SLICE_2/Q1 SLICE_86/A1 (1562:1760:1959)(1562:1760:1959))
-        (INTERCONNECT SLICE_2/Q1 SLICE_97/A0 (1932:2162:2393)(1932:2162:2393))
-        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (481:575:669)(481:575:669))
-        (INTERCONNECT SLICE_2/Q0 SLICE_35/D0 (1350:1483:1617)(1350:1483:1617))
-        (INTERCONNECT SLICE_2/Q0 SLICE_44/B1 (1110:1275:1440)(1110:1275:1440))
-        (INTERCONNECT SLICE_2/Q0 SLICE_46/A0 (1580:1781:1982)(1580:1781:1982))
-        (INTERCONNECT SLICE_2/Q0 SLICE_56/C0 (1751:1973:2196)(1751:1973:2196))
-        (INTERCONNECT SLICE_2/Q0 SLICE_60/A0 (2325:2590:2856)(2325:2590:2856))
-        (INTERCONNECT SLICE_2/Q0 SLICE_61/B1 (2727:3027:3327)(2727:3027:3327))
-        (INTERCONNECT SLICE_2/Q0 SLICE_65/A0 (1190:1357:1524)(1190:1357:1524))
-        (INTERCONNECT SLICE_2/Q0 SLICE_66/A0 (1580:1781:1982)(1580:1781:1982))
-        (INTERCONNECT SLICE_2/Q0 SLICE_73/A0 (1580:1781:1982)(1580:1781:1982))
-        (INTERCONNECT SLICE_2/Q0 SLICE_74/D0 (2442:2677:2912)(2442:2677:2912))
-        (INTERCONNECT SLICE_2/Q0 SLICE_88/D1 (2485:2717:2949)(2485:2717:2949))
-        (INTERCONNECT SLICE_2/Q0 SLICE_90/D1 (1275:1400:1526)(1275:1400:1526))
-        (INTERCONNECT SLICE_2/Q0 SLICE_92/A1 (1580:1781:1982)(1580:1781:1982))
-        (INTERCONNECT SLICE_2/Q0 SLICE_97/B0 (2283:2551:2819)(2283:2551:2819))
-        (INTERCONNECT SLICE_2/Q0 SLICE_108/B0 (2208:2468:2728)(2208:2468:2728))
-        (INTERCONNECT SLICE_2/Q0 SLICE_116/C0 (1708:1933:2159)(1708:1933:2159))
+        (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_2/Q1 SLICE_23/B1 (777:906:1036)(777:906:1036))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/C1 (821:966:1111)(821:966:1111))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/C0 (821:966:1111)(821:966:1111))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_50/D0 (1190:1313:1436)(1190:1313:1436))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_51/C1 (1196:1373:1551)(1196:1373:1551))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_56/A1 (2097:2352:2608)(2097:2352:2608))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/C1 (1571:1781:1991)(1571:1781:1991))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/C0 (1571:1781:1991)(1571:1781:1991))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_66/D1 (1185:1307:1430)(1185:1307:1430))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_70/C1 (1565:1774:1984)(1565:1774:1984))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_81/D1 (1903:2095:2288)(1903:2095:2288))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_85/B1 (1759:1985:2211)(1759:1985:2211))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_89/C1 (1940:2182:2424)(1940:2182:2424))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_98/D1 (1903:2095:2288)(1903:2095:2288))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_109/C1 (1576:1786:1997)(1576:1786:1997))
+        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_2/Q0 SLICE_23/B0 (786:914:1043)(786:914:1043))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_56/D0 (914:1006:1099)(914:1006:1099))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_58/A0 (1884:2108:2332)(1884:2108:2332))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_64/B0 (2607:2900:3193)(2607:2900:3193))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_70/B0 (1911:2137:2363)(1911:2137:2363))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_75/D0 (1294:1419:1545)(1294:1419:1545))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_76/B0 (1911:2137:2363)(1911:2137:2363))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_81/A0 (2586:2877:3169)(2586:2877:3169))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_85/D1 (1294:1419:1545)(1294:1419:1545))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_89/D1 (2049:2240:2431)(2049:2240:2431))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_97/C1 (2430:2708:2986)(2430:2708:2986))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_103/D1 (1674:1832:1991)(1674:1832:1991))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_111/D0 (1996:2189:2382)(1996:2189:2382))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_125/D1 (2794:3049:3305)(2794:3049:3305))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_128/D1 (2794:3049:3305)(2794:3049:3305))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_128/D0 (2794:3049:3305)(2794:3049:3305))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_131/D1 (914:1006:1099)(914:1006:1099))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_131/D0 (914:1006:1099)(914:1006:1099))
         (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (481:575:669)(481:575:669))
-        (INTERCONNECT SLICE_3/Q1 SLICE_44/D1 (528:582:636)(528:582:636))
-        (INTERCONNECT SLICE_3/Q1 SLICE_46/C1 (841:988:1135)(841:988:1135))
-        (INTERCONNECT SLICE_3/Q1 SLICE_56/A0 (1410:1599:1789)(1410:1599:1789))
-        (INTERCONNECT SLICE_3/Q1 SLICE_58/A1 (1810:2034:2259)(1810:2034:2259))
-        (INTERCONNECT SLICE_3/Q1 SLICE_60/C0 (1241:1423:1605)(1241:1423:1605))
-        (INTERCONNECT SLICE_3/Q1 SLICE_61/D1 (1230:1357:1484)(1230:1357:1484))
-        (INTERCONNECT SLICE_3/Q1 SLICE_62/A1 (1440:1632:1825)(1440:1632:1825))
-        (INTERCONNECT SLICE_3/Q1 SLICE_64/B0 (1442:1634:1826)(1442:1634:1826))
-        (INTERCONNECT SLICE_3/Q1 SLICE_65/C0 (1216:1395:1575)(1216:1395:1575))
-        (INTERCONNECT SLICE_3/Q1 SLICE_66/C0 (841:988:1135)(841:988:1135))
-        (INTERCONNECT SLICE_3/Q1 SLICE_70/C1 (1611:1825:2039)(1611:1825:2039))
-        (INTERCONNECT SLICE_3/Q1 SLICE_73/C1 (841:988:1135)(841:988:1135))
-        (INTERCONNECT SLICE_3/Q1 SLICE_74/C0 (2026:2284:2542)(2026:2284:2542))
-        (INTERCONNECT SLICE_3/Q1 SLICE_84/C1 (2026:2284:2542)(2026:2284:2542))
-        (INTERCONNECT SLICE_3/Q1 SLICE_88/B1 (1472:1667:1862)(1472:1667:1862))
-        (INTERCONNECT SLICE_3/Q1 SLICE_90/C0 (1241:1423:1605)(1241:1423:1605))
-        (INTERCONNECT SLICE_3/Q1 SLICE_92/C1 (841:988:1135)(841:988:1135))
-        (INTERCONNECT SLICE_3/Q1 SLICE_95/C1 (841:988:1135)(841:988:1135))
-        (INTERCONNECT SLICE_3/Q1 SLICE_97/D1 (1230:1357:1484)(1230:1357:1484))
-        (INTERCONNECT SLICE_3/Q1 SLICE_108/C1 (1216:1395:1575)(1216:1395:1575))
-        (INTERCONNECT SLICE_3/Q1 SLICE_108/C0 (1216:1395:1575)(1216:1395:1575))
+        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_56/C0 (1305:1485:1666)(1305:1485:1666))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_58/A1 (1524:1717:1910)(1524:1717:1910))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_68/C0 (1695:1909:2124)(1695:1909:2124))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_70/A0 (2269:2526:2784)(2269:2526:2784))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_75/A0 (1894:2119:2344)(1894:2119:2344))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_76/D0 (2397:2626:2855)(2397:2626:2855))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_81/C0 (1695:1909:2124)(1695:1909:2124))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_85/C1 (1996:2243:2490)(1996:2243:2490))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_90/A1 (1904:2130:2356)(1904:2130:2356))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_93/A0 (1904:2130:2356)(1904:2130:2356))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_97/B1 (2300:2560:2820)(2300:2560:2820))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_99/B0 (1931:2159:2387)(1931:2159:2387))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_103/C1 (1700:1915:2130)(1700:1915:2130))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_104/A0 (2269:2526:2784)(2269:2526:2784))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_111/D1 (2397:2626:2855)(2397:2626:2855))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_114/B0 (2258:2521:2784)(2258:2521:2784))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_124/D1 (539:599:659)(539:599:659))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_126/C1 (1299:1479:1659)(1299:1479:1659))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_126/A0 (1524:1717:1910)(1524:1717:1910))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_128/B1 (2997:3324:3651)(2997:3324:3651))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_128/C0 (2075:2322:2570)(2075:2322:2570))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_131/C1 (1262:1445:1629)(1262:1445:1629))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_131/A0 (1134:1293:1452)(1134:1293:1452))
         (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_3/Q0 SLICE_44/A1 (738:861:985)(738:861:985))
-        (INTERCONNECT SLICE_3/Q0 SLICE_50/C1 (1647:1867:2087)(1647:1867:2087))
-        (INTERCONNECT SLICE_3/Q0 SLICE_58/A0 (2216:2478:2741)(2216:2478:2741))
-        (INTERCONNECT SLICE_3/Q0 SLICE_61/A0 (2216:2478:2741)(2216:2478:2741))
-        (INTERCONNECT SLICE_3/Q0 SLICE_62/C1 (1642:1861:2081)(1642:1861:2081))
-        (INTERCONNECT SLICE_3/Q0 SLICE_64/C1 (1642:1861:2081)(1642:1861:2081))
-        (INTERCONNECT SLICE_3/Q0 SLICE_65/B1 (1868:2100:2332)(1868:2100:2332))
-        (INTERCONNECT SLICE_3/Q0 SLICE_66/B0 (1478:1676:1874)(1478:1676:1874))
-        (INTERCONNECT SLICE_3/Q0 SLICE_68/D0 (1636:1801:1966)(1636:1801:1966))
-        (INTERCONNECT SLICE_3/Q0 SLICE_70/C0 (2344:2631:2918)(2344:2631:2918))
-        (INTERCONNECT SLICE_3/Q0 SLICE_73/A1 (2211:2473:2735)(2211:2473:2735))
-        (INTERCONNECT SLICE_3/Q0 SLICE_74/B1 (1825:2060:2295)(1825:2060:2295))
-        (INTERCONNECT SLICE_3/Q0 SLICE_89/B1 (2195:2462:2729)(2195:2462:2729))
-        (INTERCONNECT SLICE_3/Q0 SLICE_90/C1 (2344:2631:2918)(2344:2631:2918))
-        (INTERCONNECT SLICE_3/Q0 SLICE_92/D1 (2001:2197:2394)(2001:2197:2394))
-        (INTERCONNECT SLICE_3/Q0 SLICE_104/A1 (1466:1663:1861)(1466:1663:1861))
-        (INTERCONNECT SLICE_3/Q0 SLICE_104/A0 (1466:1663:1861)(1466:1663:1861))
-        (INTERCONNECT SLICE_3/Q0 SLICE_116/B0 (1805:2038:2271)(1805:2038:2271))
+        (INTERCONNECT SLICE_3/Q0 SLICE_22/C0 (811:959:1107)(811:959:1107))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_56/A0 (1374:1564:1754)(1374:1564:1754))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_64/C1 (1597:1821:2046)(1597:1821:2046))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_64/D0 (1259:1393:1528)(1259:1393:1528))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_68/A0 (1844:2076:2309)(1844:2076:2309))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_73/A0 (1448:1646:1844)(1448:1646:1844))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_75/A1 (1844:2076:2309)(1844:2076:2309))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_76/C1 (1275:1465:1655)(1275:1465:1655))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_88/B1 (1506:1709:1912)(1506:1709:1912))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_90/B1 (1506:1709:1912)(1506:1709:1912))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_93/A1 (1844:2076:2309)(1844:2076:2309))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_99/D1 (1259:1393:1528)(1259:1393:1528))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_104/A1 (1838:2070:2302)(1838:2070:2302))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_109/C0 (1634:1855:2076)(1634:1855:2076))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_110/A1 (1844:2076:2309)(1844:2076:2309))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_114/D0 (1259:1393:1528)(1259:1393:1528))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_123/D1 (1623:1789:1955)(1623:1789:1955))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_123/D0 (1623:1789:1955)(1623:1789:1955))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_125/B1 (1865:2099:2333)(1865:2099:2333))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_125/B0 (1865:2099:2333)(1865:2099:2333))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_128/C1 (1634:1855:2076)(1634:1855:2076))
         (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_4/Q1 SLICE_46/D1 (933:1027:1122)(933:1027:1122))
-        (INTERCONNECT SLICE_4/Q1 SLICE_50/D1 (1313:1440:1568)(1313:1440:1568))
-        (INTERCONNECT SLICE_4/Q1 SLICE_58/B0 (1945:2174:2404)(1945:2174:2404))
-        (INTERCONNECT SLICE_4/Q1 SLICE_60/B0 (1570:1767:1964)(1570:1767:1964))
-        (INTERCONNECT SLICE_4/Q1 SLICE_61/C0 (1339:1523:1707)(1339:1523:1707))
-        (INTERCONNECT SLICE_4/Q1 SLICE_62/D0 (1328:1457:1586)(1328:1457:1586))
-        (INTERCONNECT SLICE_4/Q1 SLICE_64/D0 (1692:1852:2013)(1692:1852:2013))
-        (INTERCONNECT SLICE_4/Q1 SLICE_65/D0 (933:1027:1122)(933:1027:1122))
-        (INTERCONNECT SLICE_4/Q1 SLICE_68/B0 (2309:2570:2831)(2309:2570:2831))
-        (INTERCONNECT SLICE_4/Q1 SLICE_70/D0 (1703:1864:2026)(1703:1864:2026))
-        (INTERCONNECT SLICE_4/Q1 SLICE_74/B0 (1555:1750:1946)(1555:1750:1946))
-        (INTERCONNECT SLICE_4/Q1 SLICE_84/D1 (1313:1440:1568)(1313:1440:1568))
-        (INTERCONNECT SLICE_4/Q1 SLICE_89/D1 (933:1027:1122)(933:1027:1122))
-        (INTERCONNECT SLICE_4/Q1 SLICE_90/B1 (1570:1767:1964)(1570:1767:1964))
-        (INTERCONNECT SLICE_4/Q1 SLICE_95/D1 (933:1027:1122)(933:1027:1122))
-        (INTERCONNECT SLICE_4/Q1 SLICE_97/C1 (1339:1523:1707)(1339:1523:1707))
-        (INTERCONNECT SLICE_4/Q1 SLICE_104/C0 (1324:1506:1689)(1324:1506:1689))
-        (INTERCONNECT SLICE_4/Q1 SLICE_108/D1 (933:1027:1122)(933:1027:1122))
-        (INTERCONNECT SLICE_4/Q1 SLICE_108/D0 (933:1027:1122)(933:1027:1122))
-        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_4/Q0 SLICE_46/A1 (1023:1177:1331)(1023:1177:1331))
-        (INTERCONNECT SLICE_4/Q0 SLICE_50/A1 (1798:2019:2241)(1798:2019:2241))
-        (INTERCONNECT SLICE_4/Q0 SLICE_50/A0 (1798:2019:2241)(1798:2019:2241))
-        (INTERCONNECT SLICE_4/Q0 SLICE_58/C0 (1599:1810:2021)(1599:1810:2021))
-        (INTERCONNECT SLICE_4/Q0 SLICE_61/B0 (1455:1646:1838)(1455:1646:1838))
-        (INTERCONNECT SLICE_4/Q0 SLICE_62/C0 (1224:1402:1581)(1224:1402:1581))
-        (INTERCONNECT SLICE_4/Q0 SLICE_64/A1 (1787:2007:2228)(1787:2007:2228))
-        (INTERCONNECT SLICE_4/Q0 SLICE_65/A1 (1393:1579:1765)(1393:1579:1765))
-        (INTERCONNECT SLICE_4/Q0 SLICE_68/A0 (2162:2415:2668)(2162:2415:2668))
-        (INTERCONNECT SLICE_4/Q0 SLICE_70/A0 (1798:2019:2241)(1798:2019:2241))
-        (INTERCONNECT SLICE_4/Q0 SLICE_74/A1 (2178:2432:2687)(2178:2432:2687))
-        (INTERCONNECT SLICE_4/Q0 SLICE_89/D0 (1968:2157:2346)(1968:2157:2346))
-        (INTERCONNECT SLICE_4/Q0 SLICE_90/A1 (1423:1612:1801)(1423:1612:1801))
-        (INTERCONNECT SLICE_4/Q0 SLICE_104/B1 (2210:2467:2724)(2210:2467:2724))
-        (INTERCONNECT SLICE_4/Q0 SLICE_104/B0 (2210:2467:2724)(2210:2467:2724))
-        (INTERCONNECT SLICE_4/Q0 SLICE_105/C1 (1224:1402:1581)(1224:1402:1581))
-        (INTERCONNECT SLICE_4/Q0 SLICE_105/C0 (1224:1402:1581)(1224:1402:1581))
-        (INTERCONNECT SLICE_4/Q0 SLICE_108/A1 (1393:1579:1765)(1393:1579:1765))
-        (INTERCONNECT SLICE_4/Q0 SLICE_116/A1 (1023:1177:1331)(1023:1177:1331))
-        (INTERCONNECT SLICE_4/Q0 SLICE_116/A0 (1023:1177:1331)(1023:1177:1331))
+        (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_4/Q1 SLICE_21/B1 (777:906:1036)(777:906:1036))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_47/A0 (1458:1654:1851)(1458:1654:1851))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_68/D0 (1670:1830:1990)(1670:1830:1990))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_73/D0 (1290:1417:1544)(1290:1417:1544))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_75/D1 (2050:2243:2436)(2050:2243:2436))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_76/D1 (2050:2243:2436)(2050:2243:2436))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_88/D1 (2050:2243:2436)(2050:2243:2436))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_90/C1 (1671:1885:2099)(1671:1885:2099))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_93/B1 (1912:2140:2368)(1912:2140:2368))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_99/A1 (1458:1654:1851)(1458:1654:1851))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_104/C1 (1681:1896:2111)(1681:1896:2111))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_110/B1 (2656:2948:3241)(2656:2948:3241))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_114/D1 (910:1004:1098)(910:1004:1098))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_123/A0 (1848:2079:2311)(1848:2079:2311))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_126/D1 (2030:2221:2412)(2030:2221:2412))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_126/D0 (2030:2221:2412)(2030:2221:2412))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_128/A1 (1848:2079:2311)(1848:2079:2311))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_128/A0 (1848:2079:2311)(1848:2079:2311))
+        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_64/A1 (1006:1166:1326)(1006:1166:1326))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_68/B1 (1231:1403:1576)(1231:1403:1576))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_73/C0 (1369:1560:1752)(1369:1560:1752))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_75/B1 (1606:1811:2016)(1606:1811:2016))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_81/C1 (1739:1962:2186)(1739:1962:2186))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_93/C1 (1369:1560:1752)(1369:1560:1752))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_104/B1 (1558:1765:1973)(1558:1765:1973))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_110/D1 (1728:1896:2065)(1728:1896:2065))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_111/A0 (1901:2138:2376)(1901:2138:2376))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_114/B1 (1241:1414:1588)(1241:1414:1588))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_123/B1 (1241:1414:1588)(1241:1414:1588))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_123/B0 (1241:1414:1588)(1241:1414:1588))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_125/A1 (1536:1742:1948)(1536:1742:1948))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_125/D0 (1326:1466:1607)(1326:1466:1607))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_126/B1 (2308:2581:2855)(2308:2581:2855))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_126/B0 (2308:2581:2855)(2308:2581:2855))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_134/C0 (807:956:1106)(807:956:1106))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_145/A0 (1568:1770:1972)(1568:1770:1972))
         (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_5/Q1 SLICE_46/B1 (1491:1683:1876)(1491:1683:1876))
-        (INTERCONNECT SLICE_5/Q1 SLICE_50/B1 (1871:2096:2322)(1871:2096:2322))
-        (INTERCONNECT SLICE_5/Q1 SLICE_58/D0 (1994:2183:2372)(1994:2183:2372))
-        (INTERCONNECT SLICE_5/Q1 SLICE_61/D0 (2326:2550:2775)(2326:2550:2775))
-        (INTERCONNECT SLICE_5/Q1 SLICE_62/B0 (1866:2091:2316)(1866:2091:2316))
-        (INTERCONNECT SLICE_5/Q1 SLICE_64/B1 (2230:2486:2743)(2230:2486:2743))
-        (INTERCONNECT SLICE_5/Q1 SLICE_65/D1 (1587:1748:1910)(1587:1748:1910))
-        (INTERCONNECT SLICE_5/Q1 SLICE_68/C0 (2004:2248:2492)(2004:2248:2492))
-        (INTERCONNECT SLICE_5/Q1 SLICE_70/B0 (2236:2493:2750)(2236:2493:2750))
-        (INTERCONNECT SLICE_5/Q1 SLICE_85/D1 (1587:1748:1910)(1587:1748:1910))
-        (INTERCONNECT SLICE_5/Q1 SLICE_86/B1 (2241:2498:2756)(2241:2498:2756))
-        (INTERCONNECT SLICE_5/Q1 SLICE_89/B0 (1491:1683:1876)(1491:1683:1876))
-        (INTERCONNECT SLICE_5/Q1 SLICE_104/C1 (1967:2214:2462)(1967:2214:2462))
-        (INTERCONNECT SLICE_5/Q1 SLICE_116/B1 (1491:1683:1876)(1491:1683:1876))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_68/C1 (1343:1539:1736)(1343:1539:1736))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_68/B0 (1247:1421:1596)(1247:1421:1596))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_70/B1 (1617:1823:2030)(1617:1823:2030))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_73/B0 (1596:1800:2005)(1596:1800:2005))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_81/B1 (1622:1829:2036)(1622:1829:2036))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_93/D1 (1005:1111:1218)(1005:1111:1218))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_99/C1 (1016:1177:1339)(1016:1177:1339))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_104/D1 (984:1088:1193)(984:1088:1193))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_107/B0 (2350:2620:2890)(2350:2620:2890))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_110/C1 (995:1154:1314)(995:1154:1314))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_114/C1 (1016:1177:1339)(1016:1177:1339))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_123/C1 (1016:1177:1339)(1016:1177:1339))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_123/C0 (1016:1177:1339)(1016:1177:1339))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_125/C1 (1016:1177:1339)(1016:1177:1339))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_125/A0 (1949:2184:2420)(1949:2184:2420))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_126/A1 (1917:2156:2396)(1917:2156:2396))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_145/D0 (1354:1490:1627)(1354:1490:1627))
         (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_5/Q0 SLICE_32/A1 (1441:1635:1829)(1441:1635:1829))
-        (INTERCONNECT SLICE_5/Q0 SLICE_63/D1 (528:586:644)(528:586:644))
-        (INTERCONNECT SLICE_5/Q0 SLICE_75/B1 (2164:2427:2690)(2164:2427:2690))
+        (INTERCONNECT SLICE_5/Q0 SLICE_20/B0 (781:909:1037)(781:909:1037))
+        (INTERCONNECT SLICE_5/Q0 ram2e_ufm\/SLICE_108/D1 (1236:1363:1490)(1236:1363:1490))
+        (INTERCONNECT SLICE_5/Q0 ram2e_ufm\/SLICE_146/D0 (1600:1758:1917)(1600:1758:1917))
         (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_5/F0 SLICE_5/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_6/Q1 SLICE_32/C1 (814:956:1099)(814:956:1099))
-        (INTERCONNECT SLICE_6/Q1 SLICE_63/B1 (1409:1596:1783)(1409:1596:1783))
-        (INTERCONNECT SLICE_6/Q1 SLICE_75/C1 (1178:1352:1526)(1178:1352:1526))
+        (INTERCONNECT SLICE_6/Q1 ram2e_ufm\/SLICE_134/C1 (555:670:786)(555:670:786))
+        (INTERCONNECT SLICE_6/Q1 ram2e_ufm\/SLICE_134/A0 (1081:1242:1403)(1081:1242:1403))
+        (INTERCONNECT SLICE_6/Q1 ram2e_ufm\/SLICE_146/B0 (786:914:1043)(786:914:1043))
         (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_6/Q0 SLICE_55/D1 (549:610:671)(549:610:671))
-        (INTERCONNECT SLICE_6/Q0 SLICE_55/D0 (549:610:671)(549:610:671))
-        (INTERCONNECT SLICE_6/Q0 SLICE_72/C1 (924:1071:1219)(924:1071:1219))
-        (INTERCONNECT SLICE_6/Q0 SLICE_76/B1 (1155:1315:1476)(1155:1315:1476))
+        (INTERCONNECT SLICE_6/Q0 ram2e_ufm\/SLICE_107/D0 (978:1078:1179)(978:1078:1179))
+        (INTERCONNECT SLICE_6/Q0 ram2e_ufm\/SLICE_108/A1 (1188:1354:1520)(1188:1354:1520))
+        (INTERCONNECT SLICE_6/Q0 ram2e_ufm\/SLICE_146/A0 (1182:1347:1513)(1182:1347:1513))
         (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_7/Q1 SLICE_55/A1 (754:880:1006)(754:880:1006))
-        (INTERCONNECT SLICE_7/Q1 SLICE_71/A1 (1129:1287:1446)(1129:1287:1446))
-        (INTERCONNECT SLICE_7/Q1 SLICE_76/A1 (1129:1287:1446)(1129:1287:1446))
-        (INTERCONNECT SLICE_7/Q1 SLICE_78/A1 (1129:1287:1446)(1129:1287:1446))
-        (INTERCONNECT SLICE_7/Q1 SLICE_119/A0 (754:880:1006)(754:880:1006))
+        (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_7/Q1 SLICE_35/A1 (1195:1363:1532)(1195:1363:1532))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_57/D1 (1301:1438:1575)(1301:1438:1575))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_67/C0 (1275:1463:1652)(1275:1463:1652))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_71/B1 (1506:1707:1909)(1506:1707:1909))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_72/A1 (1195:1363:1532)(1195:1363:1532))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_107/A1 (1094:1259:1424)(1094:1259:1424))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_108/B1 (1126:1293:1461)(1126:1293:1461))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_122/C1 (1275:1463:1652)(1275:1463:1652))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_122/C0 (1275:1463:1652)(1275:1463:1652))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_124/B1 (1506:1707:1909)(1506:1707:1909))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_124/B0 (1506:1707:1909)(1506:1707:1909))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_129/B1 (1565:1773:1981)(1565:1773:1981))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_129/B0 (1565:1773:1981)(1565:1773:1981))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_146/A1 (756:884:1012)(756:884:1012))
         (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_7/Q0 SLICE_55/A0 (754:880:1006)(754:880:1006))
-        (INTERCONNECT SLICE_7/Q0 SLICE_63/A0 (754:880:1006)(754:880:1006))
-        (INTERCONNECT SLICE_7/Q0 SLICE_72/B1 (1150:1310:1470)(1150:1310:1470))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_67/A1 (1159:1320:1482)(1159:1320:1482))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_67/A0 (1159:1320:1482)(1159:1320:1482))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_71/A1 (1159:1320:1482)(1159:1320:1482))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_107/C0 (565:681:798)(565:681:798))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_122/A1 (1159:1320:1482)(1159:1320:1482))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_122/A0 (1159:1320:1482)(1159:1320:1482))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_124/A1 (1159:1320:1482)(1159:1320:1482))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_124/A0 (1159:1320:1482)(1159:1320:1482))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_131/A1 (764:891:1018)(764:891:1018))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_134/D1 (881:977:1074)(881:977:1074))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_134/B0 (796:925:1055)(796:925:1055))
         (INTERCONNECT SLICE_7/F1 SLICE_7/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_8/Q1 SLICE_55/B0 (786:914:1043)(786:914:1043))
-        (INTERCONNECT SLICE_8/Q1 SLICE_63/B0 (786:914:1043)(786:914:1043))
-        (INTERCONNECT SLICE_8/Q1 SLICE_119/B0 (786:914:1043)(786:914:1043))
+        (INTERCONNECT SLICE_8/Q1 ram2e_ufm\/SLICE_57/B1 (1113:1276:1440)(1113:1276:1440))
+        (INTERCONNECT SLICE_8/Q1 ram2e_ufm\/SLICE_67/B1 (1161:1322:1483)(1161:1322:1483))
+        (INTERCONNECT SLICE_8/Q1 ram2e_ufm\/SLICE_122/B1 (1161:1322:1483)(1161:1322:1483))
+        (INTERCONNECT SLICE_8/Q1 ram2e_ufm\/SLICE_122/B0 (1161:1322:1483)(1161:1322:1483))
+        (INTERCONNECT SLICE_8/Q1 ram2e_ufm\/SLICE_134/A1 (754:880:1006)(754:880:1006))
         (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_8/Q0 SLICE_55/C0 (892:1045:1199)(892:1045:1199))
-        (INTERCONNECT SLICE_8/Q0 SLICE_63/C0 (892:1045:1199)(892:1045:1199))
-        (INTERCONNECT SLICE_8/Q0 SLICE_119/C0 (892:1045:1199)(892:1045:1199))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_67/D1 (914:1006:1099)(914:1006:1099))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_122/D1 (1252:1381:1511)(1252:1381:1511))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_122/D0 (1252:1381:1511)(1252:1381:1511))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_124/C0 (920:1067:1214)(920:1067:1214))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_129/A0 (1488:1677:1867)(1488:1677:1867))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_131/B1 (1521:1713:1905)(1521:1713:1905))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_134/B1 (1521:1713:1905)(1521:1713:1905))
         (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_32/Q0 SLICE_9/D1 (526:578:630)(526:578:630))
-        (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT PHI1_MGIOL/IN SLICE_9/C1 (1174:1343:1512)(1174:1343:1512))
-        (INTERCONNECT PHI1_I/PADDI SLICE_9/B1 (2197:2413:2629)(2197:2413:2629))
-        (INTERCONNECT PHI1_I/PADDI nVOE_I/PADDO (3417:3711:4005)(3417:3711:4005))
-        (INTERCONNECT PHI1_I/PADDI PHI1_MGIOL/DI (544:554:565)(544:554:565))
-        (INTERCONNECT SLICE_31/Q0 SLICE_9/C0 (874:1022:1170)(874:1022:1170))
-        (INTERCONNECT SLICE_31/Q0 SLICE_12/B0 (1860:2086:2313)(1860:2086:2313))
-        (INTERCONNECT SLICE_31/Q0 SLICE_13/D1 (1993:2184:2375)(1993:2184:2375))
-        (INTERCONNECT SLICE_31/Q0 SLICE_13/D0 (1993:2184:2375)(1993:2184:2375))
-        (INTERCONNECT SLICE_31/Q0 SLICE_14/C0 (819:962:1105)(819:962:1105))
-        (INTERCONNECT SLICE_31/Q0 SLICE_15/D0 (1988:2178:2369)(1988:2178:2369))
-        (INTERCONNECT SLICE_31/Q0 SLICE_16/B0 (1860:2086:2313)(1860:2086:2313))
-        (INTERCONNECT SLICE_31/Q0 SLICE_17/B0 (2600:2890:3181)(2600:2890:3181))
-        (INTERCONNECT SLICE_31/Q0 SLICE_18/C0 (1183:1357:1532)(1183:1357:1532))
-        (INTERCONNECT SLICE_31/Q0 SLICE_19/C1 (819:962:1105)(819:962:1105))
-        (INTERCONNECT SLICE_31/Q0 SLICE_19/C0 (819:962:1105)(819:962:1105))
-        (INTERCONNECT SLICE_31/Q0 SLICE_49/B1 (3093:3419:3745)(3093:3419:3745))
-        (INTERCONNECT SLICE_31/Q0 SLICE_49/B0 (3093:3419:3745)(3093:3419:3745))
-        (INTERCONNECT SLICE_31/Q0 SLICE_53/C1 (1956:2204:2453)(1956:2204:2453))
-        (INTERCONNECT SLICE_31/Q0 SLICE_57/D1 (1233:1358:1483)(1233:1358:1483))
-        (INTERCONNECT SLICE_31/Q0 SLICE_67/A0 (3259:3613:3968)(3259:3613:3968))
-        (INTERCONNECT SLICE_31/Q0 SLICE_82/C1 (2492:2773:3054)(2492:2773:3054))
-        (INTERCONNECT SLICE_31/Q0 SLICE_87/A1 (2691:2982:3274)(2691:2982:3274))
-        (INTERCONNECT SLICE_31/Q0 SLICE_91/B0 (2723:3017:3311)(2723:3017:3311))
-        (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_9/Q0 SLICE_19/A1 (1590:1781:1972)(1590:1781:1972))
-        (INTERCONNECT SLICE_9/Q0 SLICE_19/A0 (1590:1781:1972)(1590:1781:1972))
-        (INTERCONNECT SLICE_9/Q0 SLICE_82/B1 (1986:2211:2436)(1986:2211:2436))
+        (INTERCONNECT SLICE_33/Q1 SLICE_9/D1 (556:619:683)(556:619:683))
+        (INTERCONNECT SLICE_33/Q1 SLICE_9/D0 (556:619:683)(556:619:683))
+        (INTERCONNECT SLICE_33/Q1 SLICE_33/B0 (778:905:1032)(778:905:1032))
+        (INTERCONNECT SLICE_33/Q1 SLICE_35/B1 (1120:1286:1452)(1120:1286:1452))
+        (INTERCONNECT SLICE_33/Q1 SLICE_36/D1 (946:1043:1141)(946:1043:1141))
+        (INTERCONNECT SLICE_33/Q1 SLICE_37/D1 (1326:1456:1587)(1326:1456:1587))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_56/C1 (2034:2286:2539)(2034:2286:2539))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/CKE_7\/SLICE_61/A0 (1156:1319:1482)
+          (1156:1319:1482))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_67/D0 (1326:1456:1587)(1326:1456:1587))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_69/A0 (1900:2127:2355)(1900:2127:2355))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_72/A0 (1099:1264:1430)(1099:1264:1430))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_74/A0 (1099:1264:1430)(1099:1264:1430))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_77/C0 (2555:2838:3122)(2555:2838:3122))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_78/B1 (2308:2570:2833)(2308:2570:2833))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_80/D1 (1263:1396:1530)(1263:1396:1530))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_92/B1 (1188:1353:1519)(1188:1353:1519))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_95/D1 (1326:1456:1587)(1326:1456:1587))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_96/D1 (1326:1456:1587)(1326:1456:1587))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_102/C1 (957:1109:1262)(957:1109:1262))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_106/B1 (778:905:1032)(778:905:1032))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_112/D1 (1326:1456:1587)(1326:1456:1587))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_113/A0 (1900:2127:2355)(1900:2127:2355))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_115/D1 (556:619:683)(556:619:683))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_117/D1 (1386:1524:1662)(1386:1524:1662))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_117/D0 (1386:1524:1662)(1386:1524:1662))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_118/C1 (1397:1590:1783)(1397:1590:1783))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_118/C0 (1397:1590:1783)(1397:1590:1783))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_119/C1 (910:1067:1224)(910:1067:1224))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_119/C0 (910:1067:1224)(910:1067:1224))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_121/D1 (1263:1396:1530)(1263:1396:1530))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_121/D0 (1263:1396:1530)(1263:1396:1530))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_127/C1 (910:1067:1224)(910:1067:1224))
+        (INTERCONNECT SLICE_33/Q1 SLICE_138/D1 (2914:3174:3435)(2914:3174:3435))
+        (INTERCONNECT SLICE_33/Q1 SLICE_138/D0 (2914:3174:3435)(2914:3174:3435))
+        (INTERCONNECT SLICE_33/Q0 SLICE_9/B1 (776:908:1040)(776:908:1040))
+        (INTERCONNECT SLICE_33/Q0 SLICE_9/C0 (546:671:796)(546:671:796))
+        (INTERCONNECT SLICE_33/Q0 SLICE_35/D1 (570:638:707)(570:638:707))
+        (INTERCONNECT SLICE_33/Q0 SLICE_36/B1 (1059:1233:1407)(1059:1233:1407))
+        (INTERCONNECT SLICE_33/Q0 SLICE_37/B1 (1444:1651:1859)(1444:1651:1859))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_56/B1 (1824:2064:2305)(1824:2064:2305))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_69/B0 (1444:1651:1859)(1444:1651:1859))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_71/A0 (2119:2392:2665)(2119:2392:2665))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_72/D1 (570:638:707)(570:638:707))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_74/C0 (929:1091:1254)(929:1091:1254))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_77/A0 (2655:2960:3266)(2655:2960:3266))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_78/D1 (1967:2173:2379)(1967:2173:2379))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_80/C1 (1978:2239:2500)(1978:2239:2500))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_92/D0 (817:923:1029)(817:923:1029))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_95/B1 (1429:1635:1841)(1429:1635:1841))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_96/B1 (1429:1635:1841)(1429:1635:1841))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_106/C1 (540:656:772)(540:656:772))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_107/B1 (2188:2460:2732)(2188:2460:2732))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_112/B1 (1444:1651:1859)(1444:1651:1859))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_113/B0 (1444:1651:1859)(1444:1651:1859))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_115/D0 (534:598:662)(534:598:662))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_117/C1 (874:1044:1214)(874:1044:1214))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_117/C0 (874:1044:1214)(874:1044:1214))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_118/B1 (1105:1288:1471)(1105:1288:1471))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_118/B0 (1105:1288:1471)(1105:1288:1471))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_119/D1 (570:638:707)(570:638:707))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_119/D0 (570:638:707)(570:638:707))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_120/D1 (545:611:677)(545:611:677))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_120/D0 (545:611:677)(545:611:677))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_121/A1 (2177:2448:2720)(2177:2448:2720))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_121/A0 (2177:2448:2720)(2177:2448:2720))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_127/D1 (570:638:707)(570:638:707))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_127/D0 (570:638:707)(570:638:707))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_129/C1 (929:1091:1254)(929:1091:1254))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_129/C0 (929:1091:1254)(929:1091:1254))
+        (INTERCONNECT SLICE_33/Q0 SLICE_138/A1 (3352:3724:4097)(3352:3724:4097))
+        (INTERCONNECT SLICE_33/Q0 SLICE_138/B0 (3057:3397:3737)(3057:3397:3737))
+        (INTERCONNECT SLICE_35/F0 SLICE_9/A1 (1019:1185:1351)(1019:1185:1351))
+        (INTERCONNECT SLICE_35/F0 SLICE_9/A0 (1019:1185:1351)(1019:1185:1351))
+        (INTERCONNECT SLICE_35/F0 SLICE_35/C1 (284:372:461)(284:372:461))
+        (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (7:16:25)(7:16:25))
+        (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_80/A1 (740:864:989)(740:864:989))
+        (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_92/A1 (1383:1580:1778)(1383:1580:1778))
+        (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_129/D0 (532:597:662)(532:597:662))
+        (INTERCONNECT ram2e_ufm\/CKE_7\/SLICE_61/OFX0 SLICE_9/B0 (1099:1259:1420)
+          (1099:1259:1420))
         (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20/F1 SLICE_9/CE (2023:2253:2484)(2023:2253:2484))
-        (INTERCONNECT SLICE_20/F1 SLICE_12/CE (2023:2253:2484)(2023:2253:2484))
-        (INTERCONNECT SLICE_20/F1 SLICE_13/CE (2023:2253:2484)(2023:2253:2484))
-        (INTERCONNECT SLICE_20/F1 SLICE_14/CE (2023:2253:2484)(2023:2253:2484))
-        (INTERCONNECT SLICE_20/F1 SLICE_15/CE (2023:2253:2484)(2023:2253:2484))
-        (INTERCONNECT SLICE_20/F1 SLICE_16/CE (2023:2253:2484)(2023:2253:2484))
-        (INTERCONNECT SLICE_20/F1 SLICE_17/CE (2023:2253:2484)(2023:2253:2484))
-        (INTERCONNECT SLICE_20/F1 SLICE_18/CE (2023:2253:2484)(2023:2253:2484))
-        (INTERCONNECT SLICE_20/F1 SLICE_19/CE (2023:2253:2484)(2023:2253:2484))
-        (INTERCONNECT SLICE_20/F1 SLICE_19/CE (2023:2253:2484)(2023:2253:2484))
-        (INTERCONNECT SLICE_20/F1 Dout\[7\]_MGIOL/CE (2205:2457:2710)(2205:2457:2710))
-        (INTERCONNECT SLICE_20/F1 Dout\[6\]_MGIOL/CE (2205:2457:2710)(2205:2457:2710))
-        (INTERCONNECT SLICE_20/F1 Dout\[5\]_MGIOL/CE (2205:2457:2710)(2205:2457:2710))
-        (INTERCONNECT SLICE_20/F1 Dout\[4\]_MGIOL/CE (2205:2457:2710)(2205:2457:2710))
-        (INTERCONNECT SLICE_20/F1 Dout\[3\]_MGIOL/CE (2205:2457:2710)(2205:2457:2710))
-        (INTERCONNECT SLICE_20/F1 Dout\[2\]_MGIOL/CE (2205:2457:2710)(2205:2457:2710))
-        (INTERCONNECT SLICE_20/F1 Dout\[1\]_MGIOL/CE (2205:2457:2710)(2205:2457:2710))
-        (INTERCONNECT SLICE_20/F1 Dout\[0\]_MGIOL/CE (2205:2457:2710)(2205:2457:2710))
-        (INTERCONNECT SLICE_9/F1 SLICE_33/D1 (546:605:664)(546:605:664))
-        (INTERCONNECT SLICE_9/F1 SLICE_33/B0 (1115:1277:1439)(1115:1277:1439))
-        (INTERCONNECT SLICE_9/F1 SLICE_34/C1 (557:671:785)(557:671:785))
-        (INTERCONNECT SLICE_9/F1 SLICE_34/C0 (557:671:785)(557:671:785))
-        (INTERCONNECT SLICE_57/F0 SLICE_10/D1 (1782:1951:2121)(1782:1951:2121))
-        (INTERCONNECT SLICE_57/F0 SLICE_10/C0 (1466:1655:1845)(1466:1655:1845))
-        (INTERCONNECT SLICE_57/F0 SLICE_11/B1 (1697:1899:2102)(1697:1899:2102))
-        (INTERCONNECT SLICE_57/F0 SLICE_57/B1 (765:889:1013)(765:889:1013))
-        (INTERCONNECT SLICE_57/F0 SLICE_82/A0 (2029:2260:2492)(2029:2260:2492))
-        (INTERCONNECT SLICE_10/Q0 SLICE_10/C1 (559:677:795)(559:677:795))
-        (INTERCONNECT SLICE_10/Q0 SLICE_10/A0 (483:579:675)(483:579:675))
-        (INTERCONNECT SLICE_10/Q0 SLICE_11/C1 (559:677:795)(559:677:795))
-        (INTERCONNECT SLICE_10/Q0 SLICE_49/A1 (753:882:1012)(753:882:1012))
-        (INTERCONNECT SLICE_10/Q0 SLICE_77/C1 (559:677:795)(559:677:795))
-        (INTERCONNECT SLICE_10/Q0 SLICE_81/A1 (753:882:1012)(753:882:1012))
-        (INTERCONNECT SLICE_10/Q0 SLICE_87/B1 (1117:1285:1454)(1117:1285:1454))
-        (INTERCONNECT SLICE_10/Q0 SLICE_91/B1 (1117:1285:1454)(1117:1285:1454))
-        (INTERCONNECT SLICE_82/F1 SLICE_10/B1 (771:904:1037)(771:904:1037))
-        (INTERCONNECT SLICE_82/F1 SLICE_10/B0 (771:904:1037)(771:904:1037))
-        (INTERCONNECT SLICE_82/F1 SLICE_11/D1 (529:594:659)(529:594:659))
-        (INTERCONNECT SLICE_82/F1 SLICE_82/B0 (765:889:1013)(765:889:1013))
-        (INTERCONNECT SLICE_10/Q1 SLICE_10/A1 (483:579:675)(483:579:675))
-        (INTERCONNECT SLICE_10/Q1 SLICE_11/D0 (538:599:660)(538:599:660))
-        (INTERCONNECT SLICE_10/Q1 SLICE_18/B1 (774:904:1034)(774:904:1034))
-        (INTERCONNECT SLICE_10/Q1 SLICE_49/A0 (758:888:1018)(758:888:1018))
-        (INTERCONNECT SLICE_10/Q1 SLICE_54/C1 (886:1040:1195)(886:1040:1195))
-        (INTERCONNECT SLICE_10/Q1 SLICE_87/D0 (532:594:656)(532:594:656))
-        (INTERCONNECT SLICE_10/Q1 SLICE_93/D0 (538:599:660)(538:599:660))
-        (INTERCONNECT SLICE_10/Q1 SLICE_94/A0 (758:888:1018)(758:888:1018))
-        (INTERCONNECT SLICE_10/F1 SLICE_10/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/Q0 CKEout_MGIOL/OPOS (2313:2510:2707)(2313:2510:2707))
+        (INTERCONNECT SLICE_9/F1 ram2e_ufm\/SLICE_56/CE (1277:1401:1526)(1277:1401:1526))
+        (INTERCONNECT SLICE_31/Q0 SLICE_10/B0 (1252:1425:1598)(1252:1425:1598))
+        (INTERCONNECT SLICE_31/Q0 SLICE_18/D1 (1010:1115:1220)(1010:1115:1220))
+        (INTERCONNECT SLICE_31/Q0 SLICE_18/D0 (1010:1115:1220)(1010:1115:1220))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/M0 
+          (975:1068:1162)(975:1068:1162))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_77/B1 (1237:1408:1580)(1237:1408:1580))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_79/C0 (805:952:1100)(805:952:1100))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_80/B0 (1467:1663:1859)(1467:1663:1859))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_83/B0 (1616:1820:2025)(1616:1820:2025))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_130/C1 (1006:1164:1323)(1006:1164:1323))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_130/C0 (1006:1164:1323)(1006:1164:1323))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_133/B1 (1601:1804:2007)(1601:1804:2007))
+        (INTERCONNECT SLICE_10/Q0 SLICE_10/A0 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_10/Q0 SLICE_18/C1 (547:661:775)(547:661:775))
+        (INTERCONNECT SLICE_10/Q0 SLICE_18/B0 (767:892:1017)(767:892:1017))
+        (INTERCONNECT SLICE_10/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/C0 
+          (547:661:775)(547:661:775))
         (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77/F0 SLICE_10/LSR (550:609:668)(550:609:668))
-        (INTERCONNECT SLICE_77/F0 SLICE_10/LSR (550:609:668)(550:609:668))
-        (INTERCONNECT SLICE_77/F0 SLICE_11/LSR (550:609:668)(550:609:668))
-        (INTERCONNECT SLICE_11/F1 SLICE_11/C0 (277:356:436)(277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_10/CE (1258:1384:1510)(1258:1384:1510))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_18/CE (1258:1384:1510)(1258:1384:1510))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_18/CE (1258:1384:1510)(1258:1384:1510))
+        (INTERCONNECT SLICE_10/F1 nCSout_I/PADDO (1536:1697:1858)(1536:1697:1858))
+        (INTERCONNECT SLICE_26/Q1 SLICE_11/D1 (554:615:676)(554:615:676))
+        (INTERCONNECT SLICE_26/Q1 SLICE_11/D0 (554:615:676)(554:615:676))
+        (INTERCONNECT SLICE_26/Q1 SLICE_26/A1 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_26/Q1 SLICE_26/D0 (554:615:676)(554:615:676))
+        (INTERCONNECT SLICE_26/Q1 ram2e_ufm\/SLICE_91/D1 (554:615:676)(554:615:676))
+        (INTERCONNECT SLICE_11/Q0 SLICE_11/A1 (748:874:1001)(748:874:1001))
         (INTERCONNECT SLICE_11/Q0 SLICE_11/A0 (483:579:675)(483:579:675))
-        (INTERCONNECT SLICE_11/Q0 SLICE_18/D1 (543:607:671)(543:607:671))
-        (INTERCONNECT SLICE_11/Q0 SLICE_49/D0 (543:607:671)(543:607:671))
-        (INTERCONNECT SLICE_11/Q0 SLICE_54/C0 (541:652:763)(541:652:763))
-        (INTERCONNECT SLICE_11/Q0 SLICE_87/A0 (1091:1257:1424)(1091:1257:1424))
-        (INTERCONNECT SLICE_11/Q0 SLICE_91/A1 (1091:1257:1424)(1091:1257:1424))
-        (INTERCONNECT SLICE_11/Q0 SLICE_94/D0 (543:607:671)(543:607:671))
+        (INTERCONNECT SLICE_11/Q0 SLICE_26/D1 (527:586:645)(527:586:645))
+        (INTERCONNECT SLICE_11/Q0 SLICE_26/A0 (748:874:1001)(748:874:1001))
+        (INTERCONNECT SLICE_11/Q0 ram2e_ufm\/SLICE_91/B1 (769:896:1023)(769:896:1023))
+        (INTERCONNECT SLICE_26/Q0 SLICE_11/B0 (788:917:1046)(788:917:1046))
+        (INTERCONNECT SLICE_26/Q0 SLICE_26/B1 (788:917:1046)(788:917:1046))
+        (INTERCONNECT SLICE_26/Q0 SLICE_26/B0 (788:917:1046)(788:917:1046))
+        (INTERCONNECT SLICE_26/Q0 ram2e_ufm\/CKE_7\/SLICE_61/A1 (745:872:999)(745:872:999))
+        (INTERCONNECT SLICE_26/Q0 ram2e_ufm\/SLICE_91/C1 (536:648:760)(536:648:760))
         (INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_12/D1 (2161:2313:2466)(2161:2313:2466))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_14/C1 (2199:2413:2628)(2199:2413:2628))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_21/A0 (2654:2908:3163)(2654:2908:3163))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_23/B0 (3383:3707:4031)(3383:3707:4031))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_27/A0 (3024:3310:3597)(3024:3310:3597))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_54/D1 (2631:2835:3039)(2631:2835:3039))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_92/D0 (2161:2313:2466)(2161:2313:2466))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_94/D1 (2625:2828:3032)(2625:2828:3032))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_95/C0 (2536:2775:3014)(2536:2775:3014))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_98/D1 (2188:2347:2507)(2188:2347:2507))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_99/D0 (3370:3638:3906)(3370:3638:3906))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_100/D1 (2488:2675:2863)(2488:2675:2863))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_118/D0 (3370:3638:3906)(3370:3638:3906))
-        (INTERCONNECT Din\[0\]_I/PADDI RD\[0\]_I/PADDO (4660:5052:5445)(4660:5052:5445))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_12/C1 (1737:1921:2106)(1737:1921:2106))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_24/C0 (2477:2725:2974)(2477:2725:2974))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_28/C0 (2477:2725:2974)(2477:2725:2974))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_36/A0 (3034:3324:3614)(3034:3324:3614))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_54/B1 (2414:2638:2862)(2414:2638:2862))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_94/B1 (2414:2638:2862)(2414:2638:2862))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_98/C1 (1747:1932:2118)(1747:1932:2118))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_99/C1 (1747:1932:2118)(1747:1932:2118))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_100/B1 (2450:2682:2914)(2450:2682:2914))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_118/C0 (1747:1932:2118)(1747:1932:2118))
-        (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_I/PADDO (2595:2804:3014)(2595:2804:3014))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_12/B1 (1831:2032:2234)(1831:2032:2234))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_24/C1 (2334:2586:2838)(2334:2586:2838))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_28/A1 (3224:3553:3882)(3224:3553:3882))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_36/C1 (1964:2184:2404)(1964:2184:2404))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_81/C1 (2077:2296:2516)(2077:2296:2516))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_93/C0 (2515:2781:3048)(2515:2781:3048))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_94/C1 (2077:2296:2516)(2077:2296:2516))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_98/B1 (2308:2540:2773)(2308:2540:2773))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_99/B1 (2308:2540:2773)(2308:2540:2773))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_100/C1 (2384:2649:2915)(2384:2649:2915))
-        (INTERCONNECT Din\[3\]_I/PADDI RD\[3\]_I/PADDO (3299:3575:3851)(3299:3575:3851))
-        (INTERCONNECT SLICE_12/F1 SLICE_12/D0 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_16/F1 SLICE_12/C0 (536:650:764)(536:650:764))
-        (INTERCONNECT SLICE_16/F1 SLICE_13/C0 (546:664:783)(546:664:783))
-        (INTERCONNECT SLICE_16/F1 SLICE_16/D0 (525:584:643)(525:584:643))
-        (INTERCONNECT SLICE_12/Q0 SLICE_12/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_12/Q0 SLICE_110/C0 (1234:1411:1588)(1234:1411:1588))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_11/CE (1002:1104:1207)(1002:1104:1207))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_26/CE (1002:1104:1207)(1002:1104:1207))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_26/CE (1002:1104:1207)(1002:1104:1207))
+        (INTERCONNECT SLICE_11/F1 ram2e_ufm\/CKE_7\/SLICE_61/D1 (523:573:623)(523:573:623))
+        (INTERCONNECT SLICE_13/F1 SLICE_12/D1 (520:573:626)(520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_62/F1 SLICE_12/C1 (534:645:756)(534:645:756))
+        (INTERCONNECT ram2e_ufm\/SLICE_62/F1 ram2e_ufm\/SLICE_62/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_84/F1 SLICE_12/B1 (513:611:710)(513:611:710))
+        (INTERCONNECT ram2e_ufm\/SLICE_84/F1 ram2e_ufm\/SLICE_84/B0 (767:894:1021)
+          (767:894:1021))
+        (INTERCONNECT ram2e_ufm\/SLICE_84/F1 ram2e_ufm\/SLICE_87/D0 (535:598:662)
+          (535:598:662))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_12/A1 (1081:1244:1407)(1081:1244:1407))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_12/B0 (770:897:1024)(770:897:1024))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_13/A1 (1081:1244:1407)(1081:1244:1407))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_13/D0 (528:587:646)(528:587:646))
+        (INTERCONNECT SLICE_12/Q1 SLICE_12/D0 (576:643:710)(576:643:710))
+        (INTERCONNECT SLICE_12/Q1 SLICE_13/C1 (587:709:831)(587:709:831))
+        (INTERCONNECT SLICE_12/Q1 SLICE_13/C0 (587:709:831)(587:709:831))
+        (INTERCONNECT SLICE_12/Q1 SLICE_19/C1 (552:669:786)(552:669:786))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_40/C1 (552:669:786)(552:669:786))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/C1 (542:663:784)
+          (542:663:784))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_62/A1 (786:918:1051)(786:918:1051))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_62/A0 (786:918:1051)(786:918:1051))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_65/A0 (1013:1179:1346)(1013:1179:1346))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_84/A0 (741:872:1004)(741:872:1004))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_87/B0 (818:953:1088)(818:953:1088))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_101/C0 (814:970:1126)(814:970:1126))
+        (INTERCONNECT ram2e_ufm\/SLICE_63/F0 SLICE_12/C0 (534:639:744)(534:639:744))
+        (INTERCONNECT SLICE_13/Q0 SLICE_12/A0 (770:902:1035)(770:902:1035))
+        (INTERCONNECT SLICE_13/Q0 SLICE_13/D1 (560:627:694)(560:627:694))
+        (INTERCONNECT SLICE_13/Q0 SLICE_13/A0 (485:583:681)(485:583:681))
+        (INTERCONNECT SLICE_13/Q0 SLICE_15/B1 (1043:1215:1388)(1043:1215:1388))
+        (INTERCONNECT SLICE_13/Q0 SLICE_19/B1 (787:921:1055)(787:921:1055))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_40/B1 (787:921:1055)(787:921:1055))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_62/B1 (802:937:1072)(802:937:1072))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_62/B0 (802:937:1072)(802:937:1072))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_63/D1 (535:605:675)(535:605:675))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_83/B1 (792:926:1061)(792:926:1061))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_84/D1 (535:605:675)(535:605:675))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_94/A0 (760:892:1024)(760:892:1024))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_100/C0 (561:682:804)(561:682:804))
+        (INTERCONNECT SLICE_12/F1 SLICE_12/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_13/C1 (2094:2309:2524)(2094:2309:2524))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_25/C1 (1718:1900:2083)(1718:1900:2083))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_29/C1 (2045:2262:2480)(2045:2262:2480))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_37/A1 (3021:3309:3598)(3021:3309:3598))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_93/C1 (2566:2814:3063)(2566:2814:3063))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_98/B0 (3499:3829:4159)(3499:3829:4159))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_99/B0 (3499:3829:4159)(3499:3829:4159))
-        (INTERCONNECT Din\[5\]_I/PADDI RD\[5\]_I/PADDO (3095:3329:3564)(3095:3329:3564))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_13/B1 (2775:3028:3281)(2775:3028:3281))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_26/C1 (1641:1812:1983)(1641:1812:1983))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_30/C1 (2005:2207:2410)(2005:2207:2410))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_38/B1 (3503:3819:4135)(3503:3819:4135))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_91/D0 (3708:3994:4280)(3708:3994:4280))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_93/A0 (3918:4269:4621)(3918:4269:4621))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_98/A0 (3221:3505:3790)(3221:3505:3790))
-        (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_I/PADDO (2669:2870:3072)(2669:2870:3072))
-        (INTERCONNECT SLICE_100/F1 SLICE_13/B0 (765:889:1013)(765:889:1013))
-        (INTERCONNECT SLICE_100/F1 SLICE_100/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_13/Q0 SLICE_13/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_13/Q0 SLICE_39/A0 (1013:1166:1319)(1013:1166:1319))
-        (INTERCONNECT SLICE_13/Q0 SLICE_53/A0 (1013:1166:1319)(1013:1166:1319))
-        (INTERCONNECT SLICE_13/Q0 SLICE_57/A1 (1013:1166:1319)(1013:1166:1319))
+        (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_12/LSR (933:1041:1149)(933:1041:1149))
+        (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_12/LSR (933:1041:1149)(933:1041:1149))
+        (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_13/LSR (933:1041:1149)(933:1041:1149))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_40/A1 (1089:1253:1418)(1089:1253:1418))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/B1 
+          (1153:1315:1477)(1153:1315:1477))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_63/A1 (1078:1240:1403)(1078:1240:1403))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_63/D0 (868:965:1062)(868:965:1062))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_65/B1 (2225:2487:2750)(2225:2487:2750))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_65/B0 (2225:2487:2750)(2225:2487:2750))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_77/A1 (1089:1253:1418)(1089:1253:1418))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_82/B1 (1850:2079:2308)(1850:2079:2308))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_83/A0 (745:872:999)(745:872:999))
+        (INTERCONNECT ram2e_ufm\/SLICE_87/F1 SLICE_13/B1 (769:899:1029)(769:899:1029))
+        (INTERCONNECT ram2e_ufm\/SLICE_87/F1 SLICE_13/B0 (515:616:718)(515:616:718))
+        (INTERCONNECT ram2e_ufm\/SLICE_87/F1 ram2e_ufm\/SLICE_62/D0 (527:589:651)
+          (527:589:651))
+        (INTERCONNECT ram2e_ufm\/SLICE_87/F1 ram2e_ufm\/SLICE_87/C0 (284:372:461)
+          (284:372:461))
         (INTERCONNECT SLICE_13/F0 SLICE_13/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_13/F1 SLICE_77/A1 (1051:1210:1370)(1051:1210:1370))
-        (INTERCONNECT SLICE_13/F1 SLICE_81/D0 (1677:1836:1995)(1677:1836:1995))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_14/D1 (2532:2727:2922)(2532:2727:2922))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_15/B1 (3569:3909:4249)(3569:3909:4249))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_16/B1 (4260:4666:5073)(4260:4666:5073))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_17/A1 (4063:4448:4833)(4063:4448:4833))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_25/D0 (4119:4473:4827)(4119:4473:4827))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_29/C0 (3864:4238:4613)(3864:4238:4613))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_37/C0 (2517:2759:3002)(2517:2759:3002))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_81/D1 (3271:3530:3789)(3271:3530:3789))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_93/A1 (3444:3772:4100)(3444:3772:4100))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_94/B0 (3513:3840:4167)(3513:3840:4167))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_100/A0 (4693:5144:5595)(4693:5144:5595))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_118/C1 (2543:2793:3043)(2543:2793:3043))
-        (INTERCONNECT Din\[4\]_I/PADDI RD\[4\]_I/PADDO (3334:3618:3903)(3334:3618:3903))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_14/B1 (1964:2160:2356)(1964:2160:2356))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_15/C1 (1716:1896:2076)(1716:1896:2076))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_16/A1 (2285:2507:2730)(2285:2507:2730))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_17/C1 (2102:2317:2532)(2102:2317:2532))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_23/C1 (2429:2679:2929)(2429:2679:2929))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_27/D1 (2091:2251:2411)(2091:2251:2411))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_35/B1 (2414:2636:2858)(2414:2636:2858))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_54/A1 (2736:2995:3254)(2736:2995:3254))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_54/A0 (2736:2995:3254)(2736:2995:3254))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_93/B1 (2420:2642:2865)(2420:2642:2865))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_94/A1 (2736:2995:3254)(2736:2995:3254))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_100/D0 (2075:2232:2389)(2075:2232:2389))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_118/B1 (1964:2160:2356)(1964:2160:2356))
-        (INTERCONNECT Din\[1\]_I/PADDI RD\[1\]_I/PADDO (2591:2799:3007)(2591:2799:3007))
-        (INTERCONNECT SLICE_99/F1 SLICE_14/A1 (733:854:976)(733:854:976))
-        (INTERCONNECT SLICE_99/F1 SLICE_99/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_14/F1 SLICE_14/D0 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_18/F1 SLICE_14/B0 (770:894:1018)(770:894:1018))
-        (INTERCONNECT SLICE_18/F1 SLICE_15/D1 (993:1098:1203)(993:1098:1203))
-        (INTERCONNECT SLICE_18/F1 SLICE_16/D1 (1357:1493:1630)(1357:1493:1630))
-        (INTERCONNECT SLICE_18/F1 SLICE_17/B1 (1599:1803:2008)(1599:1803:2008))
-        (INTERCONNECT SLICE_18/F1 SLICE_18/B0 (513:611:710)(513:611:710))
-        (INTERCONNECT SLICE_14/Q0 SLICE_14/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_14/Q0 SLICE_117/C1 (1437:1618:1800)(1437:1618:1800))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_14/D1 (2505:2694:2883)(2505:2694:2883))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_16/B1 (3122:3411:3701)(3122:3411:3701))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_28/B1 (3210:3494:3779)(3210:3494:3779))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_39/C1 (3432:3753:4074)
+          (3432:3753:4074))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_44/A1 (3505:3822:4139)
+          (3505:3822:4139))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_48/B1 (3938:4285:4633)
+          (3938:4285:4633))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/B1 
+          (2286:2514:2742)(2286:2514:2742))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/B0 
+          (2286:2514:2742)(2286:2514:2742))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_100/B1 (3122:3411:3701)
+          (3122:3411:3701))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_101/B1 (3122:3411:3701)
+          (3122:3411:3701))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_116/D1 (3421:3687:3953)
+          (3421:3687:3953))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_141/A0 (3042:3331:3621)
+          (3042:3331:3621))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_14/C1 (2207:2423:2640)(2207:2423:2640))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_16/C1 (2587:2836:3086)(2587:2836:3086))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_29/B1 (2278:2507:2737)(2278:2507:2737))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_39/B1 (2438:2667:2897)
+          (2438:2667:2897))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_45/B1 (2315:2541:2767)
+          (2315:2541:2767))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_49/B1 (2309:2534:2760)
+          (2309:2534:2760))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/D1 
+          (3381:3644:3908)(3381:3644:3908))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/C0 
+          (3065:3348:3632)(3065:3348:3632))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_100/C1 (2587:2836:3086)
+          (2587:2836:3086))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_101/C1 (2587:2836:3086)
+          (2587:2836:3086))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_116/C1 (2207:2423:2640)
+          (2207:2423:2640))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_147/B0 (2438:2667:2897)
+          (2438:2667:2897))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/F1 SLICE_14/A1 (751:880:1010)(751:880:1010))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_39/B0 (513:611:710)
+          (513:611:710))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_40/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_41/C0 (552:671:790)
+          (552:671:790))
+        (INTERCONNECT ram2e_ufm\/SLICE_142/F1 SLICE_14/D0 (523:573:623)(523:573:623))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_14/C0 (1743:1927:2111)(1743:1927:2111))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_15/A1 (3034:3332:3630)(3034:3332:3630))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_15/A0 (3034:3332:3630)(3034:3332:3630))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_16/A1 (2686:2945:3204)(2686:2945:3204))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_16/A0 (2686:2945:3204)(2686:2945:3204))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_17/D0 (1732:1861:1990)(1732:1861:1990))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_27/C1 (2191:2410:2629)(2191:2410:2629))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_39/A0 (4310:4724:5139)
+          (4310:4724:5139))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_41/D1 (3622:3937:4252)
+          (3622:3937:4252))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_43/C1 (2555:2805:3056)
+          (2555:2805:3056))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_47/C1 (1705:1883:2061)
+          (1705:1883:2061))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/M0 
+          (2441:2623:2805)(2441:2623:2805))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_87/C1 (1727:1909:2092)
+          (1727:1909:2092))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_100/D1 (3350:3630:3910)
+          (3350:3630:3910))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_116/B0 (4342:4759:5176)
+          (4342:4759:5176))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_143/C1 (2107:2322:2538)
+          (2107:2322:2538))
+        (INTERCONNECT SLICE_14/F1 SLICE_14/B0 (511:606:702)(511:606:702))
+        (INTERCONNECT SLICE_14/F1 SLICE_17/B1 (765:889:1013)(765:889:1013))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_14/A0 (2322:2538:2754)(2322:2538:2754))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_17/D1 (2439:2624:2810)(2439:2624:2810))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_28/B0 (1872:2056:2240)(1872:2056:2240))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_39/D0 (2112:2262:2413)
+          (2112:2262:2413))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_41/C1 (2123:2328:2534)
+          (2123:2328:2534))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_42/C1 (2016:2219:2423)
+          (2016:2219:2423))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_44/A0 (2579:2824:3070)
+          (2579:2824:3070))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_48/A0 (2943:3220:3497)
+          (2943:3220:3497))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_100/A1 (2692:2940:3188)
+          (2692:2940:3188))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_116/A0 (2322:2538:2754)
+          (2322:2538:2754))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_133/C1 (2971:3242:3514)
+          (2971:3242:3514))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_133/C0 (2971:3242:3514)
+          (2971:3242:3514))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_144/C1 (2814:3086:3358)
+          (2814:3086:3358))
         (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_98/F1 SLICE_15/A1 (1647:1842:2037)(1647:1842:2037))
-        (INTERCONNECT SLICE_98/F1 SLICE_16/C0 (2139:2390:2641)(2139:2390:2641))
-        (INTERCONNECT SLICE_98/F1 SLICE_17/D1 (985:1087:1190)(985:1087:1190))
-        (INTERCONNECT SLICE_98/F1 SLICE_98/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_15/F1 SLICE_15/B0 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_15/Q0 SLICE_15/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_15/Q0 SLICE_86/D0 (523:578:633)(523:578:633))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_14/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_15/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_16/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_17/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_27/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_27/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_28/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_28/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_29/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_29/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_30/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_30/CE (2023:2253:2484)(2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_39/CE (2023:2253:2484)
+          (2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_40/CE (2023:2253:2484)
+          (2023:2253:2484))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_41/CE (2023:2253:2484)
+          (2023:2253:2484))
+        (INTERCONNECT SLICE_14/Q0 ram2e_ufm\/SLICE_147/B1 (762:883:1004)(762:883:1004))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_15/D1 (2882:3133:3384)(2882:3133:3384))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_15/B0 (2786:3068:3350)(2786:3068:3350))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_16/D1 (2882:3133:3384)(2882:3133:3384))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_16/B0 (2786:3068:3350)(2786:3068:3350))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_17/B0 (2776:3057:3338)(2776:3057:3338))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_30/A1 (2655:2908:3162)(2655:2908:3162))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_41/A0 (3502:3821:4141)
+          (3502:3821:4141))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_46/A1 (3019:3304:3589)
+          (3019:3304:3589))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_50/A1 (2644:2896:3149)
+          (2644:2896:3149))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/D0 
+          (3016:3263:3511)(3016:3263:3511))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_94/B1 (3170:3460:3751)
+          (3170:3460:3751))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_100/D0 (2928:3150:3373)
+          (2928:3150:3373))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_142/C1 (2915:3215:3515)
+          (2915:3215:3515))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_143/B0 (3510:3854:4199)
+          (3510:3854:4199))
+        (INTERCONNECT SLICE_17/F1 SLICE_15/D0 (539:600:661)(539:600:661))
+        (INTERCONNECT SLICE_17/F1 SLICE_16/D0 (539:600:661)(539:600:661))
+        (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (280:362:445)(280:362:445))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_15/C0 (2089:2307:2526)(2089:2307:2526))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_16/C0 (2089:2307:2526)(2089:2307:2526))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_17/A0 (2663:2924:3186)(2663:2924:3186))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_29/C0 (2069:2285:2502)(2069:2285:2502))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_41/A1 (2663:2924:3186)
+          (2663:2924:3186))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_45/A0 (2595:2857:3119)
+          (2595:2857:3119))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_49/B0 (1821:2020:2220)
+          (1821:2020:2220))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_84/A1 (3104:3404:3704)
+          (3104:3404:3704))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_94/C1 (2089:2307:2526)
+          (2089:2307:2526))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_100/A0 (2615:2879:3143)
+          (2615:2879:3143))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_133/A1 (2766:3029:3292)
+          (2766:3029:3292))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_133/B0 (3136:3438:3741)
+          (3136:3438:3741))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_142/D1 (2823:3051:3279)
+          (2823:3051:3279))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_142/D0 (2823:3051:3279)
+          (2823:3051:3279))
         (INTERCONNECT SLICE_15/F0 SLICE_15/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_16/Q0 SLICE_16/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_16/Q0 SLICE_114/D0 (533:592:652)(533:592:652))
+        (INTERCONNECT SLICE_15/Q0 ram2e_ufm\/SLICE_79/D1 (1233:1354:1476)(1233:1354:1476))
+        (INTERCONNECT SLICE_15/F1 ram2e_ufm\/SLICE_101/D0 (520:573:626)(520:573:626))
         (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_17/Q0 SLICE_17/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_17/Q0 SLICE_117/D1 (526:578:630)(526:578:630))
+        (INTERCONNECT SLICE_16/Q0 ram2e_ufm\/SLICE_85/A0 (1443:1630:1817)(1443:1630:1817))
+        (INTERCONNECT SLICE_16/F1 ram2e_ufm\/SLICE_84/B1 (768:889:1010)(768:889:1010))
+        (INTERCONNECT SLICE_16/F1 ram2e_ufm\/SLICE_101/B0 (511:606:702)(511:606:702))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_17/C1 (2376:2622:2868)(2376:2622:2868))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_27/C0 (2355:2599:2843)(2355:2599:2843))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_39/D1 (1985:2143:2301)
+          (1985:2143:2301))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_41/B1 (2934:3228:3522)
+          (2934:3228:3522))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_42/A1 (2929:3216:3503)
+          (2929:3216:3503))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_42/A0 (2929:3216:3503)
+          (2929:3216:3503))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_43/A0 (2929:3216:3503)
+          (2929:3216:3503))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_65/C1 (2355:2599:2843)
+          (2355:2599:2843))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_86/D1 (1957:2111:2265)
+          (1957:2111:2265))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_94/B0 (2330:2553:2776)
+          (2330:2553:2776))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_116/D0 (1985:2143:2301)
+          (1985:2143:2301))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_133/D1 (1980:2137:2295)
+          (1980:2137:2295))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_141/B1 (2607:2866:3125)
+          (2607:2866:3125))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_142/A1 (2575:2831:3088)
+          (2575:2831:3088))
         (INTERCONNECT SLICE_17/F0 SLICE_17/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77/F1 SLICE_18/C1 (537:645:753)(537:645:753))
-        (INTERCONNECT SLICE_77/F1 SLICE_77/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_100/F0 SLICE_18/D0 (576:643:710)(576:643:710))
+        (INTERCONNECT SLICE_17/Q0 ram2e_ufm\/SLICE_147/D1 (520:573:626)(520:573:626))
+        (INTERCONNECT SLICE_18/Q0 SLICE_18/B1 (776:901:1026)(776:901:1026))
         (INTERCONNECT SLICE_18/Q0 SLICE_18/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_18/Q0 SLICE_117/B1 (1857:2088:2319)(1857:2088:2319))
+        (INTERCONNECT SLICE_18/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/A0 
+          (744:866:989)(744:866:989))
+        (INTERCONNECT SLICE_18/Q1 SLICE_18/A1 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_18/Q1 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/B0 
+          (765:888:1011)(765:888:1011))
+        (INTERCONNECT SLICE_18/F1 SLICE_18/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19/Q0 SLICE_19/D1 (534:591:648)(534:591:648))
-        (INTERCONNECT SLICE_19/Q0 SLICE_19/D0 (534:591:648)(534:591:648))
-        (INTERCONNECT SLICE_19/Q0 SLICE_82/D1 (533:592:652)(533:592:652))
-        (INTERCONNECT SLICE_19/Q1 SLICE_19/B1 (765:888:1011)(765:888:1011))
-        (INTERCONNECT SLICE_19/Q1 SLICE_82/A1 (1002:1154:1306)(1002:1154:1306))
-        (INTERCONNECT SLICE_19/F1 SLICE_19/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_34/Q0 SLICE_20/D1 (1481:1626:1772)(1481:1626:1772))
-        (INTERCONNECT SLICE_34/Q0 SLICE_20/D0 (1481:1626:1772)(1481:1626:1772))
-        (INTERCONNECT SLICE_34/Q0 SLICE_34/A1 (762:894:1027)(762:894:1027))
-        (INTERCONNECT SLICE_34/Q0 SLICE_34/A0 (487:587:687)(487:587:687))
-        (INTERCONNECT SLICE_34/Q0 SLICE_35/A1 (1669:1873:2078)(1669:1873:2078))
-        (INTERCONNECT SLICE_34/Q0 SLICE_36/D1 (1864:2038:2213)(1864:2038:2213))
-        (INTERCONNECT SLICE_34/Q0 SLICE_36/D0 (1864:2038:2213)(1864:2038:2213))
-        (INTERCONNECT SLICE_34/Q0 SLICE_37/D1 (2239:2446:2653)(2239:2446:2653))
-        (INTERCONNECT SLICE_34/Q0 SLICE_37/D0 (2239:2446:2653)(2239:2446:2653))
-        (INTERCONNECT SLICE_34/Q0 SLICE_38/D1 (1844:2016:2189)(1844:2016:2189))
-        (INTERCONNECT SLICE_34/Q0 SLICE_38/D0 (1844:2016:2189)(1844:2016:2189))
-        (INTERCONNECT SLICE_34/Q0 SLICE_40/B0 (2106:2348:2591)(2106:2348:2591))
-        (INTERCONNECT SLICE_34/Q0 SLICE_41/C0 (1875:2104:2334)(1875:2104:2334))
-        (INTERCONNECT SLICE_34/Q0 SLICE_42/B1 (2106:2348:2591)(2106:2348:2591))
-        (INTERCONNECT SLICE_34/Q0 SLICE_44/LSR (2253:2463:2674)(2253:2463:2674))
-        (INTERCONNECT SLICE_34/Q0 SLICE_47/D0 (1398:1544:1690)(1398:1544:1690))
-        (INTERCONNECT SLICE_34/Q0 SLICE_48/D1 (1762:1939:2117)(1762:1939:2117))
-        (INTERCONNECT SLICE_34/Q0 SLICE_51/B1 (794:930:1067)(794:930:1067))
-        (INTERCONNECT SLICE_34/Q0 SLICE_53/D1 (2234:2440:2647)(2234:2440:2647))
-        (INTERCONNECT SLICE_34/Q0 SLICE_53/D0 (2234:2440:2647)(2234:2440:2647))
-        (INTERCONNECT SLICE_34/Q0 SLICE_57/D0 (2234:2440:2647)(2234:2440:2647))
-        (INTERCONNECT SLICE_34/Q0 SLICE_59/A0 (1608:1819:2031)(1608:1819:2031))
-        (INTERCONNECT SLICE_34/Q0 SLICE_66/C1 (2225:2484:2744)(2225:2484:2744))
-        (INTERCONNECT SLICE_34/Q0 SLICE_67/B0 (778:912:1046)(778:912:1046))
-        (INTERCONNECT SLICE_34/Q0 SLICE_68/A1 (2074:2314:2554)(2074:2314:2554))
-        (INTERCONNECT SLICE_34/Q0 SLICE_69/C0 (1409:1610:1811)(1409:1610:1811))
-        (INTERCONNECT SLICE_34/Q0 SLICE_71/A0 (762:896:1030)(762:896:1030))
-        (INTERCONNECT SLICE_34/Q0 SLICE_72/C0 (824:980:1137)(824:980:1137))
-        (INTERCONNECT SLICE_34/Q0 SLICE_79/D1 (1003:1114:1226)(1003:1114:1226))
-        (INTERCONNECT SLICE_34/Q0 SLICE_80/C1 (1014:1180:1347)(1014:1180:1347))
-        (INTERCONNECT SLICE_34/Q0 SLICE_83/A1 (762:896:1030)(762:896:1030))
-        (INTERCONNECT SLICE_34/Q0 SLICE_84/D0 (1459:1598:1737)(1459:1598:1737))
-        (INTERCONNECT SLICE_34/Q0 SLICE_92/C0 (2219:2478:2737)(2219:2478:2737))
-        (INTERCONNECT SLICE_34/Q0 SLICE_95/B0 (2456:2728:3001)(2456:2728:3001))
-        (INTERCONNECT SLICE_34/Q0 SLICE_96/B1 (1640:1854:2068)(1640:1854:2068))
-        (INTERCONNECT SLICE_34/Q0 SLICE_101/C1 (1409:1610:1811)(1409:1610:1811))
-        (INTERCONNECT SLICE_34/Q0 SLICE_101/C0 (1409:1610:1811)(1409:1610:1811))
-        (INTERCONNECT SLICE_34/Q0 SLICE_102/A1 (762:894:1027)(762:894:1027))
-        (INTERCONNECT SLICE_34/Q0 SLICE_102/A0 (762:894:1027)(762:894:1027))
-        (INTERCONNECT SLICE_34/Q0 SLICE_103/B1 (1055:1224:1394)(1055:1224:1394))
-        (INTERCONNECT SLICE_34/Q0 SLICE_103/B0 (1055:1224:1394)(1055:1224:1394))
-        (INTERCONNECT SLICE_34/Q0 SLICE_107/C1 (547:668:789)(547:668:789))
-        (INTERCONNECT SLICE_34/Q0 SLICE_107/C0 (547:668:789)(547:668:789))
-        (INTERCONNECT SLICE_34/Q0 SLICE_109/A1 (2074:2314:2554)(2074:2314:2554))
-        (INTERCONNECT SLICE_34/Q0 SLICE_109/A0 (2074:2314:2554)(2074:2314:2554))
-        (INTERCONNECT SLICE_34/Q0 SLICE_110/D1 (2234:2440:2647)(2234:2440:2647))
-        (INTERCONNECT SLICE_34/Q0 SLICE_110/D0 (2234:2440:2647)(2234:2440:2647))
-        (INTERCONNECT SLICE_34/Q0 SLICE_114/C1 (2614:2907:3201)(2614:2907:3201))
-        (INTERCONNECT SLICE_33/Q1 SLICE_20/C1 (1484:1679:1874)(1484:1679:1874))
-        (INTERCONNECT SLICE_33/Q1 SLICE_20/C0 (1484:1679:1874)(1484:1679:1874))
-        (INTERCONNECT SLICE_33/Q1 SLICE_33/D0 (568:635:702)(568:635:702))
-        (INTERCONNECT SLICE_33/Q1 SLICE_47/A0 (1943:2188:2434)(1943:2188:2434))
-        (INTERCONNECT SLICE_33/Q1 SLICE_48/A1 (1955:2191:2428)(1955:2191:2428))
-        (INTERCONNECT SLICE_33/Q1 SLICE_57/C0 (2114:2371:2628)(2114:2371:2628))
-        (INTERCONNECT SLICE_33/Q1 SLICE_59/B0 (1975:2223:2471)(1975:2223:2471))
-        (INTERCONNECT SLICE_33/Q1 SLICE_67/C1 (541:652:763)(541:652:763))
-        (INTERCONNECT SLICE_33/Q1 SLICE_69/D0 (1733:1913:2093)(1733:1913:2093))
-        (INTERCONNECT SLICE_33/Q1 SLICE_71/D0 (2072:2278:2484)(2072:2278:2484))
-        (INTERCONNECT SLICE_33/Q1 SLICE_79/A1 (1205:1376:1548)(1205:1376:1548))
-        (INTERCONNECT SLICE_33/Q1 SLICE_80/D1 (995:1101:1207)(995:1101:1207))
-        (INTERCONNECT SLICE_33/Q1 SLICE_96/C1 (1744:1979:2214)(1744:1979:2214))
-        (INTERCONNECT SLICE_33/Q1 SLICE_101/D1 (1723:1901:2079)(1723:1901:2079))
-        (INTERCONNECT SLICE_33/Q1 SLICE_101/D0 (1723:1901:2079)(1723:1901:2079))
-        (INTERCONNECT SLICE_33/Q1 SLICE_102/D1 (568:635:702)(568:635:702))
-        (INTERCONNECT SLICE_33/Q1 SLICE_102/D0 (568:635:702)(568:635:702))
-        (INTERCONNECT SLICE_33/Q1 SLICE_106/D1 (568:635:702)(568:635:702))
-        (INTERCONNECT SLICE_33/Q1 SLICE_106/D0 (568:635:702)(568:635:702))
-        (INTERCONNECT SLICE_33/Q1 SLICE_107/A0 (747:876:1005)(747:876:1005))
-        (INTERCONNECT SLICE_33/Q1 SLICE_112/B1 (1965:2211:2457)(1965:2211:2457))
-        (INTERCONNECT SLICE_33/Q0 SLICE_20/B1 (2038:2281:2524)(2038:2281:2524))
-        (INTERCONNECT SLICE_33/Q0 SLICE_20/B0 (2038:2281:2524)(2038:2281:2524))
-        (INTERCONNECT SLICE_33/Q0 SLICE_21/A1 (762:896:1030)(762:896:1030))
-        (INTERCONNECT SLICE_33/Q0 SLICE_22/C1 (927:1082:1237)(927:1082:1237))
-        (INTERCONNECT SLICE_33/Q0 SLICE_22/C0 (927:1082:1237)(927:1082:1237))
-        (INTERCONNECT SLICE_33/Q0 SLICE_33/A0 (487:587:687)(487:587:687))
-        (INTERCONNECT SLICE_33/Q0 SLICE_47/B1 (2546:2829:3112)(2546:2829:3112))
-        (INTERCONNECT SLICE_33/Q0 SLICE_47/B0 (2546:2829:3112)(2546:2829:3112))
-        (INTERCONNECT SLICE_33/Q0 SLICE_48/C1 (1344:1546:1749)(1344:1546:1749))
-        (INTERCONNECT SLICE_33/Q0 SLICE_48/B0 (1237:1415:1594)(1237:1415:1594))
-        (INTERCONNECT SLICE_33/Q0 SLICE_57/B0 (1485:1688:1891)(1485:1688:1891))
-        (INTERCONNECT SLICE_33/Q0 SLICE_59/C0 (2315:2585:2855)(2315:2585:2855))
-        (INTERCONNECT SLICE_33/Q0 SLICE_67/A1 (762:896:1030)(762:896:1030))
-        (INTERCONNECT SLICE_33/Q0 SLICE_69/A0 (2514:2794:3075)(2514:2794:3075))
-        (INTERCONNECT SLICE_33/Q0 SLICE_71/B0 (1575:1790:2006)(1575:1790:2006))
-        (INTERCONNECT SLICE_33/Q0 SLICE_80/B0 (1709:1921:2133)(1709:1921:2133))
-        (INTERCONNECT SLICE_33/Q0 SLICE_83/D1 (541:608:676)(541:608:676))
-        (INTERCONNECT SLICE_33/Q0 SLICE_96/D0 (2304:2519:2734)(2304:2519:2734))
-        (INTERCONNECT SLICE_33/Q0 SLICE_101/A1 (1210:1386:1563)(1210:1386:1563))
-        (INTERCONNECT SLICE_33/Q0 SLICE_101/A0 (1210:1386:1563)(1210:1386:1563))
-        (INTERCONNECT SLICE_33/Q0 SLICE_102/C1 (563:685:807)(563:685:807))
-        (INTERCONNECT SLICE_33/Q0 SLICE_106/C1 (563:685:807)(563:685:807))
-        (INTERCONNECT SLICE_33/Q0 SLICE_106/C0 (563:685:807)(563:685:807))
-        (INTERCONNECT SLICE_33/Q0 SLICE_111/A1 (1870:2100:2330)(1870:2100:2330))
-        (INTERCONNECT SLICE_33/Q0 SLICE_111/A0 (1870:2100:2330)(1870:2100:2330))
-        (INTERCONNECT SLICE_33/Q0 SLICE_112/A1 (1210:1386:1563)(1210:1386:1563))
-        (INTERCONNECT SLICE_33/Q0 SLICE_112/A0 (1210:1386:1563)(1210:1386:1563))
-        (INTERCONNECT SLICE_33/Q0 SLICE_113/A1 (1870:2100:2330)(1870:2100:2330))
-        (INTERCONNECT SLICE_33/Q0 SLICE_113/A0 (1870:2100:2330)(1870:2100:2330))
-        (INTERCONNECT SLICE_33/Q0 SLICE_115/D0 (2300:2503:2707)(2300:2503:2707))
-        (INTERCONNECT SLICE_34/Q1 SLICE_20/A1 (1666:1867:2069)(1666:1867:2069))
-        (INTERCONNECT SLICE_34/Q1 SLICE_20/A0 (1666:1867:2069)(1666:1867:2069))
-        (INTERCONNECT SLICE_34/Q1 SLICE_21/D1 (580:649:719)(580:649:719))
-        (INTERCONNECT SLICE_34/Q1 SLICE_21/D0 (580:649:719)(580:649:719))
-        (INTERCONNECT SLICE_34/Q1 SLICE_22/A1 (1023:1200:1377)(1023:1200:1377))
-        (INTERCONNECT SLICE_34/Q1 SLICE_22/A0 (1023:1200:1377)(1023:1200:1377))
-        (INTERCONNECT SLICE_34/Q1 SLICE_27/B1 (1207:1378:1549)(1207:1378:1549))
-        (INTERCONNECT SLICE_34/Q1 SLICE_27/B0 (1207:1378:1549)(1207:1378:1549))
-        (INTERCONNECT SLICE_34/Q1 SLICE_28/D1 (580:649:719)(580:649:719))
-        (INTERCONNECT SLICE_34/Q1 SLICE_28/D0 (580:649:719)(580:649:719))
-        (INTERCONNECT SLICE_34/Q1 SLICE_29/B1 (1207:1378:1549)(1207:1378:1549))
-        (INTERCONNECT SLICE_34/Q1 SLICE_29/B0 (1207:1378:1549)(1207:1378:1549))
-        (INTERCONNECT SLICE_34/Q1 SLICE_30/D1 (580:649:719)(580:649:719))
-        (INTERCONNECT SLICE_34/Q1 SLICE_30/D0 (580:649:719)(580:649:719))
-        (INTERCONNECT SLICE_34/Q1 SLICE_34/B1 (802:937:1072)(802:937:1072))
-        (INTERCONNECT SLICE_34/Q1 SLICE_34/B0 (802:937:1072)(802:937:1072))
-        (INTERCONNECT SLICE_34/Q1 SLICE_39/C0 (966:1123:1280)(966:1123:1280))
-        (INTERCONNECT SLICE_34/Q1 SLICE_44/D0 (955:1057:1159)(955:1057:1159))
-        (INTERCONNECT SLICE_34/Q1 SLICE_47/C0 (849:1018:1187)(849:1018:1187))
-        (INTERCONNECT SLICE_34/Q1 SLICE_48/B1 (1230:1406:1582)(1230:1406:1582))
-        (INTERCONNECT SLICE_34/Q1 SLICE_51/D1 (888:991:1095)(888:991:1095))
-        (INTERCONNECT SLICE_34/Q1 SLICE_51/B0 (792:926:1061)(792:926:1061))
-        (INTERCONNECT SLICE_34/Q1 SLICE_53/B1 (1577:1780:1983)(1577:1780:1983))
-        (INTERCONNECT SLICE_34/Q1 SLICE_57/A0 (1165:1332:1500)(1165:1332:1500))
-        (INTERCONNECT SLICE_34/Q1 SLICE_59/D0 (838:952:1066)(838:952:1066))
-        (INTERCONNECT SLICE_34/Q1 SLICE_67/D0 (580:649:719)(580:649:719))
-        (INTERCONNECT SLICE_34/Q1 SLICE_69/B0 (1080:1262:1444)(1080:1262:1444))
-        (INTERCONNECT SLICE_34/Q1 SLICE_71/C0 (888:1044:1201)(888:1044:1201))
-        (INTERCONNECT SLICE_34/Q1 SLICE_72/A0 (1203:1377:1551)(1203:1377:1551))
-        (INTERCONNECT SLICE_34/Q1 SLICE_79/C1 (1477:1674:1871)(1477:1674:1871))
-        (INTERCONNECT SLICE_34/Q1 SLICE_80/B1 (1708:1918:2128)(1708:1918:2128))
-        (INTERCONNECT SLICE_34/Q1 SLICE_83/C1 (899:1057:1216)(899:1057:1216))
-        (INTERCONNECT SLICE_34/Q1 SLICE_96/A1 (1048:1227:1407)(1048:1227:1407))
-        (INTERCONNECT SLICE_34/Q1 SLICE_101/B1 (1080:1262:1444)(1080:1262:1444))
-        (INTERCONNECT SLICE_34/Q1 SLICE_101/B0 (1080:1262:1444)(1080:1262:1444))
-        (INTERCONNECT SLICE_34/Q1 SLICE_102/B1 (802:937:1072)(802:937:1072))
-        (INTERCONNECT SLICE_34/Q1 SLICE_102/B0 (802:937:1072)(802:937:1072))
-        (INTERCONNECT SLICE_34/Q1 SLICE_103/A1 (1203:1377:1551)(1203:1377:1551))
-        (INTERCONNECT SLICE_34/Q1 SLICE_103/A0 (1203:1377:1551)(1203:1377:1551))
-        (INTERCONNECT SLICE_34/Q1 SLICE_107/B1 (778:922:1066)(778:922:1066))
-        (INTERCONNECT SLICE_34/Q1 SLICE_107/B0 (778:922:1066)(778:922:1066))
-        (INTERCONNECT SLICE_34/Q1 SLICE_110/A1 (1545:1745:1946)(1545:1745:1946))
-        (INTERCONNECT SLICE_34/Q1 SLICE_111/D1 (1608:1796:1985)(1608:1796:1985))
-        (INTERCONNECT SLICE_34/Q1 SLICE_111/D0 (1608:1796:1985)(1608:1796:1985))
-        (INTERCONNECT SLICE_34/Q1 SLICE_112/D1 (838:952:1066)(838:952:1066))
-        (INTERCONNECT SLICE_34/Q1 SLICE_112/D0 (838:952:1066)(838:952:1066))
-        (INTERCONNECT SLICE_34/Q1 SLICE_113/D1 (1608:1796:1985)(1608:1796:1985))
-        (INTERCONNECT SLICE_34/Q1 SLICE_113/D0 (1608:1796:1985)(1608:1796:1985))
+        (INTERCONNECT SLICE_20/Q1 SLICE_19/B0 (1224:1391:1559)(1224:1391:1559))
+        (INTERCONNECT SLICE_20/Q1 RAout\[1\]_MGIOL/OPOS (2318:2516:2715)(2318:2516:2715))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 SLICE_19/A0 (1562:1763:1965)(1562:1763:1965))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 SLICE_31/A1 (2409:2676:2944)(2409:2676:2944))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_95/A0 (756:884:1013)
+          (756:884:1013))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_96/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_132/B1 (2441:2711:2981)
+          (2441:2711:2981))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_132/B0 (2441:2711:2981)
+          (2441:2711:2981))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_140/A1 (756:884:1013)
+          (756:884:1013))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_140/A0 (756:884:1013)
+          (756:884:1013))
+        (INTERCONNECT SLICE_34/Q1 SLICE_19/M0 (1263:1395:1527)(1263:1395:1527))
+        (INTERCONNECT SLICE_34/Q1 SLICE_34/A1 (485:583:681)(485:583:681))
+        (INTERCONNECT SLICE_34/Q1 SLICE_34/D0 (550:615:680)(550:615:680))
+        (INTERCONNECT SLICE_34/Q1 SLICE_35/B0 (822:959:1097)(822:959:1097))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_42/D0 (1344:1480:1616)(1344:1480:1616))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_43/D1 (1344:1480:1616)(1344:1480:1616))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_43/D0 (1344:1480:1616)(1344:1480:1616))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_44/D1 (1724:1893:2062)(1724:1893:2062))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_44/D0 (1724:1893:2062)(1724:1893:2062))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_45/D1 (1344:1480:1616)(1344:1480:1616))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_45/D0 (1344:1480:1616)(1344:1480:1616))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_46/D1 (1344:1480:1616)(1344:1480:1616))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_46/D0 (1344:1480:1616)(1344:1480:1616))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_51/D0 (2099:2300:2502)(2099:2300:2502))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_56/D1 (2479:2713:2948)(2479:2713:2948))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_69/C0 (976:1134:1292)(976:1134:1292))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_71/B0 (1571:1773:1976)(1571:1773:1976))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_72/B0 (822:959:1097)(822:959:1097))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_74/B0 (822:959:1097)(822:959:1097))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_77/D0 (1335:1475:1615)(1335:1475:1615))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_78/B0 (2721:3023:3326)(2721:3023:3326))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_79/A0 (1934:2168:2403)(1934:2168:2403))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_95/C1 (976:1134:1292)(976:1134:1292))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_96/A1 (1175:1343:1512)(1175:1343:1512))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_102/B1 (1375:1577:1779)(1375:1577:1779))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_105/A1 (1175:1343:1512)(1175:1343:1512))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_107/D1 (2099:2300:2502)(2099:2300:2502))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_113/B1 (776:908:1040)(776:908:1040))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_115/A0 (1728:1963:2198)(1728:1963:2198))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_117/B1 (1208:1384:1560)(1208:1384:1560))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_117/B0 (1208:1384:1560)(1208:1384:1560))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_118/A1 (1514:1724:1935)(1514:1724:1935))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_118/A0 (1514:1724:1935)(1514:1724:1935))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_119/B1 (822:959:1097)(822:959:1097))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_119/B0 (822:959:1097)(822:959:1097))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_120/B1 (1760:1997:2235)(1760:1997:2235))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_120/B0 (1760:1997:2235)(1760:1997:2235))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_121/C1 (2490:2779:3069)(2490:2779:3069))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_121/C0 (2490:2779:3069)(2490:2779:3069))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_127/B1 (822:959:1097)(822:959:1097))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_127/B0 (822:959:1097)(822:959:1097))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_135/C1 (561:681:801)(561:681:801))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_135/C0 (561:681:801)(561:681:801))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_136/B1 (1213:1389:1566)(1213:1389:1566))
+        (INTERCONNECT SLICE_34/Q1 SLICE_138/B1 (1213:1389:1566)(1213:1389:1566))
+        (INTERCONNECT SLICE_138/F0 SLICE_19/LSR (539:596:653)(539:596:653))
+        (INTERCONNECT SLICE_19/F0 SLICE_20/B1 (1219:1385:1551)(1219:1385:1551))
+        (INTERCONNECT SLICE_19/Q0 ram2e_ufm\/SLICE_136/D0 (520:573:626)(520:573:626))
+        (INTERCONNECT SLICE_19/F1 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/C1 
+          (547:660:773)(547:660:773))
+        (INTERCONNECT SLICE_19/F1 ram2e_ufm\/SLICE_65/D1 (1264:1385:1506)(1264:1385:1506))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_20/D1 (535:618:701)(535:618:701))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_21/B0 (777:928:1079)(777:928:1079))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_22/D1 (273:306:340)(273:306:340))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_31/B1 (1043:1228:1414)(1043:1228:1414))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_95/C0 (284:372:461)
+          (284:372:461))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_96/D0 (273:306:340)
+          (273:306:340))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_132/D1 (535:618:701)
+          (535:618:701))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_132/D0 (535:618:701)
+          (535:618:701))
+        (INTERCONNECT Ain\[1\]_I/PADDI SLICE_20/C1 (2395:2638:2881)(2395:2638:2881))
+        (INTERCONNECT ram2e_ufm\/SLICE_107/F0 SLICE_20/A1 (740:863:986)(740:863:986))
+        (INTERCONNECT ram2e_ufm\/SLICE_132/F1 SLICE_20/D0 (520:573:626)(520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_20/C0 (539:668:797)(539:668:797))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_21/A1 (738:877:1017)(738:877:1017))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_22/A0 (1004:1178:1352)(1004:1178:1352))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_23/A1 (738:877:1017)(738:877:1017))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_23/A0 (738:877:1017)(738:877:1017))
+        (INTERCONNECT ram2e_ufm\/SLICE_124/F0 SLICE_20/A0 (1067:1225:1383)(1067:1225:1383))
+        (INTERCONNECT SLICE_20/F1 SLICE_20/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20/Q0 SLICE_31/A1 (740:863:986)(740:863:986))
-        (INTERCONNECT Ain\[1\]_I/PADDI SLICE_21/C1 (1949:2165:2382)(1949:2165:2382))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_21/C0 (1167:1335:1503)
-          (1167:1335:1503))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_27/C0 (1531:1730:1930)
-          (1531:1730:1930))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_20/CE (827:920:1013)(827:920:1013))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_20/CE (827:920:1013)(827:920:1013))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_21/CE (827:920:1013)(827:920:1013))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_21/CE (827:920:1013)(827:920:1013))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_22/CE (1197:1322:1447)(1197:1322:1447))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_22/CE (1197:1322:1447)(1197:1322:1447))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_23/CE (827:920:1013)(827:920:1013))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_23/CE (827:920:1013)(827:920:1013))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_24/CE (542:602:662)(542:602:662))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_24/CE (542:602:662)(542:602:662))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_25/CE (1561:1717:1874)(1561:1717:1874))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_25/CE (1561:1717:1874)(1561:1717:1874))
+        (INTERCONNECT SLICE_20/Q0 SLICE_31/D0 (539:599:659)(539:599:659))
+        (INTERCONNECT SLICE_20/Q0 ram2e_ufm\/SLICE_132/A1 (733:853:974)(733:853:974))
+        (INTERCONNECT SLICE_20/Q0 RAout\[0\]_MGIOL/OPOS (2163:2372:2582)(2163:2372:2582))
+        (INTERCONNECT SLICE_31/F1 SLICE_21/D1 (523:573:623)(523:573:623))
+        (INTERCONNECT ram2e_ufm\/SLICE_140/F1 SLICE_21/D0 (857:949:1042)(857:949:1042))
+        (INTERCONNECT ram2e_ufm\/SLICE_134/F0 SLICE_21/C0 (534:639:744)(534:639:744))
+        (INTERCONNECT Ain\[2\]_I/PADDI SLICE_21/A0 (2456:2723:2990)(2456:2723:2990))
+        (INTERCONNECT SLICE_21/F1 SLICE_21/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_86/F0 SLICE_21/CE (876:972:1069)(876:972:1069))
-        (INTERCONNECT SLICE_21/Q0 SLICE_117/A1 (733:853:974)(733:853:974))
-        (INTERCONNECT SLICE_21/Q0 SLICE_117/D0 (523:578:633)(523:578:633))
-        (INTERCONNECT SLICE_21/F1 RA\[1\]_MGIOL/OPOS (2218:2418:2619)(2218:2418:2619))
-        (INTERCONNECT Ain\[3\]_I/PADDI SLICE_22/B1 (2262:2486:2711)(2262:2486:2711))
-        (INTERCONNECT Ain\[0\]_I/PADDI SLICE_22/B0 (2262:2486:2711)(2262:2486:2711))
+        (INTERCONNECT SLICE_21/Q0 ram2e_ufm\/SLICE_140/B1 (767:891:1015)(767:891:1015))
+        (INTERCONNECT SLICE_21/Q0 RAout\[2\]_MGIOL/OPOS (1785:1948:2112)(1785:1948:2112))
+        (INTERCONNECT SLICE_21/Q1 SLICE_31/C1 (877:1027:1177)(877:1027:1177))
+        (INTERCONNECT SLICE_21/Q1 SLICE_31/A0 (749:874:1000)(749:874:1000))
+        (INTERCONNECT SLICE_21/Q1 RAout\[3\]_MGIOL/OPOS (1530:1666:1802)(1530:1666:1802))
+        (INTERCONNECT Ain\[5\]_I/PADDI SLICE_22/C1 (1961:2162:2364)(1961:2162:2364))
+        (INTERCONNECT ram2e_ufm\/SLICE_124/F1 SLICE_22/B1 (1031:1183:1336)(1031:1183:1336))
+        (INTERCONNECT ram2e_ufm\/SLICE_140/F0 SLICE_22/A1 (730:848:967)(730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F0 SLICE_22/D0 (266:290:315)(266:290:315))
         (INTERCONNECT SLICE_22/F1 SLICE_22/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_101/F0 SLICE_22/CE (1141:1265:1389)(1141:1265:1389))
-        (INTERCONNECT SLICE_101/F0 SLICE_22/CE (1141:1265:1389)(1141:1265:1389))
-        (INTERCONNECT SLICE_101/F0 RA\[7\]_MGIOL/CE (2496:2756:3016)(2496:2756:3016))
-        (INTERCONNECT SLICE_101/F0 RA\[6\]_MGIOL/CE (2496:2756:3016)(2496:2756:3016))
-        (INTERCONNECT SLICE_101/F0 RA\[5\]_MGIOL/CE (2486:2744:3002)(2486:2744:3002))
-        (INTERCONNECT SLICE_101/F0 RA\[4\]_MGIOL/CE (2475:2731:2987)(2475:2731:2987))
-        (INTERCONNECT SLICE_101/F0 RA\[2\]_MGIOL/CE (2486:2744:3002)(2486:2744:3002))
-        (INTERCONNECT SLICE_101/F0 RA\[1\]_MGIOL/CE (2496:2756:3016)(2496:2756:3016))
-        (INTERCONNECT SLICE_22/Q0 SLICE_31/D0 (1435:1561:1688)(1435:1561:1688))
-        (INTERCONNECT SLICE_22/Q0 RA\[0\]_I/PADDO (1713:1938:2163)(1713:1938:2163))
-        (INTERCONNECT SLICE_22/Q1 SLICE_31/C0 (1437:1618:1800)(1437:1618:1800))
-        (INTERCONNECT SLICE_22/Q1 RA\[3\]_I/PADDO (1365:1550:1735)(1365:1550:1735))
-        (INTERCONNECT SLICE_27/Q1 SLICE_23/B1 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_117/F1 SLICE_23/A1 (740:867:995)(740:867:995))
-        (INTERCONNECT SLICE_117/F1 SLICE_23/A0 (740:867:995)(740:867:995))
-        (INTERCONNECT SLICE_117/F1 SLICE_24/A1 (481:577:673)(481:577:673))
-        (INTERCONNECT SLICE_117/F1 SLICE_24/B0 (513:611:710)(513:611:710))
-        (INTERCONNECT SLICE_117/F1 SLICE_25/B1 (774:916:1058)(774:916:1058))
-        (INTERCONNECT SLICE_117/F1 SLICE_25/B0 (774:916:1058)(774:916:1058))
-        (INTERCONNECT SLICE_117/F1 SLICE_26/D1 (532:606:680)(532:606:680))
-        (INTERCONNECT SLICE_117/F1 SLICE_26/D0 (532:606:680)(532:606:680))
-        (INTERCONNECT SLICE_27/Q0 SLICE_23/D0 (520:573:626)(520:573:626))
+        (INTERCONNECT SLICE_22/Q0 ram2e_ufm\/SLICE_95/D0 (523:578:633)(523:578:633))
+        (INTERCONNECT SLICE_22/Q0 RAout\[4\]_MGIOL/OPOS (1894:2061:2229)(1894:2061:2229))
+        (INTERCONNECT SLICE_22/Q1 ram2e_ufm\/SLICE_140/C0 (534:644:754)(534:644:754))
+        (INTERCONNECT SLICE_22/Q1 RAout\[5\]_MGIOL/OPOS (1429:1575:1721)(1429:1575:1721))
+        (INTERCONNECT ram2e_ufm\/SLICE_132/F0 SLICE_23/C1 (531:639:747)(531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F0 SLICE_23/C0 (534:639:744)(534:639:744))
         (INTERCONNECT SLICE_23/F1 SLICE_23/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67/F0 SLICE_23/CE (885:985:1085)(885:985:1085))
-        (INTERCONNECT SLICE_67/F0 SLICE_23/CE (885:985:1085)(885:985:1085))
-        (INTERCONNECT SLICE_67/F0 SLICE_24/CE (563:627:691)(563:627:691))
-        (INTERCONNECT SLICE_67/F0 SLICE_24/CE (563:627:691)(563:627:691))
-        (INTERCONNECT SLICE_67/F0 SLICE_25/CE (563:627:691)(563:627:691))
-        (INTERCONNECT SLICE_67/F0 SLICE_25/CE (563:627:691)(563:627:691))
-        (INTERCONNECT SLICE_67/F0 SLICE_26/CE (563:627:691)(563:627:691))
-        (INTERCONNECT SLICE_67/F0 SLICE_26/CE (563:627:691)(563:627:691))
-        (INTERCONNECT SLICE_67/F0 SLICE_86/A0 (1119:1277:1436)(1119:1277:1436))
-        (INTERCONNECT SLICE_67/F0 SLICE_114/A0 (1119:1277:1436)(1119:1277:1436))
-        (INTERCONNECT SLICE_23/Q0 SLICE_96/A0 (1538:1731:1925)(1538:1731:1925))
-        (INTERCONNECT SLICE_23/Q1 SLICE_110/C1 (534:639:744)(534:639:744))
-        (INTERCONNECT SLICE_28/Q1 SLICE_24/D1 (857:949:1042)(857:949:1042))
-        (INTERCONNECT SLICE_28/Q0 SLICE_24/A0 (740:863:986)(740:863:986))
+        (INTERCONNECT SLICE_23/Q0 ram2e_ufm\/SLICE_96/A0 (735:856:978)(735:856:978))
+        (INTERCONNECT SLICE_23/Q0 RAout\[6\]_MGIOL/OPOS (2067:2267:2467)(2067:2267:2467))
+        (INTERCONNECT SLICE_23/Q1 ram2e_ufm\/SLICE_132/A0 (733:853:974)(733:853:974))
+        (INTERCONNECT SLICE_23/Q1 RAout\[7\]_MGIOL/OPOS (1857:2028:2199)(1857:2028:2199))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F0 SLICE_24/D1 (536:594:652)(536:594:652))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F0 SLICE_25/C1 (874:1022:1170)(874:1022:1170))
+        (INTERCONNECT ram2e_ufm\/SLICE_146/F1 SLICE_24/C1 (800:939:1079)(800:939:1079))
+        (INTERCONNECT SLICE_24/Q1 SLICE_24/A1 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_24/Q1 RAout\[9\]_MGIOL/OPOS (1863:2048:2233)(1863:2048:2233))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F0 SLICE_24/D0 (857:949:1042)(857:949:1042))
+        (INTERCONNECT ram2e_ufm\/SLICE_115/F1 SLICE_24/C0 (803:945:1088)(803:945:1088))
+        (INTERCONNECT ram2e_ufm\/SLICE_115/F1 ram2e_ufm\/SLICE_115/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_127/F0 SLICE_24/B0 (762:883:1004)(762:883:1004))
+        (INTERCONNECT SLICE_24/Q0 SLICE_24/A0 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_24/Q0 RAout\[8\]_MGIOL/OPOS (1793:1970:2148)(1793:1970:2148))
         (INTERCONNECT SLICE_24/F1 SLICE_24/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_24/Q0 SLICE_69/A1 (1104:1258:1413)(1104:1258:1413))
-        (INTERCONNECT SLICE_24/Q1 SLICE_103/D1 (523:573:623)(523:573:623))
-        (INTERCONNECT SLICE_29/Q1 SLICE_25/A1 (740:863:986)(740:863:986))
-        (INTERCONNECT SLICE_29/Q0 SLICE_25/A0 (740:863:986)(740:863:986))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F0 SLICE_25/D1 (271:301:332)(271:301:332))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F0 ram2e_ufm\/SLICE_74/C1 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F0 ram2e_ufm\/SLICE_146/D1 (794:884:975)
+          (794:884:975))
+        (INTERCONNECT SLICE_29/Q0 SLICE_25/B1 (1136:1293:1450)(1136:1293:1450))
+        (INTERCONNECT SLICE_25/Q1 SLICE_25/A1 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_25/Q1 RAout\[11\]_MGIOL/OPOS (1998:2162:2326)(1998:2162:2326))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F0 SLICE_25/D0 (1449:1580:1712)(1449:1580:1712))
+        (INTERCONNECT ram2e_ufm\/SLICE_129/F0 SLICE_25/C0 (277:356:436)(277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_106/F0 SLICE_25/B0 (508:600:693)(508:600:693))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F1 SLICE_25/A0 (476:566:656)(476:566:656))
         (INTERCONNECT SLICE_25/F1 SLICE_25/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_25/Q0 SLICE_102/C0 (534:639:744)(534:639:744))
-        (INTERCONNECT SLICE_25/Q1 SLICE_107/D0 (857:949:1042)(857:949:1042))
-        (INTERCONNECT SLICE_30/Q1 SLICE_26/A1 (733:848:964)(733:848:964))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_26/C0 (1720:1901:2083)(1720:1901:2083))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_30/C0 (2411:2659:2907)(2411:2659:2907))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_38/B0 (2402:2623:2845)(2402:2623:2845))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_49/C1 (3351:3662:3973)(3351:3662:3973))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/D1 (2632:2819:3006)(2632:2819:3006))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_81/B1 (3582:3906:4230)(3582:3906:4230))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_87/C1 (3383:3689:3995)(3383:3689:3995))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_91/D1 (3699:3985:4271)(3699:3985:4271))
-        (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_I/PADDO (3091:3324:3557)(3091:3324:3557))
-        (INTERCONNECT SLICE_30/Q0 SLICE_26/B0 (772:897:1023)(772:897:1023))
+        (INTERCONNECT SLICE_25/Q0 ram2e_ufm\/SLICE_106/D0 (536:594:652)(536:594:652))
+        (INTERCONNECT SLICE_25/Q0 RAout\[10\]_MGIOL/OPOS (1432:1576:1721)(1432:1576:1721))
         (INTERCONNECT SLICE_26/F1 SLICE_26/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_26/Q0 SLICE_47/D1 (900:989:1079)(900:989:1079))
-        (INTERCONNECT SLICE_26/Q0 SLICE_59/A1 (1110:1265:1420)(1110:1265:1420))
-        (INTERCONNECT SLICE_26/Q1 SLICE_96/C0 (1232:1411:1590)(1232:1411:1590))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO1 SLICE_27/C1 (1161:1328:1496)
-          (1161:1328:1496))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_27/D1 (846:940:1035)(846:940:1035))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_27/D0 (846:940:1035)(846:940:1035))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/A1 (1811:2036:2262)(1811:2036:2262))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/A0 (1811:2036:2262)(1811:2036:2262))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_29/D1 (1231:1359:1487)(1231:1359:1487))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_29/D0 (1231:1359:1487)(1231:1359:1487))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/D1 (1231:1359:1487)(1231:1359:1487))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/D0 (1231:1359:1487)(1231:1359:1487))
+        (INTERCONNECT ram2e_ufm\/SLICE_43/Q1 SLICE_27/B1 (772:897:1023)(772:897:1023))
+        (INTERCONNECT ram2e_ufm\/SLICE_43/Q0 SLICE_27/B0 (772:897:1023)(772:897:1023))
         (INTERCONNECT SLICE_27/F1 SLICE_27/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_114/F0 SLICE_27/CE (893:992:1091)(893:992:1091))
-        (INTERCONNECT SLICE_114/F0 SLICE_27/CE (893:992:1091)(893:992:1091))
-        (INTERCONNECT SLICE_114/F0 SLICE_28/CE (893:992:1091)(893:992:1091))
-        (INTERCONNECT SLICE_114/F0 SLICE_28/CE (893:992:1091)(893:992:1091))
-        (INTERCONNECT SLICE_114/F0 SLICE_29/CE (893:992:1091)(893:992:1091))
-        (INTERCONNECT SLICE_114/F0 SLICE_29/CE (893:992:1091)(893:992:1091))
-        (INTERCONNECT SLICE_114/F0 SLICE_30/CE (893:992:1091)(893:992:1091))
-        (INTERCONNECT SLICE_114/F0 SLICE_30/CE (893:992:1091)(893:992:1091))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO3 SLICE_28/B1 (1756:1968:2180)
-          (1756:1968:2180))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO2 SLICE_28/B0 (1392:1572:1753)
-          (1392:1572:1753))
+        (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/A1 (1180:1342:1505)(1180:1342:1505))
+        (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/A0 (1180:1342:1505)(1180:1342:1505))
+        (INTERCONNECT SLICE_27/Q1 ram2e_ufm\/SLICE_78/C0 (531:639:747)(531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_44/Q1 SLICE_28/C1 (868:1015:1163)(868:1015:1163))
+        (INTERCONNECT ram2e_ufm\/SLICE_44/Q0 SLICE_28/D0 (523:573:623)(523:573:623))
         (INTERCONNECT SLICE_28/F1 SLICE_28/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_28/F0 SLICE_28/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO5 SLICE_29/D1 (1150:1262:1375)
-          (1150:1262:1375))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO4 SLICE_29/A0 (1290:1460:1631)
-          (1290:1460:1631))
+        (INTERCONNECT SLICE_28/Q0 ram2e_ufm\/SLICE_146/C1 (534:639:744)(534:639:744))
+        (INTERCONNECT SLICE_28/Q1 ram2e_ufm\/SLICE_74/A1 (1174:1336:1498)(1174:1336:1498))
+        (INTERCONNECT ram2e_ufm\/SLICE_45/Q1 SLICE_29/A1 (740:863:986)(740:863:986))
+        (INTERCONNECT ram2e_ufm\/SLICE_45/Q0 SLICE_29/A0 (740:863:986)(740:863:986))
         (INTERCONNECT SLICE_29/F1 SLICE_29/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO7 SLICE_30/A1 (1360:1538:1716)
-          (1360:1538:1716))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO6 SLICE_30/B0 (1581:1781:1981)
-          (1581:1781:1981))
+        (INTERCONNECT SLICE_29/Q1 ram2e_ufm\/SLICE_72/B1 (1136:1293:1450)(1136:1293:1450))
+        (INTERCONNECT ram2e_ufm\/SLICE_46/Q1 SLICE_30/B1 (765:883:1001)(765:883:1001))
+        (INTERCONNECT ram2e_ufm\/SLICE_46/Q0 SLICE_30/C0 (534:639:744)(534:639:744))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_30/A0 (2705:2960:3215)(2705:2960:3215))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_40/D1 (2049:2212:2375)
+          (2049:2212:2375))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_42/D1 (2913:3132:3351)
+          (2913:3132:3351))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_46/A0 (3123:3407:3692)
+          (3123:3407:3692))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_50/C0 (3288:3593:3899)
+          (3288:3593:3899))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/A1 
+          (2628:2888:3149)(2628:2888:3149))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_62/D1 (2413:2607:2802)
+          (2413:2607:2802))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_65/A1 (3220:3505:3791)
+          (3220:3505:3791))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_82/D1 (2461:2653:2845)
+          (2461:2653:2845))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_83/D1 (2461:2653:2845)
+          (2461:2653:2845))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_144/B0 (2333:2561:2789)
+          (2333:2561:2789))
         (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT nEN80_I/PADDI SLICE_31/C1 (2184:2392:2600)(2184:2392:2600))
-        (INTERCONNECT nEN80_I/PADDI SLICE_79/B1 (2742:2998:3254)(2742:2998:3254))
-        (INTERCONNECT nEN80_I/PADDI SLICE_106/B0 (2317:2542:2767)(2317:2542:2767))
-        (INTERCONNECT nEN80_I/PADDI SLICE_115/D1 (2433:2621:2809)(2433:2621:2809))
-        (INTERCONNECT nEN80_I/PADDI SLICE_117/B0 (2681:2937:3194)(2681:2937:3194))
-        (INTERCONNECT nWE_I/PADDI SLICE_31/B1 (2579:2824:3070)(2579:2824:3070))
-        (INTERCONNECT nWE_I/PADDI SLICE_31/B0 (2579:2824:3070)(2579:2824:3070))
-        (INTERCONNECT nC07X_I/PADDI SLICE_31/A0 (1987:2195:2403)(1987:2195:2403))
+        (INTERCONNECT SLICE_30/Q0 ram2e_ufm\/SLICE_129/D1 (789:873:958)(789:873:958))
+        (INTERCONNECT SLICE_30/Q1 ram2e_ufm\/SLICE_127/C0 (541:653:766)(541:653:766))
+        (INTERCONNECT Ain\[3\]_I/PADDI SLICE_31/D1 (2384:2572:2760)(2384:2572:2760))
+        (INTERCONNECT nC07X_I/PADDI SLICE_31/C0 (1909:2116:2323)(1909:2116:2323))
+        (INTERCONNECT nWE_I/PADDI SLICE_31/B0 (2602:2880:3158)(2602:2880:3158))
+        (INTERCONNECT nWE_I/PADDI SLICE_36/D0 (3105:3379:3654)(3105:3379:3654))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/CKE_7\/SLICE_61/B0 (3341:3683:4025)
+          (3341:3683:4025))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_92/D1 (3105:3379:3654)(3105:3379:3654))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_112/D0 (3073:3352:3632)(3073:3352:3632))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_113/D0 (3073:3352:3632)(3073:3352:3632))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_136/C1 (2698:2998:3298)(2698:2998:3298))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_136/B0 (2602:2880:3158)(2602:2880:3158))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_137/B1 (2214:2429:2644)(2214:2429:2644))
         (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71/F0 SLICE_31/CE (927:1039:1151)(927:1039:1151))
-        (INTERCONNECT SLICE_71/F0 SLICE_59/B1 (777:908:1040)(777:908:1040))
-        (INTERCONNECT SLICE_71/F0 SLICE_71/B1 (767:894:1021)(767:894:1021))
-        (INTERCONNECT SLICE_31/F1 nDOE_I/PADDO (1820:2001:2182)(1820:2001:2182))
-        (INTERCONNECT SLICE_97/F0 SLICE_32/D1 (975:1072:1170)(975:1072:1170))
-        (INTERCONNECT SLICE_97/F0 SLICE_51/D0 (975:1072:1170)(975:1072:1170))
-        (INTERCONNECT SLICE_97/F0 SLICE_75/D1 (975:1072:1170)(975:1072:1170))
-        (INTERCONNECT SLICE_72/F1 SLICE_32/B1 (762:883:1004)(762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_127/F1 SLICE_31/CE (549:610:672)(549:610:672))
+        (INTERCONNECT ram2e_ufm\/SLICE_57/F1 SLICE_32/D1 (520:573:626)(520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_110/F1 SLICE_32/C1 (546:664:783)(546:664:783))
+        (INTERCONNECT ram2e_ufm\/SLICE_110/F1 ram2e_ufm\/SLICE_58/B1 (1036:1194:1353)
+          (1036:1194:1353))
+        (INTERCONNECT ram2e_ufm\/SLICE_110/F1 ram2e_ufm\/SLICE_110/B0 (513:611:710)
+          (513:611:710))
+        (INTERCONNECT ram2e_ufm\/SLICE_131/F1 SLICE_32/B1 (765:883:1001)(765:883:1001))
+        (INTERCONNECT ram2e_ufm\/SLICE_146/F0 SLICE_32/A1 (730:848:967)(730:848:967))
         (INTERCONNECT SLICE_32/F1 SLICE_32/C0 (277:356:436)(277:356:436))
+        (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_137/C1 (1388:1580:1773)(1388:1580:1773))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_137/C0 (1388:1580:1773)(1388:1580:1773))
+        (INTERCONNECT SLICE_32/Q0 SLICE_139/B0 (777:906:1036)(777:906:1036))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_141/D1 (1003:1108:1213)(1003:1108:1213))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_141/D0 (1003:1108:1213)(1003:1108:1213))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_142/C0 (1014:1174:1334)(1014:1174:1334))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_143/D1 (1377:1514:1652)(1377:1514:1652))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_143/D0 (1377:1514:1652)(1377:1514:1652))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_144/A1 (1587:1790:1993)(1587:1790:1993))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_144/A0 (1587:1790:1993)(1587:1790:1993))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_147/C0 (1014:1174:1334)(1014:1174:1334))
         (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_107/F1 SLICE_33/C1 (534:639:744)(534:639:744))
-        (INTERCONNECT SLICE_67/F1 SLICE_33/B1 (770:894:1018)(770:894:1018))
-        (INTERCONNECT SLICE_67/F1 SLICE_44/B0 (1047:1206:1366)(1047:1206:1366))
-        (INTERCONNECT SLICE_67/F1 SLICE_51/A1 (1722:1947:2172)(1722:1947:2172))
-        (INTERCONNECT SLICE_67/F1 SLICE_53/B0 (1422:1614:1806)(1422:1614:1806))
-        (INTERCONNECT SLICE_67/F1 SLICE_67/C0 (536:650:764)(536:650:764))
-        (INTERCONNECT SLICE_67/F1 SLICE_72/B0 (1427:1619:1812)(1427:1619:1812))
-        (INTERCONNECT SLICE_67/F1 SLICE_103/C1 (1523:1737:1952)(1523:1737:1952))
-        (INTERCONNECT SLICE_67/F1 SLICE_103/D0 (1512:1671:1831)(1512:1671:1831))
-        (INTERCONNECT SLICE_67/F1 SLICE_110/B1 (1422:1614:1806)(1422:1614:1806))
-        (INTERCONNECT SLICE_67/F1 SLICE_110/B0 (1422:1614:1806)(1422:1614:1806))
-        (INTERCONNECT SLICE_106/F1 SLICE_33/A1 (744:867:991)(744:867:991))
-        (INTERCONNECT SLICE_106/F1 SLICE_34/D1 (534:592:650)(534:592:650))
-        (INTERCONNECT SLICE_106/F1 SLICE_34/D0 (269:296:324)(269:296:324))
-        (INTERCONNECT SLICE_102/F1 SLICE_33/C0 (531:639:747)(531:639:747))
+        (INTERCONNECT SLICE_139/F0 SLICE_33/D1 (1248:1376:1505)(1248:1376:1505))
+        (INTERCONNECT SLICE_139/F0 SLICE_33/D0 (1248:1376:1505)(1248:1376:1505))
+        (INTERCONNECT SLICE_139/F0 SLICE_34/D1 (900:989:1079)(900:989:1079))
+        (INTERCONNECT SLICE_139/F0 SLICE_34/B0 (1490:1686:1883)(1490:1686:1883))
+        (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_33/C1 (538:655:772)(538:655:772))
+        (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_34/C1 (538:655:772)(538:655:772))
+        (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_34/C0 (284:372:461)(284:372:461))
+        (INTERCONNECT ram2e_ufm\/SLICE_106/F1 ram2e_ufm\/SLICE_106/B0 (515:616:718)
+          (515:616:718))
+        (INTERCONNECT ram2e_ufm\/SLICE_135/F1 SLICE_33/B1 (511:606:702)(511:606:702))
+        (INTERCONNECT ram2e_ufm\/SLICE_135/F1 SLICE_33/C0 (534:645:756)(534:645:756))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 SLICE_33/A1 (1025:1183:1341)(1025:1183:1341))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 SLICE_38/B1 (1748:1975:2202)(1748:1975:2202))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_78/D0 (525:584:643)
+          (525:584:643))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_79/B0 (1036:1194:1353)
+          (1036:1194:1353))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_105/B1 (1421:1613:1805)
+          (1421:1613:1805))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_106/A0 (1025:1183:1341)
+          (1025:1183:1341))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_135/D0 (1142:1269:1397)
+          (1142:1269:1397))
+        (INTERCONNECT ram2e_ufm\/SLICE_117/F1 SLICE_33/A0 (1372:1566:1760)(1372:1566:1760))
         (INTERCONNECT SLICE_33/F1 SLICE_33/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_34/Q0 SLICE_34/B1 (800:933:1066)(800:933:1066))
+        (INTERCONNECT SLICE_34/Q0 SLICE_34/A0 (483:579:675)(483:579:675))
+        (INTERCONNECT SLICE_34/Q0 SLICE_35/A0 (1126:1299:1472)(1126:1299:1472))
+        (INTERCONNECT SLICE_34/Q0 SLICE_38/A1 (746:897:1049)(746:897:1049))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_47/A1 (1478:1705:1932)(1478:1705:1932))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_48/D1 (1248:1407:1567)(1248:1407:1567))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_48/D0 (1248:1407:1567)(1248:1407:1567))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_49/A1 (1853:2112:2372)(1853:2112:2372))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_49/A0 (1853:2112:2372)(1853:2112:2372))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_50/B1 (2265:2560:2855)(2265:2560:2855))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_50/B0 (2265:2560:2855)(2265:2560:2855))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_52/A0 (1868:2129:2390)(1868:2129:2390))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_53/D0 (2028:2255:2483)(2028:2255:2483))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_54/A1 (1868:2129:2390)(1868:2129:2390))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_56/LSR (2733:3030:3328)(2733:3030:3328))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_69/D0 (813:934:1056)(813:934:1056))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_71/D0 (813:934:1056)(813:934:1056))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_72/D0 (886:987:1089)(886:987:1089))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_74/D0 (886:987:1089)(886:987:1089))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_77/B0 (1972:2234:2496)(1972:2234:2496))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_78/A0 (1468:1694:1920)(1468:1694:1920))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_79/D0 (2023:2250:2477)(2023:2250:2477))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_86/A1 (1478:1705:1932)(1478:1705:1932))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_89/B0 (2270:2565:2861)(2270:2565:2861))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_90/B0 (2270:2565:2861)(2270:2565:2861))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_95/A1 (1393:1612:1831)(1393:1612:1831))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_96/C1 (1194:1402:1611)(1194:1402:1611))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_97/A0 (1868:2129:2390)(1868:2129:2390))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_98/A0 (2565:2893:3221)(2565:2893:3221))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_102/A1 (1018:1204:1391)(1018:1204:1391))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_106/C0 (569:689:809)(569:689:809))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_107/C1 (2007:2286:2566)(2007:2286:2566))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_109/B1 (1510:1739:1969)(1510:1739:1969))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_112/A0 (746:897:1049)(746:897:1049))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_113/C1 (547:688:829)(547:688:829))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_115/B1 (1420:1641:1862)(1420:1641:1862))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_117/A1 (1876:2129:2383)(1876:2129:2383))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_117/A0 (1876:2129:2383)(1876:2129:2383))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_118/D1 (1666:1854:2042)(1666:1854:2042))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_118/D0 (1666:1854:2042)(1666:1854:2042))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_119/A1 (1126:1299:1472)(1126:1299:1472))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_119/A0 (1126:1299:1472)(1126:1299:1472))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_121/B1 (1500:1728:1957)(1500:1728:1957))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_121/B0 (1500:1728:1957)(1500:1728:1957))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_127/A1 (1126:1299:1472)(1126:1299:1472))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_127/A0 (1126:1299:1472)(1126:1299:1472))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_135/A1 (768:898:1029)(768:898:1029))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_135/A0 (768:898:1029)(768:898:1029))
+        (INTERCONNECT SLICE_34/Q0 SLICE_138/A0 (1557:1755:1954)(1557:1755:1954))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_145/A1 (1868:2129:2390)(1868:2129:2390))
         (INTERCONNECT SLICE_34/F1 SLICE_34/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_34/F0 SLICE_34/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62/F1 SLICE_35/D1 (523:573:623)(523:573:623))
-        (INTERCONNECT SLICE_60/F1 SLICE_35/C1 (541:653:766)(541:653:766))
-        (INTERCONNECT SLICE_74/F1 SLICE_35/C0 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_74/F1 SLICE_74/A0 (735:859:984)(735:859:984))
-        (INTERCONNECT SLICE_74/F1 SLICE_108/A0 (745:874:1003)(745:874:1003))
-        (INTERCONNECT SLICE_85/F0 SLICE_35/B0 (765:883:1001)(765:883:1001))
-        (INTERCONNECT SLICE_104/F0 SLICE_35/A0 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_35/F1 SLICE_35/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_110/F0 SLICE_35/CE (819:908:998)(819:908:998))
-        (INTERCONNECT SLICE_110/F0 SLICE_35/CE (819:908:998)(819:908:998))
-        (INTERCONNECT SLICE_110/F0 SLICE_36/CE (1209:1332:1456)(1209:1332:1456))
-        (INTERCONNECT SLICE_110/F0 SLICE_36/CE (1209:1332:1456)(1209:1332:1456))
-        (INTERCONNECT SLICE_110/F0 SLICE_37/CE (1573:1728:1883)(1573:1728:1883))
-        (INTERCONNECT SLICE_110/F0 SLICE_37/CE (1573:1728:1883)(1573:1728:1883))
-        (INTERCONNECT SLICE_110/F0 SLICE_38/CE (819:908:998)(819:908:998))
-        (INTERCONNECT SLICE_110/F0 SLICE_38/CE (819:908:998)(819:908:998))
-        (INTERCONNECT SLICE_110/F0 SLICE_40/CE (1209:1332:1456)(1209:1332:1456))
-        (INTERCONNECT SLICE_110/F0 SLICE_40/CE (1209:1332:1456)(1209:1332:1456))
-        (INTERCONNECT SLICE_110/F0 SLICE_41/CE (1209:1332:1456)(1209:1332:1456))
-        (INTERCONNECT SLICE_110/F0 SLICE_41/CE (1209:1332:1456)(1209:1332:1456))
-        (INTERCONNECT SLICE_110/F0 SLICE_42/CE (1209:1332:1456)(1209:1332:1456))
-        (INTERCONNECT SLICE_110/F0 SLICE_42/CE (1209:1332:1456)(1209:1332:1456))
-        (INTERCONNECT SLICE_110/F0 SLICE_43/CE (1209:1332:1456)(1209:1332:1456))
-        (INTERCONNECT SLICE_110/F0 SLICE_43/CE (1209:1332:1456)(1209:1332:1456))
-        (INTERCONNECT SLICE_35/Q0 SLICE_40/D0 (1590:1742:1894)(1590:1742:1894))
-        (INTERCONNECT SLICE_35/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in (1343:1474:1606)
-          (1343:1474:1606))
-        (INTERCONNECT SLICE_35/Q1 SLICE_109/B0 (1467:1656:1846)(1467:1656:1846))
-        (INTERCONNECT SLICE_35/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in (1342:1474:1607)
-          (1342:1474:1607))
-        (INTERCONNECT SLICE_36/F1 SLICE_36/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_138/F1 SLICE_35/LSR (873:967:1062)(873:967:1062))
+        (INTERCONNECT SLICE_35/Q0 SLICE_139/A1 (733:848:964)(733:848:964))
+        (INTERCONNECT SLICE_35/F1 BA\[1\]_MGIOL/LSR (2019:2186:2354)(2019:2186:2354))
+        (INTERCONNECT SLICE_35/F1 BA\[0\]_MGIOL/LSR (2019:2186:2354)(2019:2186:2354))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_36/C1 (545:668:791)(545:668:791))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_37/A1 (739:869:1000)(739:869:1000))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_38/D0 (275:311:348)(275:311:348))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/CKE_7\/SLICE_61/D0 (532:594:656)
+          (532:594:656))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/SLICE_92/C1 (545:668:791)
+          (545:668:791))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/SLICE_113/C0 (286:377:469)
+          (286:377:469))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_36/A1 (1092:1256:1420)(1092:1256:1420))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_37/C1 (903:1058:1214)(903:1058:1214))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_38/C1 (903:1058:1214)(903:1058:1214))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_91/B0 (1150:1311:1472)
+          (1150:1311:1472))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_92/A0 (1092:1256:1420)
+          (1092:1256:1420))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_105/C1 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_112/C1 (903:1058:1214)
+          (903:1058:1214))
+        (INTERCONNECT SLICE_36/F1 SLICE_36/C0 (277:356:436)(277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_69/F1 SLICE_36/B0 (772:897:1023)(772:897:1023))
+        (INTERCONNECT ram2e_ufm\/SLICE_92/F0 SLICE_36/A0 (476:566:656)(476:566:656))
         (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_36/Q0 SLICE_41/B0 (1139:1298:1457)(1139:1298:1457))
-        (INTERCONNECT SLICE_36/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI2in (643:706:769)
-          (643:706:769))
-        (INTERCONNECT SLICE_36/Q1 SLICE_68/B1 (765:888:1011)(765:888:1011))
-        (INTERCONNECT SLICE_36/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI3in (650:720:791)
-          (650:720:791))
-        (INTERCONNECT SLICE_37/F1 SLICE_37/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_36/Q0 nCASout_MGIOL/OPOS (1549:1684:1820)(1549:1684:1820))
+        (INTERCONNECT SLICE_38/F1 SLICE_37/D0 (523:579:635)(523:579:635))
+        (INTERCONNECT SLICE_38/F1 SLICE_38/B0 (511:606:702)(511:606:702))
+        (INTERCONNECT SLICE_37/F1 SLICE_37/C0 (277:356:436)(277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_112/F0 SLICE_37/B0 (508:600:693)(508:600:693))
+        (INTERCONNECT ram2e_ufm\/SLICE_91/F0 SLICE_37/A0 (1067:1225:1383)(1067:1225:1383))
         (INTERCONNECT SLICE_37/F0 SLICE_37/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_37/Q0 SLICE_114/D1 (791:881:972)(791:881:972))
-        (INTERCONNECT SLICE_37/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI4in (1599:1767:1935)
-          (1599:1767:1935))
-        (INTERCONNECT SLICE_37/Q1 SLICE_42/A1 (1073:1231:1390)(1073:1231:1390))
-        (INTERCONNECT SLICE_37/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI5in (1344:1479:1615)
-          (1344:1479:1615))
-        (INTERCONNECT SLICE_38/F1 SLICE_38/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_37/Q0 nRASout_MGIOL/OPOS (1986:2148:2310)(1986:2148:2310))
+        (INTERCONNECT ram2e_ufm\/SLICE_136/F1 SLICE_38/D1 (977:1075:1173)(977:1075:1173))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F1 SLICE_38/C0 (534:639:744)(534:639:744))
+        (INTERCONNECT ram2e_ufm\/SLICE_112/F1 SLICE_38/A0 (733:854:976)(733:854:976))
+        (INTERCONNECT ram2e_ufm\/SLICE_112/F1 ram2e_ufm\/SLICE_112/C0 (280:362:445)
+          (280:362:445))
         (INTERCONNECT SLICE_38/F0 SLICE_38/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_38/Q0 SLICE_84/B0 (778:904:1030)(778:904:1030))
-        (INTERCONNECT SLICE_38/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI6in (1708:1875:2042)
-          (1708:1875:2042))
-        (INTERCONNECT SLICE_38/Q1 SLICE_109/C1 (980:1133:1286)(980:1133:1286))
-        (INTERCONNECT SLICE_38/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI7in (1413:1557:1701)
-          (1413:1557:1701))
-        (INTERCONNECT SLICE_63/F1 SLICE_39/D1 (791:881:972)(791:881:972))
-        (INTERCONNECT SLICE_63/F1 SLICE_52/D1 (1222:1348:1474)(1222:1348:1474))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_39/C1 (1776:2012:2248)
-          (1776:2012:2248))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_45/B1 (1996:2243:2490)
-          (1996:2243:2490))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_57/C1 (1776:2012:2248)
-          (1776:2012:2248))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_64/A0 (1623:1832:2041)
-          (1623:1832:2041))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_105/D1 (1413:1556:1700)
-          (1413:1556:1700))
-        (INTERCONNECT SLICE_39/F1 SLICE_39/B0 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_39/F0 SLICE_39/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52/F0 SLICE_39/CE (539:596:653)(539:596:653))
-        (INTERCONNECT SLICE_39/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCYCIin 
-          (1707:1870:2033)(1707:1870:2033))
-        (INTERCONNECT SLICE_39/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBSTBIin 
-          (2053:2255:2457)(2053:2255:2457))
-        (INTERCONNECT SLICE_109/F0 SLICE_40/D1 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_68/F0 SLICE_40/C1 (986:1144:1302)(986:1144:1302))
-        (INTERCONNECT SLICE_68/F0 SLICE_43/D0 (975:1078:1181)(975:1078:1181))
-        (INTERCONNECT SLICE_68/F0 SLICE_68/C1 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_68/F0 SLICE_70/B1 (770:894:1018)(770:894:1018))
-        (INTERCONNECT SLICE_90/F0 SLICE_40/B1 (770:897:1024)(770:897:1024))
-        (INTERCONNECT SLICE_90/F0 SLICE_41/B1 (1036:1197:1359)(1036:1197:1359))
-        (INTERCONNECT SLICE_90/F0 SLICE_88/A0 (733:854:976)(733:854:976))
-        (INTERCONNECT SLICE_56/F0 SLICE_40/A1 (1188:1354:1520)(1188:1354:1520))
-        (INTERCONNECT SLICE_56/F0 SLICE_43/A0 (1188:1354:1520)(1188:1354:1520))
-        (INTERCONNECT SLICE_56/F0 SLICE_50/C0 (1316:1506:1697)(1316:1506:1697))
-        (INTERCONNECT SLICE_56/F0 SLICE_104/D1 (871:968:1066)(871:968:1066))
-        (INTERCONNECT SLICE_56/F0 SLICE_104/D0 (871:968:1066)(871:968:1066))
-        (INTERCONNECT SLICE_116/F0 SLICE_40/C0 (800:939:1079)(800:939:1079))
-        (INTERCONNECT SLICE_86/F1 SLICE_40/A0 (756:886:1016)(756:886:1016))
-        (INTERCONNECT SLICE_86/F1 SLICE_74/D1 (969:1071:1174)(969:1071:1174))
-        (INTERCONNECT SLICE_86/F1 SLICE_86/C0 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_86/F1 SLICE_90/A0 (756:886:1016)(756:886:1016))
-        (INTERCONNECT SLICE_86/F1 SLICE_105/A0 (756:886:1016)(756:886:1016))
-        (INTERCONNECT SLICE_40/F1 SLICE_40/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40/F0 SLICE_40/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI0in (1233:1363:1494)
-          (1233:1363:1494))
-        (INTERCONNECT SLICE_40/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI1in (1081:1188:1296)
-          (1081:1188:1296))
-        (INTERCONNECT SLICE_58/F1 SLICE_41/D1 (523:573:623)(523:573:623))
-        (INTERCONNECT SLICE_68/F1 SLICE_41/C1 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_88/F0 SLICE_41/D0 (795:880:965)(795:880:965))
-        (INTERCONNECT SLICE_88/F0 SLICE_42/D1 (795:880:965)(795:880:965))
-        (INTERCONNECT SLICE_70/F1 SLICE_41/A0 (738:862:987)(738:862:987))
-        (INTERCONNECT SLICE_70/F1 SLICE_42/C1 (539:653:767)(539:653:767))
-        (INTERCONNECT SLICE_70/F1 SLICE_42/D0 (860:955:1051)(860:955:1051))
-        (INTERCONNECT SLICE_41/F1 SLICE_41/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_41/F0 SLICE_41/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_41/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI2in (1338:1473:1608)
-          (1338:1473:1608))
-        (INTERCONNECT SLICE_41/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI3in (906:1001:1097)
-          (906:1001:1097))
-        (INTERCONNECT SLICE_74/F0 SLICE_42/C0 (544:659:775)(544:659:775))
-        (INTERCONNECT SLICE_74/F0 SLICE_84/A0 (479:572:665)(479:572:665))
-        (INTERCONNECT SLICE_104/F1 SLICE_42/B0 (1031:1183:1336)(1031:1183:1336))
-        (INTERCONNECT SLICE_114/F1 SLICE_42/A0 (1326:1511:1696)(1326:1511:1696))
-        (INTERCONNECT SLICE_42/F1 SLICE_42/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI4in (1233:1363:1494)
-          (1233:1363:1494))
-        (INTERCONNECT SLICE_42/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI5in (1338:1473:1608)
-          (1338:1473:1608))
-        (INTERCONNECT SLICE_50/F0 SLICE_43/D1 (266:290:315)(266:290:315))
-        (INTERCONNECT SLICE_109/F1 SLICE_43/C1 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_108/F0 SLICE_43/B1 (772:897:1023)(772:897:1023))
-        (INTERCONNECT SLICE_105/F0 SLICE_43/A1 (733:848:964)(733:848:964))
-        (INTERCONNECT SLICE_84/F0 SLICE_43/B0 (765:883:1001)(765:883:1001))
-        (INTERCONNECT SLICE_43/F1 SLICE_43/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_43/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in (1233:1363:1494)
-          (1233:1363:1494))
-        (INTERCONNECT SLICE_43/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI7in (1081:1188:1296)
-          (1081:1188:1296))
-        (INTERCONNECT SLICE_44/F1 SLICE_44/A0 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_103/F0 SLICE_44/CE (1566:1725:1884)(1566:1725:1884))
-        (INTERCONNECT SLICE_44/Q0 SLICE_52/B1 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_45/F0 SLICE_45/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_47/F0 SLICE_45/LSR (1589:1762:1936)(1589:1762:1936))
-        (INTERCONNECT SLICE_47/F0 SLICE_47/C1 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_47/F0 SLICE_56/C1 (1618:1839:2060)(1618:1839:2060))
-        (INTERCONNECT SLICE_47/F0 SLICE_59/C1 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_47/F0 SLICE_73/B0 (1474:1675:1877)(1474:1675:1877))
-        (INTERCONNECT SLICE_47/F0 SLICE_75/A0 (1006:1168:1330)(1006:1168:1330))
-        (INTERCONNECT SLICE_47/F0 SLICE_86/C1 (1618:1839:2060)(1618:1839:2060))
-        (INTERCONNECT SLICE_45/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBRSTIin 
-          (1492:1649:1807)(1492:1649:1807))
-        (INTERCONNECT SLICE_45/F1 SLICE_52/A0 (1067:1225:1383)(1067:1225:1383))
-        (INTERCONNECT SLICE_95/F0 SLICE_46/D0 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_46/F1 SLICE_46/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_66/F1 SLICE_46/B0 (515:616:718)(515:616:718))
-        (INTERCONNECT SLICE_66/F1 SLICE_60/A1 (742:872:1003)(742:872:1003))
-        (INTERCONNECT SLICE_66/F1 SLICE_62/D1 (530:589:648)(530:589:648))
-        (INTERCONNECT SLICE_66/F1 SLICE_66/D0 (527:589:651)(527:589:651))
-        (INTERCONNECT SLICE_66/F1 SLICE_95/A1 (1439:1639:1840)(1439:1639:1840))
-        (INTERCONNECT SLICE_46/F0 SLICE_46/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_53/F0 SLICE_46/CE (1604:1763:1923)(1604:1763:1923))
-        (INTERCONNECT SLICE_46/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin 
+        (INTERCONNECT SLICE_38/Q0 nRWEout_MGIOL/OPOS (1913:2080:2247)(1913:2080:2247))
+        (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_39/A1 (1059:1222:1385)
+          (1059:1222:1385))
+        (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_87/D1 (1213:1342:1471)
+          (1213:1342:1471))
+        (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_94/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_116/B1 (1091:1256:1422)
+          (1091:1256:1422))
+        (INTERCONNECT ram2e_ufm\/SLICE_39/F1 ram2e_ufm\/SLICE_39/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_39/F0 ram2e_ufm\/SLICE_39/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_39/Q0 ram2e_ufm\/SLICE_80/D0 (854:944:1035)
+          (854:944:1035))
+        (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_40/B0 (511:606:702)
+          (511:606:702))
+        (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_62/C1 (550:666:782)
+          (550:666:782))
+        (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_83/A1 (1113:1271:1429)
+          (1113:1271:1429))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/F0 ram2e_ufm\/SLICE_40/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_51/A0 (1642:1834:2027)
+          (1642:1834:2027))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_66/D0 (1759:1921:2083)
+          (1759:1921:2083))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_130/A0 (743:868:993)
+          (743:868:993))
+        (INTERCONNECT ram2e_ufm\/SLICE_41/F1 ram2e_ufm\/SLICE_41/D0 (520:573:626)
+          (520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_41/B0 (781:910:1039)
+          (781:910:1039))
+        (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_87/B1 (1253:1415:1578)
+          (1253:1415:1578))
+        (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_101/A0 (733:854:976)
+          (733:854:976))
+        (INTERCONNECT ram2e_ufm\/SLICE_41/F0 ram2e_ufm\/SLICE_41/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_41/Q0 ram2e_ufm\/SLICE_147/A1 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO0 ram2e_ufm\/SLICE_42/C0 
+          (1531:1730:1930)(1531:1730:1930))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO0 ram2e_ufm\/SLICE_43/B0 
+          (1762:1974:2187)(1762:1974:2187))
+        (INTERCONNECT ram2e_ufm\/SLICE_42/F0 ram2e_ufm\/SLICE_42/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F1 ram2e_ufm\/SLICE_42/CE (876:972:1069)
+          (876:972:1069))
+        (INTERCONNECT ram2e_ufm\/SLICE_42/Q0 ram2e_ufm\/SLICE_137/B0 (1670:1864:2058)
+          (1670:1864:2058))
+        (INTERCONNECT ram2e_ufm\/SLICE_42/Q0 ram2e_ufm\/SLICE_147/C1 (993:1147:1302)
+          (993:1147:1302))
+        (INTERCONNECT ram2e_ufm\/SLICE_42/F1 ram2e_ufm\/SLICE_84/C1 (849:1000:1152)
+          (849:1000:1152))
+        (INTERCONNECT ram2e_ufm\/SLICE_42/F1 ram2e_ufm\/SLICE_87/A1 (1215:1374:1534)
+          (1215:1374:1534))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO1 ram2e_ufm\/SLICE_43/B1 
+          (1769:1982:2196)(1769:1982:2196))
+        (INTERCONNECT ram2e_ufm\/SLICE_43/F1 ram2e_ufm\/SLICE_43/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_43/F0 ram2e_ufm\/SLICE_43/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_43/CE (900:1003:1107)
+          (900:1003:1107))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_43/CE (900:1003:1107)
+          (900:1003:1107))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_44/CE (542:602:662)
+          (542:602:662))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_44/CE (542:602:662)
+          (542:602:662))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_45/CE (900:1003:1107)
+          (900:1003:1107))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_45/CE (900:1003:1107)
+          (900:1003:1107))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_46/CE (900:1003:1107)
+          (900:1003:1107))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_46/CE (900:1003:1107)
+          (900:1003:1107))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO3 ram2e_ufm\/SLICE_44/B1 
+          (1686:1890:2095)(1686:1890:2095))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO2 ram2e_ufm\/SLICE_44/C0 
+          (1174:1343:1512)(1174:1343:1512))
+        (INTERCONNECT ram2e_ufm\/SLICE_44/F1 ram2e_ufm\/SLICE_44/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_44/F0 ram2e_ufm\/SLICE_44/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO5 ram2e_ufm\/SLICE_45/C1 
+          (1525:1724:1923)(1525:1724:1923))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO4 ram2e_ufm\/SLICE_45/C0 
+          (1538:1738:1939)(1538:1738:1939))
+        (INTERCONNECT ram2e_ufm\/SLICE_45/F1 ram2e_ufm\/SLICE_45/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_45/F0 ram2e_ufm\/SLICE_45/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO7 ram2e_ufm\/SLICE_46/C1 
+          (1525:1724:1923)(1525:1724:1923))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO6 ram2e_ufm\/SLICE_46/C0 
+          (1538:1738:1939)(1538:1738:1939))
+        (INTERCONNECT ram2e_ufm\/SLICE_46/F1 ram2e_ufm\/SLICE_46/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_46/F0 ram2e_ufm\/SLICE_46/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_103/F0 ram2e_ufm\/SLICE_47/D1 (266:290:315)
+          (266:290:315))
+        (INTERCONNECT ram2e_ufm\/SLICE_114/F0 ram2e_ufm\/SLICE_47/B1 (508:600:693)
+          (508:600:693))
+        (INTERCONNECT ram2e_ufm\/SLICE_86/F0 ram2e_ufm\/SLICE_47/D0 (523:573:623)
+          (523:573:623))
+        (INTERCONNECT ram2e_ufm\/SLICE_64/F0 ram2e_ufm\/SLICE_47/C0 (534:639:744)
+          (534:639:744))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_47/B0 (1156:1317:1479)
+          (1156:1317:1479))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_52/B1 (1161:1323:1485)
+          (1161:1323:1485))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_55/A0 (1129:1288:1448)
+          (1129:1288:1448))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_64/D1 (1278:1403:1528)
+          (1278:1403:1528))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_85/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_88/D0 (544:605:667)
+          (544:605:667))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_125/C0 (930:1079:1228)
+          (930:1079:1228))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/F1 ram2e_ufm\/SLICE_47/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/F0 ram2e_ufm\/SLICE_47/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_47/CE (1369:1503:1637)
+          (1369:1503:1637))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_47/CE (1369:1503:1637)
+          (1369:1503:1637))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_48/CE (1364:1497:1631)
+          (1364:1497:1631))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_48/CE (1364:1497:1631)
+          (1364:1497:1631))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_49/CE (1733:1898:2064)
+          (1733:1898:2064))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_49/CE (1733:1898:2064)
+          (1733:1898:2064))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_50/CE (1358:1491:1624)
+          (1358:1491:1624))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_50/CE (1358:1491:1624)
+          (1358:1491:1624))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_52/CE (1744:1910:2077)
+          (1744:1910:2077))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_52/CE (1744:1910:2077)
+          (1744:1910:2077))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_53/CE (1728:1893:2058)
+          (1728:1893:2058))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_53/CE (1728:1893:2058)
+          (1728:1893:2058))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_54/CE (1744:1910:2077)
+          (1744:1910:2077))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_54/CE (1744:1910:2077)
+          (1744:1910:2077))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_55/CE (2108:2306:2504)
+          (2108:2306:2504))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_55/CE (2108:2306:2504)
+          (2108:2306:2504))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/Q0 ram2e_ufm\/SLICE_52/B0 (767:891:1015)
+          (767:891:1015))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in 
+          (1272:1405:1538)(1272:1405:1538))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/Q1 ram2e_ufm\/SLICE_97/D0 (1297:1429:1561)
+          (1297:1429:1561))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in 
+          (1451:1590:1730)(1451:1590:1730))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/F1 ram2e_ufm\/SLICE_48/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/F0 ram2e_ufm\/SLICE_48/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/Q0 ram2e_ufm\/SLICE_53/C0 (536:647:758)
+          (536:647:758))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI2in 
+          (1235:1371:1508)(1235:1371:1508))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/Q1 ram2e_ufm\/SLICE_89/A0 (1432:1623:1815)
+          (1432:1623:1815))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI3in 
+          (1235:1371:1508)(1235:1371:1508))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/F1 ram2e_ufm\/SLICE_49/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/F0 ram2e_ufm\/SLICE_49/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/Q0 ram2e_ufm\/SLICE_145/B1 (1142:1299:1457)
+          (1142:1299:1457))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI4in 
+          (1708:1875:2042)(1708:1875:2042))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/Q1 ram2e_ufm\/SLICE_54/B1 (1142:1299:1457)
+          (1142:1299:1457))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI5in 
+          (1381:1513:1645)(1381:1513:1645))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/F1 ram2e_ufm\/SLICE_50/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/F0 ram2e_ufm\/SLICE_50/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/Q0 ram2e_ufm\/SLICE_90/D0 (536:594:652)
+          (536:594:652))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI6in 
+          (1708:1875:2042)(1708:1875:2042))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/Q1 ram2e_ufm\/SLICE_98/B0 (1105:1266:1427)
+          (1105:1266:1427))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI7in 
+          (1381:1513:1645)(1381:1513:1645))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBACKO ram2e_ufm\/SLICE_51/D1 
+          (1166:1281:1396)(1166:1281:1396))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBACKO ram2e_ufm\/SLICE_66/A1 
+          (1376:1556:1737)(1376:1556:1737))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBACKO ram2e_ufm\/SLICE_66/C0 
+          (1504:1709:1914)(1504:1709:1914))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBACKO ram2e_ufm\/SLICE_75/C0 
+          (1640:1837:2035)(1640:1837:2035))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBACKO ram2e_ufm\/SLICE_110/C0 
+          (1640:1837:2035)(1640:1837:2035))
+        (INTERCONNECT ram2e_ufm\/SLICE_108/F1 ram2e_ufm\/SLICE_51/B1 (768:889:1010)
+          (768:889:1010))
+        (INTERCONNECT ram2e_ufm\/SLICE_108/F1 ram2e_ufm\/SLICE_108/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_51/F1 ram2e_ufm\/SLICE_51/B0 (508:600:693)
+          (508:600:693))
+        (INTERCONNECT ram2e_ufm\/SLICE_51/F0 ram2e_ufm\/SLICE_51/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_66/F0 ram2e_ufm\/SLICE_51/CE (539:596:653)
+          (539:596:653))
+        (INTERCONNECT ram2e_ufm\/SLICE_51/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBCYCIin 
+          (1087:1195:1303)(1087:1195:1303))
+        (INTERCONNECT ram2e_ufm\/SLICE_51/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBSTBIin 
+          (1433:1580:1727)(1433:1580:1727))
+        (INTERCONNECT ram2e_ufm\/SLICE_97/F0 ram2e_ufm\/SLICE_52/D1 (266:290:315)
+          (266:290:315))
+        (INTERCONNECT ram2e_ufm\/SLICE_111/F1 ram2e_ufm\/SLICE_52/C1 (547:660:773)
+          (547:660:773))
+        (INTERCONNECT ram2e_ufm\/SLICE_111/F1 ram2e_ufm\/SLICE_53/C1 (1645:1853:2061)
+          (1645:1853:2061))
+        (INTERCONNECT ram2e_ufm\/SLICE_111/F1 ram2e_ufm\/SLICE_73/C1 (917:1062:1207)
+          (917:1062:1207))
+        (INTERCONNECT ram2e_ufm\/SLICE_123/F0 ram2e_ufm\/SLICE_52/A1 (735:859:984)
+          (735:859:984))
+        (INTERCONNECT ram2e_ufm\/SLICE_123/F0 ram2e_ufm\/SLICE_53/D1 (1226:1356:1486)
+          (1226:1356:1486))
+        (INTERCONNECT ram2e_ufm\/SLICE_123/F0 ram2e_ufm\/SLICE_55/B0 (1211:1381:1552)
+          (1211:1381:1552))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F1 ram2e_ufm\/SLICE_52/D0 (528:587:646)
+          (528:587:646))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F1 ram2e_ufm\/SLICE_64/C0 (811:960:1109)
+          (811:960:1109))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F1 ram2e_ufm\/SLICE_81/B0 (511:606:702)
+          (511:606:702))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F1 ram2e_ufm\/SLICE_131/C0 (1539:1751:1963)
+          (1539:1751:1963))
+        (INTERCONNECT ram2e_ufm\/SLICE_128/F1 ram2e_ufm\/SLICE_52/C0 (531:639:747)
+          (531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_52/F1 ram2e_ufm\/SLICE_52/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_52/F0 ram2e_ufm\/SLICE_52/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_52/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI0in 
+          (974:1077:1181)(974:1077:1181))
+        (INTERCONNECT ram2e_ufm\/SLICE_52/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI1in 
+          (906:1001:1097)(906:1001:1097))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_53/B1 (782:917:1052)
+          (782:917:1052))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_68/D1 (275:311:348)
+          (275:311:348))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_89/C0 (286:377:469)
+          (286:377:469))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_90/A0 (742:869:997)
+          (742:869:997))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_93/B0 (782:917:1052)
+          (782:917:1052))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_145/D1 (532:594:656)
+          (532:594:656))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F0 ram2e_ufm\/SLICE_53/A1 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_73/F1 ram2e_ufm\/SLICE_53/B0 (775:903:1032)
+          (775:903:1032))
+        (INTERCONNECT ram2e_ufm\/SLICE_73/F1 ram2e_ufm\/SLICE_54/D1 (269:296:324)
+          (269:296:324))
+        (INTERCONNECT ram2e_ufm\/SLICE_93/F0 ram2e_ufm\/SLICE_53/A0 (733:854:976)
+          (733:854:976))
+        (INTERCONNECT ram2e_ufm\/SLICE_93/F0 ram2e_ufm\/SLICE_54/C1 (539:653:767)
+          (539:653:767))
+        (INTERCONNECT ram2e_ufm\/SLICE_93/F0 ram2e_ufm\/SLICE_54/C0 (539:653:767)
+          (539:653:767))
+        (INTERCONNECT ram2e_ufm\/SLICE_53/F1 ram2e_ufm\/SLICE_53/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_53/F0 ram2e_ufm\/SLICE_53/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_53/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI2in 
+          (1081:1188:1296)(1081:1188:1296))
+        (INTERCONNECT ram2e_ufm\/SLICE_53/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI3in 
+          (1011:1111:1211)(1011:1111:1211))
+        (INTERCONNECT ram2e_ufm\/SLICE_125/F0 ram2e_ufm\/SLICE_54/D0 (523:573:623)
+          (523:573:623))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F0 ram2e_ufm\/SLICE_54/B0 (1034:1189:1345)
+          (1034:1189:1345))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F0 ram2e_ufm\/SLICE_55/D0 (269:296:324)
+          (269:296:324))
+        (INTERCONNECT ram2e_ufm\/SLICE_145/F1 ram2e_ufm\/SLICE_54/A0 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_54/F1 ram2e_ufm\/SLICE_54/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_54/F0 ram2e_ufm\/SLICE_54/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_54/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI4in 
+          (906:1001:1097)(906:1001:1097))
+        (INTERCONNECT ram2e_ufm\/SLICE_54/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI5in 
+          (1233:1363:1494)(1233:1363:1494))
+        (INTERCONNECT ram2e_ufm\/SLICE_88/F0 ram2e_ufm\/SLICE_55/D1 (1220:1340:1460)
+          (1220:1340:1460))
+        (INTERCONNECT ram2e_ufm\/SLICE_70/F0 ram2e_ufm\/SLICE_55/C1 (534:639:744)
+          (534:639:744))
+        (INTERCONNECT ram2e_ufm\/SLICE_131/F0 ram2e_ufm\/SLICE_55/B1 (1206:1370:1535)
+          (1206:1370:1535))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F0 ram2e_ufm\/SLICE_55/A1 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_90/F0 ram2e_ufm\/SLICE_55/C0 (531:639:747)
+          (531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_55/F1 ram2e_ufm\/SLICE_55/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_55/F0 ram2e_ufm\/SLICE_55/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_55/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in 
+          (647:715:784)(647:715:784))
+        (INTERCONNECT ram2e_ufm\/SLICE_55/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI7in 
           (1337:1468:1599)(1337:1468:1599))
-        (INTERCONNECT SLICE_96/F1 SLICE_47/A1 (481:577:673)(481:577:673))
-        (INTERCONNECT SLICE_96/F1 SLICE_69/B1 (767:894:1021)(767:894:1021))
-        (INTERCONNECT SLICE_96/F1 SLICE_96/B0 (513:611:710)(513:611:710))
-        (INTERCONNECT SLICE_47/F1 DQMH_MGIOL/OPOS (1549:1684:1820)(1549:1684:1820))
-        (INTERCONNECT SLICE_80/F1 SLICE_48/D0 (857:950:1044)(857:950:1044))
-        (INTERCONNECT SLICE_80/F1 SLICE_80/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_76/F1 SLICE_48/C0 (538:655:772)(538:655:772))
-        (INTERCONNECT SLICE_76/F1 SLICE_63/A1 (740:864:989)(740:864:989))
-        (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (284:372:461)(284:372:461))
-        (INTERCONNECT SLICE_76/F1 SLICE_112/C1 (807:955:1104)(807:955:1104))
-        (INTERCONNECT SLICE_48/F1 SLICE_48/A0 (733:854:976)(733:854:976))
-        (INTERCONNECT SLICE_48/F1 Vout\[7\]_MGIOL/CE (1635:1790:1945)(1635:1790:1945))
-        (INTERCONNECT SLICE_48/F1 Vout\[6\]_MGIOL/CE (1635:1790:1945)(1635:1790:1945))
-        (INTERCONNECT SLICE_48/F1 Vout\[5\]_MGIOL/CE (2103:2286:2469)(2103:2286:2469))
-        (INTERCONNECT SLICE_48/F1 Vout\[4\]_MGIOL/CE (2103:2286:2469)(2103:2286:2469))
-        (INTERCONNECT SLICE_48/F1 Vout\[3\]_MGIOL/CE (1635:1790:1945)(1635:1790:1945))
-        (INTERCONNECT SLICE_48/F1 Vout\[2\]_MGIOL/CE (2103:2286:2469)(2103:2286:2469))
-        (INTERCONNECT SLICE_48/F1 Vout\[1\]_MGIOL/CE (1635:1790:1945)(1635:1790:1945))
-        (INTERCONNECT SLICE_48/F1 Vout\[0\]_MGIOL/CE (2103:2286:2469)(2103:2286:2469))
-        (INTERCONNECT SLICE_48/F0 SLICE_78/B0 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_93/F0 SLICE_49/D1 (523:573:623)(523:573:623))
-        (INTERCONNECT SLICE_49/F1 SLICE_49/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_49/F0 SLICE_81/C0 (531:639:747)(531:639:747))
-        (INTERCONNECT SLICE_50/F1 SLICE_50/D0 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_89/F1 SLICE_50/B0 (1217:1388:1559)(1217:1388:1559))
-        (INTERCONNECT SLICE_89/F1 SLICE_85/C1 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_89/F1 SLICE_89/A0 (735:859:984)(735:859:984))
-        (INTERCONNECT SLICE_89/F1 SLICE_105/B1 (1951:2185:2420)(1951:2185:2420))
-        (INTERCONNECT SLICE_89/F1 SLICE_105/B0 (1951:2185:2420)(1951:2185:2420))
-        (INTERCONNECT SLICE_106/F0 SLICE_51/C1 (1231:1406:1581)(1231:1406:1581))
-        (INTERCONNECT SLICE_51/F1 SLICE_51/C0 (531:639:747)(531:639:747))
-        (INTERCONNECT SLICE_51/F0 CKE_MGIOL/OPOS (2313:2510:2707)(2313:2510:2707))
-        (INTERCONNECT SLICE_72/F0 SLICE_52/C1 (541:658:775)(541:658:775))
-        (INTERCONNECT SLICE_72/F0 SLICE_52/C0 (541:658:775)(541:658:775))
-        (INTERCONNECT SLICE_72/F0 SLICE_72/A1 (735:859:984)(735:859:984))
-        (INTERCONNECT SLICE_72/F0 SLICE_76/A0 (1435:1626:1818)(1435:1626:1818))
-        (INTERCONNECT SLICE_57/F1 SLICE_52/D0 (266:290:315)(266:290:315))
-        (INTERCONNECT SLICE_52/F1 SLICE_52/B0 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_53/F1 SLICE_53/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_53/F1 SLICE_110/A0 (479:572:665)(479:572:665))
-        (INTERCONNECT SLICE_118/F0 SLICE_54/D0 (795:880:965)(795:880:965))
-        (INTERCONNECT SLICE_118/F0 SLICE_93/D1 (795:880:965)(795:880:965))
-        (INTERCONNECT SLICE_54/F1 SLICE_54/B0 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_54/F0 SLICE_81/A0 (476:566:656)(476:566:656))
-        (INTERCONNECT SLICE_63/F0 SLICE_55/C1 (536:650:764)(536:650:764))
-        (INTERCONNECT SLICE_63/F0 SLICE_63/C1 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_63/F0 SLICE_76/D0 (528:584:640)(528:584:640))
-        (INTERCONNECT SLICE_55/F0 SLICE_55/B1 (765:889:1013)(765:889:1013))
-        (INTERCONNECT SLICE_55/F0 SLICE_71/C1 (882:1034:1187)(882:1034:1187))
-        (INTERCONNECT SLICE_55/F0 SLICE_78/C1 (882:1034:1187)(882:1034:1187))
-        (INTERCONNECT SLICE_55/F1 SLICE_83/C0 (800:939:1079)(800:939:1079))
-        (INTERCONNECT SLICE_56/F1 SLICE_56/D0 (523:579:635)(523:579:635))
-        (INTERCONNECT SLICE_56/F1 SLICE_85/A1 (1552:1749:1947)(1552:1749:1947))
-        (INTERCONNECT SLICE_56/F1 SLICE_88/D0 (1712:1876:2040)(1712:1876:2040))
-        (INTERCONNECT SLICE_56/F1 SLICE_92/A0 (1916:2145:2374)(1916:2145:2374))
-        (INTERCONNECT SLICE_56/F1 SLICE_109/D1 (2414:2646:2879)(2414:2646:2879))
-        (INTERCONNECT SLICE_56/F1 SLICE_109/D0 (2414:2646:2879)(2414:2646:2879))
-        (INTERCONNECT SLICE_73/F0 SLICE_58/D1 (988:1090:1193)(988:1090:1193))
-        (INTERCONNECT SLICE_73/F0 SLICE_68/D1 (988:1090:1193)(988:1090:1193))
-        (INTERCONNECT SLICE_73/F0 SLICE_70/D1 (988:1090:1193)(988:1090:1193))
-        (INTERCONNECT SLICE_73/F0 SLICE_73/B1 (765:889:1013)(765:889:1013))
-        (INTERCONNECT SLICE_73/F0 SLICE_84/B1 (1927:2164:2402)(1927:2164:2402))
-        (INTERCONNECT SLICE_73/F0 SLICE_89/C0 (1733:1954:2175)(1733:1954:2175))
-        (INTERCONNECT SLICE_73/F0 SLICE_114/B1 (1220:1389:1559)(1220:1389:1559))
-        (INTERCONNECT SLICE_73/F0 SLICE_114/B0 (1220:1389:1559)(1220:1389:1559))
-        (INTERCONNECT SLICE_70/F0 SLICE_58/C1 (534:645:756)(534:645:756))
-        (INTERCONNECT SLICE_70/F0 SLICE_70/A1 (479:572:665)(479:572:665))
-        (INTERCONNECT SLICE_58/F0 SLICE_58/B1 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_59/F0 SLICE_59/D1 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_59/F1 DQML_MGIOL/OPOS (1876:2046:2217)(1876:2046:2217))
-        (INTERCONNECT SLICE_88/F1 SLICE_60/D1 (537:603:670)(537:603:670))
-        (INTERCONNECT SLICE_88/F1 SLICE_88/C0 (284:372:461)(284:372:461))
-        (INTERCONNECT SLICE_88/F1 SLICE_105/A1 (737:864:992)(737:864:992))
-        (INTERCONNECT SLICE_88/F1 SLICE_105/D0 (527:589:651)(527:589:651))
-        (INTERCONNECT SLICE_60/F0 SLICE_60/C1 (531:639:747)(531:639:747))
-        (INTERCONNECT SLICE_64/F1 SLICE_60/B1 (771:904:1037)(771:904:1037))
-        (INTERCONNECT SLICE_64/F1 SLICE_64/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_64/F1 SLICE_95/B1 (1037:1204:1372)(1037:1204:1372))
-        (INTERCONNECT SLICE_64/F1 SLICE_97/D0 (529:594:659)(529:594:659))
-        (INTERCONNECT SLICE_61/F0 SLICE_61/C1 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_61/F0 SLICE_88/B0 (767:894:1021)(767:894:1021))
-        (INTERCONNECT SLICE_61/F0 SLICE_114/A1 (738:859:981)(738:859:981))
-        (INTERCONNECT SLICE_61/F1 SLICE_109/C0 (868:1015:1163)(868:1015:1163))
-        (INTERCONNECT SLICE_62/F0 SLICE_62/B1 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_64/F0 SLICE_114/C0 (534:639:744)(534:639:744))
-        (INTERCONNECT SLICE_65/F1 SLICE_65/B0 (765:889:1013)(765:889:1013))
-        (INTERCONNECT SLICE_65/F1 SLICE_84/A1 (736:854:973)(736:854:973))
-        (INTERCONNECT SLICE_65/F0 SLICE_109/B1 (1099:1259:1420)(1099:1259:1420))
-        (INTERCONNECT SLICE_66/F0 SLICE_95/A0 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_76/F0 SLICE_69/D1 (528:587:646)(528:587:646))
-        (INTERCONNECT SLICE_76/F0 SLICE_78/D0 (269:296:324)(269:296:324))
-        (INTERCONNECT SLICE_76/F0 SLICE_115/A0 (1004:1163:1322)(1004:1163:1322))
-        (INTERCONNECT SLICE_69/F0 SLICE_69/C1 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_69/F1 RA\[10\]_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
-        (INTERCONNECT SLICE_75/F0 SLICE_71/D1 (536:594:652)(536:594:652))
-        (INTERCONNECT SLICE_75/F0 SLICE_78/C0 (547:660:773)(547:660:773))
-        (INTERCONNECT SLICE_71/F1 SLICE_115/B0 (772:897:1023)(772:897:1023))
-        (INTERCONNECT SLICE_119/F0 SLICE_72/D1 (1220:1340:1460)(1220:1340:1460))
-        (INTERCONNECT SLICE_116/F1 SLICE_73/D1 (863:956:1049)(863:956:1049))
-        (INTERCONNECT SLICE_116/F1 SLICE_92/B1 (778:904:1030)(778:904:1030))
-        (INTERCONNECT SLICE_73/F1 SLICE_85/A0 (740:863:986)(740:863:986))
-        (INTERCONNECT SLICE_75/F1 SLICE_75/C0 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_75/F1 SLICE_76/B0 (777:908:1040)(777:908:1040))
-        (INTERCONNECT SLICE_75/F1 SLICE_83/B0 (513:611:710)(513:611:710))
-        (INTERCONNECT SLICE_81/F0 SLICE_77/D0 (523:573:623)(523:573:623))
-        (INTERCONNECT SLICE_94/F0 SLICE_77/B0 (1099:1259:1420)(1099:1259:1420))
-        (INTERCONNECT SLICE_82/F0 SLICE_77/A0 (733:848:964)(733:848:964))
-        (INTERCONNECT SLICE_78/F1 SLICE_78/A0 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_78/F0 nCAS_MGIOL/OPOS (1986:2148:2310)(1986:2148:2310))
-        (INTERCONNECT SLICE_79/F1 SLICE_79/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_83/F0 SLICE_79/A0 (1218:1375:1532)(1218:1375:1532))
-        (INTERCONNECT SLICE_83/F0 SLICE_80/D0 (1008:1099:1191)(1008:1099:1191))
-        (INTERCONNECT SLICE_79/F0 nCS_MGIOL/OPOS (1854:2023:2192)(1854:2023:2192))
-        (INTERCONNECT SLICE_80/F0 nRAS_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
-        (INTERCONNECT SLICE_81/F1 SLICE_81/B0 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_91/F0 SLICE_82/D0 (266:290:315)(266:290:315))
-        (INTERCONNECT SLICE_87/F0 SLICE_82/C0 (531:639:747)(531:639:747))
-        (INTERCONNECT SLICE_112/F1 SLICE_83/D0 (523:573:623)(523:573:623))
-        (INTERCONNECT SLICE_83/F1 SLICE_83/A0 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_84/F1 SLICE_84/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_108/F1 SLICE_85/B1 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_92/F0 SLICE_85/D0 (530:587:645)(530:587:645))
-        (INTERCONNECT SLICE_89/F0 SLICE_85/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_85/F1 SLICE_85/B0 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_105/F1 SLICE_86/B0 (765:883:1001)(765:883:1001))
-        (INTERCONNECT SLICE_98/F0 SLICE_87/D1 (530:587:645)(530:587:645))
-        (INTERCONNECT SLICE_87/F1 SLICE_87/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_90/F1 SLICE_90/B0 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_99/F0 SLICE_91/C1 (534:639:744)(534:639:744))
-        (INTERCONNECT SLICE_91/F1 SLICE_91/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_92/F1 SLICE_92/B0 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_93/F1 SLICE_93/B0 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_94/F1 SLICE_94/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_95/F1 SLICE_95/D0 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_96/F0 RA\[8\]_MGIOL/OPOS (1445:1584:1723)(1445:1584:1723))
-        (INTERCONNECT SLICE_97/F1 SLICE_97/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_97/F1 SLICE_116/D0 (967:1066:1166)(967:1066:1166))
-        (INTERCONNECT SLICE_118/F1 SLICE_98/D0 (269:296:324)(269:296:324))
-        (INTERCONNECT SLICE_118/F1 SLICE_99/A0 (733:854:976)(733:854:976))
-        (INTERCONNECT SLICE_101/F1 BA\[1\]_MGIOL/LSR (2375:2573:2771)(2375:2573:2771))
-        (INTERCONNECT SLICE_101/F1 BA\[0\]_MGIOL/LSR (2739:2968:3198)(2739:2968:3198))
-        (INTERCONNECT SLICE_102/F0 BA\[0\]_MGIOL/OPOS (2322:2519:2716)(2322:2519:2716))
-        (INTERCONNECT SLICE_103/F1 RA\[11\]_MGIOL/OPOS (2313:2510:2707)(2313:2510:2707))
-        (INTERCONNECT SLICE_107/F0 BA\[1\]_MGIOL/OPOS (2432:2620:2809)(2432:2620:2809))
-        (INTERCONNECT SLICE_110/F1 RA\[9\]_MGIOL/OPOS (1973:2133:2294)(1973:2133:2294))
-        (INTERCONNECT Ain\[5\]_I/PADDI SLICE_111/B1 (2263:2489:2715)(2263:2489:2715))
-        (INTERCONNECT Ain\[4\]_I/PADDI SLICE_111/C0 (1705:1883:2061)(1705:1883:2061))
-        (INTERCONNECT SLICE_111/F0 RA\[4\]_MGIOL/OPOS (1445:1584:1723)(1445:1584:1723))
-        (INTERCONNECT SLICE_111/F1 RA\[5\]_MGIOL/OPOS (1337:1468:1599)(1337:1468:1599))
-        (INTERCONNECT Ain\[6\]_I/PADDI SLICE_112/B0 (1936:2127:2318)(1936:2127:2318))
-        (INTERCONNECT SLICE_112/F0 RA\[6\]_MGIOL/OPOS (1445:1584:1723)(1445:1584:1723))
-        (INTERCONNECT Ain\[2\]_I/PADDI SLICE_113/C1 (2923:3187:3452)(2923:3187:3452))
-        (INTERCONNECT Ain\[7\]_I/PADDI SLICE_113/C0 (2477:2715:2953)(2477:2715:2953))
-        (INTERCONNECT SLICE_113/F0 RA\[7\]_MGIOL/OPOS (1702:1868:2035)(1702:1868:2035))
-        (INTERCONNECT SLICE_113/F1 RA\[2\]_MGIOL/OPOS (1375:1506:1638)(1375:1506:1638))
-        (INTERCONNECT nWE80_I/PADDI SLICE_115/C1 (2075:2285:2495)(2075:2285:2495))
-        (INTERCONNECT nWE80_I/PADDI SLICE_115/C0 (2075:2285:2495)(2075:2285:2495))
-        (INTERCONNECT SLICE_115/F0 nRWE_MGIOL/OPOS (2313:2510:2707)(2313:2510:2707))
-        (INTERCONNECT SLICE_115/F1 RD\[0\]_I/PADDT (1600:1744:1888)(1600:1744:1888))
-        (INTERCONNECT SLICE_115/F1 RD\[7\]_I/PADDT (2390:2611:2833)(2390:2611:2833))
-        (INTERCONNECT SLICE_115/F1 RD\[6\]_I/PADDT (2390:2611:2833)(2390:2611:2833))
-        (INTERCONNECT SLICE_115/F1 RD\[5\]_I/PADDT (2390:2611:2833)(2390:2611:2833))
-        (INTERCONNECT SLICE_115/F1 RD\[4\]_I/PADDT (2390:2611:2833)(2390:2611:2833))
-        (INTERCONNECT SLICE_115/F1 RD\[3\]_I/PADDT (1600:1744:1888)(1600:1744:1888))
-        (INTERCONNECT SLICE_115/F1 RD\[2\]_I/PADDT (1600:1744:1888)(1600:1744:1888))
-        (INTERCONNECT SLICE_115/F1 RD\[1\]_I/PADDT (1600:1744:1888)(1600:1744:1888))
-        (INTERCONNECT SLICE_117/F0 LED_I/PADDO (1124:1239:1355)(1124:1239:1355))
+        (INTERCONNECT ram2e_ufm\/SLICE_56/F1 ram2e_ufm\/SLICE_56/B0 (762:883:1004)
+          (762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_56/F0 ram2e_ufm\/SLICE_56/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_56/Q0 ram2e_ufm\/SLICE_108/D0 (530:587:645)
+          (530:587:645))
+        (INTERCONNECT ram2e_ufm\/SLICE_57/F0 ram2e_ufm\/SLICE_57/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_69/F0 ram2e_ufm\/SLICE_57/LSR (813:907:1002)
+          (813:907:1002))
+        (INTERCONNECT ram2e_ufm\/SLICE_69/F0 ram2e_ufm\/SLICE_69/B1 (767:894:1021)
+          (767:894:1021))
+        (INTERCONNECT ram2e_ufm\/SLICE_69/F0 ram2e_ufm\/SLICE_105/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_57/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBRSTIin 
+          (1938:2122:2306)(1938:2122:2306))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_58/D1 (544:604:664)
+          (544:604:664))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_58/D0 (544:604:664)
+          (544:604:664))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_103/A0 (738:862:987)
+          (738:862:987))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_109/D0 (544:604:664)
+          (544:604:664))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_114/C0 (539:653:767)
+          (539:653:767))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F0 ram2e_ufm\/SLICE_58/C1 (531:639:747)
+          (531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_58/F1 ram2e_ufm\/SLICE_58/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_126/F1 ram2e_ufm\/SLICE_58/B0 (508:600:693)
+          (508:600:693))
+        (INTERCONNECT ram2e_ufm\/SLICE_58/F0 ram2e_ufm\/SLICE_58/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F0 ram2e_ufm\/SLICE_58/CE (2142:2337:2532)
+          (2142:2337:2532))
+        (INTERCONNECT ram2e_ufm\/SLICE_58/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin 
+          (1081:1188:1296)(1081:1188:1296))
+        (INTERCONNECT ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/OFX0 ram2e_ufm\/SLICE_133/D0 
+          (520:573:626)(520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_94/F0 
+          ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/D1 (530:587:645)(530:587:645))
+        (INTERCONNECT ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/OFX0 
+          ram2e_ufm\/SLICE_82/D0 (1220:1340:1460)(1220:1340:1460))
+        (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/CKE_7\/SLICE_61/C1 (536:650:764)
+          (536:650:764))
+        (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/SLICE_91/A1 (481:577:673)
+          (481:577:673))
+        (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/SLICE_102/D0 (525:584:643)
+          (525:584:643))
+        (INTERCONNECT ram2e_ufm\/SLICE_102/F0 ram2e_ufm\/CKE_7\/SLICE_61/M0 (485:526:568)
+          (485:526:568))
+        (INTERCONNECT ram2e_ufm\/SLICE_62/F0 ram2e_ufm\/SLICE_84/D0 (530:587:645)
+          (530:587:645))
+        (INTERCONNECT ram2e_ufm\/SLICE_65/F0 ram2e_ufm\/SLICE_63/C1 (534:639:744)
+          (534:639:744))
+        (INTERCONNECT ram2e_ufm\/SLICE_133/F0 ram2e_ufm\/SLICE_63/B1 (762:883:1004)
+          (762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_84/F0 ram2e_ufm\/SLICE_63/C0 (531:639:747)
+          (531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_63/F1 ram2e_ufm\/SLICE_63/B0 (762:883:1004)
+          (762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_63/A0 (1225:1391:1557)
+          (1225:1391:1557))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_66/A0 (1006:1165:1324)
+          (1006:1165:1324))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_79/C1 (284:372:461)
+          (284:372:461))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_84/C0 (1026:1181:1337)
+          (1026:1181:1337))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_85/D0 (527:589:651)
+          (527:589:651))
+        (INTERCONNECT ram2e_ufm\/SLICE_64/F1 ram2e_ufm\/SLICE_64/A0 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_100/F0 ram2e_ufm\/SLICE_65/D0 (523:573:623)
+          (523:573:623))
+        (INTERCONNECT ram2e_ufm\/SLICE_65/F1 ram2e_ufm\/SLICE_65/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_108/F0 ram2e_ufm\/SLICE_66/C1 (868:1015:1163)
+          (868:1015:1163))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_66/B1 (1042:1201:1360)
+          (1042:1201:1360))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_70/A1 (1750:1970:2191)
+          (1750:1970:2191))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_80/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_81/A1 (2125:2378:2631)
+          (2125:2378:2631))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_85/A1 (1380:1568:1757)
+          (1380:1568:1757))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_89/A1 (2489:2773:3058)
+          (2489:2773:3058))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_98/C1 (1926:2168:2411)
+          (1926:2168:2411))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_130/B0 (1249:1414:1579)
+          (1249:1414:1579))
+        (INTERCONNECT ram2e_ufm\/SLICE_66/F1 ram2e_ufm\/SLICE_66/B0 (762:883:1004)
+          (762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_67/F1 ram2e_ufm\/SLICE_67/B0 (508:600:693)
+          (508:600:693))
+        (INTERCONNECT ram2e_ufm\/SLICE_67/F0 ram2e_ufm\/SLICE_91/A0 (999:1149:1299)
+          (999:1149:1299))
+        (INTERCONNECT ram2e_ufm\/SLICE_68/F0 ram2e_ufm\/SLICE_68/A1 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_68/F1 ram2e_ufm\/SLICE_86/A0 (740:863:986)
+          (740:863:986))
+        (INTERCONNECT ram2e_ufm\/SLICE_122/F0 ram2e_ufm\/SLICE_69/A1 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_70/D0 (528:584:640)
+          (528:584:640))
+        (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_75/B0 (513:611:710)
+          (513:611:710))
+        (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_88/A0 (738:859:981)
+          (738:859:981))
+        (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_70/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_79/B1 (777:908:1040)
+          (777:908:1040))
+        (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_111/C1 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_71/C1 (286:377:469)
+          (286:377:469))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_91/D0 (973:1081:1190)
+          (973:1081:1190))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_124/C1 (540:660:780)
+          (540:660:780))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_124/D0 (529:594:659)
+          (529:594:659))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_146/B1 (774:904:1034)
+          (774:904:1034))
+        (INTERCONNECT ram2e_ufm\/SLICE_72/F0 ram2e_ufm\/SLICE_72/C1 (534:645:756)
+          (534:645:756))
+        (INTERCONNECT ram2e_ufm\/SLICE_72/F0 ram2e_ufm\/SLICE_129/A1 (733:854:976)
+          (733:854:976))
+        (INTERCONNECT ram2e_ufm\/SLICE_72/F1 BA\[0\]_MGIOL/OPOS (2268:2466:2665)
+          (2268:2466:2665))
+        (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_73/D1 (862:960:1059)
+          (862:960:1059))
+        (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_103/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_109/B0 (777:908:1040)
+          (777:908:1040))
+        (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_73/B1 (767:894:1021)
+          (767:894:1021))
+        (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_97/D1 (525:584:643)
+          (525:584:643))
+        (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_145/C1 (536:650:764)
+          (536:650:764))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_73/A1 (1013:1167:1321)
+          (1013:1167:1321))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_97/B0 (1045:1201:1358)
+          (1045:1201:1358))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_98/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_99/A0 (1383:1569:1755)
+          (1383:1569:1755))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_126/C0 (1548:1755:1962)
+          (1548:1755:1962))
+        (INTERCONNECT ram2e_ufm\/SLICE_135/F0 ram2e_ufm\/SLICE_74/B1 (765:883:1001)
+          (765:883:1001))
+        (INTERCONNECT ram2e_ufm\/SLICE_75/F0 ram2e_ufm\/SLICE_79/A1 (733:848:964)
+          (733:848:964))
+        (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_76/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_81/D0 (530:592:654)
+          (530:592:654))
+        (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_111/C0 (536:650:764)
+          (536:650:764))
+        (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_131/B0 (1469:1669:1869)
+          (1469:1669:1869))
+        (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_76/A0 (1010:1161:1312)
+          (1010:1161:1312))
+        (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_88/B0 (1369:1557:1746)
+          (1369:1557:1746))
+        (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_90/D1 (800:885:971)
+          (800:885:971))
+        (INTERCONNECT ram2e_ufm\/SLICE_76/F0 ram2e_ufm\/SLICE_98/D0 (1220:1340:1460)
+          (1220:1340:1460))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_77/C1 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_80/A0 (797:936:1075)
+          (797:936:1075))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_82/B0 (1665:1871:2078)
+          (1665:1871:2078))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_130/D1 (541:605:669)
+          (541:605:669))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_130/D0 (541:605:669)
+          (541:605:669))
+        (INTERCONNECT ram2e_ufm\/SLICE_101/F0 ram2e_ufm\/SLICE_82/C1 (534:639:744)
+          (534:639:744))
+        (INTERCONNECT ram2e_ufm\/SLICE_133/F1 ram2e_ufm\/SLICE_82/A1 (1104:1258:1413)
+          (1104:1258:1413))
+        (INTERCONNECT ram2e_ufm\/SLICE_83/F0 ram2e_ufm\/SLICE_82/C0 (531:639:747)
+          (531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_82/F1 ram2e_ufm\/SLICE_82/A0 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_83/F1 ram2e_ufm\/SLICE_83/D0 (520:573:626)
+          (520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_87/F0 ram2e_ufm\/SLICE_83/C0 (541:653:766)
+          (541:653:766))
+        (INTERCONNECT ram2e_ufm\/SLICE_110/F0 ram2e_ufm\/SLICE_85/B0 (762:883:1004)
+          (762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_86/F1 ram2e_ufm\/SLICE_86/D0 (531:586:641)
+          (531:586:641))
+        (INTERCONNECT ram2e_ufm\/SLICE_86/F1 ram2e_ufm\/SLICE_109/A0 (741:861:982)
+          (741:861:982))
+        (INTERCONNECT ram2e_ufm\/SLICE_126/F0 ram2e_ufm\/SLICE_86/C0 (531:639:747)
+          (531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_99/F0 ram2e_ufm\/SLICE_86/B0 (772:897:1023)
+          (772:897:1023))
+        (INTERCONNECT ram2e_ufm\/SLICE_88/F1 ram2e_ufm\/SLICE_88/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_88/F1 ram2e_ufm\/SLICE_111/B0 (765:889:1013)
+          (765:889:1013))
+        (INTERCONNECT ram2e_ufm\/SLICE_104/F0 ram2e_ufm\/SLICE_89/D0 (857:949:1042)
+          (857:949:1042))
+        (INTERCONNECT ram2e_ufm\/SLICE_90/F1 ram2e_ufm\/SLICE_90/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_91/F1 ram2e_ufm\/SLICE_91/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_91/F1 ram2e_ufm\/SLICE_92/C0 (537:645:753)
+          (537:645:753))
+        (INTERCONNECT ram2e_ufm\/SLICE_92/F1 ram2e_ufm\/SLICE_92/B0 (511:606:702)
+          (511:606:702))
+        (INTERCONNECT ram2e_ufm\/SLICE_92/F1 ram2e_ufm\/SLICE_102/B0 (765:889:1013)
+          (765:889:1013))
+        (INTERCONNECT ram2e_ufm\/SLICE_93/F1 ram2e_ufm\/SLICE_93/D0 (520:573:626)
+          (520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_100/F1 ram2e_ufm\/SLICE_94/D0 (269:296:324)
+          (269:296:324))
+        (INTERCONNECT ram2e_ufm\/SLICE_100/F1 ram2e_ufm\/SLICE_100/B0 (765:889:1013)
+          (765:889:1013))
+        (INTERCONNECT Ain\[4\]_I/PADDI ram2e_ufm\/SLICE_95/B0 (2382:2599:2817)
+          (2382:2599:2817))
+        (INTERCONNECT Ain\[6\]_I/PADDI ram2e_ufm\/SLICE_96/B0 (1829:2016:2203)
+          (1829:2016:2203))
+        (INTERCONNECT ram2e_ufm\/SLICE_97/F1 ram2e_ufm\/SLICE_97/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_125/F1 ram2e_ufm\/SLICE_99/D0 (523:573:623)
+          (523:573:623))
+        (INTERCONNECT ram2e_ufm\/SLICE_99/F1 ram2e_ufm\/SLICE_99/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_115/F0 ram2e_ufm\/SLICE_102/C0 (534:639:744)
+          (534:639:744))
+        (INTERCONNECT ram2e_ufm\/SLICE_128/F0 ram2e_ufm\/SLICE_103/D0 (857:949:1042)
+          (857:949:1042))
+        (INTERCONNECT ram2e_ufm\/SLICE_123/F1 ram2e_ufm\/SLICE_103/B0 (772:897:1023)
+          (772:897:1023))
+        (INTERCONNECT ram2e_ufm\/SLICE_104/F1 ram2e_ufm\/SLICE_104/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_122/F1 ram2e_ufm\/SLICE_105/D1 (520:573:626)
+          (520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_107/F1 ram2e_ufm\/SLICE_107/A0 (733:854:976)
+          (733:854:976))
+        (INTERCONNECT ram2e_ufm\/SLICE_107/F1 ram2e_ufm\/SLICE_134/D0 (523:579:635)
+          (523:579:635))
+        (INTERCONNECT ram2e_ufm\/SLICE_134/F1 ram2e_ufm\/SLICE_108/C1 (531:639:747)
+          (531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_111/F0 ram2e_ufm\/SLICE_111/A1 (476:566:656)
+          (476:566:656))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_112/B0 (1960:2153:2347)
+          (1960:2153:2347))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_113/D1 (2045:2205:2366)
+          (2045:2205:2366))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_115/B0 (2699:2956:3214)
+          (2699:2956:3214))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_135/B0 (2335:2561:2787)
+          (2335:2561:2787))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_136/A1 (3150:3439:3729)
+          (3150:3439:3729))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_136/A0 (3150:3439:3729)
+          (3150:3439:3729))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_137/A1 (3520:3841:4163)
+          (3520:3841:4163))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_137/A0 (3520:3841:4163)
+          (3520:3841:4163))
+        (INTERCONNECT ram2e_ufm\/SLICE_114/F1 ram2e_ufm\/SLICE_114/A0 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_116/F0 ram2e_ufm\/SLICE_116/A1 (476:566:656)
+          (476:566:656))
+        (INTERCONNECT ram2e_ufm\/SLICE_117/F0 BA\[1\]_MGIOL/CE (1617:1766:1916)
+          (1617:1766:1916))
+        (INTERCONNECT ram2e_ufm\/SLICE_117/F0 BA\[0\]_MGIOL/CE (1617:1766:1916)
+          (1617:1766:1916))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQMH_MGIOL/CE (1617:1766:1916)
+          (1617:1766:1916))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQML_MGIOL/CE (1617:1766:1916)
+          (1617:1766:1916))
+        (INTERCONNECT ram2e_ufm\/SLICE_120/F0 DQML_MGIOL/OPOS (1549:1684:1820)
+          (1549:1684:1820))
+        (INTERCONNECT ram2e_ufm\/SLICE_120/F1 DQMH_MGIOL/OPOS (1867:2037:2208)
+          (1867:2037:2208))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[7\]_MGIOL/CE (1550:1706:1862)
+          (1550:1706:1862))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[6\]_MGIOL/CE (1550:1706:1862)
+          (1550:1706:1862))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[5\]_MGIOL/CE (2402:2624:2847)
+          (2402:2624:2847))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[4\]_MGIOL/CE (2402:2624:2847)
+          (2402:2624:2847))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[3\]_MGIOL/CE (1550:1706:1862)
+          (1550:1706:1862))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[2\]_MGIOL/CE (2402:2624:2847)
+          (2402:2624:2847))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[1\]_MGIOL/CE (1550:1706:1862)
+          (1550:1706:1862))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[0\]_MGIOL/CE (2402:2624:2847)
+          (2402:2624:2847))
+        (INTERCONNECT ram2e_ufm\/SLICE_129/F1 BA\[1\]_MGIOL/OPOS (2322:2519:2716)
+          (2322:2519:2716))
+        (INTERCONNECT Ain\[0\]_I/PADDI ram2e_ufm\/SLICE_132/C1 (2031:2242:2454)
+          (2031:2242:2454))
+        (INTERCONNECT Ain\[7\]_I/PADDI ram2e_ufm\/SLICE_132/C0 (2031:2242:2454)
+          (2031:2242:2454))
+        (INTERCONNECT ram2e_ufm\/SLICE_136/F0 nDOE_I/PADDO (1902:2078:2254)
+          (1902:2078:2254))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F0 LED_I/PADDO (1300:1433:1567)(1300:1433:1567))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[0\]_I/PADDT (688:769:851)(688:769:851))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[7\]_I/PADDT (1491:1644:1798)
+          (1491:1644:1798))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[6\]_I/PADDT (1491:1644:1798)
+          (1491:1644:1798))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[5\]_I/PADDT (1491:1644:1798)
+          (1491:1644:1798))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[4\]_I/PADDT (1491:1644:1798)
+          (1491:1644:1798))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[3\]_I/PADDT (947:1055:1164)
+          (947:1055:1164))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[2\]_I/PADDT (947:1055:1164)
+          (947:1055:1164))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[1\]_I/PADDT (688:769:851)(688:769:851))
+        (INTERCONNECT PHI1_I/PADDI SLICE_139/B1 (2525:2775:3025)(2525:2775:3025))
+        (INTERCONNECT PHI1_I/PADDI SLICE_139/A0 (2166:2378:2591)(2166:2378:2591))
+        (INTERCONNECT PHI1_I/PADDI PHI1_MGIOL/DI (544:554:565)(544:554:565))
+        (INTERCONNECT PHI1_MGIOL/IN SLICE_139/C0 (1174:1343:1512)(1174:1343:1512))
+        (INTERCONNECT SLICE_139/F1 nVOE_I/PADDO (1534:1723:1913)(1534:1723:1913))
+        (INTERCONNECT ram2e_ufm\/SLICE_141/F0 RD\[3\]_I/PADDO (936:1038:1140)
+          (936:1038:1140))
+        (INTERCONNECT ram2e_ufm\/SLICE_141/F1 RD\[0\]_I/PADDO (1300:1433:1567)
+          (1300:1433:1567))
+        (INTERCONNECT ram2e_ufm\/SLICE_142/F0 RD\[4\]_I/PADDO (1802:1982:2163)
+          (1802:1982:2163))
+        (INTERCONNECT ram2e_ufm\/SLICE_143/F0 RD\[7\]_I/PADDO (1367:1504:1642)
+          (1367:1504:1642))
+        (INTERCONNECT ram2e_ufm\/SLICE_143/F1 RD\[1\]_I/PADDO (936:1038:1140)
+          (936:1038:1140))
+        (INTERCONNECT ram2e_ufm\/SLICE_144/F0 RD\[6\]_I/PADDO (1557:1697:1838)
+          (1557:1697:1838))
+        (INTERCONNECT ram2e_ufm\/SLICE_144/F1 RD\[2\]_I/PADDO (1111:1225:1339)
+          (1111:1225:1339))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F0 RD\[5\]_I/PADDO (1839:2016:2193)
+          (1839:2016:2193))
         (INTERCONNECT RD\[0\]_I/PADDI Vout\[0\]_MGIOL/OPOS (2735:2961:3187)
           (2735:2961:3187))
-        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_MGIOL/OPOS (1970:2136:2303)
-          (1970:2136:2303))
-        (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (30:36:43)(30:36:43))
-        (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (30:36:43)(30:36:43))
+        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2000:2173:2346)(2000:2173:2346))
         (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (3308:3554:3800)
           (3308:3554:3800))
-        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_MGIOL/OPOS (2416:2609:2802)
-          (2416:2609:2802))
+        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (2446:2645:2845)(2446:2645:2845))
         (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (3321:3568:3816)
           (3321:3568:3816))
-        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_MGIOL/OPOS (3380:3625:3871)
-          (3380:3625:3871))
-        (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (2885:3105:3325)
-          (2885:3105:3325))
-        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_MGIOL/OPOS (3249:3500:3752)
-          (3249:3500:3752))
+        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (3437:3693:3950)(3437:3693:3950))
+        (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (2884:3105:3326)
+          (2884:3105:3326))
+        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (2910:3136:3363)(2910:3136:3363))
         (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (2876:3096:3316)
           (2876:3096:3316))
-        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_MGIOL/OPOS (3604:3887:4170)
-          (3604:3887:4170))
+        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (3652:3942:4232)(3652:3942:4232))
         (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (2884:3105:3326)
           (2884:3105:3326))
-        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_MGIOL/OPOS (1970:2136:2303)
-          (1970:2136:2303))
+        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2000:2173:2346)(2000:2173:2346))
         (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (2467:2657:2847)
           (2467:2657:2847))
-        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_MGIOL/OPOS (3195:3448:3701)
-          (3195:3448:3701))
+        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (3206:3469:3733)(3206:3469:3733))
         (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (2794:3032:3271)
           (2794:3032:3271))
-        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_MGIOL/OPOS (1894:2047:2201)
-          (1894:2047:2201))
-        (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[9\]_MGIOL/IOLDO RA\[9\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[8\]_MGIOL/IOLDO RA\[8\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[7\]_MGIOL/IOLDO RA\[7\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[6\]_MGIOL/IOLDO RA\[6\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[5\]_MGIOL/IOLDO RA\[5\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[4\]_MGIOL/IOLDO RA\[4\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[2\]_MGIOL/IOLDO RA\[2\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[1\]_MGIOL/IOLDO RA\[1\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (1924:2084:2244)(1924:2084:2244))
+        (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (30:36:43)(30:36:43))
+        (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (30:36:43)(30:36:43))
+        (INTERCONNECT RAout\[11\]_MGIOL/IOLDO RAout\[11\]_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT RAout\[10\]_MGIOL/IOLDO RAout\[10\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[9\]_MGIOL/IOLDO RAout\[9\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[8\]_MGIOL/IOLDO RAout\[8\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[7\]_MGIOL/IOLDO RAout\[7\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[6\]_MGIOL/IOLDO RAout\[6\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[5\]_MGIOL/IOLDO RAout\[5\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[4\]_MGIOL/IOLDO RAout\[4\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[3\]_MGIOL/IOLDO RAout\[3\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[2\]_MGIOL/IOLDO RAout\[2\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[1\]_MGIOL/IOLDO RAout\[1\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[0\]_MGIOL/IOLDO RAout\[0\]_I/IOLDO (25:77:129)(25:77:129))
         (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (9:36:63)(9:36:63))
         (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT nCAS_MGIOL/IOLDO nCAS_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT nRAS_MGIOL/IOLDO nRAS_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT nCS_MGIOL/IOLDO nCS_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT CKE_MGIOL/IOLDO CKE_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT nRWEout_MGIOL/IOLDO nRWEout_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT nCASout_MGIOL/IOLDO nCASout_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT nRASout_MGIOL/IOLDO nRASout_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT CKEout_MGIOL/IOLDO CKEout_I/IOLDO (9:36:63)(9:36:63))
         (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (7:62:118)(7:62:118))
         (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (7:62:118)(7:62:118))
         (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (11:21:32)(11:21:32))
@@ -4932,14 +5979,6 @@
         (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (11:21:32)(11:21:32))
         (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (7:62:118)(7:62:118))
         (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (11:21:32)(11:21:32))
-        (INTERCONNECT Dout\[7\]_MGIOL/IOLDO Dout\[7\]_I/IOLDO (30:36:43)(30:36:43))
-        (INTERCONNECT Dout\[6\]_MGIOL/IOLDO Dout\[6\]_I/IOLDO (30:36:43)(30:36:43))
-        (INTERCONNECT Dout\[5\]_MGIOL/IOLDO Dout\[5\]_I/IOLDO (11:21:32)(11:21:32))
-        (INTERCONNECT Dout\[4\]_MGIOL/IOLDO Dout\[4\]_I/IOLDO (11:21:32)(11:21:32))
-        (INTERCONNECT Dout\[3\]_MGIOL/IOLDO Dout\[3\]_I/IOLDO (30:36:43)(30:36:43))
-        (INTERCONNECT Dout\[2\]_MGIOL/IOLDO Dout\[2\]_I/IOLDO (11:21:32)(11:21:32))
-        (INTERCONNECT Dout\[1\]_MGIOL/IOLDO Dout\[1\]_I/IOLDO (30:36:43)(30:36:43))
-        (INTERCONNECT Dout\[0\]_MGIOL/IOLDO Dout\[0\]_I/IOLDO (30:36:43)(30:36:43))
       )
     )
   )
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo
index f5ba39f..4821083 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo
@@ -2,8 +2,8 @@
 // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
 
 // ldbanno -n Verilog -o RAM2E_LCMXO2_1200HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd 
-// Netlist created on Thu Sep 21 05:34:46 2023
-// Netlist written on Thu Sep 21 05:35:16 2023
+// Netlist created on Thu Dec 28 23:09:57 2023
+// Netlist written on Thu Dec 28 23:10:24 2023
 // Design is for device LCMXO2-1200HC
 // Design is for package TQFP100
 // Design is for performance grade 4
@@ -11,7 +11,8 @@
 `timescale 1 ns / 1 ps
 
 module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, 
-               Vout, nVOE, CKE, nCS, nRAS, nCAS, nRWE, BA, RA, RD, DQML, DQMH );
+               Vout, nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout, BA, 
+               RAout, DQML, DQMH, RD );
   input  C14M, PHI1, nWE, nWE80, nEN80, nC07X;
   input  [7:0] Ain;
   input  [7:0] Din;
@@ -19,9 +20,9 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   output [7:0] Dout;
   output nDOE;
   output [7:0] Vout;
-  output nVOE, CKE, nCS, nRAS, nCAS, nRWE;
+  output nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout;
   output [1:0] BA;
-  output [11:0] RA;
+  output [11:0] RAout;
   output DQML, DQMH;
   inout  [7:0] RD;
   wire   \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , 
@@ -30,77 +31,140 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
          \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , 
          \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , 
          \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , 
-         \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , Ready, 
-         PHI1reg, PHI1_c, RWSel, CO0_1, \CmdTout_3[0] , N_576_i, S_1, 
-         \S_RNII9DO1_0[1] , \CS[0] , N_461, \CS[1] , N_511_i, N_504_i, 
-         un1_CS_0_sqmuxa_i, N_637, \CS[2] , N_510_i, \Din_c[0] , \Din_c[2] , 
-         \Din_c[3] , CmdBitbangMXO2_4_u_0_0_a2_0_1, N_643, CmdBitbangMXO2, 
-         CmdBitbangMXO2_4, \Din_c[5] , \Din_c[7] , N_629, CmdExecMXO2, 
-         CmdExecMXO2_4, N_466, \Din_c[4] , \Din_c[1] , N_478, 
-         CmdLEDGet_4_u_0_0_a2_0_2, N_476, CmdLEDGet, CmdLEDGet_4, N_626, N_605, 
-         CmdLEDSet, CmdLEDSet_4, CmdRWMaskSet, CmdRWMaskSet_4, N_401, 
-         CmdSetRWBankFFLED, CmdSetRWBankFFLED_4, N_474, 
-         CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0, CmdSetRWBankFFMXO2, 
-         CmdSetRWBankFFMXO2_4, \CmdTout[1] , \CmdTout[2] , N_556_i, N_555_i, 
-         \S[2] , \S[1] , \S[0] , \S[3] , N_6_i, DOEEN, \Ain_c[1] , 
-         \wb_dato[0] , LEDEN_RNO, \un1_LEDEN_0_sqmuxa_1_i_0[0] , LEDEN, 
-         N_558_i, \Ain_c[3] , \Ain_c[0] , N_552_i, N_127_i, \S_RNII9DO1_1[1] , 
-         \RA_c[0] , \RA_c[3] , \RWMask[1] , N_591, \RWMask[0] , \RWBank_5[1] , 
-         \RWBank_5[0] , LEDEN13, \RWBank[0] , \RWBank[1] , \RWMask[3] , 
-         \RWMask[2] , \RWBank_5[3] , \RWBank_5[2] , \RWBank[2] , \RWBank[3] , 
-         \RWMask[5] , \RWMask[4] , \RWBank_5[5] , \RWBank_5[4] , \RWBank[4] , 
-         \RWBank[5] , \RWMask[7] , \Din_c[6] , \RWMask[6] , \RWBank_5[7] , 
-         \RWBank_5[6] , \RWBank[6] , \RWBank[7] , \wb_dato[1] , N_291_i, 
-         N_292_i, N_88, \wb_dato[3] , \wb_dato[2] , N_289_i, N_290_i, 
-         \wb_dato[5] , \wb_dato[4] , N_287_i, N_288_i, \wb_dato[7] , 
-         \wb_dato[6] , N_285, N_286_i, nEN80_c, nWE_c, nC07X_c, RWSel_2, nCS61, 
-         nDOE_c, N_489, Ready_0_sqmuxa_0_a2_6_a2_4, Ready_0_sqmuxa, N_876_0, 
-         N_572, wb_reqc_1, N_575, \S_s_0_1[0] , N_133_i, \S_s_0[0] , N_129_i, 
-         N_131_i, N_388, wb_adr_7_5_214_0_1, N_642, \wb_adr_7_0_4[0] , N_376, 
-         \wb_adr_RNO[1] , \wb_adr_7[0] , \un1_wb_adr_0_sqmuxa_2_i[0] , 
-         \wb_adr[0] , \wb_adr[1] , N_41_i, N_43_i, \wb_adr[2] , \wb_adr[3] , 
-         N_295, N_294, \wb_adr[4] , \wb_adr[5] , N_39_i, N_296, \wb_adr[6] , 
-         \wb_adr[7] , N_300, wb_ack, N_395, wb_cyc_stb_RNO, N_104, wb_cyc_stb, 
-         \wb_dati_7_0_0[1] , N_627, N_336, N_621, \wb_dati_7_0_a2_1[0] , N_484, 
-         \wb_dati_7[1] , \wb_dati_7[0] , \wb_dati[0] , \wb_dati[1] , 
-         \wb_dati_7_0_2[3] , \wb_dati_7_0_0[3] , \wb_dati_7_0_o2_0[2] , N_345, 
-         \wb_dati_7[3] , \wb_dati_7[2] , \wb_dati[2] , \wb_dati[3] , N_346, 
-         N_349, \wb_dati_7_0_0[4] , \wb_dati_7[5] , \wb_dati_7[4] , 
-         \wb_dati[4] , \wb_dati[5] , \wb_dati_7_0_RNO[7] , \wb_dati_7_0_0[7] , 
-         N_422, N_424, \wb_dati_7_0_1[6] , \wb_dati_7[7] , \wb_dati_7[6] , 
-         \wb_dati[6] , \wb_dati[7] , N_397, wb_reqc_i, wb_adr_0_sqmuxa_i, 
-         wb_req, wb_rst8, \S_RNII9DO1[1] , wb_rst, N_586, wb_we_7_iv_0_0_0_1, 
-         N_584, N_475, wb_we_RNO, \un1_wb_cyc_stb_0_sqmuxa_1_i[0] , wb_we, 
-         N_255, N_358_i, N_635, N_254, Vout3, nCAS_s_i_tz_0, 
-         un1_CS_0_sqmuxa_0_0_a2_1_4, N_327, un1_CS_0_sqmuxa_0_0_0, 
-         \wb_dati_7_0_a2_0_1[7] , N_579, CKE_6_iv_i_a2_0, CKE_6_iv_i_0_1, 
-         CKE_6_iv_i_0, N_449, N_364, N_365, \un1_wb_adr_0_sqmuxa_2_1[0] , 
-         N_616, N_623, N_279, N_264, N_633, N_570, N_452, N_455, N_644, 
-         \wb_dati_7_0_a2_2_1[3] , DQML_s_i_a2_0, N_28_i, N_569, 
-         wb_adr_7_5_214_a2_2_0, N_577, N_634, \wb_dati_7_0_a2_2_0[1] , N_265_i, 
-         \un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] , \wb_dati_7_0_a2_0[6] , 
-         \wb_dati_7_0_a2_4_0[7] , N_393, nCAS_0_sqmuxa, N_639, \RA_42[10] , 
-         N_640, un1_nCS61_1_i, Ready_0_sqmuxa_0_a2_6_a2_2, N_562, N_377, N_628, 
-         un1_CS_0_sqmuxa_0_0_2, un1_CS_0_sqmuxa_0_0_a2_3_2, 
-         un1_CS_0_sqmuxa_0_0_3, N_567, N_561_i, nCS_6_u_i_0, N_559_1, N_559_i, 
-         nRAS_2_iv_i, un1_CS_0_sqmuxa_0_0_a2_1, N_328, N_330, N_429, 
-         nCS_6_u_i_a2_1, N_351, \wb_adr_7_0_a2_5_0[0] , \wb_adr_7_0_0[0] , 
-         N_378, \wb_adr_7_0_1[0] , \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] , 
-         un1_CS_0_sqmuxa_0_0_a2_4_2, un1_CS_0_sqmuxa_0_0_a2_4_4, N_565, 
-         un1_CS_0_sqmuxa_0_0_a2_2_2, un1_CS_0_sqmuxa_0_0_a2_2_4, 
-         \wb_adr_7_0_a2_0[0] , un1_CS_0_sqmuxa_0_0_a2_1_2, 
-         un1_CS_0_sqmuxa_0_0_a2_3_0, N_394, N_49_i, N_456, N_477, N_566_i, 
-         \BA_4[0] , \RA_42[11] , \BA_4[1] , N_59_i, \Ain_c[5] , \Ain_c[4] , 
-         N_551_i, \RA_42_3_0[5] , \Ain_c[6] , N_550_i, \Ain_c[2] , \Ain_c[7] , 
-         N_549_i, N_553_i, nWE80_c, nRWE_r_0, RDOE_i, LED_c, \RD_in[0] , 
-         DQMH_c, DQML_c, \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , 
-         \RD_in[3] , \RD_in[2] , \RD_in[1] , \RA_c[11] , \RA_c[10] , \RA_c[9] , 
-         \RA_c[8] , \RA_c[7] , \RA_c[6] , \RA_c[5] , \RA_c[4] , \RA_c[2] , 
-         \RA_c[1] , \BA_c[1] , \BA_c[0] , nRWE_c, nCAS_c, nRAS_c, nCS_c, CKE_c, 
+         \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , 
+         \S[1] , \S[0] , N_551, \ram2e_ufm/CKE_7 , CKE_7_RNIS77M1, CKE, 
+         \ram2e_ufm/wb_adr_0_sqmuxa_1_i , RWSel, CO0_0, \CmdTout_3[0] , 
+         N_185_i, GND, \RC[2] , CO0_1, \RC[1] , N_360_i, RC12, 
+         \ram2e_ufm/N_821 , \ram2e_ufm/SUM1_0_0 , \ram2e_ufm/SUM0_i_a3_4_0 , 
+         \ram2e_ufm/N_886 , \ram2e_ufm/N_215 , \CS[1] , \ram2e_ufm/SUM0_i_4 , 
+         \CS[2] , CmdExecMXO2_3_0_a3_0_RNI6S1P8, N_547_i, un1_CS_0_sqmuxa_i, 
+         \CS[0] , \ram2e_ufm/N_234 , CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514, 
+         \Din_c[3] , \Din_c[5] , \ram2e_ufm/N_800 , 
+         \ram2e_ufm/CmdLEDGet_3_0_a3_1 , \Din_c[1] , \ram2e_ufm/N_847 , 
+         \Din_c[2] , CmdLEDGet_3, N_187_i, CmdLEDGet, \Din_c[7] , 
+         \ram2e_ufm/N_883 , \Din_c[4] , CmdLEDSet_3, CmdLEDSet, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 , CmdRWMaskSet_3, CmdRWMaskSet, 
+         \ram2e_ufm/N_850 , \Din_c[0] , CmdSetRWBankFFLED_4, CmdSetRWBankFFLED, 
+         \CmdTout[1] , \CmdTout[2] , N_369_i, N_368_i, \RA[1] , 
+         \ram2e_ufm/N_186 , \S[3] , N_1080_0, \ram2e_ufm/N_660 , DOEEN, 
+         \ram2e_ufm/N_193 , \ram2e_ufm/N_182 , \Ain_c[1] , \ram2e_ufm/N_659 , 
+         \ram2e_ufm/RA_35_0_0_1[0] , \ram2e_ufm/N_801 , \ram2e_ufm/N_684 , 
+         N_223, \RA_35[0] , N_126, \RA[0] , \ram2e_ufm/RA_35_0_0_0[3] , 
+         \ram2e_ufm/N_680 , \ram2e_ufm/N_679 , \Ain_c[2] , \RA_35[3] , 
+         \RA_35[2] , \RA[2] , \RA[3] , \Ain_c[5] , \ram2e_ufm/RA_35_0_0_0[5] , 
+         \ram2e_ufm/N_621 , \ram2e_ufm/RA_35_0_0_0[4] , \RA_35[5] , \RA_35[4] , 
+         \RA[4] , \RA[5] , \ram2e_ufm/RA_35_0_0_0_0[7] , 
+         \ram2e_ufm/RA_35_0_0_0_0[6] , \RA_35[7] , \RA_35[6] , \RA[6] , 
+         \RA[7] , \ram2e_ufm/N_242 , \ram2e_ufm/RA_35_0_0_0[9] , \RA[9] , 
+         \ram2e_ufm/N_699 , \ram2e_ufm/N_221 , \ram2e_ufm/N_698 , \RA[8] , 
+         \RA_35[9] , un2_S_2_i_0_0_o3_RNIHFHN3, \ram2e_ufm/N_845 , \RWBank[4] , 
+         \RA[11] , \ram2e_ufm/N_628 , \ram2e_ufm/N_627 , \ram2e_ufm/N_624 , 
+         \ram2e_ufm/RA_35_2_0_0[10] , \RA_35[11] , \RA_35[10] , \RA[10] , 
+         \RC_3[2] , \RC_3[1] , \ram2e_ufm/N_188 , \ram2e_ufm/RWMask[1] , 
+         \ram2e_ufm/RWMask[0] , \RWBank_3[1] , \RWBank_3[0] , \RWBank[0] , 
+         \RWBank[1] , \ram2e_ufm/RWMask[3] , \ram2e_ufm/RWMask[2] , 
+         \RWBank_3[3] , \RWBank_3[2] , \RWBank[2] , \RWBank[3] , 
+         \ram2e_ufm/RWMask[5] , \ram2e_ufm/RWMask[4] , \RWBank_3[5] , 
+         \RWBank_3[4] , \RWBank[5] , \ram2e_ufm/RWMask[7] , 
+         \ram2e_ufm/RWMask[6] , \Din_c[6] , \RWBank_3[7] , \RWBank_3[6] , 
+         \RWBank[6] , \RWBank[7] , \Ain_c[3] , nC07X_c, nWE_c, RWSel_2, 
+         un9_VOEEN_0_a2_0_a3_0_a3, \ram2e_ufm/Ready3_0_a3_4 , 
+         \ram2e_ufm/N_885 , \ram2e_ufm/Ready3_0_a3_5 , 
+         \ram2e_ufm/Ready3_0_a3_3 , Ready3, Ready, N_1026_0, S_1, 
+         \ram2e_ufm/N_194 , \ram2e_ufm/N_271 , \ram2e_ufm/S_r_i_0_o2[1] , 
+         \ram2e_ufm/N_643 , N_362_i, \S_s_0_0[0] , \S[2] , N_372_i, N_361_i, 
+         N_1078_0, VOEEN, BA_0_sqmuxa, \ram2e_ufm/N_804 , \ram2e_ufm/N_285_i , 
+         \ram2e_ufm/N_872 , \ram2e_ufm/N_641 , \ram2e_ufm/N_640 , N_370_i, 
+         nCAS, \ram2e_ufm/N_615 , \ram2e_ufm/N_617 , \ram2e_ufm/N_616 , 
+         \ram2e_ufm/nRAS_s_i_0_0 , N_358_i, nRAS, \ram2e_ufm/N_226 , 
+         \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] , \ram2e_ufm/N_866 , N_359_i, nRWE, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 , 
+         \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 , \ram2e_ufm/CmdBitbangMXO2_3 , 
+         \ram2e_ufm/CmdBitbangMXO2 , \ram2e_ufm/N_851 , 
+         \ram2e_ufm/CmdExecMXO2_3 , \ram2e_ufm/CmdExecMXO2 , 
+         \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 , \ram2e_ufm/N_190 , 
+         \ram2e_ufm/CmdSetRWBankFFChip_3 , \ram2e_ufm/CmdSetRWBankFFChip , 
+         \ram2e_ufm/wb_dato[0] , \ram2e_ufm/N_295 , 
+         \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] , \ram2e_ufm/LEDEN , 
+         \ram2e_ufm/N_212 , \ram2e_ufm/wb_dato[1] , \ram2e_ufm/N_307_i , 
+         \ram2e_ufm/N_309_i , \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] , 
+         \ram2e_ufm/wb_dato[3] , \ram2e_ufm/wb_dato[2] , \ram2e_ufm/N_302_i , 
+         \ram2e_ufm/N_304_i , \ram2e_ufm/wb_dato[5] , \ram2e_ufm/wb_dato[4] , 
+         \ram2e_ufm/N_301_i , \ram2e_ufm/N_310_i , \ram2e_ufm/wb_dato[7] , 
+         \ram2e_ufm/wb_dato[6] , \ram2e_ufm/N_296 , \ram2e_ufm/N_300_i , 
+         \ram2e_ufm/wb_adr_7_5_41_0_1 , \ram2e_ufm/N_768 , 
+         \ram2e_ufm/wb_adr_7_i_i_4[0] , \ram2e_ufm/wb_adr_7_i_i_5[0] , 
+         \ram2e_ufm/N_793 , \ram2e_ufm/wb_adr_RNO[1] , 
+         \ram2e_ufm/wb_adr_7_i_i[0] , \ram2e_ufm/CmdBitbangMXO2_RNINSM62 , 
+         \ram2e_ufm/wb_adr[0] , \ram2e_ufm/wb_adr[1] , \ram2e_ufm/N_268_i , 
+         \ram2e_ufm/N_80_i , \ram2e_ufm/wb_adr[2] , \ram2e_ufm/wb_adr[3] , 
+         \ram2e_ufm/N_290 , \ram2e_ufm/N_294 , \ram2e_ufm/wb_adr[4] , 
+         \ram2e_ufm/wb_adr[5] , \ram2e_ufm/N_267_i , \ram2e_ufm/N_284 , 
+         \ram2e_ufm/wb_adr[6] , \ram2e_ufm/wb_adr[7] , \ram2e_ufm/wb_ack , 
+         \ram2e_ufm/N_336 , \ram2e_ufm/N_687 , \ram2e_ufm/wb_cyc_stb_RNO , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] , 
+         \ram2e_ufm/wb_cyc_stb , \ram2e_ufm/wb_dati_7_0_0_0[1] , 
+         \ram2e_ufm/N_611 , \ram2e_ufm/N_849 , \ram2e_ufm/N_856 , 
+         \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] , \ram2e_ufm/wb_dati_7[1] , 
+         \ram2e_ufm/wb_dati_7[0] , \ram2e_ufm/wb_dati[0] , 
+         \ram2e_ufm/wb_dati[1] , \ram2e_ufm/N_783 , 
+         \ram2e_ufm/wb_dati_7_0_0_0_0[3] , \ram2e_ufm/wb_dati_7_0_0_o3_0[2] , 
+         \ram2e_ufm/N_760 , \ram2e_ufm/wb_dati_7[3] , \ram2e_ufm/wb_dati_7[2] , 
+         \ram2e_ufm/wb_dati[2] , \ram2e_ufm/wb_dati[3] , \ram2e_ufm/N_763 , 
+         \ram2e_ufm/N_757 , \ram2e_ufm/wb_dati_7_0_0_0[4] , 
+         \ram2e_ufm/wb_dati_7[5] , \ram2e_ufm/wb_dati_7[4] , 
+         \ram2e_ufm/wb_dati[4] , \ram2e_ufm/wb_dati[5] , 
+         \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] , \ram2e_ufm/N_604 , 
+         \ram2e_ufm/N_602 , \ram2e_ufm/wb_dati_7_0_0_0_0[7] , 
+         \ram2e_ufm/wb_dati_7_0_0_0[6] , \ram2e_ufm/wb_dati_7[7] , 
+         \ram2e_ufm/wb_dati_7[6] , \ram2e_ufm/wb_dati[6] , 
+         \ram2e_ufm/wb_dati[7] , \ram2e_ufm/wb_reqc_1 , \ram2e_ufm/wb_reqc_i , 
+         \ram2e_ufm/wb_req , \ram2e_ufm/wb_rst8 , \ram2e_ufm/wb_rst16_i , 
+         \ram2e_ufm/wb_rst , \ram2e_ufm/N_799 , 
+         \ram2e_ufm/wb_we_7_iv_0_0_3_0_0 , \ram2e_ufm/wb_we_7_iv_0_0_3_0_1 , 
+         \ram2e_ufm/N_208 , \ram2e_ufm/wb_we_RNO , \ram2e_ufm/wb_we_RNO_0 , 
+         \ram2e_ufm/wb_we , \ram2e_ufm/N_338 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 , \ram2e_ufm/N_817 , 
+         \ram2e_ufm/CKE_7_sm0 , \ram2e_ufm/N_720_tz , \ram2e_ufm/SUM0_i_0 , 
+         \ram2e_ufm/N_350 , \ram2e_ufm/SUM0_i_3 , \ram2e_ufm/SUM0_i_1 , 
+         \ram2e_ufm/N_187 , \ram2e_ufm/N_755 , \ram2e_ufm/N_345 , 
+         \ram2e_ufm/N_735 , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] , 
+         \ram2e_ufm/N_777 , \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] , 
+         \ram2e_ufm/N_250 , \ram2e_ufm/N_256 , \ram2e_ufm/wb_adr_7_i_i_3_1[0] , 
+         \ram2e_ufm/wb_adr_7_i_i_3[0] , \ram2e_ufm/N_254 , \ram2e_ufm/N_876 , 
+         \ram2e_ufm/N_807 , \ram2e_ufm/N_784 , \ram2e_ufm/N_560 , \BA_4[0] , 
+         \ram2e_ufm/N_184 , \ram2e_ufm/N_873 , \ram2e_ufm/N_781 , 
+         \ram2e_ufm/N_625 , \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] , 
+         \ram2e_ufm/N_811 , \ram2e_ufm/N_206 , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] , \ram2e_ufm/N_185 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S , \ram2e_ufm/N_637 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 , \ram2e_ufm/N_592 , 
+         \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] , \ram2e_ufm/N_634 , 
+         \ram2e_ufm/N_753 , \ram2e_ufm/wb_adr_7_i_i_1[0] , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] , 
+         \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_1[6] , \ram2e_ufm/N_890 , 
+         \ram2e_ufm/N_220 , \ram2e_ufm/N_196 , \ram2e_ufm/N_243 , \Ain_c[4] , 
+         \Ain_c[6] , \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] , \ram2e_ufm/N_565 , 
+         \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] , \ram2e_ufm/CKE_7s2_0_0_0 , 
+         \ram2e_ufm/wb_adr_7_5_41_a3_3_0 , \ram2e_ufm/N_204 , 
+         \ram2e_ufm/N_595 , \ram2e_ufm/nRWE_s_i_0_63_1 , \ram2e_ufm/N_792 , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] , 
+         \ram2e_ufm/N_553 , nEN80_c, \ram2e_ufm/N_241_i , \ram2e_ufm/N_814 , 
+         N_225_i, N_201_i, N_507_i, N_508, Vout3, \BA_4[1] , \Ain_c[0] , 
+         \Ain_c[7] , nDOE_c, LED_c, RDOE_i, PHI1_c, PHI1r, nVOE_c, N_263_i, 
+         N_667, N_648, N_662, N_666, N_663, N_665, N_664, \RD_in[0] , 
+         \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , 
+         \RD_in[2] , \RD_in[1] , DQMH_c, DQML_c, \RAout_c[11] , \RAout_c[10] , 
+         \RAout_c[9] , \RAout_c[8] , \RAout_c[7] , \RAout_c[6] , \RAout_c[5] , 
+         \RAout_c[4] , \RAout_c[3] , \RAout_c[2] , \RAout_c[1] , \RAout_c[0] , 
+         \BA_c[1] , \BA_c[0] , nRWEout_c, nCASout_c, nRASout_c, CKEout_c, 
          \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] , 
-         \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , \Dout_c[7] , \Dout_c[6] , 
-         \Dout_c[5] , \Dout_c[4] , \Dout_c[3] , \Dout_c[2] , \Dout_c[1] , 
-         \Dout_c[0] , VCCI;
+         \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , VCCI;
 
   SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), 
     .Q1(\FS[0] ), .FCO(\FS_cry[0] ));
@@ -127,428 +191,679 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), 
     .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), 
     .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
-  SLICE_9 SLICE_9( .D1(Ready), .C1(PHI1reg), .B1(PHI1_c), .C0(RWSel), 
-    .A0(CO0_1), .DI0(\CmdTout_3[0] ), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(\CmdTout_3[0] ), .Q0(CO0_1), .F1(S_1));
-  SLICE_10 SLICE_10( .D1(\S_RNII9DO1_0[1] ), .C1(\CS[0] ), .B1(N_461), 
-    .A1(\CS[1] ), .C0(\S_RNII9DO1_0[1] ), .B0(N_461), .A0(\CS[0] ), 
-    .DI1(N_511_i), .DI0(N_504_i), .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), 
-    .F0(N_504_i), .Q0(\CS[0] ), .F1(N_511_i), .Q1(\CS[1] ));
-  SLICE_11 SLICE_11( .D1(N_461), .C1(\CS[0] ), .B1(\S_RNII9DO1_0[1] ), 
-    .D0(\CS[1] ), .C0(N_637), .A0(\CS[2] ), .DI0(N_510_i), 
-    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_510_i), .Q0(\CS[2] ), 
-    .F1(N_637));
-  SLICE_12 SLICE_12( .D1(\Din_c[0] ), .C1(\Din_c[2] ), .B1(\Din_c[3] ), 
-    .D0(CmdBitbangMXO2_4_u_0_0_a2_0_1), .C0(N_643), .B0(RWSel), 
-    .A0(CmdBitbangMXO2), .DI0(CmdBitbangMXO2_4), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(CmdBitbangMXO2_4), .Q0(CmdBitbangMXO2), 
-    .F1(CmdBitbangMXO2_4_u_0_0_a2_0_1));
-  SLICE_13 SLICE_13( .D1(RWSel), .C1(\Din_c[5] ), .B1(\Din_c[7] ), .D0(RWSel), 
-    .C0(N_643), .B0(N_629), .A0(CmdExecMXO2), .DI0(CmdExecMXO2_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdExecMXO2_4), .Q0(CmdExecMXO2), 
-    .F1(N_466));
-  SLICE_14 SLICE_14( .D1(\Din_c[4] ), .C1(\Din_c[0] ), .B1(\Din_c[1] ), 
-    .A1(N_478), .D0(CmdLEDGet_4_u_0_0_a2_0_2), .C0(RWSel), .B0(N_476), 
-    .A0(CmdLEDGet), .DI0(CmdLEDGet_4), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(CmdLEDGet_4), .Q0(CmdLEDGet), .F1(CmdLEDGet_4_u_0_0_a2_0_2));
-  SLICE_15 SLICE_15( .D1(N_476), .C1(\Din_c[1] ), .B1(\Din_c[4] ), .A1(N_626), 
-    .D0(RWSel), .B0(N_605), .A0(CmdLEDSet), .DI0(CmdLEDSet_4), .CE(N_576_i), 
-    .CLK(C14M_c), .F0(CmdLEDSet_4), .Q0(CmdLEDSet), .F1(N_605));
-  SLICE_16 SLICE_16( .D1(N_476), .B1(\Din_c[4] ), .A1(\Din_c[1] ), .D0(N_643), 
-    .C0(N_626), .B0(RWSel), .A0(CmdRWMaskSet), .DI0(CmdRWMaskSet_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdRWMaskSet_4), .Q0(CmdRWMaskSet), 
-    .F1(N_643));
-  SLICE_17 SLICE_17( .D1(N_626), .C1(\Din_c[1] ), .B1(N_476), .A1(\Din_c[4] ), 
-    .C0(N_401), .B0(RWSel), .A0(CmdSetRWBankFFLED), .DI0(CmdSetRWBankFFLED_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdSetRWBankFFLED_4), 
-    .Q0(CmdSetRWBankFFLED), .F1(N_401));
-  SLICE_18 SLICE_18( .D1(\CS[2] ), .C1(N_474), .B1(\CS[1] ), 
-    .D0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), .C0(RWSel), .B0(N_476), 
-    .A0(CmdSetRWBankFFMXO2), .DI0(CmdSetRWBankFFMXO2_4), .CE(N_576_i), 
-    .CLK(C14M_c), .F0(CmdSetRWBankFFMXO2_4), .Q0(CmdSetRWBankFFMXO2), 
-    .F1(N_476));
-  SLICE_19 SLICE_19( .D1(\CmdTout[1] ), .C1(RWSel), .B1(\CmdTout[2] ), 
-    .A1(CO0_1), .D0(\CmdTout[1] ), .C0(RWSel), .A0(CO0_1), .DI1(N_556_i), 
-    .DI0(N_555_i), .CE(N_576_i), .CLK(C14M_c), .F0(N_555_i), .Q0(\CmdTout[1] ), 
-    .F1(N_556_i), .Q1(\CmdTout[2] ));
-  SLICE_20 SLICE_20( .D1(\S[2] ), .C1(\S[1] ), .B1(\S[0] ), .A1(\S[3] ), 
-    .D0(\S[2] ), .C0(\S[1] ), .B0(\S[0] ), .A0(\S[3] ), .DI0(N_6_i), 
-    .CLK(C14M_c), .F0(N_6_i), .Q0(DOEEN), .F1(N_576_i));
-  SLICE_21 SLICE_21( .D1(\S[3] ), .C1(\Ain_c[1] ), .A1(\S[0] ), .D0(\S[3] ), 
-    .C0(\wb_dato[0] ), .A0(\Din_c[0] ), .DI0(LEDEN_RNO), 
-    .CE(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .CLK(C14M_c), .F0(LEDEN_RNO), 
-    .Q0(LEDEN), .F1(N_558_i));
-  SLICE_22 SLICE_22( .C1(\S[0] ), .B1(\Ain_c[3] ), .A1(\S[3] ), .C0(\S[0] ), 
-    .B0(\Ain_c[0] ), .A0(\S[3] ), .DI1(N_552_i), .DI0(N_127_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c), .F0(N_127_i), .Q0(\RA_c[0] ), 
-    .F1(N_552_i), .Q1(\RA_c[3] ));
-  SLICE_23 SLICE_23( .C1(\Din_c[1] ), .B1(\RWMask[1] ), .A1(N_591), 
-    .D0(\RWMask[0] ), .B0(\Din_c[0] ), .A0(N_591), .DI1(\RWBank_5[1] ), 
-    .DI0(\RWBank_5[0] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[0] ), 
-    .Q0(\RWBank[0] ), .F1(\RWBank_5[1] ), .Q1(\RWBank[1] ));
-  SLICE_24 SLICE_24( .D1(\RWMask[3] ), .C1(\Din_c[3] ), .A1(N_591), 
-    .C0(\Din_c[2] ), .B0(N_591), .A0(\RWMask[2] ), .DI1(\RWBank_5[3] ), 
-    .DI0(\RWBank_5[2] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[2] ), 
-    .Q0(\RWBank[2] ), .F1(\RWBank_5[3] ), .Q1(\RWBank[3] ));
-  SLICE_25 SLICE_25( .C1(\Din_c[5] ), .B1(N_591), .A1(\RWMask[5] ), 
-    .D0(\Din_c[4] ), .B0(N_591), .A0(\RWMask[4] ), .DI1(\RWBank_5[5] ), 
-    .DI0(\RWBank_5[4] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[4] ), 
-    .Q0(\RWBank[4] ), .F1(\RWBank_5[5] ), .Q1(\RWBank[5] ));
-  SLICE_26 SLICE_26( .D1(N_591), .C1(\Din_c[7] ), .A1(\RWMask[7] ), .D0(N_591), 
-    .C0(\Din_c[6] ), .B0(\RWMask[6] ), .DI1(\RWBank_5[7] ), 
-    .DI0(\RWBank_5[6] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[6] ), 
-    .Q0(\RWBank[6] ), .F1(\RWBank_5[7] ), .Q1(\RWBank[7] ));
-  SLICE_27 SLICE_27( .D1(\Din_c[1] ), .C1(\wb_dato[1] ), .B1(\S[3] ), 
-    .C0(\wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), .DI1(N_291_i), 
-    .DI0(N_292_i), .CE(N_88), .CLK(C14M_c), .F0(N_292_i), .Q0(\RWMask[0] ), 
-    .F1(N_291_i), .Q1(\RWMask[1] ));
-  SLICE_28 SLICE_28( .D1(\S[3] ), .B1(\wb_dato[3] ), .A1(\Din_c[3] ), 
-    .D0(\S[3] ), .C0(\Din_c[2] ), .B0(\wb_dato[2] ), .DI1(N_289_i), 
-    .DI0(N_290_i), .CE(N_88), .CLK(C14M_c), .F0(N_290_i), .Q0(\RWMask[2] ), 
-    .F1(N_289_i), .Q1(\RWMask[3] ));
-  SLICE_29 SLICE_29( .D1(\wb_dato[5] ), .C1(\Din_c[5] ), .B1(\S[3] ), 
-    .C0(\Din_c[4] ), .B0(\S[3] ), .A0(\wb_dato[4] ), .DI1(N_287_i), 
-    .DI0(N_288_i), .CE(N_88), .CLK(C14M_c), .F0(N_288_i), .Q0(\RWMask[4] ), 
-    .F1(N_287_i), .Q1(\RWMask[5] ));
-  SLICE_30 SLICE_30( .D1(\S[3] ), .C1(\Din_c[7] ), .A1(\wb_dato[7] ), 
-    .D0(\S[3] ), .C0(\Din_c[6] ), .B0(\wb_dato[6] ), .DI1(N_285), 
-    .DI0(N_286_i), .CE(N_88), .CLK(C14M_c), .F0(N_286_i), .Q0(\RWMask[6] ), 
-    .F1(N_285), .Q1(\RWMask[7] ));
-  SLICE_31 SLICE_31( .C1(nEN80_c), .B1(nWE_c), .A1(DOEEN), .D0(\RA_c[0] ), 
-    .C0(\RA_c[3] ), .B0(nWE_c), .A0(nC07X_c), .DI0(RWSel_2), .CE(nCS61), 
-    .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(nDOE_c));
-  SLICE_32 SLICE_32( .D1(N_489), .C1(\FS[6] ), .B1(Ready_0_sqmuxa_0_a2_6_a2_4), 
-    .A1(\FS[7] ), .C0(Ready_0_sqmuxa), .A0(Ready), .DI0(N_876_0), .CLK(C14M_c), 
-    .F0(N_876_0), .Q0(Ready), .F1(Ready_0_sqmuxa));
-  SLICE_33 SLICE_33( .D1(S_1), .C1(N_572), .B1(wb_reqc_1), .A1(N_575), 
-    .D0(\S[1] ), .C0(\S_s_0_1[0] ), .B0(S_1), .A0(\S[0] ), .DI1(N_133_i), 
-    .DI0(\S_s_0[0] ), .CLK(C14M_c), .F0(\S_s_0[0] ), .Q0(\S[0] ), .F1(N_133_i), 
-    .Q1(\S[1] ));
-  SLICE_34 SLICE_34( .D1(N_575), .C1(S_1), .B1(\S[3] ), .A1(\S[2] ), 
-    .D0(N_575), .C0(S_1), .B0(\S[3] ), .A0(\S[2] ), .DI1(N_129_i), 
-    .DI0(N_131_i), .CLK(C14M_c), .F0(N_131_i), .Q0(\S[2] ), .F1(N_129_i), 
-    .Q1(\S[3] ));
-  SLICE_35 SLICE_35( .D1(N_388), .C1(wb_adr_7_5_214_0_1), .B1(\Din_c[1] ), 
-    .A1(\S[2] ), .D0(\FS[13] ), .C0(N_642), .B0(\wb_adr_7_0_4[0] ), .A0(N_376), 
-    .DI1(\wb_adr_RNO[1] ), .DI0(\wb_adr_7[0] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_adr_7[0] ), 
-    .Q0(\wb_adr[0] ), .F1(\wb_adr_RNO[1] ), .Q1(\wb_adr[1] ));
-  SLICE_36 SLICE_36( .D1(\S[2] ), .C1(\Din_c[3] ), .D0(\S[2] ), 
-    .A0(\Din_c[2] ), .DI1(N_41_i), .DI0(N_43_i), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_43_i), 
-    .Q0(\wb_adr[2] ), .F1(N_41_i), .Q1(\wb_adr[3] ));
-  SLICE_37 SLICE_37( .D1(\S[2] ), .B1(\FS[14] ), .A1(\Din_c[5] ), .D0(\S[2] ), 
-    .C0(\Din_c[4] ), .B0(\FS[14] ), .DI1(N_295), .DI0(N_294), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_294), 
-    .Q0(\wb_adr[4] ), .F1(N_295), .Q1(\wb_adr[5] ));
-  SLICE_38 SLICE_38( .D1(\S[2] ), .B1(\Din_c[7] ), .D0(\S[2] ), .C0(\FS[14] ), 
-    .B0(\Din_c[6] ), .DI1(N_39_i), .DI0(N_296), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_296), 
-    .Q0(\wb_adr[6] ), .F1(N_39_i), .Q1(\wb_adr[7] ));
-  SLICE_39 SLICE_39( .D1(N_300), .C1(wb_ack), .B1(\FS[14] ), .A1(\FS[0] ), 
-    .C0(\S[3] ), .B0(N_395), .A0(CmdExecMXO2), .DI0(wb_cyc_stb_RNO), 
-    .CE(N_104), .CLK(C14M_c), .F0(wb_cyc_stb_RNO), .Q0(wb_cyc_stb), .F1(N_395));
-  SLICE_40 SLICE_40( .D1(\wb_dati_7_0_0[1] ), .C1(N_627), .B1(N_336), 
-    .A1(N_621), .D0(\wb_adr[0] ), .C0(\wb_dati_7_0_a2_1[0] ), .B0(\S[2] ), 
-    .A0(N_484), .DI1(\wb_dati_7[1] ), .DI0(\wb_dati_7[0] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[0] ), 
-    .Q0(\wb_dati[0] ), .F1(\wb_dati_7[1] ), .Q1(\wb_dati[1] ));
-  SLICE_41 SLICE_41( .D1(\wb_dati_7_0_2[3] ), .C1(\wb_dati_7_0_0[3] ), 
-    .B1(N_336), .D0(\wb_dati_7_0_o2_0[2] ), .C0(\S[2] ), .B0(\wb_adr[2] ), 
-    .A0(N_345), .DI1(\wb_dati_7[3] ), .DI0(\wb_dati_7[2] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[2] ), 
-    .Q0(\wb_dati[2] ), .F1(\wb_dati_7[3] ), .Q1(\wb_dati[3] ));
-  SLICE_42 SLICE_42( .D1(\wb_dati_7_0_o2_0[2] ), .C1(N_345), .B1(\S[2] ), 
-    .A1(\wb_adr[5] ), .D0(N_345), .C0(N_346), .B0(N_349), 
-    .A0(\wb_dati_7_0_0[4] ), .DI1(\wb_dati_7[5] ), .DI0(\wb_dati_7[4] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[4] ), 
-    .Q0(\wb_dati[4] ), .F1(\wb_dati_7[5] ), .Q1(\wb_dati[5] ));
-  SLICE_43 SLICE_43( .D1(\wb_dati_7_0_RNO[7] ), .C1(\wb_dati_7_0_0[7] ), 
-    .B1(N_422), .A1(N_424), .D0(N_627), .B0(\wb_dati_7_0_1[6] ), .A0(N_621), 
-    .DI1(\wb_dati_7[7] ), .DI0(\wb_dati_7[6] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[6] ), 
-    .Q0(\wb_dati[6] ), .F1(\wb_dati_7[7] ), .Q1(\wb_dati[7] ));
-  SLICE_44 SLICE_44( .D1(\FS[12] ), .B1(\FS[13] ), .A1(\FS[11] ), .D0(\S[3] ), 
-    .C0(\FS[14] ), .B0(wb_reqc_1), .A0(N_397), .DI0(wb_reqc_i), 
-    .CE(wb_adr_0_sqmuxa_i), .LSR(\S[2] ), .CLK(C14M_c), .F0(wb_reqc_i), 
-    .Q0(wb_req), .F1(N_397));
-  SLICE_45 SLICE_45( .B1(wb_ack), .A1(\FS[14] ), .D0(\FS[15] ), .A0(\FS[14] ), 
-    .DI0(wb_rst8), .LSR(\S_RNII9DO1[1] ), .CLK(C14M_c), .F0(wb_rst8), 
-    .Q0(wb_rst), .F1(N_586));
-  SLICE_46 SLICE_46( .D1(\FS[10] ), .C1(\FS[12] ), .B1(\FS[8] ), .A1(\FS[9] ), 
-    .D0(wb_we_7_iv_0_0_0_1), .C0(N_584), .B0(N_475), .A0(\FS[13] ), 
-    .DI0(wb_we_RNO), .CE(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), .CLK(C14M_c), 
-    .F0(wb_we_RNO), .Q0(wb_we), .F1(N_584));
-  SLICE_47 SLICE_47( .D1(\RWBank[6] ), .C1(\S_RNII9DO1[1] ), .B1(\S[0] ), 
-    .A1(N_255), .D0(\S[2] ), .C0(\S[3] ), .B0(\S[0] ), .A0(\S[1] ), 
-    .F0(\S_RNII9DO1[1] ), .F1(N_358_i));
-  SLICE_48 SLICE_48( .D1(\S[2] ), .C1(\S[0] ), .B1(\S[3] ), .A1(\S[1] ), 
-    .D0(N_635), .C0(N_254), .B0(\S[0] ), .A0(Vout3), .F0(nCAS_s_i_tz_0), 
-    .F1(Vout3));
-  SLICE_49 SLICE_49( .D1(un1_CS_0_sqmuxa_0_0_a2_1_4), .C1(\Din_c[6] ), 
-    .B1(RWSel), .A1(\CS[0] ), .D0(\CS[2] ), .C0(N_327), .B0(RWSel), 
-    .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_0), .F1(N_327));
-  SLICE_50 SLICE_50( .D1(\FS[10] ), .C1(\FS[11] ), .B1(\FS[8] ), .A1(\FS[9] ), 
-    .D0(\wb_dati_7_0_a2_0_1[7] ), .C0(N_621), .B0(N_579), .A0(\FS[9] ), 
-    .F0(\wb_dati_7_0_RNO[7] ), .F1(\wb_dati_7_0_a2_0_1[7] ));
-  SLICE_51 SLICE_51( .D1(\S[3] ), .C1(CKE_6_iv_i_a2_0), .B1(\S[2] ), 
-    .A1(wb_reqc_1), .D0(N_489), .C0(CKE_6_iv_i_0_1), .B0(\S[3] ), 
-    .A0(\FS[15] ), .F0(CKE_6_iv_i_0), .F1(CKE_6_iv_i_0_1));
-  SLICE_52 SLICE_52( .D1(N_300), .C1(N_449), .B1(wb_req), .A1(\FS[0] ), 
-    .D0(N_364), .C0(N_449), .B0(N_365), .A0(N_586), .F0(N_104), .F1(N_365));
-  SLICE_53 SLICE_53( .D1(\S[2] ), .C1(RWSel), .B1(\S[3] ), .A1(\FS[15] ), 
-    .D0(\S[2] ), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .B0(wb_reqc_1), 
-    .A0(CmdExecMXO2), .F0(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), 
-    .F1(\un1_wb_adr_0_sqmuxa_2_1[0] ));
-  SLICE_54 SLICE_54( .D1(\Din_c[0] ), .C1(\CS[1] ), .B1(\Din_c[2] ), 
-    .A1(\Din_c[1] ), .D0(N_616), .C0(\CS[2] ), .B0(N_623), .A0(\Din_c[1] ), 
-    .F0(N_279), .F1(N_623));
-  SLICE_55 SLICE_55( .D1(\FS[5] ), .C1(N_264), .B1(N_633), .A1(\FS[4] ), 
-    .D0(\FS[5] ), .C0(\FS[1] ), .B0(\FS[2] ), .A0(\FS[3] ), .F0(N_633), 
-    .F1(N_570));
-  SLICE_56 SLICE_56( .D1(\FS[15] ), .C1(\S_RNII9DO1[1] ), .A1(\FS[14] ), 
-    .D0(N_452), .C0(\FS[13] ), .A0(\FS[12] ), .F0(N_621), .F1(N_452));
-  SLICE_57 SLICE_57( .D1(RWSel), .C1(wb_ack), .B1(\S_RNII9DO1_0[1] ), 
-    .A1(CmdExecMXO2), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[0] ), .A0(\S[3] ), 
-    .F0(\S_RNII9DO1_0[1] ), .F1(N_364));
-  SLICE_58 SLICE_58( .D1(N_455), .C1(N_644), .B1(\wb_dati_7_0_a2_2_1[3] ), 
-    .A1(\FS[12] ), .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), 
-    .F0(\wb_dati_7_0_a2_2_1[3] ), .F1(\wb_dati_7_0_2[3] ));
-  SLICE_59 SLICE_59( .D1(DQML_s_i_a2_0), .C1(\S_RNII9DO1[1] ), .B1(nCS61), 
-    .A1(\RWBank[6] ), .D0(\S[3] ), .C0(\S[0] ), .B0(\S[1] ), .A0(\S[2] ), 
-    .F0(DQML_s_i_a2_0), .F1(N_28_i));
-  SLICE_60 SLICE_60( .D1(N_569), .C1(wb_adr_7_5_214_a2_2_0), .B1(N_577), 
-    .A1(N_475), .C0(\FS[12] ), .B0(\FS[10] ), .A0(\FS[13] ), 
-    .F0(wb_adr_7_5_214_a2_2_0), .F1(wb_adr_7_5_214_0_1));
-  SLICE_61 SLICE_61( .D1(\FS[12] ), .C1(N_634), .B1(\FS[13] ), .D0(\FS[8] ), 
-    .C0(\FS[10] ), .B0(\FS[9] ), .A0(\FS[11] ), .F0(N_634), 
-    .F1(\wb_dati_7_0_a2_2_0[1] ));
-  SLICE_62 SLICE_62( .D1(N_475), .C1(\FS[11] ), .B1(N_265_i), .A1(\FS[12] ), 
-    .D0(\FS[10] ), .C0(\FS[9] ), .B0(\FS[8] ), .F0(N_265_i), .F1(N_388));
-  SLICE_63 SLICE_63( .D1(\FS[7] ), .C1(N_264), .B1(\FS[6] ), .A1(N_254), 
-    .C0(\FS[1] ), .B0(\FS[2] ), .A0(\FS[3] ), .F0(N_264), .F1(N_300));
-  SLICE_64 SLICE_64( .C1(\FS[11] ), .B1(\FS[8] ), .A1(\FS[9] ), .D0(\FS[10] ), 
-    .C0(N_577), .B0(\FS[12] ), .A0(wb_ack), 
-    .F0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .F1(N_577));
-  SLICE_65 SLICE_65( .D1(\FS[8] ), .B1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[10] ), 
-    .C0(\FS[12] ), .B0(\wb_dati_7_0_a2_0[6] ), .A0(\FS[13] ), 
-    .F0(\wb_dati_7_0_a2_4_0[7] ), .F1(\wb_dati_7_0_a2_0[6] ));
-  SLICE_66 SLICE_66( .C1(\S[2] ), .A1(\FS[14] ), .D0(N_475), .C0(\FS[12] ), 
-    .B0(\FS[11] ), .A0(\FS[13] ), .F0(N_393), .F1(N_475));
-  SLICE_67 SLICE_67( .C1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(wb_reqc_1), 
-    .B0(\S[2] ), .A0(RWSel), .F0(LEDEN13), .F1(wb_reqc_1));
-  SLICE_68 SLICE_68( .D1(N_455), .C1(N_627), .B1(\wb_adr[3] ), .A1(\S[2] ), 
-    .D0(\FS[11] ), .C0(\FS[8] ), .B0(\FS[10] ), .A0(\FS[9] ), .F0(N_627), 
-    .F1(\wb_dati_7_0_0[3] ));
-  SLICE_69 SLICE_69( .D1(nCAS_0_sqmuxa), .C1(N_639), .B1(N_255), 
-    .A1(\RWBank[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), 
-    .F0(N_639), .F1(\RA_42[10] ));
-  SLICE_70 SLICE_70( .D1(N_455), .C1(\FS[12] ), .B1(N_627), .A1(N_644), 
-    .D0(\FS[10] ), .C0(\FS[11] ), .B0(\FS[8] ), .A0(\FS[9] ), .F0(N_644), 
-    .F1(N_345));
-  SLICE_71 SLICE_71( .D1(N_640), .C1(N_633), .B1(nCS61), .A1(\FS[4] ), 
-    .D0(\S[1] ), .C0(\S[3] ), .B0(\S[0] ), .A0(\S[2] ), .F0(nCS61), 
-    .F1(un1_nCS61_1_i));
-  SLICE_72 SLICE_72( .D1(Ready_0_sqmuxa_0_a2_6_a2_2), .C1(\FS[5] ), 
-    .B1(\FS[3] ), .A1(N_449), .D0(\FS[15] ), .C0(\S[2] ), .B0(wb_reqc_1), 
-    .A0(\S[3] ), .F0(N_449), .F1(Ready_0_sqmuxa_0_a2_6_a2_4));
-  SLICE_73 SLICE_73( .D1(N_562), .C1(\FS[12] ), .B1(N_455), .A1(\FS[11] ), 
-    .D0(\FS[15] ), .C0(\FS[14] ), .B0(\S_RNII9DO1[1] ), .A0(\FS[13] ), 
-    .F0(N_455), .F1(N_377));
-  SLICE_74 SLICE_74( .D1(N_484), .B1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[13] ), 
-    .C0(\FS[12] ), .B0(\FS[10] ), .A0(N_642), .F0(N_346), .F1(N_642));
-  SLICE_75 SLICE_75( .D1(N_489), .C1(\FS[6] ), .B1(\FS[7] ), .A1(\FS[0] ), 
-    .D0(\FS[15] ), .C0(N_628), .A0(\S_RNII9DO1[1] ), .F0(N_640), .F1(N_628));
-  SLICE_76 SLICE_76( .B1(\FS[5] ), .A1(\FS[4] ), .D0(N_264), .C0(N_254), 
-    .B0(N_628), .A0(N_449), .F0(nCAS_0_sqmuxa), .F1(N_254));
-  SLICE_77 SLICE_77( .D1(\Din_c[6] ), .C1(\CS[0] ), .A1(N_466), 
-    .D0(un1_CS_0_sqmuxa_0_0_2), .C0(N_474), .B0(un1_CS_0_sqmuxa_0_0_a2_3_2), 
-    .A0(un1_CS_0_sqmuxa_0_0_3), .F0(un1_CS_0_sqmuxa_i), .F1(N_474));
-  SLICE_78 SLICE_78( .C1(N_633), .A1(\FS[4] ), .D0(nCAS_0_sqmuxa), .C0(N_640), 
-    .B0(nCAS_s_i_tz_0), .A0(N_567), .F0(N_561_i), .F1(N_567));
-  SLICE_79 SLICE_79( .D1(\S[2] ), .C1(\S[3] ), .B1(nEN80_c), .A1(\S[1] ), 
-    .C0(nCS_6_u_i_0), .A0(N_559_1), .F0(N_559_i), .F1(nCS_6_u_i_0));
-  SLICE_80 SLICE_80( .D1(\S[1] ), .C1(\S[2] ), .B1(\S[3] ), .D0(N_559_1), 
-    .C0(N_635), .B0(\S[0] ), .F0(nRAS_2_iv_i), .F1(N_635));
-  SLICE_81 SLICE_81( .D1(\Din_c[4] ), .C1(\Din_c[3] ), .B1(\Din_c[6] ), 
-    .A1(\CS[0] ), .D0(N_466), .C0(un1_CS_0_sqmuxa_0_0_0), 
-    .B0(un1_CS_0_sqmuxa_0_0_a2_1), .A0(N_279), .F0(un1_CS_0_sqmuxa_0_0_2), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_1));
-  SLICE_82 SLICE_82( .D1(\CmdTout[1] ), .C1(RWSel), .B1(CO0_1), 
-    .A1(\CmdTout[2] ), .D0(N_328), .C0(N_330), .B0(N_461), 
-    .A0(\S_RNII9DO1_0[1] ), .F0(un1_CS_0_sqmuxa_0_0_3), .F1(N_461));
-  SLICE_83 SLICE_83( .D1(\S[0] ), .C1(\S[3] ), .B1(\FS[15] ), .A1(\S[2] ), 
-    .D0(N_429), .C0(N_570), .B0(N_628), .A0(nCS_6_u_i_a2_1), .F0(N_559_1), 
-    .F1(nCS_6_u_i_a2_1));
-  SLICE_84 SLICE_84( .D1(\FS[10] ), .C1(\FS[12] ), .B1(N_455), 
-    .A1(\wb_dati_7_0_a2_0[6] ), .D0(\S[2] ), .C0(N_351), .B0(\wb_adr[6] ), 
-    .A0(N_346), .F0(\wb_dati_7_0_1[6] ), .F1(N_351));
-  SLICE_85 SLICE_85( .D1(\FS[8] ), .C1(N_579), .B1(\wb_adr_7_0_a2_5_0[0] ), 
-    .A1(N_452), .D0(\wb_adr_7_0_0[0] ), .C0(N_378), .B0(\wb_adr_7_0_1[0] ), 
-    .A0(N_377), .F0(\wb_adr_7_0_4[0] ), .F1(\wb_adr_7_0_1[0] ));
-  SLICE_86 SLICE_86( .D1(\FS[15] ), .C1(\S_RNII9DO1[1] ), .B1(\FS[8] ), 
-    .A1(\FS[14] ), .D0(CmdLEDSet), .C0(N_484), 
-    .B0(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ), .A0(LEDEN13), 
-    .F0(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .F1(N_484));
-  SLICE_87 SLICE_87( .D1(un1_CS_0_sqmuxa_0_0_a2_4_2), .C1(\Din_c[6] ), 
-    .B1(\CS[0] ), .A1(RWSel), .D0(\CS[1] ), .C0(un1_CS_0_sqmuxa_0_0_a2_4_4), 
-    .A0(\CS[2] ), .F0(N_330), .F1(un1_CS_0_sqmuxa_0_0_a2_4_4));
-  SLICE_88 SLICE_88( .D1(\FS[13] ), .B1(\FS[12] ), .D0(N_452), .C0(N_569), 
-    .B0(N_634), .A0(N_336), .F0(\wb_dati_7_0_o2_0[2] ), .F1(N_569));
-  SLICE_89 SLICE_89( .D1(\FS[10] ), .B1(\FS[11] ), .D0(\FS[9] ), .C0(N_455), 
-    .B0(\FS[8] ), .A0(N_579), .F0(N_378), .F1(N_579));
-  SLICE_90 SLICE_90( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), 
-    .C0(\FS[12] ), .B0(N_565), .A0(N_484), .F0(N_336), .F1(N_565));
-  SLICE_91 SLICE_91( .D1(\Din_c[6] ), .C1(un1_CS_0_sqmuxa_0_0_a2_2_2), 
-    .B1(\CS[0] ), .A1(\CS[2] ), .D0(\Din_c[7] ), 
-    .C0(un1_CS_0_sqmuxa_0_0_a2_2_4), .B0(RWSel), .F0(N_328), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_2_4));
-  SLICE_92 SLICE_92( .D1(\FS[11] ), .C1(\FS[12] ), .B1(N_562), .A1(\FS[13] ), 
-    .D0(\Din_c[0] ), .C0(\S[2] ), .B0(\wb_adr_7_0_a2_0[0] ), .A0(N_452), 
-    .F0(\wb_adr_7_0_0[0] ), .F1(\wb_adr_7_0_a2_0[0] ));
-  SLICE_93 SLICE_93( .D1(N_616), .C1(\Din_c[5] ), .B1(\Din_c[1] ), 
-    .A1(\Din_c[4] ), .D0(\CS[1] ), .C0(\Din_c[3] ), 
-    .B0(un1_CS_0_sqmuxa_0_0_a2_1_2), .A0(\Din_c[7] ), 
-    .F0(un1_CS_0_sqmuxa_0_0_a2_1_4), .F1(un1_CS_0_sqmuxa_0_0_a2_1_2));
-  SLICE_94 SLICE_94( .D1(\Din_c[0] ), .C1(\Din_c[3] ), .B1(\Din_c[2] ), 
-    .A1(\Din_c[1] ), .D0(\CS[2] ), .C0(un1_CS_0_sqmuxa_0_0_a2_3_0), 
-    .B0(\Din_c[4] ), .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_a2_3_2), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_3_0));
-  SLICE_95 SLICE_95( .D1(\FS[10] ), .C1(\FS[12] ), .B1(N_577), .A1(N_475), 
-    .D0(N_394), .C0(\Din_c[0] ), .B0(\S[2] ), .A0(N_393), 
-    .F0(wb_we_7_iv_0_0_0_1), .F1(N_394));
-  SLICE_96 SLICE_96( .C1(\S[1] ), .B1(\S[2] ), .A1(\S[3] ), .D0(\S[0] ), 
-    .C0(\RWBank[7] ), .B0(N_255), .A0(\RWBank[0] ), .F0(N_49_i), .F1(N_255));
-  SLICE_97 SLICE_97( .D1(\FS[12] ), .C1(\FS[10] ), .D0(N_577), .C0(N_456), 
-    .B0(\FS[13] ), .A0(\FS[14] ), .F0(N_489), .F1(N_456));
-  SLICE_98 SLICE_98( .D1(\Din_c[0] ), .C1(\Din_c[2] ), .B1(\Din_c[3] ), 
-    .D0(N_477), .C0(N_626), .B0(\Din_c[5] ), .A0(\Din_c[7] ), 
-    .F0(un1_CS_0_sqmuxa_0_0_a2_4_2), .F1(N_626));
-  SLICE_99 SLICE_99( .C1(\Din_c[2] ), .B1(\Din_c[3] ), .D0(\Din_c[0] ), 
-    .C0(N_478), .B0(\Din_c[5] ), .A0(N_477), .F0(un1_CS_0_sqmuxa_0_0_a2_2_2), 
-    .F1(N_478));
-  SLICE_100 SLICE_100( .D1(\Din_c[0] ), .C1(\Din_c[3] ), .B1(\Din_c[2] ), 
-    .D0(\Din_c[1] ), .C0(N_629), .A0(\Din_c[4] ), 
-    .F0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), .F1(N_629));
-  SLICE_101 SLICE_101( .D1(\S[1] ), .C1(\S[2] ), .B1(\S[3] ), .A1(\S[0] ), 
-    .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), .F0(\S_RNII9DO1_1[1] ), 
-    .F1(N_566_i));
-  SLICE_102 SLICE_102( .D1(\S[1] ), .C1(\S[0] ), .B1(\S[3] ), .A1(\S[2] ), 
-    .D0(\S[1] ), .C0(\RWBank[4] ), .B0(\S[3] ), .A0(\S[2] ), .F0(\BA_4[0] ), 
-    .F1(\S_s_0_1[0] ));
-  SLICE_103 SLICE_103( .D1(\RWBank[3] ), .C1(wb_reqc_1), .B1(\S[2] ), 
-    .A1(\S[3] ), .D0(wb_reqc_1), .C0(\FS[15] ), .B0(\S[2] ), .A0(\S[3] ), 
-    .F0(wb_adr_0_sqmuxa_i), .F1(\RA_42[11] ));
-  SLICE_104 SLICE_104( .D1(N_621), .C1(\FS[8] ), .B1(\FS[9] ), .A1(\FS[11] ), 
-    .D0(N_621), .C0(\FS[10] ), .B0(\FS[9] ), .A0(\FS[11] ), .F0(N_376), 
-    .F1(N_349));
-  SLICE_105 SLICE_105( .D1(wb_ack), .C1(\FS[9] ), .B1(N_579), .A1(N_569), 
-    .D0(N_569), .C0(\FS[9] ), .B0(N_579), .A0(N_484), .F0(N_424), 
-    .F1(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ));
-  SLICE_106 SLICE_106( .D1(\S[1] ), .C1(\S[0] ), .D0(\S[1] ), .C0(\S[0] ), 
-    .B0(nEN80_c), .F0(CKE_6_iv_i_a2_0), .F1(N_575));
-  SLICE_107 SLICE_107( .C1(\S[2] ), .B1(\S[3] ), .D0(\RWBank[5] ), .C0(\S[2] ), 
-    .B0(\S[3] ), .A0(\S[1] ), .F0(\BA_4[1] ), .F1(N_572));
-  SLICE_108 SLICE_108( .D1(\FS[10] ), .C1(\FS[12] ), .A1(\FS[9] ), 
-    .D0(\FS[10] ), .C0(\FS[12] ), .B0(\FS[13] ), .A0(N_642), .F0(N_422), 
-    .F1(\wb_adr_7_0_a2_5_0[0] ));
-  SLICE_109 SLICE_109( .D1(N_452), .C1(\wb_adr[7] ), 
-    .B1(\wb_dati_7_0_a2_4_0[7] ), .A1(\S[2] ), .D0(N_452), 
-    .C0(\wb_dati_7_0_a2_2_0[1] ), .B0(\wb_adr[1] ), .A0(\S[2] ), 
-    .F0(\wb_dati_7_0_0[1] ), .F1(\wb_dati_7_0_0[7] ));
-  SLICE_110 SLICE_110( .D1(\S[2] ), .C1(\RWBank[1] ), .B1(wb_reqc_1), 
-    .A1(\S[3] ), .D0(\S[2] ), .C0(CmdBitbangMXO2), .B0(wb_reqc_1), 
-    .A0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .F0(\un1_wb_adr_0_sqmuxa_2_i[0] ), 
-    .F1(N_59_i));
-  SLICE_111 SLICE_111( .D1(\S[3] ), .B1(\Ain_c[5] ), .A1(\S[0] ), .D0(\S[3] ), 
-    .C0(\Ain_c[4] ), .A0(\S[0] ), .F0(N_551_i), .F1(\RA_42_3_0[5] ));
-  SLICE_112 SLICE_112( .D1(\S[3] ), .C1(N_254), .B1(\S[1] ), .A1(\S[0] ), 
-    .D0(\S[3] ), .B0(\Ain_c[6] ), .A0(\S[0] ), .F0(N_550_i), .F1(N_429));
-  SLICE_113 SLICE_113( .D1(\S[3] ), .C1(\Ain_c[2] ), .A1(\S[0] ), .D0(\S[3] ), 
-    .C0(\Ain_c[7] ), .A0(\S[0] ), .F0(N_549_i), .F1(N_553_i));
-  SLICE_114 SLICE_114( .D1(\wb_adr[4] ), .C1(\S[2] ), .B1(N_455), .A1(N_634), 
-    .D0(CmdRWMaskSet), .C0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .B0(N_455), 
-    .A0(LEDEN13), .F0(N_88), .F1(\wb_dati_7_0_0[4] ));
-  SLICE_115 SLICE_115( .D1(nEN80_c), .C1(nWE80_c), .D0(\S[0] ), .C0(nWE80_c), 
-    .B0(un1_nCS61_1_i), .A0(nCAS_0_sqmuxa), .F0(nRWE_r_0), .F1(RDOE_i));
-  SLICE_116 SLICE_116( .B1(\FS[8] ), .A1(\FS[9] ), .D0(N_456), .C0(\FS[13] ), 
-    .B0(\FS[11] ), .A0(\FS[9] ), .F0(\wb_dati_7_0_a2_1[0] ), .F1(N_562));
-  SLICE_117 SLICE_117( .D1(CmdSetRWBankFFLED), .C1(CmdLEDGet), 
-    .B1(CmdSetRWBankFFMXO2), .A1(LEDEN), .D0(LEDEN), .B0(nEN80_c), .F0(LED_c), 
-    .F1(N_591));
-  SLICE_118 SLICE_118( .C1(\Din_c[4] ), .B1(\Din_c[1] ), .D0(\Din_c[0] ), 
-    .C0(\Din_c[2] ), .F0(N_616), .F1(N_477));
-  SLICE_119 SLICE_119( .D0(\FS[0] ), .C0(\FS[1] ), .B0(\FS[2] ), .A0(\FS[4] ), 
-    .F0(Ready_0_sqmuxa_0_a2_6_a2_2));
-  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(\Din_c[0] ), 
+  SLICE_9 SLICE_9( .D1(\S[1] ), .C1(\FS[15] ), .B1(\S[0] ), .A1(N_551), 
+    .D0(\S[1] ), .C0(\S[0] ), .B0(\ram2e_ufm/CKE_7 ), .A0(N_551), 
+    .DI0(CKE_7_RNIS77M1), .CLK(C14M_c), .F0(CKE_7_RNIS77M1), .Q0(CKE), 
+    .F1(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ));
+  SLICE_10 SLICE_10( .B0(RWSel), .A0(CO0_0), .DI0(\CmdTout_3[0] ), 
+    .CE(N_185_i), .CLK(C14M_c), .F0(\CmdTout_3[0] ), .Q0(CO0_0), .F1(GND));
+  SLICE_11 SLICE_11( .D1(\RC[2] ), .A1(CO0_1), .D0(\RC[2] ), .B0(\RC[1] ), 
+    .A0(CO0_1), .DI0(N_360_i), .CE(RC12), .CLK(C14M_c), .F0(N_360_i), 
+    .Q0(CO0_1), .F1(\ram2e_ufm/N_821 ));
+  SLICE_12 SLICE_12( .D1(\ram2e_ufm/SUM1_0_0 ), .C1(\ram2e_ufm/SUM0_i_a3_4_0 ), 
+    .B1(\ram2e_ufm/N_886 ), .A1(\ram2e_ufm/N_215 ), .D0(\CS[1] ), 
+    .C0(\ram2e_ufm/SUM0_i_4 ), .B0(\ram2e_ufm/N_215 ), .A0(\CS[2] ), 
+    .DI1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .DI0(N_547_i), 
+    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_547_i), .Q0(\CS[0] ), 
+    .F1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .Q1(\CS[1] ));
+  SLICE_13 SLICE_13( .D1(\CS[2] ), .C1(\CS[1] ), .B1(\ram2e_ufm/N_234 ), 
+    .A1(\ram2e_ufm/N_215 ), .D0(\ram2e_ufm/N_215 ), .C0(\CS[1] ), 
+    .B0(\ram2e_ufm/N_234 ), .A0(\CS[2] ), 
+    .DI0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), .LSR(un1_CS_0_sqmuxa_i), 
+    .CLK(C14M_c), .F0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), .Q0(\CS[2] ), 
+    .F1(\ram2e_ufm/SUM1_0_0 ));
+  SLICE_14 SLICE_14( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .A1(\ram2e_ufm/N_800 ), 
+    .D0(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ), .C0(\Din_c[1] ), 
+    .B0(\ram2e_ufm/N_847 ), .A0(\Din_c[2] ), .DI0(CmdLEDGet_3), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(CmdLEDGet_3), .Q0(CmdLEDGet), .F1(\ram2e_ufm/N_847 ));
+  SLICE_15 SLICE_15( .D1(\Din_c[7] ), .B1(\CS[2] ), .A1(\Din_c[1] ), 
+    .D0(\ram2e_ufm/N_883 ), .C0(\Din_c[4] ), .B0(\Din_c[7] ), .A0(\Din_c[1] ), 
+    .DI0(CmdLEDSet_3), .CE(N_187_i), .CLK(C14M_c), .F0(CmdLEDSet_3), 
+    .Q0(CmdLEDSet), .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ));
+  SLICE_16 SLICE_16( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[3] ), 
+    .A1(\Din_c[1] ), .D0(\ram2e_ufm/N_883 ), .C0(\Din_c[4] ), .B0(\Din_c[7] ), 
+    .A0(\Din_c[1] ), .DI0(CmdRWMaskSet_3), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(CmdRWMaskSet_3), .Q0(CmdRWMaskSet), .F1(\ram2e_ufm/N_850 ));
+  SLICE_17 SLICE_17( .D1(\Din_c[2] ), .C1(\Din_c[0] ), .B1(\ram2e_ufm/N_847 ), 
+    .D0(\Din_c[1] ), .C0(\ram2e_ufm/N_883 ), .B0(\Din_c[7] ), .A0(\Din_c[4] ), 
+    .DI0(CmdSetRWBankFFLED_4), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(CmdSetRWBankFFLED_4), .Q0(CmdSetRWBankFFLED), .F1(\ram2e_ufm/N_883 ));
+  SLICE_18 SLICE_18( .D1(RWSel), .C1(CO0_0), .B1(\CmdTout[1] ), 
+    .A1(\CmdTout[2] ), .D0(RWSel), .B0(CO0_0), .A0(\CmdTout[1] ), 
+    .DI1(N_369_i), .DI0(N_368_i), .CE(N_185_i), .CLK(C14M_c), .F0(N_368_i), 
+    .Q0(\CmdTout[1] ), .F1(N_369_i), .Q1(\CmdTout[2] ));
+  SLICE_19 SLICE_19( .C1(\CS[1] ), .B1(\CS[2] ), .B0(\RA[1] ), 
+    .A0(\ram2e_ufm/N_186 ), .M0(\S[3] ), .LSR(N_1080_0), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_660 ), .Q0(DOEEN), .F1(\ram2e_ufm/N_193 ));
+  SLICE_20 SLICE_20( .D1(\ram2e_ufm/N_182 ), .C1(\Ain_c[1] ), 
+    .B1(\ram2e_ufm/N_660 ), .A1(\ram2e_ufm/N_659 ), 
+    .D0(\ram2e_ufm/RA_35_0_0_1[0] ), .C0(\ram2e_ufm/N_801 ), .B0(\FS[7] ), 
+    .A0(\ram2e_ufm/N_684 ), .DI1(N_223), .DI0(\RA_35[0] ), .CE(N_126), 
+    .CLK(C14M_c), .F0(\RA_35[0] ), .Q0(\RA[0] ), .F1(N_223), .Q1(\RA[1] ));
+  SLICE_21 SLICE_21( .D1(\ram2e_ufm/RA_35_0_0_0[3] ), .B1(\FS[10] ), 
+    .A1(\ram2e_ufm/N_801 ), .D0(\ram2e_ufm/N_680 ), .C0(\ram2e_ufm/N_679 ), 
+    .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[2] ), .DI1(\RA_35[3] ), 
+    .DI0(\RA_35[2] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[2] ), .Q0(\RA[2] ), 
+    .F1(\RA_35[3] ), .Q1(\RA[3] ));
+  SLICE_22 SLICE_22( .D1(\ram2e_ufm/N_182 ), .C1(\Ain_c[5] ), 
+    .B1(\ram2e_ufm/RA_35_0_0_0[5] ), .A1(\ram2e_ufm/N_621 ), 
+    .D0(\ram2e_ufm/RA_35_0_0_0[4] ), .C0(\FS[11] ), .A0(\ram2e_ufm/N_801 ), 
+    .DI1(\RA_35[5] ), .DI0(\RA_35[4] ), .CE(N_126), .CLK(C14M_c), 
+    .F0(\RA_35[4] ), .Q0(\RA[4] ), .F1(\RA_35[5] ), .Q1(\RA[5] ));
+  SLICE_23 SLICE_23( .C1(\ram2e_ufm/RA_35_0_0_0_0[7] ), .B1(\FS[14] ), 
+    .A1(\ram2e_ufm/N_801 ), .C0(\ram2e_ufm/RA_35_0_0_0_0[6] ), .B0(\FS[13] ), 
+    .A0(\ram2e_ufm/N_801 ), .DI1(\RA_35[7] ), .DI0(\RA_35[6] ), .CE(N_126), 
+    .CLK(C14M_c), .F0(\RA_35[6] ), .Q0(\RA[6] ), .F1(\RA_35[7] ), .Q1(\RA[7] ));
+  SLICE_24 SLICE_24( .D1(\ram2e_ufm/N_242 ), .C1(\ram2e_ufm/RA_35_0_0_0[9] ), 
+    .A1(\RA[9] ), .D0(\ram2e_ufm/N_699 ), .C0(\ram2e_ufm/N_221 ), 
+    .B0(\ram2e_ufm/N_698 ), .A0(\RA[8] ), .DI1(\RA_35[9] ), 
+    .DI0(un2_S_2_i_0_0_o3_RNIHFHN3), .CE(N_126), .CLK(C14M_c), 
+    .F0(un2_S_2_i_0_0_o3_RNIHFHN3), .Q0(\RA[8] ), .F1(\RA_35[9] ), 
+    .Q1(\RA[9] ));
+  SLICE_25 SLICE_25( .D1(\ram2e_ufm/N_845 ), .C1(\ram2e_ufm/N_242 ), 
+    .B1(\RWBank[4] ), .A1(\RA[11] ), .D0(\ram2e_ufm/N_628 ), 
+    .C0(\ram2e_ufm/N_627 ), .B0(\ram2e_ufm/N_624 ), 
+    .A0(\ram2e_ufm/RA_35_2_0_0[10] ), .DI1(\RA_35[11] ), .DI0(\RA_35[10] ), 
+    .CE(N_126), .CLK(C14M_c), .F0(\RA_35[10] ), .Q0(\RA[10] ), 
+    .F1(\RA_35[11] ), .Q1(\RA[11] ));
+  SLICE_26 SLICE_26( .D1(CO0_1), .B1(\RC[1] ), .A1(\RC[2] ), .D0(\RC[2] ), 
+    .B0(\RC[1] ), .A0(CO0_1), .DI1(\RC_3[2] ), .DI0(\RC_3[1] ), .CE(RC12), 
+    .CLK(C14M_c), .F0(\RC_3[1] ), .Q0(\RC[1] ), .F1(\RC_3[2] ), .Q1(\RC[2] ));
+  SLICE_27 SLICE_27( .D1(\ram2e_ufm/N_188 ), .C1(\Din_c[1] ), 
+    .B1(\ram2e_ufm/RWMask[1] ), .D0(\ram2e_ufm/N_188 ), .C0(\Din_c[0] ), 
+    .B0(\ram2e_ufm/RWMask[0] ), .DI1(\RWBank_3[1] ), .DI0(\RWBank_3[0] ), 
+    .CE(N_187_i), .CLK(C14M_c), .F0(\RWBank_3[0] ), .Q0(\RWBank[0] ), 
+    .F1(\RWBank_3[1] ), .Q1(\RWBank[1] ));
+  SLICE_28 SLICE_28( .C1(\ram2e_ufm/RWMask[3] ), .B1(\Din_c[3] ), 
+    .A1(\ram2e_ufm/N_188 ), .D0(\ram2e_ufm/RWMask[2] ), .B0(\Din_c[2] ), 
+    .A0(\ram2e_ufm/N_188 ), .DI1(\RWBank_3[3] ), .DI0(\RWBank_3[2] ), 
+    .CE(N_187_i), .CLK(C14M_c), .F0(\RWBank_3[2] ), .Q0(\RWBank[2] ), 
+    .F1(\RWBank_3[3] ), .Q1(\RWBank[3] ));
+  SLICE_29 SLICE_29( .D1(\ram2e_ufm/N_188 ), .B1(\Din_c[5] ), 
+    .A1(\ram2e_ufm/RWMask[5] ), .D0(\ram2e_ufm/N_188 ), .C0(\Din_c[4] ), 
+    .A0(\ram2e_ufm/RWMask[4] ), .DI1(\RWBank_3[5] ), .DI0(\RWBank_3[4] ), 
+    .CE(N_187_i), .CLK(C14M_c), .F0(\RWBank_3[4] ), .Q0(\RWBank[4] ), 
+    .F1(\RWBank_3[5] ), .Q1(\RWBank[5] ));
+  SLICE_30 SLICE_30( .D1(\ram2e_ufm/N_188 ), .B1(\ram2e_ufm/RWMask[7] ), 
+    .A1(\Din_c[7] ), .D0(\ram2e_ufm/N_188 ), .C0(\ram2e_ufm/RWMask[6] ), 
+    .A0(\Din_c[6] ), .DI1(\RWBank_3[7] ), .DI0(\RWBank_3[6] ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\RWBank_3[6] ), .Q0(\RWBank[6] ), .F1(\RWBank_3[7] ), 
+    .Q1(\RWBank[7] ));
+  SLICE_31 SLICE_31( .D1(\Ain_c[3] ), .C1(\RA[3] ), .B1(\ram2e_ufm/N_182 ), 
+    .A1(\ram2e_ufm/N_186 ), .D0(\RA[0] ), .C0(nC07X_c), .B0(nWE_c), 
+    .A0(\RA[3] ), .DI0(RWSel_2), .CE(un9_VOEEN_0_a2_0_a3_0_a3), .CLK(C14M_c), 
+    .F0(RWSel_2), .Q0(RWSel), .F1(\ram2e_ufm/RA_35_0_0_0[3] ));
+  SLICE_32 SLICE_32( .D1(\ram2e_ufm/Ready3_0_a3_4 ), .C1(\ram2e_ufm/N_885 ), 
+    .B1(\ram2e_ufm/Ready3_0_a3_5 ), .A1(\ram2e_ufm/Ready3_0_a3_3 ), 
+    .C0(Ready3), .A0(Ready), .DI0(N_1026_0), .CLK(C14M_c), .F0(N_1026_0), 
+    .Q0(Ready), .F1(Ready3));
+  SLICE_33 SLICE_33( .D1(S_1), .C1(\ram2e_ufm/N_194 ), .B1(\ram2e_ufm/N_271 ), 
+    .A1(\ram2e_ufm/S_r_i_0_o2[1] ), .D0(S_1), .C0(\ram2e_ufm/N_271 ), 
+    .B0(\S[1] ), .A0(\ram2e_ufm/N_643 ), .DI1(N_362_i), .DI0(\S_s_0_0[0] ), 
+    .CLK(C14M_c), .F0(\S_s_0_0[0] ), .Q0(\S[0] ), .F1(N_362_i), .Q1(\S[1] ));
+  SLICE_34 SLICE_34( .D1(S_1), .C1(\ram2e_ufm/N_194 ), .B1(\S[2] ), 
+    .A1(\S[3] ), .D0(\S[3] ), .C0(\ram2e_ufm/N_194 ), .B0(S_1), .A0(\S[2] ), 
+    .DI1(N_372_i), .DI0(N_361_i), .CLK(C14M_c), .F0(N_361_i), .Q0(\S[2] ), 
+    .F1(N_372_i), .Q1(\S[3] ));
+  SLICE_35 SLICE_35( .D1(\S[0] ), .C1(N_551), .B1(\S[1] ), .A1(\FS[4] ), 
+    .B0(\S[3] ), .A0(\S[2] ), .DI0(N_551), .LSR(N_1078_0), .CLK(C14M_c), 
+    .F0(N_551), .Q0(VOEEN), .F1(BA_0_sqmuxa));
+  SLICE_36 SLICE_36( .D1(\S[1] ), .C1(\ram2e_ufm/N_804 ), .B1(\S[0] ), 
+    .A1(\ram2e_ufm/N_285_i ), .D0(nWE_c), .C0(\ram2e_ufm/N_872 ), 
+    .B0(\ram2e_ufm/N_641 ), .A0(\ram2e_ufm/N_640 ), .DI0(N_370_i), 
+    .CLK(C14M_c), .F0(N_370_i), .Q0(nCAS), .F1(\ram2e_ufm/N_872 ));
+  SLICE_37 SLICE_37( .D1(\S[1] ), .C1(\ram2e_ufm/N_285_i ), .B1(\S[0] ), 
+    .A1(\ram2e_ufm/N_804 ), .D0(\ram2e_ufm/N_615 ), .C0(\ram2e_ufm/N_617 ), 
+    .B0(\ram2e_ufm/N_616 ), .A0(\ram2e_ufm/nRAS_s_i_0_0 ), .DI0(N_358_i), 
+    .CLK(C14M_c), .F0(N_358_i), .Q0(nRAS), .F1(\ram2e_ufm/N_617 ));
+  SLICE_38 SLICE_38( .D1(\ram2e_ufm/N_226 ), .C1(\ram2e_ufm/N_285_i ), 
+    .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\S[2] ), .D0(\ram2e_ufm/N_804 ), 
+    .C0(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ), .B0(\ram2e_ufm/N_615 ), 
+    .A0(\ram2e_ufm/N_866 ), .DI0(N_359_i), .CLK(C14M_c), .F0(N_359_i), 
+    .Q0(nRWE), .F1(\ram2e_ufm/N_615 ));
+  ram2e_ufm_SLICE_39 \ram2e_ufm/SLICE_39 ( .D1(\Din_c[0] ), .C1(\Din_c[3] ), 
+    .B1(\Din_c[5] ), .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .D0(\Din_c[2] ), 
+    .C0(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ), .B0(\ram2e_ufm/N_800 ), 
+    .A0(\Din_c[1] ), .DI0(\ram2e_ufm/CmdBitbangMXO2_3 ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/CmdBitbangMXO2_3 ), 
+    .Q0(\ram2e_ufm/CmdBitbangMXO2 ), .F1(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ));
+  ram2e_ufm_SLICE_40 \ram2e_ufm/SLICE_40 ( .D1(\Din_c[6] ), .C1(\CS[1] ), 
+    .B1(\CS[2] ), .A1(\CS[0] ), .C0(\ram2e_ufm/N_800 ), .B0(\ram2e_ufm/N_851 ), 
+    .DI0(\ram2e_ufm/CmdExecMXO2_3 ), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/CmdExecMXO2_3 ), .Q0(\ram2e_ufm/CmdExecMXO2 ), 
+    .F1(\ram2e_ufm/N_800 ));
+  ram2e_ufm_SLICE_41 \ram2e_ufm/SLICE_41 ( .D1(\Din_c[1] ), .C1(\Din_c[2] ), 
+    .B1(\Din_c[0] ), .A1(\Din_c[4] ), 
+    .D0(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ), .C0(\ram2e_ufm/N_800 ), 
+    .B0(\ram2e_ufm/N_190 ), .A0(\Din_c[7] ), 
+    .DI0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .Q0(\ram2e_ufm/CmdSetRWBankFFChip ), 
+    .F1(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ));
+  ram2e_ufm_SLICE_42 \ram2e_ufm/SLICE_42 ( .D1(\Din_c[6] ), .C1(\Din_c[2] ), 
+    .A1(\Din_c[0] ), .D0(\S[3] ), .C0(\ram2e_ufm/wb_dato[0] ), .A0(\Din_c[0] ), 
+    .DI0(\ram2e_ufm/N_295 ), .CE(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_295 ), .Q0(\ram2e_ufm/LEDEN ), 
+    .F1(\ram2e_ufm/N_212 ));
+  ram2e_ufm_SLICE_43 \ram2e_ufm/SLICE_43 ( .D1(\S[3] ), .C1(\Din_c[1] ), 
+    .B1(\ram2e_ufm/wb_dato[1] ), .D0(\S[3] ), .B0(\ram2e_ufm/wb_dato[0] ), 
+    .A0(\Din_c[0] ), .DI1(\ram2e_ufm/N_307_i ), .DI0(\ram2e_ufm/N_309_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_309_i ), .Q0(\ram2e_ufm/RWMask[0] ), 
+    .F1(\ram2e_ufm/N_307_i ), .Q1(\ram2e_ufm/RWMask[1] ));
+  ram2e_ufm_SLICE_44 \ram2e_ufm/SLICE_44 ( .D1(\S[3] ), 
+    .B1(\ram2e_ufm/wb_dato[3] ), .A1(\Din_c[3] ), .D0(\S[3] ), 
+    .C0(\ram2e_ufm/wb_dato[2] ), .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_302_i ), 
+    .DI0(\ram2e_ufm/N_304_i ), .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_304_i ), .Q0(\ram2e_ufm/RWMask[2] ), 
+    .F1(\ram2e_ufm/N_302_i ), .Q1(\ram2e_ufm/RWMask[3] ));
+  ram2e_ufm_SLICE_45 \ram2e_ufm/SLICE_45 ( .D1(\S[3] ), 
+    .C1(\ram2e_ufm/wb_dato[5] ), .B1(\Din_c[5] ), .D0(\S[3] ), 
+    .C0(\ram2e_ufm/wb_dato[4] ), .A0(\Din_c[4] ), .DI1(\ram2e_ufm/N_301_i ), 
+    .DI0(\ram2e_ufm/N_310_i ), .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_310_i ), .Q0(\ram2e_ufm/RWMask[4] ), 
+    .F1(\ram2e_ufm/N_301_i ), .Q1(\ram2e_ufm/RWMask[5] ));
+  ram2e_ufm_SLICE_46 \ram2e_ufm/SLICE_46 ( .D1(\S[3] ), 
+    .C1(\ram2e_ufm/wb_dato[7] ), .A1(\Din_c[7] ), .D0(\S[3] ), 
+    .C0(\ram2e_ufm/wb_dato[6] ), .A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_296 ), 
+    .DI0(\ram2e_ufm/N_300_i ), .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_300_i ), .Q0(\ram2e_ufm/RWMask[6] ), 
+    .F1(\ram2e_ufm/N_296 ), .Q1(\ram2e_ufm/RWMask[7] ));
+  ram2e_ufm_SLICE_47 \ram2e_ufm/SLICE_47 ( .D1(\ram2e_ufm/wb_adr_7_5_41_0_1 ), 
+    .C1(\Din_c[1] ), .B1(\ram2e_ufm/N_768 ), .A1(\S[2] ), 
+    .D0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), 
+    .B0(\ram2e_ufm/N_793 ), .A0(\FS[10] ), .DI1(\ram2e_ufm/wb_adr_RNO[1] ), 
+    .DI0(\ram2e_ufm/wb_adr_7_i_i[0] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i[0] ), .Q0(\ram2e_ufm/wb_adr[0] ), 
+    .F1(\ram2e_ufm/wb_adr_RNO[1] ), .Q1(\ram2e_ufm/wb_adr[1] ));
+  ram2e_ufm_SLICE_48 \ram2e_ufm/SLICE_48 ( .D1(\S[2] ), .B1(\Din_c[3] ), 
+    .D0(\S[2] ), .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_268_i ), 
+    .DI0(\ram2e_ufm/N_80_i ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_80_i ), .Q0(\ram2e_ufm/wb_adr[2] ), 
+    .F1(\ram2e_ufm/N_268_i ), .Q1(\ram2e_ufm/wb_adr[3] ));
+  ram2e_ufm_SLICE_49 \ram2e_ufm/SLICE_49 ( .C1(\FS[14] ), .B1(\Din_c[5] ), 
+    .A1(\S[2] ), .C0(\FS[14] ), .B0(\Din_c[4] ), .A0(\S[2] ), 
+    .DI1(\ram2e_ufm/N_290 ), .DI0(\ram2e_ufm/N_294 ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_294 ), .Q0(\ram2e_ufm/wb_adr[4] ), .F1(\ram2e_ufm/N_290 ), 
+    .Q1(\ram2e_ufm/wb_adr[5] ));
+  ram2e_ufm_SLICE_50 \ram2e_ufm/SLICE_50 ( .B1(\S[2] ), .A1(\Din_c[7] ), 
+    .D0(\FS[14] ), .C0(\Din_c[6] ), .B0(\S[2] ), .DI1(\ram2e_ufm/N_267_i ), 
+    .DI0(\ram2e_ufm/N_284 ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_284 ), .Q0(\ram2e_ufm/wb_adr[6] ), 
+    .F1(\ram2e_ufm/N_267_i ), .Q1(\ram2e_ufm/wb_adr[7] ));
+  ram2e_ufm_SLICE_51 \ram2e_ufm/SLICE_51 ( .D1(\ram2e_ufm/wb_ack ), 
+    .C1(\FS[14] ), .B1(\ram2e_ufm/N_336 ), .A1(\FS[0] ), .D0(\S[3] ), 
+    .B0(\ram2e_ufm/N_687 ), .A0(\ram2e_ufm/CmdExecMXO2 ), 
+    .DI0(\ram2e_ufm/wb_cyc_stb_RNO ), 
+    .CE(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_cyc_stb_RNO ), .Q0(\ram2e_ufm/wb_cyc_stb ), 
+    .F1(\ram2e_ufm/N_687 ));
+  ram2e_ufm_SLICE_52 \ram2e_ufm/SLICE_52 ( .D1(\ram2e_ufm/wb_dati_7_0_0_0[1] ), 
+    .C1(\ram2e_ufm/N_611 ), .B1(\ram2e_ufm/N_793 ), .A1(\ram2e_ufm/N_849 ), 
+    .D0(\ram2e_ufm/N_856 ), .C0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ), 
+    .B0(\ram2e_ufm/wb_adr[0] ), .A0(\S[2] ), .DI1(\ram2e_ufm/wb_dati_7[1] ), 
+    .DI0(\ram2e_ufm/wb_dati_7[0] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[0] ), .Q0(\ram2e_ufm/wb_dati[0] ), 
+    .F1(\ram2e_ufm/wb_dati_7[1] ), .Q1(\ram2e_ufm/wb_dati[1] ));
+  ram2e_ufm_SLICE_53 \ram2e_ufm/SLICE_53 ( .D1(\ram2e_ufm/N_849 ), 
+    .C1(\ram2e_ufm/N_611 ), .B1(\ram2e_ufm/N_783 ), 
+    .A1(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .D0(\S[2] ), 
+    .C0(\ram2e_ufm/wb_adr[2] ), .B0(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), 
+    .A0(\ram2e_ufm/N_760 ), .DI1(\ram2e_ufm/wb_dati_7[3] ), 
+    .DI0(\ram2e_ufm/wb_dati_7[2] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[2] ), .Q0(\ram2e_ufm/wb_dati[2] ), 
+    .F1(\ram2e_ufm/wb_dati_7[3] ), .Q1(\ram2e_ufm/wb_dati[3] ));
+  ram2e_ufm_SLICE_54 \ram2e_ufm/SLICE_54 ( 
+    .D1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C1(\ram2e_ufm/N_760 ), 
+    .B1(\ram2e_ufm/wb_adr[5] ), .A1(\S[2] ), .D0(\ram2e_ufm/N_763 ), 
+    .C0(\ram2e_ufm/N_760 ), .B0(\ram2e_ufm/N_757 ), 
+    .A0(\ram2e_ufm/wb_dati_7_0_0_0[4] ), .DI1(\ram2e_ufm/wb_dati_7[5] ), 
+    .DI0(\ram2e_ufm/wb_dati_7[4] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[4] ), .Q0(\ram2e_ufm/wb_dati[4] ), 
+    .F1(\ram2e_ufm/wb_dati_7[5] ), .Q1(\ram2e_ufm/wb_dati[5] ));
+  ram2e_ufm_SLICE_55 \ram2e_ufm/SLICE_55 ( 
+    .D1(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), .C1(\ram2e_ufm/N_604 ), 
+    .B1(\ram2e_ufm/N_602 ), .A1(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), 
+    .D0(\ram2e_ufm/N_757 ), .C0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), 
+    .B0(\ram2e_ufm/N_849 ), .A0(\ram2e_ufm/N_793 ), 
+    .DI1(\ram2e_ufm/wb_dati_7[7] ), .DI0(\ram2e_ufm/wb_dati_7[6] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_dati_7[6] ), .Q0(\ram2e_ufm/wb_dati[6] ), 
+    .F1(\ram2e_ufm/wb_dati_7[7] ), .Q1(\ram2e_ufm/wb_dati[7] ));
+  ram2e_ufm_SLICE_56 \ram2e_ufm/SLICE_56 ( .D1(\S[3] ), .C1(\S[1] ), 
+    .B1(\S[0] ), .A1(\FS[14] ), .D0(\FS[13] ), .C0(\FS[12] ), 
+    .B0(\ram2e_ufm/wb_reqc_1 ), .A0(\FS[11] ), .DI0(\ram2e_ufm/wb_reqc_i ), 
+    .CE(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ), .LSR(\S[2] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_reqc_i ), .Q0(\ram2e_ufm/wb_req ), 
+    .F1(\ram2e_ufm/wb_reqc_1 ));
+  ram2e_ufm_SLICE_57 \ram2e_ufm/SLICE_57 ( .D1(\FS[4] ), .C1(\FS[14] ), 
+    .B1(\FS[2] ), .A1(\FS[15] ), .C0(\FS[14] ), .A0(\FS[15] ), 
+    .DI0(\ram2e_ufm/wb_rst8 ), .LSR(\ram2e_ufm/wb_rst16_i ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_rst8 ), .Q0(\ram2e_ufm/wb_rst ), 
+    .F1(\ram2e_ufm/Ready3_0_a3_4 ));
+  ram2e_ufm_SLICE_58 \ram2e_ufm/SLICE_58 ( .D1(\ram2e_ufm/N_799 ), 
+    .C1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), .B1(\ram2e_ufm/N_885 ), 
+    .A1(\FS[12] ), .D0(\ram2e_ufm/N_799 ), 
+    .C0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ), .B0(\ram2e_ufm/N_208 ), 
+    .A0(\FS[13] ), .DI0(\ram2e_ufm/wb_we_RNO ), .CE(\ram2e_ufm/wb_we_RNO_0 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/wb_we_RNO ), .Q0(\ram2e_ufm/wb_we ), 
+    .F1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ));
+  ram2e_ufm_SUM0_i_m3_0_SLICE_59 \ram2e_ufm/SUM0_i_m3_0/SLICE_59 ( 
+    .D1(\Din_c[5] ), .C1(\CS[1] ), .B1(\Din_c[3] ), .D0(\Din_c[7] ), 
+    .C0(\Din_c[5] ), .B0(\Din_c[3] ), .M0(\Din_c[1] ), 
+    .OFX0(\ram2e_ufm/N_338 ));
+  ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 
+    \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60 ( 
+    .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), .C1(\ram2e_ufm/N_193 ), 
+    .B1(\CS[0] ), .A1(\Din_c[6] ), .C0(CO0_0), .B0(\CmdTout[2] ), 
+    .A0(\CmdTout[1] ), .M0(RWSel), .OFX0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ));
+  ram2e_ufm_CKE_7_SLICE_61 \ram2e_ufm/CKE_7/SLICE_61 ( .D1(\ram2e_ufm/N_821 ), 
+    .C1(\ram2e_ufm/N_817 ), .A1(\RC[1] ), .D0(\ram2e_ufm/N_804 ), .B0(nWE_c), 
+    .A0(\S[1] ), .M0(\ram2e_ufm/CKE_7_sm0 ), .OFX0(\ram2e_ufm/CKE_7 ));
+  ram2e_ufm_SLICE_62 \ram2e_ufm/SLICE_62 ( .D1(\Din_c[6] ), 
+    .C1(\ram2e_ufm/N_851 ), .B1(\CS[2] ), .A1(\CS[1] ), .D0(\ram2e_ufm/N_234 ), 
+    .C0(\ram2e_ufm/SUM0_i_a3_4_0 ), .B0(\CS[2] ), .A0(\CS[1] ), 
+    .F0(\ram2e_ufm/N_720_tz ), .F1(\ram2e_ufm/SUM0_i_a3_4_0 ));
+  ram2e_ufm_SLICE_63 \ram2e_ufm/SLICE_63 ( .D1(\CS[2] ), 
+    .C1(\ram2e_ufm/SUM0_i_0 ), .B1(\ram2e_ufm/N_350 ), .A1(\CS[0] ), 
+    .D0(\CS[0] ), .C0(\ram2e_ufm/SUM0_i_3 ), .B0(\ram2e_ufm/SUM0_i_1 ), 
+    .A0(\ram2e_ufm/N_187 ), .F0(\ram2e_ufm/SUM0_i_4 ), 
+    .F1(\ram2e_ufm/SUM0_i_1 ));
+  ram2e_ufm_SLICE_64 \ram2e_ufm/SLICE_64 ( .D1(\ram2e_ufm/N_793 ), 
+    .C1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[11] ), .C0(\ram2e_ufm/N_856 ), 
+    .B0(\FS[13] ), .A0(\ram2e_ufm/N_755 ), .F0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), 
+    .F1(\ram2e_ufm/N_755 ));
+  ram2e_ufm_SLICE_65 \ram2e_ufm/SLICE_65 ( .D1(\ram2e_ufm/N_193 ), 
+    .C1(\Din_c[0] ), .B1(\CS[0] ), .A1(\Din_c[6] ), .D0(\ram2e_ufm/N_345 ), 
+    .C0(\ram2e_ufm/N_735 ), .B0(\CS[0] ), .A0(\CS[1] ), 
+    .F0(\ram2e_ufm/SUM0_i_0 ), .F1(\ram2e_ufm/N_735 ));
+  ram2e_ufm_SLICE_66 \ram2e_ufm/SLICE_66 ( .D1(\FS[14] ), 
+    .C1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), 
+    .B1(\ram2e_ufm/N_777 ), .A1(\ram2e_ufm/wb_ack ), 
+    .D0(\ram2e_ufm/CmdExecMXO2 ), .C0(\ram2e_ufm/wb_ack ), 
+    .B0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ), 
+    .A0(\ram2e_ufm/N_187 ), 
+    .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), 
+    .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ));
+  ram2e_ufm_SLICE_67 \ram2e_ufm/SLICE_67 ( .D1(\FS[1] ), .B1(\FS[2] ), 
+    .A1(\FS[3] ), .D0(\S[1] ), .C0(\FS[4] ), .B0(\ram2e_ufm/N_250 ), 
+    .A0(\FS[3] ), .F0(\ram2e_ufm/N_256 ), .F1(\ram2e_ufm/N_250 ));
+  ram2e_ufm_SLICE_68 \ram2e_ufm/SLICE_68 ( .D1(\ram2e_ufm/N_783 ), 
+    .C1(\FS[8] ), .B1(\FS[9] ), .A1(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), 
+    .D0(\FS[10] ), .C0(\FS[12] ), .B0(\FS[8] ), .A0(\FS[11] ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .F1(\ram2e_ufm/wb_adr_7_i_i_3[0] ));
+  ram2e_ufm_SLICE_69 \ram2e_ufm/SLICE_69 ( .D1(\FS[0] ), .C1(\FS[15] ), 
+    .B1(\ram2e_ufm/wb_rst16_i ), .A1(\ram2e_ufm/N_254 ), .D0(\S[2] ), 
+    .C0(\S[3] ), .B0(\S[0] ), .A0(\S[1] ), .F0(\ram2e_ufm/wb_rst16_i ), 
+    .F1(\ram2e_ufm/N_641 ));
+  ram2e_ufm_SLICE_70 \ram2e_ufm/SLICE_70 ( .C1(\FS[14] ), .B1(\FS[8] ), 
+    .A1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/N_876 ), .C0(\ram2e_ufm/N_807 ), 
+    .B0(\FS[13] ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_604 ), 
+    .F1(\ram2e_ufm/N_807 ));
+  ram2e_ufm_SLICE_71 \ram2e_ufm/SLICE_71 ( .C1(\ram2e_ufm/N_784 ), 
+    .B1(\FS[4] ), .A1(\FS[3] ), .D0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), 
+    .F0(\ram2e_ufm/N_784 ), .F1(\ram2e_ufm/N_801 ));
+  ram2e_ufm_SLICE_72 \ram2e_ufm/SLICE_72 ( .D1(\S[0] ), .C1(\ram2e_ufm/N_560 ), 
+    .B1(\RWBank[5] ), .A1(\FS[4] ), .D0(\S[2] ), .B0(\S[3] ), .A0(\S[1] ), 
+    .F0(\ram2e_ufm/N_560 ), .F1(\BA_4[0] ));
+  ram2e_ufm_SLICE_73 \ram2e_ufm/SLICE_73 ( .D1(\ram2e_ufm/N_184 ), 
+    .C1(\ram2e_ufm/N_611 ), .B1(\ram2e_ufm/N_873 ), .A1(\ram2e_ufm/N_781 ), 
+    .D0(\FS[10] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[11] ), 
+    .F0(\ram2e_ufm/N_873 ), .F1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ));
+  ram2e_ufm_SLICE_74 \ram2e_ufm/SLICE_74 ( .C1(\ram2e_ufm/N_845 ), 
+    .B1(\ram2e_ufm/N_625 ), .A1(\RWBank[3] ), .D0(\S[2] ), .C0(\S[0] ), 
+    .B0(\S[3] ), .A0(\S[1] ), .F0(\ram2e_ufm/N_845 ), 
+    .F1(\ram2e_ufm/RA_35_2_0_0[10] ));
+  ram2e_ufm_SLICE_75 \ram2e_ufm/SLICE_75 ( .D1(\FS[10] ), .B1(\FS[9] ), 
+    .A1(\FS[11] ), .D0(\FS[13] ), .C0(\ram2e_ufm/wb_ack ), 
+    .B0(\ram2e_ufm/N_876 ), .A0(\FS[12] ), 
+    .F0(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), 
+    .F1(\ram2e_ufm/N_876 ));
+  ram2e_ufm_SLICE_76 \ram2e_ufm/SLICE_76 ( .D1(\FS[10] ), .C1(\FS[11] ), 
+    .D0(\FS[12] ), .C0(\ram2e_ufm/N_811 ), .B0(\FS[13] ), 
+    .A0(\ram2e_ufm/N_206 ), .F0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), 
+    .F1(\ram2e_ufm/N_811 ));
+  ram2e_ufm_SLICE_77 \ram2e_ufm/SLICE_77 ( .C1(\ram2e_ufm/N_185 ), .B1(RWSel), 
+    .A1(\CS[0] ), .D0(\S[3] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[0] ), 
+    .F0(\ram2e_ufm/N_185 ), .F1(\ram2e_ufm/N_215 ));
+  ram2e_ufm_SLICE_78 \ram2e_ufm/SLICE_78 ( .D1(\S[0] ), .B1(\S[1] ), 
+    .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\RWBank[1] ), .B0(\S[3] ), .A0(\S[2] ), 
+    .F0(\ram2e_ufm/N_699 ), .F1(\ram2e_ufm/S_r_i_0_o2[1] ));
+  ram2e_ufm_SLICE_79 \ram2e_ufm/SLICE_79 ( .D1(CmdLEDSet), 
+    .C1(\ram2e_ufm/N_187 ), .B1(\ram2e_ufm/N_807 ), 
+    .A1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), .D0(\S[2] ), 
+    .C0(RWSel), .B0(\ram2e_ufm/S_r_i_0_o2[1] ), .A0(\S[3] ), 
+    .F0(\ram2e_ufm/N_187 ), .F1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ));
+  ram2e_ufm_SLICE_80 \ram2e_ufm/SLICE_80 ( .D1(\S[1] ), .C1(\S[0] ), 
+    .B1(\FS[15] ), .A1(N_551), .D0(\ram2e_ufm/CmdBitbangMXO2 ), 
+    .C0(\ram2e_ufm/N_777 ), .B0(RWSel), .A0(\ram2e_ufm/N_185 ), 
+    .F0(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .F1(\ram2e_ufm/N_777 ));
+  ram2e_ufm_SLICE_81 \ram2e_ufm/SLICE_81 ( .D1(\FS[14] ), .C1(\FS[9] ), 
+    .B1(\FS[8] ), .A1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/N_811 ), 
+    .C0(\FS[12] ), .B0(\ram2e_ufm/N_856 ), .A0(\FS[13] ), 
+    .F0(\ram2e_ufm/N_757 ), .F1(\ram2e_ufm/N_856 ));
+  ram2e_ufm_SLICE_82 \ram2e_ufm/SLICE_82 ( .D1(\Din_c[6] ), 
+    .C1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .B1(\CS[0] ), 
+    .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ), 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ), 
+    .C0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), 
+    .B0(\ram2e_ufm/N_185 ), .A0(\ram2e_ufm/N_637 ), .F0(un1_CS_0_sqmuxa_i), 
+    .F1(\ram2e_ufm/N_637 ));
+  ram2e_ufm_SLICE_83 \ram2e_ufm/SLICE_83 ( .D1(\Din_c[6] ), .B1(\CS[2] ), 
+    .A1(\ram2e_ufm/N_851 ), .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ), 
+    .C0(\ram2e_ufm/N_592 ), .B0(RWSel), .A0(\CS[0] ), 
+    .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ));
+  ram2e_ufm_SLICE_84 \ram2e_ufm/SLICE_84 ( .D1(\CS[2] ), 
+    .C1(\ram2e_ufm/N_212 ), .B1(\ram2e_ufm/N_850 ), .A1(\Din_c[4] ), 
+    .D0(\ram2e_ufm/N_720_tz ), .C0(\ram2e_ufm/N_187 ), .B0(\ram2e_ufm/N_886 ), 
+    .A0(\CS[1] ), .F0(\ram2e_ufm/SUM0_i_3 ), .F1(\ram2e_ufm/N_886 ));
+  ram2e_ufm_SLICE_85 \ram2e_ufm/SLICE_85 ( .D1(\FS[13] ), .C1(\FS[12] ), 
+    .B1(\FS[14] ), .A1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/N_187 ), 
+    .C0(\ram2e_ufm/N_793 ), 
+    .B0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), .A0(CmdRWMaskSet), 
+    .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .F1(\ram2e_ufm/N_793 ));
+  ram2e_ufm_SLICE_86 \ram2e_ufm/SLICE_86 ( .D1(\Din_c[0] ), .A1(\S[2] ), 
+    .D0(\ram2e_ufm/N_634 ), .C0(\ram2e_ufm/N_753 ), 
+    .B0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), .A0(\ram2e_ufm/wb_adr_7_i_i_3[0] ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), .F1(\ram2e_ufm/N_634 ));
+  ram2e_ufm_SLICE_87 \ram2e_ufm/SLICE_87 ( 
+    .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C1(\Din_c[1] ), 
+    .B1(\ram2e_ufm/N_190 ), .A1(\ram2e_ufm/N_212 ), .D0(\ram2e_ufm/N_886 ), 
+    .C0(\ram2e_ufm/N_234 ), .B0(\CS[1] ), .F0(\ram2e_ufm/N_592 ), 
+    .F1(\ram2e_ufm/N_234 ));
+  ram2e_ufm_SLICE_88 \ram2e_ufm/SLICE_88 ( .D1(\FS[10] ), .B1(\FS[11] ), 
+    .D0(\ram2e_ufm/N_793 ), .C0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), 
+    .B0(\ram2e_ufm/N_206 ), .A0(\ram2e_ufm/N_876 ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ));
+  ram2e_ufm_SLICE_89 \ram2e_ufm/SLICE_89 ( .D1(\FS[13] ), .C1(\FS[14] ), 
+    .A1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), 
+    .C0(\ram2e_ufm/N_783 ), .B0(\S[2] ), .A0(\ram2e_ufm/wb_adr[3] ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .F1(\ram2e_ufm/N_783 ));
+  ram2e_ufm_SLICE_90 \ram2e_ufm/SLICE_90 ( .D1(\ram2e_ufm/N_206 ), 
+    .C1(\FS[10] ), .B1(\FS[11] ), .A1(\FS[12] ), .D0(\ram2e_ufm/wb_adr[6] ), 
+    .C0(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ), .B0(\S[2] ), 
+    .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ));
+  ram2e_ufm_SLICE_91 \ram2e_ufm/SLICE_91 ( .D1(\RC[2] ), .C1(\RC[1] ), 
+    .B1(CO0_1), .A1(\ram2e_ufm/N_817 ), .D0(\ram2e_ufm/N_784 ), 
+    .C0(\ram2e_ufm/N_890 ), .B0(\ram2e_ufm/N_285_i ), .A0(\ram2e_ufm/N_256 ), 
+    .F0(\ram2e_ufm/nRAS_s_i_0_0 ), .F1(\ram2e_ufm/N_890 ));
+  ram2e_ufm_SLICE_92 \ram2e_ufm/SLICE_92 ( .D1(nWE_c), .C1(\ram2e_ufm/N_804 ), 
+    .B1(\S[1] ), .A1(N_551), .D0(\S[0] ), .C0(\ram2e_ufm/N_890 ), 
+    .B0(\ram2e_ufm/N_220 ), .A0(\ram2e_ufm/N_285_i ), .F0(\ram2e_ufm/N_640 ), 
+    .F1(\ram2e_ufm/N_220 ));
+  ram2e_ufm_SLICE_93 \ram2e_ufm/SLICE_93 ( .D1(\FS[8] ), .C1(\FS[9] ), 
+    .B1(\FS[10] ), .A1(\FS[11] ), .D0(\ram2e_ufm/N_196 ), 
+    .B0(\ram2e_ufm/N_783 ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_760 ), 
+    .F1(\ram2e_ufm/N_196 ));
+  ram2e_ufm_SLICE_94 \ram2e_ufm/SLICE_94 ( .C1(\Din_c[4] ), .B1(\Din_c[7] ), 
+    .D0(\ram2e_ufm/N_243 ), .C0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), 
+    .B0(\Din_c[0] ), .A0(\CS[2] ), .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ));
+  ram2e_ufm_SLICE_95 \ram2e_ufm/SLICE_95 ( .D1(\S[1] ), .C1(\S[3] ), 
+    .B1(\S[0] ), .A1(\S[2] ), .D0(\RA[4] ), .C0(\ram2e_ufm/N_182 ), 
+    .B0(\Ain_c[4] ), .A0(\ram2e_ufm/N_186 ), .F0(\ram2e_ufm/RA_35_0_0_0[4] ), 
+    .F1(\ram2e_ufm/N_182 ));
+  ram2e_ufm_SLICE_96 \ram2e_ufm/SLICE_96 ( .D1(\S[1] ), .C1(\S[2] ), 
+    .B1(\S[0] ), .A1(\S[3] ), .D0(\ram2e_ufm/N_182 ), .C0(\ram2e_ufm/N_186 ), 
+    .B0(\Ain_c[6] ), .A0(\RA[6] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[6] ), 
+    .F1(\ram2e_ufm/N_186 ));
+  ram2e_ufm_SLICE_97 \ram2e_ufm/SLICE_97 ( .D1(\ram2e_ufm/N_873 ), 
+    .C1(\FS[13] ), .B1(\FS[12] ), .D0(\ram2e_ufm/wb_adr[1] ), 
+    .C0(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ), .B0(\ram2e_ufm/N_781 ), 
+    .A0(\S[2] ), .F0(\ram2e_ufm/wb_dati_7_0_0_0[1] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ));
+  ram2e_ufm_SLICE_98 \ram2e_ufm/SLICE_98 ( .D1(\FS[14] ), 
+    .C1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), 
+    .C0(\ram2e_ufm/N_781 ), .B0(\ram2e_ufm/wb_adr[7] ), .A0(\S[2] ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), .F1(\ram2e_ufm/N_781 ));
+  ram2e_ufm_SLICE_99 \ram2e_ufm/SLICE_99 ( .D1(\FS[11] ), .C1(\FS[8] ), 
+    .A1(\FS[10] ), .D0(\ram2e_ufm/N_565 ), 
+    .C0(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ), .B0(\FS[12] ), 
+    .A0(\ram2e_ufm/N_781 ), .F0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), 
+    .F1(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ));
+  ram2e_ufm_SLICE_100 \ram2e_ufm/SLICE_100 ( .D1(\Din_c[1] ), .C1(\Din_c[5] ), 
+    .B1(\Din_c[3] ), .A1(\Din_c[2] ), .D0(\Din_c[7] ), .C0(\CS[2] ), 
+    .B0(\ram2e_ufm/N_243 ), .A0(\Din_c[4] ), .F0(\ram2e_ufm/N_345 ), 
+    .F1(\ram2e_ufm/N_243 ));
+  ram2e_ufm_SLICE_101 \ram2e_ufm/SLICE_101 ( .C1(\Din_c[5] ), .B1(\Din_c[3] ), 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ), .C0(\CS[1] ), 
+    .B0(\ram2e_ufm/N_850 ), .A0(\ram2e_ufm/N_190 ), 
+    .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .F1(\ram2e_ufm/N_190 ));
+  ram2e_ufm_SLICE_102 \ram2e_ufm/SLICE_102 ( .C1(\S[1] ), .B1(\S[3] ), 
+    .A1(\S[2] ), .D0(\ram2e_ufm/N_817 ), .C0(\ram2e_ufm/CKE_7s2_0_0_0 ), 
+    .B0(\ram2e_ufm/N_220 ), .F0(\ram2e_ufm/CKE_7_sm0 ), .F1(\ram2e_ufm/N_817 ));
+  ram2e_ufm_SLICE_103 \ram2e_ufm/SLICE_103 ( .D1(\FS[13] ), .C1(\FS[12] ), 
+    .D0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), .C0(\ram2e_ufm/N_184 ), 
+    .B0(\ram2e_ufm/N_204 ), .A0(\ram2e_ufm/N_799 ), 
+    .F0(\ram2e_ufm/wb_adr_7_5_41_0_1 ), .F1(\ram2e_ufm/N_184 ));
+  ram2e_ufm_SLICE_104 \ram2e_ufm/SLICE_104 ( .D1(\FS[8] ), .C1(\FS[10] ), 
+    .B1(\FS[9] ), .A1(\FS[11] ), .C0(\ram2e_ufm/N_595 ), .A0(\FS[12] ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .F1(\ram2e_ufm/N_595 ));
+  ram2e_ufm_SLICE_105 \ram2e_ufm/SLICE_105 ( .D1(\ram2e_ufm/nRWE_s_i_0_63_1 ), 
+    .C1(\ram2e_ufm/N_285_i ), .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\S[3] ), 
+    .D0(\FS[0] ), .C0(\ram2e_ufm/wb_rst16_i ), .A0(\FS[15] ), 
+    .F0(\ram2e_ufm/N_285_i ), .F1(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ));
+  ram2e_ufm_SLICE_106 \ram2e_ufm/SLICE_106 ( .C1(\S[0] ), .B1(\S[1] ), 
+    .D0(\RA[10] ), .C0(\S[2] ), .B0(\ram2e_ufm/N_194 ), 
+    .A0(\ram2e_ufm/S_r_i_0_o2[1] ), .F0(\ram2e_ufm/N_624 ), 
+    .F1(\ram2e_ufm/N_194 ));
+  ram2e_ufm_SLICE_107 \ram2e_ufm/SLICE_107 ( .D1(\S[3] ), .C1(\S[2] ), 
+    .B1(\S[0] ), .A1(\FS[4] ), .D0(\FS[5] ), .C0(\FS[3] ), .B0(\FS[8] ), 
+    .A0(\ram2e_ufm/N_792 ), .F0(\ram2e_ufm/N_659 ), .F1(\ram2e_ufm/N_792 ));
+  ram2e_ufm_SLICE_108 \ram2e_ufm/SLICE_108 ( .D1(\FS[7] ), 
+    .C1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ), .B1(\FS[4] ), 
+    .A1(\FS[5] ), .D0(\ram2e_ufm/wb_req ), .C0(\ram2e_ufm/N_336 ), 
+    .B0(\FS[0] ), .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), 
+    .F1(\ram2e_ufm/N_336 ));
+  ram2e_ufm_SLICE_109 \ram2e_ufm/SLICE_109 ( .C1(\FS[14] ), .B1(\S[2] ), 
+    .D0(\ram2e_ufm/N_799 ), .C0(\FS[11] ), .B0(\ram2e_ufm/N_184 ), 
+    .A0(\ram2e_ufm/N_634 ), .F0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), 
+    .F1(\ram2e_ufm/N_799 ));
+  ram2e_ufm_SLICE_110 \ram2e_ufm/SLICE_110 ( .D1(\FS[9] ), .C1(\FS[8] ), 
+    .B1(\FS[10] ), .A1(\FS[11] ), .C0(\ram2e_ufm/wb_ack ), 
+    .B0(\ram2e_ufm/N_885 ), 
+    .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), 
+    .F1(\ram2e_ufm/N_885 ));
+  ram2e_ufm_SLICE_111 \ram2e_ufm/SLICE_111 ( .D1(\FS[12] ), 
+    .C1(\ram2e_ufm/N_807 ), .A1(\ram2e_ufm/N_553 ), .D0(\FS[13] ), 
+    .C0(\ram2e_ufm/N_811 ), .B0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), 
+    .A0(\FS[9] ), .F0(\ram2e_ufm/N_553 ), .F1(\ram2e_ufm/N_611 ));
+  ram2e_ufm_SLICE_112 \ram2e_ufm/SLICE_112 ( .D1(\S[1] ), 
+    .C1(\ram2e_ufm/N_285_i ), .B1(\S[0] ), .D0(nWE_c), .C0(\ram2e_ufm/N_866 ), 
+    .B0(nEN80_c), .A0(\S[2] ), .F0(\ram2e_ufm/N_616 ), .F1(\ram2e_ufm/N_866 ));
+  ram2e_ufm_SLICE_113 \ram2e_ufm/SLICE_113 ( .D1(nEN80_c), .C1(\S[2] ), 
+    .B1(\S[3] ), .D0(nWE_c), .C0(\ram2e_ufm/N_804 ), .B0(\S[0] ), .A0(\S[1] ), 
+    .F0(\ram2e_ufm/N_628 ), .F1(\ram2e_ufm/N_804 ));
+  ram2e_ufm_SLICE_114 \ram2e_ufm/SLICE_114 ( .D1(\FS[10] ), .C1(\FS[8] ), 
+    .B1(\FS[9] ), .D0(\FS[11] ), .C0(\ram2e_ufm/N_799 ), .B0(\FS[12] ), 
+    .A0(\ram2e_ufm/N_241_i ), .F0(\ram2e_ufm/N_768 ), .F1(\ram2e_ufm/N_241_i ));
+  ram2e_ufm_SLICE_115 \ram2e_ufm/SLICE_115 ( .D1(\S[1] ), .B1(\S[2] ), 
+    .D0(\S[0] ), .C0(\ram2e_ufm/N_221 ), .B0(nEN80_c), .A0(\S[3] ), 
+    .F0(\ram2e_ufm/CKE_7s2_0_0_0 ), .F1(\ram2e_ufm/N_221 ));
+  ram2e_ufm_SLICE_116 \ram2e_ufm/SLICE_116 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ), 
+    .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .A1(\ram2e_ufm/N_814 ), 
+    .D0(\Din_c[0] ), .B0(\Din_c[1] ), .A0(\Din_c[2] ), .F0(\ram2e_ufm/N_814 ), 
+    .F1(\ram2e_ufm/N_851 ));
+  ram2e_ufm_SLICE_117 \ram2e_ufm/SLICE_117 ( .D1(\S[1] ), .C1(\S[0] ), 
+    .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[0] ), .B0(\S[3] ), 
+    .A0(\S[2] ), .F0(N_225_i), .F1(\ram2e_ufm/N_643 ));
+  ram2e_ufm_SLICE_118 \ram2e_ufm/SLICE_118 ( .D1(\S[2] ), .C1(\S[1] ), 
+    .B1(\S[0] ), .A1(\S[3] ), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[0] ), 
+    .A0(\S[3] ), .F0(N_201_i), .F1(RC12));
+  ram2e_ufm_SLICE_119 \ram2e_ufm/SLICE_119 ( .D1(\S[0] ), .C1(\S[1] ), 
+    .B1(\S[3] ), .A1(\S[2] ), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[3] ), 
+    .A0(\S[2] ), .F0(N_126), .F1(N_185_i));
+  ram2e_ufm_SLICE_120 \ram2e_ufm/SLICE_120 ( .D1(\S[0] ), .C1(\FS[15] ), 
+    .B1(\S[3] ), .A1(\RWBank[0] ), .D0(\S[0] ), .C0(\FS[15] ), .B0(\S[3] ), 
+    .A0(\RWBank[0] ), .F0(N_507_i), .F1(N_508));
+  ram2e_ufm_SLICE_121 \ram2e_ufm/SLICE_121 ( .D1(\S[1] ), .C1(\S[3] ), 
+    .B1(\S[2] ), .A1(\S[0] ), .D0(\S[1] ), .C0(\S[3] ), .B0(\S[2] ), 
+    .A0(\S[0] ), .F0(\ram2e_ufm/N_242 ), .F1(Vout3));
+  ram2e_ufm_SLICE_122 \ram2e_ufm/SLICE_122 ( .D1(\FS[1] ), .C1(\FS[4] ), 
+    .B1(\FS[2] ), .A1(\FS[3] ), .D0(\FS[1] ), .C0(\FS[4] ), .B0(\FS[2] ), 
+    .A0(\FS[3] ), .F0(\ram2e_ufm/N_254 ), .F1(\ram2e_ufm/nRWE_s_i_0_63_1 ));
+  ram2e_ufm_SLICE_123 \ram2e_ufm/SLICE_123 ( .D1(\FS[11] ), .C1(\FS[8] ), 
+    .B1(\FS[9] ), .D0(\FS[11] ), .C0(\FS[8] ), .B0(\FS[9] ), .A0(\FS[10] ), 
+    .F0(\ram2e_ufm/N_849 ), .F1(\ram2e_ufm/N_204 ));
+  ram2e_ufm_SLICE_124 \ram2e_ufm/SLICE_124 ( .D1(\FS[12] ), 
+    .C1(\ram2e_ufm/N_784 ), .B1(\FS[4] ), .A1(\FS[3] ), .D0(\ram2e_ufm/N_784 ), 
+    .C0(\FS[1] ), .B0(\FS[4] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_684 ), 
+    .F1(\ram2e_ufm/RA_35_0_0_0[5] ));
+  ram2e_ufm_SLICE_125 \ram2e_ufm/SLICE_125 ( .D1(\FS[13] ), .C1(\FS[8] ), 
+    .B1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[9] ), .C0(\ram2e_ufm/N_793 ), 
+    .B0(\FS[11] ), .A0(\FS[8] ), .F0(\ram2e_ufm/N_763 ), 
+    .F1(\ram2e_ufm/N_565 ));
+  ram2e_ufm_SLICE_126 \ram2e_ufm/SLICE_126 ( .D1(\FS[10] ), .C1(\FS[12] ), 
+    .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[10] ), .C0(\ram2e_ufm/N_781 ), 
+    .B0(\FS[9] ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_753 ), 
+    .F1(\ram2e_ufm/N_208 ));
+  ram2e_ufm_SLICE_127 \ram2e_ufm/SLICE_127 ( .D1(\S[0] ), .C1(\S[1] ), 
+    .B1(\S[3] ), .A1(\S[2] ), .D0(\S[0] ), .C0(\RWBank[7] ), .B0(\S[3] ), 
+    .A0(\S[2] ), .F0(\ram2e_ufm/N_698 ), .F1(un9_VOEEN_0_a2_0_a3_0_a3));
+  ram2e_ufm_SLICE_128 \ram2e_ufm/SLICE_128 ( .D1(\FS[13] ), .C1(\FS[11] ), 
+    .B1(\FS[12] ), .A1(\FS[10] ), .D0(\FS[13] ), .C0(\FS[12] ), .A0(\FS[10] ), 
+    .F0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ));
+  ram2e_ufm_SLICE_129 \ram2e_ufm/SLICE_129 ( .D1(\RWBank[6] ), .C1(\S[0] ), 
+    .B1(\FS[4] ), .A1(\ram2e_ufm/N_560 ), .D0(N_551), .C0(\S[0] ), 
+    .B0(\FS[4] ), .A0(\FS[1] ), .F0(\ram2e_ufm/N_627 ), .F1(\BA_4[1] ));
+  ram2e_ufm_SLICE_130 \ram2e_ufm/SLICE_130 ( .D1(\ram2e_ufm/N_185 ), 
+    .C1(RWSel), .D0(\ram2e_ufm/N_185 ), .C0(RWSel), .B0(\ram2e_ufm/N_777 ), 
+    .A0(\ram2e_ufm/CmdExecMXO2 ), .F0(\ram2e_ufm/wb_we_RNO_0 ), .F1(N_187_i));
+  ram2e_ufm_SLICE_131 \ram2e_ufm/SLICE_131 ( .D1(\FS[13] ), .C1(\FS[12] ), 
+    .B1(\FS[1] ), .A1(\FS[3] ), .D0(\FS[13] ), .C0(\ram2e_ufm/N_856 ), 
+    .B0(\ram2e_ufm/N_811 ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_602 ), 
+    .F1(\ram2e_ufm/Ready3_0_a3_5 ));
+  ram2e_ufm_SLICE_132 \ram2e_ufm/SLICE_132 ( .D1(\ram2e_ufm/N_182 ), 
+    .C1(\Ain_c[0] ), .B1(\ram2e_ufm/N_186 ), .A1(\RA[0] ), 
+    .D0(\ram2e_ufm/N_182 ), .C0(\Ain_c[7] ), .B0(\ram2e_ufm/N_186 ), 
+    .A0(\RA[7] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[7] ), 
+    .F1(\ram2e_ufm/RA_35_0_0_1[0] ));
+  ram2e_ufm_SLICE_133 \ram2e_ufm/SLICE_133 ( .D1(\Din_c[0] ), .C1(\Din_c[2] ), 
+    .B1(RWSel), .A1(\Din_c[4] ), .D0(\ram2e_ufm/N_338 ), .C0(\Din_c[2] ), 
+    .B0(\Din_c[4] ), .F0(\ram2e_ufm/N_350 ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ));
+  ram2e_ufm_SLICE_134 \ram2e_ufm/SLICE_134 ( .D1(\FS[3] ), .C1(\FS[6] ), 
+    .B1(\FS[1] ), .A1(\FS[2] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[9] ), 
+    .B0(\FS[3] ), .A0(\FS[6] ), .F0(\ram2e_ufm/N_679 ), 
+    .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ));
+  ram2e_ufm_SLICE_135 \ram2e_ufm/SLICE_135 ( .C1(\S[3] ), .A1(\S[2] ), 
+    .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[3] ), .B0(nEN80_c), .A0(\S[2] ), 
+    .F0(\ram2e_ufm/N_625 ), .F1(\ram2e_ufm/N_271 ));
+  ram2e_ufm_SLICE_136 \ram2e_ufm/SLICE_136 ( .C1(nWE_c), .B1(\S[3] ), 
+    .A1(nEN80_c), .D0(DOEEN), .B0(nWE_c), .A0(nEN80_c), .F0(nDOE_c), 
+    .F1(\ram2e_ufm/N_226 ));
+  ram2e_ufm_SLICE_137 \ram2e_ufm/SLICE_137 ( .C1(Ready), .B1(nWE_c), 
+    .A1(nEN80_c), .C0(Ready), .B0(\ram2e_ufm/LEDEN ), .A0(nEN80_c), .F0(LED_c), 
+    .F1(RDOE_i));
+  SLICE_138 SLICE_138( .D1(\S[1] ), .B1(\S[3] ), .A1(\S[0] ), .D0(\S[1] ), 
+    .B0(\S[0] ), .A0(\S[2] ), .F0(N_1080_0), .F1(N_1078_0));
+  SLICE_139 SLICE_139( .B1(PHI1_c), .A1(VOEEN), .C0(PHI1r), .B0(Ready), 
+    .A0(PHI1_c), .F0(S_1), .F1(nVOE_c));
+  ram2e_ufm_SLICE_140 \ram2e_ufm/SLICE_140 ( .B1(\RA[2] ), 
+    .A1(\ram2e_ufm/N_186 ), .C0(\RA[5] ), .A0(\ram2e_ufm/N_186 ), 
+    .F0(\ram2e_ufm/N_621 ), .F1(\ram2e_ufm/N_680 ));
+  ram2e_ufm_SLICE_141 \ram2e_ufm/SLICE_141 ( .D1(Ready), .B1(\Din_c[0] ), 
+    .D0(Ready), .A0(\Din_c[3] ), .F0(N_263_i), .F1(N_667));
+  ram2e_ufm_SLICE_142 \ram2e_ufm/SLICE_142 ( .D1(\Din_c[4] ), .C1(\Din_c[7] ), 
+    .A1(\Din_c[0] ), .D0(\Din_c[4] ), .C0(Ready), .F0(N_648), 
+    .F1(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ));
+  ram2e_ufm_SLICE_143 \ram2e_ufm/SLICE_143 ( .D1(Ready), .C1(\Din_c[1] ), 
+    .D0(Ready), .B0(\Din_c[7] ), .F0(N_662), .F1(N_666));
+  ram2e_ufm_SLICE_144 \ram2e_ufm/SLICE_144 ( .C1(\Din_c[2] ), .A1(Ready), 
+    .B0(\Din_c[6] ), .A0(Ready), .F0(N_663), .F1(N_665));
+  ram2e_ufm_SLICE_145 \ram2e_ufm/SLICE_145 ( .D1(\ram2e_ufm/N_783 ), 
+    .C1(\ram2e_ufm/N_873 ), .B1(\ram2e_ufm/wb_adr[4] ), .A1(\S[2] ), 
+    .D0(\FS[8] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_206 ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_0[4] ));
+  ram2e_ufm_SLICE_146 \ram2e_ufm/SLICE_146 ( .D1(\ram2e_ufm/N_845 ), 
+    .C1(\RWBank[2] ), .B1(\ram2e_ufm/N_784 ), .A1(\FS[4] ), .D0(\FS[7] ), 
+    .C0(\FS[0] ), .B0(\FS[6] ), .A0(\FS[5] ), .F0(\ram2e_ufm/Ready3_0_a3_3 ), 
+    .F1(\ram2e_ufm/RA_35_0_0_0[9] ));
+  ram2e_ufm_SLICE_147 \ram2e_ufm/SLICE_147 ( .D1(CmdSetRWBankFFLED), 
+    .C1(\ram2e_ufm/LEDEN ), .B1(CmdLEDGet), 
+    .A1(\ram2e_ufm/CmdSetRWBankFFChip ), .C0(Ready), .B0(\Din_c[5] ), 
+    .F0(N_664), .F1(\ram2e_ufm/N_188 ));
+  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(N_667), 
     .RD0(RD[0]));
   LED LED_I( .PADDO(LED_c), .LED(LED));
   C14M C14M_I( .PADDI(C14M_c), .C14M(C14M));
-  DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH));
-  DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_358_i), .CLK(C14M_c));
-  DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML));
-  DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_28_i), .CLK(C14M_c));
-  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(\Din_c[7] ), 
+  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(N_662), 
     .RD7(RD[7]));
-  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(\Din_c[6] ), 
+  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(N_663), 
     .RD6(RD[6]));
-  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(\Din_c[5] ), 
+  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(N_664), 
     .RD5(RD[5]));
-  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(\Din_c[4] ), 
+  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(N_648), 
     .RD4(RD[4]));
-  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(\Din_c[3] ), 
+  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(N_263_i), 
     .RD3(RD[3]));
-  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(\Din_c[2] ), 
+  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(N_665), 
     .RD2(RD[2]));
-  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(\Din_c[1] ), 
+  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(N_666), 
     .RD1(RD[1]));
-  RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11]));
-  RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(\RA_42[11] ), 
+  DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH));
+  DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_508), .CE(N_201_i), 
     .CLK(C14M_c));
-  RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10]));
-  RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(\RA_42[10] ), 
+  DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML));
+  DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_507_i), .CE(N_201_i), 
+    .CLK(C14M_c));
+  RAout_11_ \RAout[11]_I ( .IOLDO(\RAout_c[11] ), .RAout11(RAout[11]));
+  RAout_11__MGIOL \RAout[11]_MGIOL ( .IOLDO(\RAout_c[11] ), .OPOS(\RA[11] ), 
+    .CLK(C14M_c));
+  RAout_10_ \RAout[10]_I ( .IOLDO(\RAout_c[10] ), .RAout10(RAout[10]));
+  RAout_10__MGIOL \RAout[10]_MGIOL ( .IOLDO(\RAout_c[10] ), .OPOS(\RA[10] ), 
+    .CLK(C14M_c));
+  RAout_9_ \RAout[9]_I ( .IOLDO(\RAout_c[9] ), .RAout9(RAout[9]));
+  RAout_9__MGIOL \RAout[9]_MGIOL ( .IOLDO(\RAout_c[9] ), .OPOS(\RA[9] ), 
+    .CLK(C14M_c));
+  RAout_8_ \RAout[8]_I ( .IOLDO(\RAout_c[8] ), .RAout8(RAout[8]));
+  RAout_8__MGIOL \RAout[8]_MGIOL ( .IOLDO(\RAout_c[8] ), .OPOS(\RA[8] ), 
+    .CLK(C14M_c));
+  RAout_7_ \RAout[7]_I ( .IOLDO(\RAout_c[7] ), .RAout7(RAout[7]));
+  RAout_7__MGIOL \RAout[7]_MGIOL ( .IOLDO(\RAout_c[7] ), .OPOS(\RA[7] ), 
+    .CLK(C14M_c));
+  RAout_6_ \RAout[6]_I ( .IOLDO(\RAout_c[6] ), .RAout6(RAout[6]));
+  RAout_6__MGIOL \RAout[6]_MGIOL ( .IOLDO(\RAout_c[6] ), .OPOS(\RA[6] ), 
+    .CLK(C14M_c));
+  RAout_5_ \RAout[5]_I ( .IOLDO(\RAout_c[5] ), .RAout5(RAout[5]));
+  RAout_5__MGIOL \RAout[5]_MGIOL ( .IOLDO(\RAout_c[5] ), .OPOS(\RA[5] ), 
+    .CLK(C14M_c));
+  RAout_4_ \RAout[4]_I ( .IOLDO(\RAout_c[4] ), .RAout4(RAout[4]));
+  RAout_4__MGIOL \RAout[4]_MGIOL ( .IOLDO(\RAout_c[4] ), .OPOS(\RA[4] ), 
+    .CLK(C14M_c));
+  RAout_3_ \RAout[3]_I ( .IOLDO(\RAout_c[3] ), .RAout3(RAout[3]));
+  RAout_3__MGIOL \RAout[3]_MGIOL ( .IOLDO(\RAout_c[3] ), .OPOS(\RA[3] ), 
+    .CLK(C14M_c));
+  RAout_2_ \RAout[2]_I ( .IOLDO(\RAout_c[2] ), .RAout2(RAout[2]));
+  RAout_2__MGIOL \RAout[2]_MGIOL ( .IOLDO(\RAout_c[2] ), .OPOS(\RA[2] ), 
+    .CLK(C14M_c));
+  RAout_1_ \RAout[1]_I ( .IOLDO(\RAout_c[1] ), .RAout1(RAout[1]));
+  RAout_1__MGIOL \RAout[1]_MGIOL ( .IOLDO(\RAout_c[1] ), .OPOS(\RA[1] ), 
+    .CLK(C14M_c));
+  RAout_0_ \RAout[0]_I ( .IOLDO(\RAout_c[0] ), .RAout0(RAout[0]));
+  RAout_0__MGIOL \RAout[0]_MGIOL ( .IOLDO(\RAout_c[0] ), .OPOS(\RA[0] ), 
     .CLK(C14M_c));
-  RA_9_ \RA[9]_I ( .IOLDO(\RA_c[9] ), .RA9(RA[9]));
-  RA_9__MGIOL \RA[9]_MGIOL ( .IOLDO(\RA_c[9] ), .OPOS(N_59_i), .CLK(C14M_c));
-  RA_8_ \RA[8]_I ( .IOLDO(\RA_c[8] ), .RA8(RA[8]));
-  RA_8__MGIOL \RA[8]_MGIOL ( .IOLDO(\RA_c[8] ), .OPOS(N_49_i), .CLK(C14M_c));
-  RA_7_ \RA[7]_I ( .IOLDO(\RA_c[7] ), .RA7(RA[7]));
-  RA_7__MGIOL \RA[7]_MGIOL ( .IOLDO(\RA_c[7] ), .OPOS(N_549_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_6_ \RA[6]_I ( .IOLDO(\RA_c[6] ), .RA6(RA[6]));
-  RA_6__MGIOL \RA[6]_MGIOL ( .IOLDO(\RA_c[6] ), .OPOS(N_550_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_5_ \RA[5]_I ( .IOLDO(\RA_c[5] ), .RA5(RA[5]));
-  RA_5__MGIOL \RA[5]_MGIOL ( .IOLDO(\RA_c[5] ), .OPOS(\RA_42_3_0[5] ), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_4_ \RA[4]_I ( .IOLDO(\RA_c[4] ), .RA4(RA[4]));
-  RA_4__MGIOL \RA[4]_MGIOL ( .IOLDO(\RA_c[4] ), .OPOS(N_551_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
-  RA_2_ \RA[2]_I ( .IOLDO(\RA_c[2] ), .RA2(RA[2]));
-  RA_2__MGIOL \RA[2]_MGIOL ( .IOLDO(\RA_c[2] ), .OPOS(N_553_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_1_ \RA[1]_I ( .IOLDO(\RA_c[1] ), .RA1(RA[1]));
-  RA_1__MGIOL \RA[1]_MGIOL ( .IOLDO(\RA_c[1] ), .OPOS(N_558_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
   BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1]));
-  BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), 
-    .LSR(N_566_i), .CLK(C14M_c));
+  BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), .CE(N_225_i), 
+    .LSR(BA_0_sqmuxa), .CLK(C14M_c));
   BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0]));
-  BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), 
-    .LSR(N_566_i), .CLK(C14M_c));
-  nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE));
-  nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(nRWE_r_0), .CLK(C14M_c));
-  nCAS nCAS_I( .IOLDO(nCAS_c), .nCAS(nCAS));
-  nCAS_MGIOL nCAS_MGIOL( .IOLDO(nCAS_c), .OPOS(N_561_i), .CLK(C14M_c));
-  nRAS nRAS_I( .IOLDO(nRAS_c), .nRAS(nRAS));
-  nRAS_MGIOL nRAS_MGIOL( .IOLDO(nRAS_c), .OPOS(nRAS_2_iv_i), .CLK(C14M_c));
-  nCS nCS_I( .IOLDO(nCS_c), .nCS(nCS));
-  nCS_MGIOL nCS_MGIOL( .IOLDO(nCS_c), .OPOS(N_559_i), .CLK(C14M_c));
-  CKE CKE_I( .IOLDO(CKE_c), .CKE(CKE));
-  CKE_MGIOL CKE_MGIOL( .IOLDO(CKE_c), .OPOS(CKE_6_iv_i_0), .CLK(C14M_c));
-  nVOE nVOE_I( .PADDO(PHI1_c), .nVOE(nVOE));
+  BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), .CE(N_225_i), 
+    .LSR(BA_0_sqmuxa), .CLK(C14M_c));
+  nRWEout nRWEout_I( .IOLDO(nRWEout_c), .nRWEout(nRWEout));
+  nRWEout_MGIOL nRWEout_MGIOL( .IOLDO(nRWEout_c), .OPOS(nRWE), .CLK(C14M_c));
+  nCASout nCASout_I( .IOLDO(nCASout_c), .nCASout(nCASout));
+  nCASout_MGIOL nCASout_MGIOL( .IOLDO(nCASout_c), .OPOS(nCAS), .CLK(C14M_c));
+  nRASout nRASout_I( .IOLDO(nRASout_c), .nRASout(nRASout));
+  nRASout_MGIOL nRASout_MGIOL( .IOLDO(nRASout_c), .OPOS(nRAS), .CLK(C14M_c));
+  nCSout nCSout_I( .PADDO(GND), .nCSout(nCSout));
+  CKEout CKEout_I( .IOLDO(CKEout_c), .CKEout(CKEout));
+  CKEout_MGIOL CKEout_MGIOL( .IOLDO(CKEout_c), .OPOS(CKE), .CLK(C14M_c));
+  nVOE nVOE_I( .PADDO(nVOE_c), .nVOE(nVOE));
   Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7]));
   Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), 
     .CE(Vout3), .CLK(C14M_c));
@@ -574,30 +889,14 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), 
     .CE(Vout3), .CLK(C14M_c));
   nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE));
-  Dout_7_ \Dout[7]_I ( .IOLDO(\Dout_c[7] ), .Dout7(Dout[7]));
-  Dout_7__MGIOL \Dout[7]_MGIOL ( .IOLDO(\Dout_c[7] ), .OPOS(\RD_in[7] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_6_ \Dout[6]_I ( .IOLDO(\Dout_c[6] ), .Dout6(Dout[6]));
-  Dout_6__MGIOL \Dout[6]_MGIOL ( .IOLDO(\Dout_c[6] ), .OPOS(\RD_in[6] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_5_ \Dout[5]_I ( .IOLDO(\Dout_c[5] ), .Dout5(Dout[5]));
-  Dout_5__MGIOL \Dout[5]_MGIOL ( .IOLDO(\Dout_c[5] ), .OPOS(\RD_in[5] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_4_ \Dout[4]_I ( .IOLDO(\Dout_c[4] ), .Dout4(Dout[4]));
-  Dout_4__MGIOL \Dout[4]_MGIOL ( .IOLDO(\Dout_c[4] ), .OPOS(\RD_in[4] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_3_ \Dout[3]_I ( .IOLDO(\Dout_c[3] ), .Dout3(Dout[3]));
-  Dout_3__MGIOL \Dout[3]_MGIOL ( .IOLDO(\Dout_c[3] ), .OPOS(\RD_in[3] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_2_ \Dout[2]_I ( .IOLDO(\Dout_c[2] ), .Dout2(Dout[2]));
-  Dout_2__MGIOL \Dout[2]_MGIOL ( .IOLDO(\Dout_c[2] ), .OPOS(\RD_in[2] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_1_ \Dout[1]_I ( .IOLDO(\Dout_c[1] ), .Dout1(Dout[1]));
-  Dout_1__MGIOL \Dout[1]_MGIOL ( .IOLDO(\Dout_c[1] ), .OPOS(\RD_in[1] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_0_ \Dout[0]_I ( .IOLDO(\Dout_c[0] ), .Dout0(Dout[0]));
-  Dout_0__MGIOL \Dout[0]_MGIOL ( .IOLDO(\Dout_c[0] ), .OPOS(\RD_in[0] ), 
-    .CE(N_576_i), .CLK(C14M_c));
+  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
+  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
+  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
+  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
+  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
+  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
+  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
+  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
   Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
   Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
   Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
@@ -616,21 +915,25 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0]));
   nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X));
   nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80));
-  nWE80 nWE80_I( .PADDI(nWE80_c), .nWE80(nWE80));
   nWE nWE_I( .PADDI(nWE_c), .nWE(nWE));
   PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1));
-  PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1reg));
-  ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), .WBRSTI(wb_rst), 
-    .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), 
-    .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), 
-    .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), 
-    .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), 
-    .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), 
-    .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), 
-    .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), 
-    .WBDATO2(\wb_dato[2] ), .WBDATO3(\wb_dato[3] ), .WBDATO4(\wb_dato[4] ), 
-    .WBDATO5(\wb_dato[5] ), .WBDATO6(\wb_dato[6] ), .WBDATO7(\wb_dato[7] ), 
-    .WBACKO(wb_ack));
+  PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1r));
+  ram2e_ufm_ufmefb_EFBInst_0 \ram2e_ufm/ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), 
+    .WBRSTI(\ram2e_ufm/wb_rst ), .WBCYCI(\ram2e_ufm/wb_cyc_stb ), 
+    .WBSTBI(\ram2e_ufm/wb_cyc_stb ), .WBWEI(\ram2e_ufm/wb_we ), 
+    .WBADRI0(\ram2e_ufm/wb_adr[0] ), .WBADRI1(\ram2e_ufm/wb_adr[1] ), 
+    .WBADRI2(\ram2e_ufm/wb_adr[2] ), .WBADRI3(\ram2e_ufm/wb_adr[3] ), 
+    .WBADRI4(\ram2e_ufm/wb_adr[4] ), .WBADRI5(\ram2e_ufm/wb_adr[5] ), 
+    .WBADRI6(\ram2e_ufm/wb_adr[6] ), .WBADRI7(\ram2e_ufm/wb_adr[7] ), 
+    .WBDATI0(\ram2e_ufm/wb_dati[0] ), .WBDATI1(\ram2e_ufm/wb_dati[1] ), 
+    .WBDATI2(\ram2e_ufm/wb_dati[2] ), .WBDATI3(\ram2e_ufm/wb_dati[3] ), 
+    .WBDATI4(\ram2e_ufm/wb_dati[4] ), .WBDATI5(\ram2e_ufm/wb_dati[5] ), 
+    .WBDATI6(\ram2e_ufm/wb_dati[6] ), .WBDATI7(\ram2e_ufm/wb_dati[7] ), 
+    .WBDATO0(\ram2e_ufm/wb_dato[0] ), .WBDATO1(\ram2e_ufm/wb_dato[1] ), 
+    .WBDATO2(\ram2e_ufm/wb_dato[2] ), .WBDATO3(\ram2e_ufm/wb_dato[3] ), 
+    .WBDATO4(\ram2e_ufm/wb_dato[4] ), .WBDATO5(\ram2e_ufm/wb_dato[5] ), 
+    .WBDATO6(\ram2e_ufm/wb_dato[6] ), .WBDATO7(\ram2e_ufm/wb_dato[7] ), 
+    .WBACKO(\ram2e_ufm/wb_ack ));
   VHI VHI_INST( .Z(VCCI));
   PUR PUR_INST( .PUR(VCCI));
   GSR GSR_INST( .GSR(VCCI));
@@ -941,21 +1244,63 @@ module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
 
 endmodule
 
-module SLICE_9 ( input D1, C1, B1, C0, A0, DI0, CE, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
 
-  lut4 S_1( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40003 \CmdTout_3_0_a2[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  lut4 \ram2e_ufm/wb_req_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40003 \ram2e_ufm/CKE_7_RNIS77M1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0004 CKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut4 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40003 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hCCCD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_10 ( input B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40005 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40006 \ram2e_ufm/CmdTout_3_0_a3_0_a3[0] ( .A(A0), .B(B0), .C(GNDI), 
+    .D(GNDI), .Z(F0));
+  vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
@@ -966,27 +1311,64 @@ module SLICE_9 ( input D1, C1, B1, C0, A0, DI0, CE, CLK, output F0, Q0, F1 );
 
 endmodule
 
-module lut4 ( input A, B, C, D, output Z );
+module lut40005 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40003 ( input A, B, C, D, output Z );
+module lut40006 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly;
+module SLICE_11 ( input D1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40004 \CS_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40005 \CS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40007 \ram2e_ufm/RC_3_0_0_a3_1[1] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre0006 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
+  lut40008 \ram2e_ufm/N_360_i ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre \RC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40007 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40008 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_12 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly;
+
+  lut40009 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNI6S1P8 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40010 \ram2e_ufm/S_r_i_0_o2_RNIVM0LF[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0011 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre0006 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+  vmuxregsre0011 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
 
   specify
@@ -994,6 +1376,7 @@ module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK,
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1010,30 +1393,31 @@ module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK,
 
 endmodule
 
-module lut40004 ( input A, B, C, D, output Z );
+module lut40009 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAA9A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40005 ( input A, B, C, D, output Z );
+module lut40010 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0D0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q );
+module vmuxregsre0011 ( input D0, D1, SD, SP, CK, LSR, output Q );
 
   FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module SLICE_11 ( input D1, C1, B1, D0, C0, A0, DI0, LSR, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
+module SLICE_13 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
 
-  lut40007 \CS_RNO_0[2] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40008 \CS_RNO[2] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0006 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+  lut40012 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 ( .A(A1), 
+    .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40013 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0011 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
@@ -1041,8 +1425,10 @@ module SLICE_11 ( input D1, C1, B1, D0, C0, A0, DI0, LSR, CLK, output F0, Q0,
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
@@ -1055,108 +1441,32 @@ module SLICE_11 ( input D1, C1, B1, D0, C0, A0, DI0, LSR, CLK, output F0, Q0,
 
 endmodule
 
-module lut40007 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40008 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_12 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40009 CmdBitbangMXO2_4_u_0_0_a2_0_1( .A(GNDI), .B(B1), .C(C1), .D(D1), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40010 CmdBitbangMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdBitbangMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40009 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40010 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_13 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40011 un1_CS_0_sqmuxa_0_0_a2_7( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40012 CmdExecMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdExecMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40011 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
 module lut40012 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+module lut40013 ( input A, B, C, D, output Z );
 
-  lut40013 CmdLEDGet_4_u_0_0_a2_0_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40014 CmdLEDGet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'hAA1A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_14 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
+    Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40014 \ram2e_ufm/CmdLEDGet_3_0_a3_0 ( .A(A1), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40015 \ram2e_ufm/CmdLEDGet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
   vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
@@ -1171,66 +1481,29 @@ module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
 
 endmodule
 
-module lut40013 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
 module lut40014 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_15 ( input D1, C1, B1, A1, D0, B0, A0, DI0, CE, CLK, output F0, 
+module lut40015 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_15 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
     Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40015 CmdLEDSet_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40016 CmdLEDSet_4_u_0_0_0( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ( .A(A1), .B(B1), .C(GNDI), 
+    .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
+  lut40017 \ram2e_ufm/CmdLEDSet_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
   vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40015 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40016 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hCCEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_16 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40017 CmdBitbangMXO2_4_u_0_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(D1), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40018 CmdRWMaskSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
@@ -1248,69 +1521,70 @@ module SLICE_16 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
+module lut40016 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h2200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
 module lut40017 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_16 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40018 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40019 \ram2e_ufm/CmdRWMaskSet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40018 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_17 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
+module lut40019 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_17 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
     Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40019 CmdSetRWBankFFLED_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), 
+  lut40020 \ram2e_ufm/CmdRWMaskSet_3_0_a3_0 ( .A(GNDI), .B(B1), .C(C1), .D(D1), 
     .Z(F1));
-  lut40020 CmdSetRWBankFFLED_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), 
-    .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
+  lut40021 \ram2e_ufm/CmdSetRWBankFFLED_4_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
   vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
     .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40019 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40020 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hF2F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_18 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40021 CmdSetRWBankFFLED_4_u_0_0_a2_1( .A(GNDI), .B(B1), .C(C1), .D(D1), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40014 CmdSetRWBankFFMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
-  vmuxregsre CmdSetRWBankFFMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
-    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
@@ -1328,17 +1602,22 @@ module SLICE_18 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40021 ( input A, B, C, D, output Z );
+module lut40020 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h000C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_19 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output 
+module lut40021 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_18 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output 
     F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40022 \CmdTout_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40023 \CmdTout_RNO[1] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  lut40022 \ram2e_ufm/N_369_i ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40023 \ram2e_ufm/N_368_i ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
   vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
@@ -1352,7 +1631,7 @@ module SLICE_19 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     (CLK => Q1) = (0:0:0,0:0:0);
@@ -1367,24 +1646,63 @@ endmodule
 
 module lut40022 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h060C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h006A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40023 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h050A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0066) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+module SLICE_19 ( input C1, B1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, M0_dly, CLK_dly, LSR_dly;
 
-  lut40024 \S_RNII9DO1_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40025 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre DOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  lut40024 \ram2e_ufm/SUM0_i_o2 ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40025 \ram2e_ufm/RA_35_i_i_0_a3_0[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre0011 DOEEN( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40024 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40025 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40026 \ram2e_ufm/RA_35_i_i_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40027 \ram2e_ufm/RA_35_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \RA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -1396,42 +1714,8 @@ module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40024 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40025 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hAA80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_21 ( input D1, C1, A1, D0, C0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40026 \RA_0io_RNO[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40027 LEDEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
     $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
@@ -1442,31 +1726,32 @@ endmodule
 
 module lut40026 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40027 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_22 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
+module SLICE_21 ( input D1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40028 \RA_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40028 \ram2e_ufm/RA_35_0_0[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40028 \RA_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40029 \ram2e_ufm/RA_35_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
   vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
-    (C1 => F1) = (0:0:0,0:0:0);
+    (D1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1483,28 +1768,34 @@ endmodule
 
 module lut40028 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hC8C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_23 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
+module lut40029 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_22 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40029 \RWBank_5_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40026 \ram2e_ufm/RA_35_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40030 \ram2e_ufm/RA_35_0_0[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40030 \RWBank_5_0[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     (CLK => Q1) = (0:0:0,0:0:0);
@@ -1517,32 +1808,29 @@ module SLICE_23 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40029 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
 module lut40030 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAAEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_24 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40031 \RWBank_5_0[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40031 \ram2e_ufm/RA_35_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40032 \RWBank_5_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40031 \ram2e_ufm/RA_35_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre \RA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -1560,32 +1848,29 @@ endmodule
 
 module lut40031 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40032 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hDCDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_25 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
+module SLICE_24 ( input D1, C1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40032 \RWBank_5_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40032 \ram2e_ufm/RA_35_0_0[9] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40033 \RWBank_5_0[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40033 \ram2e_ufm/un2_S_2_i_0_0_o3_RNIHFHN3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre \RA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
@@ -1599,31 +1884,38 @@ module SLICE_25 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40033 ( input A, B, C, D, output Z );
+module lut40032 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hDDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_26 ( input D1, C1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module lut40033 ( input A, B, C, D, output Z );
 
-  lut40034 \RWBank_5_0_0[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40035 \RWBank_5_0[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_25 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40034 \ram2e_ufm/RA_35_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40035 \ram2e_ufm/RA_35_2_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \RA[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \RA[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     (CLK => Q1) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
@@ -1637,32 +1929,32 @@ endmodule
 
 module lut40034 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40035 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFF30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_27 ( input D1, C1, B1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+module SLICE_26 ( input D1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40036 \RWMask_RNO[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40036 \ram2e_ufm/RC_3_0_0[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40037 \RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40037 \ram2e_ufm/RC_3_0_0[1] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre \RC[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RC[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
@@ -1678,31 +1970,32 @@ endmodule
 
 module lut40036 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h30FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h6622) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40037 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h7474) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h2266) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_28 ( input D1, B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, 
+module SLICE_27 ( input D1, C1, B1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40038 \RWMask_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  lut40038 \ram2e_ufm/RWBank_3_0[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40039 \RWMask_RNO[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40038 \ram2e_ufm/RWBank_3_0_0[0] ( .A(GNDI), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -1719,75 +2012,71 @@ endmodule
 
 module lut40038 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h55CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_28 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40039 \ram2e_ufm/RWBank_3_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40040 \ram2e_ufm/RWBank_3_0[2] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40039 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0FCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_29 ( input D1, C1, B1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40040 \RWMask_RNO[5] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40041 \RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40040 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3F0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hAAEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40041 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2E2E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_30 ( input D1, C1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, 
+module SLICE_29 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40042 \RWMask_RNO[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40041 \ram2e_ufm/RWBank_3_0[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40039 \RWMask_RNO[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40042 \ram2e_ufm/RWBank_3_0_0[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     (CLK => Q1) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
@@ -1799,31 +2088,39 @@ module SLICE_30 ( input D1, C1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40042 ( input A, B, C, D, output Z );
+module lut40041 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+module lut40042 ( input A, B, C, D, output Z );
 
-  lut40043 nDOE_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  ROM16X1A #(16'hFF50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_30 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40043 \ram2e_ufm/RWBank_3_0[7] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40044 RWSel_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  lut40044 \ram2e_ufm/RWBank_3_0[6] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
-    (C1 => F1) = (0:0:0,0:0:0);
+    (D1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
     $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
@@ -1834,19 +2131,59 @@ endmodule
 
 module lut40043 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40044 ( input A, B, C, D, output Z );
 
+  ROM16X1A #(16'hFF0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40045 \ram2e_ufm/RA_35_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40046 \ram2e_ufm/RWSel_2_0_a3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40045 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40046 ( input A, B, C, D, output Z );
+
   ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module SLICE_32 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly;
 
-  lut40045 Ready_0_sqmuxa_0_a2_6_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40046 Ready_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  lut40047 \ram2e_ufm/Ready3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40048 Ready_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
   vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
@@ -1867,12 +2204,12 @@ module SLICE_32 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
 
 endmodule
 
-module lut40045 ( input A, B, C, D, output Z );
+module lut40047 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40046 ( input A, B, C, D, output Z );
+module lut40048 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
@@ -1881,8 +2218,9 @@ module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
     F0, Q0, F1, Q1 );
   wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
 
-  lut40047 \S_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40048 \S_s_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40049 \ram2e_ufm/S_r_i_0_o2_0_RNI36E21[1] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40050 \ram2e_ufm/S_s_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
   vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1909,22 +2247,24 @@ module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
 
 endmodule
 
-module lut40047 ( input A, B, C, D, output Z );
+module lut40049 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h008C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h00A2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40048 ( input A, B, C, D, output Z );
+module lut40050 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output 
     F0, Q0, F1, Q1 );
   wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
 
-  lut40049 \S_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40050 \S_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40051 \ram2e_ufm/S_r_i_0_o2_RNIFNP81_0[2] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40052 \ram2e_ufm/S_r_i_0_o2_RNIFNP81[2] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
   vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1951,82 +2291,41 @@ module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
 
 endmodule
 
-module lut40049 ( input A, B, C, D, output Z );
+module lut40051 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0C0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h00AE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40050 ( input A, B, C, D, output Z );
+module lut40052 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0A0D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h2321) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module SLICE_35 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
 
-  lut40051 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40052 \wb_adr_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
+  lut40053 \ram2e_ufm/CKE_7_m1_0_0_o2_RNICM8E1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40054 \ram2e_ufm/CKE_7_m1_0_0_o2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vmuxregsre0011 VOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40051 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40052 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_36 ( input D1, C1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40053 \wb_adr_RNO[3] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40054 \wb_adr_RNO[2] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
-  vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
@@ -2035,39 +2334,38 @@ endmodule
 
 module lut40053 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40054 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_37 ( input D1, B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
 
-  lut40055 \wb_adr_RNO[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40056 \wb_adr_RNO[4] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40055 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40056 \ram2e_ufm/nCAS_s_i_0_a3_RNIO1UQ3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0004 nCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
@@ -2076,38 +2374,38 @@ endmodule
 
 module lut40055 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAA33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40056 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_38 ( input D1, B1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
 
-  lut40057 \wb_adr_RNO[7] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40058 \wb_adr_RNO[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40057 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40058 \ram2e_ufm/nRAS_s_i_0_0_RNI0PC64 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0004 nRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
@@ -2116,64 +2414,25 @@ endmodule
 
 module lut40057 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40058 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCC0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_39 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
+module SLICE_38 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
     Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
 
-  lut40059 wb_cyc_stb_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40060 wb_cyc_stb_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40059 \ram2e_ufm/nRAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40060 \ram2e_ufm/nRAS_s_i_0_a3_0_RNIIR094 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre0004 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40059 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40060 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40061 \wb_dati_7_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40062 \wb_dati_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2185,8 +2444,46 @@ module SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40059 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40060 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0103) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_39 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40061 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40062 \ram2e_ufm/CmdBitbangMXO2_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/CmdBitbangMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
     $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
@@ -2197,38 +2494,35 @@ endmodule
 
 module lut40061 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40062 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_41 ( input D1, C1, B1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module ram2e_ufm_SLICE_40 ( input D1, C1, B1, A1, C0, B0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40063 \wb_dati_7_0[3] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40063 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40064 \ram2e_ufm/CmdExecMXO2_3_0_a3 ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40064 \wb_dati_7_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vmuxregsre \ram2e_ufm/CmdExecMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
     $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
@@ -2239,26 +2533,26 @@ endmodule
 
 module lut40063 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40064 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module ram2e_ufm_SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40065 \wb_dati_7_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40066 \wb_dati_7_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  lut40065 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0_0 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40066 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/CmdSetRWBankFFChip ( .D0(VCCI), .D1(DI0_dly), 
+    .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2270,8 +2564,6 @@ module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
     $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
@@ -2282,32 +2574,68 @@ endmodule
 
 module lut40065 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40066 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_43 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output 
-    F0, Q0, F1, Q1 );
+module ram2e_ufm_SLICE_42 ( input D1, C1, A1, D0, C0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40067 \ram2e_ufm/SUM1_0_o3_0 ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40068 \ram2e_ufm/LEDEN_RNO ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/LEDEN ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40067 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40068 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_43 ( input D1, C1, B1, D0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40067 \wb_dati_7_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40068 \wb_dati_7_0[6] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  lut40069 \ram2e_ufm/RWMask_RNO[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  lut40070 \ram2e_ufm/RWMask_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vmuxregsre \ram2e_ufm/RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -2322,26 +2650,28 @@ module SLICE_43 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output
 
 endmodule
 
-module lut40067 ( input A, B, C, D, output Z );
+module lut40069 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0FCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40068 ( input A, B, C, D, output Z );
+module lut40070 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hEECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h55CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_44 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output 
-    F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
+module ram2e_ufm_SLICE_44 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40069 wb_req_RNO_1( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  lut40070 \ram2e_ufm/RWMask_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40070 wb_req_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0006 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  lut40071 \ram2e_ufm/RWMask_RNO[2] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2349,50 +2679,12 @@ module SLICE_44 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
     $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge LSR, 0:0:0);
-    $width (negedge LSR, 0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40069 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h8800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40070 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_45 ( input B1, A1, D0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40071 \un1_LEDEN13_2_i_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40072 wb_rst8_0_a2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
-  vmuxregsre0006 wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge LSR, 0:0:0);
-    $width (negedge LSR, 0:0:0);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
@@ -2401,24 +2693,88 @@ endmodule
 
 module lut40071 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h55F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_45 ( input D1, C1, B1, D0, C0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40072 \ram2e_ufm/RWMask_RNO[5] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40071 \ram2e_ufm/RWMask_RNO[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40072 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h33F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+module ram2e_ufm_SLICE_46 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40073 wb_we_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40074 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  lut40068 \ram2e_ufm/RWMask_RNO[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40071 \ram2e_ufm/RWMask_RNO[6] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40073 \ram2e_ufm/wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40074 \ram2e_ufm/wb_adr_7_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2430,6 +2786,8 @@ module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
     $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
@@ -2440,74 +2798,139 @@ endmodule
 
 module lut40073 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h70F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40074 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_48 ( input D1, B1, D0, A0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40075 DQMH_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40076 \S_RNII9DO1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40075 \ram2e_ufm/wb_adr_RNO[3] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40076 \ram2e_ufm/wb_adr_RNO[2] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40075 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40076 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_49 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40077 Vout3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40078 nCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40077 \ram2e_ufm/wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40077 \ram2e_ufm/wb_adr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40077 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8D8D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_50 ( input B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40025 \ram2e_ufm/wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40078 \ram2e_ufm/wb_adr_RNO[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40078 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hC0F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_51 ( input D1, C1, B1, A1, D0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40079 un1_CS_0_sqmuxa_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40080 un1_CS_0_sqmuxa_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40079 \ram2e_ufm/wb_cyc_stb_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40080 \ram2e_ufm/wb_cyc_stb_RNO ( .A(A0), .B(B0), .C(GNDI), .D(D0), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_cyc_stb ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2515,27 +2938,41 @@ module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40079 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h000E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40080 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40081 \wb_dati_7_0_a2_0_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40082 \wb_dati_7_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40081 \ram2e_ufm/wb_dati_7_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40082 \ram2e_ufm/wb_dati_7_0_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2546,24 +2983,41 @@ module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40081 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00B0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40082 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40083 CKE_6_iv_i_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40084 CKE_6_iv_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40083 \ram2e_ufm/wb_dati_7_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40084 \ram2e_ufm/wb_dati_7_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2574,24 +3028,41 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40083 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h30EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40084 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40085 \un1_LEDEN13_2_i_a2_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40086 \un1_LEDEN13_2_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40085 \ram2e_ufm/wb_dati_7_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40035 \ram2e_ufm/wb_dati_7_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2602,25 +3073,36 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40085 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40086 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40087 \un1_wb_adr_0_sqmuxa_2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+  lut40035 \ram2e_ufm/wb_dati_7_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), 
     .Z(F1));
-  lut40088 wb_we_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40086 \ram2e_ufm/wb_dati_7_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2631,52 +3113,113 @@ module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40086 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, 
+    CLK, output F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
+
+  lut40087 \ram2e_ufm/wb_reqc_1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40088 \ram2e_ufm/wb_req_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0011 \ram2e_ufm/wb_req ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40087 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3FDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40088 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_57 ( input D1, C1, B1, A1, C0, A0, DI0, LSR, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
 
-  lut40089 un1_CS_0_sqmuxa_0_0_a2_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40090 un1_CS_0_sqmuxa_0_0_o2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40089 \ram2e_ufm/Ready3_0_a3_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40090 \ram2e_ufm/wb_rst8_0_a3_0_a3 ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre0011 \ram2e_ufm/wb_rst ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40089 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40090 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40091 nCS_6_u_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40092 un1_nCS61_1_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40091 \ram2e_ufm/wb_we_RNO_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40092 \ram2e_ufm/wb_we_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_we ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2687,108 +3230,159 @@ module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40091 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hEEEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40092 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_56 ( input D1, C1, A1, D0, C0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SUM0_i_m3_0_SLICE_59 ( input D1, C1, B1, D0, C0, B0, M0, 
+    output OFX0 );
+  wire   GNDI, 
+         \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 , 
+         \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ;
 
-  lut40093 \wb_dati_7_0_a2_5[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40093 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1 ( .A(GNDI), .B(B1), .C(C1), 
+    .D(D1), 
+    .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40094 \wb_dati_7_0_a2_6[1] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  lut40094 \ram2e_ufm/SUM0_i_m3_0/GATE ( .A(GNDI), .B(B0), .C(C0), .D(D0), 
+    .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ));
+  selmux2 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K0K1MUX ( 
+    .D0(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ), 
+    .D1(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ), 
+    .SD(M0), .Z(OFX0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40093 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF3FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40094 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module selmux2 ( input D0, D1, SD, output Z );
 
-  lut40095 \un1_LEDEN13_2_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40096 \S_RNII9DO1_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
+endmodule
+
+module ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 ( input D1, C1, B1, A1, C0, B0, 
+    A0, M0, output OFX0 );
+  wire   
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 
+         , GNDI, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 
+         ;
+
+  lut40095 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), 
+    .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 )
+    );
+  lut40096 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE ( .A(A0), .B(B0), .C(C0), 
+    .D(GNDI), 
+    .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 )
+    );
+  gnd DRIVEGND( .PWR0(GNDI));
+  selmux2 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K0K1MUX ( 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 )
+    , 
+    .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 )
+    , .SD(M0), .Z(OFX0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40095 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h2F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40096 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFDFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_CKE_7_SLICE_61 ( input D1, C1, A1, D0, B0, A0, M0, output 
+    OFX0 );
+  wire   GNDI, \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 , 
+         \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ;
 
-  lut40097 \wb_dati_7_0_2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40098 \wb_dati_7_0_2_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40097 \ram2e_ufm/CKE_7/SLICE_61_K1 ( .A(A1), .B(GNDI), .C(C1), .D(D1), 
+    .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40098 \ram2e_ufm/CKE_7/GATE ( .A(A0), .B(B0), .C(GNDI), .D(D0), 
+    .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ));
+  selmux2 \ram2e_ufm/CKE_7/SLICE_61_K0K1MUX ( 
+    .D0(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ), 
+    .D1(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ), .SD(M0), 
+    .Z(OFX0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40097 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40098 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h2200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40099 DQML_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40100 DQML_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40099 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIAJ811 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40100 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIPG3P2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2805,26 +3399,28 @@ endmodule
 
 module lut40099 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0FBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40100 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF0F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_60 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40101 \wb_adr_RNO_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40102 \wb_adr_RNO_3[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40101 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40102 \ram2e_ufm/S_r_i_0_o2_RNI3VQTC[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -2834,25 +3430,27 @@ endmodule
 
 module lut40101 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h20A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF0F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40102 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_61 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_64 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40103 \wb_dati_7_0_a2_2_0[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40103 \ram2e_ufm/wb_adr_7_i_i_a3_6[0] ( .A(A1), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40104 \FS_RNIOD6E_1[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40104 \ram2e_ufm/wb_adr_7_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -2863,20 +3461,20 @@ endmodule
 
 module lut40103 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40104 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40105 \wb_adr_RNO_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40106 \wb_adr_RNO_2[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40105 \ram2e_ufm/SUM0_i_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40106 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2886,32 +3484,35 @@ module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40105 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40106 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hC03F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF1F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40107 \un1_LEDEN13_2_i_o2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40108 \FS_RNI9FGA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40107 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40108 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -2921,24 +3522,23 @@ endmodule
 
 module lut40107 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40108 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hDDDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_67 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40109 \FS_RNI6JJA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40109 \ram2e_ufm/nRAS_s_i_0_m3 ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40110 \un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
+  lut40110 \ram2e_ufm/nRAS_s_i_0_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
-    (C1 => F1) = (0:0:0,0:0:0);
+    (D1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -2951,23 +3551,25 @@ endmodule
 
 module lut40109 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hDD11) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40110 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFDE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_65 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40111 \wb_dati_7_0_a2_0_0[6] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40112 \wb_dati_7_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40111 \ram2e_ufm/wb_adr_7_i_i_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40112 \ram2e_ufm/wb_adr_7_i_i_3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -2980,23 +3582,25 @@ endmodule
 
 module lut40111 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40112 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0819) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_66 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40003 \FS_RNIJ9MH[14] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40113 wb_we_RNO_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40113 \ram2e_ufm/nCAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40114 \ram2e_ufm/wb_rst16_i_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
@@ -3008,184 +3612,236 @@ endmodule
 
 module lut40113 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_67 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40114 wb_reqc_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40115 wb_reqc_1_RNIRU4M1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40114 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_70 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40115 \ram2e_ufm/wb_dati_7_0_0_a3_12[7] ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40116 \ram2e_ufm/wb_dati_7_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40115 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40116 \wb_dati_7_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40117 \FS_RNIOD6E_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40116 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hB000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_71 ( input C1, B1, A1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40117 \ram2e_ufm/RA_35_0_0_a3_4[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40118 \ram2e_ufm/nRAS_s_i_0_a3_4 ( .A(A0), .B(B0), .C(GNDI), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40117 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40118 \RA_42_0[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40119 \RA_42_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40118 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFF2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_72 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40119 \ram2e_ufm/BA_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40120 \ram2e_ufm/un1_RC12_i_0_o3 ( .A(A0), .B(B0), .C(GNDI), .D(D0), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40119 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0208) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40120 \wb_dati_7_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40121 \FS_RNIOD6E[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hC0C4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40120 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0E00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40121 \ram2e_ufm/wb_dati_7_0_0_o3_0[2] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40122 \ram2e_ufm/wb_dati_7_0_0_a3_3[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40121 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h7800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40122 nRWE_r_0_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40123 \S_RNII9DO1_3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40122 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40123 \ram2e_ufm/RA_35_2_0_0[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40124 \ram2e_ufm/RA_35_2_0_a3_5[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40123 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40124 Ready_0_sqmuxa_0_a2_6_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40125 \FS_RNI5OOF1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40124 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_75 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40125 \ram2e_ufm/wb_dati_7_0_0_a3_15[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40126 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0] ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40125 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40126 ( input A, B, C, D, output Z );
 
-  lut40126 \wb_adr_7_0_a2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40127 \FS_RNIK5632[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_76 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40127 \ram2e_ufm/wb_dati_7_0_0_a3_13[7] ( .A(GNDI), .B(GNDI), .C(C1), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40128 \ram2e_ufm/wb_dati_7_0_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40127 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40128 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40129 \ram2e_ufm/SUM2_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40130 \ram2e_ufm/N_314_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -3197,80 +3853,28 @@ module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40126 ( input A, B, C, D, output Z );
+module lut40129 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00C4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40127 ( input A, B, C, D, output Z );
+module lut40130 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_74 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_78 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40128 \wb_dati_7_0_a2_5[4] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  lut40131 \ram2e_ufm/S_r_i_0_o2[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40129 \wb_dati_7_0_a2_5_RNIC22J[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40132 \ram2e_ufm/S_r_i_0_o2_RNIP4KI1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40128 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40129 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_75 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40079 nCS_6_u_i_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40130 nCS_6_u_i_a2_4_RNI3A062( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40130 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40071 nCS_6_u_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40131 nCS_6_u_i_a2_4_RNICJKD2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -3281,75 +3885,61 @@ endmodule
 
 module lut40131 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_77 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40132 un1_CS_0_sqmuxa_0_0_a2_10( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40133 un1_CS_0_sqmuxa_0_0_2_RNIQS7F( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hFFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40132 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40133 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_79 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'h0015) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_78 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40114 nCAS_s_i_o2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40134 nCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40134 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFF13) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_79 ( input D1, C1, B1, A1, C0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40135 nCS_6_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40003 nCS_0io_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40133 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40134 \ram2e_ufm/S_r_i_0_o2_RNIOGTF1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40133 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8F88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40134 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40135 \ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40136 \ram2e_ufm/CmdBitbangMXO2_RNINSM62 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
@@ -3357,41 +3947,21 @@ endmodule
 
 module lut40135 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h001A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_80 ( input D1, C1, B1, D0, C0, B0, output F0, F1 );
-  wire   GNDI;
-
-  lut40136 nRAS_2_iv_0_a2_0( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40137 nRAS_2_iv_i( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40136 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h030C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40137 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'h00CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40138 un1_CS_0_sqmuxa_0_0_a2_1_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40080 un1_CS_0_sqmuxa_0_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40137 \ram2e_ufm/wb_dati_7_0_0_a3_14[7] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40138 \ram2e_ufm/wb_dati_7_0_0_a3_13_RNI81UL[7] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3406,15 +3976,23 @@ module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40138 ( input A, B, C, D, output Z );
+module lut40137 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40138 ( input A, B, C, D, output Z );
 
-  lut40139 un1_CS_0_sqmuxa_0_0_a2_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40066 un1_CS_0_sqmuxa_0_0_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40139 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40140 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3431,69 +4009,52 @@ endmodule
 
 module lut40139 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h070F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40140 nCS_6_u_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40141 nCS_6_u_i_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40140 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_83 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40141 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ( .A(A1), .B(B1), .C(GNDI), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40142 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40141 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40142 \wb_dati_7_0_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40143 \wb_dati_7_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40142 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40143 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40144 \wb_adr_7_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40145 \wb_adr_7_0_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40143 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40144 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3508,20 +4069,175 @@ module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
+module lut40143 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
 module lut40144 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8A88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0F04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40145 \ram2e_ufm/wb_dati_7_0_0_a3_10[7] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40146 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40145 ( input A, B, C, D, output Z );
 
+  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40146 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_86 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40147 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_1 ( .A(A1), .B(GNDI), .C(GNDI), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40148 \ram2e_ufm/wb_adr_7_i_i_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40147 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40148 ( input A, B, C, D, output Z );
+
   ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_87 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
 
-  lut40146 \wb_dati_7_0_a2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40147 \un1_LEDEN_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40149 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40150 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_m3 ( .A(GNDI), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40149 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40150 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hC0F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_88 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40151 \ram2e_ufm/wb_dati_7_0_0_a3_4_1_0[7] ( .A(GNDI), .B(B1), .C(GNDI), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40152 \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40151 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40152 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hEA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_89 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40153 \ram2e_ufm/wb_dati_7_0_0_a3_7[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40154 \ram2e_ufm/wb_dati_7_0_0_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40153 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h000A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40154 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40155 \ram2e_ufm/wb_dati_7_0_0_a3_1_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40156 \ram2e_ufm/wb_dati_7_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
 
   specify
@@ -3537,158 +4253,21 @@ module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40146 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40147 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_87 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40148 un1_CS_0_sqmuxa_0_0_a2_4_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40149 un1_CS_0_sqmuxa_0_0_a2_4( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40148 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40149 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_88 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40150 \FS_RNI9Q57[13] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40151 \wb_dati_7_0_o2_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40150 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hCCFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40151 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_89 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40152 \wb_adr_7_0_o2[0] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40153 \wb_adr_7_0_a2_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40152 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40153 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40154 \wb_dati_7_0_o2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40155 \wb_dati_7_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40154 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
 module lut40155 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
-  wire   GNDI;
-
-  lut40156 un1_CS_0_sqmuxa_0_0_a2_2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40103 un1_CS_0_sqmuxa_0_0_a2_2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0021) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40156 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40157 \wb_adr_7_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40158 \wb_adr_7_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40157 \ram2e_ufm/nRAS_s_i_0_a3_8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40158 \ram2e_ufm/nRAS_s_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3705,18 +4284,19 @@ endmodule
 
 module lut40157 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0C0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40158 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h3230) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40159 un1_CS_0_sqmuxa_0_0_a2_1_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40160 un1_CS_0_sqmuxa_0_0_a2_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40159 \ram2e_ufm/CKE_7s2_0_0_o3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40160 \ram2e_ufm/nCAS_s_i_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3733,18 +4313,22 @@ endmodule
 
 module lut40159 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40160 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_93 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40161 un1_CS_0_sqmuxa_0_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40162 un1_CS_0_sqmuxa_0_0_a2_3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40161 \ram2e_ufm/wb_dati_7_0_0_o2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40162 \ram2e_ufm/wb_dati_7_0_0_a3[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3752,7 +4336,6 @@ module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
@@ -3761,24 +4344,26 @@ endmodule
 
 module lut40161 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h6888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40162 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_94 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40163 wb_we_RNO_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40164 wb_we_RNO_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40163 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ( .A(GNDI), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40164 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -3789,22 +4374,22 @@ endmodule
 
 module lut40163 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF3F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40164 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40165 \RA_42_i_o2[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40166 \RA_0io_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40165 \ram2e_ufm/RA_35_0_0_o2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40166 \ram2e_ufm/RA_35_0_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -3818,124 +4403,22 @@ endmodule
 
 module lut40165 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEEC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40166 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_97 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40053 \wb_dati_7_0_a2_1[0] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40167 CKE_6_iv_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40167 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_98 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40168 un1_CS_0_sqmuxa_0_0_a2_16( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40169 un1_CS_0_sqmuxa_0_0_a2_4_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40168 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40169 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_99 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40170 un1_CS_0_sqmuxa_0_0_a2_12( .A(GNDI), .B(B1), .C(C1), .D(GNDI), 
+  lut40167 \ram2e_ufm/RA_35_0_0_o2_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), 
     .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40171 un1_CS_0_sqmuxa_0_0_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40170 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40171 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_100 ( input D1, C1, B1, D0, C0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40011 un1_CS_0_sqmuxa_0_0_a2_17( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40172 CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0( .A(A0), .B(GNDI), .C(C0), .D(D0), 
+  lut40168 \ram2e_ufm/RA_35_0_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
 
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40172 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40173 wb_reqc_1_RNIEO5C1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40174 \S_RNII9DO1_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
@@ -3949,20 +4432,115 @@ module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
+module lut40167 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0236) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40168 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_97 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40169 \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ( .A(GNDI), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40170 \ram2e_ufm/wb_dati_7_0_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40169 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40170 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_98 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40171 \ram2e_ufm/wb_dati_7_0_0_a3_9[7] ( .A(GNDI), .B(GNDI), .C(C1), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40172 \ram2e_ufm/wb_dati_7_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40171 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h00F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40172 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_99 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40173 \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ( .A(A1), .B(GNDI), .C(C1), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40174 \ram2e_ufm/wb_adr_7_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
 module lut40173 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40174 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hE209) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA2A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40175 \S_s_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40176 \BA_0io_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40175 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40176 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3979,24 +4557,26 @@ endmodule
 
 module lut40175 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8E0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40176 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hE4FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_101 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40177 \RA_0io_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40076 wb_req_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40177 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3 ( .A(GNDI), .B(B1), 
+    .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40178 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -4007,67 +4587,50 @@ endmodule
 
 module lut40177 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40178 \wb_dati_7_0_a2_3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40179 \wb_adr_7_0_a2_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40178 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hC5C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40179 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_102 ( input C1, B1, A1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
 
-  ROM16X1A #(16'hF400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40180 \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+  lut40179 \ram2e_ufm/CKE_7s2_0_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
     .Z(F1));
-  lut40077 \wb_dati_7_0_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40180 \ram2e_ufm/CKE_7s2_0_0 ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module lut40180 ( input A, B, C, D, output Z );
+module lut40179 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_106 ( input D1, C1, D0, C0, B0, output F0, F1 );
+module lut40180 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_103 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40181 \S_RNINI6S[1] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40181 \ram2e_ufm/wb_dati_7_0_0_0_o2[7] ( .A(GNDI), .B(GNDI), .C(C1), 
+    .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40182 CKE_6_iv_i_0_1_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40182 \ram2e_ufm/wb_adr_RNO_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -4075,33 +4638,36 @@ module SLICE_106 ( input D1, C1, D0, C0, B0, output F0, F1 );
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40181 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40182 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h2A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_107 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_104 ( input D1, C1, B1, A1, C0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40183 \S_r_i_o2[1] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40183 \ram2e_ufm/wb_dati_7_0_0_o2_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40184 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ( .A(A0), .B(GNDI), .C(C0), 
+    .D(GNDI), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40184 \BA_0io_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
@@ -4109,28 +4675,29 @@ endmodule
 
 module lut40183 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h60A4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40184 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_108 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_105 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40185 \wb_adr_7_0_a2_5_0[0] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40185 \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40186 \ram2e_ufm/N_285_i ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40186 \wb_dati_7_0_a2[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
@@ -4138,24 +4705,26 @@ endmodule
 
 module lut40185 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h000A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40186 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0F05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_106 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40187 \wb_dati_7_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40188 \wb_dati_7_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40024 \ram2e_ufm/S_r_i_0_o2[2] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40187 \ram2e_ufm/RA_35_2_0_a3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -4166,116 +4735,15 @@ endmodule
 
 module lut40187 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hB300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40188 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_107 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40189 \RA_0io_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40190 CmdBitbangMXO2_RNI8CSO1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40189 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0031) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40190 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_111 ( input D1, B1, A1, D0, C0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40191 \RA_42_3_0[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40026 \RA_0io_RNO[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40191 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hCCDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_112 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40192 nCS_6_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40193 \RA_0io_RNO[6] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40192 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40193 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hCC88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_113 ( input D1, C1, A1, D0, C0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40026 \RA_0io_RNO[2] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40026 \RA_0io_RNO[7] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40194 \wb_dati_7_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40195 \un1_RWMask_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40188 \ram2e_ufm/CKE_7_m1_0_0_o2_RNIGC501 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40189 \ram2e_ufm/RA_35_i_i_0_a3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
 
   specify
@@ -4291,26 +4759,119 @@ module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40194 ( input A, B, C, D, output Z );
+module lut40188 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40195 ( input A, B, C, D, output Z );
+module lut40189 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_115 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_108 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
   wire   GNDI;
 
-  lut40196 nWE80_pad_RNI3ICD( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40190 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40191 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ( .A(GNDI), 
+    .B(B0), .C(C0), .D(D0), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40197 nRWE_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40190 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40191 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0F03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_109 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40192 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_6 ( .A(GNDI), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40193 \ram2e_ufm/wb_we_RNO_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40192 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40193 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_110 ( input D1, C1, B1, A1, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40194 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_7 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40195 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ( .A(GNDI), .B(B0), 
+    .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40194 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40195 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_111 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40196 \ram2e_ufm/wb_dati_7_0_0_a3_2[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40197 \ram2e_ufm/wb_dati_7_0_0_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -4321,24 +4882,26 @@ endmodule
 
 module lut40196 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40197 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h5444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_116 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_112 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40198 \wb_adr_7_0_o2_2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  lut40198 \ram2e_ufm/nRAS_s_i_0_a3_6 ( .A(GNDI), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40199 \wb_dati_7_0_a2_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40199 \ram2e_ufm/nRAS_s_i_0_a3_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -4349,19 +4912,106 @@ endmodule
 
 module lut40198 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40199 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_117 ( input D1, C1, B1, A1, D0, B0, output F0, F1 );
+module ram2e_ufm_SLICE_113 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40200 \RWBank_5_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40150 LED_pad_RNO( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  lut40200 \ram2e_ufm/nRAS_s_i_0_a3_5 ( .A(GNDI), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40201 \ram2e_ufm/RA_35_2_0_a3_3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40200 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h000C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40201 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_114 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40202 \ram2e_ufm/wb_adr_RNO_2[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40203 \ram2e_ufm/wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40202 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hC03F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40203 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_115 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40131 \ram2e_ufm/un2_S_2_i_0_0_o3 ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40204 \ram2e_ufm/CKE_7s2_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40204 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_116 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40066 \ram2e_ufm/CmdExecMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40205 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ( .A(A0), .B(B0), 
+    .C(GNDI), .D(D0), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
@@ -4371,49 +5021,27 @@ module SLICE_117 ( input D1, C1, B1, A1, D0, B0, output F0, F1 );
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module lut40200 ( input A, B, C, D, output Z );
+module lut40205 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h2200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_118 ( input C1, B1, D0, C0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_117 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40201 un1_CS_0_sqmuxa_0_0_a2_11( .A(GNDI), .B(B1), .C(C1), .D(GNDI), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40202 un1_CS_0_sqmuxa_0_0_a2_13( .A(GNDI), .B(GNDI), .C(C0), .D(D0), 
-    .Z(F0));
+  lut40206 \ram2e_ufm/S_s_0_0_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40207 \ram2e_ufm/N_225_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40201 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40202 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_119 ( input D0, C0, B0, A0, output F0 );
-
-  lut40203 Ready_0_sqmuxa_0_a2_6_a2_2_0( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
-
-  specify
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -4422,11 +5050,847 @@ module SLICE_119 ( input D0, C0, B0, A0, output F0 );
 
 endmodule
 
-module lut40203 ( input A, B, C, D, output Z );
+module lut40206 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0F0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40207 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0015) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_118 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40208 \ram2e_ufm/CKE_7_m1_0_0_o2_RNI7FOA1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40209 \ram2e_ufm/N_201_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40208 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40209 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_119 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40210 \ram2e_ufm/S_r_i_0_o2_RNIBAU51[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40211 \ram2e_ufm/un1_CKE75_0_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40210 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40211 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hB5CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_120 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40212 \ram2e_ufm/DQMH_4_iv_0_0_i_i_a3_0_a3 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40213 \ram2e_ufm/N_507_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40212 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7707) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40213 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h888F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_121 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40214 \ram2e_ufm/Vout3_0_a3_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40215 \ram2e_ufm/RA_35_0_0_o2[11] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40214 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40215 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_122 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40216 \ram2e_ufm/nRWE_s_i_0_63_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40217 \ram2e_ufm/nCAS_s_i_0_m2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40216 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5EDE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40217 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h3F7A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_123 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40218 \ram2e_ufm/wb_adr_RNO_3[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40062 \ram2e_ufm/wb_dati_7_0_0_a3_8[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40218 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h3FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_124 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40219 \ram2e_ufm/RA_35_0_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40220 \ram2e_ufm/RA_35_0_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40219 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40220 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
+module ram2e_ufm_SLICE_125 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40221 \ram2e_ufm/wb_adr_7_i_i_o2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40061 \ram2e_ufm/wb_dati_7_0_0_a3_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40221 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7F4C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_126 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40222 \ram2e_ufm/wb_we_RNO_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40223 \ram2e_ufm/wb_adr_7_i_i_a3_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40222 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h70F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40223 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_127 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40224 \ram2e_ufm/un9_VOEEN_0_a2_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40225 \ram2e_ufm/RA_35_2_30_a3_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40224 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40225 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_128 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40226 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40227 \ram2e_ufm/wb_adr_RNO_4[1] ( .A(A0), .B(GNDI), .C(C0), .D(D0), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40226 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40227 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40228 \ram2e_ufm/BA_4[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40140 \ram2e_ufm/RA_35_2_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40228 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAB00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_130 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40229 \ram2e_ufm/N_187_i ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40230 \ram2e_ufm/wb_we_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40229 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h00F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40230 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_131 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40231 \ram2e_ufm/Ready3_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40232 \ram2e_ufm/wb_dati_7_0_0_0_a3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40231 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40232 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_132 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40233 \ram2e_ufm/RA_35_0_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40234 \ram2e_ufm/RA_35_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40233 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40234 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_133 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40235 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40236 \ram2e_ufm/SUM0_i_o2_2 ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40235 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40236 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFF3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_134 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40190 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ( .A(A1), 
+    .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40237 \ram2e_ufm/RA_35_0_0_a3[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40237 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hB800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_135 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40238 \ram2e_ufm/S_r_i_0_o2_0[1] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40239 \ram2e_ufm/RA_35_2_0_a3_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40238 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40239 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h002A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_136 ( input C1, B1, A1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40240 \ram2e_ufm/nRAS_s_i_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40241 \ram2e_ufm/un1_nDOE_i ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40240 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h3737) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40241 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hBBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_137 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40242 \ram2e_ufm/RDOE_i ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40243 \ram2e_ufm/LEDEN_RNI6G6M ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40242 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40243 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hBFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_138 ( input D1, B1, A1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40244 VOEEN_RNO( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40245 DOEEN_RNO( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40244 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1133) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40245 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_139 ( input B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40246 nVOE_pad_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40247 S_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40246 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40247 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_140 ( input B1, A1, C0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40025 \ram2e_ufm/RA_35_0_0_a3_0[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40248 \ram2e_ufm/RA_35_0_0_a3[5] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), 
+    .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40248 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_141 ( input D1, B1, D0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40075 \ram2e_ufm/RDout_i_0_i_a3[0] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40076 \ram2e_ufm/N_263_i ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_142 ( input D1, C1, A1, D0, C0, output F0, F1 );
+  wire   GNDI;
+
+  lut40227 \ram2e_ufm/CmdLEDGet_3_0_a3_1 ( .A(A1), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40249 \ram2e_ufm/RDout_i_i_a3[4] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40249 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_143 ( input D1, C1, D0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40250 \ram2e_ufm/RDout_i_0_i_a3[1] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40075 \ram2e_ufm/RDout_i_0_i_a3[7] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40250 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_144 ( input C1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40251 \ram2e_ufm/RDout_i_0_i_a3[2] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40252 \ram2e_ufm/RDout_i_0_i_a3[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40251 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40252 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_145 ( input D1, C1, B1, A1, D0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40253 \ram2e_ufm/wb_dati_7_0_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40254 \ram2e_ufm/wb_dati_7_0_0_o2_0[7] ( .A(A0), .B(GNDI), .C(GNDI), 
+    .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40253 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40254 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_146 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40255 \ram2e_ufm/RA_35_0_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40256 \ram2e_ufm/Ready3_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40255 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40256 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_147 ( input D1, C1, B1, A1, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40257 \ram2e_ufm/RWBank_3_0_0_o3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40195 \ram2e_ufm/RDout_i_0_i_a3[5] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40257 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
 module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
 
   xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
@@ -4449,7 +5913,7 @@ endmodule
 
 module LED ( input PADDO, output LED );
 
-  xo2iobuf0204 LED_pad( .I(PADDO), .PAD(LED));
+  xo2iobuf0258 LED_pad( .I(PADDO), .PAD(LED));
 
   specify
     (PADDO => LED) = (0:0:0,0:0:0);
@@ -4457,14 +5921,14 @@ module LED ( input PADDO, output LED );
 
 endmodule
 
-module xo2iobuf0204 ( input I, output PAD );
+module xo2iobuf0258 ( input I, output PAD );
 
   OB INST5( .I(I), .O(PAD));
 endmodule
 
 module C14M ( output PADDI, input C14M );
 
-  xo2iobuf0205 C14M_pad( .Z(PADDI), .PAD(C14M));
+  xo2iobuf0259 C14M_pad( .Z(PADDI), .PAD(C14M));
 
   specify
     (C14M => PADDI) = (0:0:0,0:0:0);
@@ -4474,71 +5938,11 @@ module C14M ( output PADDI, input C14M );
 
 endmodule
 
-module xo2iobuf0205 ( output Z, input PAD );
+module xo2iobuf0259 ( output Z, input PAD );
 
   IB INST1( .I(PAD), .O(Z));
 endmodule
 
-module DQMH ( input IOLDO, output DQMH );
-
-  xo2iobuf0204 DQMH_pad( .I(IOLDO), .PAD(DQMH));
-
-  specify
-    (IOLDO => DQMH) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module DQMH_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre DQMH_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module mfflsre ( input D0, SP, CK, LSR, output Q );
-
-  FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module DQML ( input IOLDO, output DQML );
-
-  xo2iobuf0204 DQML_pad( .I(IOLDO), .PAD(DQML));
-
-  specify
-    (IOLDO => DQML) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module DQML_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre DQML_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
 module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
 
   xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
@@ -4637,305 +6041,416 @@ module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
 
 endmodule
 
-module RA_11_ ( input IOLDO, output RA11 );
+module DQMH ( input IOLDO, output DQMH );
 
-  xo2iobuf0204 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));
+  xo2iobuf0258 DQMH_pad( .I(IOLDO), .PAD(DQMH));
 
   specify
-    (IOLDO => RA11) = (0:0:0,0:0:0);
+    (IOLDO => DQMH) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_11__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module DQMH_MGIOL ( output IOLDO, input OPOS, CE, CLK );
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0206 \RA_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre DQMH_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), 
     .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
-module mfflsre0206 ( input D0, SP, CK, LSR, output Q );
+module mfflsre ( input D0, SP, CK, LSR, output Q );
+
+  FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module DQML ( input IOLDO, output DQML );
+
+  xo2iobuf0258 DQML_pad( .I(IOLDO), .PAD(DQML));
+
+  specify
+    (IOLDO => DQML) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module DQML_MGIOL ( output IOLDO, input OPOS, CE, CLK );
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+
+  mfflsre DQML_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), 
+    .Q(IOLDO));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_11_ ( input IOLDO, output RAout11 );
+
+  xo2iobuf0258 \RAout_pad[11] ( .I(IOLDO), .PAD(RAout11));
+
+  specify
+    (IOLDO => RAout11) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_11__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0260 \RAout_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+  endspecify
+
+endmodule
+
+module mfflsre0260 ( input D0, SP, CK, LSR, output Q );
 
   FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module RA_10_ ( input IOLDO, output RA10 );
+module inverter ( input I, output Z );
 
-  xo2iobuf0204 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));
+  INV INST1( .A(I), .Z(Z));
+endmodule
+
+module RAout_10_ ( input IOLDO, output RAout10 );
+
+  xo2iobuf0258 \RAout_pad[10] ( .I(IOLDO), .PAD(RAout10));
 
   specify
-    (IOLDO => RA10) = (0:0:0,0:0:0);
+    (IOLDO => RAout10) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_10__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_10__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0206 \RA_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0260 \RAout_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_9_ ( input IOLDO, output RA9 );
+module RAout_9_ ( input IOLDO, output RAout9 );
 
-  xo2iobuf0204 \RA_pad[9] ( .I(IOLDO), .PAD(RA9));
+  xo2iobuf0258 \RAout_pad[9] ( .I(IOLDO), .PAD(RAout9));
 
   specify
-    (IOLDO => RA9) = (0:0:0,0:0:0);
+    (IOLDO => RAout9) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_9__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_9__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0206 \RA_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0260 \RAout_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_8_ ( input IOLDO, output RA8 );
+module RAout_8_ ( input IOLDO, output RAout8 );
 
-  xo2iobuf0204 \RA_pad[8] ( .I(IOLDO), .PAD(RA8));
+  xo2iobuf0258 \RAout_pad[8] ( .I(IOLDO), .PAD(RAout8));
 
   specify
-    (IOLDO => RA8) = (0:0:0,0:0:0);
+    (IOLDO => RAout8) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_8__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_8__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0206 \RA_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0260 \RAout_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_7_ ( input IOLDO, output RA7 );
+module RAout_7_ ( input IOLDO, output RAout7 );
 
-  xo2iobuf0204 \RA_pad[7] ( .I(IOLDO), .PAD(RA7));
+  xo2iobuf0258 \RAout_pad[7] ( .I(IOLDO), .PAD(RAout7));
 
   specify
-    (IOLDO => RA7) = (0:0:0,0:0:0);
+    (IOLDO => RAout7) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_7__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0206 \RA_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0260 \RAout_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_6_ ( input IOLDO, output RA6 );
+module RAout_6_ ( input IOLDO, output RAout6 );
 
-  xo2iobuf0204 \RA_pad[6] ( .I(IOLDO), .PAD(RA6));
+  xo2iobuf0258 \RAout_pad[6] ( .I(IOLDO), .PAD(RAout6));
 
   specify
-    (IOLDO => RA6) = (0:0:0,0:0:0);
+    (IOLDO => RAout6) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_6__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0206 \RA_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0260 \RAout_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_5_ ( input IOLDO, output RA5 );
+module RAout_5_ ( input IOLDO, output RAout5 );
 
-  xo2iobuf0204 \RA_pad[5] ( .I(IOLDO), .PAD(RA5));
+  xo2iobuf0258 \RAout_pad[5] ( .I(IOLDO), .PAD(RAout5));
 
   specify
-    (IOLDO => RA5) = (0:0:0,0:0:0);
+    (IOLDO => RAout5) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_5__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0206 \RA_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0260 \RAout_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_4_ ( input IOLDO, output RA4 );
+module RAout_4_ ( input IOLDO, output RAout4 );
 
-  xo2iobuf0204 \RA_pad[4] ( .I(IOLDO), .PAD(RA4));
+  xo2iobuf0258 \RAout_pad[4] ( .I(IOLDO), .PAD(RAout4));
 
   specify
-    (IOLDO => RA4) = (0:0:0,0:0:0);
+    (IOLDO => RAout4) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_4__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0206 \RA_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0260 \RAout_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_3_ ( input PADDO, output RA3 );
+module RAout_3_ ( input IOLDO, output RAout3 );
 
-  xo2iobuf0204 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
+  xo2iobuf0258 \RAout_pad[3] ( .I(IOLDO), .PAD(RAout3));
 
   specify
-    (PADDO => RA3) = (0:0:0,0:0:0);
+    (IOLDO => RAout3) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_2_ ( input IOLDO, output RA2 );
+module RAout_3__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  xo2iobuf0204 \RA_pad[2] ( .I(IOLDO), .PAD(RA2));
-
-  specify
-    (IOLDO => RA2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0206 \RA_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0260 \RAout_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_1_ ( input IOLDO, output RA1 );
+module RAout_2_ ( input IOLDO, output RAout2 );
 
-  xo2iobuf0204 \RA_pad[1] ( .I(IOLDO), .PAD(RA1));
+  xo2iobuf0258 \RAout_pad[2] ( .I(IOLDO), .PAD(RAout2));
 
   specify
-    (IOLDO => RA1) = (0:0:0,0:0:0);
+    (IOLDO => RAout2) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_2__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0206 \RA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0260 \RAout_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_0_ ( input PADDO, output RA0 );
+module RAout_1_ ( input IOLDO, output RAout1 );
 
-  xo2iobuf0204 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
+  xo2iobuf0258 \RAout_pad[1] ( .I(IOLDO), .PAD(RAout1));
 
   specify
-    (PADDO => RA0) = (0:0:0,0:0:0);
+    (IOLDO => RAout1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_1__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0260 \RAout_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+  endspecify
+
+endmodule
+
+module RAout_0_ ( input IOLDO, output RAout0 );
+
+  xo2iobuf0258 \RAout_pad[0] ( .I(IOLDO), .PAD(RAout0));
+
+  specify
+    (IOLDO => RAout0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_0__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0260 \RAout_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
 module BA_1_ ( input IOLDO, output BA1 );
 
-  xo2iobuf0204 \BA_pad[1] ( .I(IOLDO), .PAD(BA1));
+  xo2iobuf0258 \BA_pad[1] ( .I(IOLDO), .PAD(BA1));
 
   specify
     (IOLDO => BA1) = (0:0:0,0:0:0);
@@ -4943,16 +6458,16 @@ module BA_1_ ( input IOLDO, output BA1 );
 
 endmodule
 
-module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
-  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;
+module BA_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK );
+  wire   OPOS_dly, CLK_dly, CE_dly, LSR_dly;
 
-  mfflsre0207 \BA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), 
+  mfflsre0261 \BA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(LSR_dly), .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
@@ -4960,7 +6475,7 @@ module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
 
 endmodule
 
-module mfflsre0207 ( input D0, SP, CK, LSR, output Q );
+module mfflsre0261 ( input D0, SP, CK, LSR, output Q );
 
   FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
@@ -4968,7 +6483,7 @@ endmodule
 
 module BA_0_ ( input IOLDO, output BA0 );
 
-  xo2iobuf0204 \BA_pad[0] ( .I(IOLDO), .PAD(BA0));
+  xo2iobuf0258 \BA_pad[0] ( .I(IOLDO), .PAD(BA0));
 
   specify
     (IOLDO => BA0) = (0:0:0,0:0:0);
@@ -4976,16 +6491,16 @@ module BA_0_ ( input IOLDO, output BA0 );
 
 endmodule
 
-module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
-  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;
+module BA_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK );
+  wire   OPOS_dly, CLK_dly, CE_dly, LSR_dly;
 
-  mfflsre0207 \BA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), 
+  mfflsre0261 \BA_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(LSR_dly), .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
@@ -4993,144 +6508,131 @@ module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
 
 endmodule
 
-module nRWE ( input IOLDO, output nRWE );
+module nRWEout ( input IOLDO, output nRWEout );
 
-  xo2iobuf0204 nRWE_pad( .I(IOLDO), .PAD(nRWE));
+  xo2iobuf0258 nRWEout_pad( .I(IOLDO), .PAD(nRWEout));
 
   specify
-    (IOLDO => nRWE) = (0:0:0,0:0:0);
+    (IOLDO => nRWEout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nRWE_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nRWEout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nRWEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nCAS ( input IOLDO, output nCAS );
+module nCASout ( input IOLDO, output nCASout );
 
-  xo2iobuf0204 nCAS_pad( .I(IOLDO), .PAD(nCAS));
+  xo2iobuf0258 nCASout_pad( .I(IOLDO), .PAD(nCASout));
 
   specify
-    (IOLDO => nCAS) = (0:0:0,0:0:0);
+    (IOLDO => nCASout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nCAS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nCASout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nCASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nRAS ( input IOLDO, output nRAS );
+module nRASout ( input IOLDO, output nRASout );
 
-  xo2iobuf0204 nRAS_pad( .I(IOLDO), .PAD(nRAS));
+  xo2iobuf0258 nRASout_pad( .I(IOLDO), .PAD(nRASout));
 
   specify
-    (IOLDO => nRAS) = (0:0:0,0:0:0);
+    (IOLDO => nRASout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nRAS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nRASout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nRASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nCS ( input IOLDO, output nCS );
+module nCSout ( input PADDO, output nCSout );
 
-  xo2iobuf0204 nCS_pad( .I(IOLDO), .PAD(nCS));
+  xo2iobuf0258 nCSout_pad( .I(PADDO), .PAD(nCSout));
 
   specify
-    (IOLDO => nCS) = (0:0:0,0:0:0);
+    (PADDO => nCSout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nCS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module CKEout ( input IOLDO, output CKEout );
 
-  mfflsre nCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  xo2iobuf0258 CKEout_pad( .I(IOLDO), .PAD(CKEout));
+
+  specify
+    (IOLDO => CKEout) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module CKEout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0260 CKEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module CKE ( input IOLDO, output CKE );
-
-  xo2iobuf0204 CKE_pad( .I(IOLDO), .PAD(CKE));
-
-  specify
-    (IOLDO => CKE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module CKE_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre0206 CKE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
 module nVOE ( input PADDO, output nVOE );
 
-  xo2iobuf0204 nVOE_pad( .I(PADDO), .PAD(nVOE));
+  xo2iobuf0258 nVOE_pad( .I(PADDO), .PAD(nVOE));
 
   specify
     (PADDO => nVOE) = (0:0:0,0:0:0);
@@ -5140,7 +6642,7 @@ endmodule
 
 module Vout_7_ ( input IOLDO, output Vout7 );
 
-  xo2iobuf0204 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7));
+  xo2iobuf0258 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7));
 
   specify
     (IOLDO => Vout7) = (0:0:0,0:0:0);
@@ -5149,31 +6651,25 @@ module Vout_7_ ( input IOLDO, output Vout7 );
 endmodule
 
 module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0206 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0260 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
-module inverter ( input I, output Z );
-
-  INV INST1( .A(I), .Z(Z));
-endmodule
-
 module Vout_6_ ( input IOLDO, output Vout6 );
 
-  xo2iobuf0204 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6));
+  xo2iobuf0258 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6));
 
   specify
     (IOLDO => Vout6) = (0:0:0,0:0:0);
@@ -5182,26 +6678,25 @@ module Vout_6_ ( input IOLDO, output Vout6 );
 endmodule
 
 module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0206 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0260 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_5_ ( input IOLDO, output Vout5 );
 
-  xo2iobuf0204 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5));
+  xo2iobuf0258 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5));
 
   specify
     (IOLDO => Vout5) = (0:0:0,0:0:0);
@@ -5210,26 +6705,25 @@ module Vout_5_ ( input IOLDO, output Vout5 );
 endmodule
 
 module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0206 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0260 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_4_ ( input IOLDO, output Vout4 );
 
-  xo2iobuf0204 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4));
+  xo2iobuf0258 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4));
 
   specify
     (IOLDO => Vout4) = (0:0:0,0:0:0);
@@ -5238,26 +6732,25 @@ module Vout_4_ ( input IOLDO, output Vout4 );
 endmodule
 
 module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0206 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0260 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_3_ ( input IOLDO, output Vout3 );
 
-  xo2iobuf0204 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3));
+  xo2iobuf0258 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3));
 
   specify
     (IOLDO => Vout3) = (0:0:0,0:0:0);
@@ -5266,26 +6759,25 @@ module Vout_3_ ( input IOLDO, output Vout3 );
 endmodule
 
 module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0206 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0260 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_2_ ( input IOLDO, output Vout2 );
 
-  xo2iobuf0204 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2));
+  xo2iobuf0258 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2));
 
   specify
     (IOLDO => Vout2) = (0:0:0,0:0:0);
@@ -5294,26 +6786,25 @@ module Vout_2_ ( input IOLDO, output Vout2 );
 endmodule
 
 module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0206 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0260 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_1_ ( input IOLDO, output Vout1 );
 
-  xo2iobuf0204 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1));
+  xo2iobuf0258 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1));
 
   specify
     (IOLDO => Vout1) = (0:0:0,0:0:0);
@@ -5322,26 +6813,25 @@ module Vout_1_ ( input IOLDO, output Vout1 );
 endmodule
 
 module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0206 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0260 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_0_ ( input IOLDO, output Vout0 );
 
-  xo2iobuf0204 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0));
+  xo2iobuf0258 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0));
 
   specify
     (IOLDO => Vout0) = (0:0:0,0:0:0);
@@ -5350,26 +6840,25 @@ module Vout_0_ ( input IOLDO, output Vout0 );
 endmodule
 
 module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0206 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0260 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module nDOE ( input PADDO, output nDOE );
 
-  xo2iobuf0204 nDOE_pad( .I(PADDO), .PAD(nDOE));
+  xo2iobuf0258 nDOE_pad( .I(PADDO), .PAD(nDOE));
 
   specify
     (PADDO => nDOE) = (0:0:0,0:0:0);
@@ -5377,238 +6866,89 @@ module nDOE ( input PADDO, output nDOE );
 
 endmodule
 
-module Dout_7_ ( input IOLDO, output Dout7 );
+module Dout_7_ ( input PADDO, output Dout7 );
 
-  xo2iobuf0208 \Dout_pad[7] ( .I(IOLDO), .PAD(Dout7));
+  xo2iobuf0258 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
 
   specify
-    (IOLDO => Dout7) = (0:0:0,0:0:0);
+    (PADDO => Dout7) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module xo2iobuf0208 ( input I, output PAD );
+module Dout_6_ ( input PADDO, output Dout6 );
 
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module Dout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0206 \Dout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0258 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout6) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_6_ ( input IOLDO, output Dout6 );
+module Dout_5_ ( input PADDO, output Dout5 );
 
-  xo2iobuf0208 \Dout_pad[6] ( .I(IOLDO), .PAD(Dout6));
+  xo2iobuf0258 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
 
   specify
-    (IOLDO => Dout6) = (0:0:0,0:0:0);
+    (PADDO => Dout5) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_4_ ( input PADDO, output Dout4 );
 
-  mfflsre0206 \Dout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0258 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout4) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_5_ ( input IOLDO, output Dout5 );
+module Dout_3_ ( input PADDO, output Dout3 );
 
-  xo2iobuf0208 \Dout_pad[5] ( .I(IOLDO), .PAD(Dout5));
+  xo2iobuf0258 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
 
   specify
-    (IOLDO => Dout5) = (0:0:0,0:0:0);
+    (PADDO => Dout3) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_2_ ( input PADDO, output Dout2 );
 
-  mfflsre0206 \Dout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0258 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout2) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_4_ ( input IOLDO, output Dout4 );
+module Dout_1_ ( input PADDO, output Dout1 );
 
-  xo2iobuf0208 \Dout_pad[4] ( .I(IOLDO), .PAD(Dout4));
+  xo2iobuf0258 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
 
   specify
-    (IOLDO => Dout4) = (0:0:0,0:0:0);
+    (PADDO => Dout1) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_0_ ( input PADDO, output Dout0 );
 
-  mfflsre0206 \Dout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0258 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_3_ ( input IOLDO, output Dout3 );
-
-  xo2iobuf0208 \Dout_pad[3] ( .I(IOLDO), .PAD(Dout3));
-
-  specify
-    (IOLDO => Dout3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0206 \Dout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_2_ ( input IOLDO, output Dout2 );
-
-  xo2iobuf0208 \Dout_pad[2] ( .I(IOLDO), .PAD(Dout2));
-
-  specify
-    (IOLDO => Dout2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0206 \Dout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_1_ ( input IOLDO, output Dout1 );
-
-  xo2iobuf0208 \Dout_pad[1] ( .I(IOLDO), .PAD(Dout1));
-
-  specify
-    (IOLDO => Dout1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0206 \Dout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_0_ ( input IOLDO, output Dout0 );
-
-  xo2iobuf0208 \Dout_pad[0] ( .I(IOLDO), .PAD(Dout0));
-
-  specify
-    (IOLDO => Dout0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0206 \Dout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module Din_7_ ( output PADDI, input Din7 );
 
-  xo2iobuf0205 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
+  xo2iobuf0259 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
 
   specify
     (Din7 => PADDI) = (0:0:0,0:0:0);
@@ -5620,7 +6960,7 @@ endmodule
 
 module Din_6_ ( output PADDI, input Din6 );
 
-  xo2iobuf0205 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
+  xo2iobuf0259 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
 
   specify
     (Din6 => PADDI) = (0:0:0,0:0:0);
@@ -5632,7 +6972,7 @@ endmodule
 
 module Din_5_ ( output PADDI, input Din5 );
 
-  xo2iobuf0205 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
+  xo2iobuf0259 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
 
   specify
     (Din5 => PADDI) = (0:0:0,0:0:0);
@@ -5644,7 +6984,7 @@ endmodule
 
 module Din_4_ ( output PADDI, input Din4 );
 
-  xo2iobuf0205 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
+  xo2iobuf0259 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
 
   specify
     (Din4 => PADDI) = (0:0:0,0:0:0);
@@ -5656,7 +6996,7 @@ endmodule
 
 module Din_3_ ( output PADDI, input Din3 );
 
-  xo2iobuf0205 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
+  xo2iobuf0259 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
 
   specify
     (Din3 => PADDI) = (0:0:0,0:0:0);
@@ -5668,7 +7008,7 @@ endmodule
 
 module Din_2_ ( output PADDI, input Din2 );
 
-  xo2iobuf0205 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
+  xo2iobuf0259 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
 
   specify
     (Din2 => PADDI) = (0:0:0,0:0:0);
@@ -5680,7 +7020,7 @@ endmodule
 
 module Din_1_ ( output PADDI, input Din1 );
 
-  xo2iobuf0205 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
+  xo2iobuf0259 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
 
   specify
     (Din1 => PADDI) = (0:0:0,0:0:0);
@@ -5692,7 +7032,7 @@ endmodule
 
 module Din_0_ ( output PADDI, input Din0 );
 
-  xo2iobuf0205 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
+  xo2iobuf0259 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
 
   specify
     (Din0 => PADDI) = (0:0:0,0:0:0);
@@ -5704,7 +7044,7 @@ endmodule
 
 module Ain_7_ ( output PADDI, input Ain7 );
 
-  xo2iobuf0205 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7));
+  xo2iobuf0259 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7));
 
   specify
     (Ain7 => PADDI) = (0:0:0,0:0:0);
@@ -5716,7 +7056,7 @@ endmodule
 
 module Ain_6_ ( output PADDI, input Ain6 );
 
-  xo2iobuf0205 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6));
+  xo2iobuf0259 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6));
 
   specify
     (Ain6 => PADDI) = (0:0:0,0:0:0);
@@ -5728,7 +7068,7 @@ endmodule
 
 module Ain_5_ ( output PADDI, input Ain5 );
 
-  xo2iobuf0205 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5));
+  xo2iobuf0259 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5));
 
   specify
     (Ain5 => PADDI) = (0:0:0,0:0:0);
@@ -5740,7 +7080,7 @@ endmodule
 
 module Ain_4_ ( output PADDI, input Ain4 );
 
-  xo2iobuf0205 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4));
+  xo2iobuf0259 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4));
 
   specify
     (Ain4 => PADDI) = (0:0:0,0:0:0);
@@ -5752,7 +7092,7 @@ endmodule
 
 module Ain_3_ ( output PADDI, input Ain3 );
 
-  xo2iobuf0205 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3));
+  xo2iobuf0259 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3));
 
   specify
     (Ain3 => PADDI) = (0:0:0,0:0:0);
@@ -5764,7 +7104,7 @@ endmodule
 
 module Ain_2_ ( output PADDI, input Ain2 );
 
-  xo2iobuf0205 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2));
+  xo2iobuf0259 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2));
 
   specify
     (Ain2 => PADDI) = (0:0:0,0:0:0);
@@ -5776,7 +7116,7 @@ endmodule
 
 module Ain_1_ ( output PADDI, input Ain1 );
 
-  xo2iobuf0205 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1));
+  xo2iobuf0259 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1));
 
   specify
     (Ain1 => PADDI) = (0:0:0,0:0:0);
@@ -5788,7 +7128,7 @@ endmodule
 
 module Ain_0_ ( output PADDI, input Ain0 );
 
-  xo2iobuf0205 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0));
+  xo2iobuf0259 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0));
 
   specify
     (Ain0 => PADDI) = (0:0:0,0:0:0);
@@ -5800,7 +7140,7 @@ endmodule
 
 module nC07X ( output PADDI, input nC07X );
 
-  xo2iobuf0205 nC07X_pad( .Z(PADDI), .PAD(nC07X));
+  xo2iobuf0259 nC07X_pad( .Z(PADDI), .PAD(nC07X));
 
   specify
     (nC07X => PADDI) = (0:0:0,0:0:0);
@@ -5812,7 +7152,7 @@ endmodule
 
 module nEN80 ( output PADDI, input nEN80 );
 
-  xo2iobuf0205 nEN80_pad( .Z(PADDI), .PAD(nEN80));
+  xo2iobuf0259 nEN80_pad( .Z(PADDI), .PAD(nEN80));
 
   specify
     (nEN80 => PADDI) = (0:0:0,0:0:0);
@@ -5822,21 +7162,9 @@ module nEN80 ( output PADDI, input nEN80 );
 
 endmodule
 
-module nWE80 ( output PADDI, input nWE80 );
-
-  xo2iobuf0205 nWE80_pad( .Z(PADDI), .PAD(nWE80));
-
-  specify
-    (nWE80 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nWE80, 0:0:0);
-    $width (negedge nWE80, 0:0:0);
-  endspecify
-
-endmodule
-
 module nWE ( output PADDI, input nWE );
 
-  xo2iobuf0205 nWE_pad( .Z(PADDI), .PAD(nWE));
+  xo2iobuf0259 nWE_pad( .Z(PADDI), .PAD(nWE));
 
   specify
     (nWE => PADDI) = (0:0:0,0:0:0);
@@ -5848,7 +7176,7 @@ endmodule
 
 module PHI1 ( output PADDI, input PHI1 );
 
-  xo2iobuf0205 PHI1_pad( .Z(PADDI), .PAD(PHI1));
+  xo2iobuf0259 PHI1_pad( .Z(PADDI), .PAD(PHI1));
 
   specify
     (PHI1 => PADDI) = (0:0:0,0:0:0);
@@ -5861,7 +7189,7 @@ endmodule
 module PHI1_MGIOL ( input DI, CLK, output IN );
   wire   VCCI, GNDI, DI_dly, CLK_dly;
 
-  smuxlregsre PHI1reg_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  smuxlregsre PHI1r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
     .Q(IN));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
@@ -5881,14 +7209,14 @@ module smuxlregsre ( input D0, SP, CK, LSR, output Q );
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, 
-    WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, 
-    WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output 
-    WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, 
-    WBACKO );
+module ram2e_ufm_ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, 
+    WBWEI, WBADRI0, WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, 
+    WBADRI7, WBDATI0, WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, 
+    WBDATI7, output WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, 
+    WBDATO6, WBDATO7, WBACKO );
   wire   VCCI, GNDI;
 
-  EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), 
+  EFB_B \ram2e_ufm/ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), 
     .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), 
     .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), 
     .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), 
diff --git a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html
index 63b2b29..7c84143 100644
--- a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html
+++ b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html
@@ -1,10 +1,12 @@
 <HTML>         	<HEAD><TITLE></TITLE>                                   	<STYLE TYPE="text/css">                               	<!--                                                    	body,pre{                                              	font-family:'Courier New', monospace;             	color: #000000;                                     	font-size:88%;                                      	background-color: #ffffff;                          	}                                                       	h1 {                                                    	font-weight: bold;                                  	margin-top: 24px;                                   	margin-bottom: 10px;                                	border-bottom: 3px solid #000;    font-size: 1em;   	}                                                       	h2 {                                                    	font-weight: bold;                                  	margin-top: 18px;                                   	margin-bottom: 5px;                                 	font-size: 0.90em;                                  	}                                                       	h3 {                                                    	font-weight: bold;                                  	margin-top: 12px;                                   	margin-bottom: 5px;                                 	font-size: 0.80em;                                       	}                                                       	p {                                                     	font-size:78%;                                      	}                                                       	P.Table {                                               	margin-top: 4px;                                    	margin-bottom: 4px;                                 	margin-right: 4px;                                  	margin-left: 4px;                                   	}                                                       	table                                                   	{                                                       	border-width: 1px 1px 1px 1px;                      	border-style: solid solid solid solid;              	border-color: black black black black;              	border-collapse: collapse;                          	}                                                       	th {                                                    	font-weight:bold;                                   	padding: 4px;                                       	border-width: 1px 1px 1px 1px;                      	border-style: solid solid solid solid;              	border-color: black black black black;              	vertical-align:top;                                 	text-align:left;                                    	font-size:78%;                                           	}                                                       	td {                                                    	padding: 4px;                                       	border-width: 1px 1px 1px 1px;                      	border-style: solid solid solid solid;              	border-color: black black black black;              	vertical-align:top;                                 	font-size:78%;                                      	}                                                       	a {                                                     	color:#013C9A;                                      	text-decoration:none;                               	}                                                       		a:visited {                                             	color:#013C9A;                                      	}                                                       		a:hover, a:active {                                     	text-decoration:underline;                          	color:#5BAFD4;                                      	}                                                       	.pass                                                   	{                                                       	background-color: #00ff00;                              	}                                                                	.fail                                                   	{                                                       	background-color: #ff0000;                              	}                                                       	.comment                                                	{                                                       	font-size: 90%;                                     	font-style: italic;                                 	}                                                       		-->                                                     	</STYLE>                                                	</HEAD>                                                 	<BODY>                                                  	<PRE>Setting log file to '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html'.
 Starting: parse design source files
 (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
-(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v'
+(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v'
+(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v'
 (VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v'
-INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E'
-INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v(1,1-831,10) (VERI-9000) elaborating module 'RAM2E'
+INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E'
+INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-463,10) (VERI-9000) elaborating module 'RAM2E'
+INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-333,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
 INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
 INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
 INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior b/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior
index 14f4acc..be29cb8 100644
--- a/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior
+++ b/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior
@@ -29,7 +29,7 @@ Performance Hardware Data Status:   Final          Version 34.4.
 // Package: TQFP100
 // ncd File: ram2e_lcmxo2_1200hc_impl1.ncd
 // Version: Diamond (64-bit) 3.12.1.454
-// Written on Thu Sep 21 05:35:11 2023
+// Written on Thu Dec 28 23:10:20 2023
 // M: Minimum Performance Grade
 // iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
 
@@ -41,80 +41,78 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
 
 Port   Clock Edge  Setup Performance_Grade  Hold Performance_Grade
 ----------------------------------------------------------------------
-Ain[0] C14M  R    -0.231      M       2.350     4
-Ain[1] C14M  R     1.429      4       0.543     4
-Ain[2] C14M  R     1.518      4       0.412     4
-Ain[3] C14M  R    -0.231      M       2.350     4
-Ain[4] C14M  R     0.212      4       1.560     4
-Ain[5] C14M  R     0.742      4       1.110     4
-Ain[6] C14M  R     0.469      4       1.329     4
-Ain[7] C14M  R     1.416      4       0.531     4
-Din[0] C14M  R     8.327      4       1.958     4
-Din[1] C14M  R     5.826      4       2.521     4
-Din[2] C14M  R     6.539      4       2.135     4
-Din[3] C14M  R     5.849      4       2.648     4
-Din[4] C14M  R     7.061      4       2.095     4
-Din[5] C14M  R     6.295      4       2.894     4
-Din[6] C14M  R     4.991      4       2.892     4
-Din[7] C14M  R     6.416      4       2.971     4
-PHI1   C14M  R     1.151      4       4.842     4
-RD[0]  C14M  F    -0.266      M       3.107     4
-RD[1]  C14M  F    -0.248      M       3.183     4
-RD[2]  C14M  F    -0.105      M       2.610     4
-RD[3]  C14M  F    -0.243      M       3.107     4
-RD[4]  C14M  F     0.103      4       2.201     4
-RD[5]  C14M  F    -0.092      M       2.192     4
-RD[6]  C14M  F    -0.084      M       1.756     4
-RD[7]  C14M  F    -0.092      M       2.661     4
-nC07X  C14M  R    -0.316      M       2.625     4
-nEN80  C14M  R     5.220      4       0.032     M
-nWE    C14M  R    -0.093      M       2.033     4
-nWE80  C14M  R     1.630      4       0.329     6
+Ain[0] C14M  R     0.163      4       1.694     4
+Ain[1] C14M  R    -0.150      M       2.217     4
+Ain[2] C14M  R    -0.080      M       2.156     4
+Ain[3] C14M  R     0.466      4       1.338     4
+Ain[4] C14M  R     0.215      4       1.597     4
+Ain[5] C14M  R    -0.331      M       2.651     4
+Ain[6] C14M  R     0.065      M       1.882     4
+Ain[7] C14M  R     0.284      4       1.683     4
+Din[0] C14M  R     6.887      4       2.257     4
+Din[1] C14M  R     8.753      4       2.907     4
+Din[2] C14M  R     6.379      4       2.740     4
+Din[3] C14M  R     7.129      4       1.402     4
+Din[4] C14M  R     6.869      4       2.791     4
+Din[5] C14M  R     6.514      4       2.334     4
+Din[6] C14M  R     6.735      4       1.914     4
+Din[7] C14M  R     8.094      4       1.968     4
+PHI1   C14M  R     1.557      4       4.842     4
+RD[0]  C14M  R    -0.266      M       2.342     4
+RD[1]  C14M  R    -0.248      M       2.283     4
+RD[2]  C14M  R    -0.407      M       2.610     4
+RD[3]  C14M  R    -0.243      M       2.193     4
+RD[4]  C14M  R    -0.246      M       2.201     4
+RD[5]  C14M  R    -0.243      M       2.193     4
+RD[6]  C14M  R    -0.087      M       1.756     4
+RD[7]  C14M  R    -0.092      M       1.769     4
+nC07X  C14M  R    -0.320      M       2.703     4
+nEN80  C14M  R     4.607      4       1.925     4
+nWE    C14M  R     4.609      4       2.010     4
 
 
 // Clock to Output Delay
 
-Port    Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+Port      Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
 ------------------------------------------------------------------------
-BA[0]   C14M  R    10.424         4        3.355          M
-BA[1]   C14M  R    10.424         4        3.355          M
-CKE     C14M  R    10.424         4        3.355          M
-DQMH    C14M  R    10.404         4        3.362          M
-DQML    C14M  R    10.404         4        3.362          M
-Dout[0] C14M  F    10.750         4        3.634          M
-Dout[1] C14M  F    10.750         4        3.634          M
-Dout[2] C14M  F    10.739         4        3.628          M
-Dout[3] C14M  F    10.750         4        3.634          M
-Dout[4] C14M  F    10.739         4        3.628          M
-Dout[5] C14M  F    10.739         4        3.628          M
-Dout[6] C14M  F    10.750         4        3.634          M
-Dout[7] C14M  F    10.750         4        3.634          M
-LED     C14M  R    21.299         4        8.576          M
-RA[0]   C14M  R    12.236         4        3.758          M
-RA[10]  C14M  R    10.490         4        3.360          M
-RA[11]  C14M  R    10.424         4        3.355          M
-RA[1]   C14M  R    10.490         4        3.360          M
-RA[2]   C14M  R    10.490         4        3.360          M
-RA[3]   C14M  R    11.808         4        3.656          M
-RA[4]   C14M  R    10.490         4        3.360          M
-RA[5]   C14M  R    10.490         4        3.360          M
-RA[6]   C14M  R    10.490         4        3.360          M
-RA[7]   C14M  R    10.490         4        3.360          M
-RA[8]   C14M  R    10.490         4        3.360          M
-RA[9]   C14M  R    10.490         4        3.360          M
-Vout[0] C14M  F    11.348         4        3.872          M
-Vout[1] C14M  F    11.434         4        3.871          M
-Vout[2] C14M  F    11.348         4        3.872          M
-Vout[3] C14M  F    11.434         4        3.871          M
-Vout[4] C14M  F    11.348         4        3.872          M
-Vout[5] C14M  F    11.348         4        3.872          M
-Vout[6] C14M  F    11.434         4        3.871          M
-Vout[7] C14M  F    11.434         4        3.871          M
-nCAS    C14M  R    10.424         4        3.355          M
-nCS     C14M  R    10.424         4        3.355          M
-nDOE    C14M  R    14.217         4        4.353          M
-nRAS    C14M  R    10.424         4        3.355          M
-nRWE    C14M  R    10.424         4        3.355          M
+BA[0]     C14M  R    10.424         4        3.355          M
+BA[1]     C14M  R    10.424         4        3.355          M
+CKEout    C14M  F    10.424         4        3.355          M
+DQMH      C14M  R    10.404         4        3.362          M
+DQML      C14M  R    10.404         4        3.362          M
+LED       C14M  R    22.936         4        8.890          M
+RAout[0]  C14M  F    10.490         4        3.360          M
+RAout[10] C14M  F    10.490         4        3.360          M
+RAout[11] C14M  F    10.424         4        3.355          M
+RAout[1]  C14M  F    10.490         4        3.360          M
+RAout[2]  C14M  F    10.490         4        3.360          M
+RAout[3]  C14M  F    10.490         4        3.360          M
+RAout[4]  C14M  F    10.490         4        3.360          M
+RAout[5]  C14M  F    10.490         4        3.360          M
+RAout[6]  C14M  F    10.490         4        3.360          M
+RAout[7]  C14M  F    10.490         4        3.360          M
+RAout[8]  C14M  F    10.490         4        3.360          M
+RAout[9]  C14M  F    10.490         4        3.360          M
+RD[0]     C14M  R    13.733         4        3.707          M
+RD[1]     C14M  R    13.745         4        3.707          M
+RD[2]     C14M  R    14.285         4        3.790          M
+RD[3]     C14M  R    13.348         4        3.790          M
+RD[4]     C14M  R    14.450         4        3.952          M
+RD[5]     C14M  R    14.480         4        3.952          M
+RD[6]     C14M  R    14.784         4        3.952          M
+RD[7]     C14M  R    14.247         4        3.952          M
+Vout[0]   C14M  R    11.348         4        3.872          M
+Vout[1]   C14M  R    11.434         4        3.871          M
+Vout[2]   C14M  R    11.348         4        3.872          M
+Vout[3]   C14M  R    11.434         4        3.871          M
+Vout[4]   C14M  R    11.348         4        3.872          M
+Vout[5]   C14M  R    11.348         4        3.872          M
+Vout[6]   C14M  R    11.434         4        3.871          M
+Vout[7]   C14M  R    11.434         4        3.871          M
+nCASout   C14M  F    10.424         4        3.355          M
+nDOE      C14M  R    13.929         4        4.309          M
+nRASout   C14M  F    10.424         4        3.355          M
+nRWEout   C14M  F    10.424         4        3.355          M
+nVOE      C14M  R    13.926         4        4.281          M
 WARNING: you must also run trce with hold speed: 4
-WARNING: you must also run trce with hold speed: 6
 WARNING: you must also run trce with setup speed: M
diff --git a/CPLD/LCMXO2-1200HC/promote.xml b/CPLD/LCMXO2-1200HC/promote.xml
index fc0beb9..b1d2d7e 100644
--- a/CPLD/LCMXO2-1200HC/promote.xml
+++ b/CPLD/LCMXO2-1200HC/promote.xml
@@ -1,3 +1,3 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Sep 21 05:35:49 2023" vendor="Lattice Semiconductor Corporation" >
+<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:11:37 2023" vendor="Lattice Semiconductor Corporation" >
 </userSetting>
diff --git a/CPLD/LCMXO2-1200HC/reportview.xml b/CPLD/LCMXO2-1200HC/reportview.xml
index 145f9dd..7c96405 100644
--- a/CPLD/LCMXO2-1200HC/reportview.xml
+++ b/CPLD/LCMXO2-1200HC/reportview.xml
@@ -3,7 +3,7 @@
 <ReportView version="2.0">
     <Implement name="impl1">
         <ToolReport id="tooldec" path="" status="0"/>
-        <ToolReport id="toolhle_genhierarchy" path="Y:/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html" status="1"/>
+        <ToolReport id="toolhle_genhierarchy" path="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html" status="1"/>
         <ToolReport id="toolpio" path="" status="2"/>
         <ToolReport id="toolsso" path="" status="2"/>
     </Implement>
diff --git a/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf b/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf
index 7165bc8..584a95c 100644
--- a/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf
+++ b/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf
@@ -3,9 +3,12 @@
     <Options/>
     <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
         <Options def_top="RAM2E" top="RAM2E"/>
-        <Source name="../RAM2E-LCMXO2.v" type="Verilog" type_short="Verilog">
+        <Source name="../RAM2E.v" type="Verilog" type_short="Verilog">
             <Options top_module="RAM2E"/>
         </Source>
+        <Source name="../UFM-LCMXO2.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
         <Source name="REFB.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
diff --git a/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html
index decf099..fed6f25 100644
--- a/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html
+++ b/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html
@@ -6,12 +6,39 @@
 -->
 </STYLE>
 </HEAD>
-<PRE><A name="pn230921045933"></A><B><U><big>pn230921045933</big></U></B>
-#Start recording tcl command: 9/21/2023 04:58:25
-#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
-prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
+<PRE><A name="pn231205230924"></A><B><U><big>pn231205230924</big></U></B>
+#Start recording tcl command: 12/5/2023 14:55:22
+#Project Location: //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
+prj_project open "//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_project save
+prj_project close
+#Stop recording: 12/5/2023 23:09:24
+
+
+
+<A name="pn231226232445"></A><B><U><big>pn231226232445</big></U></B>
+#Start recording tcl command: 12/26/2023 18:23:53
+#Project Location: //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
+prj_project open "//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1 -task IBIS
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1
 prj_run Export -impl impl1 -forceAll
-#Stop recording: 9/21/2023 04:59:33
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1
+prj_run Export -impl impl1 -forceAll
+prj_run Export -impl impl1 -forceAll
+prj_src remove "//Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.v"
+#Stop recording: 12/26/2023 23:24:45
 
 
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt
index feef941..c423c9a 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt
@@ -1,14 +1,12 @@
 NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
 NOTE All Rights Reserved *
-NOTE DATE CREATED: Thu Sep 21 05:35:24 2023 *
+NOTE DATE CREATED: Thu Dec 28 23:10:32 2023 *
 NOTE DESIGN NAME: RAM2E *
 NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
 NOTE PIN ASSIGNMENTS *
 NOTE PINS RD[0] : 36 : inout *
 NOTE PINS LED : 35 : out *
 NOTE PINS C14M : 62 : in *
-NOTE PINS DQMH : 49 : out *
-NOTE PINS DQML : 48 : out *
 NOTE PINS RD[7] : 43 : inout *
 NOTE PINS RD[6] : 42 : inout *
 NOTE PINS RD[5] : 41 : inout *
@@ -16,25 +14,27 @@ NOTE PINS RD[4] : 40 : inout *
 NOTE PINS RD[3] : 39 : inout *
 NOTE PINS RD[2] : 38 : inout *
 NOTE PINS RD[1] : 37 : inout *
-NOTE PINS RA[11] : 59 : out *
-NOTE PINS RA[10] : 64 : out *
-NOTE PINS RA[9] : 63 : out *
-NOTE PINS RA[8] : 65 : out *
-NOTE PINS RA[7] : 67 : out *
-NOTE PINS RA[6] : 69 : out *
-NOTE PINS RA[5] : 71 : out *
-NOTE PINS RA[4] : 75 : out *
-NOTE PINS RA[3] : 74 : out *
-NOTE PINS RA[2] : 70 : out *
-NOTE PINS RA[1] : 68 : out *
-NOTE PINS RA[0] : 66 : out *
+NOTE PINS DQMH : 49 : out *
+NOTE PINS DQML : 48 : out *
+NOTE PINS RAout[11] : 59 : out *
+NOTE PINS RAout[10] : 64 : out *
+NOTE PINS RAout[9] : 63 : out *
+NOTE PINS RAout[8] : 65 : out *
+NOTE PINS RAout[7] : 67 : out *
+NOTE PINS RAout[6] : 69 : out *
+NOTE PINS RAout[5] : 71 : out *
+NOTE PINS RAout[4] : 75 : out *
+NOTE PINS RAout[3] : 74 : out *
+NOTE PINS RAout[2] : 70 : out *
+NOTE PINS RAout[1] : 68 : out *
+NOTE PINS RAout[0] : 66 : out *
 NOTE PINS BA[1] : 60 : out *
 NOTE PINS BA[0] : 58 : out *
-NOTE PINS nRWE : 51 : out *
-NOTE PINS nCAS : 52 : out *
-NOTE PINS nRAS : 54 : out *
-NOTE PINS nCS : 57 : out *
-NOTE PINS CKE : 53 : out *
+NOTE PINS nRWEout : 51 : out *
+NOTE PINS nCASout : 52 : out *
+NOTE PINS nRASout : 54 : out *
+NOTE PINS nCSout : 57 : out *
+NOTE PINS CKEout : 53 : out *
 NOTE PINS nVOE : 10 : out *
 NOTE PINS Vout[7] : 12 : out *
 NOTE PINS Vout[6] : 14 : out *
@@ -71,7 +71,6 @@ NOTE PINS Ain[1] : 2 : in *
 NOTE PINS Ain[0] : 3 : in *
 NOTE PINS nC07X : 34 : in *
 NOTE PINS nEN80 : 82 : in *
-NOTE PINS nWE80 : 83 : in *
 NOTE PINS nWE : 29 : in *
 NOTE PINS PHI1 : 85 : in *
 NOTE CONFIGURATION MODE: NONE *
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.areasrr b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.areasrr
index 9749d2a..545fb4f 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.areasrr
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.areasrr
@@ -1,41 +1,61 @@
 ----------------------------------------------------------------------
 Report for cell RAM2E.verilog
 
-Register bits: 111 of 640 (17%)
+Register bits: 122 of 640 (19%)
 PIC Latch:       0
-I/O cells:       70
+I/O cells:       69
                                           Cell usage:
                                cell       count    Res Usage(%)
                                  BB        8       100.0
                               CCU2D        9       100.0
                                 EFB        1       100.0
-                            FD1P3AX       48       100.0
+                            FD1P3AX       61       100.0
                             FD1P3IX        1       100.0
-                            FD1S3AX       22       100.0
-                            FD1S3IX        4       100.0
+                            FD1S3AX       21       100.0
+                            FD1S3AY        4       100.0
+                            FD1S3IX        6       100.0
                                 GSR        1       100.0
-                                 IB       22       100.0
+                                 IB       21       100.0
                            IFS1P3DX        1       100.0
                                 INV        1       100.0
                                  OB       40       100.0
-                           OFS1P3BX        6       100.0
-                           OFS1P3DX       27       100.0
+                           OFS1P3BX        5       100.0
+                           OFS1P3DX       21       100.0
                            OFS1P3IX        2       100.0
-                           ORCALUT4      221       100.0
+                           ORCALUT4      277       100.0
+                              PFUMX        3       100.0
                                 PUR        1       100.0
-                                VHI        2       100.0
-                                VLO        2       100.0
+                                VHI        3       100.0
+                                VLO        3       100.0
 SUB MODULES 
+                          RAM2E_UFM        1       100.0
                                REFB        1       100.0
                             
-                         TOTAL           420           
+                         TOTAL           492           
 ----------------------------------------------------------------------
-Report for cell REFB.netlist
-     Instance path:  ufmefb
+Report for cell RAM2E_UFM.netlist
+     Instance path:  ram2e_ufm
                                           Cell usage:
                                cell       count    Res Usage(%)
                                 EFB        1       100.0
-                                VHI        1        50.0
-                                VLO        1        50.0
+                            FD1P3AX       30        49.2
+                            FD1P3IX        1       100.0
+                            FD1S3IX        1        16.7
+                           ORCALUT4      272        98.2
+                              PFUMX        3       100.0
+                                VHI        2        66.7
+                                VLO        2        66.7
+SUB MODULES 
+                               REFB        1       100.0
+                            
+                         TOTAL           313           
+----------------------------------------------------------------------
+Report for cell REFB.netlist
+     Instance path:  ram2e_ufm.ufmefb
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                                EFB        1       100.0
+                                VHI        1        33.3
+                                VLO        1        33.3
                             
                          TOTAL             3           
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn
index 0abdd18..d9a4ab2 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn
@@ -4,10 +4,10 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Sep 21 05:35:20 2023
+Thu Dec 28 23:10:28 2023
 
 
-Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
 
 Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
 Design name: RAM2E
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bit b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bit
index ae6963e60624f98a32c606a765eab4ef16b528c7..bdb8c2844bf33a48f141e35ff0400dced8e8d91c 100644
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diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.edi b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.edi
index a5617d9..f5e583a 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.edi
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.edi
@@ -4,7 +4,7 @@
   (keywordMap (keywordLevel 0))
   (status
     (written
-      (timeStamp 2023 9 21 5 34 43)
+      (timeStamp 2023 12 28 23 9 53)
       (author "Synopsys, Inc.")
       (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
      )
@@ -70,6 +70,15 @@
          )
        )
     )
+    (cell FD1S3AY (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port D (direction INPUT))
+           (port CK (direction INPUT))
+           (port Q (direction OUTPUT))
+         )
+       )
+    )
     (cell FD1S3AX (cellType GENERIC)
        (view PRIM (viewType NETLIST)
          (interface
@@ -155,6 +164,16 @@
          )
        )
     )
+    (cell PFUMX (cellType GENERIC)
+       (view PRIM (viewType NETLIST)
+         (interface
+           (port ALUT (direction INPUT))
+           (port BLUT (direction INPUT))
+           (port C0 (direction INPUT))
+           (port Z (direction OUTPUT))
+         )
+       )
+    )
     (cell GSR (cellType GENERIC)
        (view PRIM (viewType NETLIST)
          (interface
@@ -726,248 +745,184 @@
         (property orig_inst_of (string "REFB"))
        )
     )
-    (cell RAM2E (cellType GENERIC)
-       (view verilog (viewType NETLIST)
+    (cell RAM2E_UFM (cellType GENERIC)
+       (view netlist (viewType NETLIST)
          (interface
-           (port C14M (direction INPUT))
-           (port PHI1 (direction INPUT))
-           (port LED (direction OUTPUT))
-           (port nWE (direction INPUT))
-           (port nWE80 (direction INPUT))
-           (port nEN80 (direction INPUT))
-           (port nC07X (direction INPUT))
-           (port (array (rename ain "Ain[7:0]") 8) (direction INPUT))
-           (port (array (rename din "Din[7:0]") 8) (direction INPUT))
-           (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT))
-           (port nDOE (direction OUTPUT))
-           (port (array (rename vout "Vout[7:0]") 8) (direction OUTPUT))
-           (port nVOE (direction OUTPUT))
-           (port CKE (direction OUTPUT))
-           (port nCS (direction OUTPUT))
-           (port nRAS (direction OUTPUT))
-           (port nCAS (direction OUTPUT))
-           (port nRWE (direction OUTPUT))
-           (port (array (rename ba "BA[1:0]") 2) (direction OUTPUT))
-           (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT))
-           (port (array (rename rd "RD[7:0]") 8) (direction INOUT))
-           (port DQML (direction OUTPUT))
-           (port DQMH (direction OUTPUT))
+           (port (array (rename ra_35 "RA_35[11:0]") 12) (direction OUTPUT))
+           (port (array (rename ain_c "Ain_c[7:0]") 8) (direction INPUT))
+           (port CmdTout_3_0 (direction OUTPUT))
+           (port (array (rename rwbank "RWBank[7:0]") 8) (direction INPUT))
+           (port (array (rename fs "FS[15:0]") 16) (direction INPUT))
+           (port (array (rename ra "RA[11:0]") 12) (direction INPUT))
+           (port (array (rename rc_3 "RC_3[2:1]") 2) (direction OUTPUT))
+           (port (array (rename rwbank_3 "RWBank_3[7:0]") 8) (direction OUTPUT))
+           (port (array (rename din_c "Din_c[7:0]") 8) (direction INPUT))
+           (port S_s_0_0_0 (direction OUTPUT))
+           (port (array (rename ba_4 "BA_4[1:0]") 2) (direction OUTPUT))
+           (port (array (rename cs "CS[2:0]") 3) (direction INPUT))
+           (port (array (rename cmdtout "CmdTout[2:1]") 2) (direction INPUT))
+           (port (array (rename rc "RC[2:1]") 2) (direction INPUT))
+           (port (array (rename s "S[3:0]") 4) (direction INPUT))
+           (port N_359_i (direction OUTPUT))
+           (port CmdRWMaskSet_3 (direction OUTPUT))
+           (port CmdLEDSet_3 (direction OUTPUT))
+           (port N_667 (direction OUTPUT))
+           (port N_666 (direction OUTPUT))
+           (port N_665 (direction OUTPUT))
+           (port N_664 (direction OUTPUT))
+           (port N_663 (direction OUTPUT))
+           (port N_662 (direction OUTPUT))
+           (port N_648 (direction OUTPUT))
+           (port CmdSetRWBankFFLED (direction INPUT))
+           (port CmdLEDGet (direction INPUT))
+           (port Vout3 (direction OUTPUT))
+           (port un9_VOEEN_0_a2_0_a3_0_a3_1z (direction OUTPUT))
+           (port N_263_i_1z (direction OUTPUT))
+           (port N_508 (direction OUTPUT))
+           (port RWSel_2 (direction OUTPUT))
+           (port nC07X_c (direction INPUT))
+           (port RDOE_i_1z (direction OUTPUT))
+           (port LED_c (direction OUTPUT))
+           (port Ready (direction INPUT))
+           (port nDOE_c (direction OUTPUT))
+           (port DOEEN (direction INPUT))
+           (port nEN80_c (direction INPUT))
+           (port N_360_i_1z (direction OUTPUT))
+           (port N_368_i_1z (direction OUTPUT))
+           (port N_507_i_1z (direction OUTPUT))
+           (port un2_S_2_i_0_0_o3_RNIHFHN3_1z (direction OUTPUT))
+           (port CmdLEDGet_3 (direction OUTPUT))
+           (port N_126 (direction OUTPUT))
+           (port N_362_i (direction OUTPUT))
+           (port N_369_i_1z (direction OUTPUT))
+           (port Ready3 (direction OUTPUT))
+           (port CmdSetRWBankFFLED_4 (direction OUTPUT))
+           (port N_361_i (direction OUTPUT))
+           (port N_223 (direction OUTPUT))
+           (port CmdLEDSet (direction INPUT))
+           (port CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_1z (direction OUTPUT))
+           (port CmdRWMaskSet (direction INPUT))
+           (port CmdExecMXO2_3_0_a3_0_RNI6S1P8_1z (direction OUTPUT))
+           (port N_370_i (direction OUTPUT))
+           (port nWE_c (direction INPUT))
+           (port N_358_i (direction OUTPUT))
+           (port un1_CS_0_sqmuxa_i (direction OUTPUT))
+           (port N_547_i (direction OUTPUT))
+           (port C14M_c (direction INPUT))
+           (port CO0_0 (direction INPUT))
+           (port N_187_i_1z (direction OUTPUT))
+           (port N_185_i (direction OUTPUT))
+           (port CKE_7_RNIS77M1_1z (direction OUTPUT))
+           (port N_372_i (direction OUTPUT))
+           (port S_1 (direction INPUT))
+           (port RWSel (direction INPUT))
+           (port N_201_i_1z (direction OUTPUT))
+           (port N_225_i_1z (direction OUTPUT))
+           (port BA_0_sqmuxa (direction OUTPUT))
+           (port CO0_1 (direction INPUT))
+           (port RC12 (direction OUTPUT))
+           (port N_551 (direction OUTPUT))
          )
          (contents
-          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
-          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
-          (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
-          )
-          (instance (rename S_RNII9DO1_2_1 "S_RNII9DO1_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
-          )
-          (instance (rename S_RNII9DO1_0_1 "S_RNII9DO1_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(!B+!A)))"))
-          )
-          (instance (rename wb_dati_7_0_2_RNO_3 "wb_dati_7_0_2_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)))"))
-          )
-          (instance DQML_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance (rename wb_adr_RNO_3_1 "wb_adr_RNO_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B !A))"))
-          )
-          (instance CKE_6_iv_i_0_1_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !A+C (!B !A))"))
-          )
-          (instance (rename FS_RNIOD6E_1_8 "FS_RNIOD6E_1[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B !A)))"))
-          )
-          (instance (rename wb_adr_RNO_2_1 "wb_adr_RNO_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !A+C (!B !A+B A))"))
-          )
-          (instance (rename FS_RNI9FGA_1 "FS_RNI9FGA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+A))"))
-          )
-          (instance (rename S_RNII9DO1_1 "S_RNII9DO1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance wb_rst16_i_i_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D+(C+(B+A)))"))
           )
-          (instance (rename un1_RWMask_0_sqmuxa_1_i_0_RNO_0 "un1_RWMask_0_sqmuxa_1_i_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
+          (instance (rename wb_dati_7_0_0_0_RNO_7 "wb_dati_7_0_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A))+D (B A))"))
           )
-          (instance (rename wb_dati_7_0_0_RNO_7 "wb_dati_7_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
+          (instance nRAS_s_i_0_a3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A))"))
           )
-          (instance wb_we_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A))+D (!B A))"))
+          (instance un1_RC12_i_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
           )
-          (instance wb_reqc_1_RNIRU4M1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B A)))"))
+          (instance (rename wb_dati_7_0_0_a3_3_4 "wb_dati_7_0_0_a3_3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B !A)))"))
           )
-          (instance (rename FS_RNIOD6E_0_8 "FS_RNIOD6E_0[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance (rename RA_42_0_RNO_10 "RA_42_0_RNO[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A))+D (!C (!B A)))"))
-          )
-          (instance (rename FS_RNIOD6E_8 "FS_RNIOD6E[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (!C (B A)+C (B !A)))"))
-          )
-          (instance (rename S_RNII9DO1_3_1 "S_RNII9DO1_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
-          )
-          (instance (rename FS_RNI5OOF1_15 "FS_RNI5OOF1[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename RA_35_2_0_a3_5_10 "RA_35_2_0_a3_5[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C (!B A)))"))
           )
-          (instance (rename BA_0io_RNO_0 "BA_0io_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0 "un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_0_RNO_7 "wb_dati_7_0_0_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance (rename S_s_0_0_RNO_0 "S_s_0_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C !A)"))
+          )
+          (instance CKE_7_m1_0_0_o2_RNI7FOA1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance CKE_7_m1_0_0_o2_RNIGC501 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance (rename RC_3_0_0_1 "RC_3_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A+B !A)+C (B !A))"))
+          )
+          (instance N_314_i_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(!B+!A)))"))
+          )
+          (instance nRAS_s_i_0_a3_5_RNIH7J73 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C (B A)))"))
           )
-          (instance (rename BA_0io_RNO_1 "BA_0io_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename wb_dati_7_0_0_a3_8_3 "wb_dati_7_0_0_a3_8[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance CKE_7_m1_0_0_o2_RNICM8E1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNIP4KI1_1 "S_r_i_0_o2_RNIP4KI1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(!D (!C (B A)))"))
           )
-          (instance nCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B A)+D (C+(!B A)))"))
+          (instance nRAS_s_i_0_a3_5_RNIH7J73_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)))"))
           )
-          (instance wb_we_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B+A)+D (!C (!B+A)+C (!B A)))"))
+          (instance N_225_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B+!A)))"))
           )
-          (instance DOEEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (!C (B A)+C A))"))
+          (instance N_201_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B+!A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNIOGTF1_1 "S_r_i_0_o2_RNIOGTF1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C+(!B+!A)))"))
+          )
+          (instance (rename RA_35_0_0_RNO_0 "RA_35_0_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance (rename RA_35_2_0_RNO_10 "RA_35_2_0_RNO[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNIFNP81_0_2 "S_r_i_0_o2_RNIFNP81_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C A)+D (!C (!B+A)))"))
           )
           (instance wb_req_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D+(C+(B+A)))"))
           )
-          (instance (rename FS_RNIK5632_15 "FS_RNIK5632[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B !A)))"))
+          (instance CmdBitbangMXO2_RNINSM62 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (B+A))+D B)"))
           )
-          (instance DQMH_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C+(!B+!A)))"))
+          (instance wb_we_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (B+A))+D B)"))
           )
-          (instance (rename CmdTout_RNO_2 "CmdTout_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (!B A+B !A)))"))
-          )
-          (instance wb_cyc_stb_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_5_RNIC22J_4 "wb_dati_7_0_a2_5_RNIC22J[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+          (instance (rename wb_dati_7_0_0_a3_13_RNI81UL_7 "wb_dati_7_0_0_a3_13_RNI81UL[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(D (C (B A)))"))
           )
-          (instance nCS_6_u_i_a2_4_RNI3A062 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B A))"))
+          (instance CKE_7_RNIS77M1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B+A)+C A)+D A)"))
           )
-          (instance nCS_6_u_i_a2_4_RNICJKD2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
+          (instance (rename S_r_i_0_o2_RNIBAU51_1 "S_r_i_0_o2_RNIBAU51[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A))"))
           )
-          (instance wb_reqc_1_RNIEO5C1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A))"))
+          (instance N_187_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
           )
-          (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
+          (instance un1_CS_0_sqmuxa_0_0_0 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
+          (instance un1_CS_0_sqmuxa_0_0_0_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !A+C (B+!A))+D !A)"))
           )
-          (instance (rename Vout_0__CN "Vout_0_.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
-          (instance PHI1reg_0io (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nRWE_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nRAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nCS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance nCAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_0 "Vout_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_1 "Vout_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_2 "Vout_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_3 "Vout_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_4 "Vout_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_5 "Vout_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_6 "Vout_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Vout_0io_7 "Vout_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_1 "RA_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_2 "RA_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_4 "RA_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_5 "RA_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_6 "RA_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_7 "RA_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_8 "RA_0io[8]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_9 "RA_0io[9]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_10 "RA_0io[10]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename RA_0io_11 "RA_0io[11]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_0 "Dout_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_1 "Dout_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_2 "Dout_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_3 "Dout_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_4 "Dout_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_5 "Dout_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_6 "Dout_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename Dout_0io_7 "Dout_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance DQML_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance DQMH_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance CKE_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename BA_0io_0 "BA_0io[0]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
-          )
-          (instance (rename BA_0io_1 "BA_0io[1]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
-           (property IOB (string "FALSE"))
+          (instance un1_CS_0_sqmuxa_0_0_0_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+!A))"))
           )
           (instance wb_we (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
@@ -1009,18 +964,6 @@
           )
           (instance (rename wb_adr_7 "wb_adr[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
-          (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename S_2 "S[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance (rename S_3 "S[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
-          )
-          (instance RWSel (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
           (instance (rename RWMask_0 "RWMask[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
           (instance (rename RWMask_1 "RWMask[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
@@ -1037,6 +980,3203 @@
           )
           (instance (rename RWMask_7 "RWMask[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
+          (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdSetRWBankFFChip (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdExecMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance CmdBitbangMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename S_r_i_0_o2_RNIVM0LF_1 "S_r_i_0_o2_RNIVM0LF[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNI3VQTC_1 "S_r_i_0_o2_RNI3VQTC[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B !A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_0 "wb_adr_7_i_i[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A))+D (C A))"))
+          )
+          (instance nRAS_s_i_0_0_RNI0PC64 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance nCAS_s_i_0_a3_RNIO1UQ3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A))+D (!B !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_5 "wb_dati_7_0_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_2 "wb_dati_7_0_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_7 "wb_dati_7_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance CmdExecMXO2_3_0_a3_0_RNI6S1P8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C (B !A)+C !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_6 "wb_dati_7_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_4 "wb_dati_7_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !B)+D (!C (!B !A)+C !B))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C (!B !A)))"))
+          )
+          (instance (rename un1_RWMask_0_sqmuxa_1_i_0_0_0 "un1_RWMask_0_sqmuxa_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B A)+D (C+(!B A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_0 "wb_dati_7_0_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_1 "wb_dati_7_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C A+C (B+A)))"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A+B !A)+C B)+D (!C (B !A)+C B))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_3 "wb_dati_7_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C A+C (B+A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_4_0 "wb_adr_7_i_i_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_5_0 "wb_adr_7_i_i_5[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D C+D (C+(B !A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+!A)+C (B A))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C (!B !A)))"))
+          )
+          (instance (rename un1_LEDEN_0_sqmuxa_1_i_0_0_0 "un1_LEDEN_0_sqmuxa_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B A)+D (C+(!B A)))"))
+          )
+          (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B !A))+D (C+!A))"))
+          )
+          (instance (rename wb_dati_7_0_0_RNO_0_7 "wb_dati_7_0_0_RNO_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C (B A)+C B))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_a3_7 "wb_dati_7_0_0_0_a3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B !A+B A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_a3_6_0 "wb_adr_7_i_i_a3_6[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
+          )
+          (instance (rename RA_35_0_0_0_7 "RA_35_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance (rename RA_35_0_0_0_6 "RA_35_0_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance (rename RA_35_0_0_4 "RA_35_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance (rename RA_35_0_0_3 "RA_35_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_2_4 "wb_dati_7_0_0_a3_2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B !A)))"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C A)+D (!C (!B A)+C A))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_0_3 "wb_dati_7_0_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_6 "wb_dati_7_0_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_4 "wb_dati_7_0_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
+          )
+          (instance CKE_7_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A))"))
+          )
+          (instance CKE_7 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
+          (instance wb_cyc_stb_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C A+C (B+A))"))
+          )
+          (instance CmdExecMXO2_3_0_a3_0_RNIPG3P2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C (!B A)))"))
+          )
+          (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)+C B)+D B)"))
+          )
+          (instance nRAS_s_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A))+D !A)"))
+          )
+          (instance nCAS_s_i_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)+C !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_4 "wb_dati_7_0_0_a3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B !A))"))
+          )
+          (instance (rename RA_35_i_i_0_1 "RA_35_i_i_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B A)))"))
+          )
+          (instance (rename RA_35_0_0_2 "RA_35_0_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance (rename RA_35_0_0_5 "RA_35_0_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B A)))"))
+          )
+          (instance (rename RA_35_2_0_10 "RA_35_2_0[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance wb_we_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C (B !A)))"))
+          )
+          (instance (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(!C B+C (B+A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B !A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)))"))
+          )
+          (instance (rename RA_35_0_0_0_4 "RA_35_0_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
+          )
+          (instance (rename RA_35_0_0_0_0_6 "RA_35_0_0_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
+          )
+          (instance (rename RA_35_0_0_0_0_7 "RA_35_0_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
+          )
+          (instance (rename RA_35_0_0_0_3 "RA_35_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_1 "wb_dati_7_0_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_0_7 "wb_dati_7_0_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_1_0 "wb_adr_7_i_i_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A))+D C)"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C+(B A))+D (!C+(!B+A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNIFNP81_2 "S_r_i_0_o2_RNIFNP81[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C (B !A))+D (!C (!B !A)+C !A))"))
+          )
+          (instance (rename RA_35_0_0_a3_5 "RA_35_0_0_a3[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RA_35_i_i_0_a3_0_1 "RA_35_i_i_0_a3_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RA_35_0_0_a3_0_2 "RA_35_0_0_a3_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance wb_cyc_stb_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)+C !B))"))
+          )
+          (instance (rename RA_35_0_0_11 "RA_35_0_0[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C A)+D (!C (!B !A)+C (!B+A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
+          )
+          (instance CmdExecMXO2_3_0_a3_0_RNIAJ811 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)))"))
+          )
+          (instance CKE_7s2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
+          )
+          (instance (rename wb_adr_7_i_i_a3_4_0 "wb_adr_7_i_i_a3_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance (rename RA_35_0_0_9 "RA_35_0_0[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B A))"))
+          )
+          (instance CmdBitbangMXO2_3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance CmdSetRWBankFFLED_4_0_a8_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B !A)))"))
+          )
+          (instance Ready3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance (rename wb_adr_RNO_1_1 "wb_adr_RNO_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A))+D (C (!B+!A)))"))
+          )
+          (instance wb_we_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C (B !A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_a3_0_3 "wb_dati_7_0_0_0_a3_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance nCAS_s_i_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance SUM0_i_o2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(!B+!A))"))
+          )
+          (instance N_285_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A))"))
+          )
+          (instance N_369_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)+C (!B+!A)))"))
+          )
+          (instance (rename S_r_i_0_o2_0_RNI36E21_1 "S_r_i_0_o2_0_RNI36E21[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C !A+C (B !A)))"))
+          )
+          (instance (rename RA_35_2_0_a3_10 "RA_35_2_0_a3[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !A)+D (C (B+!A)))"))
+          )
+          (instance (rename RA_35_i_i_0_a3_1 "RA_35_i_i_0_a3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)+C (B+!A)))"))
+          )
+          (instance (rename RA_35_0_0_a3_2 "RA_35_0_0_a3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)+C (B+!A)))"))
+          )
+          (instance CmdExecMXO2_3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_9_7 "wb_dati_7_0_0_a3_9[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance CmdRWMaskSet_3_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_o2_4 "wb_dati_7_0_0_o2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B A))+D (!C (B A)+C (!B+!A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_o2_0_3 "wb_dati_7_0_0_o2_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B !A)+C (B A))+D (C (!B+!A)))"))
+          )
+          (instance CKE_7s2_0_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C !A)+D (!C B+C !A))"))
+          )
+          (instance (rename BA_4_1 "BA_4[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B+!A))+D (C B))"))
+          )
+          (instance (rename BA_4_0 "BA_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B+!A))+D (C B))"))
+          )
+          (instance wb_we_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B+!A))+D (!C+(!B+!A)))"))
+          )
+          (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A)+C !B)"))
+          )
+          (instance wb_req_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C+(!B+!A)))"))
+          )
+          (instance un1_CKE75_0_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B+A)+C (!B !A+B A))+D (!C (!B+!A)+C (B+!A)))"))
+          )
+          (instance nRAS_s_i_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B !A)))"))
+          )
+          (instance (rename S_s_0_0_0 "S_s_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+A)+D (C+(!B+A)))"))
+          )
+          (instance CmdLEDGet_3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance (rename RA_35_0_0_o2_0_5 "RA_35_0_0_o2_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)+C (!B !A))+D (!C !A+C (!B !A)))"))
+          )
+          (instance un2_S_2_i_0_0_o3_RNIHFHN3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+          )
+          (instance (rename RA_35_0_0_0_9 "RA_35_0_0_0[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B !A)+D (C+(B !A)))"))
+          )
+          (instance wb_we_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D C+D (C+(B !A)))"))
+          )
+          (instance (rename RA_35_2_0_0_10 "RA_35_2_0_0[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C A+C (B+A))"))
+          )
+          (instance (rename RA_35_0_0_0_5 "RA_35_0_0_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C !B+C (!B+!A)))"))
+          )
+          (instance (rename un1_RWMask_0_sqmuxa_1_i_0_a3_0_0_0 "un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance SUM0_i_m3_0_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
+          )
+          (instance SUM0_i_m3_0 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT)))          )
+          (instance N_507_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C !A)+D (!C (B+!A)+C B))"))
+          )
+          (instance N_368_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A+B !A))"))
+          )
+          (instance N_360_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !A+C (!B !A))"))
+          )
+          (instance (rename RA_35_2_0_a3_0_10 "RA_35_2_0_a3_0[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (B !A)+D (!C (B !A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_9 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename RWBank_3_0_0_0 "RWBank_3_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_0_4 "RWBank_3_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_1 "RWBank_3_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_2 "RWBank_3_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_3 "RWBank_3_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_5 "RWBank_3_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_6 "RWBank_3_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+A)+C B)"))
+          )
+          (instance (rename RWBank_3_0_7 "RWBank_3_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C B+C (B+A))"))
+          )
+          (instance (rename RA_35_0_0_o2_5 "RA_35_0_0_o2[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B A)+C (B+A))+D (!C A+C (B+A)))"))
+          )
+          (instance (rename RA_35_0_0_o2_11 "RA_35_0_0_o2[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+(B A))+D (C+B))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_o2_1_0 "wb_adr_7_i_i_o2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B+!A))+D (!C+(!B+!A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_o2_3 "wb_dati_7_0_0_0_o2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B A))+D (!C (!B !A)+C (!B !A+B A)))"))
+          )
+          (instance (rename RC_3_0_0_2 "RC_3_0_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C !B)"))
+          )
+          (instance un1_nDOE_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(B+!A))"))
+          )
+          (instance LEDEN_RNI6G6M (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(!B+!A))"))
+          )
+          (instance RDOE_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C A)"))
+          )
+          (instance nRAS_s_i_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance (rename RA_35_2_0_a3_3_10 "RA_35_2_0_a3_3[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance SUM0_i_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C !A+C (!B !A)))"))
+          )
+          (instance (rename wb_adr_RNO_0_1 "wb_adr_RNO_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance RWSel_2_0_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)))"))
+          )
+          (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_o3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance nRAS_s_i_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(!B A+B !A)))"))
+          )
+          (instance CmdLEDGet_3_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B !A))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance CKE_7s2_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C B+C (B !A))+D (!C B))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_0_0_1 "wb_dati_7_0_0_a3_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_1_0_6 "wb_dati_7_0_0_a3_1_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C (!B A)))"))
+          )
+          (instance (rename RWMask_RNO_0 "RWMask_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_1 "RWMask_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_2 "RWMask_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_3 "RWMask_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_4 "RWMask_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_5 "RWMask_RNO[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance (rename RWMask_RNO_6 "RWMask_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
+          )
+          (instance nCAS_s_i_0_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+A)+D (!C (!B+!A)+C !B))"))
+          )
+          (instance (rename wb_adr_RNO_2 "wb_adr_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename wb_adr_RNO_3 "wb_adr_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename wb_adr_RNO_7 "wb_adr_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance DQMH_4_iv_0_0_i_i_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+!A)+D (!C (!B !A)+C !B))"))
+          )
+          (instance nRAS_s_i_0_a3_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B A))"))
+          )
+          (instance nRAS_s_i_0_a3_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (!B !A))"))
+          )
+          (instance (rename wb_adr_RNO_3_1 "wb_adr_RNO_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+!A))"))
+          )
+          (instance SUM1_0_o3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(B+A))"))
+          )
+          (instance (rename wb_adr_RNO_2_1 "wb_adr_RNO_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+!A)+C (B A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_15_7 "wb_dati_7_0_0_a3_15[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B !A))"))
+          )
+          (instance nRAS_s_i_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+!A)+C !A)"))
+          )
+          (instance CKE_7s2_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance N_263_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance RA_35_2_30_a3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance un9_VOEEN_0_a2_0_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (!B A)))"))
+          )
+          (instance Vout3_0_a3_0_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B !A)))"))
+          )
+          (instance (rename RWBank_3_0_0_o3_0 "RWBank_3_0_0_o3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_a3_5_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B !A))"))
+          )
+          (instance wb_reqc_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+A)))"))
+          )
+          (instance (rename wb_adr_RNO_4_1 "wb_adr_RNO_4[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A))"))
+          )
+          (instance Ready3_0_a3_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance Ready3_0_a3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance Ready3_0_a3_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_a3_2_0_0 "wb_adr_7_i_i_a3_2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B A))"))
+          )
+          (instance (rename wb_dati_7_0_0_0_a3_0_0 "wb_dati_7_0_0_0_a3_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B A))+D (C (!B A)))"))
+          )
+          (instance (rename wb_adr_RNO_6 "wb_adr_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !B+C A)"))
+          )
+          (instance (rename wb_adr_RNO_5 "wb_adr_RNO[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !B+C A)"))
+          )
+          (instance (rename wb_adr_RNO_4 "wb_adr_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !B+C A)"))
+          )
+          (instance LEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C (!B+A))"))
+          )
+          (instance (rename RWMask_RNO_7 "RWMask_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A)+C (!B+A))"))
+          )
+          (instance nRAS_s_i_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (!B+A)+C (B A))"))
+          )
+          (instance wb_we_7_iv_0_0_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_i_a3_4 "RDout_i_i_a3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_7 "RDout_i_0_i_a3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_6 "RDout_i_0_i_a3[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_5 "RDout_i_0_i_a3[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_2 "RDout_i_0_i_a3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_1 "RDout_i_0_i_a3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename RDout_i_0_i_a3_0 "RDout_i_0_i_a3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B A)"))
+          )
+          (instance (rename CmdTout_3_0_a3_0_a3_0 "CmdTout_3_0_a3_0_a3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance wb_rst8_0_a3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance wb_we_7_iv_0_0_0_a3_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance (rename S_r_i_0_o2_1 "S_r_i_0_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance SUM0_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance (rename S_r_i_0_o2_2 "S_r_i_0_o2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance un1_CS_0_sqmuxa_0_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+A)"))
+          )
+          (instance (rename S_r_i_0_o2_0_1 "S_r_i_0_o2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+!A)"))
+          )
+          (instance (rename wb_dati_7_0_0_o2_0_7 "wb_dati_7_0_0_o2_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+!A)"))
+          )
+          (instance (rename wb_dati_7_0_0_0_o2_7 "wb_dati_7_0_0_0_o2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+A)"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_13_7 "wb_dati_7_0_0_a3_13[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B A)"))
+          )
+          (instance un2_S_2_i_0_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance CKE_7_m1_0_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance (rename RC_3_0_0_a3_1_1 "RC_3_0_0_a3_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B !A)"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_4_1_0_7 "wb_dati_7_0_0_a3_4_1_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B !A)"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D+(C+(B+!A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_2_3 "wb_dati_7_0_0_a3_2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B A))"))
+          )
+          (instance (rename wb_dati_7_0_0_o3_0_2 "wb_dati_7_0_0_o3_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D B+D (!C B+C (B+A)))"))
+          )
+          (instance CKE_7_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B+!A)+C !A)"))
+          )
+          (instance nRWE_s_i_0_63_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C+B)+D (!C+(B !A)))"))
+          )
+          (instance (rename S_r_i_0_o2_RNI62C53_1 "S_r_i_0_o2_RNI62C53[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_3_1_0 "wb_adr_7_i_i_3_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B !A)+C A)+D (!C (!B !A)))"))
+          )
+          (instance (rename wb_adr_7_i_i_3_0 "wb_adr_7_i_i_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B !A+B A)))"))
+          )
+          (instance (rename RA_35_0_0_1_0 "RA_35_0_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B+!A)+D (!C (!B+!A)))"))
+          )
+          (instance (rename RA_35_0_0_0 "RA_35_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D+(!C B+C (B+A)))"))
+          )
+          (instance CmdSetRWBankFFChip_3_0_a8_0_a3_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (!C (B A)))"))
+          )
+          (instance wb_we_7_iv_0_0_0_a3_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (B A)))"))
+          )
+          (instance CmdExecMXO2_3_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance CmdBitbangMXO2_3_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B !A)))"))
+          )
+          (instance SUM0_i_m3_0_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C+(!B+A))"))
+          )
+          (instance CmdBitbangMXO2_3_0_a3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(D (C (!B A)))"))
+          )
+          (instance CmdLEDSet_3_0_a8_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (B A)))"))
+          )
+          (instance CmdRWMaskSet_3_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A)))"))
+          )
+          (instance CmdLEDGet_3_0_a3_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B A))"))
+          )
+          (instance nRAS_s_i_0_a3_8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (B !A)))"))
+          )
+          (instance nRAS_s_i_0_a3_0_RNIIR094 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!B !A)+D (!C (!B !A)))"))
+          )
+          (instance (rename un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0 "un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (!C (!B A)))"))
+          )
+          (instance SUM2_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C+(!B+!A))"))
+          )
+          (instance (rename RA_35_0_0_a3_4_7 "RA_35_0_0_a3_4[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(C (B !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_7_3 "wb_dati_7_0_0_a3_7[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_12_7 "wb_dati_7_0_0_a3_12[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C (B !A))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_14_7 "wb_dati_7_0_0_a3_14[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A)))"))
+          )
+          (instance (rename wb_dati_7_0_0_a3_10_7 "wb_dati_7_0_0_a3_10[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!D (C (!B A)))"))
+          )
+          (instance ufmefb (viewRef netlist (cellRef REFB))
+          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (net (rename S_0 "S[0]") (joined
+           (portRef (member s 3))
+           (portRef B (instanceRef un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0))
+           (portRef A (instanceRef S_r_i_0_o2_2))
+           (portRef A (instanceRef S_r_i_0_o2_1))
+           (portRef B (instanceRef wb_reqc_1_0))
+           (portRef A (instanceRef Vout3_0_a3_0_a3_0_a3))
+           (portRef A (instanceRef un9_VOEEN_0_a2_0_a3_0_a3))
+           (portRef B (instanceRef RA_35_2_30_a3_2))
+           (portRef B (instanceRef nRAS_s_i_0_a3_6))
+           (portRef C (instanceRef DQMH_4_iv_0_0_i_i_a3_0_a3))
+           (portRef B (instanceRef CKE_7s2_0_0_0))
+           (portRef B (instanceRef RA_35_2_0_a3_3_10))
+           (portRef A (instanceRef RA_35_0_0_o2_11))
+           (portRef A (instanceRef RA_35_0_0_o2_5))
+           (portRef C (instanceRef N_507_i))
+           (portRef A (instanceRef RA_35_0_0_o2_0_5))
+           (portRef A (instanceRef un1_CKE75_0_i_0))
+           (portRef D (instanceRef BA_4_0))
+           (portRef D (instanceRef BA_4_1))
+           (portRef D (instanceRef nCAS_s_i_0_a3))
+           (portRef B (instanceRef CKE_7_RNIS77M1))
+           (portRef B (instanceRef wb_req_RNO_0))
+           (portRef C (instanceRef RA_35_2_0_RNO_10))
+           (portRef B (instanceRef N_201_i))
+           (portRef B (instanceRef N_225_i))
+           (portRef D (instanceRef nRAS_s_i_0_a3_5_RNIH7J73_0))
+           (portRef B (instanceRef CKE_7_m1_0_0_o2_RNICM8E1))
+           (portRef C (instanceRef nRAS_s_i_0_a3_5_RNIH7J73))
+           (portRef D (instanceRef N_314_i_i_o3))
+           (portRef B (instanceRef CKE_7_m1_0_0_o2_RNIGC501))
+           (portRef A (instanceRef CKE_7_m1_0_0_o2_RNI7FOA1))
+           (portRef A (instanceRef S_s_0_0_RNO_0))
+           (portRef D (instanceRef RA_35_2_0_a3_5_10))
+           (portRef A (instanceRef nRAS_s_i_0_a3_4))
+           (portRef A (instanceRef wb_rst16_i_i_i_o3))
+          ))
+          (net (rename SZ0Z_1 "S[1]") (joined
+           (portRef (member s 2))
+           (portRef C (instanceRef un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0))
+           (portRef A (instanceRef un2_S_2_i_0_0_o3))
+           (portRef B (instanceRef S_r_i_0_o2_2))
+           (portRef B (instanceRef S_r_i_0_o2_1))
+           (portRef C (instanceRef wb_reqc_1_0))
+           (portRef B (instanceRef Vout3_0_a3_0_a3_0_a3))
+           (portRef B (instanceRef un9_VOEEN_0_a2_0_a3_0_a3))
+           (portRef A (instanceRef CKE_7s2_0_0_a2_1))
+           (portRef C (instanceRef nRAS_s_i_0_a3_6))
+           (portRef D (instanceRef nRAS_s_i_0_o2_0))
+           (portRef C (instanceRef RA_35_2_0_a3_3_10))
+           (portRef B (instanceRef RA_35_0_0_o2_11))
+           (portRef B (instanceRef RA_35_0_0_o2_5))
+           (portRef B (instanceRef RA_35_0_0_o2_0_5))
+           (portRef D (instanceRef S_s_0_0_0))
+           (portRef B (instanceRef un1_CKE75_0_i_0))
+           (portRef C (instanceRef CKE_7s2_0_0_o3))
+           (portRef B (instanceRef CKE_7_am))
+           (portRef C (instanceRef CKE_7_RNIS77M1))
+           (portRef C (instanceRef wb_req_RNO_0))
+           (portRef D (instanceRef N_201_i))
+           (portRef D (instanceRef N_225_i))
+           (portRef C (instanceRef nRAS_s_i_0_a3_5_RNIH7J73_0))
+           (portRef C (instanceRef CKE_7_m1_0_0_o2_RNICM8E1))
+           (portRef B (instanceRef nRAS_s_i_0_a3_5_RNIH7J73))
+           (portRef C (instanceRef N_314_i_i_o3))
+           (portRef B (instanceRef CKE_7_m1_0_0_o2_RNI7FOA1))
+           (portRef B (instanceRef S_s_0_0_RNO_0))
+           (portRef C (instanceRef RA_35_2_0_a3_5_10))
+           (portRef A (instanceRef un1_RC12_i_0_o3))
+           (portRef B (instanceRef wb_rst16_i_i_i_o3))
+          ))
+          (net (rename S_3 "S[3]") (joined
+           (portRef (member s 0))
+           (portRef C (instanceRef S_r_i_0_o2_RNI62C53_1))
+           (portRef B (instanceRef CKE_7_m1_0_0_o2))
+           (portRef B (instanceRef S_r_i_0_o2_0_1))
+           (portRef B (instanceRef RWMask_RNO_7))
+           (portRef B (instanceRef LEDEN_RNO))
+           (portRef D (instanceRef wb_reqc_1_0))
+           (portRef D (instanceRef Vout3_0_a3_0_a3_0_a3))
+           (portRef D (instanceRef un9_VOEEN_0_a2_0_a3_0_a3))
+           (portRef D (instanceRef RA_35_2_30_a3_2))
+           (portRef C (instanceRef CKE_7s2_0_0_a2_1))
+           (portRef A (instanceRef nRAS_s_i_0_o2))
+           (portRef B (instanceRef nRAS_s_i_0_a3_5))
+           (portRef D (instanceRef DQMH_4_iv_0_0_i_i_a3_0_a3))
+           (portRef B (instanceRef RWMask_RNO_6))
+           (portRef B (instanceRef RWMask_RNO_5))
+           (portRef B (instanceRef RWMask_RNO_4))
+           (portRef B (instanceRef RWMask_RNO_3))
+           (portRef B (instanceRef RWMask_RNO_2))
+           (portRef B (instanceRef RWMask_RNO_1))
+           (portRef B (instanceRef RWMask_RNO_0))
+           (portRef C (instanceRef CKE_7s2_0_0_0))
+           (portRef D (instanceRef RA_35_0_0_o2_11))
+           (portRef D (instanceRef RA_35_0_0_o2_5))
+           (portRef C (instanceRef RA_35_2_0_a3_0_10))
+           (portRef D (instanceRef N_507_i))
+           (portRef D (instanceRef RA_35_0_0_o2_0_5))
+           (portRef D (instanceRef un1_CKE75_0_i_0))
+           (portRef D (instanceRef S_r_i_0_o2_RNIFNP81_2))
+           (portRef B (instanceRef wb_cyc_stb_RNO))
+           (portRef A (instanceRef S_r_i_0_o2_RNIBAU51_1))
+           (portRef A (instanceRef S_r_i_0_o2_RNIFNP81_0_2))
+           (portRef B (instanceRef S_r_i_0_o2_RNIOGTF1_1))
+           (portRef A (instanceRef N_201_i))
+           (portRef A (instanceRef N_225_i))
+           (portRef B (instanceRef S_r_i_0_o2_RNIP4KI1_1))
+           (portRef A (instanceRef N_314_i_i_o3))
+           (portRef A (instanceRef RA_35_2_0_a3_5_10))
+           (portRef B (instanceRef un1_RC12_i_0_o3))
+           (portRef B (instanceRef nRAS_s_i_0_a3_4))
+           (portRef C (instanceRef wb_rst16_i_i_i_o3))
+          ))
+          (net (rename S_2 "S[2]") (joined
+           (portRef (member s 1))
+           (portRef A (instanceRef CKE_7_m1_0_0_o2))
+           (portRef B (instanceRef un2_S_2_i_0_0_o3))
+           (portRef A (instanceRef S_r_i_0_o2_0_1))
+           (portRef B (instanceRef wb_we_7_iv_0_0_0_a3_6))
+           (portRef B (instanceRef wb_we_7_iv_0_0_0_a3_1))
+           (portRef C (instanceRef wb_adr_RNO_4))
+           (portRef C (instanceRef wb_adr_RNO_5))
+           (portRef C (instanceRef wb_adr_RNO_6))
+           (portRef C (instanceRef Vout3_0_a3_0_a3_0_a3))
+           (portRef C (instanceRef un9_VOEEN_0_a2_0_a3_0_a3))
+           (portRef C (instanceRef RA_35_2_30_a3_2))
+           (portRef B (instanceRef CKE_7s2_0_0_a2_1))
+           (portRef A (instanceRef nRAS_s_i_0_a3_5))
+           (portRef B (instanceRef wb_adr_RNO_7))
+           (portRef B (instanceRef wb_adr_RNO_3))
+           (portRef B (instanceRef wb_adr_RNO_2))
+           (portRef B (instanceRef nRAS_s_i_0_a3_1))
+           (portRef C (instanceRef RA_35_0_0_o2_11))
+           (portRef C (instanceRef RA_35_0_0_o2_5))
+           (portRef B (instanceRef RA_35_2_0_a3_0_10))
+           (portRef C (instanceRef RA_35_0_0_o2_0_5))
+           (portRef D (instanceRef nRAS_s_i_0_a3_0))
+           (portRef C (instanceRef un1_CKE75_0_i_0))
+           (portRef D (instanceRef RA_35_2_0_a3_10))
+           (portRef C (instanceRef S_r_i_0_o2_RNIFNP81_2))
+           (portRef B (instanceRef wb_dati_7_0_0_0_0_7))
+           (portRef B (instanceRef wb_dati_7_0_0_0_1))
+           (portRef C (instanceRef wb_adr_RNO_1))
+           (portRef C (instanceRef wb_dati_7_0_0_0_4))
+           (portRef B (instanceRef wb_dati_7_0_0_0_6))
+           (portRef B (instanceRef wb_dati_7_0_0_0_0_3))
+           (portRef B (instanceRef wb_dati_7_0_0_0_0))
+           (portRef B (instanceRef wb_dati_7_0_0_2))
+           (portRef B (instanceRef wb_dati_7_0_0_5))
+           (portRef CD (instanceRef wb_req))
+           (portRef B (instanceRef S_r_i_0_o2_RNIBAU51_1))
+           (portRef D (instanceRef S_r_i_0_o2_RNIFNP81_0_2))
+           (portRef C (instanceRef S_r_i_0_o2_RNIOGTF1_1))
+           (portRef C (instanceRef N_201_i))
+           (portRef C (instanceRef N_225_i))
+           (portRef C (instanceRef S_r_i_0_o2_RNIP4KI1_1))
+           (portRef B (instanceRef N_314_i_i_o3))
+           (portRef B (instanceRef RA_35_2_0_a3_5_10))
+           (portRef C (instanceRef un1_RC12_i_0_o3))
+           (portRef C (instanceRef nRAS_s_i_0_a3_4))
+           (portRef D (instanceRef wb_rst16_i_i_i_o3))
+          ))
+          (net wb_rst16_i (joined
+           (portRef Z (instanceRef wb_rst16_i_i_i_o3))
+           (portRef C (instanceRef N_285_i))
+           (portRef C (instanceRef nCAS_s_i_0_a3_0))
+           (portRef CD (instanceRef wb_rst))
+          ))
+          (net N_876 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_15_7))
+           (portRef C (instanceRef wb_dati_7_0_0_RNO_0_7))
+           (portRef B (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0))
+           (portRef A (instanceRef wb_dati_7_0_0_0_RNO_7))
+          ))
+          (net N_807 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_12_7))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_2_3))
+           (portRef C (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_0))
+           (portRef B (instanceRef wb_dati_7_0_0_0_RNO_7))
+          ))
+          (net (rename FS_13 "FS[13]") (joined
+           (portRef (member fs 2))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_10_7))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_7_3))
+           (portRef B (instanceRef wb_dati_7_0_0_0_o2_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_a3_0_0))
+           (portRef D (instanceRef Ready3_0_a3_5))
+           (portRef C (instanceRef wb_adr_RNO_4_1))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_0_0_1))
+           (portRef B (instanceRef wb_dati_7_0_0_0_o2_3))
+           (portRef D (instanceRef wb_adr_7_i_i_o2_1_0))
+           (portRef C (instanceRef wb_req_RNO))
+           (portRef A (instanceRef wb_we_RNO))
+           (portRef A (instanceRef RA_35_0_0_0_6))
+           (portRef B (instanceRef wb_dati_7_0_0_0_a3_7))
+           (portRef B (instanceRef wb_adr_7_i_i_5_0))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_13_RNI81UL_7))
+           (portRef C (instanceRef wb_dati_7_0_0_0_0_RNO_7))
+           (portRef C (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0))
+           (portRef C (instanceRef wb_dati_7_0_0_0_RNO_7))
+          ))
+          (net (rename FS_12 "FS[12]") (joined
+           (portRef (member fs 3))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_10_7))
+           (portRef D (instanceRef wb_adr_7_i_i_3_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_2_3))
+           (portRef A (instanceRef wb_dati_7_0_0_0_o2_7))
+           (portRef C (instanceRef wb_dati_7_0_0_0_a3_0_0))
+           (portRef C (instanceRef Ready3_0_a3_5))
+           (portRef B (instanceRef wb_adr_RNO_4_1))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_1_0_6))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_0_0_1))
+           (portRef B (instanceRef wb_adr_RNO_0_1))
+           (portRef C (instanceRef RA_35_0_0_0_5))
+           (portRef B (instanceRef wb_req_RNO))
+           (portRef D (instanceRef wb_we_RNO_1))
+           (portRef A (instanceRef wb_dati_7_0_0_0_a3_0_3))
+           (portRef A (instanceRef wb_we_RNO_2))
+           (portRef C (instanceRef wb_adr_7_i_i_a3_4_0))
+           (portRef A (instanceRef wb_adr_7_i_i_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_4))
+           (portRef A (instanceRef wb_dati_7_0_0_0_a3_7))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_13_RNI81UL_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_0_RNO_7))
+           (portRef D (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0))
+           (portRef D (instanceRef wb_dati_7_0_0_0_RNO_7))
+          ))
+          (net N_604 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_RNO_7))
+           (portRef B (instanceRef wb_dati_7_0_0_0_7))
+          ))
+          (net N_784 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_4))
+           (portRef B (instanceRef RA_35_0_0_a3_4_7))
+           (portRef D (instanceRef RA_35_0_0_0_5))
+           (portRef B (instanceRef RA_35_0_0_0_9))
+           (portRef C (instanceRef nRAS_s_i_0_0))
+           (portRef C (instanceRef RA_35_0_0_RNO_0))
+          ))
+          (net N_560 (joined
+           (portRef Z (instanceRef un1_RC12_i_0_o3))
+           (portRef B (instanceRef BA_4_0))
+           (portRef B (instanceRef BA_4_1))
+          ))
+          (net (rename FS_11 "FS[11]") (joined
+           (portRef (member fs 4))
+           (portRef B (instanceRef wb_we_7_iv_0_0_0_a3_7))
+           (portRef C (instanceRef wb_adr_7_i_i_3_1_0))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_4_1_0_7))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_13_7))
+           (portRef B (instanceRef wb_dati_7_0_0_0_a3_0_0))
+           (portRef C (instanceRef wb_adr_7_i_i_a3_2_0_0))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_15_7))
+           (portRef C (instanceRef wb_adr_RNO_3_1))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_1_0_6))
+           (portRef A (instanceRef wb_adr_RNO_0_1))
+           (portRef C (instanceRef wb_adr_7_i_i_o2_1_0))
+           (portRef A (instanceRef wb_we_RNO_3))
+           (portRef A (instanceRef wb_req_RNO))
+           (portRef D (instanceRef wb_dati_7_0_0_o2_0_3))
+           (portRef D (instanceRef wb_dati_7_0_0_o2_4))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_2_4))
+           (portRef A (instanceRef RA_35_0_0_4))
+           (portRef B (instanceRef wb_adr_7_i_i_a3_6_0))
+           (portRef A (instanceRef wb_adr_7_i_i_5_0))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_8_3))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_3_4))
+          ))
+          (net (rename FS_10 "FS[10]") (joined
+           (portRef (member fs 5))
+           (portRef A (instanceRef wb_we_7_iv_0_0_0_a3_7))
+           (portRef B (instanceRef wb_adr_7_i_i_3_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_4_1_0_7))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_13_7))
+           (portRef A (instanceRef wb_dati_7_0_0_0_a3_0_0))
+           (portRef B (instanceRef wb_adr_7_i_i_a3_2_0_0))
+           (portRef A (instanceRef wb_adr_RNO_4_1))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_15_7))
+           (portRef C (instanceRef wb_adr_RNO_2_1))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_1_0_6))
+           (portRef C (instanceRef wb_we_RNO_1))
+           (portRef C (instanceRef wb_dati_7_0_0_o2_0_3))
+           (portRef C (instanceRef wb_dati_7_0_0_o2_4))
+           (portRef B (instanceRef wb_adr_7_i_i_a3_4_0))
+           (portRef A (instanceRef RA_35_0_0_3))
+           (portRef A (instanceRef wb_adr_7_i_i_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_8_3))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_3_4))
+          ))
+          (net (rename FS_9 "FS[9]") (joined
+           (portRef (member fs 6))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_14_7))
+           (portRef C (instanceRef wb_we_7_iv_0_0_0_a3_7))
+           (portRef B (instanceRef wb_adr_7_i_i_3_0))
+           (portRef B (instanceRef wb_dati_7_0_0_o2_0_7))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_15_7))
+           (portRef B (instanceRef wb_adr_RNO_2_1))
+           (portRef B (instanceRef wb_adr_RNO_3_1))
+           (portRef A (instanceRef wb_dati_7_0_0_0_o2_3))
+           (portRef B (instanceRef wb_adr_7_i_i_o2_1_0))
+           (portRef B (instanceRef wb_we_RNO_1))
+           (portRef B (instanceRef wb_dati_7_0_0_o2_0_3))
+           (portRef B (instanceRef wb_dati_7_0_0_o2_4))
+           (portRef C (instanceRef RA_35_0_0_a3_2))
+           (portRef A (instanceRef wb_adr_7_i_i_a3_4_0))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_2_4))
+           (portRef A (instanceRef wb_adr_7_i_i_a3_6_0))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_8_3))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_3_4))
+          ))
+          (net (rename FS_8 "FS[8]") (joined
+           (portRef (member fs 7))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_14_7))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_12_7))
+           (portRef D (instanceRef wb_we_7_iv_0_0_0_a3_7))
+           (portRef A (instanceRef wb_adr_7_i_i_3_0))
+           (portRef A (instanceRef wb_adr_7_i_i_3_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_o2_0_7))
+           (portRef A (instanceRef wb_adr_7_i_i_a3_2_0_0))
+           (portRef A (instanceRef wb_adr_RNO_2_1))
+           (portRef A (instanceRef wb_adr_RNO_3_1))
+           (portRef A (instanceRef wb_adr_7_i_i_o2_1_0))
+           (portRef A (instanceRef wb_we_RNO_1))
+           (portRef A (instanceRef wb_dati_7_0_0_o2_0_3))
+           (portRef A (instanceRef wb_dati_7_0_0_o2_4))
+           (portRef C (instanceRef RA_35_i_i_0_a3_1))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_2_4))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_8_3))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_3_4))
+          ))
+          (net N_873 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_3_4))
+           (portRef D (instanceRef wb_dati_7_0_0_o3_0_2))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_0_0_1))
+           (portRef B (instanceRef wb_dati_7_0_0_0_4))
+          ))
+          (net N_845 (joined
+           (portRef Z (instanceRef RA_35_2_0_a3_5_10))
+           (portRef B (instanceRef RA_35_2_0_0_10))
+           (portRef C (instanceRef RA_35_0_0_0_9))
+           (portRef B (instanceRef RA_35_0_0_11))
+          ))
+          (net wb_ack (joined
+           (portRef wb_ack (instanceRef ufmefb))
+           (portRef B (instanceRef un1_RWMask_0_sqmuxa_1_i_0_a3_0_0_0))
+           (portRef D (instanceRef wb_cyc_stb_RNO_0))
+           (portRef D (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0_0))
+           (portRef D (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0))
+           (portRef A (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0))
+          ))
+          (net (rename un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1_0 "un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0]") (joined
+           (portRef Z (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0))
+           (portRef D (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_0))
+          ))
+          (net N_206 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_o2_0_7))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_1_0_6))
+           (portRef A (instanceRef wb_dati_7_0_0_RNO_0_7))
+           (portRef A (instanceRef wb_dati_7_0_0_0_0_RNO_7))
+          ))
+          (net N_811 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_13_7))
+           (portRef C (instanceRef wb_dati_7_0_0_0_o2_3))
+           (portRef C (instanceRef wb_dati_7_0_0_0_a3_7))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_13_RNI81UL_7))
+           (portRef B (instanceRef wb_dati_7_0_0_0_0_RNO_7))
+          ))
+          (net (rename wb_dati_7_0_0_a3_8_0_7 "wb_dati_7_0_0_a3_8_0[7]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_0_RNO_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_0_7))
+          ))
+          (net N_551 (joined
+           (portRef Z (instanceRef CKE_7_m1_0_0_o2))
+           (portRef D (instanceRef un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0))
+           (portRef A (instanceRef CKE_7s2_0_0_o3))
+           (portRef D (instanceRef CKE_7_RNIS77M1))
+           (portRef D (instanceRef wb_req_RNO_0))
+           (portRef D (instanceRef RA_35_2_0_RNO_10))
+           (portRef D (instanceRef CKE_7_m1_0_0_o2_RNICM8E1))
+           (portRef C (instanceRef CKE_7_m1_0_0_o2_RNIGC501))
+           (portRef C (instanceRef CKE_7_m1_0_0_o2_RNI7FOA1))
+           (portRef C (instanceRef S_s_0_0_RNO_0))
+           (portRef N_551)
+          ))
+          (net N_643 (joined
+           (portRef Z (instanceRef S_s_0_0_RNO_0))
+           (portRef C (instanceRef S_s_0_0_0))
+          ))
+          (net RC12 (joined
+           (portRef Z (instanceRef CKE_7_m1_0_0_o2_RNI7FOA1))
+           (portRef RC12)
+          ))
+          (net (rename FS_4 "FS[4]") (joined
+           (portRef (member fs 11))
+           (portRef C (instanceRef RA_35_0_0_a3_4_7))
+           (portRef D (instanceRef nRWE_s_i_0_63_1))
+           (portRef B (instanceRef Ready3_0_a3_4))
+           (portRef D (instanceRef nCAS_s_i_0_m2))
+           (portRef B (instanceRef nRAS_s_i_0_o2_0))
+           (portRef A (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0))
+           (portRef B (instanceRef RA_35_0_0_0_5))
+           (portRef A (instanceRef RA_35_0_0_0_9))
+           (portRef A (instanceRef BA_4_0))
+           (portRef A (instanceRef BA_4_1))
+           (portRef A (instanceRef RA_35_2_0_RNO_10))
+           (portRef D (instanceRef RA_35_0_0_RNO_0))
+           (portRef A (instanceRef CKE_7_m1_0_0_o2_RNICM8E1))
+           (portRef A (instanceRef CKE_7_m1_0_0_o2_RNIGC501))
+          ))
+          (net N_792 (joined
+           (portRef Z (instanceRef CKE_7_m1_0_0_o2_RNIGC501))
+           (portRef D (instanceRef RA_35_0_0_a3_2))
+           (portRef D (instanceRef RA_35_i_i_0_a3_1))
+          ))
+          (net (rename RC_1 "RC[1]") (joined
+           (portRef (member rc 1))
+           (portRef A (instanceRef nRAS_s_i_0_a3_8))
+           (portRef C (instanceRef CKE_7_bm))
+           (portRef B (instanceRef RC_3_0_0_2))
+           (portRef B (instanceRef N_360_i))
+           (portRef A (instanceRef RC_3_0_0_1))
+          ))
+          (net CO0_1 (joined
+           (portRef CO0_1)
+           (portRef D (instanceRef nRAS_s_i_0_a3_8))
+           (portRef A (instanceRef RC_3_0_0_a3_1_1))
+           (portRef A (instanceRef RC_3_0_0_2))
+           (portRef A (instanceRef N_360_i))
+           (portRef B (instanceRef RC_3_0_0_1))
+          ))
+          (net (rename RC_2 "RC[2]") (joined
+           (portRef (member rc 0))
+           (portRef C (instanceRef nRAS_s_i_0_a3_8))
+           (portRef B (instanceRef RC_3_0_0_a3_1_1))
+           (portRef C (instanceRef RC_3_0_0_2))
+           (portRef C (instanceRef N_360_i))
+           (portRef C (instanceRef RC_3_0_0_1))
+          ))
+          (net (rename RC_3_1 "RC_3[1]") (joined
+           (portRef Z (instanceRef RC_3_0_0_1))
+           (portRef (member rc_3 1))
+          ))
+          (net N_185 (joined
+           (portRef Z (instanceRef N_314_i_i_o3))
+           (portRef C (instanceRef SUM2_0_o2))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2))
+           (portRef B (instanceRef N_187_i))
+           (portRef D (instanceRef wb_we_RNO_0))
+           (portRef D (instanceRef CmdBitbangMXO2_RNINSM62))
+          ))
+          (net N_804 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_5))
+           (portRef D (instanceRef nRAS_s_i_0_a3_0_RNIIR094))
+           (portRef A (instanceRef RA_35_2_0_a3_3_10))
+           (portRef B (instanceRef CKE_7s2_0_0_o3))
+           (portRef A (instanceRef CKE_7_am))
+           (portRef A (instanceRef nRAS_s_i_0_a3_5_RNIH7J73_0))
+           (portRef A (instanceRef nRAS_s_i_0_a3_5_RNIH7J73))
+          ))
+          (net N_285_i (joined
+           (portRef Z (instanceRef N_285_i))
+           (portRef A (instanceRef S_r_i_0_o2_RNI62C53_1))
+           (portRef A (instanceRef nRAS_s_i_0_a3_6))
+           (portRef A (instanceRef nRAS_s_i_0_a3_0))
+           (portRef A (instanceRef nCAS_s_i_0_a3_0))
+           (portRef A (instanceRef nCAS_s_i_0_a3))
+           (portRef A (instanceRef nRAS_s_i_0_0))
+           (portRef B (instanceRef nRAS_s_i_0_a3_5_RNIH7J73_0))
+           (portRef D (instanceRef nRAS_s_i_0_a3_5_RNIH7J73))
+          ))
+          (net N_872 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_5_RNIH7J73))
+           (portRef C (instanceRef nCAS_s_i_0_a3_RNIO1UQ3))
+          ))
+          (net N_849 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_8_3))
+           (portRef C (instanceRef wb_dati_7_0_0_0_3))
+           (portRef C (instanceRef wb_dati_7_0_0_1))
+           (portRef C (instanceRef wb_dati_7_0_0_6))
+          ))
+          (net BA_0_sqmuxa (joined
+           (portRef Z (instanceRef CKE_7_m1_0_0_o2_RNICM8E1))
+           (portRef BA_0_sqmuxa)
+          ))
+          (net (rename RWBank_1 "RWBank[1]") (joined
+           (portRef (member rwbank 6))
+           (portRef A (instanceRef S_r_i_0_o2_RNIP4KI1_1))
+          ))
+          (net (rename S_r_i_0_o2_1 "S_r_i_0_o2[1]") (joined
+           (portRef Z (instanceRef S_r_i_0_o2_1))
+           (portRef B (instanceRef S_r_i_0_o2_RNI62C53_1))
+           (portRef A (instanceRef RA_35_2_0_a3_0_10))
+           (portRef C (instanceRef nRAS_s_i_0_a3_0))
+           (portRef B (instanceRef RA_35_2_0_a3_10))
+           (portRef D (instanceRef S_r_i_0_o2_0_RNI36E21_1))
+           (portRef C (instanceRef S_r_i_0_o2_RNIBAU51_1))
+           (portRef D (instanceRef S_r_i_0_o2_RNIOGTF1_1))
+           (portRef D (instanceRef S_r_i_0_o2_RNIP4KI1_1))
+          ))
+          (net N_699 (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIP4KI1_1))
+           (portRef C (instanceRef un2_S_2_i_0_0_o3_RNIHFHN3))
+          ))
+          (net N_617 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_5_RNIH7J73_0))
+           (portRef C (instanceRef nRAS_s_i_0_0_RNI0PC64))
+          ))
+          (net (rename N_225_i_1z "N_225_i") (joined
+           (portRef Z (instanceRef N_225_i))
+           (portRef N_225_i_1z)
+          ))
+          (net (rename N_201_i_1z "N_201_i") (joined
+           (portRef Z (instanceRef N_201_i))
+           (portRef N_201_i_1z)
+          ))
+          (net RWSel (joined
+           (portRef RWSel)
+           (portRef B (instanceRef SUM2_0_o2))
+           (portRef B (instanceRef CmdTout_3_0_a3_0_a3_0))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_0_1))
+           (portRef C (instanceRef N_368_i))
+           (portRef D (instanceRef N_369_i))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S))
+           (portRef C0 (instanceRef un1_CS_0_sqmuxa_0_0_0))
+           (portRef A (instanceRef N_187_i))
+           (portRef C (instanceRef wb_we_RNO_0))
+           (portRef C (instanceRef CmdBitbangMXO2_RNINSM62))
+           (portRef A (instanceRef S_r_i_0_o2_RNIOGTF1_1))
+          ))
+          (net N_187 (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIOGTF1_1))
+           (portRef A (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0))
+           (portRef B (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_0))
+           (portRef B (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5))
+           (portRef B (instanceRef S_r_i_0_o2_RNI3VQTC_1))
+          ))
+          (net (rename FS_3 "FS[3]") (joined
+           (portRef (member fs 12))
+           (portRef A (instanceRef RA_35_0_0_a3_4_7))
+           (portRef C (instanceRef nRWE_s_i_0_63_1))
+           (portRef C (instanceRef nRAS_s_i_0_m3))
+           (portRef B (instanceRef Ready3_0_a3_5))
+           (portRef C (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0))
+           (portRef C (instanceRef nCAS_s_i_0_m2))
+           (portRef A (instanceRef nRAS_s_i_0_o2_0))
+           (portRef A (instanceRef RA_35_0_0_0_5))
+           (portRef A (instanceRef RA_35_0_0_a3_2))
+           (portRef A (instanceRef RA_35_i_i_0_a3_1))
+           (portRef A (instanceRef RA_35_0_0_RNO_0))
+          ))
+          (net (rename FS_1 "FS[1]") (joined
+           (portRef (member fs 14))
+           (portRef A (instanceRef nRWE_s_i_0_63_1))
+           (portRef A (instanceRef nRAS_s_i_0_m3))
+           (portRef A (instanceRef Ready3_0_a3_5))
+           (portRef A (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0))
+           (portRef A (instanceRef nCAS_s_i_0_m2))
+           (portRef B (instanceRef RA_35_2_0_RNO_10))
+           (portRef B (instanceRef RA_35_0_0_RNO_0))
+          ))
+          (net N_684 (joined
+           (portRef Z (instanceRef RA_35_0_0_RNO_0))
+           (portRef B (instanceRef RA_35_0_0_0))
+          ))
+          (net N_627 (joined
+           (portRef Z (instanceRef RA_35_2_0_RNO_10))
+           (portRef B (instanceRef RA_35_2_0_10))
+          ))
+          (net N_194 (joined
+           (portRef Z (instanceRef S_r_i_0_o2_2))
+           (portRef A (instanceRef RA_35_2_0_a3_10))
+           (portRef B (instanceRef S_r_i_0_o2_0_RNI36E21_1))
+           (portRef B (instanceRef S_r_i_0_o2_RNIFNP81_2))
+           (portRef B (instanceRef S_r_i_0_o2_RNIFNP81_0_2))
+          ))
+          (net S_1 (joined
+           (portRef S_1)
+           (portRef A (instanceRef S_s_0_0_0))
+           (portRef A (instanceRef S_r_i_0_o2_0_RNI36E21_1))
+           (portRef A (instanceRef S_r_i_0_o2_RNIFNP81_2))
+           (portRef C (instanceRef S_r_i_0_o2_RNIFNP81_0_2))
+          ))
+          (net N_372_i (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIFNP81_0_2))
+           (portRef N_372_i)
+          ))
+          (net (rename FS_15 "FS[15]") (joined
+           (portRef (member fs 0))
+           (portRef A (instanceRef un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0))
+           (portRef B (instanceRef wb_rst8_0_a3_0_a3))
+           (portRef D (instanceRef Ready3_0_a3_4))
+           (portRef A (instanceRef DQMH_4_iv_0_0_i_i_a3_0_a3))
+           (portRef A (instanceRef N_507_i))
+           (portRef B (instanceRef N_285_i))
+           (portRef A (instanceRef wb_req_RNO_0))
+          ))
+          (net wb_adr_0_sqmuxa_1_i (joined
+           (portRef Z (instanceRef wb_req_RNO_0))
+           (portRef SP (instanceRef wb_req))
+          ))
+          (net CmdBitbangMXO2 (joined
+           (portRef Q (instanceRef CmdBitbangMXO2))
+           (portRef A (instanceRef CmdBitbangMXO2_RNINSM62))
+          ))
+          (net N_777 (joined
+           (portRef Z (instanceRef un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2_0))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_10_7))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_14_7))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_12_7))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_7_3))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_9_7))
+           (portRef B (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0_0))
+           (portRef B (instanceRef wb_we_RNO_0))
+           (portRef B (instanceRef CmdBitbangMXO2_RNINSM62))
+          ))
+          (net CmdBitbangMXO2_RNINSM62 (joined
+           (portRef Z (instanceRef CmdBitbangMXO2_RNINSM62))
+           (portRef SP (instanceRef wb_adr_7))
+           (portRef SP (instanceRef wb_adr_6))
+           (portRef SP (instanceRef wb_adr_5))
+           (portRef SP (instanceRef wb_adr_4))
+           (portRef SP (instanceRef wb_adr_3))
+           (portRef SP (instanceRef wb_adr_2))
+           (portRef SP (instanceRef wb_adr_1))
+           (portRef SP (instanceRef wb_adr_0))
+           (portRef SP (instanceRef wb_dati_7))
+           (portRef SP (instanceRef wb_dati_6))
+           (portRef SP (instanceRef wb_dati_5))
+           (portRef SP (instanceRef wb_dati_4))
+           (portRef SP (instanceRef wb_dati_3))
+           (portRef SP (instanceRef wb_dati_2))
+           (portRef SP (instanceRef wb_dati_1))
+           (portRef SP (instanceRef wb_dati_0))
+          ))
+          (net CmdExecMXO2 (joined
+           (portRef Q (instanceRef CmdExecMXO2))
+           (portRef C (instanceRef wb_cyc_stb_RNO))
+           (portRef B (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0))
+           (portRef A (instanceRef wb_we_RNO_0))
+          ))
+          (net wb_we_RNO_0 (joined
+           (portRef Z (instanceRef wb_we_RNO_0))
+           (portRef SP (instanceRef wb_we))
+          ))
+          (net N_856 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_14_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_a3_7))
+           (portRef D (instanceRef wb_adr_7_i_i_5_0))
+           (portRef A (instanceRef wb_dati_7_0_0_0_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_13_RNI81UL_7))
+          ))
+          (net N_757 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_13_RNI81UL_7))
+           (portRef A (instanceRef wb_dati_7_0_0_4))
+           (portRef A (instanceRef wb_dati_7_0_0_6))
+          ))
+          (net CKE_7 (joined
+           (portRef Z (instanceRef CKE_7))
+           (portRef A (instanceRef CKE_7_RNIS77M1))
+          ))
+          (net (rename CKE_7_RNIS77M1_1z "CKE_7_RNIS77M1") (joined
+           (portRef Z (instanceRef CKE_7_RNIS77M1))
+           (portRef CKE_7_RNIS77M1_1z)
+          ))
+          (net N_185_i (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIBAU51_1))
+           (portRef N_185_i)
+          ))
+          (net (rename N_187_i_1z "N_187_i") (joined
+           (portRef Z (instanceRef N_187_i))
+           (portRef SP (instanceRef CmdBitbangMXO2))
+           (portRef SP (instanceRef CmdExecMXO2))
+           (portRef SP (instanceRef CmdSetRWBankFFChip))
+           (portRef N_187_i_1z)
+          ))
+          (net un1_CS_0_sqmuxa_0_0_0_bm (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_0_bm))
+           (portRef ALUT (instanceRef un1_CS_0_sqmuxa_0_0_0))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_0_am (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_0_am))
+           (portRef BLUT (instanceRef un1_CS_0_sqmuxa_0_0_0))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_0 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_0))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2))
+          ))
+          (net N_193 (joined
+           (portRef Z (instanceRef SUM0_i_o2))
+           (portRef D (instanceRef SUM0_i_a3_1))
+           (portRef A (instanceRef S_r_i_0_o2_RNIVM0LF_1))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_0_bm))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_a3_2_2 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_2_2))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_0_bm))
+          ))
+          (net (rename Din_c_6 "Din_c[6]") (joined
+           (portRef (member din_c 1))
+           (portRef A (instanceRef CmdBitbangMXO2_3_0_a3_0))
+           (portRef A (instanceRef RDout_i_0_i_a3_6))
+           (portRef A (instanceRef wb_adr_RNO_6))
+           (portRef C (instanceRef SUM1_0_o3_0))
+           (portRef A (instanceRef RWMask_RNO_6))
+           (portRef C (instanceRef SUM0_i_a3_1))
+           (portRef A (instanceRef RWBank_3_0_6))
+           (portRef C (instanceRef CmdExecMXO2_3_0_a3_0_RNIAJ811))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_0))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_0_bm))
+          ))
+          (net (rename CS_0 "CS[0]") (joined
+           (portRef (member cs 2))
+           (portRef A (instanceRef SUM2_0_o2))
+           (portRef B (instanceRef CmdBitbangMXO2_3_0_a3_0))
+           (portRef A (instanceRef SUM0_i_a3_1))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_0))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S))
+           (portRef A (instanceRef S_r_i_0_o2_RNI3VQTC_1))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_0_bm))
+          ))
+          (net (rename CmdTout_2 "CmdTout[2]") (joined
+           (portRef (member cmdtout 0))
+           (portRef C (instanceRef N_369_i))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_0_am))
+          ))
+          (net (rename CmdTout_1 "CmdTout[1]") (joined
+           (portRef (member cmdtout 1))
+           (portRef B (instanceRef N_368_i))
+           (portRef B (instanceRef N_369_i))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_0_am))
+          ))
+          (net CO0_0 (joined
+           (portRef CO0_0)
+           (portRef A (instanceRef CmdTout_3_0_a3_0_a3_0))
+           (portRef A (instanceRef N_368_i))
+           (portRef A (instanceRef N_369_i))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_0_am))
+          ))
+          (net wb_we_RNO (joined
+           (portRef Z (instanceRef wb_we_RNO))
+           (portRef D (instanceRef wb_we))
+          ))
+          (net C14M_c (joined
+           (portRef C14M_c)
+           (portRef C14M_c (instanceRef ufmefb))
+           (portRef CK (instanceRef CmdBitbangMXO2))
+           (portRef CK (instanceRef CmdExecMXO2))
+           (portRef CK (instanceRef CmdSetRWBankFFChip))
+           (portRef CK (instanceRef LEDEN))
+           (portRef CK (instanceRef RWMask_7))
+           (portRef CK (instanceRef RWMask_6))
+           (portRef CK (instanceRef RWMask_5))
+           (portRef CK (instanceRef RWMask_4))
+           (portRef CK (instanceRef RWMask_3))
+           (portRef CK (instanceRef RWMask_2))
+           (portRef CK (instanceRef RWMask_1))
+           (portRef CK (instanceRef RWMask_0))
+           (portRef CK (instanceRef wb_adr_7))
+           (portRef CK (instanceRef wb_adr_6))
+           (portRef CK (instanceRef wb_adr_5))
+           (portRef CK (instanceRef wb_adr_4))
+           (portRef CK (instanceRef wb_adr_3))
+           (portRef CK (instanceRef wb_adr_2))
+           (portRef CK (instanceRef wb_adr_1))
+           (portRef CK (instanceRef wb_adr_0))
+           (portRef CK (instanceRef wb_cyc_stb))
+           (portRef CK (instanceRef wb_dati_7))
+           (portRef CK (instanceRef wb_dati_6))
+           (portRef CK (instanceRef wb_dati_5))
+           (portRef CK (instanceRef wb_dati_4))
+           (portRef CK (instanceRef wb_dati_3))
+           (portRef CK (instanceRef wb_dati_2))
+           (portRef CK (instanceRef wb_dati_1))
+           (portRef CK (instanceRef wb_dati_0))
+           (portRef CK (instanceRef wb_req))
+           (portRef CK (instanceRef wb_rst))
+           (portRef CK (instanceRef wb_we))
+          ))
+          (net wb_we (joined
+           (portRef Q (instanceRef wb_we))
+           (portRef wb_we (instanceRef ufmefb))
+          ))
+          (net wb_rst8 (joined
+           (portRef Z (instanceRef wb_rst8_0_a3_0_a3))
+           (portRef D (instanceRef wb_rst))
+          ))
+          (net wb_rst (joined
+           (portRef Q (instanceRef wb_rst))
+           (portRef wb_rst (instanceRef ufmefb))
+          ))
+          (net wb_reqc_i (joined
+           (portRef Z (instanceRef wb_req_RNO))
+           (portRef D (instanceRef wb_req))
+          ))
+          (net wb_req (joined
+           (portRef Q (instanceRef wb_req))
+           (portRef C (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0))
+          ))
+          (net (rename wb_dati_7_0 "wb_dati_7[0]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_0))
+           (portRef D (instanceRef wb_dati_0))
+          ))
+          (net (rename wb_dati_0 "wb_dati[0]") (joined
+           (portRef Q (instanceRef wb_dati_0))
+           (portRef (member wb_dati 7) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_1 "wb_dati_7[1]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_1))
+           (portRef D (instanceRef wb_dati_1))
+          ))
+          (net (rename wb_dati_1 "wb_dati[1]") (joined
+           (portRef Q (instanceRef wb_dati_1))
+           (portRef (member wb_dati 6) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_2 "wb_dati_7[2]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_2))
+           (portRef D (instanceRef wb_dati_2))
+          ))
+          (net (rename wb_dati_2 "wb_dati[2]") (joined
+           (portRef Q (instanceRef wb_dati_2))
+           (portRef (member wb_dati 5) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_3 "wb_dati_7[3]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_3))
+           (portRef D (instanceRef wb_dati_3))
+          ))
+          (net (rename wb_dati_3 "wb_dati[3]") (joined
+           (portRef Q (instanceRef wb_dati_3))
+           (portRef (member wb_dati 4) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_4 "wb_dati_7[4]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_4))
+           (portRef D (instanceRef wb_dati_4))
+          ))
+          (net (rename wb_dati_4 "wb_dati[4]") (joined
+           (portRef Q (instanceRef wb_dati_4))
+           (portRef (member wb_dati 3) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_5 "wb_dati_7[5]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_5))
+           (portRef D (instanceRef wb_dati_5))
+          ))
+          (net (rename wb_dati_5 "wb_dati[5]") (joined
+           (portRef Q (instanceRef wb_dati_5))
+           (portRef (member wb_dati 2) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_6 "wb_dati_7[6]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_6))
+           (portRef D (instanceRef wb_dati_6))
+          ))
+          (net (rename wb_dati_6 "wb_dati[6]") (joined
+           (portRef Q (instanceRef wb_dati_6))
+           (portRef (member wb_dati 1) (instanceRef ufmefb))
+          ))
+          (net (rename wb_dati_7_7 "wb_dati_7[7]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_7))
+           (portRef D (instanceRef wb_dati_7))
+          ))
+          (net (rename wb_dati_7 "wb_dati[7]") (joined
+           (portRef Q (instanceRef wb_dati_7))
+           (portRef (member wb_dati 0) (instanceRef ufmefb))
+          ))
+          (net wb_cyc_stb_RNO (joined
+           (portRef Z (instanceRef wb_cyc_stb_RNO))
+           (portRef D (instanceRef wb_cyc_stb))
+          ))
+          (net (rename un1_CmdSetRWBankFFChip13_1_i_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0[0]") (joined
+           (portRef Z (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0))
+           (portRef SP (instanceRef wb_cyc_stb))
+          ))
+          (net wb_cyc_stb (joined
+           (portRef Q (instanceRef wb_cyc_stb))
+           (portRef wb_cyc_stb (instanceRef ufmefb))
+          ))
+          (net (rename wb_adr_7_i_i_0 "wb_adr_7_i_i[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_0))
+           (portRef D (instanceRef wb_adr_0))
+          ))
+          (net (rename wb_adr_0 "wb_adr[0]") (joined
+           (portRef Q (instanceRef wb_adr_0))
+           (portRef (member wb_adr 7) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_0_0))
+          ))
+          (net (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (joined
+           (portRef Z (instanceRef wb_adr_RNO_1))
+           (portRef D (instanceRef wb_adr_1))
+          ))
+          (net (rename wb_adr_1 "wb_adr[1]") (joined
+           (portRef Q (instanceRef wb_adr_1))
+           (portRef (member wb_adr 6) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_0_1))
+          ))
+          (net N_80_i (joined
+           (portRef Z (instanceRef wb_adr_RNO_2))
+           (portRef D (instanceRef wb_adr_2))
+          ))
+          (net (rename wb_adr_2 "wb_adr[2]") (joined
+           (portRef Q (instanceRef wb_adr_2))
+           (portRef (member wb_adr 5) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_2))
+          ))
+          (net N_268_i (joined
+           (portRef Z (instanceRef wb_adr_RNO_3))
+           (portRef D (instanceRef wb_adr_3))
+          ))
+          (net (rename wb_adr_3 "wb_adr[3]") (joined
+           (portRef Q (instanceRef wb_adr_3))
+           (portRef (member wb_adr 4) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_0_0_3))
+          ))
+          (net N_294 (joined
+           (portRef Z (instanceRef wb_adr_RNO_4))
+           (portRef D (instanceRef wb_adr_4))
+          ))
+          (net (rename wb_adr_4 "wb_adr[4]") (joined
+           (portRef Q (instanceRef wb_adr_4))
+           (portRef (member wb_adr 3) (instanceRef ufmefb))
+           (portRef D (instanceRef wb_dati_7_0_0_0_4))
+          ))
+          (net N_290 (joined
+           (portRef Z (instanceRef wb_adr_RNO_5))
+           (portRef D (instanceRef wb_adr_5))
+          ))
+          (net (rename wb_adr_5 "wb_adr[5]") (joined
+           (portRef Q (instanceRef wb_adr_5))
+           (portRef (member wb_adr 2) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_5))
+          ))
+          (net N_284 (joined
+           (portRef Z (instanceRef wb_adr_RNO_6))
+           (portRef D (instanceRef wb_adr_6))
+          ))
+          (net (rename wb_adr_6 "wb_adr[6]") (joined
+           (portRef Q (instanceRef wb_adr_6))
+           (portRef (member wb_adr 1) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_0_6))
+          ))
+          (net N_267_i (joined
+           (portRef Z (instanceRef wb_adr_RNO_7))
+           (portRef D (instanceRef wb_adr_7))
+          ))
+          (net (rename wb_adr_7 "wb_adr[7]") (joined
+           (portRef Q (instanceRef wb_adr_7))
+           (portRef (member wb_adr 0) (instanceRef ufmefb))
+           (portRef C (instanceRef wb_dati_7_0_0_0_0_7))
+          ))
+          (net N_309_i (joined
+           (portRef Z (instanceRef RWMask_RNO_0))
+           (portRef D (instanceRef RWMask_0))
+          ))
+          (net (rename un1_RWMask_0_sqmuxa_1_i_0_0_0 "un1_RWMask_0_sqmuxa_1_i_0_0[0]") (joined
+           (portRef Z (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0_0))
+           (portRef SP (instanceRef RWMask_7))
+           (portRef SP (instanceRef RWMask_6))
+           (portRef SP (instanceRef RWMask_5))
+           (portRef SP (instanceRef RWMask_4))
+           (portRef SP (instanceRef RWMask_3))
+           (portRef SP (instanceRef RWMask_2))
+           (portRef SP (instanceRef RWMask_1))
+           (portRef SP (instanceRef RWMask_0))
+          ))
+          (net (rename RWMask_0 "RWMask[0]") (joined
+           (portRef Q (instanceRef RWMask_0))
+           (portRef C (instanceRef RWBank_3_0_0_0))
+          ))
+          (net N_307_i (joined
+           (portRef Z (instanceRef RWMask_RNO_1))
+           (portRef D (instanceRef RWMask_1))
+          ))
+          (net (rename RWMask_1 "RWMask[1]") (joined
+           (portRef Q (instanceRef RWMask_1))
+           (portRef C (instanceRef RWBank_3_0_1))
+          ))
+          (net N_304_i (joined
+           (portRef Z (instanceRef RWMask_RNO_2))
+           (portRef D (instanceRef RWMask_2))
+          ))
+          (net (rename RWMask_2 "RWMask[2]") (joined
+           (portRef Q (instanceRef RWMask_2))
+           (portRef C (instanceRef RWBank_3_0_2))
+          ))
+          (net N_302_i (joined
+           (portRef Z (instanceRef RWMask_RNO_3))
+           (portRef D (instanceRef RWMask_3))
+          ))
+          (net (rename RWMask_3 "RWMask[3]") (joined
+           (portRef Q (instanceRef RWMask_3))
+           (portRef C (instanceRef RWBank_3_0_3))
+          ))
+          (net N_310_i (joined
+           (portRef Z (instanceRef RWMask_RNO_4))
+           (portRef D (instanceRef RWMask_4))
+          ))
+          (net (rename RWMask_4 "RWMask[4]") (joined
+           (portRef Q (instanceRef RWMask_4))
+           (portRef C (instanceRef RWBank_3_0_0_4))
+          ))
+          (net N_301_i (joined
+           (portRef Z (instanceRef RWMask_RNO_5))
+           (portRef D (instanceRef RWMask_5))
+          ))
+          (net (rename RWMask_5 "RWMask[5]") (joined
+           (portRef Q (instanceRef RWMask_5))
+           (portRef C (instanceRef RWBank_3_0_5))
+          ))
+          (net N_300_i (joined
+           (portRef Z (instanceRef RWMask_RNO_6))
+           (portRef D (instanceRef RWMask_6))
+          ))
+          (net (rename RWMask_6 "RWMask[6]") (joined
+           (portRef Q (instanceRef RWMask_6))
+           (portRef C (instanceRef RWBank_3_0_6))
+          ))
+          (net N_296 (joined
+           (portRef Z (instanceRef RWMask_RNO_7))
+           (portRef D (instanceRef RWMask_7))
+          ))
+          (net (rename RWMask_7 "RWMask[7]") (joined
+           (portRef Q (instanceRef RWMask_7))
+           (portRef C (instanceRef RWBank_3_0_7))
+          ))
+          (net N_295 (joined
+           (portRef Z (instanceRef LEDEN_RNO))
+           (portRef D (instanceRef LEDEN))
+          ))
+          (net (rename un1_LEDEN_0_sqmuxa_1_i_0_0_0 "un1_LEDEN_0_sqmuxa_1_i_0_0[0]") (joined
+           (portRef Z (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_0))
+           (portRef SP (instanceRef LEDEN))
+          ))
+          (net LEDEN (joined
+           (portRef Q (instanceRef LEDEN))
+           (portRef D (instanceRef RWBank_3_0_0_o3_0))
+           (portRef A (instanceRef LEDEN_RNI6G6M))
+          ))
+          (net CmdSetRWBankFFChip_3 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3))
+           (portRef D (instanceRef CmdSetRWBankFFChip))
+          ))
+          (net CmdSetRWBankFFChip (joined
+           (portRef Q (instanceRef CmdSetRWBankFFChip))
+           (portRef B (instanceRef RWBank_3_0_0_o3_0))
+          ))
+          (net CmdExecMXO2_3 (joined
+           (portRef Z (instanceRef CmdExecMXO2_3_0_a3))
+           (portRef D (instanceRef CmdExecMXO2))
+          ))
+          (net CmdBitbangMXO2_3 (joined
+           (portRef Z (instanceRef CmdBitbangMXO2_3_0_a3))
+           (portRef D (instanceRef CmdBitbangMXO2))
+          ))
+          (net N_215 (joined
+           (portRef Z (instanceRef SUM2_0_o2))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514))
+           (portRef A (instanceRef CmdExecMXO2_3_0_a3_0_RNI6S1P8))
+           (portRef B (instanceRef S_r_i_0_o2_RNIVM0LF_1))
+          ))
+          (net SUM0_i_4 (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNI3VQTC_1))
+           (portRef C (instanceRef S_r_i_0_o2_RNIVM0LF_1))
+          ))
+          (net N_547_i (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIVM0LF_1))
+           (portRef N_547_i)
+          ))
+          (net N_637 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2))
+          ))
+          (net un1_CS_0_sqmuxa_i (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2))
+           (portRef un1_CS_0_sqmuxa_i)
+          ))
+          (net SUM0_i_1 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95))
+           (portRef C (instanceRef S_r_i_0_o2_RNI3VQTC_1))
+          ))
+          (net SUM0_i_3 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5))
+           (portRef D (instanceRef S_r_i_0_o2_RNI3VQTC_1))
+          ))
+          (net N_793 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_10_7))
+           (portRef D (instanceRef wb_dati_7_0_0_a3_2_4))
+           (portRef C (instanceRef wb_adr_7_i_i_a3_6_0))
+           (portRef B (instanceRef wb_dati_7_0_0_RNO_0_7))
+           (portRef B (instanceRef wb_dati_7_0_0_1))
+           (portRef C (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0_0))
+           (portRef B (instanceRef wb_dati_7_0_0_6))
+           (portRef B (instanceRef wb_adr_7_i_i_0))
+          ))
+          (net (rename wb_adr_7_i_i_4_0 "wb_adr_7_i_i_4[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_4_0))
+           (portRef C (instanceRef wb_adr_7_i_i_0))
+          ))
+          (net (rename wb_adr_7_i_i_5_0 "wb_adr_7_i_i_5[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_5_0))
+           (portRef D (instanceRef wb_adr_7_i_i_0))
+          ))
+          (net N_592 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_m3))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_a3_1_0 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S))
+          ))
+          (net N_615 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_0))
+           (portRef A (instanceRef nRAS_s_i_0_a3_0_RNIIR094))
+           (portRef A (instanceRef nRAS_s_i_0_0_RNI0PC64))
+          ))
+          (net N_616 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_1))
+           (portRef B (instanceRef nRAS_s_i_0_0_RNI0PC64))
+          ))
+          (net nRAS_s_i_0_0 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_0))
+           (portRef D (instanceRef nRAS_s_i_0_0_RNI0PC64))
+          ))
+          (net N_358_i (joined
+           (portRef Z (instanceRef nRAS_s_i_0_0_RNI0PC64))
+           (portRef N_358_i)
+          ))
+          (net N_640 (joined
+           (portRef Z (instanceRef nCAS_s_i_0_a3))
+           (portRef A (instanceRef nCAS_s_i_0_a3_RNIO1UQ3))
+          ))
+          (net N_641 (joined
+           (portRef Z (instanceRef nCAS_s_i_0_a3_0))
+           (portRef B (instanceRef nCAS_s_i_0_a3_RNIO1UQ3))
+          ))
+          (net nWE_c (joined
+           (portRef nWE_c)
+           (portRef C (instanceRef nRAS_s_i_0_o2))
+           (portRef D (instanceRef RWSel_2_0_a3_0_a3))
+           (portRef D (instanceRef RA_35_2_0_a3_3_10))
+           (portRef D (instanceRef nRAS_s_i_0_a3_1))
+           (portRef C (instanceRef RDOE_i))
+           (portRef C (instanceRef un1_nDOE_i))
+           (portRef D (instanceRef CKE_7s2_0_0_o3))
+           (portRef C (instanceRef CKE_7_am))
+           (portRef D (instanceRef nCAS_s_i_0_a3_RNIO1UQ3))
+          ))
+          (net N_370_i (joined
+           (portRef Z (instanceRef nCAS_s_i_0_a3_RNIO1UQ3))
+           (portRef N_370_i)
+          ))
+          (net N_760 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_4))
+           (portRef B (instanceRef wb_dati_7_0_0_4))
+           (portRef A (instanceRef wb_dati_7_0_0_2))
+           (portRef A (instanceRef wb_dati_7_0_0_5))
+          ))
+          (net (rename wb_dati_7_0_0_o3_0_2 "wb_dati_7_0_0_o3_0[2]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_o3_0_2))
+           (portRef D (instanceRef wb_dati_7_0_0_2))
+           (portRef D (instanceRef wb_dati_7_0_0_5))
+          ))
+          (net N_602 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_a3_7))
+           (portRef A (instanceRef wb_dati_7_0_0_0_7))
+          ))
+          (net (rename wb_dati_7_0_0_RNO_0_7 "wb_dati_7_0_0_RNO_0[7]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_RNO_0_7))
+           (portRef C (instanceRef wb_dati_7_0_0_0_7))
+          ))
+          (net (rename wb_dati_7_0_0_0_0_7 "wb_dati_7_0_0_0_0[7]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_0_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_7))
+          ))
+          (net N_886 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_m3))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5))
+           (portRef B (instanceRef CmdExecMXO2_3_0_a3_0_RNI6S1P8))
+          ))
+          (net SUM0_i_a3_4_0 (joined
+           (portRef Z (instanceRef CmdExecMXO2_3_0_a3_0_RNIAJ811))
+           (portRef D (instanceRef CmdExecMXO2_3_0_a3_0_RNIPG3P2))
+           (portRef C (instanceRef CmdExecMXO2_3_0_a3_0_RNI6S1P8))
+          ))
+          (net SUM1_0_0 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0))
+           (portRef D (instanceRef CmdExecMXO2_3_0_a3_0_RNI6S1P8))
+          ))
+          (net (rename CmdExecMXO2_3_0_a3_0_RNI6S1P8_1z "CmdExecMXO2_3_0_a3_0_RNI6S1P8") (joined
+           (portRef Z (instanceRef CmdExecMXO2_3_0_a3_0_RNI6S1P8))
+           (portRef CmdExecMXO2_3_0_a3_0_RNI6S1P8_1z)
+          ))
+          (net (rename wb_dati_7_0_0_0_6 "wb_dati_7_0_0_0[6]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_6))
+           (portRef D (instanceRef wb_dati_7_0_0_6))
+          ))
+          (net N_763 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_2_4))
+           (portRef C (instanceRef wb_dati_7_0_0_4))
+          ))
+          (net (rename wb_dati_7_0_0_0_4 "wb_dati_7_0_0_0[4]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_4))
+           (portRef D (instanceRef wb_dati_7_0_0_4))
+          ))
+          (net (rename CS_1 "CS[1]") (joined
+           (portRef (member cs 1))
+           (portRef D (instanceRef CmdBitbangMXO2_3_0_a3_0))
+           (portRef A (instanceRef SUM0_i_m3_0_bm))
+           (portRef A (instanceRef SUM0_i_o2))
+           (portRef A (instanceRef CmdExecMXO2_3_0_a3_0_RNIAJ811))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o2))
+           (portRef A (instanceRef CmdExecMXO2_3_0_a3_0_RNIPG3P2))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_m3))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5))
+          ))
+          (net N_720_tz (joined
+           (portRef Z (instanceRef CmdExecMXO2_3_0_a3_0_RNIPG3P2))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5))
+          ))
+          (net (rename CS_2 "CS[2]") (joined
+           (portRef (member cs 0))
+           (portRef C (instanceRef CmdBitbangMXO2_3_0_a3_0))
+           (portRef B (instanceRef SUM0_i_o2))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_5_1))
+           (portRef B (instanceRef CmdExecMXO2_3_0_a3_0_RNIAJ811))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_2_2))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1))
+           (portRef B (instanceRef CmdExecMXO2_3_0_a3_0_RNIPG3P2))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95))
+          ))
+          (net N_350 (joined
+           (portRef Z (instanceRef SUM0_i_o2_2))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95))
+          ))
+          (net SUM0_i_0 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95))
+          ))
+          (net CmdRWMaskSet (joined
+           (portRef CmdRWMaskSet)
+           (portRef A (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0_0))
+          ))
+          (net (rename un1_RWMask_0_sqmuxa_1_i_0_a3_0_0_0 "un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]") (joined
+           (portRef Z (instanceRef un1_RWMask_0_sqmuxa_1_i_0_a3_0_0_0))
+           (portRef D (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0_0))
+          ))
+          (net (rename wb_dati_7_0_0_0_a3_0_0 "wb_dati_7_0_0_0_a3_0[0]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_a3_0_0))
+           (portRef D (instanceRef wb_dati_7_0_0_0_0))
+          ))
+          (net N_611 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_2_3))
+           (portRef B (instanceRef wb_dati_7_0_0_o3_0_2))
+           (portRef A (instanceRef wb_dati_7_0_0_0_3))
+           (portRef A (instanceRef wb_dati_7_0_0_1))
+          ))
+          (net (rename wb_dati_7_0_0_0_1 "wb_dati_7_0_0_0[1]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_1))
+           (portRef D (instanceRef wb_dati_7_0_0_1))
+          ))
+          (net N_234 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91))
+           (portRef C (instanceRef CmdExecMXO2_3_0_a3_0_RNIPG3P2))
+           (portRef D (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_m3))
+           (portRef D (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514))
+          ))
+          (net (rename CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_1z "CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514") (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514))
+           (portRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_1z)
+          ))
+          (net N_783 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_7_3))
+           (portRef C (instanceRef wb_adr_7_i_i_3_0))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_4))
+           (portRef A (instanceRef wb_dati_7_0_0_0_4))
+           (portRef A (instanceRef wb_dati_7_0_0_0_6))
+           (portRef A (instanceRef wb_dati_7_0_0_0_0_3))
+           (portRef B (instanceRef wb_dati_7_0_0_0_3))
+          ))
+          (net (rename wb_dati_7_0_0_0_0_3 "wb_dati_7_0_0_0_0[3]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_0_3))
+           (portRef D (instanceRef wb_dati_7_0_0_0_3))
+          ))
+          (net N_634 (joined
+           (portRef Z (instanceRef wb_we_7_iv_0_0_0_a3_1))
+           (portRef C (instanceRef wb_we_RNO_3))
+           (portRef A (instanceRef wb_adr_7_i_i_4_0))
+          ))
+          (net N_753 (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_a3_4_0))
+           (portRef B (instanceRef wb_adr_7_i_i_4_0))
+          ))
+          (net (rename wb_adr_7_i_i_1_0 "wb_adr_7_i_i_1[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_1_0))
+           (portRef C (instanceRef wb_adr_7_i_i_4_0))
+          ))
+          (net (rename wb_adr_7_i_i_3_0 "wb_adr_7_i_i_3[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_3_0))
+           (portRef D (instanceRef wb_adr_7_i_i_4_0))
+          ))
+          (net N_755 (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_a3_6_0))
+           (portRef C (instanceRef wb_adr_7_i_i_5_0))
+          ))
+          (net N_345 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2))
+          ))
+          (net N_735 (joined
+           (portRef Z (instanceRef SUM0_i_a3_1))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2))
+          ))
+          (net CmdLEDSet (joined
+           (portRef CmdLEDSet)
+           (portRef A (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0_0))
+          ))
+          (net (rename un1_CmdSetRWBankFFChip13_1_i_0_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_0[0]") (joined
+           (portRef Z (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0_0))
+           (portRef C (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0))
+          ))
+          (net (rename wb_dati_7_0_0_a3_6_1_3 "wb_dati_7_0_0_a3_6_1[3]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_4_1_0_7))
+           (portRef D (instanceRef wb_dati_7_0_0_0_o2_3))
+           (portRef D (instanceRef wb_dati_7_0_0_RNO_0_7))
+          ))
+          (net (rename FS_14 "FS[14]") (joined
+           (portRef (member fs 1))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_10_7))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_14_7))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_12_7))
+           (portRef C (instanceRef wb_dati_7_0_0_a3_7_3))
+           (portRef A (instanceRef wb_we_7_iv_0_0_0_a3_6))
+           (portRef A (instanceRef wb_rst8_0_a3_0_a3))
+           (portRef B (instanceRef wb_adr_RNO_4))
+           (portRef B (instanceRef wb_adr_RNO_5))
+           (portRef B (instanceRef wb_adr_RNO_6))
+           (portRef C (instanceRef Ready3_0_a3_4))
+           (portRef A (instanceRef wb_reqc_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_a3_9_7))
+           (portRef B (instanceRef wb_cyc_stb_RNO_0))
+           (portRef A (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0_0))
+           (portRef A (instanceRef RA_35_0_0_0_7))
+          ))
+          (net N_801 (joined
+           (portRef Z (instanceRef RA_35_0_0_a3_4_7))
+           (portRef C (instanceRef RA_35_0_0_0))
+           (portRef B (instanceRef RA_35_0_0_3))
+           (portRef B (instanceRef RA_35_0_0_4))
+           (portRef B (instanceRef RA_35_0_0_0_6))
+           (portRef B (instanceRef RA_35_0_0_0_7))
+          ))
+          (net (rename RA_35_0_0_0_0_7 "RA_35_0_0_0_0[7]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_0_7))
+           (portRef C (instanceRef RA_35_0_0_0_7))
+          ))
+          (net (rename RA_35_7 "RA_35[7]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_7))
+           (portRef (member ra_35 4))
+          ))
+          (net (rename RA_35_0_0_0_0_6 "RA_35_0_0_0_0[6]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_0_6))
+           (portRef C (instanceRef RA_35_0_0_0_6))
+          ))
+          (net (rename RA_35_6 "RA_35[6]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_6))
+           (portRef (member ra_35 5))
+          ))
+          (net (rename RA_35_0_0_0_4 "RA_35_0_0_0[4]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_4))
+           (portRef C (instanceRef RA_35_0_0_4))
+          ))
+          (net (rename RA_35_4 "RA_35[4]") (joined
+           (portRef Z (instanceRef RA_35_0_0_4))
+           (portRef (member ra_35 7))
+          ))
+          (net (rename RA_35_0_0_0_3 "RA_35_0_0_0[3]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_3))
+           (portRef C (instanceRef RA_35_0_0_3))
+          ))
+          (net (rename RA_35_3 "RA_35[3]") (joined
+           (portRef Z (instanceRef RA_35_0_0_3))
+           (portRef (member ra_35 8))
+          ))
+          (net (rename wb_dati_7_0_0_0_a3_0_3 "wb_dati_7_0_0_0_a3_0[3]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_a3_0_3))
+           (portRef D (instanceRef wb_dati_7_0_0_0_0_3))
+          ))
+          (net (rename wb_dati_7_0_0_a3_1_6 "wb_dati_7_0_0_a3_1[6]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_1_0_6))
+           (portRef D (instanceRef wb_dati_7_0_0_0_6))
+          ))
+          (net CKE_7_am (joined
+           (portRef Z (instanceRef CKE_7_am))
+           (portRef BLUT (instanceRef CKE_7))
+          ))
+          (net CKE_7_bm (joined
+           (portRef Z (instanceRef CKE_7_bm))
+           (portRef ALUT (instanceRef CKE_7))
+          ))
+          (net CKE_7_sm0 (joined
+           (portRef Z (instanceRef CKE_7s2_0_0))
+           (portRef C0 (instanceRef CKE_7))
+          ))
+          (net N_687 (joined
+           (portRef Z (instanceRef wb_cyc_stb_RNO_0))
+           (portRef A (instanceRef wb_cyc_stb_RNO))
+          ))
+          (net (rename un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0]") (joined
+           (portRef Z (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0))
+           (portRef C (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_0_0))
+          ))
+          (net N_256 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_o2_0))
+           (portRef B (instanceRef nRAS_s_i_0_0))
+          ))
+          (net N_890 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_8))
+           (portRef C (instanceRef nCAS_s_i_0_a3))
+           (portRef D (instanceRef nRAS_s_i_0_0))
+          ))
+          (net N_220 (joined
+           (portRef Z (instanceRef CKE_7s2_0_0_o3))
+           (portRef A (instanceRef CKE_7s2_0_0))
+           (portRef B (instanceRef nCAS_s_i_0_a3))
+          ))
+          (net N_196 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_o2_4))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_4))
+          ))
+          (net (rename Ain_c_1 "Ain_c[1]") (joined
+           (portRef (member ain_c 6))
+           (portRef A (instanceRef RA_35_i_i_0_1))
+          ))
+          (net N_182 (joined
+           (portRef Z (instanceRef RA_35_0_0_o2_5))
+           (portRef B (instanceRef RA_35_0_0_1_0))
+           (portRef B (instanceRef RA_35_0_0_0_3))
+           (portRef B (instanceRef RA_35_0_0_0_0_7))
+           (portRef B (instanceRef RA_35_0_0_0_0_6))
+           (portRef B (instanceRef RA_35_0_0_0_4))
+           (portRef B (instanceRef RA_35_0_0_5))
+           (portRef B (instanceRef RA_35_0_0_2))
+           (portRef B (instanceRef RA_35_i_i_0_1))
+          ))
+          (net N_659 (joined
+           (portRef Z (instanceRef RA_35_i_i_0_a3_1))
+           (portRef C (instanceRef RA_35_i_i_0_1))
+          ))
+          (net N_660 (joined
+           (portRef Z (instanceRef RA_35_i_i_0_a3_0_1))
+           (portRef D (instanceRef RA_35_i_i_0_1))
+          ))
+          (net N_223 (joined
+           (portRef Z (instanceRef RA_35_i_i_0_1))
+           (portRef N_223)
+          ))
+          (net (rename Ain_c_2 "Ain_c[2]") (joined
+           (portRef (member ain_c 5))
+           (portRef A (instanceRef RA_35_0_0_2))
+          ))
+          (net N_679 (joined
+           (portRef Z (instanceRef RA_35_0_0_a3_2))
+           (portRef C (instanceRef RA_35_0_0_2))
+          ))
+          (net N_680 (joined
+           (portRef Z (instanceRef RA_35_0_0_a3_0_2))
+           (portRef D (instanceRef RA_35_0_0_2))
+          ))
+          (net (rename RA_35_2 "RA_35[2]") (joined
+           (portRef Z (instanceRef RA_35_0_0_2))
+           (portRef (member ra_35 9))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_o2 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o2))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_0))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_a3_0_1 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_0_1))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_0))
+          ))
+          (net (rename Ain_c_5 "Ain_c[5]") (joined
+           (portRef (member ain_c 2))
+           (portRef A (instanceRef RA_35_0_0_5))
+          ))
+          (net N_621 (joined
+           (portRef Z (instanceRef RA_35_0_0_a3_5))
+           (portRef C (instanceRef RA_35_0_0_5))
+          ))
+          (net (rename RA_35_0_0_0_5 "RA_35_0_0_0[5]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_5))
+           (portRef D (instanceRef RA_35_0_0_5))
+          ))
+          (net (rename RA_35_5 "RA_35[5]") (joined
+           (portRef Z (instanceRef RA_35_0_0_5))
+           (portRef (member ra_35 6))
+          ))
+          (net N_624 (joined
+           (portRef Z (instanceRef RA_35_2_0_a3_10))
+           (portRef A (instanceRef RA_35_2_0_10))
+          ))
+          (net N_628 (joined
+           (portRef Z (instanceRef RA_35_2_0_a3_3_10))
+           (portRef C (instanceRef RA_35_2_0_10))
+          ))
+          (net (rename RA_35_2_0_0_10 "RA_35_2_0_0[10]") (joined
+           (portRef Z (instanceRef RA_35_2_0_0_10))
+           (portRef D (instanceRef RA_35_2_0_10))
+          ))
+          (net (rename RA_35_10 "RA_35[10]") (joined
+           (portRef Z (instanceRef RA_35_2_0_10))
+           (portRef (member ra_35 1))
+          ))
+          (net N_208 (joined
+           (portRef Z (instanceRef wb_we_RNO_1))
+           (portRef B (instanceRef wb_we_RNO))
+          ))
+          (net N_799 (joined
+           (portRef Z (instanceRef wb_we_7_iv_0_0_0_a3_6))
+           (portRef D (instanceRef wb_adr_RNO_0_1))
+           (portRef D (instanceRef wb_we_RNO_3))
+           (portRef B (instanceRef wb_we_RNO_2))
+           (portRef C (instanceRef wb_adr_RNO_1_1))
+           (portRef C (instanceRef wb_we_RNO))
+          ))
+          (net wb_we_7_iv_0_0_3_0_1 (joined
+           (portRef Z (instanceRef wb_we_RNO_2))
+           (portRef D (instanceRef wb_we_RNO))
+          ))
+          (net (rename Din_c_1 "Din_c[1]") (joined
+           (portRef (member din_c 6))
+           (portRef B (instanceRef CmdRWMaskSet_3_0_a3))
+           (portRef B (instanceRef CmdLEDSet_3_0_a8_0_a3))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0_0))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91))
+           (portRef A (instanceRef RDout_i_0_i_a3_1))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_5_1))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0))
+           (portRef A (instanceRef RWMask_RNO_1))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o3_0))
+           (portRef A (instanceRef RWBank_3_0_1))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_9))
+           (portRef C0 (instanceRef SUM0_i_m3_0))
+           (portRef A (instanceRef CmdLEDGet_3_0_a3))
+           (portRef A (instanceRef CmdSetRWBankFFLED_4_0_a8_0_a3))
+           (portRef A (instanceRef CmdBitbangMXO2_3_0_a3))
+           (portRef A (instanceRef wb_adr_RNO_1))
+          ))
+          (net N_768 (joined
+           (portRef Z (instanceRef wb_adr_RNO_0_1))
+           (portRef B (instanceRef wb_adr_RNO_1))
+          ))
+          (net wb_adr_7_5_41_0_1 (joined
+           (portRef Z (instanceRef wb_adr_RNO_1_1))
+           (portRef D (instanceRef wb_adr_RNO_1))
+          ))
+          (net (rename Din_c_4 "Din_c[4]") (joined
+           (portRef (member din_c 3))
+           (portRef C (instanceRef CmdLEDGet_3_0_a3_1))
+           (portRef D (instanceRef CmdRWMaskSet_3_0_a3))
+           (portRef D (instanceRef CmdLEDSet_3_0_a8_0_a3))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0_0))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o3))
+           (portRef A (instanceRef RDout_i_i_a3_4))
+           (portRef A (instanceRef wb_adr_RNO_4))
+           (portRef A (instanceRef RWMask_RNO_4))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_0_1))
+           (portRef A (instanceRef RWBank_3_0_0_4))
+           (portRef B (instanceRef SUM0_i_o2_2))
+           (portRef B (instanceRef CmdSetRWBankFFLED_4_0_a8_0_a3))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1))
+          ))
+          (net N_212 (joined
+           (portRef Z (instanceRef SUM1_0_o3_0))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1))
+          ))
+          (net N_850 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_9))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o2))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1))
+          ))
+          (net (rename Din_c_0 "Din_c[0]") (joined
+           (portRef (member din_c 7))
+           (portRef A (instanceRef CmdLEDGet_3_0_a3_1))
+           (portRef B (instanceRef CmdBitbangMXO2_3_0_a3_1))
+           (portRef D (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0_0))
+           (portRef A (instanceRef RDout_i_0_i_a3_0))
+           (portRef A (instanceRef wb_we_7_iv_0_0_0_a3_1))
+           (portRef A (instanceRef LEDEN_RNO))
+           (portRef A (instanceRef SUM1_0_o3_0))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0))
+           (portRef A (instanceRef RWMask_RNO_0))
+           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a3_0_1))
+           (portRef B (instanceRef SUM0_i_a3_1))
+           (portRef A (instanceRef RWBank_3_0_0_0))
+           (portRef A (instanceRef CmdRWMaskSet_3_0_a3_0))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_2_2))
+          ))
+          (net N_243 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o3_0))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_2_2))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_o3 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o3))
+           (portRef A (instanceRef CmdBitbangMXO2_3_0_a3_1))
+           (portRef B (instanceRef CmdExecMXO2_3_0_a3_0))
+           (portRef D (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_2_2))
+          ))
+          (net (rename Ain_c_4 "Ain_c[4]") (joined
+           (portRef (member ain_c 3))
+           (portRef A (instanceRef RA_35_0_0_0_4))
+          ))
+          (net N_186 (joined
+           (portRef Z (instanceRef RA_35_0_0_o2_0_5))
+           (portRef C (instanceRef RA_35_0_0_1_0))
+           (portRef A (instanceRef RA_35_0_0_a3_0_2))
+           (portRef A (instanceRef RA_35_i_i_0_a3_0_1))
+           (portRef A (instanceRef RA_35_0_0_a3_5))
+           (portRef C (instanceRef RA_35_0_0_0_3))
+           (portRef C (instanceRef RA_35_0_0_0_0_7))
+           (portRef C (instanceRef RA_35_0_0_0_0_6))
+           (portRef C (instanceRef RA_35_0_0_0_4))
+          ))
+          (net (rename RA_4 "RA[4]") (joined
+           (portRef (member ra 7))
+           (portRef D (instanceRef RA_35_0_0_0_4))
+          ))
+          (net (rename Ain_c_6 "Ain_c[6]") (joined
+           (portRef (member ain_c 1))
+           (portRef A (instanceRef RA_35_0_0_0_0_6))
+          ))
+          (net (rename RA_6 "RA[6]") (joined
+           (portRef (member ra 5))
+           (portRef D (instanceRef RA_35_0_0_0_0_6))
+          ))
+          (net (rename Ain_c_7 "Ain_c[7]") (joined
+           (portRef (member ain_c 0))
+           (portRef A (instanceRef RA_35_0_0_0_0_7))
+          ))
+          (net (rename RA_7 "RA[7]") (joined
+           (portRef (member ra 4))
+           (portRef D (instanceRef RA_35_0_0_0_0_7))
+          ))
+          (net (rename Ain_c_3 "Ain_c[3]") (joined
+           (portRef (member ain_c 4))
+           (portRef A (instanceRef RA_35_0_0_0_3))
+          ))
+          (net (rename RA_3 "RA[3]") (joined
+           (portRef (member ra 8))
+           (portRef B (instanceRef RWSel_2_0_a3_0_a3))
+           (portRef D (instanceRef RA_35_0_0_0_3))
+          ))
+          (net N_781 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_9_7))
+           (portRef C (instanceRef wb_dati_7_0_0_o3_0_2))
+           (portRef D (instanceRef wb_adr_7_i_i_a3_4_0))
+           (portRef C (instanceRef wb_adr_7_i_i_1_0))
+           (portRef A (instanceRef wb_dati_7_0_0_0_0_7))
+           (portRef A (instanceRef wb_dati_7_0_0_0_1))
+          ))
+          (net (rename wb_dati_7_0_0_a3_0_0_1 "wb_dati_7_0_0_a3_0_0[1]") (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_a3_0_0_1))
+           (portRef D (instanceRef wb_dati_7_0_0_0_1))
+          ))
+          (net N_565 (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_o2_1_0))
+           (portRef B (instanceRef wb_adr_7_i_i_1_0))
+          ))
+          (net (rename wb_adr_7_i_i_a3_2_0_0 "wb_adr_7_i_i_a3_2_0[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_a3_2_0_0))
+           (portRef D (instanceRef wb_adr_7_i_i_1_0))
+          ))
+          (net (rename Din_c_7 "Din_c[7]") (joined
+           (portRef (member din_c 0))
+           (portRef B (instanceRef CmdLEDGet_3_0_a3_1))
+           (portRef C (instanceRef CmdRWMaskSet_3_0_a3))
+           (portRef C (instanceRef CmdLEDSet_3_0_a8_0_a3))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o3))
+           (portRef A (instanceRef RDout_i_0_i_a3_7))
+           (portRef A (instanceRef RWMask_RNO_7))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_5_1))
+           (portRef A (instanceRef wb_adr_RNO_7))
+           (portRef A (instanceRef RWBank_3_0_7))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a3_9))
+           (portRef C (instanceRef SUM0_i_m3_0_am))
+           (portRef C (instanceRef CmdSetRWBankFFLED_4_0_a8_0_a3))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R))
+          ))
+          (net N_361_i (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNIFNP81_2))
+           (portRef N_361_i)
+          ))
+          (net (rename RA_5 "RA[5]") (joined
+           (portRef (member ra 6))
+           (portRef B (instanceRef RA_35_0_0_a3_5))
+          ))
+          (net (rename RA_1 "RA[1]") (joined
+           (portRef (member ra 10))
+           (portRef B (instanceRef RA_35_i_i_0_a3_0_1))
+          ))
+          (net (rename RA_2 "RA[2]") (joined
+           (portRef (member ra 9))
+           (portRef B (instanceRef RA_35_0_0_a3_0_2))
+          ))
+          (net (rename FS_0 "FS[0]") (joined
+           (portRef (member fs 15))
+           (portRef A (instanceRef Ready3_0_a3_3))
+           (portRef A (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0))
+           (portRef A (instanceRef N_285_i))
+           (portRef A (instanceRef wb_cyc_stb_RNO_0))
+          ))
+          (net N_336 (joined
+           (portRef Z (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0))
+           (portRef B (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0_0))
+           (portRef C (instanceRef wb_cyc_stb_RNO_0))
+          ))
+          (net N_242 (joined
+           (portRef Z (instanceRef RA_35_0_0_o2_11))
+           (portRef A (instanceRef RA_35_0_0_9))
+           (portRef A (instanceRef RA_35_0_0_11))
+          ))
+          (net (rename RA_11 "RA[11]") (joined
+           (portRef (member ra 0))
+           (portRef C (instanceRef RA_35_0_0_11))
+          ))
+          (net (rename RWBank_4 "RWBank[4]") (joined
+           (portRef (member rwbank 3))
+           (portRef D (instanceRef RA_35_0_0_11))
+          ))
+          (net (rename RA_35_11 "RA_35[11]") (joined
+           (portRef Z (instanceRef RA_35_0_0_11))
+           (portRef (member ra_35 0))
+          ))
+          (net N_190 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o2))
+          ))
+          (net un1_CS_0_sqmuxa_0_0_a3_5_1 (joined
+           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a3_5_1))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o2))
+          ))
+          (net N_851 (joined
+           (portRef Z (instanceRef CmdExecMXO2_3_0_a3_0))
+           (portRef B (instanceRef CmdExecMXO2_3_0_a3))
+           (portRef D (instanceRef CmdExecMXO2_3_0_a3_0_RNIAJ811))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_1_0))
+          ))
+          (net N_817 (joined
+           (portRef Z (instanceRef CKE_7s2_0_0_a2_1))
+           (portRef B (instanceRef nRAS_s_i_0_a3_8))
+           (portRef A (instanceRef CKE_7_bm))
+           (portRef B (instanceRef CKE_7s2_0_0))
+          ))
+          (net CKE_7s2_0_0_0 (joined
+           (portRef Z (instanceRef CKE_7s2_0_0_0))
+           (portRef C (instanceRef CKE_7s2_0_0))
+          ))
+          (net (rename RA_9 "RA[9]") (joined
+           (portRef (member ra 2))
+           (portRef B (instanceRef RA_35_0_0_9))
+          ))
+          (net (rename RA_35_0_0_0_9 "RA_35_0_0_0[9]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0_9))
+           (portRef C (instanceRef RA_35_0_0_9))
+          ))
+          (net (rename RA_35_9 "RA_35[9]") (joined
+           (portRef Z (instanceRef RA_35_0_0_9))
+           (portRef (member ra_35 2))
+          ))
+          (net (rename Din_c_2 "Din_c[2]") (joined
+           (portRef (member din_c 5))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0_0))
+           (portRef A (instanceRef RDout_i_0_i_a3_2))
+           (portRef B (instanceRef SUM1_0_o3_0))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0))
+           (portRef A (instanceRef wb_adr_RNO_2))
+           (portRef A (instanceRef RWMask_RNO_2))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_0_1))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o3_0))
+           (portRef A (instanceRef RWBank_3_0_2))
+           (portRef B (instanceRef CmdLEDGet_3_0_a3))
+           (portRef B (instanceRef CmdRWMaskSet_3_0_a3_0))
+           (portRef A (instanceRef SUM0_i_o2_2))
+           (portRef B (instanceRef CmdBitbangMXO2_3_0_a3))
+          ))
+          (net N_800 (joined
+           (portRef Z (instanceRef CmdBitbangMXO2_3_0_a3_0))
+           (portRef C (instanceRef CmdLEDGet_3_0_a3_0))
+           (portRef A (instanceRef CmdExecMXO2_3_0_a3))
+           (portRef C (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3))
+           (portRef C (instanceRef CmdBitbangMXO2_3_0_a3))
+          ))
+          (net CmdBitbangMXO2_3_0_a3_1 (joined
+           (portRef Z (instanceRef CmdBitbangMXO2_3_0_a3_1))
+           (portRef D (instanceRef CmdBitbangMXO2_3_0_a3))
+          ))
+          (net CmdSetRWBankFFChip_3_0_a8_0_a3_0 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0_0))
+           (portRef D (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3))
+          ))
+          (net N_883 (joined
+           (portRef Z (instanceRef CmdRWMaskSet_3_0_a3_0))
+           (portRef A (instanceRef CmdRWMaskSet_3_0_a3))
+           (portRef A (instanceRef CmdLEDSet_3_0_a8_0_a3))
+           (portRef D (instanceRef CmdSetRWBankFFLED_4_0_a8_0_a3))
+          ))
+          (net CmdSetRWBankFFLED_4 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFLED_4_0_a8_0_a3))
+           (portRef CmdSetRWBankFFLED_4)
+          ))
+          (net N_885 (joined
+           (portRef Z (instanceRef wb_we_7_iv_0_0_0_a3_7))
+           (portRef A (instanceRef un1_RWMask_0_sqmuxa_1_i_0_a3_0_0_0))
+           (portRef C (instanceRef wb_we_RNO_2))
+           (portRef A (instanceRef Ready3_0_a3))
+          ))
+          (net Ready3_0_a3_3 (joined
+           (portRef Z (instanceRef Ready3_0_a3_3))
+           (portRef B (instanceRef Ready3_0_a3))
+          ))
+          (net Ready3_0_a3_4 (joined
+           (portRef Z (instanceRef Ready3_0_a3_4))
+           (portRef C (instanceRef Ready3_0_a3))
+          ))
+          (net Ready3_0_a3_5 (joined
+           (portRef Z (instanceRef Ready3_0_a3_5))
+           (portRef D (instanceRef Ready3_0_a3))
+          ))
+          (net Ready3 (joined
+           (portRef Z (instanceRef Ready3_0_a3))
+           (portRef Ready3)
+          ))
+          (net N_184 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_o2_7))
+           (portRef A (instanceRef wb_dati_7_0_0_o3_0_2))
+           (portRef B (instanceRef wb_we_RNO_3))
+           (portRef A (instanceRef wb_adr_RNO_1_1))
+          ))
+          (net N_204 (joined
+           (portRef Z (instanceRef wb_adr_RNO_3_1))
+           (portRef B (instanceRef wb_adr_RNO_1_1))
+          ))
+          (net wb_adr_7_5_41_a3_3_0 (joined
+           (portRef Z (instanceRef wb_adr_RNO_4_1))
+           (portRef D (instanceRef wb_adr_RNO_1_1))
+          ))
+          (net wb_we_7_iv_0_0_3_0_0 (joined
+           (portRef Z (instanceRef wb_we_RNO_3))
+           (portRef D (instanceRef wb_we_RNO_2))
+          ))
+          (net N_595 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_o2_0_3))
+           (portRef B (instanceRef wb_dati_7_0_0_0_a3_0_3))
+          ))
+          (net N_254 (joined
+           (portRef Z (instanceRef nCAS_s_i_0_m2))
+           (portRef B (instanceRef nCAS_s_i_0_a3_0))
+          ))
+          (net N_338 (joined
+           (portRef Z (instanceRef SUM0_i_m3_0))
+           (portRef C (instanceRef SUM0_i_o2_2))
+          ))
+          (net (rename N_369_i_1z "N_369_i") (joined
+           (portRef Z (instanceRef N_369_i))
+           (portRef N_369_i_1z)
+          ))
+          (net N_271 (joined
+           (portRef Z (instanceRef S_r_i_0_o2_0_1))
+           (portRef B (instanceRef S_s_0_0_0))
+           (portRef C (instanceRef S_r_i_0_o2_0_RNI36E21_1))
+          ))
+          (net N_362_i (joined
+           (portRef Z (instanceRef S_r_i_0_o2_0_RNI36E21_1))
+           (portRef N_362_i)
+          ))
+          (net (rename RA_10 "RA[10]") (joined
+           (portRef (member ra 1))
+           (portRef C (instanceRef RA_35_2_0_a3_10))
+          ))
+          (net (rename FS_5 "FS[5]") (joined
+           (portRef (member fs 10))
+           (portRef B (instanceRef Ready3_0_a3_3))
+           (portRef B (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0))
+           (portRef B (instanceRef RA_35_i_i_0_a3_1))
+          ))
+          (net (rename FS_6 "FS[6]") (joined
+           (portRef (member fs 9))
+           (portRef C (instanceRef Ready3_0_a3_3))
+           (portRef D (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0))
+           (portRef B (instanceRef RA_35_0_0_a3_2))
+          ))
+          (net N_847 (joined
+           (portRef Z (instanceRef CmdLEDGet_3_0_a3_0))
+           (portRef C (instanceRef CmdLEDGet_3_0_a3))
+           (portRef C (instanceRef CmdRWMaskSet_3_0_a3_0))
+          ))
+          (net (rename RWBank_6 "RWBank[6]") (joined
+           (portRef (member rwbank 1))
+           (portRef C (instanceRef BA_4_1))
+          ))
+          (net (rename BA_4_1 "BA_4[1]") (joined
+           (portRef Z (instanceRef BA_4_1))
+           (portRef (member ba_4 0))
+          ))
+          (net (rename RWBank_5 "RWBank[5]") (joined
+           (portRef (member rwbank 2))
+           (portRef C (instanceRef BA_4_0))
+          ))
+          (net (rename BA_4_0 "BA_4[0]") (joined
+           (portRef Z (instanceRef BA_4_0))
+           (portRef (member ba_4 1))
+          ))
+          (net wb_reqc_1 (joined
+           (portRef Z (instanceRef wb_reqc_1_0))
+           (portRef D (instanceRef wb_req_RNO))
+          ))
+          (net N_126 (joined
+           (portRef Z (instanceRef un1_CKE75_0_i_0))
+           (portRef N_126)
+          ))
+          (net N_226 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_o2))
+           (portRef B (instanceRef nRAS_s_i_0_a3_0))
+          ))
+          (net (rename S_s_0_0_0 "S_s_0_0[0]") (joined
+           (portRef Z (instanceRef S_s_0_0_0))
+           (portRef S_s_0_0_0)
+          ))
+          (net CmdLEDGet_3_0_a3_1 (joined
+           (portRef Z (instanceRef CmdLEDGet_3_0_a3_1))
+           (portRef D (instanceRef CmdLEDGet_3_0_a3))
+          ))
+          (net CmdLEDGet_3 (joined
+           (portRef Z (instanceRef CmdLEDGet_3_0_a3))
+           (portRef CmdLEDGet_3)
+          ))
+          (net N_221 (joined
+           (portRef Z (instanceRef un2_S_2_i_0_0_o3))
+           (portRef A (instanceRef CKE_7s2_0_0_0))
+           (portRef A (instanceRef un2_S_2_i_0_0_o3_RNIHFHN3))
+          ))
+          (net N_698 (joined
+           (portRef Z (instanceRef RA_35_2_30_a3_2))
+           (portRef B (instanceRef un2_S_2_i_0_0_o3_RNIHFHN3))
+          ))
+          (net (rename RA_8 "RA[8]") (joined
+           (portRef (member ra 3))
+           (portRef D (instanceRef un2_S_2_i_0_0_o3_RNIHFHN3))
+          ))
+          (net (rename un2_S_2_i_0_0_o3_RNIHFHN3_1z "un2_S_2_i_0_0_o3_RNIHFHN3") (joined
+           (portRef Z (instanceRef un2_S_2_i_0_0_o3_RNIHFHN3))
+           (portRef un2_S_2_i_0_0_o3_RNIHFHN3_1z)
+          ))
+          (net (rename RWBank_2 "RWBank[2]") (joined
+           (portRef (member rwbank 5))
+           (portRef D (instanceRef RA_35_0_0_0_9))
+          ))
+          (net N_625 (joined
+           (portRef Z (instanceRef RA_35_2_0_a3_0_10))
+           (portRef A (instanceRef RA_35_2_0_0_10))
+          ))
+          (net (rename RWBankZ0Z_3 "RWBank[3]") (joined
+           (portRef (member rwbank 4))
+           (portRef C (instanceRef RA_35_2_0_0_10))
+          ))
+          (net (rename Din_c_3 "Din_c[3]") (joined
+           (portRef (member din_c 4))
+           (portRef C (instanceRef SUM0_i_m3_0_bm))
+           (portRef D (instanceRef CmdBitbangMXO2_3_0_a3_1))
+           (portRef D (instanceRef CmdExecMXO2_3_0_a3_0))
+           (portRef A (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3))
+           (portRef A (instanceRef N_263_i))
+           (portRef A (instanceRef wb_adr_RNO_3))
+           (portRef A (instanceRef RWMask_RNO_3))
+           (portRef A (instanceRef CmdLEDGet_3_0_a3_0))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o3_0))
+           (portRef A (instanceRef RWBank_3_0_3))
+           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a3_9))
+           (portRef A (instanceRef SUM0_i_m3_0_am))
+          ))
+          (net (rename Din_c_5 "Din_c[5]") (joined
+           (portRef (member din_c 2))
+           (portRef B (instanceRef SUM0_i_m3_0_bm))
+           (portRef C (instanceRef CmdBitbangMXO2_3_0_a3_1))
+           (portRef C (instanceRef CmdExecMXO2_3_0_a3_0))
+           (portRef B (instanceRef CmdSetRWBankFFChip_3_0_a8_0_o3))
+           (portRef A (instanceRef RDout_i_0_i_a3_5))
+           (portRef A (instanceRef wb_adr_RNO_5))
+           (portRef A (instanceRef RWMask_RNO_5))
+           (portRef B (instanceRef CmdLEDGet_3_0_a3_0))
+           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o3_0))
+           (portRef A (instanceRef RWBank_3_0_5))
+           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a3_9))
+           (portRef B (instanceRef SUM0_i_m3_0_am))
+          ))
+          (net SUM0_i_m3_0_am (joined
+           (portRef Z (instanceRef SUM0_i_m3_0_am))
+           (portRef BLUT (instanceRef SUM0_i_m3_0))
+          ))
+          (net SUM0_i_m3_0_bm (joined
+           (portRef Z (instanceRef SUM0_i_m3_0_bm))
+           (portRef ALUT (instanceRef SUM0_i_m3_0))
+          ))
+          (net (rename RWBank_0 "RWBank[0]") (joined
+           (portRef (member rwbank 7))
+           (portRef B (instanceRef DQMH_4_iv_0_0_i_i_a3_0_a3))
+           (portRef B (instanceRef N_507_i))
+          ))
+          (net (rename N_507_i_1z "N_507_i") (joined
+           (portRef Z (instanceRef N_507_i))
+           (portRef N_507_i_1z)
+          ))
+          (net (rename N_368_i_1z "N_368_i") (joined
+           (portRef Z (instanceRef N_368_i))
+           (portRef N_368_i_1z)
+          ))
+          (net (rename N_360_i_1z "N_360_i") (joined
+           (portRef Z (instanceRef N_360_i))
+           (portRef N_360_i_1z)
+          ))
+          (net nEN80_c (joined
+           (portRef nEN80_c)
+           (portRef B (instanceRef nRAS_s_i_0_o2))
+           (portRef C (instanceRef nRAS_s_i_0_a3_5))
+           (portRef D (instanceRef CKE_7s2_0_0_0))
+           (portRef C (instanceRef nRAS_s_i_0_a3_1))
+           (portRef B (instanceRef RDOE_i))
+           (portRef C (instanceRef LEDEN_RNI6G6M))
+           (portRef B (instanceRef un1_nDOE_i))
+           (portRef D (instanceRef RA_35_2_0_a3_0_10))
+          ))
+          (net N_188 (joined
+           (portRef Z (instanceRef RWBank_3_0_0_o3_0))
+           (portRef B (instanceRef RWBank_3_0_7))
+           (portRef B (instanceRef RWBank_3_0_6))
+           (portRef B (instanceRef RWBank_3_0_5))
+           (portRef B (instanceRef RWBank_3_0_3))
+           (portRef B (instanceRef RWBank_3_0_2))
+           (portRef B (instanceRef RWBank_3_0_1))
+           (portRef B (instanceRef RWBank_3_0_0_4))
+           (portRef B (instanceRef RWBank_3_0_0_0))
+          ))
+          (net (rename RWBank_3_0 "RWBank_3[0]") (joined
+           (portRef Z (instanceRef RWBank_3_0_0_0))
+           (portRef (member rwbank_3 7))
+          ))
+          (net (rename RWBank_3_4 "RWBank_3[4]") (joined
+           (portRef Z (instanceRef RWBank_3_0_0_4))
+           (portRef (member rwbank_3 3))
+          ))
+          (net (rename RWBank_3_1 "RWBank_3[1]") (joined
+           (portRef Z (instanceRef RWBank_3_0_1))
+           (portRef (member rwbank_3 6))
+          ))
+          (net (rename RWBank_3_2 "RWBank_3[2]") (joined
+           (portRef Z (instanceRef RWBank_3_0_2))
+           (portRef (member rwbank_3 5))
+          ))
+          (net (rename RWBank_3_3 "RWBank_3[3]") (joined
+           (portRef Z (instanceRef RWBank_3_0_3))
+           (portRef (member rwbank_3 4))
+          ))
+          (net (rename RWBank_3_5 "RWBank_3[5]") (joined
+           (portRef Z (instanceRef RWBank_3_0_5))
+           (portRef (member rwbank_3 2))
+          ))
+          (net (rename RWBank_3_6 "RWBank_3[6]") (joined
+           (portRef Z (instanceRef RWBank_3_0_6))
+           (portRef (member rwbank_3 1))
+          ))
+          (net (rename RWBank_3_7 "RWBank_3[7]") (joined
+           (portRef Z (instanceRef RWBank_3_0_7))
+           (portRef (member rwbank_3 0))
+          ))
+          (net N_553 (joined
+           (portRef Z (instanceRef wb_dati_7_0_0_0_o2_3))
+           (portRef B (instanceRef wb_dati_7_0_0_a3_2_3))
+          ))
+          (net (rename RC_3_2 "RC_3[2]") (joined
+           (portRef Z (instanceRef RC_3_0_0_2))
+           (portRef (member rc_3 0))
+          ))
+          (net DOEEN (joined
+           (portRef DOEEN)
+           (portRef A (instanceRef un1_nDOE_i))
+          ))
+          (net nDOE_c (joined
+           (portRef Z (instanceRef un1_nDOE_i))
+           (portRef nDOE_c)
+          ))
+          (net Ready (joined
+           (portRef Ready)
+           (portRef B (instanceRef RDout_i_0_i_a3_0))
+           (portRef B (instanceRef RDout_i_0_i_a3_1))
+           (portRef B (instanceRef RDout_i_0_i_a3_2))
+           (portRef B (instanceRef RDout_i_0_i_a3_5))
+           (portRef B (instanceRef RDout_i_0_i_a3_6))
+           (portRef B (instanceRef RDout_i_0_i_a3_7))
+           (portRef B (instanceRef RDout_i_i_a3_4))
+           (portRef B (instanceRef N_263_i))
+           (portRef A (instanceRef RDOE_i))
+           (portRef B (instanceRef LEDEN_RNI6G6M))
+          ))
+          (net LED_c (joined
+           (portRef Z (instanceRef LEDEN_RNI6G6M))
+           (portRef LED_c)
+          ))
+          (net (rename RDOE_i_1z "RDOE_i") (joined
+           (portRef Z (instanceRef RDOE_i))
+           (portRef RDOE_i_1z)
+          ))
+          (net N_866 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_6))
+           (portRef C (instanceRef nRAS_s_i_0_a3_0_RNIIR094))
+           (portRef A (instanceRef nRAS_s_i_0_a3_1))
+          ))
+          (net N_241_i (joined
+           (portRef Z (instanceRef wb_adr_RNO_2_1))
+           (portRef C (instanceRef wb_adr_RNO_0_1))
+          ))
+          (net (rename RA_0 "RA[0]") (joined
+           (portRef (member ra 11))
+           (portRef D (instanceRef RA_35_0_0_1_0))
+           (portRef A (instanceRef RWSel_2_0_a3_0_a3))
+          ))
+          (net nC07X_c (joined
+           (portRef nC07X_c)
+           (portRef C (instanceRef RWSel_2_0_a3_0_a3))
+          ))
+          (net RWSel_2 (joined
+           (portRef Z (instanceRef RWSel_2_0_a3_0_a3))
+           (portRef RWSel_2)
+          ))
+          (net (rename FS_7 "FS[7]") (joined
+           (portRef (member fs 8))
+           (portRef A (instanceRef RA_35_0_0_0))
+           (portRef D (instanceRef Ready3_0_a3_3))
+           (portRef C (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0))
+          ))
+          (net (rename un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0]") (joined
+           (portRef Z (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0))
+           (portRef D (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_0))
+          ))
+          (net N_250 (joined
+           (portRef Z (instanceRef nRAS_s_i_0_m3))
+           (portRef C (instanceRef nRAS_s_i_0_o2_0))
+          ))
+          (net (rename wb_dato_0 "wb_dato[0]") (joined
+           (portRef (member wb_dato 7) (instanceRef ufmefb))
+           (portRef C (instanceRef LEDEN_RNO))
+           (portRef C (instanceRef RWMask_RNO_0))
+          ))
+          (net (rename wb_dato_1 "wb_dato[1]") (joined
+           (portRef (member wb_dato 6) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_1))
+          ))
+          (net (rename wb_dato_2 "wb_dato[2]") (joined
+           (portRef (member wb_dato 5) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_2))
+          ))
+          (net (rename wb_dato_3 "wb_dato[3]") (joined
+           (portRef (member wb_dato 4) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_3))
+          ))
+          (net (rename wb_dato_4 "wb_dato[4]") (joined
+           (portRef (member wb_dato 3) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_4))
+          ))
+          (net (rename wb_dato_5 "wb_dato[5]") (joined
+           (portRef (member wb_dato 2) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_5))
+          ))
+          (net (rename wb_dato_6 "wb_dato[6]") (joined
+           (portRef (member wb_dato 1) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_6))
+          ))
+          (net (rename FS_2 "FS[2]") (joined
+           (portRef (member fs 13))
+           (portRef B (instanceRef nRWE_s_i_0_63_1))
+           (portRef B (instanceRef nRAS_s_i_0_m3))
+           (portRef A (instanceRef Ready3_0_a3_4))
+           (portRef B (instanceRef un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3_0))
+           (portRef B (instanceRef nCAS_s_i_0_m2))
+          ))
+          (net N_508 (joined
+           (portRef Z (instanceRef DQMH_4_iv_0_0_i_i_a3_0_a3))
+           (portRef N_508)
+          ))
+          (net N_814 (joined
+           (portRef Z (instanceRef CmdSetRWBankFFChip_3_0_a8_0_a3_0))
+           (portRef A (instanceRef CmdExecMXO2_3_0_a3_0))
+          ))
+          (net (rename N_263_i_1z "N_263_i") (joined
+           (portRef Z (instanceRef N_263_i))
+           (portRef N_263_i_1z)
+          ))
+          (net (rename RWBank_7 "RWBank[7]") (joined
+           (portRef (member rwbank 0))
+           (portRef A (instanceRef RA_35_2_30_a3_2))
+          ))
+          (net (rename un9_VOEEN_0_a2_0_a3_0_a3_1z "un9_VOEEN_0_a2_0_a3_0_a3") (joined
+           (portRef Z (instanceRef un9_VOEEN_0_a2_0_a3_0_a3))
+           (portRef un9_VOEEN_0_a2_0_a3_0_a3_1z)
+          ))
+          (net Vout3 (joined
+           (portRef Z (instanceRef Vout3_0_a3_0_a3_0_a3))
+           (portRef Vout3)
+          ))
+          (net CmdLEDGet (joined
+           (portRef CmdLEDGet)
+           (portRef A (instanceRef RWBank_3_0_0_o3_0))
+          ))
+          (net CmdSetRWBankFFLED (joined
+           (portRef CmdSetRWBankFFLED)
+           (portRef C (instanceRef RWBank_3_0_0_o3_0))
+          ))
+          (net (rename wb_dato_7 "wb_dato[7]") (joined
+           (portRef (member wb_dato 0) (instanceRef ufmefb))
+           (portRef C (instanceRef RWMask_RNO_7))
+          ))
+          (net N_648 (joined
+           (portRef Z (instanceRef RDout_i_i_a3_4))
+           (portRef N_648)
+          ))
+          (net N_662 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_7))
+           (portRef N_662)
+          ))
+          (net N_663 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_6))
+           (portRef N_663)
+          ))
+          (net N_664 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_5))
+           (portRef N_664)
+          ))
+          (net N_665 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_2))
+           (portRef N_665)
+          ))
+          (net N_666 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_1))
+           (portRef N_666)
+          ))
+          (net N_667 (joined
+           (portRef Z (instanceRef RDout_i_0_i_a3_0))
+           (portRef N_667)
+          ))
+          (net (rename CmdTout_3_0 "CmdTout_3[0]") (joined
+           (portRef Z (instanceRef CmdTout_3_0_a3_0_a3_0))
+           (portRef CmdTout_3_0)
+          ))
+          (net N_821 (joined
+           (portRef Z (instanceRef RC_3_0_0_a3_1_1))
+           (portRef B (instanceRef CKE_7_bm))
+          ))
+          (net nRWE_s_i_0_63_1 (joined
+           (portRef Z (instanceRef nRWE_s_i_0_63_1))
+           (portRef D (instanceRef S_r_i_0_o2_RNI62C53_1))
+          ))
+          (net (rename S_r_i_0_o2_RNI62C53_1 "S_r_i_0_o2_RNI62C53[1]") (joined
+           (portRef Z (instanceRef S_r_i_0_o2_RNI62C53_1))
+           (portRef B (instanceRef nRAS_s_i_0_a3_0_RNIIR094))
+          ))
+          (net (rename wb_adr_7_i_i_3_1_0 "wb_adr_7_i_i_3_1[0]") (joined
+           (portRef Z (instanceRef wb_adr_7_i_i_3_1_0))
+           (portRef D (instanceRef wb_adr_7_i_i_3_0))
+          ))
+          (net (rename Ain_c_0 "Ain_c[0]") (joined
+           (portRef (member ain_c 7))
+           (portRef A (instanceRef RA_35_0_0_1_0))
+          ))
+          (net (rename RA_35_0_0_1_0 "RA_35_0_0_1[0]") (joined
+           (portRef Z (instanceRef RA_35_0_0_1_0))
+           (portRef D (instanceRef RA_35_0_0_0))
+          ))
+          (net (rename RA_35_0 "RA_35[0]") (joined
+           (portRef Z (instanceRef RA_35_0_0_0))
+           (portRef (member ra_35 11))
+          ))
+          (net CmdLEDSet_3 (joined
+           (portRef Z (instanceRef CmdLEDSet_3_0_a8_0_a3))
+           (portRef CmdLEDSet_3)
+          ))
+          (net CmdRWMaskSet_3 (joined
+           (portRef Z (instanceRef CmdRWMaskSet_3_0_a3))
+           (portRef CmdRWMaskSet_3)
+          ))
+          (net N_359_i (joined
+           (portRef Z (instanceRef nRAS_s_i_0_a3_0_RNIIR094))
+           (portRef N_359_i)
+          ))
+         )
+        (property orig_inst_of (string "RAM2E_UFM"))
+       )
+    )
+    (cell RAM2E (cellType GENERIC)
+       (view verilog (viewType NETLIST)
+         (interface
+           (port C14M (direction INPUT))
+           (port PHI1 (direction INPUT))
+           (port LED (direction OUTPUT))
+           (port nWE (direction INPUT))
+           (port nWE80 (direction INPUT))
+           (port nEN80 (direction INPUT))
+           (port nC07X (direction INPUT))
+           (port (array (rename ain "Ain[7:0]") 8) (direction INPUT))
+           (port (array (rename din "Din[7:0]") 8) (direction INPUT))
+           (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT))
+           (port nDOE (direction OUTPUT))
+           (port (array (rename vout "Vout[7:0]") 8) (direction OUTPUT))
+           (port nVOE (direction OUTPUT))
+           (port CKEout (direction OUTPUT))
+           (port nCSout (direction OUTPUT))
+           (port nRASout (direction OUTPUT))
+           (port nCASout (direction OUTPUT))
+           (port nRWEout (direction OUTPUT))
+           (port (array (rename ba "BA[1:0]") 2) (direction OUTPUT))
+           (port (array (rename raout "RAout[11:0]") 12) (direction OUTPUT))
+           (port DQML (direction OUTPUT))
+           (port DQMH (direction OUTPUT))
+           (port (array (rename rd "RD[7:0]") 8) (direction INOUT))
+         )
+         (contents
+          (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT)))          )
+          (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT)))          )
+          (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
+          )
+          (instance DOEEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !A+C (!B !A))"))
+          )
+          (instance VOEEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!C !A+C (!B !A))"))
+          )
+          (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(B+A)"))
+          )
+          (instance (rename nCASout_CN "nCASout.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT)))          )
+          (instance PHI1r_0io (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance nRWEout_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance nRASout_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance nCASout_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_0 "Vout_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_1 "Vout_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_2 "Vout_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_3 "Vout_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_4 "Vout_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_5 "Vout_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_6 "Vout_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename Vout_0io_7 "Vout_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_0 "RAout_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_1 "RAout_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_2 "RAout_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_3 "RAout_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_4 "RAout_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_5 "RAout_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_6 "RAout_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_7 "RAout_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_8 "RAout_0io[8]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_9 "RAout_0io[9]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_10 "RAout_0io[10]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename RAout_0io_11 "RAout_0io[11]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance DQML_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance DQMH_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance CKEout_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename BA_0io_0 "BA_0io[0]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance (rename BA_0io_1 "BA_0io[1]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT)))
+           (property IOB (string "FALSE"))
+          )
+          (instance nRWE (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nRAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance nCAS (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
+          (instance VOEEN (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
+          )
+          (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename S_2 "S[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance (rename S_3 "S[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          )
+          (instance RWSel (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
           (instance (rename RWBank_0 "RWBank[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
           (instance (rename RWBank_1 "RWBank[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
@@ -1053,11 +4193,35 @@
           )
           (instance (rename RWBank_7 "RWBank[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
+          (instance (rename RC_0 "RC[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RC_1 "RC[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RC_2 "RC[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
           (instance (rename RA_0 "RA[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
+          (instance (rename RA_1 "RA[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_2 "RA[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
           (instance (rename RA_3 "RA[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
-          (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          (instance (rename RA_4 "RA[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_5 "RA[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_6 "RA[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_7 "RA[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_8 "RA[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_9 "RA[9]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_10 "RA[10]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
+          )
+          (instance (rename RA_11 "RA[11]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
           (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
           )
@@ -1091,7 +4255,7 @@
           )
           (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
           )
-          (instance DOEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT)))
+          (instance DOEEN (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
           )
           (instance (rename CmdTout_0 "CmdTout[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
@@ -1099,8 +4263,6 @@
           )
           (instance (rename CmdTout_2 "CmdTout[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
-          (instance CmdSetRWBankFFMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
           (instance CmdSetRWBankFFLED (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
           (instance CmdRWMaskSet (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
@@ -1109,18 +4271,14 @@
           )
           (instance CmdLEDGet (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
           )
-          (instance CmdExecMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
-          (instance CmdBitbangMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT)))
-          )
           (instance (rename CS_0 "CS[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
           )
           (instance (rename CS_1 "CS[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
           )
           (instance (rename CS_2 "CS[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT)))
           )
-          (instance DQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance DQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance CKE (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT)))
+          )
           (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
           (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
           (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
@@ -1129,25 +4287,27 @@
           (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
           (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
           (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance DQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance DQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_11 "RAout_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_10 "RAout_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_9 "RAout_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_8 "RAout_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_7 "RAout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_6 "RAout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_5 "RAout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_4 "RAout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_3 "RAout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_2 "RAout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_1 "RAout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance (rename RAout_pad_0 "RAout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance (rename BA_pad_1 "BA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance (rename BA_pad_0 "BA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance nCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
-          (instance CKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nRWEout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nCASout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nRASout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance nCSout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
+          (instance CKEout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance nVOE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance (rename Vout_pad_7 "Vout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance (rename Vout_pad_6 "Vout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
@@ -1184,573 +4344,17 @@
           (instance (rename Ain_pad_0 "Ain_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
           (instance nC07X_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
           (instance nEN80_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance nWE80_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
           (instance nWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
           (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT)))          )
           (instance PHI1_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
           )
           (instance C14M_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT)))          )
-          (instance un1_CS_0_sqmuxa_0_0_2_RNIQS7F (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C !B)+D (!C (!B !A)))"))
-          )
-          (instance nCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C+(!B+A))+D A)"))
-          )
-          (instance nRWE_r_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C+(!B+A)))"))
-          )
-          (instance nCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance nRAS_2_iv_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A)+C !A)"))
-          )
-          (instance (rename wb_dati_7_0_5 "wb_dati_7_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C A+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_2 "wb_dati_7_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C A+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_7 "wb_dati_7_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance (rename wb_adr_7_0_0 "wb_adr_7_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C B+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_6 "wb_dati_7_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B A))"))
-          )
-          (instance (rename wb_dati_7_0_4 "wb_dati_7_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_3 "wb_dati_7_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C+(B+A))"))
-          )
-          (instance (rename RA_42_0_10 "RA_42_0[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C B+C (B+!A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D C+D (C+(B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance (rename CS_RNO_2 "CS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C (!B A+B !A))"))
-          )
-          (instance nCS_6_u_i_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_1 "wb_dati_7_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C A+C (B+A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D C+D (C+(B A)))"))
-          )
-          (instance (rename wb_dati_7_0_1_6 "wb_dati_7_0_1[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B+A)+D (C+(B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_2_3 "wb_dati_7_0_2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A))+D (B !A))"))
-          )
-          (instance (rename wb_adr_7_0_4_0 "wb_adr_7_0_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance (rename CS_RNO_0 "CS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A+B A)+C A)"))
-          )
-          (instance CmdSetRWBankFFLED_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance CmdExecMXO2_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D (C B))"))
-          )
-          (instance CmdRWMaskSet_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D (C B))"))
-          )
-          (instance CmdBitbangMXO2_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D (C B))"))
-          )
-          (instance CmdLEDSet_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename un1_LEDEN_0_sqmuxa_1_i_0_0 "un1_LEDEN_0_sqmuxa_1_i_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
-          )
-          (instance wb_cyc_stb_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C (B+A))"))
-          )
-          (instance (rename un1_RWMask_0_sqmuxa_1_i_0_0 "un1_RWMask_0_sqmuxa_1_i_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
-          )
-          (instance (rename wb_dati_7_0_0 "wb_dati_7_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
-          )
-          (instance (rename wb_adr_7_0_a2_0_0 "wb_adr_7_0_a2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B+A)+C B))"))
-          )
-          (instance (rename wb_dati_7_0_a2_4 "wb_dati_7_0_a2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A))+D (B !A))"))
-          )
-          (instance (rename wb_dati_7_0_RNO_7 "wb_dati_7_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D C)"))
-          )
-          (instance (rename wb_dati_7_0_a2_3_4 "wb_dati_7_0_a2_3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_7 "wb_dati_7_0_a2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)+C (B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B !A))"))
-          )
-          (instance (rename wb_dati_7_0_o2_0_2 "wb_dati_7_0_o2_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C A+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_0_3 "wb_dati_7_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
-          )
-          (instance (rename wb_dati_7_0_0_4 "wb_dati_7_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B A)+D (C+(B A)))"))
-          )
-          (instance DQML_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B+!A)+D (!C !B+C (!B+!A)))"))
-          )
-          (instance CmdSetRWBankFFMXO2_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D (C B))"))
-          )
-          (instance CmdSetRWBankFFLED_4_u_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance CmdLEDGet_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D (C B))"))
-          )
-          (instance (rename wb_dati_7_0_a2_5_4 "wb_dati_7_0_a2_5[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B A))"))
-          )
-          (instance nCS_6_u_i_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance CKE_6_iv_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C A+C (B+A))+D A)"))
-          )
-          (instance wb_we_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C (B !A)))"))
-          )
-          (instance (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C B+C (B+A)))"))
-          )
-          (instance (rename wb_adr_7_0_a2_2_0 "wb_adr_7_0_a2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_6 "wb_dati_7_0_a2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A+B A)))"))
-          )
-          (instance (rename un1_LEDEN13_2_i_0_0 "un1_LEDEN13_2_i_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B+A)+D (C+(B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_1_7 "wb_dati_7_0_a2_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A)))"))
-          )
-          (instance (rename wb_adr_7_0_a2_1_0 "wb_adr_7_0_a2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B+!A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_1 "wb_dati_7_0_a2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance Ready_0_sqmuxa_0_a2_6_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance CmdLEDSet_4_u_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_4_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance (rename wb_dati_7_0_0_1 "wb_dati_7_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_0_7 "wb_dati_7_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))"))
-          )
-          (instance (rename wb_adr_7_0_0_0 "wb_adr_7_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))"))
-          )
-          (instance (rename wb_adr_7_0_1_0 "wb_adr_7_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A))+D B)"))
-          )
-          (instance (rename S_RNO_2 "S_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)+C (B !A))+D (!C (!B !A)+C !A))"))
-          )
-          (instance (rename un1_LEDEN13_2_i_a2_0_0 "un1_LEDEN13_2_i_a2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D (C !B))"))
-          )
-          (instance (rename S_RNII9DO1_1_1 "S_RNII9DO1_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A+B A)+C (B A))+D (!C (!B A)+C B))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B !A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_1_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance (rename wb_adr_RNO_1_1 "wb_adr_RNO_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A))+D (!C A+C (!B A)))"))
-          )
-          (instance wb_we_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
-          )
-          (instance wb_we_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B+A)))"))
-          )
-          (instance CmdBitbangMXO2_RNI8CSO1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B+A)))"))
-          )
-          (instance (rename RA_0io_RNO_8 "RA_0io_RNO[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (B !A)+D (C !A))"))
-          )
-          (instance (rename RA_0io_RNO_9 "RA_0io_RNO[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C !B+C (!B A)))"))
-          )
-          (instance (rename S_RNO_1 "S_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)+C !A))"))
-          )
-          (instance (rename S_RNO_3 "S_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D !A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C (!B A)))"))
-          )
-          (instance CmdSetRWBankFFLED_4_u_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance wb_req_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B !A)))"))
-          )
-          (instance CKE_6_iv_i_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B A)))"))
-          )
-          (instance (rename un1_LEDEN13_2_i_o2_2_0 "un1_LEDEN13_2_i_o2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(B+A)))"))
-          )
-          (instance (rename S_s_0_0 "S_s_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(!C A+C (!B+A)))"))
-          )
-          (instance (rename CS_RNO_0_2 "CS_RNO_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B !A)))"))
-          )
-          (instance CKE_6_iv_i_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C B+C (!B A))+D (!C+(!B A)))"))
-          )
-          (instance Ready_0_sqmuxa_0_a2_6_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance nCS_6_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)+C (!B !A))+D (!C (!B A)))"))
-          )
-          (instance (rename wb_adr_7_0_a2_0_0_0 "wb_adr_7_0_a2_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D (!C (!B A)+C !B))"))
-          )
-          (instance (rename CmdTout_RNO_1 "CmdTout_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A+B !A))"))
-          )
-          (instance (rename RA_RNO_3 "RA_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_0io_RNO_4 "RA_0io_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_0io_RNO_6 "RA_0io_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_0io_RNO_7 "RA_0io_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_RNO_0 "RA_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_0io_RNO_1 "RA_0io_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance (rename RA_0io_RNO_2 "RA_0io_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B !A))"))
-          )
-          (instance (rename RWBank_5_0_4 "RWBank_5_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C+(!B+!A)))"))
-          )
-          (instance nCAS_s_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance (rename wb_dati_7_0_o2_1 "wb_dati_7_0_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A))+D (!C (B A)))"))
-          )
-          (instance (rename RWBank_5_0_2 "RWBank_5_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename RWBank_5_0_3 "RWBank_5_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename RWBank_5_0_5 "RWBank_5_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename RWBank_5_0_6 "RWBank_5_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename RWBank_5_0_0_7 "RWBank_5_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C B+C (B+A))"))
-          )
-          (instance (rename RWBank_5_0_1 "RWBank_5_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance (rename RWBank_5_0_0 "RWBank_5_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B+A)+C B)"))
-          )
-          (instance nRWE_r_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!B A)+D (!C (!B A)+C !B))"))
-          )
-          (instance nDOE_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C+(B+!A))"))
-          )
-          (instance (rename RA_0io_RNO_11 "RA_0io_RNO[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
-          )
-          (instance RWSel_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)))"))
-          )
-          (instance wb_we_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
-          )
-          (instance nCS_6_u_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B !A)))"))
-          )
-          (instance (rename wb_adr_RNO_0_1 "wb_adr_RNO_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_15 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (!B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (!B A)))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_1_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B !A)))"))
-          )
-          (instance (rename S_s_0_1_0 "S_s_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C !A)+D (!C !A+C (B+!A)))"))
-          )
-          (instance CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B !A))"))
-          )
-          (instance CmdLEDGet_4_u_0_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_2_0_1 "wb_dati_7_0_a2_2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance (rename un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0 "un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (!B !A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_1_0_0 "wb_dati_7_0_a2_1_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B A)+C (!B A)))"))
-          )
-          (instance (rename RWMask_RNO_6 "RWMask_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_5 "RWMask_RNO[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_4 "RWMask_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_3 "RWMask_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_2 "RWMask_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_1 "RWMask_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename RWMask_RNO_0 "RWMask_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B !A)+C (!B+!A))"))
-          )
-          (instance (rename un1_wb_adr_0_sqmuxa_2_0_1_0 "un1_wb_adr_0_sqmuxa_2_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+!A)+D (!C+!B))"))
-          )
-          (instance (rename wb_adr_RNO_2 "wb_adr_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename wb_adr_RNO_3 "wb_adr_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance (rename wb_adr_RNO_7 "wb_adr_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance wb_req_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance (rename RA_42_i_o2_8 "RA_42_i_o2[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C+(B+A))"))
-          )
-          (instance nRAS_2_iv_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A)+C (!B !A))"))
-          )
-          (instance Vout3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B !A)))"))
-          )
-          (instance (rename RA_42_3_0_5 "RA_42_3_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B+A)+C A)"))
-          )
-          (instance (rename wb_dati_7_0_a2_0_2_7 "wb_dati_7_0_a2_0_2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (!C (B+!A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_0_0_6 "wb_dati_7_0_a2_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A))"))
-          )
-          (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+!A)"))
-          )
-          (instance nWE80_pad_RNI3ICD (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance (rename RWBank_5_0_o2_0 "RWBank_5_0_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C+B)+D (C+(B+A)))"))
+          (instance nVOE_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
+           (property lut_function (string "(!B+A)"))
           )
           (instance (rename SZ0Z_1 "S_1") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
            (property lut_function (string "(C (!B A))"))
           )
-          (instance un1_CS_0_sqmuxa_0_0_a2_1_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
-          )
-          (instance (rename wb_adr_7_0_a2_5_0_0 "wb_adr_7_0_a2_5_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A))"))
-          )
-          (instance CmdBitbangMXO2_4_u_0_0_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B !A))"))
-          )
-          (instance Ready_0_sqmuxa_0_a2_6_a2_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance nCS_6_u_i_a2_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (!B A)))"))
-          )
-          (instance (rename wb_adr_RNO_4 "wb_adr_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !B+C A)"))
-          )
-          (instance (rename wb_adr_RNO_6 "wb_adr_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !B+C A)"))
-          )
-          (instance (rename wb_adr_RNO_5 "wb_adr_RNO[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C !B+C A)"))
-          )
-          (instance LEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C (!B+A))"))
-          )
-          (instance (rename RWMask_RNO_7 "RWMask_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A)+C (!B+A))"))
-          )
-          (instance (rename CmdTout_3_0_a2_0 "CmdTout_3_0_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_12 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_13 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance nCS_6_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance (rename un1_LEDEN13_2_i_o2_0 "un1_LEDEN13_2_i_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance (rename wb_adr_7_0_o2_0 "wb_adr_7_0_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance (rename S_RNINI6S_1 "S_RNINI6S[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance (rename S_r_i_o2_1 "S_r_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance (rename FS_RNI9Q57_13 "FS_RNI9Q57[13]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+A)"))
-          )
-          (instance (rename wb_adr_7_0_o2_2_0 "wb_adr_7_0_o2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B+!A)"))
-          )
-          (instance (rename FS_RNIJ9MH_14 "FS_RNIJ9MH[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance (rename wb_dati_7_0_a2_1_0 "wb_dati_7_0_a2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B A)"))
-          )
-          (instance wb_rst8_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!B !A)"))
-          )
-          (instance wb_reqc_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(B+A)"))
-          )
-          (instance CmdBitbangMXO2_4_u_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B A))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_16 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (!B !A))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_17 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (B A))"))
-          )
-          (instance un1_nCS61_1_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B A)))"))
-          )
-          (instance (rename FS_RNI6JJA_8 "FS_RNI6JJA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C+(!B+!A))"))
-          )
-          (instance un1_CS_0_sqmuxa_0_0_a2_3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D (C (B A)))"))
-          )
-          (instance (rename CS_RNO_1 "CS_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D A+D (!C (!B !A+B A)+C A))"))
-          )
-          (instance (rename wb_dati_7_0_a2_5_1 "wb_dati_7_0_a2_5[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(C (!B !A))"))
-          )
-          (instance nCS_6_u_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(D+(C+(!B !A)))"))
-          )
-          (instance (rename un1_LEDEN13_2_i_a2_0 "un1_LEDEN13_2_i_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (C (B+A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_2_0 "wb_dati_7_0_a2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!D (!C (B !A)))"))
-          )
-          (instance (rename wb_dati_7_0_a2_6_1 "wb_dati_7_0_a2_6[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT)))
-           (property lut_function (string "(!C (B A))"))
-          )
           (instance (rename FS_s_0_15 "FS_s_0[15]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT)))
            (property INIT0 (string "0x5002"))
            (property INJECT1_1 (string "NO"))
@@ -1805,674 +4409,206 @@
            (property INJECT1_0 (string "NO"))
            (property INIT1 (string "0x300A"))
           )
-          (instance ufmefb (viewRef netlist (cellRef REFB))
+          (instance ram2e_ufm (viewRef netlist (cellRef RAM2E_UFM))
           )
-          (net wb_rst (joined
-           (portRef Q (instanceRef wb_rst))
-           (portRef wb_rst (instanceRef ufmefb))
-          ))
-          (net wb_cyc_stb (joined
-           (portRef Q (instanceRef wb_cyc_stb))
-           (portRef wb_cyc_stb (instanceRef ufmefb))
-          ))
-          (net wb_we (joined
-           (portRef Q (instanceRef wb_we))
-           (portRef wb_we (instanceRef ufmefb))
-          ))
-          (net (rename wb_adr_0 "wb_adr[0]") (joined
-           (portRef Q (instanceRef wb_adr_0))
-           (portRef (member wb_adr 7) (instanceRef ufmefb))
-           (portRef C (instanceRef wb_dati_7_0_0))
-          ))
-          (net (rename wb_adr_1 "wb_adr[1]") (joined
-           (portRef Q (instanceRef wb_adr_1))
-           (portRef (member wb_adr 6) (instanceRef ufmefb))
-           (portRef C (instanceRef wb_dati_7_0_0_1))
-          ))
-          (net (rename wb_adr_2 "wb_adr[2]") (joined
-           (portRef Q (instanceRef wb_adr_2))
-           (portRef (member wb_adr 5) (instanceRef ufmefb))
-           (portRef C (instanceRef wb_dati_7_0_2))
-          ))
-          (net (rename wb_adr_3 "wb_adr[3]") (joined
-           (portRef Q (instanceRef wb_adr_3))
-           (portRef (member wb_adr 4) (instanceRef ufmefb))
-           (portRef D (instanceRef wb_dati_7_0_0_3))
-          ))
-          (net (rename wb_adr_4 "wb_adr[4]") (joined
-           (portRef Q (instanceRef wb_adr_4))
-           (portRef (member wb_adr 3) (instanceRef ufmefb))
-           (portRef D (instanceRef wb_dati_7_0_0_4))
-          ))
-          (net (rename wb_adr_5 "wb_adr[5]") (joined
-           (portRef Q (instanceRef wb_adr_5))
-           (portRef (member wb_adr 2) (instanceRef ufmefb))
-           (portRef C (instanceRef wb_dati_7_0_5))
-          ))
-          (net (rename wb_adr_6 "wb_adr[6]") (joined
-           (portRef Q (instanceRef wb_adr_6))
-           (portRef (member wb_adr 1) (instanceRef ufmefb))
-           (portRef D (instanceRef wb_dati_7_0_1_6))
-          ))
-          (net (rename wb_adr_7 "wb_adr[7]") (joined
-           (portRef Q (instanceRef wb_adr_7))
-           (portRef (member wb_adr 0) (instanceRef ufmefb))
-           (portRef C (instanceRef wb_dati_7_0_0_7))
-          ))
-          (net (rename wb_dati_0 "wb_dati[0]") (joined
-           (portRef Q (instanceRef wb_dati_0))
-           (portRef (member wb_dati 7) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_1 "wb_dati[1]") (joined
-           (portRef Q (instanceRef wb_dati_1))
-           (portRef (member wb_dati 6) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_2 "wb_dati[2]") (joined
-           (portRef Q (instanceRef wb_dati_2))
-           (portRef (member wb_dati 5) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_3 "wb_dati[3]") (joined
-           (portRef Q (instanceRef wb_dati_3))
-           (portRef (member wb_dati 4) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_4 "wb_dati[4]") (joined
-           (portRef Q (instanceRef wb_dati_4))
-           (portRef (member wb_dati 3) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_5 "wb_dati[5]") (joined
-           (portRef Q (instanceRef wb_dati_5))
-           (portRef (member wb_dati 2) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_6 "wb_dati[6]") (joined
-           (portRef Q (instanceRef wb_dati_6))
-           (portRef (member wb_dati 1) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dati_7 "wb_dati[7]") (joined
-           (portRef Q (instanceRef wb_dati_7))
-           (portRef (member wb_dati 0) (instanceRef ufmefb))
-          ))
-          (net (rename wb_dato_0 "wb_dato[0]") (joined
-           (portRef (member wb_dato 7) (instanceRef ufmefb))
-           (portRef C (instanceRef LEDEN_RNO))
-           (portRef C (instanceRef RWMask_RNO_0))
-          ))
-          (net (rename wb_dato_1 "wb_dato[1]") (joined
-           (portRef (member wb_dato 6) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_1))
-          ))
-          (net (rename wb_dato_2 "wb_dato[2]") (joined
-           (portRef (member wb_dato 5) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_2))
-          ))
-          (net (rename wb_dato_3 "wb_dato[3]") (joined
-           (portRef (member wb_dato 4) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_3))
-          ))
-          (net (rename wb_dato_4 "wb_dato[4]") (joined
-           (portRef (member wb_dato 3) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_4))
-          ))
-          (net (rename wb_dato_5 "wb_dato[5]") (joined
-           (portRef (member wb_dato 2) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_5))
-          ))
-          (net (rename wb_dato_6 "wb_dato[6]") (joined
-           (portRef (member wb_dato 1) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_6))
-          ))
-          (net (rename wb_dato_7 "wb_dato[7]") (joined
-           (portRef (member wb_dato 0) (instanceRef ufmefb))
-           (portRef C (instanceRef RWMask_RNO_7))
-          ))
-          (net wb_ack (joined
-           (portRef wb_ack (instanceRef ufmefb))
-           (portRef A (instanceRef un1_LEDEN13_2_i_a2_0))
-           (portRef B (instanceRef un1_LEDEN13_2_i_o2_0))
-           (portRef D (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0))
-           (portRef C (instanceRef wb_cyc_stb_RNO_0))
-           (portRef A (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0))
-          ))
-          (net (rename S_2 "S[2]") (joined
-           (portRef Q (instanceRef S_2))
-           (portRef B (instanceRef FS_RNIJ9MH_14))
-           (portRef A (instanceRef S_r_i_o2_1))
-           (portRef C (instanceRef wb_adr_RNO_5))
-           (portRef C (instanceRef wb_adr_RNO_6))
-           (portRef C (instanceRef wb_adr_RNO_4))
-           (portRef C (instanceRef nCS_6_u_i_a2_1_0))
-           (portRef C (instanceRef Vout3_0_a2))
-           (portRef B (instanceRef nRAS_2_iv_0_a2_0))
-           (portRef B (instanceRef RA_42_i_o2_8))
-           (portRef B (instanceRef wb_adr_RNO_7))
-           (portRef B (instanceRef wb_adr_RNO_3))
-           (portRef B (instanceRef wb_adr_RNO_2))
-           (portRef C (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0))
-           (portRef C (instanceRef S_s_0_1_0))
-           (portRef B (instanceRef RA_0io_RNO_11))
-           (portRef B (instanceRef nCS_6_u_i_0))
-           (portRef B (instanceRef CKE_6_iv_i_0_1))
-           (portRef C (instanceRef S_RNO_3))
-           (portRef B (instanceRef RA_0io_RNO_9))
-           (portRef B (instanceRef CmdBitbangMXO2_RNI8CSO1))
-           (portRef B (instanceRef wb_we_RNO_0))
-           (portRef D (instanceRef wb_we_RNO_2))
-           (portRef C (instanceRef S_RNII9DO1_1_1))
-           (portRef C (instanceRef S_RNO_2))
-           (portRef C (instanceRef wb_adr_7_0_0_0))
-           (portRef B (instanceRef wb_dati_7_0_0_7))
-           (portRef B (instanceRef wb_dati_7_0_0_1))
-           (portRef C (instanceRef wb_adr_RNO_1))
-           (portRef C (instanceRef wb_dati_7_0_0_4))
-           (portRef C (instanceRef wb_dati_7_0_0_3))
-           (portRef B (instanceRef wb_dati_7_0_0))
-           (portRef C (instanceRef wb_dati_7_0_1_6))
-           (portRef B (instanceRef wb_dati_7_0_2))
-           (portRef B (instanceRef wb_dati_7_0_5))
-           (portRef CD (instanceRef wb_req))
-           (portRef C (instanceRef wb_reqc_1_RNIEO5C1))
-           (portRef D (instanceRef wb_req_RNO_0))
-           (portRef B (instanceRef DOEEN_RNO))
-           (portRef C (instanceRef BA_0io_RNO_1))
-           (portRef C (instanceRef BA_0io_RNO_0))
-           (portRef D (instanceRef FS_RNI5OOF1_15))
-           (portRef C (instanceRef S_RNII9DO1_3_1))
-           (portRef C (instanceRef RA_42_0_RNO_10))
-           (portRef B (instanceRef wb_reqc_1_RNIRU4M1))
-           (portRef B (instanceRef S_RNII9DO1_1))
-           (portRef B (instanceRef DQML_0io_RNO_0))
-           (portRef A (instanceRef S_RNII9DO1_0_1))
-           (portRef B (instanceRef S_RNII9DO1_2_1))
-          ))
-          (net RWSel (joined
-           (portRef Q (instanceRef RWSel))
-           (portRef C (instanceRef un1_LEDEN13_2_i_a2_0))
-           (portRef B (instanceRef CmdTout_3_0_a2_0))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_7))
-           (portRef B (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_5))
-           (portRef C (instanceRef CmdTout_RNO_1))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_2))
-           (portRef D (instanceRef CmdLEDGet_4_u_0_0_0))
-           (portRef D (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_1))
-           (portRef C (instanceRef CmdLEDSet_4_u_0_0_0))
-           (portRef D (instanceRef CmdBitbangMXO2_4_u_0_0_0))
-           (portRef D (instanceRef CmdRWMaskSet_4_u_0_0_0))
-           (portRef D (instanceRef CmdExecMXO2_4_u_0_0_0))
-           (portRef C (instanceRef CmdSetRWBankFFLED_4_u_0_0_0))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_0))
-           (portRef D (instanceRef CmdTout_RNO_2))
-           (portRef A (instanceRef wb_reqc_1_RNIRU4M1))
+          (net un9_VOEEN_0_a2_0_a3_0_a3 (joined
+           (portRef un9_VOEEN_0_a2_0_a3_0_a3_1z (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef RWSel))
           ))
           (net (rename S_0 "S[0]") (joined
            (portRef Q (instanceRef S_0))
-           (portRef A (instanceRef wb_reqc_1))
-           (portRef A (instanceRef S_RNINI6S_1))
-           (portRef B (instanceRef nCS_6_u_i_a2_1_0))
-           (portRef B (instanceRef RA_42_3_0_5))
-           (portRef A (instanceRef Vout3_0_a2))
-           (portRef A (instanceRef S_s_0_1_0))
-           (portRef B (instanceRef nCS_6_u_i_a2_0))
-           (portRef C (instanceRef nRWE_r_0))
-           (portRef B (instanceRef RA_0io_RNO_2))
-           (portRef B (instanceRef RA_0io_RNO_1))
-           (portRef B (instanceRef RA_RNO_0))
-           (portRef B (instanceRef RA_0io_RNO_7))
-           (portRef B (instanceRef RA_0io_RNO_6))
-           (portRef B (instanceRef RA_0io_RNO_4))
-           (portRef B (instanceRef RA_RNO_3))
-           (portRef B (instanceRef S_s_0_0))
-           (portRef D (instanceRef RA_0io_RNO_8))
-           (portRef A (instanceRef S_RNII9DO1_1_1))
-           (portRef C (instanceRef nRAS_2_iv_i))
-           (portRef C (instanceRef DQMH_0io_RNO))
-           (portRef D (instanceRef DOEEN_RNO))
-           (portRef C (instanceRef nCAS_0io_RNO_0))
-           (portRef A (instanceRef S_RNII9DO1_3_1))
-           (portRef A (instanceRef RA_42_0_RNO_10))
-           (portRef D (instanceRef S_RNII9DO1_1))
-           (portRef C (instanceRef CKE_6_iv_i_0_1_RNO))
-           (portRef D (instanceRef DQML_0io_RNO_0))
-           (portRef D (instanceRef S_RNII9DO1_0_1))
-           (portRef D (instanceRef S_RNII9DO1_2_1))
+           (portRef (member s 3) (instanceRef ram2e_ufm))
+           (portRef C (instanceRef VOEEN_RNO))
+           (portRef C (instanceRef DOEEN_RNO))
           ))
           (net (rename S_1 "S[1]") (joined
            (portRef Q (instanceRef S_1))
-           (portRef B (instanceRef wb_reqc_1))
-           (portRef B (instanceRef S_RNINI6S_1))
-           (portRef B (instanceRef Vout3_0_a2))
-           (portRef A (instanceRef nRAS_2_iv_0_a2_0))
-           (portRef A (instanceRef RA_42_i_o2_8))
-           (portRef B (instanceRef S_s_0_1_0))
-           (portRef C (instanceRef nCS_6_u_i_a2_0))
-           (portRef A (instanceRef nCS_6_u_i_0))
-           (portRef C (instanceRef S_s_0_0))
-           (portRef B (instanceRef S_RNII9DO1_1_1))
-           (portRef C (instanceRef DOEEN_RNO))
-           (portRef D (instanceRef BA_0io_RNO_1))
-           (portRef D (instanceRef BA_0io_RNO_0))
-           (portRef D (instanceRef S_RNII9DO1_3_1))
-           (portRef D (instanceRef RA_42_0_RNO_10))
-           (portRef C (instanceRef S_RNII9DO1_1))
-           (portRef B (instanceRef CKE_6_iv_i_0_1_RNO))
-           (portRef C (instanceRef DQML_0io_RNO_0))
-           (portRef C (instanceRef S_RNII9DO1_0_1))
-           (portRef C (instanceRef S_RNII9DO1_2_1))
+           (portRef (member s 2) (instanceRef ram2e_ufm))
+           (portRef B (instanceRef VOEEN_RNO))
+           (portRef B (instanceRef DOEEN_RNO))
+          ))
+          (net (rename S_2 "S[2]") (joined
+           (portRef Q (instanceRef S_2))
+           (portRef (member s 1) (instanceRef ram2e_ufm))
+           (portRef A (instanceRef DOEEN_RNO))
           ))
           (net (rename S_3 "S[3]") (joined
            (portRef Q (instanceRef S_3))
-           (portRef B (instanceRef S_r_i_o2_1))
-           (portRef B (instanceRef RWMask_RNO_7))
-           (portRef B (instanceRef LEDEN_RNO))
-           (portRef D (instanceRef nCS_6_u_i_a2_1_0))
-           (portRef C (instanceRef RA_42_3_0_5))
-           (portRef D (instanceRef Vout3_0_a2))
-           (portRef C (instanceRef nRAS_2_iv_0_a2_0))
-           (portRef C (instanceRef RA_42_i_o2_8))
-           (portRef D (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0))
-           (portRef B (instanceRef RWMask_RNO_0))
-           (portRef B (instanceRef RWMask_RNO_1))
-           (portRef B (instanceRef RWMask_RNO_2))
-           (portRef B (instanceRef RWMask_RNO_3))
-           (portRef B (instanceRef RWMask_RNO_4))
-           (portRef B (instanceRef RWMask_RNO_5))
-           (portRef B (instanceRef RWMask_RNO_6))
-           (portRef D (instanceRef S_s_0_1_0))
-           (portRef D (instanceRef nCS_6_u_i_a2_0))
-           (portRef C (instanceRef RA_0io_RNO_11))
-           (portRef C (instanceRef RA_0io_RNO_2))
-           (portRef C (instanceRef RA_0io_RNO_1))
-           (portRef C (instanceRef RA_RNO_0))
-           (portRef C (instanceRef RA_0io_RNO_7))
-           (portRef C (instanceRef RA_0io_RNO_6))
-           (portRef C (instanceRef RA_0io_RNO_4))
-           (portRef C (instanceRef RA_RNO_3))
-           (portRef C (instanceRef nCS_6_u_i_0))
-           (portRef C (instanceRef CKE_6_iv_i_0_1))
-           (portRef C (instanceRef wb_req_RNO))
-           (portRef D (instanceRef S_RNO_3))
-           (portRef C (instanceRef RA_0io_RNO_9))
-           (portRef D (instanceRef S_RNII9DO1_1_1))
-           (portRef D (instanceRef S_RNO_2))
-           (portRef D (instanceRef CKE_6_iv_i_0))
-           (portRef C (instanceRef wb_cyc_stb_RNO))
-           (portRef B (instanceRef wb_reqc_1_RNIEO5C1))
-           (portRef C (instanceRef wb_req_RNO_0))
-           (portRef A (instanceRef DOEEN_RNO))
-           (portRef B (instanceRef BA_0io_RNO_1))
-           (portRef B (instanceRef BA_0io_RNO_0))
-           (portRef C (instanceRef FS_RNI5OOF1_15))
-           (portRef B (instanceRef S_RNII9DO1_3_1))
-           (portRef B (instanceRef RA_42_0_RNO_10))
-           (portRef C (instanceRef wb_reqc_1_RNIRU4M1))
-           (portRef A (instanceRef S_RNII9DO1_1))
-           (portRef A (instanceRef DQML_0io_RNO_0))
-           (portRef B (instanceRef S_RNII9DO1_0_1))
-           (portRef A (instanceRef S_RNII9DO1_2_1))
+           (portRef (member s 0) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef DOEEN))
+           (portRef A (instanceRef VOEEN_RNO))
           ))
           (net (rename FS_0 "FS[0]") (joined
            (portRef Q (instanceRef FS_0))
+           (portRef (member fs 15) (instanceRef ram2e_ufm))
            (portRef A1 (instanceRef FS_cry_0_0))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0))
-           (portRef A (instanceRef un1_LEDEN13_2_i_a2_0_0))
-           (portRef A (instanceRef nCS_6_u_i_a2_4))
-           (portRef B (instanceRef wb_cyc_stb_RNO_0))
-          ))
-          (net (rename FS_8 "FS[8]") (joined
-           (portRef Q (instanceRef FS_8))
-           (portRef A1 (instanceRef FS_cry_0_7))
-           (portRef A (instanceRef wb_dati_7_0_a2_2_0))
-           (portRef C (instanceRef FS_RNI6JJA_8))
-           (portRef A (instanceRef wb_adr_7_0_o2_2_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_0_0_6))
-           (portRef A (instanceRef wb_dati_7_0_a2_0_2_7))
-           (portRef A (instanceRef wb_adr_7_0_1_0))
-           (portRef A (instanceRef wb_adr_7_0_a2_2_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_3_4))
-           (portRef D (instanceRef wb_we_RNO_1))
-           (portRef D (instanceRef FS_RNIOD6E_8))
-           (portRef B (instanceRef FS_RNIOD6E_0_8))
-           (portRef C (instanceRef wb_adr_RNO_2_1))
-           (portRef B (instanceRef FS_RNIOD6E_1_8))
-           (portRef B (instanceRef wb_dati_7_0_2_RNO_3))
-          ))
-          (net (rename FS_9 "FS[9]") (joined
-           (portRef Q (instanceRef FS_9))
-           (portRef A0 (instanceRef FS_cry_0_9))
-           (portRef B (instanceRef FS_RNI6JJA_8))
-           (portRef B (instanceRef wb_adr_7_0_o2_2_0))
-           (portRef A (instanceRef wb_adr_7_0_a2_5_0_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_0_0_6))
-           (portRef B (instanceRef wb_dati_7_0_a2_0_2_7))
-           (portRef A (instanceRef wb_dati_7_0_a2_1_0_0))
-           (portRef A (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0))
-           (portRef A (instanceRef wb_dati_7_0_o2_1))
-           (portRef A (instanceRef wb_dati_7_0_a2_1_7))
-           (portRef B (instanceRef wb_adr_7_0_a2_2_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_5_4))
-           (portRef B (instanceRef wb_dati_7_0_a2_3_4))
-           (portRef A (instanceRef wb_dati_7_0_RNO_7))
-           (portRef A (instanceRef wb_adr_7_0_a2_0_0))
-           (portRef C (instanceRef wb_we_RNO_1))
-           (portRef C (instanceRef FS_RNIOD6E_8))
-           (portRef C (instanceRef FS_RNIOD6E_0_8))
-           (portRef B (instanceRef wb_adr_RNO_2_1))
-           (portRef A (instanceRef FS_RNIOD6E_1_8))
-           (portRef A (instanceRef wb_dati_7_0_2_RNO_3))
-          ))
-          (net (rename FS_10 "FS[10]") (joined
-           (portRef Q (instanceRef FS_10))
-           (portRef A1 (instanceRef FS_cry_0_9))
-           (portRef A (instanceRef wb_dati_7_0_a2_1_0))
-           (portRef A (instanceRef wb_adr_7_0_o2_0))
-           (portRef B (instanceRef wb_adr_7_0_a2_5_0_0))
-           (portRef C (instanceRef wb_dati_7_0_a2_0_2_7))
-           (portRef A (instanceRef wb_we_RNO_4))
-           (portRef B (instanceRef wb_dati_7_0_o2_1))
-           (portRef A (instanceRef wb_dati_7_0_a2_6))
-           (portRef A (instanceRef wb_dati_7_0_a2_7))
-           (portRef B (instanceRef wb_adr_7_0_a2_0_0))
-           (portRef D (instanceRef wb_dati_7_0_a2_5_RNIC22J_4))
-           (portRef B (instanceRef wb_we_RNO_1))
-           (portRef B (instanceRef FS_RNIOD6E_8))
-           (portRef A (instanceRef FS_RNIOD6E_0_8))
-           (portRef D (instanceRef wb_dati_7_0_0_RNO_7))
-           (portRef D (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0))
-           (portRef A (instanceRef wb_adr_RNO_2_1))
-           (portRef D (instanceRef FS_RNIOD6E_1_8))
-           (portRef C (instanceRef wb_adr_RNO_3_1))
-           (portRef D (instanceRef wb_dati_7_0_2_RNO_3))
-          ))
-          (net (rename FS_11 "FS[11]") (joined
-           (portRef Q (instanceRef FS_11))
-           (portRef A0 (instanceRef FS_cry_0_11))
-           (portRef A (instanceRef FS_RNI6JJA_8))
-           (portRef B (instanceRef wb_adr_7_0_o2_0))
-           (portRef C (instanceRef wb_dati_7_0_a2_0_0_6))
-           (portRef D (instanceRef wb_dati_7_0_a2_0_2_7))
-           (portRef A (instanceRef wb_req_RNO_1))
-           (portRef B (instanceRef wb_dati_7_0_a2_1_0_0))
-           (portRef A (instanceRef wb_adr_RNO_0_1))
-           (portRef C (instanceRef wb_dati_7_0_o2_1))
-           (portRef A (instanceRef wb_adr_7_0_a2_0_0_0))
-           (portRef A (instanceRef wb_adr_7_0_a2_1_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_5_4))
-           (portRef C (instanceRef wb_dati_7_0_a2_3_4))
-           (portRef C (instanceRef wb_adr_7_0_a2_0_0))
-           (portRef A (instanceRef FS_RNIOD6E_8))
-           (portRef D (instanceRef FS_RNIOD6E_0_8))
-           (portRef B (instanceRef wb_we_RNO_3))
-           (portRef C (instanceRef FS_RNIOD6E_1_8))
-           (portRef C (instanceRef wb_dati_7_0_2_RNO_3))
-          ))
-          (net (rename FS_12 "FS[12]") (joined
-           (portRef Q (instanceRef FS_12))
-           (portRef A1 (instanceRef FS_cry_0_11))
-           (portRef A (instanceRef wb_dati_7_0_a2_6_1))
-           (portRef B (instanceRef wb_dati_7_0_a2_1_0))
-           (portRef A (instanceRef FS_RNI9Q57_13))
-           (portRef C (instanceRef wb_adr_7_0_a2_5_0_0))
-           (portRef B (instanceRef wb_req_RNO_1))
-           (portRef A (instanceRef wb_dati_7_0_a2_2_0_1))
-           (portRef B (instanceRef wb_adr_RNO_0_1))
-           (portRef B (instanceRef wb_we_RNO_4))
-           (portRef B (instanceRef wb_adr_7_0_a2_0_0_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_1))
-           (portRef B (instanceRef wb_adr_7_0_a2_1_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_6))
-           (portRef B (instanceRef wb_dati_7_0_a2_7))
-           (portRef A (instanceRef wb_dati_7_0_a2_4))
-           (portRef A (instanceRef wb_dati_7_0_2_3))
-           (portRef C (instanceRef wb_dati_7_0_a2_5_RNIC22J_4))
-           (portRef A (instanceRef wb_we_RNO_1))
-           (portRef D (instanceRef wb_we_RNO_3))
-           (portRef C (instanceRef wb_dati_7_0_0_RNO_7))
-           (portRef C (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0))
-           (portRef B (instanceRef wb_adr_RNO_3_1))
-          ))
-          (net (rename FS_13 "FS[13]") (joined
-           (portRef Q (instanceRef FS_13))
-           (portRef A0 (instanceRef FS_cry_0_13))
-           (portRef C (instanceRef wb_dati_7_0_a2_6_1))
-           (portRef B (instanceRef FS_RNI9Q57_13))
-           (portRef C (instanceRef wb_req_RNO_1))
-           (portRef C (instanceRef wb_dati_7_0_a2_1_0_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_2_0_1))
-           (portRef D (instanceRef wb_dati_7_0_o2_1))
-           (portRef C (instanceRef wb_adr_7_0_a2_0_0_0))
-           (portRef A (instanceRef CKE_6_iv_i_a2_3))
-           (portRef A (instanceRef wb_we_RNO))
-           (portRef C (instanceRef wb_dati_7_0_a2_7))
-           (portRef A (instanceRef wb_adr_7_0_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_5_RNIC22J_4))
-           (portRef A (instanceRef FS_RNIK5632_15))
-           (portRef C (instanceRef wb_we_RNO_3))
-           (portRef B (instanceRef wb_dati_7_0_0_RNO_7))
-           (portRef A (instanceRef wb_adr_RNO_3_1))
-          ))
-          (net (rename FS_15 "FS[15]") (joined
-           (portRef Q (instanceRef FS_15))
-           (portRef A0 (instanceRef FS_s_0_15))
-           (portRef B (instanceRef wb_dati_7_0_a2_2_0))
-           (portRef C (instanceRef wb_dati_7_0_a2_5_1))
-           (portRef B (instanceRef wb_rst8_0_a2))
-           (portRef A (instanceRef nCS_6_u_i_a2_1_0))
-           (portRef A (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0))
-           (portRef B (instanceRef CKE_6_iv_i_0))
-           (portRef C (instanceRef nCS_6_u_i_a2_4_RNI3A062))
-           (portRef B (instanceRef FS_RNIK5632_15))
-           (portRef A (instanceRef wb_req_RNO_0))
-           (portRef A (instanceRef FS_RNI5OOF1_15))
-          ))
-          (net PHI1reg (joined
-           (portRef Q (instanceRef PHI1reg_0io))
-           (portRef B (instanceRef SZ0Z_1))
-          ))
-          (net (rename FS_14 "FS[14]") (joined
-           (portRef Q (instanceRef FS_14))
-           (portRef A1 (instanceRef FS_cry_0_13))
-           (portRef D (instanceRef wb_dati_7_0_a2_2_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_5_1))
-           (portRef A (instanceRef wb_rst8_0_a2))
-           (portRef A (instanceRef FS_RNIJ9MH_14))
-           (portRef A (instanceRef un1_LEDEN13_2_i_o2_0))
-           (portRef B (instanceRef wb_adr_RNO_5))
-           (portRef B (instanceRef wb_adr_RNO_6))
-           (portRef B (instanceRef wb_adr_RNO_4))
-           (portRef B (instanceRef CKE_6_iv_i_a2_3))
-           (portRef A (instanceRef wb_req_RNO))
-           (portRef D (instanceRef wb_cyc_stb_RNO_0))
-           (portRef D (instanceRef FS_RNIK5632_15))
-          ))
-          (net (rename FS_6 "FS[6]") (joined
-           (portRef Q (instanceRef FS_6))
-           (portRef A1 (instanceRef FS_cry_0_5))
-           (portRef A (instanceRef un1_LEDEN13_2_i_o2_2_0))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a2_6_a2))
-           (portRef B (instanceRef nCS_6_u_i_a2_4))
-          ))
-          (net (rename FS_2 "FS[2]") (joined
-           (portRef Q (instanceRef FS_2))
-           (portRef A1 (instanceRef FS_cry_0_1))
-           (portRef C (instanceRef un1_nCS61_1_0_a2_0))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0))
-           (portRef B (instanceRef FS_RNI9FGA_1))
           ))
           (net (rename FS_1 "FS[1]") (joined
            (portRef Q (instanceRef FS_1))
+           (portRef (member fs 14) (instanceRef ram2e_ufm))
            (portRef A0 (instanceRef FS_cry_0_1))
-           (portRef D (instanceRef un1_nCS61_1_0_a2_0))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0))
-           (portRef C (instanceRef FS_RNI9FGA_1))
+          ))
+          (net (rename FS_2 "FS[2]") (joined
+           (portRef Q (instanceRef FS_2))
+           (portRef (member fs 13) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_1))
           ))
           (net (rename FS_3 "FS[3]") (joined
            (portRef Q (instanceRef FS_3))
+           (portRef (member fs 12) (instanceRef ram2e_ufm))
            (portRef A0 (instanceRef FS_cry_0_3))
-           (portRef B (instanceRef un1_nCS61_1_0_a2_0))
-           (portRef A (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4))
-           (portRef A (instanceRef FS_RNI9FGA_1))
-          ))
-          (net (rename FS_7 "FS[7]") (joined
-           (portRef Q (instanceRef FS_7))
-           (portRef A0 (instanceRef FS_cry_0_7))
-           (portRef B (instanceRef un1_LEDEN13_2_i_o2_2_0))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a2_6_a2))
-           (portRef C (instanceRef nCS_6_u_i_a2_4))
-          ))
-          (net (rename FS_5 "FS[5]") (joined
-           (portRef Q (instanceRef FS_5))
-           (portRef A0 (instanceRef FS_cry_0_5))
-           (portRef B (instanceRef nCS_6_u_i_o2))
-           (portRef A (instanceRef un1_nCS61_1_0_a2_0))
-           (portRef B (instanceRef nCS_6_u_i_o2_0))
-           (portRef B (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4))
           ))
           (net (rename FS_4 "FS[4]") (joined
            (portRef Q (instanceRef FS_4))
+           (portRef (member fs 11) (instanceRef ram2e_ufm))
            (portRef A1 (instanceRef FS_cry_0_3))
-           (portRef D (instanceRef nCS_6_u_i_o2))
-           (portRef A (instanceRef nCS_6_u_i_o2_0))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0))
-           (portRef A (instanceRef nCAS_s_i_o2))
-           (portRef A (instanceRef nRWE_r_0_RNO))
           ))
-          (net (rename RWBank_6 "RWBank[6]") (joined
-           (portRef Q (instanceRef RWBank_6))
-           (portRef C (instanceRef DQML_0io_RNO))
-           (portRef A (instanceRef DQMH_0io_RNO))
+          (net (rename FS_5 "FS[5]") (joined
+           (portRef Q (instanceRef FS_5))
+           (portRef (member fs 10) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_cry_0_5))
           ))
-          (net (rename RWMask_0 "RWMask[0]") (joined
-           (portRef Q (instanceRef RWMask_0))
-           (portRef C (instanceRef RWBank_5_0_0))
+          (net (rename FS_6 "FS[6]") (joined
+           (portRef Q (instanceRef FS_6))
+           (portRef (member fs 9) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_5))
           ))
-          (net (rename RWMask_1 "RWMask[1]") (joined
-           (portRef Q (instanceRef RWMask_1))
-           (portRef C (instanceRef RWBank_5_0_1))
+          (net (rename FS_7 "FS[7]") (joined
+           (portRef Q (instanceRef FS_7))
+           (portRef (member fs 8) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_cry_0_7))
           ))
-          (net (rename RWMask_2 "RWMask[2]") (joined
-           (portRef Q (instanceRef RWMask_2))
-           (portRef C (instanceRef RWBank_5_0_2))
+          (net (rename FS_8 "FS[8]") (joined
+           (portRef Q (instanceRef FS_8))
+           (portRef (member fs 7) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_7))
           ))
-          (net (rename RWMask_3 "RWMask[3]") (joined
-           (portRef Q (instanceRef RWMask_3))
-           (portRef C (instanceRef RWBank_5_0_3))
+          (net (rename FS_9 "FS[9]") (joined
+           (portRef Q (instanceRef FS_9))
+           (portRef (member fs 6) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_cry_0_9))
           ))
-          (net (rename RWMask_4 "RWMask[4]") (joined
-           (portRef Q (instanceRef RWMask_4))
-           (portRef C (instanceRef RWBank_5_0_4))
+          (net (rename FS_10 "FS[10]") (joined
+           (portRef Q (instanceRef FS_10))
+           (portRef (member fs 5) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_9))
           ))
-          (net (rename RWMask_5 "RWMask[5]") (joined
-           (portRef Q (instanceRef RWMask_5))
-           (portRef C (instanceRef RWBank_5_0_5))
+          (net (rename FS_11 "FS[11]") (joined
+           (portRef Q (instanceRef FS_11))
+           (portRef (member fs 4) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_cry_0_11))
           ))
-          (net (rename RWMask_6 "RWMask[6]") (joined
-           (portRef Q (instanceRef RWMask_6))
-           (portRef C (instanceRef RWBank_5_0_6))
+          (net (rename FS_12 "FS[12]") (joined
+           (portRef Q (instanceRef FS_12))
+           (portRef (member fs 3) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_11))
+          ))
+          (net (rename FS_13 "FS[13]") (joined
+           (portRef Q (instanceRef FS_13))
+           (portRef (member fs 2) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_cry_0_13))
+          ))
+          (net (rename FS_14 "FS[14]") (joined
+           (portRef Q (instanceRef FS_14))
+           (portRef (member fs 1) (instanceRef ram2e_ufm))
+           (portRef A1 (instanceRef FS_cry_0_13))
+          ))
+          (net (rename FS_15 "FS[15]") (joined
+           (portRef Q (instanceRef FS_15))
+           (portRef (member fs 0) (instanceRef ram2e_ufm))
+           (portRef A0 (instanceRef FS_s_0_15))
           ))
           (net (rename CS_0 "CS[0]") (joined
            (portRef Q (instanceRef CS_0))
-           (portRef D (instanceRef CS_RNO_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_10))
-           (portRef A (instanceRef CS_RNO_0_2))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_1))
-           (portRef A (instanceRef CS_RNO_0))
+           (portRef (member cs 2) (instanceRef ram2e_ufm))
           ))
           (net (rename CS_1 "CS[1]") (joined
            (portRef Q (instanceRef CS_1))
-           (portRef A (instanceRef CS_RNO_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_15))
-           (portRef A (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_4))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_0))
-           (portRef A (instanceRef CS_RNO_2))
+           (portRef (member cs 1) (instanceRef ram2e_ufm))
           ))
           (net (rename CS_2 "CS[2]") (joined
            (portRef Q (instanceRef CS_2))
-           (portRef B (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o2_0))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_0))
-           (portRef B (instanceRef CS_RNO_2))
-          ))
-          (net CmdExecMXO2 (joined
-           (portRef Q (instanceRef CmdExecMXO2))
-           (portRef B (instanceRef un1_LEDEN13_2_i_a2_0))
-           (portRef A (instanceRef wb_we_RNO_0))
-           (portRef A (instanceRef wb_cyc_stb_RNO))
-           (portRef A (instanceRef CmdExecMXO2_4_u_0_0_0))
-          ))
-          (net DOEEN (joined
-           (portRef Q (instanceRef DOEEN))
-           (portRef A (instanceRef nDOE_pad_RNO))
-          ))
-          (net LEDEN (joined
-           (portRef Q (instanceRef LEDEN))
-           (portRef D (instanceRef RWBank_5_0_o2_0))
-           (portRef A (instanceRef LED_pad_RNO))
-          ))
-          (net CmdLEDGet (joined
-           (portRef Q (instanceRef CmdLEDGet))
-           (portRef A (instanceRef RWBank_5_0_o2_0))
-           (portRef A (instanceRef CmdLEDGet_4_u_0_0_0))
-          ))
-          (net CO0_1 (joined
-           (portRef Q (instanceRef CmdTout_0))
-           (portRef A (instanceRef CmdTout_3_0_a2_0))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_5))
-           (portRef A (instanceRef CmdTout_RNO_1))
-           (portRef C (instanceRef CmdTout_RNO_2))
-          ))
-          (net (rename CmdTout_1 "CmdTout[1]") (joined
-           (portRef Q (instanceRef CmdTout_1))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_5))
-           (portRef B (instanceRef CmdTout_RNO_1))
-           (portRef B (instanceRef CmdTout_RNO_2))
-          ))
-          (net (rename CmdTout_2 "CmdTout[2]") (joined
-           (portRef Q (instanceRef CmdTout_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_5))
-           (portRef A (instanceRef CmdTout_RNO_2))
-          ))
-          (net (rename SZ0Z_1 "S_1") (joined
-           (portRef Z (instanceRef SZ0Z_1))
-           (portRef A (instanceRef S_s_0_0))
-           (portRef A (instanceRef S_RNO_3))
-           (portRef A (instanceRef S_RNO_1))
-           (portRef A (instanceRef S_RNO_2))
+           (portRef (member cs 0) (instanceRef ram2e_ufm))
           ))
           (net Ready (joined
            (portRef Q (instanceRef Ready))
+           (portRef Ready (instanceRef ram2e_ufm))
            (portRef C (instanceRef SZ0Z_1))
            (portRef B (instanceRef Ready_RNO))
           ))
-          (net wb_rst8 (joined
-           (portRef Z (instanceRef wb_rst8_0_a2))
-           (portRef D (instanceRef wb_rst))
+          (net RWSel (joined
+           (portRef Q (instanceRef RWSel))
+           (portRef RWSel (instanceRef ram2e_ufm))
           ))
-          (net nCS61 (joined
-           (portRef Z (instanceRef S_RNII9DO1_3_1))
-           (portRef D (instanceRef DQML_0io_RNO))
-           (portRef D (instanceRef nRWE_r_0_RNO))
-           (portRef SP (instanceRef RWSel))
+          (net CmdRWMaskSet (joined
+           (portRef Q (instanceRef CmdRWMaskSet))
+           (portRef CmdRWMaskSet (instanceRef ram2e_ufm))
           ))
-          (net RWSel_2 (joined
-           (portRef Z (instanceRef RWSel_2))
-           (portRef D (instanceRef RWSel))
+          (net CmdLEDSet (joined
+           (portRef Q (instanceRef CmdLEDSet))
+           (portRef CmdLEDSet (instanceRef ram2e_ufm))
           ))
-          (net (rename RWMask_7 "RWMask[7]") (joined
-           (portRef Q (instanceRef RWMask_7))
-           (portRef C (instanceRef RWBank_5_0_0_7))
+          (net PHI1r (joined
+           (portRef Q (instanceRef PHI1r_0io))
+           (portRef B (instanceRef SZ0Z_1))
+          ))
+          (net (rename RC_1 "RC[1]") (joined
+           (portRef Q (instanceRef RC_1))
+           (portRef (member rc 1) (instanceRef ram2e_ufm))
+          ))
+          (net (rename RC_2 "RC[2]") (joined
+           (portRef Q (instanceRef RC_2))
+           (portRef (member rc 0) (instanceRef ram2e_ufm))
+          ))
+          (net CO0_1 (joined
+           (portRef Q (instanceRef RC_0))
+           (portRef CO0_1 (instanceRef ram2e_ufm))
+          ))
+          (net (rename RA_3 "RA[3]") (joined
+           (portRef Q (instanceRef RA_3))
+           (portRef (member ra 8) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_3))
+          ))
+          (net (rename RWBank_0 "RWBank[0]") (joined
+           (portRef Q (instanceRef RWBank_0))
+           (portRef (member rwbank 7) (instanceRef ram2e_ufm))
+          ))
+          (net CO0_0 (joined
+           (portRef Q (instanceRef CmdTout_0))
+           (portRef CO0_0 (instanceRef ram2e_ufm))
+          ))
+          (net (rename CmdTout_1 "CmdTout[1]") (joined
+           (portRef Q (instanceRef CmdTout_1))
+           (portRef (member cmdtout 1) (instanceRef ram2e_ufm))
+          ))
+          (net (rename CmdTout_2 "CmdTout[2]") (joined
+           (portRef Q (instanceRef CmdTout_2))
+           (portRef (member cmdtout 0) (instanceRef ram2e_ufm))
+          ))
+          (net CmdLEDGet (joined
+           (portRef Q (instanceRef CmdLEDGet))
+           (portRef CmdLEDGet (instanceRef ram2e_ufm))
+          ))
+          (net (rename SZ0Z_1 "S_1") (joined
+           (portRef Z (instanceRef SZ0Z_1))
+           (portRef S_1 (instanceRef ram2e_ufm))
+          ))
+          (net DOEEN (joined
+           (portRef Q (instanceRef DOEEN))
+           (portRef DOEEN (instanceRef ram2e_ufm))
+          ))
+          (net VOEEN (joined
+           (portRef Q (instanceRef VOEEN))
+           (portRef B (instanceRef nVOE_pad_RNO))
+          ))
+          (net RC12 (joined
+           (portRef RC12 (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef RC_2))
+           (portRef SP (instanceRef RC_1))
+           (portRef SP (instanceRef RC_0))
           ))
           (net Vout3 (joined
-           (portRef Z (instanceRef Vout3_0_a2))
+           (portRef Vout3 (instanceRef ram2e_ufm))
            (portRef SP (instanceRef Vout_0io_7))
            (portRef SP (instanceRef Vout_0io_6))
            (portRef SP (instanceRef Vout_0io_5))
@@ -2481,721 +4617,308 @@
            (portRef SP (instanceRef Vout_0io_2))
            (portRef SP (instanceRef Vout_0io_1))
            (portRef SP (instanceRef Vout_0io_0))
-           (portRef A (instanceRef nCAS_0io_RNO_0))
+          ))
+          (net RWSel_2 (joined
+           (portRef RWSel_2 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RWSel))
+          ))
+          (net (rename RA_0 "RA[0]") (joined
+           (portRef Q (instanceRef RA_0))
+           (portRef (member ra 11) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_0))
           ))
           (net CmdSetRWBankFFLED (joined
            (portRef Q (instanceRef CmdSetRWBankFFLED))
-           (portRef B (instanceRef RWBank_5_0_o2_0))
-           (portRef A (instanceRef CmdSetRWBankFFLED_4_u_0_0_0))
+           (portRef CmdSetRWBankFFLED (instanceRef ram2e_ufm))
           ))
-          (net CmdSetRWBankFFMXO2 (joined
-           (portRef Q (instanceRef CmdSetRWBankFFMXO2))
-           (portRef C (instanceRef RWBank_5_0_o2_0))
-           (portRef A (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0))
+          (net Ready3 (joined
+           (portRef Ready3 (instanceRef ram2e_ufm))
+           (portRef A (instanceRef Ready_RNO))
           ))
-          (net wb_req (joined
-           (portRef Q (instanceRef wb_req))
-           (portRef D (instanceRef un1_LEDEN13_2_i_a2_0_0))
+          (net BA_0_sqmuxa (joined
+           (portRef BA_0_sqmuxa (instanceRef ram2e_ufm))
+           (portRef CD (instanceRef BA_0io_1))
+           (portRef CD (instanceRef BA_0io_0))
           ))
-          (net LEDEN13 (joined
-           (portRef Z (instanceRef wb_reqc_1_RNIRU4M1))
-           (portRef B (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0))
-           (portRef B (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0))
-           (portRef SP (instanceRef RWBank_7))
-           (portRef SP (instanceRef RWBank_6))
-           (portRef SP (instanceRef RWBank_5))
-           (portRef SP (instanceRef RWBank_4))
-           (portRef SP (instanceRef RWBank_3))
-           (portRef SP (instanceRef RWBank_2))
-           (portRef SP (instanceRef RWBank_1))
-           (portRef SP (instanceRef RWBank_0))
-          ))
-          (net (rename RWBank_5_0 "RWBank_5[0]") (joined
-           (portRef Z (instanceRef RWBank_5_0_0))
+          (net (rename RWBank_3_0 "RWBank_3[0]") (joined
+           (portRef (member rwbank_3 7) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_0))
           ))
-          (net (rename RWBank_5_1 "RWBank_5[1]") (joined
-           (portRef Z (instanceRef RWBank_5_0_1))
+          (net (rename RWBank_3_1 "RWBank_3[1]") (joined
+           (portRef (member rwbank_3 6) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_1))
           ))
-          (net (rename RWBank_5_2 "RWBank_5[2]") (joined
-           (portRef Z (instanceRef RWBank_5_0_2))
+          (net (rename RWBank_3_2 "RWBank_3[2]") (joined
+           (portRef (member rwbank_3 5) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_2))
           ))
-          (net (rename RWBank_5_3 "RWBank_5[3]") (joined
-           (portRef Z (instanceRef RWBank_5_0_3))
+          (net (rename RWBank_3_3 "RWBank_3[3]") (joined
+           (portRef (member rwbank_3 4) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_3))
           ))
-          (net (rename RWBank_5_5 "RWBank_5[5]") (joined
-           (portRef Z (instanceRef RWBank_5_0_5))
+          (net (rename RWBank_3_4 "RWBank_3[4]") (joined
+           (portRef (member rwbank_3 3) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RWBank_4))
+          ))
+          (net (rename RWBank_3_5 "RWBank_3[5]") (joined
+           (portRef (member rwbank_3 2) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_5))
           ))
-          (net (rename RWBank_5_6 "RWBank_5[6]") (joined
-           (portRef Z (instanceRef RWBank_5_0_6))
+          (net (rename RWBank_3_6 "RWBank_3[6]") (joined
+           (portRef (member rwbank_3 1) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_6))
           ))
-          (net (rename RWBank_5_7 "RWBank_5[7]") (joined
-           (portRef Z (instanceRef RWBank_5_0_0_7))
+          (net (rename RWBank_3_7 "RWBank_3[7]") (joined
+           (portRef (member rwbank_3 0) (instanceRef ram2e_ufm))
            (portRef D (instanceRef RWBank_7))
           ))
-          (net (rename RWBank_0 "RWBank[0]") (joined
-           (portRef Q (instanceRef RWBank_0))
-           (portRef B (instanceRef RA_0io_RNO_8))
+          (net CmdSetRWBankFFLED_4 (joined
+           (portRef CmdSetRWBankFFLED_4 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CmdSetRWBankFFLED))
+          ))
+          (net CmdLEDGet_3 (joined
+           (portRef CmdLEDGet_3 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CmdLEDGet))
+          ))
+          (net CmdLEDSet_3 (joined
+           (portRef CmdLEDSet_3 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CmdLEDSet))
+          ))
+          (net CmdRWMaskSet_3 (joined
+           (portRef CmdRWMaskSet_3 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CmdRWMaskSet))
+          ))
+          (net (rename CmdTout_3_0 "CmdTout_3[0]") (joined
+           (portRef CmdTout_3_0 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CmdTout_0))
           ))
           (net (rename RWBank_1 "RWBank[1]") (joined
            (portRef Q (instanceRef RWBank_1))
-           (portRef A (instanceRef RA_0io_RNO_9))
+           (portRef (member rwbank 6) (instanceRef ram2e_ufm))
           ))
           (net (rename RWBank_2 "RWBank[2]") (joined
            (portRef Q (instanceRef RWBank_2))
-           (portRef C (instanceRef RA_42_0_10))
+           (portRef (member rwbank 5) (instanceRef ram2e_ufm))
           ))
           (net (rename RWBank_3 "RWBank[3]") (joined
            (portRef Q (instanceRef RWBank_3))
-           (portRef A (instanceRef RA_0io_RNO_11))
+           (portRef (member rwbank 4) (instanceRef ram2e_ufm))
           ))
           (net (rename RWBank_4 "RWBank[4]") (joined
            (portRef Q (instanceRef RWBank_4))
-           (portRef A (instanceRef BA_0io_RNO_0))
+           (portRef (member rwbank 3) (instanceRef ram2e_ufm))
           ))
           (net (rename RWBank_5 "RWBank[5]") (joined
            (portRef Q (instanceRef RWBank_5))
-           (portRef A (instanceRef BA_0io_RNO_1))
+           (portRef (member rwbank 2) (instanceRef ram2e_ufm))
+          ))
+          (net (rename RWBank_6 "RWBank[6]") (joined
+           (portRef Q (instanceRef RWBank_6))
+           (portRef (member rwbank 1) (instanceRef ram2e_ufm))
           ))
           (net (rename RWBank_7 "RWBank[7]") (joined
            (portRef Q (instanceRef RWBank_7))
-           (portRef C (instanceRef RA_0io_RNO_8))
-          ))
-          (net CmdLEDSet (joined
-           (portRef Q (instanceRef CmdLEDSet))
-           (portRef A (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0))
-           (portRef A (instanceRef CmdLEDSet_4_u_0_0_0))
-          ))
-          (net CmdRWMaskSet (joined
-           (portRef Q (instanceRef CmdRWMaskSet))
-           (portRef A (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0))
-           (portRef A (instanceRef CmdRWMaskSet_4_u_0_0_0))
-          ))
-          (net CmdBitbangMXO2 (joined
-           (portRef Q (instanceRef CmdBitbangMXO2))
-           (portRef A (instanceRef CmdBitbangMXO2_RNI8CSO1))
-           (portRef A (instanceRef CmdBitbangMXO2_4_u_0_0_0))
-          ))
-          (net nCAS_0_sqmuxa (joined
-           (portRef Z (instanceRef nCS_6_u_i_a2_4_RNICJKD2))
-           (portRef B (instanceRef nRWE_r_0))
-           (portRef D (instanceRef RA_42_0_10))
-           (portRef A (instanceRef nCAS_0io_RNO))
-          ))
-          (net Ready_0_sqmuxa (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_6_a2))
-           (portRef A (instanceRef Ready_RNO))
+           (portRef (member rwbank 0) (instanceRef ram2e_ufm))
           ))
           (net (rename BA_4_0 "BA_4[0]") (joined
-           (portRef Z (instanceRef BA_0io_RNO_0))
+           (portRef (member ba_4 1) (instanceRef ram2e_ufm))
            (portRef D (instanceRef BA_0io_0))
           ))
           (net (rename BA_4_1 "BA_4[1]") (joined
-           (portRef Z (instanceRef BA_0io_RNO_1))
+           (portRef (member ba_4 0) (instanceRef ram2e_ufm))
            (portRef D (instanceRef BA_0io_1))
           ))
-          (net (rename RA_42_11 "RA_42[11]") (joined
-           (portRef Z (instanceRef RA_0io_RNO_11))
-           (portRef D (instanceRef RA_0io_11))
+          (net (rename RA_1 "RA[1]") (joined
+           (portRef Q (instanceRef RA_1))
+           (portRef (member ra 10) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_1))
           ))
-          (net nRWE_r_0 (joined
-           (portRef Z (instanceRef nRWE_r_0))
-           (portRef D (instanceRef nRWE_0io))
+          (net (rename RA_2 "RA[2]") (joined
+           (portRef Q (instanceRef RA_2))
+           (portRef (member ra 9) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_2))
           ))
-          (net (rename S_s_0_0 "S_s_0[0]") (joined
-           (portRef Z (instanceRef S_s_0_0))
+          (net (rename RA_4 "RA[4]") (joined
+           (portRef Q (instanceRef RA_4))
+           (portRef (member ra 7) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_4))
+          ))
+          (net (rename RA_5 "RA[5]") (joined
+           (portRef Q (instanceRef RA_5))
+           (portRef (member ra 6) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_5))
+          ))
+          (net (rename RA_6 "RA[6]") (joined
+           (portRef Q (instanceRef RA_6))
+           (portRef (member ra 5) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_6))
+          ))
+          (net (rename RA_7 "RA[7]") (joined
+           (portRef Q (instanceRef RA_7))
+           (portRef (member ra 4) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_7))
+          ))
+          (net (rename RA_8 "RA[8]") (joined
+           (portRef Q (instanceRef RA_8))
+           (portRef (member ra 3) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_8))
+          ))
+          (net (rename RA_9 "RA[9]") (joined
+           (portRef Q (instanceRef RA_9))
+           (portRef (member ra 2) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_9))
+          ))
+          (net (rename RA_10 "RA[10]") (joined
+           (portRef Q (instanceRef RA_10))
+           (portRef (member ra 1) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_10))
+          ))
+          (net (rename RA_11 "RA[11]") (joined
+           (portRef Q (instanceRef RA_11))
+           (portRef (member ra 0) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RAout_0io_11))
+          ))
+          (net CKE (joined
+           (portRef Q (instanceRef CKE))
+           (portRef D (instanceRef CKEout_0io))
+          ))
+          (net nRWE (joined
+           (portRef Q (instanceRef nRWE))
+           (portRef D (instanceRef nRWEout_0io))
+          ))
+          (net nCAS (joined
+           (portRef Q (instanceRef nCAS))
+           (portRef D (instanceRef nCASout_0io))
+          ))
+          (net nRAS (joined
+           (portRef Q (instanceRef nRAS))
+           (portRef D (instanceRef nRASout_0io))
+          ))
+          (net (rename S_s_0_0_0 "S_s_0_0[0]") (joined
+           (portRef S_s_0_0_0 (instanceRef ram2e_ufm))
            (portRef D (instanceRef S_0))
           ))
-          (net (rename wb_dati_7_0 "wb_dati_7[0]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0))
-           (portRef D (instanceRef wb_dati_0))
+          (net CmdExecMXO2_3_0_a3_0_RNI6S1P8 (joined
+           (portRef CmdExecMXO2_3_0_a3_0_RNI6S1P8_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CS_1))
           ))
-          (net (rename wb_dati_7_1 "wb_dati_7[1]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_1))
-           (portRef D (instanceRef wb_dati_1))
+          (net CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 (joined
+           (portRef CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CS_2))
           ))
-          (net (rename wb_dati_7_2 "wb_dati_7[2]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_2))
-           (portRef D (instanceRef wb_dati_2))
+          (net (rename RA_35_0 "RA_35[0]") (joined
+           (portRef (member ra_35 11) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_0))
           ))
-          (net (rename wb_dati_7_3 "wb_dati_7[3]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_3))
-           (portRef D (instanceRef wb_dati_3))
+          (net (rename RA_35_2 "RA_35[2]") (joined
+           (portRef (member ra_35 9) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_2))
           ))
-          (net (rename wb_dati_7_4 "wb_dati_7[4]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_4))
-           (portRef D (instanceRef wb_dati_4))
+          (net (rename RA_35_3 "RA_35[3]") (joined
+           (portRef (member ra_35 8) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_3))
           ))
-          (net (rename wb_dati_7_5 "wb_dati_7[5]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_5))
-           (portRef D (instanceRef wb_dati_5))
+          (net (rename RA_35_4 "RA_35[4]") (joined
+           (portRef (member ra_35 7) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_4))
           ))
-          (net (rename wb_dati_7_6 "wb_dati_7[6]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_6))
-           (portRef D (instanceRef wb_dati_6))
+          (net (rename RA_35_5 "RA_35[5]") (joined
+           (portRef (member ra_35 6) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_5))
           ))
-          (net (rename wb_dati_7_7 "wb_dati_7[7]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_7))
-           (portRef D (instanceRef wb_dati_7))
+          (net (rename RA_35_6 "RA_35[6]") (joined
+           (portRef (member ra_35 5) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_6))
           ))
-          (net (rename wb_adr_7_0 "wb_adr_7[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_0))
-           (portRef D (instanceRef wb_adr_0))
+          (net (rename RA_35_7 "RA_35[7]") (joined
+           (portRef (member ra_35 4) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_7))
           ))
-          (net (rename RA_42_3_0_5 "RA_42_3_0[5]") (joined
-           (portRef Z (instanceRef RA_42_3_0_5))
-           (portRef D (instanceRef RA_0io_5))
+          (net (rename RA_35_9 "RA_35[9]") (joined
+           (portRef (member ra_35 2) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_9))
           ))
-          (net (rename RA_42_10 "RA_42[10]") (joined
-           (portRef Z (instanceRef RA_42_0_10))
-           (portRef D (instanceRef RA_0io_10))
+          (net (rename RA_35_10 "RA_35[10]") (joined
+           (portRef (member ra_35 1) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_10))
           ))
-          (net CmdLEDGet_4 (joined
-           (portRef Z (instanceRef CmdLEDGet_4_u_0_0_0))
-           (portRef D (instanceRef CmdLEDGet))
+          (net (rename RA_35_11 "RA_35[11]") (joined
+           (portRef (member ra_35 0) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_11))
           ))
-          (net (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (joined
-           (portRef Z (instanceRef wb_adr_RNO_1))
-           (portRef D (instanceRef wb_adr_1))
+          (net un2_S_2_i_0_0_o3_RNIHFHN3 (joined
+           (portRef un2_S_2_i_0_0_o3_RNIHFHN3_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_8))
           ))
-          (net wb_we_RNO (joined
-           (portRef Z (instanceRef wb_we_RNO))
-           (portRef D (instanceRef wb_we))
-          ))
-          (net wb_cyc_stb_RNO (joined
-           (portRef Z (instanceRef wb_cyc_stb_RNO))
-           (portRef D (instanceRef wb_cyc_stb))
-          ))
-          (net (rename S_RNII9DO1_1_1 "S_RNII9DO1_1[1]") (joined
-           (portRef Z (instanceRef S_RNII9DO1_1_1))
+          (net N_126 (joined
+           (portRef N_126 (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef RA_11))
+           (portRef SP (instanceRef RA_10))
+           (portRef SP (instanceRef RA_9))
+           (portRef SP (instanceRef RA_8))
+           (portRef SP (instanceRef RA_7))
+           (portRef SP (instanceRef RA_6))
+           (portRef SP (instanceRef RA_5))
+           (portRef SP (instanceRef RA_4))
            (portRef SP (instanceRef RA_3))
+           (portRef SP (instanceRef RA_2))
+           (portRef SP (instanceRef RA_1))
            (portRef SP (instanceRef RA_0))
-           (portRef SP (instanceRef RA_0io_7))
-           (portRef SP (instanceRef RA_0io_6))
-           (portRef SP (instanceRef RA_0io_5))
-           (portRef SP (instanceRef RA_0io_4))
-           (portRef SP (instanceRef RA_0io_2))
-           (portRef SP (instanceRef RA_0io_1))
           ))
-          (net N_88 (joined
-           (portRef Z (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0))
-           (portRef SP (instanceRef RWMask_7))
-           (portRef SP (instanceRef RWMask_6))
-           (portRef SP (instanceRef RWMask_5))
-           (portRef SP (instanceRef RWMask_4))
-           (portRef SP (instanceRef RWMask_3))
-           (portRef SP (instanceRef RWMask_2))
-           (portRef SP (instanceRef RWMask_1))
-           (portRef SP (instanceRef RWMask_0))
+          (net N_223 (joined
+           (portRef N_223 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RA_1))
           ))
-          (net N_104 (joined
-           (portRef Z (instanceRef un1_LEDEN13_2_i_0_0))
-           (portRef SP (instanceRef wb_cyc_stb))
+          (net N_508 (joined
+           (portRef N_508 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef DQMH_0io))
           ))
-          (net (rename un1_LEDEN_0_sqmuxa_1_i_0_0 "un1_LEDEN_0_sqmuxa_1_i_0[0]") (joined
-           (portRef Z (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0))
-           (portRef SP (instanceRef LEDEN))
+          (net N_648 (joined
+           (portRef N_648 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_4))
           ))
-          (net CKE_6_iv_i_0 (joined
-           (portRef Z (instanceRef CKE_6_iv_i_0))
-           (portRef D (instanceRef CKE_0io))
+          (net N_662 (joined
+           (portRef N_662 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_7))
           ))
-          (net (rename S_RNII9DO1_1 "S_RNII9DO1[1]") (joined
-           (portRef Z (instanceRef S_RNII9DO1_1))
-           (portRef C (instanceRef wb_dati_7_0_a2_2_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_5_1))
-           (portRef B (instanceRef DQML_0io_RNO))
-           (portRef CD (instanceRef wb_rst))
-           (portRef B (instanceRef nCS_6_u_i_a2_4_RNI3A062))
-           (portRef B (instanceRef DQMH_0io_RNO))
-           (portRef C (instanceRef FS_RNIK5632_15))
+          (net N_663 (joined
+           (portRef N_663 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_6))
           ))
-          (net (rename S_RNII9DO1_0_1 "S_RNII9DO1_0[1]") (joined
-           (portRef Z (instanceRef S_RNII9DO1_0_1))
-           (portRef D (instanceRef un1_LEDEN13_2_i_a2_0))
-           (portRef B (instanceRef CS_RNO_1))
-           (portRef C (instanceRef CS_RNO_0_2))
-           (portRef C (instanceRef CS_RNO_0))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_3))
+          (net N_664 (joined
+           (portRef N_664 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_5))
           ))
-          (net N_285 (joined
-           (portRef Z (instanceRef RWMask_RNO_7))
-           (portRef D (instanceRef RWMask_7))
+          (net N_665 (joined
+           (portRef N_665 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_2))
           ))
-          (net LEDEN_RNO (joined
-           (portRef Z (instanceRef LEDEN_RNO))
-           (portRef D (instanceRef LEDEN))
+          (net N_666 (joined
+           (portRef N_666 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_1))
           ))
-          (net N_295 (joined
-           (portRef Z (instanceRef wb_adr_RNO_5))
-           (portRef D (instanceRef wb_adr_5))
+          (net N_667 (joined
+           (portRef N_667 (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_0))
           ))
-          (net N_296 (joined
-           (portRef Z (instanceRef wb_adr_RNO_6))
-           (portRef D (instanceRef wb_adr_6))
+          (net CKE_7_RNIS77M1 (joined
+           (portRef CKE_7_RNIS77M1_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef CKE))
           ))
-          (net N_294 (joined
-           (portRef Z (instanceRef wb_adr_RNO_4))
-           (portRef D (instanceRef wb_adr_4))
+          (net N_551 (joined
+           (portRef N_551 (instanceRef ram2e_ufm))
+           (portRef D (instanceRef VOEEN))
           ))
-          (net CmdLEDSet_4 (joined
-           (portRef Z (instanceRef CmdLEDSet_4_u_0_0_0))
-           (portRef D (instanceRef CmdLEDSet))
+          (net (rename RC_3_1 "RC_3[1]") (joined
+           (portRef (member rc_3 1) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RC_1))
           ))
-          (net CmdBitbangMXO2_4 (joined
-           (portRef Z (instanceRef CmdBitbangMXO2_4_u_0_0_0))
-           (portRef D (instanceRef CmdBitbangMXO2))
-          ))
-          (net CmdRWMaskSet_4 (joined
-           (portRef Z (instanceRef CmdRWMaskSet_4_u_0_0_0))
-           (portRef D (instanceRef CmdRWMaskSet))
-          ))
-          (net (rename RWBank_5_4 "RWBank_5[4]") (joined
-           (portRef Z (instanceRef RWBank_5_0_4))
-           (portRef D (instanceRef RWBank_4))
-          ))
-          (net CmdExecMXO2_4 (joined
-           (portRef Z (instanceRef CmdExecMXO2_4_u_0_0_0))
-           (portRef D (instanceRef CmdExecMXO2))
-          ))
-          (net CmdSetRWBankFFMXO2_4 (joined
-           (portRef Z (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0))
-           (portRef D (instanceRef CmdSetRWBankFFMXO2))
-          ))
-          (net CmdSetRWBankFFLED_4 (joined
-           (portRef Z (instanceRef CmdSetRWBankFFLED_4_u_0_0_0))
-           (portRef D (instanceRef CmdSetRWBankFFLED))
-          ))
-          (net (rename CmdTout_3_0 "CmdTout_3[0]") (joined
-           (portRef Z (instanceRef CmdTout_3_0_a2_0))
-           (portRef D (instanceRef CmdTout_0))
-          ))
-          (net N_637 (joined
-           (portRef Z (instanceRef CS_RNO_0_2))
-           (portRef C (instanceRef CS_RNO_2))
-          ))
-          (net N_466 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_7))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_10))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_2))
-          ))
-          (net N_474 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_10))
-           (portRef C (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F))
-          ))
-          (net N_477 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_11))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_2))
-          ))
-          (net N_478 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_12))
-           (portRef D (instanceRef CmdLEDGet_4_u_0_0_a2_0_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_2))
-          ))
-          (net N_616 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_13))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_o2_0))
-          ))
-          (net N_629 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_17))
-           (portRef C (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0))
-           (portRef B (instanceRef CmdExecMXO2_4_u_0_0_0))
-          ))
-          (net N_461 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_5))
-           (portRef C (instanceRef CS_RNO_1))
-           (portRef B (instanceRef CS_RNO_0_2))
-           (portRef B (instanceRef CS_RNO_0))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_3))
-          ))
-          (net N_401 (joined
-           (portRef Z (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_0))
-           (portRef B (instanceRef CmdSetRWBankFFLED_4_u_0_0_0))
-          ))
-          (net N_591 (joined
-           (portRef Z (instanceRef RWBank_5_0_o2_0))
-           (portRef B (instanceRef RWBank_5_0_0))
-           (portRef B (instanceRef RWBank_5_0_1))
-           (portRef B (instanceRef RWBank_5_0_0_7))
-           (portRef B (instanceRef RWBank_5_0_6))
-           (portRef B (instanceRef RWBank_5_0_5))
-           (portRef B (instanceRef RWBank_5_0_3))
-           (portRef B (instanceRef RWBank_5_0_2))
-           (portRef B (instanceRef RWBank_5_0_4))
-          ))
-          (net N_279 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_o2_0))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_2))
-          ))
-          (net N_623 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_15))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_o2_0))
-          ))
-          (net N_327 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_1))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_0))
-          ))
-          (net N_328 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_2))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_3))
-          ))
-          (net N_330 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_3))
-          ))
-          (net N_476 (joined
-           (portRef Z (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_1))
-           (portRef A (instanceRef CmdBitbangMXO2_4_u_0_0_a2_1))
-           (portRef C (instanceRef CmdLEDSet_4_u_0_0_a2_0))
-           (portRef C (instanceRef CmdLEDGet_4_u_0_0_0))
-           (portRef C (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_0))
-           (portRef C (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0))
-          ))
-          (net N_626 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_16))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_2))
-           (portRef D (instanceRef CmdLEDSet_4_u_0_0_a2_0))
-           (portRef D (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_0))
-           (portRef B (instanceRef CmdRWMaskSet_4_u_0_0_0))
-          ))
-          (net N_643 (joined
-           (portRef Z (instanceRef CmdBitbangMXO2_4_u_0_0_a2_1))
-           (portRef C (instanceRef CmdBitbangMXO2_4_u_0_0_0))
-           (portRef C (instanceRef CmdRWMaskSet_4_u_0_0_0))
-           (portRef C (instanceRef CmdExecMXO2_4_u_0_0_0))
-          ))
-          (net N_605 (joined
-           (portRef Z (instanceRef CmdLEDSet_4_u_0_0_a2_0))
-           (portRef B (instanceRef CmdLEDSet_4_u_0_0_0))
-          ))
-          (net N_255 (joined
-           (portRef Z (instanceRef RA_42_i_o2_8))
-           (portRef A (instanceRef RA_0io_RNO_8))
-           (portRef A (instanceRef RA_42_0_10))
-           (portRef D (instanceRef DQMH_0io_RNO))
-          ))
-          (net N_575 (joined
-           (portRef Z (instanceRef S_RNINI6S_1))
-           (portRef B (instanceRef S_RNO_3))
-           (portRef C (instanceRef S_RNO_1))
-           (portRef B (instanceRef S_RNO_2))
-          ))
-          (net N_397 (joined
-           (portRef Z (instanceRef wb_req_RNO_1))
-           (portRef B (instanceRef wb_req_RNO))
-          ))
-          (net N_635 (joined
-           (portRef Z (instanceRef nRAS_2_iv_0_a2_0))
-           (portRef B (instanceRef nRAS_2_iv_i))
-           (portRef D (instanceRef nCAS_0io_RNO_0))
-          ))
-          (net N_449 (joined
-           (portRef Z (instanceRef FS_RNI5OOF1_15))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4))
-           (portRef C (instanceRef un1_LEDEN13_2_i_a2_0_0))
-           (portRef C (instanceRef un1_LEDEN13_2_i_0_0))
-           (portRef D (instanceRef nCS_6_u_i_a2_4_RNICJKD2))
-          ))
-          (net N_633 (joined
-           (portRef Z (instanceRef un1_nCS61_1_0_a2_0))
-           (portRef C (instanceRef nCS_6_u_i_o2))
-           (portRef B (instanceRef nCAS_s_i_o2))
-           (portRef B (instanceRef nRWE_r_0_RNO))
-          ))
-          (net N_264 (joined
-           (portRef Z (instanceRef FS_RNI9FGA_1))
-           (portRef A (instanceRef nCS_6_u_i_o2))
-           (portRef D (instanceRef un1_LEDEN13_2_i_o2_2_0))
-           (portRef A (instanceRef nCS_6_u_i_a2_4_RNICJKD2))
-          ))
-          (net N_559_1 (joined
-           (portRef Z (instanceRef nCS_6_u_i_1))
-           (portRef A (instanceRef nRAS_2_iv_i))
-           (portRef A (instanceRef nCS_0io_RNO))
-          ))
-          (net N_429 (joined
-           (portRef Z (instanceRef nCS_6_u_i_a2_0))
-           (portRef A (instanceRef nCS_6_u_i_1))
-          ))
-          (net N_640 (joined
-           (portRef Z (instanceRef nCS_6_u_i_a2_4_RNI3A062))
-           (portRef C (instanceRef nRWE_r_0_RNO))
-           (portRef C (instanceRef nCAS_0io_RNO))
-          ))
-          (net N_336 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_1))
-           (portRef A (instanceRef wb_dati_7_0_o2_0_2))
-           (portRef A (instanceRef wb_dati_7_0_1))
-           (portRef A (instanceRef wb_dati_7_0_3))
-          ))
-          (net N_565 (joined
-           (portRef Z (instanceRef wb_dati_7_0_o2_1))
-           (portRef C (instanceRef wb_dati_7_0_a2_1))
-          ))
-          (net N_484 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_2_0))
-           (portRef B (instanceRef wb_dati_7_0_a2_1))
-           (portRef B (instanceRef wb_dati_7_0_a2_1_7))
-           (portRef C (instanceRef wb_dati_7_0_a2_5_4))
-           (portRef A (instanceRef wb_dati_7_0_0))
-           (portRef C (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0))
-          ))
-          (net N_634 (joined
-           (portRef Z (instanceRef FS_RNIOD6E_1_8))
-           (portRef C (instanceRef wb_dati_7_0_a2_2_0_1))
-           (portRef B (instanceRef wb_dati_7_0_0_4))
-           (portRef D (instanceRef wb_dati_7_0_o2_0_2))
-          ))
-          (net N_452 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_5_1))
-           (portRef B (instanceRef wb_dati_7_0_a2_6_1))
-           (portRef B (instanceRef wb_adr_7_0_1_0))
-           (portRef B (instanceRef wb_adr_7_0_0_0))
-           (portRef A (instanceRef wb_dati_7_0_0_7))
-           (portRef A (instanceRef wb_dati_7_0_0_1))
-           (portRef B (instanceRef wb_dati_7_0_o2_0_2))
-          ))
-          (net N_365 (joined
-           (portRef Z (instanceRef un1_LEDEN13_2_i_a2_0_0))
-           (portRef B (instanceRef un1_LEDEN13_2_i_0_0))
-          ))
-          (net N_300 (joined
-           (portRef Z (instanceRef un1_LEDEN13_2_i_o2_2_0))
-           (portRef B (instanceRef un1_LEDEN13_2_i_a2_0_0))
-           (portRef A (instanceRef wb_cyc_stb_RNO_0))
-          ))
-          (net N_377 (joined
-           (portRef Z (instanceRef wb_adr_7_0_a2_1_0))
-           (portRef A (instanceRef wb_adr_7_0_4_0))
-          ))
-          (net N_455 (joined
-           (portRef Z (instanceRef FS_RNIK5632_15))
-           (portRef C (instanceRef wb_adr_7_0_a2_1_0))
-           (portRef C (instanceRef wb_dati_7_0_a2_6))
-           (portRef C (instanceRef wb_adr_7_0_a2_2_0))
-           (portRef A (instanceRef wb_dati_7_0_0_4))
-           (portRef A (instanceRef wb_dati_7_0_0_3))
-           (portRef B (instanceRef wb_dati_7_0_a2_4))
-           (portRef C (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0))
-           (portRef B (instanceRef wb_dati_7_0_2_3))
-          ))
-          (net N_562 (joined
-           (portRef Z (instanceRef wb_adr_7_0_o2_2_0))
-           (portRef D (instanceRef wb_adr_7_0_a2_0_0_0))
-           (portRef D (instanceRef wb_adr_7_0_a2_1_0))
-          ))
-          (net N_579 (joined
-           (portRef Z (instanceRef wb_adr_7_0_o2_0))
-           (portRef C (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0))
-           (portRef C (instanceRef wb_adr_7_0_1_0))
-           (portRef D (instanceRef wb_dati_7_0_a2_1_7))
-           (portRef D (instanceRef wb_adr_7_0_a2_2_0))
-           (portRef B (instanceRef wb_dati_7_0_RNO_7))
-          ))
-          (net N_388 (joined
-           (portRef Z (instanceRef wb_adr_RNO_0_1))
-           (portRef B (instanceRef wb_adr_RNO_1))
-          ))
-          (net N_265_i (joined
-           (portRef Z (instanceRef wb_adr_RNO_2_1))
-           (portRef C (instanceRef wb_adr_RNO_0_1))
-          ))
-          (net N_475 (joined
-           (portRef Z (instanceRef FS_RNIJ9MH_14))
-           (portRef D (instanceRef wb_adr_RNO_0_1))
-           (portRef C (instanceRef wb_we_RNO_4))
-           (portRef A (instanceRef wb_adr_RNO_1_1))
-           (portRef B (instanceRef wb_we_RNO))
-           (portRef A (instanceRef wb_we_RNO_3))
-          ))
-          (net N_577 (joined
-           (portRef Z (instanceRef FS_RNI6JJA_8))
-           (portRef D (instanceRef wb_we_RNO_4))
-           (portRef D (instanceRef CKE_6_iv_i_a2_3))
-           (portRef C (instanceRef wb_adr_RNO_1_1))
-           (portRef B (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0))
-          ))
-          (net N_569 (joined
-           (portRef Z (instanceRef FS_RNI9Q57_13))
-           (portRef B (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0))
-           (portRef B (instanceRef wb_adr_RNO_1_1))
-           (portRef C (instanceRef wb_dati_7_0_a2_1_7))
-           (portRef C (instanceRef wb_dati_7_0_o2_0_2))
-          ))
-          (net N_584 (joined
-           (portRef Z (instanceRef wb_we_RNO_1))
-           (portRef C (instanceRef wb_we_RNO))
-          ))
-          (net N_393 (joined
-           (portRef Z (instanceRef wb_we_RNO_3))
-           (portRef B (instanceRef wb_we_RNO_2))
-          ))
-          (net N_422 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_7))
-           (portRef A (instanceRef wb_dati_7_0_7))
-          ))
-          (net N_642 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_5_4))
-           (portRef D (instanceRef wb_dati_7_0_a2_7))
-           (portRef C (instanceRef wb_adr_7_0_0))
-           (portRef A (instanceRef wb_dati_7_0_a2_5_RNIC22J_4))
-          ))
-          (net N_424 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_1_7))
-           (portRef B (instanceRef wb_dati_7_0_7))
-          ))
-          (net N_254 (joined
-           (portRef Z (instanceRef nCS_6_u_i_o2_0))
-           (portRef A (instanceRef nCS_6_u_i_a2_0))
-           (portRef C (instanceRef un1_LEDEN13_2_i_o2_2_0))
-           (portRef B (instanceRef nCS_6_u_i_a2_4_RNICJKD2))
-           (portRef B (instanceRef nCAS_0io_RNO_0))
-          ))
-          (net N_489 (joined
-           (portRef Z (instanceRef CKE_6_iv_i_a2_3))
-           (portRef C (instanceRef Ready_0_sqmuxa_0_a2_6_a2))
-           (portRef C (instanceRef CKE_6_iv_i_0))
-           (portRef D (instanceRef nCS_6_u_i_a2_4))
-          ))
-          (net N_567 (joined
-           (portRef Z (instanceRef nCAS_s_i_o2))
-           (portRef B (instanceRef nCAS_0io_RNO))
-          ))
-          (net N_639 (joined
-           (portRef Z (instanceRef RA_42_0_RNO_10))
-           (portRef B (instanceRef RA_42_0_10))
-          ))
-          (net N_364 (joined
-           (portRef Z (instanceRef un1_LEDEN13_2_i_a2_0))
-           (portRef A (instanceRef un1_LEDEN13_2_i_0_0))
-          ))
-          (net N_456 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_1_0))
-           (portRef D (instanceRef wb_dati_7_0_a2_1_0_0))
-           (portRef C (instanceRef CKE_6_iv_i_a2_3))
-          ))
-          (net N_349 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_3_4))
-           (portRef C (instanceRef wb_dati_7_0_4))
-          ))
-          (net N_621 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_6_1))
-           (portRef D (instanceRef wb_dati_7_0_a2_3_4))
-           (portRef C (instanceRef wb_dati_7_0_RNO_7))
-           (portRef D (instanceRef wb_adr_7_0_a2_0_0))
-           (portRef B (instanceRef wb_dati_7_0_1))
-           (portRef A (instanceRef wb_dati_7_0_6))
-          ))
-          (net N_351 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_6))
-           (portRef B (instanceRef wb_dati_7_0_1_6))
-          ))
-          (net N_378 (joined
-           (portRef Z (instanceRef wb_adr_7_0_a2_2_0))
-           (portRef B (instanceRef wb_adr_7_0_4_0))
-          ))
-          (net N_394 (joined
-           (portRef Z (instanceRef wb_we_RNO_4))
-           (portRef C (instanceRef wb_we_RNO_2))
-          ))
-          (net N_628 (joined
-           (portRef Z (instanceRef nCS_6_u_i_a2_4))
-           (portRef C (instanceRef nCS_6_u_i_1))
-           (portRef C (instanceRef nCS_6_u_i_a2_4_RNICJKD2))
-           (portRef A (instanceRef nCS_6_u_i_a2_4_RNI3A062))
-          ))
-          (net N_570 (joined
-           (portRef Z (instanceRef nCS_6_u_i_o2))
-           (portRef B (instanceRef nCS_6_u_i_1))
-          ))
-          (net N_345 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_4))
-           (portRef A (instanceRef wb_dati_7_0_4))
-           (portRef A (instanceRef wb_dati_7_0_2))
-           (portRef A (instanceRef wb_dati_7_0_5))
-          ))
-          (net N_346 (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_5_RNIC22J_4))
-           (portRef A (instanceRef wb_dati_7_0_1_6))
-           (portRef B (instanceRef wb_dati_7_0_4))
-          ))
-          (net (rename un1_wb_adr_0_sqmuxa_2_1_0 "un1_wb_adr_0_sqmuxa_2_1[0]") (joined
-           (portRef Z (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0))
-           (portRef C (instanceRef CmdBitbangMXO2_RNI8CSO1))
-           (portRef C (instanceRef wb_we_RNO_0))
-          ))
-          (net N_376 (joined
-           (portRef Z (instanceRef wb_adr_7_0_a2_0_0))
-           (portRef B (instanceRef wb_adr_7_0_0))
-          ))
-          (net N_586 (joined
-           (portRef Z (instanceRef un1_LEDEN13_2_i_o2_0))
-           (portRef D (instanceRef un1_LEDEN13_2_i_0_0))
-          ))
-          (net N_627 (joined
-           (portRef Z (instanceRef FS_RNIOD6E_0_8))
-           (portRef B (instanceRef wb_dati_7_0_0_3))
-           (portRef C (instanceRef wb_dati_7_0_a2_4))
-           (portRef C (instanceRef wb_dati_7_0_1))
-           (portRef B (instanceRef wb_dati_7_0_6))
-          ))
-          (net N_644 (joined
-           (portRef Z (instanceRef FS_RNIOD6E_8))
-           (portRef D (instanceRef wb_dati_7_0_a2_4))
-           (portRef C (instanceRef wb_dati_7_0_2_3))
-          ))
-          (net N_572 (joined
-           (portRef Z (instanceRef S_r_i_o2_1))
-           (portRef B (instanceRef S_RNO_1))
-          ))
-          (net N_395 (joined
-           (portRef Z (instanceRef wb_cyc_stb_RNO_0))
-           (portRef B (instanceRef wb_cyc_stb_RNO))
-          ))
-          (net (rename wb_dati_7_0_RNO_7 "wb_dati_7_0_RNO[7]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_RNO_7))
-           (portRef C (instanceRef wb_dati_7_0_7))
-          ))
-          (net (rename wb_dati_7_0_a2_0_1_7 "wb_dati_7_0_a2_0_1[7]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_0_2_7))
-           (portRef D (instanceRef wb_dati_7_0_RNO_7))
-          ))
-          (net (rename wb_dati_7_0_a2_0_6 "wb_dati_7_0_a2_0[6]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_0_0_6))
-           (portRef D (instanceRef wb_dati_7_0_a2_6))
-           (portRef A (instanceRef wb_dati_7_0_0_RNO_7))
-          ))
-          (net N_576_i (joined
-           (portRef Z (instanceRef S_RNII9DO1_2_1))
-           (portRef SP (instanceRef CmdBitbangMXO2))
-           (portRef SP (instanceRef CmdExecMXO2))
-           (portRef SP (instanceRef CmdLEDGet))
-           (portRef SP (instanceRef CmdLEDSet))
-           (portRef SP (instanceRef CmdRWMaskSet))
-           (portRef SP (instanceRef CmdSetRWBankFFLED))
-           (portRef SP (instanceRef CmdSetRWBankFFMXO2))
-           (portRef SP (instanceRef CmdTout_2))
-           (portRef SP (instanceRef CmdTout_1))
-           (portRef SP (instanceRef CmdTout_0))
-           (portRef SP (instanceRef Dout_0io_7))
-           (portRef SP (instanceRef Dout_0io_6))
-           (portRef SP (instanceRef Dout_0io_5))
-           (portRef SP (instanceRef Dout_0io_4))
-           (portRef SP (instanceRef Dout_0io_3))
-           (portRef SP (instanceRef Dout_0io_2))
-           (portRef SP (instanceRef Dout_0io_1))
-           (portRef SP (instanceRef Dout_0io_0))
+          (net (rename RC_3_2 "RC_3[2]") (joined
+           (portRef (member rc_3 0) (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RC_2))
           ))
           (net RDOE_i (joined
-           (portRef Z (instanceRef nWE80_pad_RNI3ICD))
+           (portRef RDOE_i_1z (instanceRef ram2e_ufm))
            (portRef T (instanceRef RD_pad_0))
            (portRef T (instanceRef RD_pad_1))
            (portRef T (instanceRef RD_pad_2))
@@ -3205,174 +4928,69 @@
            (portRef T (instanceRef RD_pad_6))
            (portRef T (instanceRef RD_pad_7))
           ))
-          (net N_6_i (joined
-           (portRef Z (instanceRef DOEEN_RNO))
-           (portRef D (instanceRef DOEEN))
+          (net N_263_i (joined
+           (portRef N_263_i_1z (instanceRef ram2e_ufm))
+           (portRef I (instanceRef RD_pad_3))
           ))
-          (net N_358_i (joined
-           (portRef Z (instanceRef DQMH_0io_RNO))
-           (portRef D (instanceRef DQMH_0io))
+          (net N_370_i (joined
+           (portRef N_370_i (instanceRef ram2e_ufm))
+           (portRef D (instanceRef nCAS))
           ))
-          (net N_28_i (joined
-           (portRef Z (instanceRef DQML_0io_RNO))
-           (portRef D (instanceRef DQML_0io))
+          (net N_359_i (joined
+           (portRef N_359_i (instanceRef ram2e_ufm))
+           (portRef D (instanceRef nRWE))
           ))
-          (net N_129_i (joined
-           (portRef Z (instanceRef S_RNO_3))
+          (net N_372_i (joined
+           (portRef N_372_i (instanceRef ram2e_ufm))
            (portRef D (instanceRef S_3))
           ))
-          (net N_131_i (joined
-           (portRef Z (instanceRef S_RNO_2))
+          (net N_361_i (joined
+           (portRef N_361_i (instanceRef ram2e_ufm))
            (portRef D (instanceRef S_2))
           ))
-          (net N_133_i (joined
-           (portRef Z (instanceRef S_RNO_1))
+          (net N_362_i (joined
+           (portRef N_362_i (instanceRef ram2e_ufm))
            (portRef D (instanceRef S_1))
           ))
-          (net N_561_i (joined
-           (portRef Z (instanceRef nCAS_0io_RNO))
-           (portRef D (instanceRef nCAS_0io))
-          ))
-          (net nRAS_2_iv_i (joined
-           (portRef Z (instanceRef nRAS_2_iv_i))
-           (portRef D (instanceRef nRAS_0io))
-          ))
-          (net N_559_i (joined
-           (portRef Z (instanceRef nCS_0io_RNO))
-           (portRef D (instanceRef nCS_0io))
-          ))
-          (net N_553_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_2))
-           (portRef D (instanceRef RA_0io_2))
-          ))
-          (net N_558_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_1))
-           (portRef D (instanceRef RA_0io_1))
-          ))
-          (net N_127_i (joined
-           (portRef Z (instanceRef RA_RNO_0))
-           (portRef D (instanceRef RA_0))
-          ))
-          (net N_59_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_9))
-           (portRef D (instanceRef RA_0io_9))
-          ))
-          (net N_49_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_8))
-           (portRef D (instanceRef RA_0io_8))
-          ))
-          (net N_549_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_7))
-           (portRef D (instanceRef RA_0io_7))
-          ))
-          (net N_550_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_6))
-           (portRef D (instanceRef RA_0io_6))
-          ))
-          (net N_551_i (joined
-           (portRef Z (instanceRef RA_0io_RNO_4))
-           (portRef D (instanceRef RA_0io_4))
-          ))
-          (net N_552_i (joined
-           (portRef Z (instanceRef RA_RNO_3))
-           (portRef D (instanceRef RA_3))
-          ))
-          (net N_510_i (joined
-           (portRef Z (instanceRef CS_RNO_2))
-           (portRef D (instanceRef CS_2))
+          (net N_358_i (joined
+           (portRef N_358_i (instanceRef ram2e_ufm))
+           (portRef D (instanceRef nRAS))
           ))
           (net un1_CS_0_sqmuxa_i (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F))
+           (portRef un1_CS_0_sqmuxa_i (instanceRef ram2e_ufm))
            (portRef CD (instanceRef CS_2))
            (portRef CD (instanceRef CS_1))
            (portRef CD (instanceRef CS_0))
           ))
-          (net N_511_i (joined
-           (portRef Z (instanceRef CS_RNO_1))
-           (portRef D (instanceRef CS_1))
-          ))
-          (net N_504_i (joined
-           (portRef Z (instanceRef CS_RNO_0))
+          (net N_547_i (joined
+           (portRef N_547_i (instanceRef ram2e_ufm))
            (portRef D (instanceRef CS_0))
           ))
-          (net N_556_i (joined
-           (portRef Z (instanceRef CmdTout_RNO_2))
+          (net N_360_i (joined
+           (portRef N_360_i_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef RC_0))
+          ))
+          (net N_369_i (joined
+           (portRef N_369_i_1z (instanceRef ram2e_ufm))
            (portRef D (instanceRef CmdTout_2))
           ))
-          (net N_555_i (joined
-           (portRef Z (instanceRef CmdTout_RNO_1))
+          (net N_368_i (joined
+           (portRef N_368_i_1z (instanceRef ram2e_ufm))
            (portRef D (instanceRef CmdTout_1))
           ))
-          (net wb_adr_0_sqmuxa_i (joined
-           (portRef Z (instanceRef wb_req_RNO_0))
-           (portRef SP (instanceRef wb_req))
+          (net N_225_i (joined
+           (portRef N_225_i_1z (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef BA_0io_1))
+           (portRef SP (instanceRef BA_0io_0))
           ))
-          (net (rename un1_wb_adr_0_sqmuxa_2_i_0 "un1_wb_adr_0_sqmuxa_2_i[0]") (joined
-           (portRef Z (instanceRef CmdBitbangMXO2_RNI8CSO1))
-           (portRef SP (instanceRef wb_adr_7))
-           (portRef SP (instanceRef wb_adr_6))
-           (portRef SP (instanceRef wb_adr_5))
-           (portRef SP (instanceRef wb_adr_4))
-           (portRef SP (instanceRef wb_adr_3))
-           (portRef SP (instanceRef wb_adr_2))
-           (portRef SP (instanceRef wb_adr_1))
-           (portRef SP (instanceRef wb_adr_0))
-           (portRef SP (instanceRef wb_dati_7))
-           (portRef SP (instanceRef wb_dati_6))
-           (portRef SP (instanceRef wb_dati_5))
-           (portRef SP (instanceRef wb_dati_4))
-           (portRef SP (instanceRef wb_dati_3))
-           (portRef SP (instanceRef wb_dati_2))
-           (portRef SP (instanceRef wb_dati_1))
-           (portRef SP (instanceRef wb_dati_0))
+          (net N_201_i (joined
+           (portRef N_201_i_1z (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef DQMH_0io))
+           (portRef SP (instanceRef DQML_0io))
           ))
-          (net (rename un1_wb_cyc_stb_0_sqmuxa_1_i_0 "un1_wb_cyc_stb_0_sqmuxa_1_i[0]") (joined
-           (portRef Z (instanceRef wb_we_RNO_0))
-           (portRef SP (instanceRef wb_we))
-          ))
-          (net N_39_i (joined
-           (portRef Z (instanceRef wb_adr_RNO_7))
-           (portRef D (instanceRef wb_adr_7))
-          ))
-          (net N_41_i (joined
-           (portRef Z (instanceRef wb_adr_RNO_3))
-           (portRef D (instanceRef wb_adr_3))
-          ))
-          (net N_43_i (joined
-           (portRef Z (instanceRef wb_adr_RNO_2))
-           (portRef D (instanceRef wb_adr_2))
-          ))
-          (net N_292_i (joined
-           (portRef Z (instanceRef RWMask_RNO_0))
-           (portRef D (instanceRef RWMask_0))
-          ))
-          (net N_291_i (joined
-           (portRef Z (instanceRef RWMask_RNO_1))
-           (portRef D (instanceRef RWMask_1))
-          ))
-          (net N_290_i (joined
-           (portRef Z (instanceRef RWMask_RNO_2))
-           (portRef D (instanceRef RWMask_2))
-          ))
-          (net N_289_i (joined
-           (portRef Z (instanceRef RWMask_RNO_3))
-           (portRef D (instanceRef RWMask_3))
-          ))
-          (net N_288_i (joined
-           (portRef Z (instanceRef RWMask_RNO_4))
-           (portRef D (instanceRef RWMask_4))
-          ))
-          (net N_287_i (joined
-           (portRef Z (instanceRef RWMask_RNO_5))
-           (portRef D (instanceRef RWMask_5))
-          ))
-          (net N_286_i (joined
-           (portRef Z (instanceRef RWMask_RNO_6))
-           (portRef D (instanceRef RWMask_6))
-          ))
-          (net un1_nCS61_1_i (joined
-           (portRef Z (instanceRef nRWE_r_0_RNO))
-           (portRef A (instanceRef nRWE_r_0))
+          (net N_507_i (joined
+           (portRef N_507_i_1z (instanceRef ram2e_ufm))
+           (portRef D (instanceRef DQML_0io))
           ))
           (net (rename FS_cry_0 "FS_cry[0]") (joined
            (portRef COUT (instanceRef FS_cry_0_0))
@@ -3470,205 +5088,6 @@
            (portRef S0 (instanceRef FS_s_0_15))
            (portRef D (instanceRef FS_15))
           ))
-          (net wb_reqc_i (joined
-           (portRef Z (instanceRef wb_req_RNO))
-           (portRef D (instanceRef wb_req))
-          ))
-          (net wb_reqc_1 (joined
-           (portRef Z (instanceRef wb_reqc_1))
-           (portRef D (instanceRef RA_0io_RNO_11))
-           (portRef D (instanceRef CKE_6_iv_i_0_1))
-           (portRef D (instanceRef wb_req_RNO))
-           (portRef D (instanceRef S_RNO_1))
-           (portRef D (instanceRef RA_0io_RNO_9))
-           (portRef D (instanceRef CmdBitbangMXO2_RNI8CSO1))
-           (portRef D (instanceRef wb_we_RNO_0))
-           (portRef A (instanceRef wb_reqc_1_RNIEO5C1))
-           (portRef B (instanceRef wb_req_RNO_0))
-           (portRef B (instanceRef FS_RNI5OOF1_15))
-           (portRef D (instanceRef wb_reqc_1_RNIRU4M1))
-          ))
-          (net CKE_6_iv_i_a2_0 (joined
-           (portRef Z (instanceRef CKE_6_iv_i_0_1_RNO))
-           (portRef A (instanceRef CKE_6_iv_i_0_1))
-          ))
-          (net wb_adr_7_5_214_a2_2_0 (joined
-           (portRef Z (instanceRef wb_adr_RNO_3_1))
-           (portRef D (instanceRef wb_adr_RNO_1_1))
-          ))
-          (net DQML_s_i_a2_0 (joined
-           (portRef Z (instanceRef DQML_0io_RNO_0))
-           (portRef A (instanceRef DQML_0io_RNO))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_2_2 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_2_4 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_2))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_1_2 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_1_4 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_1))
-          ))
-          (net (rename S_s_0_1_0 "S_s_0_1[0]") (joined
-           (portRef Z (instanceRef S_s_0_1_0))
-           (portRef D (instanceRef S_s_0_0))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_1 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_2))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_3_0 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_0))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_3_2 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_4_2 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_a2_4_4 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_4))
-          ))
-          (net CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0 (joined
-           (portRef Z (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0))
-           (portRef B (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0))
-          ))
-          (net wb_adr_7_5_214_0_1 (joined
-           (portRef Z (instanceRef wb_adr_RNO_1_1))
-           (portRef D (instanceRef wb_adr_RNO_1))
-          ))
-          (net CmdLEDGet_4_u_0_0_a2_0_2 (joined
-           (portRef Z (instanceRef CmdLEDGet_4_u_0_0_a2_0_2))
-           (portRef B (instanceRef CmdLEDGet_4_u_0_0_0))
-          ))
-          (net wb_we_7_iv_0_0_0_1 (joined
-           (portRef Z (instanceRef wb_we_RNO_2))
-           (portRef D (instanceRef wb_we_RNO))
-          ))
-          (net (rename wb_adr_7_0_a2_5_0_0 "wb_adr_7_0_a2_5_0[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_a2_5_0_0))
-           (portRef D (instanceRef wb_adr_7_0_1_0))
-          ))
-          (net (rename wb_adr_7_0_a2_0_0 "wb_adr_7_0_a2_0[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_a2_0_0_0))
-           (portRef D (instanceRef wb_adr_7_0_0_0))
-          ))
-          (net (rename wb_dati_7_0_a2_4_0_7 "wb_dati_7_0_a2_4_0[7]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0_RNO_7))
-           (portRef D (instanceRef wb_dati_7_0_0_7))
-          ))
-          (net (rename wb_dati_7_0_a2_2_0_1 "wb_dati_7_0_a2_2_0[1]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_2_0_1))
-           (portRef D (instanceRef wb_dati_7_0_0_1))
-          ))
-          (net CmdBitbangMXO2_4_u_0_0_a2_0_1 (joined
-           (portRef Z (instanceRef CmdBitbangMXO2_4_u_0_0_a2_0_1))
-           (portRef B (instanceRef CmdBitbangMXO2_4_u_0_0_0))
-          ))
-          (net CKE_6_iv_i_0_1 (joined
-           (portRef Z (instanceRef CKE_6_iv_i_0_1))
-           (portRef A (instanceRef CKE_6_iv_i_0))
-          ))
-          (net (rename un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0 "un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0]") (joined
-           (portRef Z (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0))
-           (portRef D (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0))
-          ))
-          (net (rename wb_dati_7_0_a2_1_0 "wb_dati_7_0_a2_1[0]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_a2_1_0_0))
-           (portRef D (instanceRef wb_dati_7_0_0))
-          ))
-          (net (rename un1_RWMask_0_sqmuxa_1_i_a2_0_1_0 "un1_RWMask_0_sqmuxa_1_i_a2_0_1[0]") (joined
-           (portRef Z (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0))
-           (portRef D (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0))
-          ))
-          (net Ready_0_sqmuxa_0_a2_6_a2_2 (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4))
-          ))
-          (net Ready_0_sqmuxa_0_a2_6_a2_4 (joined
-           (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4))
-           (portRef D (instanceRef Ready_0_sqmuxa_0_a2_6_a2))
-          ))
-          (net nCS_6_u_i_a2_1 (joined
-           (portRef Z (instanceRef nCS_6_u_i_a2_1_0))
-           (portRef D (instanceRef nCS_6_u_i_1))
-          ))
-          (net (rename wb_dati_7_0_a2_2_1_3 "wb_dati_7_0_a2_2_1[3]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_2_RNO_3))
-           (portRef D (instanceRef wb_dati_7_0_2_3))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_0 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_0))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_2))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_2 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_2))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F))
-          ))
-          (net un1_CS_0_sqmuxa_0_0_3 (joined
-           (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_3))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F))
-          ))
-          (net (rename wb_dati_7_0_0_1 "wb_dati_7_0_0[1]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0_1))
-           (portRef D (instanceRef wb_dati_7_0_1))
-          ))
-          (net (rename wb_dati_7_0_o2_0_2 "wb_dati_7_0_o2_0[2]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_o2_0_2))
-           (portRef D (instanceRef wb_dati_7_0_2))
-           (portRef D (instanceRef wb_dati_7_0_5))
-          ))
-          (net nCAS_s_i_tz_0 (joined
-           (portRef Z (instanceRef nCAS_0io_RNO_0))
-           (portRef D (instanceRef nCAS_0io_RNO))
-          ))
-          (net (rename wb_dati_7_0_1_6 "wb_dati_7_0_1[6]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_1_6))
-           (portRef C (instanceRef wb_dati_7_0_6))
-          ))
-          (net (rename wb_dati_7_0_0_7 "wb_dati_7_0_0[7]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0_7))
-           (portRef D (instanceRef wb_dati_7_0_7))
-          ))
-          (net (rename wb_dati_7_0_0_3 "wb_dati_7_0_0[3]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0_3))
-           (portRef B (instanceRef wb_dati_7_0_3))
-          ))
-          (net (rename wb_dati_7_0_2_3 "wb_dati_7_0_2[3]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_2_3))
-           (portRef C (instanceRef wb_dati_7_0_3))
-          ))
-          (net nCS_6_u_i_0 (joined
-           (portRef Z (instanceRef nCS_6_u_i_0))
-           (portRef B (instanceRef nCS_0io_RNO))
-          ))
-          (net (rename wb_adr_7_0_0_0 "wb_adr_7_0_0[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_0_0))
-           (portRef C (instanceRef wb_adr_7_0_4_0))
-          ))
-          (net (rename wb_adr_7_0_1_0 "wb_adr_7_0_1[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_1_0))
-           (portRef D (instanceRef wb_adr_7_0_4_0))
-          ))
-          (net (rename wb_adr_7_0_4_0 "wb_adr_7_0_4[0]") (joined
-           (portRef Z (instanceRef wb_adr_7_0_4_0))
-           (portRef D (instanceRef wb_adr_7_0_0))
-          ))
-          (net (rename wb_dati_7_0_0_4 "wb_dati_7_0_0[4]") (joined
-           (portRef Z (instanceRef wb_dati_7_0_0_4))
-           (portRef D (instanceRef wb_dati_7_0_4))
-          ))
           (net (rename FS_cry_0_S0_0 "FS_cry_0_S0[0]") (joined
            (portRef S0 (instanceRef FS_cry_0_0))
           ))
@@ -3678,42 +5097,45 @@
           (net (rename FS_s_0_COUT_15 "FS_s_0_COUT[15]") (joined
            (portRef COUT (instanceRef FS_s_0_15))
           ))
-          (net (rename Dout_0__CN "Dout_0_.CN") (joined
-           (portRef Z (instanceRef Vout_0__CN))
-           (portRef SCLK (instanceRef Dout_0io_7))
-           (portRef SCLK (instanceRef Dout_0io_6))
-           (portRef SCLK (instanceRef Dout_0io_5))
-           (portRef SCLK (instanceRef Dout_0io_4))
-           (portRef SCLK (instanceRef Dout_0io_3))
-           (portRef SCLK (instanceRef Dout_0io_2))
-           (portRef SCLK (instanceRef Dout_0io_1))
-           (portRef SCLK (instanceRef Dout_0io_0))
-           (portRef SCLK (instanceRef Vout_0io_7))
-           (portRef SCLK (instanceRef Vout_0io_6))
-           (portRef SCLK (instanceRef Vout_0io_5))
-           (portRef SCLK (instanceRef Vout_0io_4))
-           (portRef SCLK (instanceRef Vout_0io_3))
-           (portRef SCLK (instanceRef Vout_0io_2))
-           (portRef SCLK (instanceRef Vout_0io_1))
-           (portRef SCLK (instanceRef Vout_0io_0))
+          (net (rename CKEout_CN "CKEout.CN") (joined
+           (portRef Z (instanceRef nCASout_CN))
+           (portRef SCLK (instanceRef CKEout_0io))
+           (portRef SCLK (instanceRef RAout_0io_11))
+           (portRef SCLK (instanceRef RAout_0io_10))
+           (portRef SCLK (instanceRef RAout_0io_9))
+           (portRef SCLK (instanceRef RAout_0io_8))
+           (portRef SCLK (instanceRef RAout_0io_7))
+           (portRef SCLK (instanceRef RAout_0io_6))
+           (portRef SCLK (instanceRef RAout_0io_5))
+           (portRef SCLK (instanceRef RAout_0io_4))
+           (portRef SCLK (instanceRef RAout_0io_3))
+           (portRef SCLK (instanceRef RAout_0io_2))
+           (portRef SCLK (instanceRef RAout_0io_1))
+           (portRef SCLK (instanceRef RAout_0io_0))
+           (portRef SCLK (instanceRef nCASout_0io))
+           (portRef SCLK (instanceRef nRASout_0io))
+           (portRef SCLK (instanceRef nRWEout_0io))
           ))
           (net VCC (joined
            (portRef Z (instanceRef VCC))
            (portRef B0 (instanceRef FS_cry_0_0))
-           (portRef SP (instanceRef BA_0io_1))
-           (portRef SP (instanceRef BA_0io_0))
-           (portRef SP (instanceRef CKE_0io))
-           (portRef SP (instanceRef DQMH_0io))
-           (portRef SP (instanceRef DQML_0io))
-           (portRef SP (instanceRef RA_0io_11))
-           (portRef SP (instanceRef RA_0io_10))
-           (portRef SP (instanceRef RA_0io_9))
-           (portRef SP (instanceRef RA_0io_8))
-           (portRef SP (instanceRef nCAS_0io))
-           (portRef SP (instanceRef nCS_0io))
-           (portRef SP (instanceRef nRAS_0io))
-           (portRef SP (instanceRef nRWE_0io))
-           (portRef SP (instanceRef PHI1reg_0io))
+           (portRef SP (instanceRef CKEout_0io))
+           (portRef SP (instanceRef RAout_0io_11))
+           (portRef SP (instanceRef RAout_0io_10))
+           (portRef SP (instanceRef RAout_0io_9))
+           (portRef SP (instanceRef RAout_0io_8))
+           (portRef SP (instanceRef RAout_0io_7))
+           (portRef SP (instanceRef RAout_0io_6))
+           (portRef SP (instanceRef RAout_0io_5))
+           (portRef SP (instanceRef RAout_0io_4))
+           (portRef SP (instanceRef RAout_0io_3))
+           (portRef SP (instanceRef RAout_0io_2))
+           (portRef SP (instanceRef RAout_0io_1))
+           (portRef SP (instanceRef RAout_0io_0))
+           (portRef SP (instanceRef nCASout_0io))
+           (portRef SP (instanceRef nRASout_0io))
+           (portRef SP (instanceRef nRWEout_0io))
+           (portRef SP (instanceRef PHI1r_0io))
            (portRef GSR (instanceRef GSR_INST))
           ))
           (net GND (joined
@@ -3773,27 +5195,22 @@
            (portRef D0 (instanceRef FS_s_0_15))
            (portRef C0 (instanceRef FS_s_0_15))
            (portRef B0 (instanceRef FS_s_0_15))
-           (portRef CD (instanceRef CKE_0io))
+           (portRef I (instanceRef nCSout_pad))
+           (portRef CD (instanceRef CKEout_0io))
            (portRef PD (instanceRef DQMH_0io))
            (portRef PD (instanceRef DQML_0io))
-           (portRef CD (instanceRef Dout_0io_7))
-           (portRef CD (instanceRef Dout_0io_6))
-           (portRef CD (instanceRef Dout_0io_5))
-           (portRef CD (instanceRef Dout_0io_4))
-           (portRef CD (instanceRef Dout_0io_3))
-           (portRef CD (instanceRef Dout_0io_2))
-           (portRef CD (instanceRef Dout_0io_1))
-           (portRef CD (instanceRef Dout_0io_0))
-           (portRef CD (instanceRef RA_0io_11))
-           (portRef CD (instanceRef RA_0io_10))
-           (portRef CD (instanceRef RA_0io_9))
-           (portRef CD (instanceRef RA_0io_8))
-           (portRef CD (instanceRef RA_0io_7))
-           (portRef CD (instanceRef RA_0io_6))
-           (portRef CD (instanceRef RA_0io_5))
-           (portRef CD (instanceRef RA_0io_4))
-           (portRef CD (instanceRef RA_0io_2))
-           (portRef CD (instanceRef RA_0io_1))
+           (portRef CD (instanceRef RAout_0io_11))
+           (portRef CD (instanceRef RAout_0io_10))
+           (portRef CD (instanceRef RAout_0io_9))
+           (portRef CD (instanceRef RAout_0io_8))
+           (portRef CD (instanceRef RAout_0io_7))
+           (portRef CD (instanceRef RAout_0io_6))
+           (portRef CD (instanceRef RAout_0io_5))
+           (portRef CD (instanceRef RAout_0io_4))
+           (portRef CD (instanceRef RAout_0io_3))
+           (portRef CD (instanceRef RAout_0io_2))
+           (portRef CD (instanceRef RAout_0io_1))
+           (portRef CD (instanceRef RAout_0io_0))
            (portRef CD (instanceRef Vout_0io_7))
            (portRef CD (instanceRef Vout_0io_6))
            (portRef CD (instanceRef Vout_0io_5))
@@ -3802,25 +5219,22 @@
            (portRef CD (instanceRef Vout_0io_2))
            (portRef CD (instanceRef Vout_0io_1))
            (portRef CD (instanceRef Vout_0io_0))
-           (portRef PD (instanceRef nCAS_0io))
-           (portRef PD (instanceRef nCS_0io))
-           (portRef PD (instanceRef nRAS_0io))
-           (portRef PD (instanceRef nRWE_0io))
-           (portRef CD (instanceRef PHI1reg_0io))
+           (portRef PD (instanceRef nCASout_0io))
+           (portRef PD (instanceRef nRASout_0io))
+           (portRef PD (instanceRef nRWEout_0io))
+           (portRef CD (instanceRef PHI1r_0io))
           ))
           (net C14M_c (joined
            (portRef O (instanceRef C14M_pad))
-           (portRef C14M_c (instanceRef ufmefb))
+           (portRef C14M_c (instanceRef ram2e_ufm))
+           (portRef CK (instanceRef CKE))
            (portRef CK (instanceRef CS_2))
            (portRef CK (instanceRef CS_1))
            (portRef CK (instanceRef CS_0))
-           (portRef CK (instanceRef CmdBitbangMXO2))
-           (portRef CK (instanceRef CmdExecMXO2))
            (portRef CK (instanceRef CmdLEDGet))
            (portRef CK (instanceRef CmdLEDSet))
            (portRef CK (instanceRef CmdRWMaskSet))
            (portRef CK (instanceRef CmdSetRWBankFFLED))
-           (portRef CK (instanceRef CmdSetRWBankFFMXO2))
            (portRef CK (instanceRef CmdTout_2))
            (portRef CK (instanceRef CmdTout_1))
            (portRef CK (instanceRef CmdTout_0))
@@ -3841,9 +5255,21 @@
            (portRef CK (instanceRef FS_2))
            (portRef CK (instanceRef FS_1))
            (portRef CK (instanceRef FS_0))
-           (portRef CK (instanceRef LEDEN))
+           (portRef CK (instanceRef RA_11))
+           (portRef CK (instanceRef RA_10))
+           (portRef CK (instanceRef RA_9))
+           (portRef CK (instanceRef RA_8))
+           (portRef CK (instanceRef RA_7))
+           (portRef CK (instanceRef RA_6))
+           (portRef CK (instanceRef RA_5))
+           (portRef CK (instanceRef RA_4))
            (portRef CK (instanceRef RA_3))
+           (portRef CK (instanceRef RA_2))
+           (portRef CK (instanceRef RA_1))
            (portRef CK (instanceRef RA_0))
+           (portRef CK (instanceRef RC_2))
+           (portRef CK (instanceRef RC_1))
+           (portRef CK (instanceRef RC_0))
            (portRef CK (instanceRef RWBank_7))
            (portRef CK (instanceRef RWBank_6))
            (portRef CK (instanceRef RWBank_5))
@@ -3852,61 +5278,30 @@
            (portRef CK (instanceRef RWBank_2))
            (portRef CK (instanceRef RWBank_1))
            (portRef CK (instanceRef RWBank_0))
-           (portRef CK (instanceRef RWMask_7))
-           (portRef CK (instanceRef RWMask_6))
-           (portRef CK (instanceRef RWMask_5))
-           (portRef CK (instanceRef RWMask_4))
-           (portRef CK (instanceRef RWMask_3))
-           (portRef CK (instanceRef RWMask_2))
-           (portRef CK (instanceRef RWMask_1))
-           (portRef CK (instanceRef RWMask_0))
            (portRef CK (instanceRef RWSel))
            (portRef CK (instanceRef Ready))
            (portRef CK (instanceRef S_3))
            (portRef CK (instanceRef S_2))
            (portRef CK (instanceRef S_1))
            (portRef CK (instanceRef S_0))
-           (portRef CK (instanceRef wb_adr_7))
-           (portRef CK (instanceRef wb_adr_6))
-           (portRef CK (instanceRef wb_adr_5))
-           (portRef CK (instanceRef wb_adr_4))
-           (portRef CK (instanceRef wb_adr_3))
-           (portRef CK (instanceRef wb_adr_2))
-           (portRef CK (instanceRef wb_adr_1))
-           (portRef CK (instanceRef wb_adr_0))
-           (portRef CK (instanceRef wb_cyc_stb))
-           (portRef CK (instanceRef wb_dati_7))
-           (portRef CK (instanceRef wb_dati_6))
-           (portRef CK (instanceRef wb_dati_5))
-           (portRef CK (instanceRef wb_dati_4))
-           (portRef CK (instanceRef wb_dati_3))
-           (portRef CK (instanceRef wb_dati_2))
-           (portRef CK (instanceRef wb_dati_1))
-           (portRef CK (instanceRef wb_dati_0))
-           (portRef CK (instanceRef wb_req))
-           (portRef CK (instanceRef wb_rst))
-           (portRef CK (instanceRef wb_we))
+           (portRef CK (instanceRef VOEEN))
+           (portRef CK (instanceRef nCAS))
+           (portRef CK (instanceRef nRAS))
+           (portRef CK (instanceRef nRWE))
            (portRef SCLK (instanceRef BA_0io_1))
            (portRef SCLK (instanceRef BA_0io_0))
-           (portRef SCLK (instanceRef CKE_0io))
            (portRef SCLK (instanceRef DQMH_0io))
            (portRef SCLK (instanceRef DQML_0io))
-           (portRef SCLK (instanceRef RA_0io_11))
-           (portRef SCLK (instanceRef RA_0io_10))
-           (portRef SCLK (instanceRef RA_0io_9))
-           (portRef SCLK (instanceRef RA_0io_8))
-           (portRef SCLK (instanceRef RA_0io_7))
-           (portRef SCLK (instanceRef RA_0io_6))
-           (portRef SCLK (instanceRef RA_0io_5))
-           (portRef SCLK (instanceRef RA_0io_4))
-           (portRef SCLK (instanceRef RA_0io_2))
-           (portRef SCLK (instanceRef RA_0io_1))
-           (portRef SCLK (instanceRef nCAS_0io))
-           (portRef SCLK (instanceRef nCS_0io))
-           (portRef SCLK (instanceRef nRAS_0io))
-           (portRef SCLK (instanceRef nRWE_0io))
-           (portRef SCLK (instanceRef PHI1reg_0io))
-           (portRef A (instanceRef Vout_0__CN))
+           (portRef SCLK (instanceRef Vout_0io_7))
+           (portRef SCLK (instanceRef Vout_0io_6))
+           (portRef SCLK (instanceRef Vout_0io_5))
+           (portRef SCLK (instanceRef Vout_0io_4))
+           (portRef SCLK (instanceRef Vout_0io_3))
+           (portRef SCLK (instanceRef Vout_0io_2))
+           (portRef SCLK (instanceRef Vout_0io_1))
+           (portRef SCLK (instanceRef Vout_0io_0))
+           (portRef SCLK (instanceRef PHI1r_0io))
+           (portRef A (instanceRef nCASout_CN))
           ))
           (net C14M (joined
            (portRef C14M)
@@ -3915,15 +5310,15 @@
           (net PHI1_c (joined
            (portRef O (instanceRef PHI1_pad))
            (portRef A (instanceRef SZ0Z_1))
-           (portRef I (instanceRef nVOE_pad))
-           (portRef D (instanceRef PHI1reg_0io))
+           (portRef A (instanceRef nVOE_pad_RNO))
+           (portRef D (instanceRef PHI1r_0io))
           ))
           (net PHI1 (joined
            (portRef PHI1)
            (portRef I (instanceRef PHI1_pad))
           ))
           (net LED_c (joined
-           (portRef Z (instanceRef LED_pad_RNO))
+           (portRef LED_c (instanceRef ram2e_ufm))
            (portRef I (instanceRef LED_pad))
           ))
           (net LED (joined
@@ -3932,29 +5327,18 @@
           ))
           (net nWE_c (joined
            (portRef O (instanceRef nWE_pad))
-           (portRef D (instanceRef RWSel_2))
-           (portRef C (instanceRef nDOE_pad_RNO))
+           (portRef nWE_c (instanceRef ram2e_ufm))
           ))
           (net nWE (joined
            (portRef nWE)
            (portRef I (instanceRef nWE_pad))
           ))
-          (net nWE80_c (joined
-           (portRef O (instanceRef nWE80_pad))
-           (portRef B (instanceRef nWE80_pad_RNI3ICD))
-           (portRef D (instanceRef nRWE_r_0))
-          ))
           (net nWE80 (joined
            (portRef nWE80)
-           (portRef I (instanceRef nWE80_pad))
           ))
           (net nEN80_c (joined
            (portRef O (instanceRef nEN80_pad))
-           (portRef A (instanceRef nWE80_pad_RNI3ICD))
-           (portRef B (instanceRef LED_pad_RNO))
-           (portRef B (instanceRef nDOE_pad_RNO))
-           (portRef D (instanceRef nCS_6_u_i_0))
-           (portRef A (instanceRef CKE_6_iv_i_0_1_RNO))
+           (portRef nEN80_c (instanceRef ram2e_ufm))
           ))
           (net nEN80 (joined
            (portRef nEN80)
@@ -3962,7 +5346,7 @@
           ))
           (net nC07X_c (joined
            (portRef O (instanceRef nC07X_pad))
-           (portRef C (instanceRef RWSel_2))
+           (portRef nC07X_c (instanceRef ram2e_ufm))
           ))
           (net nC07X (joined
            (portRef nC07X)
@@ -3970,7 +5354,7 @@
           ))
           (net (rename Ain_c_0 "Ain_c[0]") (joined
            (portRef O (instanceRef Ain_pad_0))
-           (portRef A (instanceRef RA_RNO_0))
+           (portRef (member ain_c 7) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_0 "Ain[0]") (joined
            (portRef (member ain 7))
@@ -3978,7 +5362,7 @@
           ))
           (net (rename Ain_c_1 "Ain_c[1]") (joined
            (portRef O (instanceRef Ain_pad_1))
-           (portRef A (instanceRef RA_0io_RNO_1))
+           (portRef (member ain_c 6) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_1 "Ain[1]") (joined
            (portRef (member ain 6))
@@ -3986,7 +5370,7 @@
           ))
           (net (rename Ain_c_2 "Ain_c[2]") (joined
            (portRef O (instanceRef Ain_pad_2))
-           (portRef A (instanceRef RA_0io_RNO_2))
+           (portRef (member ain_c 5) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_2 "Ain[2]") (joined
            (portRef (member ain 5))
@@ -3994,7 +5378,7 @@
           ))
           (net (rename Ain_c_3 "Ain_c[3]") (joined
            (portRef O (instanceRef Ain_pad_3))
-           (portRef A (instanceRef RA_RNO_3))
+           (portRef (member ain_c 4) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_3 "Ain[3]") (joined
            (portRef (member ain 4))
@@ -4002,7 +5386,7 @@
           ))
           (net (rename Ain_c_4 "Ain_c[4]") (joined
            (portRef O (instanceRef Ain_pad_4))
-           (portRef A (instanceRef RA_0io_RNO_4))
+           (portRef (member ain_c 3) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_4 "Ain[4]") (joined
            (portRef (member ain 3))
@@ -4010,7 +5394,7 @@
           ))
           (net (rename Ain_c_5 "Ain_c[5]") (joined
            (portRef O (instanceRef Ain_pad_5))
-           (portRef A (instanceRef RA_42_3_0_5))
+           (portRef (member ain_c 2) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_5 "Ain[5]") (joined
            (portRef (member ain 2))
@@ -4018,7 +5402,7 @@
           ))
           (net (rename Ain_c_6 "Ain_c[6]") (joined
            (portRef O (instanceRef Ain_pad_6))
-           (portRef A (instanceRef RA_0io_RNO_6))
+           (portRef (member ain_c 1) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_6 "Ain[6]") (joined
            (portRef (member ain 1))
@@ -4026,7 +5410,7 @@
           ))
           (net (rename Ain_c_7 "Ain_c[7]") (joined
            (portRef O (instanceRef Ain_pad_7))
-           (portRef A (instanceRef RA_0io_RNO_7))
+           (portRef (member ain_c 0) (instanceRef ram2e_ufm))
           ))
           (net (rename Ain_7 "Ain[7]") (joined
            (portRef (member ain 0))
@@ -4034,20 +5418,7 @@
           ))
           (net (rename Din_c_0 "Din_c[0]") (joined
            (portRef O (instanceRef Din_pad_0))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_0))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_17))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_16))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_13))
-           (portRef A (instanceRef LEDEN_RNO))
-           (portRef A (instanceRef CmdBitbangMXO2_4_u_0_0_a2_0_1))
-           (portRef A (instanceRef RWMask_RNO_0))
-           (portRef A (instanceRef CmdLEDGet_4_u_0_0_a2_0_2))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_2))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_15))
-           (portRef A (instanceRef RWBank_5_0_0))
-           (portRef A (instanceRef wb_we_RNO_2))
-           (portRef A (instanceRef wb_adr_7_0_0_0))
-           (portRef I (instanceRef RD_pad_0))
+           (portRef (member din_c 7) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_0 "Din[0]") (joined
            (portRef (member din 7))
@@ -4055,20 +5426,7 @@
           ))
           (net (rename Din_c_1 "Din_c[1]") (joined
            (portRef O (instanceRef Din_pad_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_0))
-           (portRef C (instanceRef CmdBitbangMXO2_4_u_0_0_a2_1))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_11))
-           (portRef A (instanceRef RWMask_RNO_1))
-           (portRef B (instanceRef CmdLEDGet_4_u_0_0_a2_0_2))
-           (portRef A (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_15))
-           (portRef A (instanceRef RWBank_5_0_1))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_o2_0))
-           (portRef A (instanceRef CmdLEDSet_4_u_0_0_a2_0))
-           (portRef A (instanceRef wb_adr_RNO_1))
-           (portRef A (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_0))
-           (portRef I (instanceRef RD_pad_1))
+           (portRef (member din_c 6) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_1 "Din[1]") (joined
            (portRef (member din 6))
@@ -4076,17 +5434,7 @@
           ))
           (net (rename Din_c_2 "Din_c[2]") (joined
            (portRef O (instanceRef Din_pad_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_0))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_17))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_16))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_13))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_12))
-           (portRef B (instanceRef CmdBitbangMXO2_4_u_0_0_a2_0_1))
-           (portRef A (instanceRef wb_adr_RNO_2))
-           (portRef A (instanceRef RWMask_RNO_2))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_15))
-           (portRef A (instanceRef RWBank_5_0_2))
-           (portRef I (instanceRef RD_pad_2))
+           (portRef (member din_c 5) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_2 "Din[2]") (joined
            (portRef (member din 5))
@@ -4094,17 +5442,7 @@
           ))
           (net (rename Din_c_3 "Din_c[3]") (joined
            (portRef O (instanceRef Din_pad_3))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_0))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_17))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_16))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_12))
-           (portRef C (instanceRef CmdBitbangMXO2_4_u_0_0_a2_0_1))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6))
-           (portRef A (instanceRef wb_adr_RNO_3))
-           (portRef A (instanceRef RWMask_RNO_3))
-           (portRef A (instanceRef RWBank_5_0_3))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4))
-           (portRef I (instanceRef RD_pad_3))
+           (portRef (member din_c 4) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_3 "Din[3]") (joined
            (portRef (member din 4))
@@ -4112,19 +5450,7 @@
           ))
           (net (rename Din_c_4 "Din_c[4]") (joined
            (portRef O (instanceRef Din_pad_4))
-           (portRef B (instanceRef CmdBitbangMXO2_4_u_0_0_a2_1))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_11))
-           (portRef A (instanceRef wb_adr_RNO_4))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6))
-           (portRef A (instanceRef RWMask_RNO_4))
-           (portRef C (instanceRef CmdLEDGet_4_u_0_0_a2_0_2))
-           (portRef B (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_2))
-           (portRef A (instanceRef RWBank_5_0_4))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2))
-           (portRef B (instanceRef CmdLEDSet_4_u_0_0_a2_0))
-           (portRef B (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_0))
-           (portRef I (instanceRef RD_pad_4))
+           (portRef (member din_c 3) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_4 "Din[4]") (joined
            (portRef (member din 3))
@@ -4132,14 +5458,7 @@
           ))
           (net (rename Din_c_5 "Din_c[5]") (joined
            (portRef O (instanceRef Din_pad_5))
-           (portRef A (instanceRef wb_adr_RNO_5))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_7))
-           (portRef A (instanceRef RWMask_RNO_5))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_2))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_2))
-           (portRef A (instanceRef RWBank_5_0_5))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_2))
-           (portRef I (instanceRef RD_pad_5))
+           (portRef (member din_c 2) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_5 "Din[5]") (joined
            (portRef (member din 2))
@@ -4147,15 +5466,7 @@
           ))
           (net (rename Din_c_6 "Din_c[6]") (joined
            (portRef O (instanceRef Din_pad_6))
-           (portRef A (instanceRef wb_adr_RNO_6))
-           (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6))
-           (portRef A (instanceRef RWMask_RNO_6))
-           (portRef A (instanceRef RWBank_5_0_6))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_10))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_1))
-           (portRef I (instanceRef RD_pad_6))
+           (portRef (member din_c 1) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_6 "Din[6]") (joined
            (portRef (member din 1))
@@ -4163,85 +5474,46 @@
           ))
           (net (rename Din_c_7 "Din_c[7]") (joined
            (portRef O (instanceRef Din_pad_7))
-           (portRef A (instanceRef RWMask_RNO_7))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_7))
-           (portRef A (instanceRef wb_adr_RNO_7))
-           (portRef A (instanceRef RWBank_5_0_0_7))
-           (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_2))
-           (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4))
-           (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_2))
-           (portRef I (instanceRef RD_pad_7))
+           (portRef (member din_c 0) (instanceRef ram2e_ufm))
           ))
           (net (rename Din_7 "Din[7]") (joined
            (portRef (member din 0))
            (portRef I (instanceRef Din_pad_7))
           ))
-          (net (rename Dout_c_0 "Dout_c[0]") (joined
-           (portRef Q (instanceRef Dout_0io_0))
-           (portRef I (instanceRef Dout_pad_0))
-          ))
           (net (rename Dout_0 "Dout[0]") (joined
            (portRef O (instanceRef Dout_pad_0))
            (portRef (member dout 7))
           ))
-          (net (rename Dout_c_1 "Dout_c[1]") (joined
-           (portRef Q (instanceRef Dout_0io_1))
-           (portRef I (instanceRef Dout_pad_1))
-          ))
           (net (rename Dout_1 "Dout[1]") (joined
            (portRef O (instanceRef Dout_pad_1))
            (portRef (member dout 6))
           ))
-          (net (rename Dout_c_2 "Dout_c[2]") (joined
-           (portRef Q (instanceRef Dout_0io_2))
-           (portRef I (instanceRef Dout_pad_2))
-          ))
           (net (rename Dout_2 "Dout[2]") (joined
            (portRef O (instanceRef Dout_pad_2))
            (portRef (member dout 5))
           ))
-          (net (rename Dout_c_3 "Dout_c[3]") (joined
-           (portRef Q (instanceRef Dout_0io_3))
-           (portRef I (instanceRef Dout_pad_3))
-          ))
           (net (rename Dout_3 "Dout[3]") (joined
            (portRef O (instanceRef Dout_pad_3))
            (portRef (member dout 4))
           ))
-          (net (rename Dout_c_4 "Dout_c[4]") (joined
-           (portRef Q (instanceRef Dout_0io_4))
-           (portRef I (instanceRef Dout_pad_4))
-          ))
           (net (rename Dout_4 "Dout[4]") (joined
            (portRef O (instanceRef Dout_pad_4))
            (portRef (member dout 3))
           ))
-          (net (rename Dout_c_5 "Dout_c[5]") (joined
-           (portRef Q (instanceRef Dout_0io_5))
-           (portRef I (instanceRef Dout_pad_5))
-          ))
           (net (rename Dout_5 "Dout[5]") (joined
            (portRef O (instanceRef Dout_pad_5))
            (portRef (member dout 2))
           ))
-          (net (rename Dout_c_6 "Dout_c[6]") (joined
-           (portRef Q (instanceRef Dout_0io_6))
-           (portRef I (instanceRef Dout_pad_6))
-          ))
           (net (rename Dout_6 "Dout[6]") (joined
            (portRef O (instanceRef Dout_pad_6))
            (portRef (member dout 1))
           ))
-          (net (rename Dout_c_7 "Dout_c[7]") (joined
-           (portRef Q (instanceRef Dout_0io_7))
-           (portRef I (instanceRef Dout_pad_7))
-          ))
           (net (rename Dout_7 "Dout[7]") (joined
            (portRef O (instanceRef Dout_pad_7))
            (portRef (member dout 0))
           ))
           (net nDOE_c (joined
-           (portRef Z (instanceRef nDOE_pad_RNO))
+           (portRef nDOE_c (instanceRef ram2e_ufm))
            (portRef I (instanceRef nDOE_pad))
           ))
           (net nDOE (joined
@@ -4312,49 +5584,49 @@
            (portRef O (instanceRef Vout_pad_7))
            (portRef (member vout 0))
           ))
+          (net nVOE_c (joined
+           (portRef Z (instanceRef nVOE_pad_RNO))
+           (portRef I (instanceRef nVOE_pad))
+          ))
           (net nVOE (joined
            (portRef O (instanceRef nVOE_pad))
            (portRef nVOE)
           ))
-          (net CKE_c (joined
-           (portRef Q (instanceRef CKE_0io))
-           (portRef I (instanceRef CKE_pad))
+          (net CKEout_c (joined
+           (portRef Q (instanceRef CKEout_0io))
+           (portRef I (instanceRef CKEout_pad))
           ))
-          (net CKE (joined
-           (portRef O (instanceRef CKE_pad))
-           (portRef CKE)
+          (net CKEout (joined
+           (portRef O (instanceRef CKEout_pad))
+           (portRef CKEout)
           ))
-          (net nCS_c (joined
-           (portRef Q (instanceRef nCS_0io))
-           (portRef I (instanceRef nCS_pad))
+          (net nCSout (joined
+           (portRef O (instanceRef nCSout_pad))
+           (portRef nCSout)
           ))
-          (net nCS (joined
-           (portRef O (instanceRef nCS_pad))
-           (portRef nCS)
+          (net nRASout_c (joined
+           (portRef Q (instanceRef nRASout_0io))
+           (portRef I (instanceRef nRASout_pad))
           ))
-          (net nRAS_c (joined
-           (portRef Q (instanceRef nRAS_0io))
-           (portRef I (instanceRef nRAS_pad))
+          (net nRASout (joined
+           (portRef O (instanceRef nRASout_pad))
+           (portRef nRASout)
           ))
-          (net nRAS (joined
-           (portRef O (instanceRef nRAS_pad))
-           (portRef nRAS)
+          (net nCASout_c (joined
+           (portRef Q (instanceRef nCASout_0io))
+           (portRef I (instanceRef nCASout_pad))
           ))
-          (net nCAS_c (joined
-           (portRef Q (instanceRef nCAS_0io))
-           (portRef I (instanceRef nCAS_pad))
+          (net nCASout (joined
+           (portRef O (instanceRef nCASout_pad))
+           (portRef nCASout)
           ))
-          (net nCAS (joined
-           (portRef O (instanceRef nCAS_pad))
-           (portRef nCAS)
+          (net nRWEout_c (joined
+           (portRef Q (instanceRef nRWEout_0io))
+           (portRef I (instanceRef nRWEout_pad))
           ))
-          (net nRWE_c (joined
-           (portRef Q (instanceRef nRWE_0io))
-           (portRef I (instanceRef nRWE_pad))
-          ))
-          (net nRWE (joined
-           (portRef O (instanceRef nRWE_pad))
-           (portRef nRWE)
+          (net nRWEout (joined
+           (portRef O (instanceRef nRWEout_pad))
+           (portRef nRWEout)
           ))
           (net (rename BA_c_0 "BA_c[0]") (joined
            (portRef Q (instanceRef BA_0io_0))
@@ -4372,175 +5644,101 @@
            (portRef O (instanceRef BA_pad_1))
            (portRef (member ba 0))
           ))
-          (net (rename RA_c_0 "RA_c[0]") (joined
-           (portRef Q (instanceRef RA_0))
-           (portRef A (instanceRef RWSel_2))
-           (portRef I (instanceRef RA_pad_0))
+          (net (rename RAout_c_0 "RAout_c[0]") (joined
+           (portRef Q (instanceRef RAout_0io_0))
+           (portRef I (instanceRef RAout_pad_0))
           ))
-          (net (rename RA_0 "RA[0]") (joined
-           (portRef O (instanceRef RA_pad_0))
-           (portRef (member ra 11))
+          (net (rename RAout_0 "RAout[0]") (joined
+           (portRef O (instanceRef RAout_pad_0))
+           (portRef (member raout 11))
           ))
-          (net (rename RA_c_1 "RA_c[1]") (joined
-           (portRef Q (instanceRef RA_0io_1))
-           (portRef I (instanceRef RA_pad_1))
+          (net (rename RAout_c_1 "RAout_c[1]") (joined
+           (portRef Q (instanceRef RAout_0io_1))
+           (portRef I (instanceRef RAout_pad_1))
           ))
-          (net (rename RA_1 "RA[1]") (joined
-           (portRef O (instanceRef RA_pad_1))
-           (portRef (member ra 10))
+          (net (rename RAout_1 "RAout[1]") (joined
+           (portRef O (instanceRef RAout_pad_1))
+           (portRef (member raout 10))
           ))
-          (net (rename RA_c_2 "RA_c[2]") (joined
-           (portRef Q (instanceRef RA_0io_2))
-           (portRef I (instanceRef RA_pad_2))
+          (net (rename RAout_c_2 "RAout_c[2]") (joined
+           (portRef Q (instanceRef RAout_0io_2))
+           (portRef I (instanceRef RAout_pad_2))
           ))
-          (net (rename RA_2 "RA[2]") (joined
-           (portRef O (instanceRef RA_pad_2))
-           (portRef (member ra 9))
+          (net (rename RAout_2 "RAout[2]") (joined
+           (portRef O (instanceRef RAout_pad_2))
+           (portRef (member raout 9))
           ))
-          (net (rename RA_c_3 "RA_c[3]") (joined
-           (portRef Q (instanceRef RA_3))
-           (portRef B (instanceRef RWSel_2))
-           (portRef I (instanceRef RA_pad_3))
+          (net (rename RAout_c_3 "RAout_c[3]") (joined
+           (portRef Q (instanceRef RAout_0io_3))
+           (portRef I (instanceRef RAout_pad_3))
           ))
-          (net (rename RA_3 "RA[3]") (joined
-           (portRef O (instanceRef RA_pad_3))
-           (portRef (member ra 8))
+          (net (rename RAout_3 "RAout[3]") (joined
+           (portRef O (instanceRef RAout_pad_3))
+           (portRef (member raout 8))
           ))
-          (net (rename RA_c_4 "RA_c[4]") (joined
-           (portRef Q (instanceRef RA_0io_4))
-           (portRef I (instanceRef RA_pad_4))
+          (net (rename RAout_c_4 "RAout_c[4]") (joined
+           (portRef Q (instanceRef RAout_0io_4))
+           (portRef I (instanceRef RAout_pad_4))
           ))
-          (net (rename RA_4 "RA[4]") (joined
-           (portRef O (instanceRef RA_pad_4))
-           (portRef (member ra 7))
+          (net (rename RAout_4 "RAout[4]") (joined
+           (portRef O (instanceRef RAout_pad_4))
+           (portRef (member raout 7))
           ))
-          (net (rename RA_c_5 "RA_c[5]") (joined
-           (portRef Q (instanceRef RA_0io_5))
-           (portRef I (instanceRef RA_pad_5))
+          (net (rename RAout_c_5 "RAout_c[5]") (joined
+           (portRef Q (instanceRef RAout_0io_5))
+           (portRef I (instanceRef RAout_pad_5))
           ))
-          (net (rename RA_5 "RA[5]") (joined
-           (portRef O (instanceRef RA_pad_5))
-           (portRef (member ra 6))
+          (net (rename RAout_5 "RAout[5]") (joined
+           (portRef O (instanceRef RAout_pad_5))
+           (portRef (member raout 6))
           ))
-          (net (rename RA_c_6 "RA_c[6]") (joined
-           (portRef Q (instanceRef RA_0io_6))
-           (portRef I (instanceRef RA_pad_6))
+          (net (rename RAout_c_6 "RAout_c[6]") (joined
+           (portRef Q (instanceRef RAout_0io_6))
+           (portRef I (instanceRef RAout_pad_6))
           ))
-          (net (rename RA_6 "RA[6]") (joined
-           (portRef O (instanceRef RA_pad_6))
-           (portRef (member ra 5))
+          (net (rename RAout_6 "RAout[6]") (joined
+           (portRef O (instanceRef RAout_pad_6))
+           (portRef (member raout 5))
           ))
-          (net (rename RA_c_7 "RA_c[7]") (joined
-           (portRef Q (instanceRef RA_0io_7))
-           (portRef I (instanceRef RA_pad_7))
+          (net (rename RAout_c_7 "RAout_c[7]") (joined
+           (portRef Q (instanceRef RAout_0io_7))
+           (portRef I (instanceRef RAout_pad_7))
           ))
-          (net (rename RA_7 "RA[7]") (joined
-           (portRef O (instanceRef RA_pad_7))
-           (portRef (member ra 4))
+          (net (rename RAout_7 "RAout[7]") (joined
+           (portRef O (instanceRef RAout_pad_7))
+           (portRef (member raout 4))
           ))
-          (net (rename RA_c_8 "RA_c[8]") (joined
-           (portRef Q (instanceRef RA_0io_8))
-           (portRef I (instanceRef RA_pad_8))
+          (net (rename RAout_c_8 "RAout_c[8]") (joined
+           (portRef Q (instanceRef RAout_0io_8))
+           (portRef I (instanceRef RAout_pad_8))
           ))
-          (net (rename RA_8 "RA[8]") (joined
-           (portRef O (instanceRef RA_pad_8))
-           (portRef (member ra 3))
+          (net (rename RAout_8 "RAout[8]") (joined
+           (portRef O (instanceRef RAout_pad_8))
+           (portRef (member raout 3))
           ))
-          (net (rename RA_c_9 "RA_c[9]") (joined
-           (portRef Q (instanceRef RA_0io_9))
-           (portRef I (instanceRef RA_pad_9))
+          (net (rename RAout_c_9 "RAout_c[9]") (joined
+           (portRef Q (instanceRef RAout_0io_9))
+           (portRef I (instanceRef RAout_pad_9))
           ))
-          (net (rename RA_9 "RA[9]") (joined
-           (portRef O (instanceRef RA_pad_9))
-           (portRef (member ra 2))
+          (net (rename RAout_9 "RAout[9]") (joined
+           (portRef O (instanceRef RAout_pad_9))
+           (portRef (member raout 2))
           ))
-          (net (rename RA_c_10 "RA_c[10]") (joined
-           (portRef Q (instanceRef RA_0io_10))
-           (portRef I (instanceRef RA_pad_10))
+          (net (rename RAout_c_10 "RAout_c[10]") (joined
+           (portRef Q (instanceRef RAout_0io_10))
+           (portRef I (instanceRef RAout_pad_10))
           ))
-          (net (rename RA_10 "RA[10]") (joined
-           (portRef O (instanceRef RA_pad_10))
-           (portRef (member ra 1))
+          (net (rename RAout_10 "RAout[10]") (joined
+           (portRef O (instanceRef RAout_pad_10))
+           (portRef (member raout 1))
           ))
-          (net (rename RA_c_11 "RA_c[11]") (joined
-           (portRef Q (instanceRef RA_0io_11))
-           (portRef I (instanceRef RA_pad_11))
+          (net (rename RAout_c_11 "RAout_c[11]") (joined
+           (portRef Q (instanceRef RAout_0io_11))
+           (portRef I (instanceRef RAout_pad_11))
           ))
-          (net (rename RA_11 "RA[11]") (joined
-           (portRef O (instanceRef RA_pad_11))
-           (portRef (member ra 0))
-          ))
-          (net (rename RD_in_0 "RD_in[0]") (joined
-           (portRef O (instanceRef RD_pad_0))
-           (portRef D (instanceRef Dout_0io_0))
-           (portRef D (instanceRef Vout_0io_0))
-          ))
-          (net (rename RD_0 "RD[0]") (joined
-           (portRef B (instanceRef RD_pad_0))
-           (portRef (member rd 7))
-          ))
-          (net (rename RD_in_1 "RD_in[1]") (joined
-           (portRef O (instanceRef RD_pad_1))
-           (portRef D (instanceRef Dout_0io_1))
-           (portRef D (instanceRef Vout_0io_1))
-          ))
-          (net (rename RD_1 "RD[1]") (joined
-           (portRef B (instanceRef RD_pad_1))
-           (portRef (member rd 6))
-          ))
-          (net (rename RD_in_2 "RD_in[2]") (joined
-           (portRef O (instanceRef RD_pad_2))
-           (portRef D (instanceRef Dout_0io_2))
-           (portRef D (instanceRef Vout_0io_2))
-          ))
-          (net (rename RD_2 "RD[2]") (joined
-           (portRef B (instanceRef RD_pad_2))
-           (portRef (member rd 5))
-          ))
-          (net (rename RD_in_3 "RD_in[3]") (joined
-           (portRef O (instanceRef RD_pad_3))
-           (portRef D (instanceRef Dout_0io_3))
-           (portRef D (instanceRef Vout_0io_3))
-          ))
-          (net (rename RD_3 "RD[3]") (joined
-           (portRef B (instanceRef RD_pad_3))
-           (portRef (member rd 4))
-          ))
-          (net (rename RD_in_4 "RD_in[4]") (joined
-           (portRef O (instanceRef RD_pad_4))
-           (portRef D (instanceRef Dout_0io_4))
-           (portRef D (instanceRef Vout_0io_4))
-          ))
-          (net (rename RD_4 "RD[4]") (joined
-           (portRef B (instanceRef RD_pad_4))
-           (portRef (member rd 3))
-          ))
-          (net (rename RD_in_5 "RD_in[5]") (joined
-           (portRef O (instanceRef RD_pad_5))
-           (portRef D (instanceRef Dout_0io_5))
-           (portRef D (instanceRef Vout_0io_5))
-          ))
-          (net (rename RD_5 "RD[5]") (joined
-           (portRef B (instanceRef RD_pad_5))
-           (portRef (member rd 2))
-          ))
-          (net (rename RD_in_6 "RD_in[6]") (joined
-           (portRef O (instanceRef RD_pad_6))
-           (portRef D (instanceRef Dout_0io_6))
-           (portRef D (instanceRef Vout_0io_6))
-          ))
-          (net (rename RD_6 "RD[6]") (joined
-           (portRef B (instanceRef RD_pad_6))
-           (portRef (member rd 1))
-          ))
-          (net (rename RD_in_7 "RD_in[7]") (joined
-           (portRef O (instanceRef RD_pad_7))
-           (portRef D (instanceRef Dout_0io_7))
-           (portRef D (instanceRef Vout_0io_7))
-          ))
-          (net (rename RD_7 "RD[7]") (joined
-           (portRef B (instanceRef RD_pad_7))
-           (portRef (member rd 0))
+          (net (rename RAout_11 "RAout[11]") (joined
+           (portRef O (instanceRef RAout_pad_11))
+           (portRef (member raout 0))
           ))
           (net DQML_c (joined
            (portRef Q (instanceRef DQML_0io))
@@ -4558,14 +5756,110 @@
            (portRef O (instanceRef DQMH_pad))
            (portRef DQMH)
           ))
-          (net N_876_0 (joined
+          (net (rename RD_in_0 "RD_in[0]") (joined
+           (portRef O (instanceRef RD_pad_0))
+           (portRef I (instanceRef Dout_pad_0))
+           (portRef D (instanceRef Vout_0io_0))
+          ))
+          (net (rename RD_0 "RD[0]") (joined
+           (portRef B (instanceRef RD_pad_0))
+           (portRef (member rd 7))
+          ))
+          (net (rename RD_in_1 "RD_in[1]") (joined
+           (portRef O (instanceRef RD_pad_1))
+           (portRef I (instanceRef Dout_pad_1))
+           (portRef D (instanceRef Vout_0io_1))
+          ))
+          (net (rename RD_1 "RD[1]") (joined
+           (portRef B (instanceRef RD_pad_1))
+           (portRef (member rd 6))
+          ))
+          (net (rename RD_in_2 "RD_in[2]") (joined
+           (portRef O (instanceRef RD_pad_2))
+           (portRef I (instanceRef Dout_pad_2))
+           (portRef D (instanceRef Vout_0io_2))
+          ))
+          (net (rename RD_2 "RD[2]") (joined
+           (portRef B (instanceRef RD_pad_2))
+           (portRef (member rd 5))
+          ))
+          (net (rename RD_in_3 "RD_in[3]") (joined
+           (portRef O (instanceRef RD_pad_3))
+           (portRef I (instanceRef Dout_pad_3))
+           (portRef D (instanceRef Vout_0io_3))
+          ))
+          (net (rename RD_3 "RD[3]") (joined
+           (portRef B (instanceRef RD_pad_3))
+           (portRef (member rd 4))
+          ))
+          (net (rename RD_in_4 "RD_in[4]") (joined
+           (portRef O (instanceRef RD_pad_4))
+           (portRef I (instanceRef Dout_pad_4))
+           (portRef D (instanceRef Vout_0io_4))
+          ))
+          (net (rename RD_4 "RD[4]") (joined
+           (portRef B (instanceRef RD_pad_4))
+           (portRef (member rd 3))
+          ))
+          (net (rename RD_in_5 "RD_in[5]") (joined
+           (portRef O (instanceRef RD_pad_5))
+           (portRef I (instanceRef Dout_pad_5))
+           (portRef D (instanceRef Vout_0io_5))
+          ))
+          (net (rename RD_5 "RD[5]") (joined
+           (portRef B (instanceRef RD_pad_5))
+           (portRef (member rd 2))
+          ))
+          (net (rename RD_in_6 "RD_in[6]") (joined
+           (portRef O (instanceRef RD_pad_6))
+           (portRef I (instanceRef Dout_pad_6))
+           (portRef D (instanceRef Vout_0io_6))
+          ))
+          (net (rename RD_6 "RD[6]") (joined
+           (portRef B (instanceRef RD_pad_6))
+           (portRef (member rd 1))
+          ))
+          (net (rename RD_in_7 "RD_in[7]") (joined
+           (portRef O (instanceRef RD_pad_7))
+           (portRef I (instanceRef Dout_pad_7))
+           (portRef D (instanceRef Vout_0io_7))
+          ))
+          (net (rename RD_7 "RD[7]") (joined
+           (portRef B (instanceRef RD_pad_7))
+           (portRef (member rd 0))
+          ))
+          (net N_1080_0 (joined
+           (portRef Z (instanceRef DOEEN_RNO))
+           (portRef CD (instanceRef DOEEN))
+          ))
+          (net N_1026_0 (joined
            (portRef Z (instanceRef Ready_RNO))
            (portRef D (instanceRef Ready))
           ))
-          (net N_566_i (joined
-           (portRef Z (instanceRef wb_reqc_1_RNIEO5C1))
-           (portRef CD (instanceRef BA_0io_1))
-           (portRef CD (instanceRef BA_0io_0))
+          (net N_1078_0 (joined
+           (portRef Z (instanceRef VOEEN_RNO))
+           (portRef CD (instanceRef VOEEN))
+          ))
+          (net N_187_i (joined
+           (portRef N_187_i_1z (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef CmdLEDGet))
+           (portRef SP (instanceRef CmdLEDSet))
+           (portRef SP (instanceRef CmdRWMaskSet))
+           (portRef SP (instanceRef CmdSetRWBankFFLED))
+           (portRef SP (instanceRef RWBank_7))
+           (portRef SP (instanceRef RWBank_6))
+           (portRef SP (instanceRef RWBank_5))
+           (portRef SP (instanceRef RWBank_4))
+           (portRef SP (instanceRef RWBank_3))
+           (portRef SP (instanceRef RWBank_2))
+           (portRef SP (instanceRef RWBank_1))
+           (portRef SP (instanceRef RWBank_0))
+          ))
+          (net N_185_i (joined
+           (portRef N_185_i (instanceRef ram2e_ufm))
+           (portRef SP (instanceRef CmdTout_2))
+           (portRef SP (instanceRef CmdTout_1))
+           (portRef SP (instanceRef CmdTout_0))
           ))
           (net N_1 (joined
            (portRef CIN (instanceRef FS_cry_0_0))
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.jed b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.jed
index 12342e4..73ece0b 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.jed
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.jed
@@ -2,7 +2,7 @@
 NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
 NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
 NOTE All Rights Reserved.*
-NOTE DATE CREATED:	Thu Sep 21 05:35:21 2023*
+NOTE DATE CREATED:	Thu Dec 28 23:10:29 2023*
 NOTE DESIGN NAME:	RAM2E_LCMXO2_640HC_impl1.ncd*
 NOTE DEVICE NAME:	LCMXO2-640HC-4TQFP100*
 NOTE JEDEC FILE STATUS:	Final   Version 1.95*
@@ -10,8 +10,6 @@ NOTE PIN ASSIGNMENTS*
 NOTE PINS RD[0] : 36 : inout*
 NOTE PINS LED : 35 : out*
 NOTE PINS C14M : 62 : in*
-NOTE PINS DQMH : 49 : out*
-NOTE PINS DQML : 48 : out*
 NOTE PINS RD[7] : 43 : inout*
 NOTE PINS RD[6] : 42 : inout*
 NOTE PINS RD[5] : 41 : inout*
@@ -19,25 +17,27 @@ NOTE PINS RD[4] : 40 : inout*
 NOTE PINS RD[3] : 39 : inout*
 NOTE PINS RD[2] : 38 : inout*
 NOTE PINS RD[1] : 37 : inout*
-NOTE PINS RA[11] : 59 : out*
-NOTE PINS RA[10] : 64 : out*
-NOTE PINS RA[9] : 63 : out*
-NOTE PINS RA[8] : 65 : out*
-NOTE PINS RA[7] : 67 : out*
-NOTE PINS RA[6] : 69 : out*
-NOTE PINS RA[5] : 71 : out*
-NOTE PINS RA[4] : 75 : out*
-NOTE PINS RA[3] : 74 : out*
-NOTE PINS RA[2] : 70 : out*
-NOTE PINS RA[1] : 68 : out*
-NOTE PINS RA[0] : 66 : out*
+NOTE PINS DQMH : 49 : out*
+NOTE PINS DQML : 48 : out*
+NOTE PINS RAout[11] : 59 : out*
+NOTE PINS RAout[10] : 64 : out*
+NOTE PINS RAout[9] : 63 : out*
+NOTE PINS RAout[8] : 65 : out*
+NOTE PINS RAout[7] : 67 : out*
+NOTE PINS RAout[6] : 69 : out*
+NOTE PINS RAout[5] : 71 : out*
+NOTE PINS RAout[4] : 75 : out*
+NOTE PINS RAout[3] : 74 : out*
+NOTE PINS RAout[2] : 70 : out*
+NOTE PINS RAout[1] : 68 : out*
+NOTE PINS RAout[0] : 66 : out*
 NOTE PINS BA[1] : 60 : out*
 NOTE PINS BA[0] : 58 : out*
-NOTE PINS nRWE : 51 : out*
-NOTE PINS nCAS : 52 : out*
-NOTE PINS nRAS : 54 : out*
-NOTE PINS nCS : 57 : out*
-NOTE PINS CKE : 53 : out*
+NOTE PINS nRWEout : 51 : out*
+NOTE PINS nCASout : 52 : out*
+NOTE PINS nRASout : 54 : out*
+NOTE PINS nCSout : 57 : out*
+NOTE PINS CKEout : 53 : out*
 NOTE PINS nVOE : 10 : out*
 NOTE PINS Vout[7] : 12 : out*
 NOTE PINS Vout[6] : 14 : out*
@@ -74,7 +74,6 @@ NOTE PINS Ain[1] : 2 : in*
 NOTE PINS Ain[0] : 3 : in*
 NOTE PINS nC07X : 34 : in*
 NOTE PINS nEN80 : 82 : in*
-NOTE PINS nWE80 : 83 : in*
 NOTE PINS nWE : 29 : in*
 NOTE PINS PHI1 : 85 : in*
 QP100*
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 *
 NOTE END CONFIG DATA*
-L48896
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@@ -1432,10 +1431,10 @@ L171648
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 *
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 0000010001100000*
 NOTE User Electronic Signature Data*
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diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.mrp
index 9c54f98..fc44249 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.mrp
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.mrp
@@ -8,31 +8,31 @@ Design Information
 Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
      RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
      RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
-     loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
-     lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
-     //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml 
+     loud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
+     lpf -lpf //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
+     //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml 
 Target Vendor:  LATTICE
 Target Device:  LCMXO2-640HCTQFP100
 Target Performance:   4
 Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  09/21/23  05:34:46
+Mapped on:  12/28/23  23:09:57
 
 Design Summary
 --------------
 
-   Number of registers:    111 out of   877 (13%)
-      PFU registers:           75 out of   640 (12%)
-      PIO registers:           36 out of   237 (15%)
-   Number of SLICEs:       120 out of   320 (38%)
-      SLICEs as Logic/ROM:    120 out of   320 (38%)
+   Number of registers:    122 out of   877 (14%)
+      PFU registers:           93 out of   640 (15%)
+      PIO registers:           29 out of   237 (12%)
+   Number of SLICEs:       148 out of   320 (46%)
+      SLICEs as Logic/ROM:    148 out of   320 (46%)
       SLICEs as RAM:            0 out of   240 (0%)
       SLICEs as Carry:          9 out of   320 (3%)
-   Number of LUT4s:        239 out of   640 (37%)
-      Number used as logic LUTs:        221
+   Number of LUT4s:        296 out of   640 (46%)
+      Number used as logic LUTs:        278
       Number used as distributed RAM:     0
       Number used as ripple logic:       18
       Number used as shift registers:     0
-   Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%)
+   Number of PIO sites used: 69 + 4(JTAG) out of 79 (92%)
    Number of block RAMs:  0 out of 2 (0%)
    Number of GSRs:        0 out of 1 (0%)
    EFB used :        Yes
@@ -52,70 +52,90 @@ Design Summary
       2. Number of logic LUT4s does not include count of distributed RAM and
      ripple logic.
    Number of clocks:  1
-     Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
-   Number of Clock Enables:  11
-     Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
-     Net N_576_i: 17 loads, 9 LSLICEs
-     Net LEDEN13: 4 loads, 4 LSLICEs
-     Net nCS61: 1 loads, 1 LSLICEs
-     Net Vout3: 8 loads, 0 LSLICEs
-     Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
+     Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M )
+   Number of Clock Enables:  14
+     Net N_225_i: 2 loads, 0 LSLICEs
+     Net N_201_i: 2 loads, 0 LSLICEs
+     Net N_187_i: 11 loads, 11 LSLICEs
+     Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
+     Net RC12: 2 loads, 2 LSLICEs
+     Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs
 
                                     Page 1
 
 
 
 
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
 
 Design Summary (cont)
 ---------------------
-     Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
-     Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
-     Net N_104: 1 loads, 1 LSLICEs
-     Net N_88: 4 loads, 4 LSLICEs
-     Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
-   Number of LSRs:  5
+     Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs
+     Net N_185_i: 2 loads, 2 LSLICEs
+     Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs
+     Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs
+     Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs
+     Net N_126: 6 loads, 6 LSLICEs
+     Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs
+     Net Vout3: 8 loads, 0 LSLICEs
+   Number of LSRs:  7
      Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
+     Net BA_0_sqmuxa: 2 loads, 0 LSLICEs
      Net S[2]: 1 loads, 1 LSLICEs
-     Net N_566_i: 2 loads, 0 LSLICEs
-     Net wb_rst: 1 loads, 0 LSLICEs
-     Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
+     Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
+     Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs
+     Net N_1080_0: 1 loads, 1 LSLICEs
+     Net N_1078_0: 1 loads, 1 LSLICEs
    Number of nets driven by tri-state buffers:  0
    Top 10 highest fanout non-clock nets:
-     Net S[2]: 48 loads
-     Net S[3]: 48 loads
-     Net S[0]: 30 loads
-     Net FS[12]: 22 loads
-     Net FS[9]: 21 loads
-     Net S[1]: 21 loads
-     Net FS[10]: 20 loads
-     Net FS[11]: 19 loads
-     Net RWSel: 19 loads
-     Net FS[13]: 17 loads
+     Net S[2]: 50 loads
+     Net S[3]: 45 loads
+     Net S[0]: 37 loads
+     Net S[1]: 34 loads
+     Net FS[12]: 24 loads
+     Net FS[11]: 22 loads
+     Net FS[10]: 19 loads
+     Net FS[13]: 19 loads
+     Net FS[9]: 19 loads
+     Net FS[8]: 18 loads
 
 
 
 
-   Number of warnings:  1
+   Number of warnings:  3
    Number of errors:    0
      
 
 Design Errors/Warnings
 ----------------------
 
+WARNING - map: //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf(93): Semantic
+     error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
+     "nWE80" does not exist in the design. This preference has been disabled.
 WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
      temporarily disable certain features of the device including Power
      Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
      Functionality is restored after the Flash Memory (UFM/Configuration)
      Interface is disabled using Disable Configuration Interface command 0x26
      followed by Bypass command 0xFF. 
+WARNING - map: IO buffer missing for top level port nWE80...logic will be
+     discarded.
 
 IO (PIO) Attributes
 -------------------
 
 +---------------------+-----------+-----------+------------+
 | IO Name             | Direction | Levelmode | IO         |
+
+                                    Page 2
+
+
+
+
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
+
+IO (PIO) Attributes (cont)
+--------------------------
 |                     |           |  IO_TYPE  | Register   |
 +---------------------+-----------+-----------+------------+
 | RD[0]               | BIDIR     | LVCMOS33  |            |
@@ -124,20 +144,6 @@ IO (PIO) Attributes
 +---------------------+-----------+-----------+------------+
 | C14M                | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-
-                                    Page 2
-
-
-
-
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
-
-IO (PIO) Attributes (cont)
---------------------------
-| DQML                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
 | RD[7]               | BIDIR     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | RD[6]               | BIDIR     | LVCMOS33  |            |
@@ -152,45 +158,39 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | RD[1]               | BIDIR     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| RA[11]              | OUTPUT    | LVCMOS33  | OUT        |
+| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[10]              | OUTPUT    | LVCMOS33  | OUT        |
+| DQML                | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[9]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[11]           | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[8]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[10]           | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[7]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[9]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[6]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[8]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[5]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[7]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[4]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[6]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[3]               | OUTPUT    | LVCMOS33  |            |
+| RAout[5]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[2]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[4]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[1]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[3]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[0]               | OUTPUT    | LVCMOS33  |            |
+| RAout[2]            | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RAout[1]            | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RAout[0]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | BA[1]               | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | BA[0]               | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| nRWE                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nCAS                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nRAS                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nCS                 | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| CKE                 | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nVOE                | OUTPUT    | LVCMOS33  |            |
+| nRWEout             | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 
                                     Page 3
@@ -198,10 +198,20 @@ IO (PIO) Attributes (cont)
 
 
 
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
 
 IO (PIO) Attributes (cont)
 --------------------------
+| nCASout             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRASout             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nCSout              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| CKEout              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nVOE                | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
 | Vout[7]             | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | Vout[6]             | OUTPUT    | LVCMOS33  | OUT        |
@@ -220,21 +230,21 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | nDOE                | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[7]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[7]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[6]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[6]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[5]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[5]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[4]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[4]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[3]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[3]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[2]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[2]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[1]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[1]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[0]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[0]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Din[7]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -248,6 +258,16 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | Din[2]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
+
+                                    Page 4
+
+
+
+
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
+
+IO (PIO) Attributes (cont)
+--------------------------
 | Din[1]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Din[0]              | INPUT     | LVCMOS33  |            |
@@ -258,16 +278,6 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | Ain[5]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-
-                                    Page 4
-
-
-
-
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
-
-IO (PIO) Attributes (cont)
---------------------------
 | Ain[4]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Ain[3]              | INPUT     | LVCMOS33  |            |
@@ -282,8 +292,6 @@ IO (PIO) Attributes (cont)
 +---------------------+-----------+-----------+------------+
 | nEN80               | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| nWE80               | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
 | nWE                 | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | PHI1                | INPUT     | LVCMOS33  | IN         |
@@ -293,77 +301,84 @@ Removed logic
 -------------
 
 Block GSR_INST undriven or does not drive anything - clipped.
-Signal Dout_0_.CN was merged into signal C14M_c
-Signal GND undriven or does not drive anything - clipped.
-Signal ufmefb/VCC undriven or does not drive anything - clipped.
-Signal ufmefb/GND undriven or does not drive anything - clipped.
+Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
+Block ram2e_ufm/GND undriven or does not drive anything - clipped.
+Signal CKEout.CN was merged into signal C14M_c
+Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
 Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
 Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
-Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
-Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
-Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
-Signal ufmefb/TCOC undriven or does not drive anything - clipped.
-Signal ufmefb/TCINT undriven or does not drive anything - clipped.
-Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
-Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
-Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
 
                                     Page 5
 
 
 
 
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
 
 Removed logic (cont)
 --------------------
-Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
-Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
-Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
+     
+Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
+     
+Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
 Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
 Signal N_1 undriven or does not drive anything - clipped.
-Block Vout_0_.CN was optimized away.
-Block GND was optimized away.
-Block ufmefb/VCC was optimized away.
-Block ufmefb/GND was optimized away.
+Block nCASout.CN was optimized away.
+Block ram2e_ufm/ufmefb/VCC was optimized away.
+Block ram2e_ufm/ufmefb/GND was optimized away.
 
      
 
@@ -372,9 +387,19 @@ Embedded Functional Block Connection Summary
 
    Desired WISHBONE clock frequency: 14.4 MHz
    Clock source:                     C14M_c
-   Reset source:                     wb_rst
+   Reset source:                     ram2e_ufm/wb_rst
    Functions mode:
       I2C #1 (Primary) Function:     DISABLED
+
+                                    Page 6
+
+
+
+
+Design:  RAM2E                                         Date:  12/28/23  23:09:57
+
+Embedded Functional Block Connection Summary (cont)
+---------------------------------------------------
       I2C #2 (Secondary) Function:   DISABLED
       SPI Function:                  DISABLED
       Timer/Counter Function:        DISABLED
@@ -390,16 +415,6 @@ Embedded Functional Block Connection Summary
       None
    Timer/Counter Function Summary:
    ------------------------------
-
-                                    Page 6
-
-
-
-
-Design:  RAM2E                                         Date:  09/21/23  05:34:46
-
-Embedded Functional Block Connection Summary (cont)
----------------------------------------------------
       None
    UFM Function Summary:
    --------------------
@@ -418,7 +433,7 @@ Embedded Functional Block Connection Summary (cont)
 ASIC Components
 ---------------
 
-Instance Name: ufmefb/EFBInst_0
+Instance Name: ram2e_ufm/ufmefb/EFBInst_0
          Type: EFB
 
 Run Time and Memory Usage
@@ -426,7 +441,7 @@ Run Time and Memory Usage
 
    Total CPU Time: 0 secs  
    Total REAL Time: 0 secs  
-   Peak Memory Usage: 58 MB
+   Peak Memory Usage: 59 MB
         
 
 
@@ -436,21 +451,6 @@ Run Time and Memory Usage
 
 
 
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
 
 
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad
index 938b7ba..9a74770 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad
@@ -6,7 +6,7 @@ Performance Grade:      4
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.39
 
-Thu Sep 21 05:35:00 2023
+Thu Dec 28 23:10:10 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -23,7 +23,7 @@ Pinout by Port Name:
 | BA[0]     | 58/1     | LVCMOS33_OUT  | PR6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | BA[1]     | 60/1     | LVCMOS33_OUT  | PR6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | C14M      | 62/1     | LVCMOS33_IN   | PR5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| CKE       | 53/1     | LVCMOS33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| CKEout    | 53/1     | LVCMOS33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | DQMH      | 49/2     | LVCMOS33_OUT  | PB14D |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | DQML      | 48/2     | LVCMOS33_OUT  | PB14C |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | Din[0]    | 96/0     | LVCMOS33_IN   | PT6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
@@ -34,28 +34,28 @@ Pinout by Port Name:
 | Din[5]    | 99/0     | LVCMOS33_IN   | PT6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 | Din[6]    | 88/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 | Din[7]    | 87/0     | LVCMOS33_IN   | PT9B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4A  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL7D  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4B  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL7C  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL7B  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6A  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | LED       | 35/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | PHI1      | 85/0     | LVCMOS33_IN   | PT9D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| RA[0]     | 66/1     | LVCMOS33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[10]    | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[11]    | 59/1     | LVCMOS33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[1]     | 68/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[2]     | 70/1     | LVCMOS33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[3]     | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[4]     | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[5]     | 71/1     | LVCMOS33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[6]     | 69/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[7]     | 67/1     | LVCMOS33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[8]     | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[9]     | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[0]  | 66/1     | LVCMOS33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[10] | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[11] | 59/1     | LVCMOS33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[1]  | 68/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[2]  | 70/1     | LVCMOS33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[3]  | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[4]  | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[5]  | 71/1     | LVCMOS33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[6]  | 69/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[7]  | 67/1     | LVCMOS33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[8]  | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[9]  | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | RD[0]     | 36/2     | LVCMOS33_BIDI | PB10A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[1]     | 37/2     | LVCMOS33_BIDI | PB10B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[2]     | 38/2     | LVCMOS33_BIDI | PB10C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
@@ -73,15 +73,14 @@ Pinout by Port Name:
 | Vout[6]   | 14/3     | LVCMOS33_OUT  | PL5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | Vout[7]   | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nC07X     | 34/2     | LVCMOS33_IN   | PB6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nCAS      | 52/1     | LVCMOS33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nCS       | 57/1     | LVCMOS33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nCASout   | 52/1     | LVCMOS33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nCSout    | 57/1     | LVCMOS33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nDOE      | 20/3     | LVCMOS33_OUT  | PL7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nEN80     | 82/0     | LVCMOS33_IN   | PT10C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nRAS      | 54/1     | LVCMOS33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nRWE      | 51/1     | LVCMOS33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRASout   | 54/1     | LVCMOS33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWEout   | 51/1     | LVCMOS33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nVOE      | 10/3     | LVCMOS33_OUT  | PL3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nWE       | 29/2     | LVCMOS33_IN   | PB4C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nWE80     | 83/0     | LVCMOS33_IN   | PT10B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
 
 Vccio by Bank:
@@ -144,32 +143,32 @@ Pinout by Pin Number:
 | 47/2     |     unused, PULL:DOWN |            |               | PB14B |               |           |           |
 | 48/2     | DQML                  | LOCATED    | LVCMOS33_OUT  | PB14C | SN            |           |           |
 | 49/2     | DQMH                  | LOCATED    | LVCMOS33_OUT  | PB14D | SI/SISPI      |           |           |
-| 51/1     | nRWE                  | LOCATED    | LVCMOS33_OUT  | PR7D  |               |           |           |
-| 52/1     | nCAS                  | LOCATED    | LVCMOS33_OUT  | PR7C  |               |           |           |
-| 53/1     | CKE                   | LOCATED    | LVCMOS33_OUT  | PR7B  |               |           |           |
-| 54/1     | nRAS                  | LOCATED    | LVCMOS33_OUT  | PR7A  |               |           |           |
-| 57/1     | nCS                   | LOCATED    | LVCMOS33_OUT  | PR6D  |               |           |           |
+| 51/1     | nRWEout               | LOCATED    | LVCMOS33_OUT  | PR7D  |               |           |           |
+| 52/1     | nCASout               | LOCATED    | LVCMOS33_OUT  | PR7C  |               |           |           |
+| 53/1     | CKEout                | LOCATED    | LVCMOS33_OUT  | PR7B  |               |           |           |
+| 54/1     | nRASout               | LOCATED    | LVCMOS33_OUT  | PR7A  |               |           |           |
+| 57/1     | nCSout                | LOCATED    | LVCMOS33_OUT  | PR6D  |               |           |           |
 | 58/1     | BA[0]                 | LOCATED    | LVCMOS33_OUT  | PR6C  |               |           |           |
-| 59/1     | RA[11]                | LOCATED    | LVCMOS33_OUT  | PR6B  |               |           |           |
+| 59/1     | RAout[11]             | LOCATED    | LVCMOS33_OUT  | PR6B  |               |           |           |
 | 60/1     | BA[1]                 | LOCATED    | LVCMOS33_OUT  | PR6A  |               |           |           |
 | 62/1     | C14M                  | LOCATED    | LVCMOS33_IN   | PR5D  | PCLKC1_0      |           |           |
-| 63/1     | RA[9]                 | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0      |           |           |
-| 64/1     | RA[10]                | LOCATED    | LVCMOS33_OUT  | PR5B  |               |           |           |
-| 65/1     | RA[8]                 | LOCATED    | LVCMOS33_OUT  | PR5A  |               |           |           |
-| 66/1     | RA[0]                 | LOCATED    | LVCMOS33_OUT  | PR3D  |               |           |           |
-| 67/1     | RA[7]                 | LOCATED    | LVCMOS33_OUT  | PR3C  |               |           |           |
-| 68/1     | RA[1]                 | LOCATED    | LVCMOS33_OUT  | PR3B  |               |           |           |
-| 69/1     | RA[6]                 | LOCATED    | LVCMOS33_OUT  | PR3A  |               |           |           |
-| 70/1     | RA[2]                 | LOCATED    | LVCMOS33_OUT  | PR2D  |               |           |           |
-| 71/1     | RA[5]                 | LOCATED    | LVCMOS33_OUT  | PR2C  |               |           |           |
-| 74/1     | RA[3]                 | LOCATED    | LVCMOS33_OUT  | PR2B  |               |           |           |
-| 75/1     | RA[4]                 | LOCATED    | LVCMOS33_OUT  | PR2A  |               |           |           |
+| 63/1     | RAout[9]              | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0      |           |           |
+| 64/1     | RAout[10]             | LOCATED    | LVCMOS33_OUT  | PR5B  |               |           |           |
+| 65/1     | RAout[8]              | LOCATED    | LVCMOS33_OUT  | PR5A  |               |           |           |
+| 66/1     | RAout[0]              | LOCATED    | LVCMOS33_OUT  | PR3D  |               |           |           |
+| 67/1     | RAout[7]              | LOCATED    | LVCMOS33_OUT  | PR3C  |               |           |           |
+| 68/1     | RAout[1]              | LOCATED    | LVCMOS33_OUT  | PR3B  |               |           |           |
+| 69/1     | RAout[6]              | LOCATED    | LVCMOS33_OUT  | PR3A  |               |           |           |
+| 70/1     | RAout[2]              | LOCATED    | LVCMOS33_OUT  | PR2D  |               |           |           |
+| 71/1     | RAout[5]              | LOCATED    | LVCMOS33_OUT  | PR2C  |               |           |           |
+| 74/1     | RAout[3]              | LOCATED    | LVCMOS33_OUT  | PR2B  |               |           |           |
+| 75/1     | RAout[4]              | LOCATED    | LVCMOS33_OUT  | PR2A  |               |           |           |
 | 76/0     |     unused, PULL:DOWN |            |               | PT11D | DONE          |           |           |
 | 77/0     |     unused, PULL:DOWN |            |               | PT11C | INITN         |           |           |
 | 78/0     | Ain[4]                | LOCATED    | LVCMOS33_IN   | PT11A |               |           |           |
 | 81/0     |     unused, PULL:DOWN |            |               | PT10D | PROGRAMN      |           |           |
 | 82/0     | nEN80                 | LOCATED    | LVCMOS33_IN   | PT10C | JTAGENB       |           |           |
-| 83/0     | nWE80                 | LOCATED    | LVCMOS33_IN   | PT10B |               |           |           |
+| 83/0     |     unused, PULL:DOWN |            |               | PT10B |               |           |           |
 | 84/0     | Ain[5]                | LOCATED    | LVCMOS33_IN   | PT10A |               |           |           |
 | 85/0     | PHI1                  | LOCATED    | LVCMOS33_IN   | PT9D  | SDA/PCLKC0_0  |           |           |
 | 86/0     | Ain[6]                | LOCATED    | LVCMOS33_IN   | PT9C  | SCL/PCLKT0_0  |           |           |
@@ -213,7 +212,7 @@ LOCATE  COMP  "Ain[7]"  SITE  "8";
 LOCATE  COMP  "BA[0]"  SITE  "58";
 LOCATE  COMP  "BA[1]"  SITE  "60";
 LOCATE  COMP  "C14M"  SITE  "62";
-LOCATE  COMP  "CKE"  SITE  "53";
+LOCATE  COMP  "CKEout"  SITE  "53";
 LOCATE  COMP  "DQMH"  SITE  "49";
 LOCATE  COMP  "DQML"  SITE  "48";
 LOCATE  COMP  "Din[0]"  SITE  "96";
@@ -234,18 +233,18 @@ LOCATE  COMP  "Dout[6]"  SITE  "31";
 LOCATE  COMP  "Dout[7]"  SITE  "32";
 LOCATE  COMP  "LED"  SITE  "35";
 LOCATE  COMP  "PHI1"  SITE  "85";
-LOCATE  COMP  "RA[0]"  SITE  "66";
-LOCATE  COMP  "RA[10]"  SITE  "64";
-LOCATE  COMP  "RA[11]"  SITE  "59";
-LOCATE  COMP  "RA[1]"  SITE  "68";
-LOCATE  COMP  "RA[2]"  SITE  "70";
-LOCATE  COMP  "RA[3]"  SITE  "74";
-LOCATE  COMP  "RA[4]"  SITE  "75";
-LOCATE  COMP  "RA[5]"  SITE  "71";
-LOCATE  COMP  "RA[6]"  SITE  "69";
-LOCATE  COMP  "RA[7]"  SITE  "67";
-LOCATE  COMP  "RA[8]"  SITE  "65";
-LOCATE  COMP  "RA[9]"  SITE  "63";
+LOCATE  COMP  "RAout[0]"  SITE  "66";
+LOCATE  COMP  "RAout[10]"  SITE  "64";
+LOCATE  COMP  "RAout[11]"  SITE  "59";
+LOCATE  COMP  "RAout[1]"  SITE  "68";
+LOCATE  COMP  "RAout[2]"  SITE  "70";
+LOCATE  COMP  "RAout[3]"  SITE  "74";
+LOCATE  COMP  "RAout[4]"  SITE  "75";
+LOCATE  COMP  "RAout[5]"  SITE  "71";
+LOCATE  COMP  "RAout[6]"  SITE  "69";
+LOCATE  COMP  "RAout[7]"  SITE  "67";
+LOCATE  COMP  "RAout[8]"  SITE  "65";
+LOCATE  COMP  "RAout[9]"  SITE  "63";
 LOCATE  COMP  "RD[0]"  SITE  "36";
 LOCATE  COMP  "RD[1]"  SITE  "37";
 LOCATE  COMP  "RD[2]"  SITE  "38";
@@ -263,15 +262,14 @@ LOCATE  COMP  "Vout[5]"  SITE  "16";
 LOCATE  COMP  "Vout[6]"  SITE  "14";
 LOCATE  COMP  "Vout[7]"  SITE  "12";
 LOCATE  COMP  "nC07X"  SITE  "34";
-LOCATE  COMP  "nCAS"  SITE  "52";
-LOCATE  COMP  "nCS"  SITE  "57";
+LOCATE  COMP  "nCASout"  SITE  "52";
+LOCATE  COMP  "nCSout"  SITE  "57";
 LOCATE  COMP  "nDOE"  SITE  "20";
 LOCATE  COMP  "nEN80"  SITE  "82";
-LOCATE  COMP  "nRAS"  SITE  "54";
-LOCATE  COMP  "nRWE"  SITE  "51";
+LOCATE  COMP  "nRASout"  SITE  "54";
+LOCATE  COMP  "nRWEout"  SITE  "51";
 LOCATE  COMP  "nVOE"  SITE  "10";
 LOCATE  COMP  "nWE"  SITE  "29";
-LOCATE  COMP  "nWE80"  SITE  "83";
 
 
 
@@ -283,5 +281,5 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Sep 21 05:35:04 2023
+Thu Dec 28 23:10:13 2023
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf
index 77b562e..d59bddc 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf
@@ -1,12 +1,10 @@
 SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:34:47 2023
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:09:58 2023
 
 SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
 LOCATE COMP "RD[0]" SITE "36" ;
 LOCATE COMP "LED" SITE "35" ;
 LOCATE COMP "C14M" SITE "62" ;
-LOCATE COMP "DQMH" SITE "49" ;
-LOCATE COMP "DQML" SITE "48" ;
 LOCATE COMP "RD[7]" SITE "43" ;
 LOCATE COMP "RD[6]" SITE "42" ;
 LOCATE COMP "RD[5]" SITE "41" ;
@@ -14,25 +12,27 @@ LOCATE COMP "RD[4]" SITE "40" ;
 LOCATE COMP "RD[3]" SITE "39" ;
 LOCATE COMP "RD[2]" SITE "38" ;
 LOCATE COMP "RD[1]" SITE "37" ;
-LOCATE COMP "RA[11]" SITE "59" ;
-LOCATE COMP "RA[10]" SITE "64" ;
-LOCATE COMP "RA[9]" SITE "63" ;
-LOCATE COMP "RA[8]" SITE "65" ;
-LOCATE COMP "RA[7]" SITE "67" ;
-LOCATE COMP "RA[6]" SITE "69" ;
-LOCATE COMP "RA[5]" SITE "71" ;
-LOCATE COMP "RA[4]" SITE "75" ;
-LOCATE COMP "RA[3]" SITE "74" ;
-LOCATE COMP "RA[2]" SITE "70" ;
-LOCATE COMP "RA[1]" SITE "68" ;
-LOCATE COMP "RA[0]" SITE "66" ;
+LOCATE COMP "DQMH" SITE "49" ;
+LOCATE COMP "DQML" SITE "48" ;
+LOCATE COMP "RAout[11]" SITE "59" ;
+LOCATE COMP "RAout[10]" SITE "64" ;
+LOCATE COMP "RAout[9]" SITE "63" ;
+LOCATE COMP "RAout[8]" SITE "65" ;
+LOCATE COMP "RAout[7]" SITE "67" ;
+LOCATE COMP "RAout[6]" SITE "69" ;
+LOCATE COMP "RAout[5]" SITE "71" ;
+LOCATE COMP "RAout[4]" SITE "75" ;
+LOCATE COMP "RAout[3]" SITE "74" ;
+LOCATE COMP "RAout[2]" SITE "70" ;
+LOCATE COMP "RAout[1]" SITE "68" ;
+LOCATE COMP "RAout[0]" SITE "66" ;
 LOCATE COMP "BA[1]" SITE "60" ;
 LOCATE COMP "BA[0]" SITE "58" ;
-LOCATE COMP "nRWE" SITE "51" ;
-LOCATE COMP "nCAS" SITE "52" ;
-LOCATE COMP "nRAS" SITE "54" ;
-LOCATE COMP "nCS" SITE "57" ;
-LOCATE COMP "CKE" SITE "53" ;
+LOCATE COMP "nRWEout" SITE "51" ;
+LOCATE COMP "nCASout" SITE "52" ;
+LOCATE COMP "nRASout" SITE "54" ;
+LOCATE COMP "nCSout" SITE "57" ;
+LOCATE COMP "CKEout" SITE "53" ;
 LOCATE COMP "nVOE" SITE "10" ;
 LOCATE COMP "Vout[7]" SITE "12" ;
 LOCATE COMP "Vout[6]" SITE "14" ;
@@ -69,7 +69,6 @@ LOCATE COMP "Ain[1]" SITE "2" ;
 LOCATE COMP "Ain[0]" SITE "3" ;
 LOCATE COMP "nC07X" SITE "34" ;
 LOCATE COMP "nEN80" SITE "82" ;
-LOCATE COMP "nWE80" SITE "83" ;
 LOCATE COMP "nWE" SITE "29" ;
 LOCATE COMP "PHI1" SITE "85" ;
 FREQUENCY PORT "C14M" 14.300000 MHz ;
@@ -79,7 +78,7 @@ BLOCK ASYNCPATHS ;
 OUTPUT PORT "LED" LOAD 100.000000 pF ;
 OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
 OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
-OUTPUT PORT "CKE" LOAD 5.000000 pF ;
+OUTPUT PORT "CKEout" LOAD 5.000000 pF ;
 OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
 OUTPUT PORT "DQML" LOAD 5.000000 pF ;
 OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
@@ -90,18 +89,18 @@ OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
 OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
 OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
 OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
-OUTPUT PORT "RA[0]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[1]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[2]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[3]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[4]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[5]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[6]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[7]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[8]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[9]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[10]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[11]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ;
 OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
@@ -110,11 +109,11 @@ OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
-OUTPUT PORT "nCAS" LOAD 5.000000 pF ;
-OUTPUT PORT "nCS" LOAD 5.000000 pF ;
+OUTPUT PORT "nCASout" LOAD 5.000000 pF ;
+OUTPUT PORT "nCSout" LOAD 5.000000 pF ;
 OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
-OUTPUT PORT "nRAS" LOAD 5.000000 pF ;
-OUTPUT PORT "nRWE" LOAD 5.000000 pF ;
+OUTPUT PORT "nRASout" LOAD 5.000000 pF ;
+OUTPUT PORT "nRWEout" LOAD 5.000000 pF ;
 OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
 OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
 OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr
index dd1963b..229858a 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr
@@ -3,7 +3,7 @@
 #OS: Windows 8 6.2
 #Hostname: ZANEMACWIN11
 
-# Thu Sep 21 05:34:32 2023
+# Thu Dec 28 23:09:44 2023
 
 #Implementation: impl1
 
@@ -48,30 +48,35 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
-@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work)
+@I::"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v" (library work)
+@I::"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v" (library work)
+@I::"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v" (library work)
 Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
 Selecting top level module RAM2E
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
 Running optimization stage 1 on VHI .......
-Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
 Running optimization stage 1 on VLO .......
-Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
 Running optimization stage 1 on EFB .......
-Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
 Running optimization stage 1 on REFB .......
-Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
+Running optimization stage 1 on RAM2E_UFM .......
+Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
 Running optimization stage 1 on RAM2E .......
 Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
 Running optimization stage 2 on RAM2E .......
-Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
+Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
+Running optimization stage 2 on RAM2E_UFM .......
+@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
+Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
 Running optimization stage 2 on REFB .......
 Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
 Running optimization stage 2 on EFB .......
@@ -81,12 +86,12 @@ Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current:
 Running optimization stage 2 on VHI .......
 Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
 
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB)
+At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:32 2023
+# Thu Dec 28 23:09:45 2023
 
 ###########################################################]
 ###########################################################[
@@ -108,58 +113,58 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
 
 @N|Running in 64-bit mode
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Sep 21 05:34:33 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Sep 21 05:34:33 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
-
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:34 2023
+# Thu Dec 28 23:09:45 2023
 
 ###########################################################]
-# Thu Sep 21 05:34:34 2023
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: A:\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Dec 28 23:09:46 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Dec 28 23:09:47 2023
+
+###########################################################]
+# Thu Dec 28 23:09:47 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -178,14 +183,14 @@ Implementation : impl1
 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
 
-Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
-@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt 
-See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
+Reading constraint file: \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc
+@L: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt 
+See clock summary report "\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@@ -199,33 +204,32 @@ Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0
 Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB)
 
-@N: FX493 |Applying initial value "0" on instance PHI1reg.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance DOEEN.
-@N: FX493 |Applying initial value "0" on instance RWSel.
-@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
-@N: FX493 |Applying initial value "1" on instance DQMH.
-@N: FX493 |Applying initial value "0" on instance Ready.
 @N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 @N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
+@N: FX493 |Applying initial value "0" on instance PHI1r.
+@N: FX493 |Applying initial value "0" on instance RWSel.
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
 @N: FX493 |Applying initial value "0" on instance CmdLEDGet.
 @N: FX493 |Applying initial value "0" on instance CmdLEDSet.
 @N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
 @N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
-@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "0000" on instance S[3:0].
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "1" on instance DQMH.
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
 @N: FX493 |Applying initial value "1" on instance DQML.
-@N: FX493 |Applying initial value "0" on instance CKE.
-@N: FX493 |Applying initial value "1" on instance nCS.
-@N: FX493 |Applying initial value "1" on instance nRAS.
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "0000" on instance S[3:0].
+@N: FX493 |Applying initial value "1" on instance CKE.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+@N: FX493 |Applying initial value "1" on instance nRWEout.
 @N: FX493 |Applying initial value "1" on instance nCAS.
+@N: FX493 |Applying initial value "1" on instance nCASout.
+@N: FX493 |Applying initial value "1" on instance nRAS.
+@N: FX493 |Applying initial value "1" on instance nRASout.
 
 Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
@@ -236,11 +240,11 @@ Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapse
 Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
 
 
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
 
 @N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E 
 
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
 
 
 
@@ -250,7 +254,7 @@ Clock Summary
           Start      Requested     Requested     Clock        Clock                Clock
 Level     Clock      Frequency     Period        Type         Group                Load 
 ----------------------------------------------------------------------------------------
-0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     111  
+0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     122  
                                                                                         
 0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
 ========================================================================================
@@ -263,7 +267,7 @@ Clock Load Summary
            Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin     
 Clock      Load      Pin            Seq Example     Seq Example       Comb Example      
 ----------------------------------------------------------------------------------------
-C14M       111       C14M(port)     wb_rst.C        -                 un1_C14M.I[0](inv)
+C14M       122       C14M(port)     DOEEN.C         -                 un1_C14M.I[0](inv)
                                                                                         
 System     0         -              -               -                 -                 
 ========================================================================================
@@ -280,14 +284,14 @@ For details review file gcc_ICG_report.rpt
 
 #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
 
-1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
+1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
 0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
 =========================== Non-Gated/Non-Generated Clocks ============================
 Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
 ---------------------------------------------------------------------------------------
-@KP:ckid0_0       C14M                port                   111        nCAS           
+@KP:ckid0_0       C14M                port                   122        nRAS           
 =======================================================================================
 
 
@@ -296,23 +300,23 @@ Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample I
 @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
 Finished Pre Mapping Phase.
 
-Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
 
 
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
 
 
-Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB)
 
 Pre-mapping successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
 
-Process took 0h:00m:02s realtime, 0h:00m:01s cputime
-# Thu Sep 21 05:34:37 2023
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Thu Dec 28 23:09:49 2023
 
 ###########################################################]
-# Thu Sep 21 05:34:37 2023
+# Thu Dec 28 23:09:49 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -331,97 +335,97 @@ Implementation : impl1
 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
 
 
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
 
 
 Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
 
 
 
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
 
-@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
-@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
 
-Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
 
-@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
+@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 
 Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
 Available hyper_sources - for debug and ip models
 	None Found
 
 
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
 
 
-Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
 
 
-Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
 
 Pass		 CPU time		Worst Slack		Luts / Registers
 ------------------------------------------------------------
-   1		0h:00m:02s		    29.35ns		 222 /       111
+   1		0h:00m:02s		    33.71ns		 284 /       122
 
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
 
 @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
 
-Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
 
 
-Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
 
-Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
+Writing Analyst data base \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
 
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 206MB peak: 206MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB)
 
 Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
+@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
 
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
 
 
-Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
 
 
-Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
+Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB)
 
 @W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
 @N: MT615 |Found clock C14M with period 69.84ns 
 
 
 ##### START OF TIMING REPORT #####[
-# Timing report written on Thu Sep 21 05:34:43 2023
+# Timing report written on Thu Dec 28 23:09:54 2023
 #
 
 
@@ -429,7 +433,7 @@ Top view:               RAM2E
 Requested Frequency:    14.3 MHz
 Wire load mode:         top
 Paths requested:        5
-Constraint File(s):    \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
+Constraint File(s):    \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc
                        
 @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
 
@@ -441,12 +445,12 @@ Performance Summary
 *******************
 
 
-Worst slack in design: 31.782
+Worst slack in design: 33.707
 
                    Requested     Estimated     Requested     Estimated                Clock        Clock           
 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
 -------------------------------------------------------------------------------------------------------------------
-C14M               14.3 MHz      131.4 MHz     69.841        7.610         31.782     declared     default_clkgroup
+C14M               14.3 MHz      128.0 MHz     69.841        7.813         33.707     declared     default_clkgroup
 System             100.0 MHz     NA            10.000        NA            67.088     system       system_clkgroup 
 ===================================================================================================================
 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
@@ -464,7 +468,7 @@ Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  sl
 ----------------------------------------------------------------------------------------------------------
 System    C14M    |  69.841      67.088  |  No paths    -      |  No paths    -       |  No paths    -    
 C14M      System  |  69.841      68.797  |  No paths    -      |  No paths    -       |  No paths    -    
-C14M      C14M    |  69.841      62.231  |  No paths    -      |  34.920      31.782  |  No paths    -    
+C14M      C14M    |  69.841      62.028  |  No paths    -      |  34.920      33.707  |  No paths    -    
 ==========================================================================================================
  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
@@ -487,41 +491,41 @@ Detailed Report for Clock: C14M
 Starting Points with Worst Slack
 ********************************
 
-             Starting                                     Arrival           
-Instance     Reference     Type        Pin     Net        Time        Slack 
-             Clock                                                          
-----------------------------------------------------------------------------
-S[2]         C14M          FD1S3AX     Q       S[2]       1.350       31.782
-S[3]         C14M          FD1S3AX     Q       S[3]       1.350       31.782
-S[0]         C14M          FD1S3AX     Q       S[0]       1.312       31.820
-S[1]         C14M          FD1S3AX     Q       S[1]       1.280       31.852
-FS[9]        C14M          FD1S3AX     Q       FS[9]      1.284       62.425
-FS[11]       C14M          FD1S3AX     Q       FS[11]     1.276       62.433
-FS[8]        C14M          FD1S3AX     Q       FS[8]      1.260       62.449
-FS[12]       C14M          FD1S3AX     Q       FS[12]     1.288       62.525
-FS[10]       C14M          FD1S3AX     Q       FS[10]     1.280       62.533
-RWSel        C14M          FD1P3AX     Q       RWSel      1.276       63.482
-============================================================================
+             Starting                                    Arrival           
+Instance     Reference     Type        Pin     Net       Time        Slack 
+             Clock                                                         
+---------------------------------------------------------------------------
+RA[0]        C14M          FD1P3AX     Q       RA[0]     1.108       33.707
+RA[3]        C14M          FD1P3AX     Q       RA[3]     1.108       33.707
+RA[1]        C14M          FD1P3AX     Q       RA[1]     1.044       33.771
+RA[2]        C14M          FD1P3AX     Q       RA[2]     1.044       33.771
+RA[4]        C14M          FD1P3AX     Q       RA[4]     1.044       33.771
+RA[5]        C14M          FD1P3AX     Q       RA[5]     1.044       33.771
+RA[6]        C14M          FD1P3AX     Q       RA[6]     1.044       33.771
+RA[7]        C14M          FD1P3AX     Q       RA[7]     1.044       33.771
+RA[8]        C14M          FD1P3AX     Q       RA[8]     1.044       33.771
+RA[9]        C14M          FD1P3AX     Q       RA[9]     1.044       33.771
+===========================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-                Starting                                       Required           
-Instance        Reference     Type         Pin     Net         Time         Slack 
-                Clock                                                             
-----------------------------------------------------------------------------------
-Dout_0io[0]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[1]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[2]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[3]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[4]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[5]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[6]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[7]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Vout_0io[0]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
-Vout_0io[1]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
-==================================================================================
+                 Starting                                     Required           
+Instance         Reference     Type         Pin     Net       Time         Slack 
+                 Clock                                                           
+---------------------------------------------------------------------------------
+RAout_0io[0]     C14M          OFS1P3DX     D       RA[0]     34.815       33.707
+RAout_0io[3]     C14M          OFS1P3DX     D       RA[3]     34.815       33.707
+RAout_0io[1]     C14M          OFS1P3DX     D       RA[1]     34.815       33.771
+RAout_0io[2]     C14M          OFS1P3DX     D       RA[2]     34.815       33.771
+RAout_0io[4]     C14M          OFS1P3DX     D       RA[4]     34.815       33.771
+RAout_0io[5]     C14M          OFS1P3DX     D       RA[5]     34.815       33.771
+RAout_0io[6]     C14M          OFS1P3DX     D       RA[6]     34.815       33.771
+RAout_0io[7]     C14M          OFS1P3DX     D       RA[7]     34.815       33.771
+RAout_0io[8]     C14M          OFS1P3DX     D       RA[8]     34.815       33.771
+RAout_0io[9]     C14M          OFS1P3DX     D       RA[9]     34.815       33.771
+=================================================================================
 
 
 
@@ -531,30 +535,27 @@ Worst Path Information
 
 Path information for path number 1: 
       Requested Period:                      34.920
-    - Setup time:                            0.472
+    - Setup time:                            0.106
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         34.449
+    = Required time:                         34.815
 
-    - Propagation time:                      2.667
+    - Propagation time:                      1.108
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     31.782
+    = Slack (critical) :                     33.707
 
-    Number of logic level(s):                1
-    Starting point:                          S[2] / Q
-    Ending point:                            Dout_0io[0] / SP
+    Number of logic level(s):                0
+    Starting point:                          RA[0] / Q
+    Ending point:                            RAout_0io[0] / D
     The start point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
     The end   point is clocked by            C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
 
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-S[2]                FD1S3AX      Q        Out     1.350     1.350 r     -         
-S[2]                Net          -        -       -         -           48        
-S_RNII9DO1_2[1]     ORCALUT4     B        In      0.000     1.350 r     -         
-S_RNII9DO1_2[1]     ORCALUT4     Z        Out     1.317     2.667 r     -         
-N_576_i             Net          -        -       -         -           18        
-Dout_0io[0]         OFS1P3DX     SP       In      0.000     2.667 r     -         
-==================================================================================
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+RA[0]              FD1P3AX      Q        Out     1.108     1.108 r     -         
+RA[0]              Net          -        -       -         -           3         
+RAout_0io[0]       OFS1P3DX     D        In      0.000     1.108 r     -         
+=================================================================================
 
 
 
@@ -568,40 +569,40 @@ Detailed Report for Clock: System
 Starting Points with Worst Slack
 ********************************
 
-                     Starting                                          Arrival           
-Instance             Reference     Type     Pin         Net            Time        Slack 
-                     Clock                                                               
------------------------------------------------------------------------------------------
-ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
-ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
-=========================================================================================
+                               Starting                                          Arrival           
+Instance                       Reference     Type     Pin         Net            Time        Slack 
+                               Clock                                                               
+---------------------------------------------------------------------------------------------------
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
+===================================================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-               Starting                                                          Required           
-Instance       Reference     Type        Pin     Net                             Time         Slack 
-               Clock                                                                                
-----------------------------------------------------------------------------------------------------
-RWMask[0]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[1]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[2]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[3]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[4]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[5]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[6]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[7]      System        FD1P3AX     SP      N_88                            69.369       67.088
-LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0[0]     69.369       67.736
-wb_cyc_stb     System        FD1P3AX     SP      N_104                           69.369       67.736
-====================================================================================================
+                         Starting                                                                  Required           
+Instance                 Reference     Type        Pin     Net                                     Time         Slack 
+                         Clock                                                                                        
+----------------------------------------------------------------------------------------------------------------------
+ram2e_ufm.RWMask[0]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[1]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[2]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[3]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[4]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[5]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[6]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[7]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0_0[0]           69.369       67.736
+ram2e_ufm.wb_cyc_stb     System        FD1P3AX     SP      un1_CmdSetRWBankFFChip13_1_i_0_0[0]     69.369       67.736
+======================================================================================================================
 
 
 
@@ -621,24 +622,24 @@ Path information for path number 1:
     = Slack (non-critical) :                 67.088
 
     Number of logic level(s):                2
-    Starting point:                          ufmefb.EFBInst_0 / WBACKO
-    Ending point:                            RWMask[0] / SP
+    Starting point:                          ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
+    Ending point:                            ram2e_ufm.RWMask[0] / SP
     The start point is clocked by            System [rising]
     The end   point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
 
-Instance / Net                                     Pin        Pin               Arrival     No. of    
-Name                                  Type         Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
-ufmefb.EFBInst_0                      EFB          WBACKO     Out     0.000     0.000 r     -         
-wb_ack                                Net          -          -       -         -           5         
-un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     A          In      0.000     0.000 r     -         
-un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     Z          Out     1.017     1.017 r     -         
-un1_RWMask_0_sqmuxa_1_i_a2_0_1[0]     Net          -          -       -         -           1         
-un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
-un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
-N_88                                  Net          -          -       -         -           8         
-RWMask[0]                             FD1P3AX      SP         In      0.000     2.282 r     -         
-======================================================================================================
+Instance / Net                                                 Pin        Pin               Arrival     No. of    
+Name                                              Type         Name       Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------------------------------------
+ram2e_ufm.ufmefb.EFBInst_0                        EFB          WBACKO     Out     0.000     0.000 r     -         
+wb_ack                                            Net          -          -       -         -           5         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     B          In      0.000     0.000 r     -         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     Z          Out     1.017     1.017 r     -         
+un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]               Net          -          -       -         -           1         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
+un1_RWMask_0_sqmuxa_1_i_0_0[0]                    Net          -          -       -         -           8         
+ram2e_ufm.RWMask[0]                               FD1P3AX      SP         In      0.000     2.282 r     -         
+==================================================================================================================
 
 
 
@@ -646,45 +647,47 @@ RWMask[0]                             FD1P3AX      SP         In      0.000
 
 Timing exceptions that could not be applied
 
-Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
 
 
-Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
 
 ---------------------------------------
 Resource Usage Report
 Part: lcmxo2_640hc-4
 
-Register bits: 111 of 640 (17%)
+Register bits: 122 of 640 (19%)
 PIC Latch:       0
-I/O cells:       70
+I/O cells:       69
 
 
 Details:
 BB:             8
 CCU2D:          9
 EFB:            1
-FD1P3AX:        48
+FD1P3AX:        61
 FD1P3IX:        1
-FD1S3AX:        22
-FD1S3IX:        4
+FD1S3AX:        21
+FD1S3AY:        4
+FD1S3IX:        6
 GSR:            1
-IB:             22
+IB:             21
 IFS1P3DX:       1
 INV:            1
 OB:             40
-OFS1P3BX:       6
-OFS1P3DX:       27
+OFS1P3BX:       5
+OFS1P3DX:       21
 OFS1P3IX:       2
-ORCALUT4:       221
+ORCALUT4:       277
+PFUMX:          3
 PUR:            1
-VHI:            2
-VLO:            2
+VHI:            3
+VLO:            3
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 77MB peak: 211MB)
+At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 79MB peak: 217MB)
 
-Process took 0h:00m:06s realtime, 0h:00m:04s cputime
-# Thu Sep 21 05:34:44 2023
+Process took 0h:00m:04s realtime, 0h:00m:04s cputime
+# Thu Dec 28 23:09:54 2023
 
 ###########################################################]
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.tw1
index 9f9184a..02317af 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.tw1
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.tw1
@@ -13,7 +13,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:34:48 2023
+Thu Dec 28 23:09:59 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -23,7 +23,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
 Design file:     ram2e_lcmxo2_640hc_impl1_map.ncd
 Preference file: ram2e_lcmxo2_640hc_impl1.prf
 Device,speed:    LCMXO2-640HC,4
@@ -38,48 +38,48 @@ BLOCK RESETPATHS
 
 ================================================================================
 Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 58.471ns
+Passed: The following path meets requirements by 58.937ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              11.306ns  (30.3% logic, 69.7% route), 7 logic levels.
+   Delay:              10.827ns  (31.6% logic, 68.4% route), 7 logic levels.
 
  Constraint Details:
 
-     11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
-      0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns
 
  Physical Path Details:
 
-      Data path SLICE_3 to nRWE_MGIOL:
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452    SLICE_3.CLK to     SLICE_3.Q0 SLICE_3 (from C14M_c)
-ROUTE        19   e 1.234     SLICE_3.Q0 to    SLICE_64.A1 FS[11]
-CTOF_DEL    ---     0.495    SLICE_64.A1 to    SLICE_64.F1 SLICE_64
-ROUTE         4   e 1.234    SLICE_64.F1 to    SLICE_97.D0 N_577
-CTOF_DEL    ---     0.495    SLICE_97.D0 to    SLICE_97.F0 SLICE_97
-ROUTE         3   e 1.234    SLICE_97.F0 to    SLICE_75.D1 N_489
-CTOF_DEL    ---     0.495    SLICE_75.D1 to    SLICE_75.F1 SLICE_75
-ROUTE         3   e 0.480    SLICE_75.F1 to    SLICE_75.A0 N_628
-CTOF_DEL    ---     0.495    SLICE_75.A0 to    SLICE_75.F0 SLICE_75
-ROUTE         2   e 1.234    SLICE_75.F0 to    SLICE_71.C1 N_640
-CTOF_DEL    ---     0.495    SLICE_71.C1 to    SLICE_71.F1 SLICE_71
-ROUTE         1   e 1.234    SLICE_71.F1 to   SLICE_115.A0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495   SLICE_115.A0 to   SLICE_115.F0 SLICE_115
-ROUTE         1   e 1.234   SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
+REG_DEL     ---     0.452   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from C14M_c)
+ROUTE        50   e 1.234    SLICE_34.Q0 to    SLICE_35.A0 S[2]
+CTOF_DEL    ---     0.495    SLICE_35.A0 to    SLICE_35.F0 SLICE_35
+ROUTE         7   e 1.234    SLICE_35.F0 to *m/SLICE_80.D1 N_551
+CTOF_DEL    ---     0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
+ROUTE         8   e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
+ROUTE         5   e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
+ROUTE         1   e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
+CTOF_DEL    ---     0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
+ROUTE         1   e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
+ROUTE         1   e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   11.306   (30.3% logic, 69.7% route), 7 logic levels.
+                   10.827   (31.6% logic, 68.4% route), 7 logic levels.
 
-Report:   87.268MHz is the maximum frequency for this preference.
+Report:   90.967MHz is the maximum frequency for this preference.
 
 Report Summary
 --------------
@@ -87,7 +87,7 @@ Report Summary
 Preference                              |   Constraint|       Actual|Levels
 ----------------------------------------------------------------------------
                                         |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   87.268 MHz|   7  
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   90.967 MHz|   7  
                                         |             |             |
 ----------------------------------------------------------------------------
 
@@ -100,7 +100,7 @@ Clock Domains Analysis
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -110,11 +110,11 @@ Timing summary (Setup):
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:34:48 2023
+Thu Dec 28 23:09:59 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -124,7 +124,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
 Design file:     ram2e_lcmxo2_640hc_impl1_map.ncd
 Preference file: ram2e_lcmxo2_640hc_impl1.prf
 Device,speed:    LCMXO2-640HC,M
@@ -139,7 +139,7 @@ BLOCK RESETPATHS
 
 ================================================================================
 Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
@@ -164,7 +164,7 @@ Passed: The following path meets requirements by 0.447ns
 
    Name    Fanout   Delay (ns)          Site               Resource
 REG_DEL     ---     0.133    SLICE_0.CLK to     SLICE_0.Q1 SLICE_0 (from C14M_c)
-ROUTE         5   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
+ROUTE         6   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
 CTOF_DEL    ---     0.101     SLICE_0.A1 to     SLICE_0.F1 SLICE_0
 ROUTE         1   e 0.001     SLICE_0.F1 to    SLICE_0.DI1 FS_s[0] (to C14M_c)
                   --------
@@ -189,7 +189,7 @@ Clock Domains Analysis
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -199,7 +199,7 @@ Timing summary (Hold):
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr
index 8f602e5..48488ef 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr
@@ -13,7 +13,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:35:07 2023
+Thu Dec 28 23:10:16 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -23,7 +23,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
 Design file:     ram2e_lcmxo2_640hc_impl1.ncd
 Preference file: ram2e_lcmxo2_640hc_impl1.prf
 Device,speed:    LCMXO2-640HC,4
@@ -38,536 +38,550 @@ BLOCK RESETPATHS
 
 ================================================================================
 Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 57.366ns
+Passed: The following path meets requirements by 57.938ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              12.584ns  (27.2% logic, 72.8% route), 7 logic levels.
+   Delay:              11.826ns  (24.8% logic, 75.2% route), 6 logic levels.
 
  Constraint Details:
 
-     12.584ns physical path delay SLICE_3 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.366ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     0.453       R3C9C.F1 to       R3C9C.C0 N_628
-CTOF_DEL    ---     0.495       R3C9C.C0 to       R3C9C.F0 SLICE_75
-ROUTE         2     0.993       R3C9C.F0 to       R5C9A.A1 N_640
-CTOF_DEL    ---     0.495       R5C9A.A1 to       R5C9A.F1 SLICE_71
-ROUTE         1     0.623       R5C9A.F1 to      R5C10B.D0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495      R5C10B.D0 to      R5C10B.F0 SLICE_115
-ROUTE         1     2.192      R5C10B.F0 to   IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   12.584   (27.2% logic, 72.8% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R7D.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.494ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRAS_0io  (to C14M_c +)
-
-   Delay:              12.456ns  (23.5% logic, 76.5% route), 6 logic levels.
-
- Constraint Details:
-
-     12.456ns physical path delay SLICE_3 to nRAS_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.494ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nRAS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     1.003       R3C9C.F1 to      R3C10D.A0 N_628
-CTOF_DEL    ---     0.495      R3C10D.A0 to      R3C10D.F0 SLICE_83
-ROUTE         2     1.505      R3C10D.F0 to      R5C10A.A0 N_559_1
-CTOF_DEL    ---     0.495      R5C10A.A0 to      R5C10A.F0 SLICE_80
-ROUTE         1     2.120      R5C10A.F0 to   IOL_R7A.OPOS nRAS_2_iv_i (to C14M_c)
-                  --------
-                   12.456   (23.5% logic, 76.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRAS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R7A.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.502ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
-
-   Delay:              12.448ns  (23.5% logic, 76.5% route), 6 logic levels.
-
- Constraint Details:
-
-     12.448ns physical path delay SLICE_3 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.502ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     0.710       R3C9C.F1 to       R3C9B.B0 N_628
-CTOF_DEL    ---     0.495       R3C9B.B0 to       R3C9B.F0 SLICE_76
-ROUTE         3     1.718       R3C9B.F0 to      R5C10B.C0 nCAS_0_sqmuxa
-CTOF_DEL    ---     0.495      R5C10B.C0 to      R5C10B.F0 SLICE_115
-ROUTE         1     2.192      R5C10B.F0 to   IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   12.448   (23.5% logic, 76.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R7D.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.921ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nCS_0io  (to C14M_c +)
-
-   Delay:              12.029ns  (24.3% logic, 75.7% route), 6 logic levels.
-
- Constraint Details:
-
-     12.029ns physical path delay SLICE_3 to nCS_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.921ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nCS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     1.003       R3C9C.F1 to      R3C10D.A0 N_628
-CTOF_DEL    ---     0.495      R3C10D.A0 to      R3C10D.F0 SLICE_83
-ROUTE         2     1.505      R3C10D.F0 to      R6C10A.A0 N_559_1
-CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_79
-ROUTE         1     1.693      R6C10A.F0 to   IOL_R6D.OPOS N_559_i (to C14M_c)
-                  --------
-                   12.029   (24.3% logic, 75.7% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nCS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R6D.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.106ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nCAS_0io  (to C14M_c +)
-
-   Delay:              11.844ns  (24.7% logic, 75.3% route), 6 logic levels.
-
- Constraint Details:
-
-     11.844ns physical path delay SLICE_3 to nCAS_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 58.106ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nCAS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     0.710       R3C9C.F1 to       R3C9B.B0 N_628
-CTOF_DEL    ---     0.495       R3C9B.B0 to       R3C9B.F0 SLICE_76
-ROUTE         3     1.511       R3C9B.F0 to       R5C9C.A0 nCAS_0_sqmuxa
-CTOF_DEL    ---     0.495       R5C9C.A0 to       R5C9C.F0 SLICE_78
-ROUTE         1     1.795       R5C9C.F0 to   IOL_R7C.OPOS N_561_i (to C14M_c)
-                  --------
-                   11.844   (24.7% logic, 75.3% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nCAS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R7C.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.447ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        RA_0io[10]  (to C14M_c +)
-
-   Delay:              11.503ns  (25.4% logic, 74.6% route), 6 logic levels.
-
- Constraint Details:
-
-     11.503ns physical path delay SLICE_3 to RA[10]_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 58.447ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to RA[10]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     0.710       R3C9C.F1 to       R3C9B.B0 N_628
-CTOF_DEL    ---     0.495       R3C9B.B0 to       R3C9B.F0 SLICE_76
-ROUTE         3     1.170       R3C9B.F0 to       R5C9D.D1 nCAS_0_sqmuxa
-CTOF_DEL    ---     0.495       R5C9D.D1 to       R5C9D.F1 SLICE_69
-ROUTE         1     1.795       R5C9D.F1 to   IOL_R5B.OPOS RA_42[10] (to C14M_c)
-                  --------
-                   11.503   (25.4% logic, 74.6% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to RA[10]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R5B.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.587ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[2]  (from C14M_c +)
-   Destination:    FF         Data in        wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.177ns  (26.2% logic, 73.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.177ns physical path delay SLICE_34 to SLICE_35 meets
+     11.826ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
       0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.587ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.938ns
 
  Physical Path Details:
 
-      Data path SLICE_34 to SLICE_35:
+      Data path SLICE_33 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R4C9C.CLK to       R4C9C.Q0 SLICE_34 (from C14M_c)
-ROUTE        48     1.873       R4C9C.Q0 to       R6C9B.B0 S[2]
-CTOF_DEL    ---     0.495       R6C9B.B0 to       R6C9B.F0 SLICE_47
-ROUTE         7     2.435       R6C9B.F0 to       R4C5B.B0 S_RNII9DO1[1]
-CTOF_DEL    ---     0.495       R4C5B.B0 to       R4C5B.F0 SLICE_73
-ROUTE         8     1.931       R4C5B.F0 to       R4C4C.D0 N_455
-CTOF_DEL    ---     0.495       R4C4C.D0 to       R4C4C.F0 SLICE_89
-ROUTE         1     0.626       R4C4C.F0 to       R4C4A.D0 N_378
-CTOF_DEL    ---     0.495       R4C4A.D0 to       R4C4A.F0 SLICE_85
-ROUTE         1     1.385       R4C4A.F0 to       R2C4B.D0 wb_adr_7_0_4[0]
-CTOF_DEL    ---     0.495       R2C4B.D0 to       R2C4B.F0 SLICE_35
-ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 wb_adr_7[0] (to C14M_c)
+REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
+CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
+ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
+CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
+ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
+CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   11.177   (26.2% logic, 73.8% route), 6 logic levels.
+                   11.826   (24.8% logic, 75.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 57.944ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              11.820ns  (29.0% logic, 71.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.820ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.944ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
+CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
+ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
+CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
+ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
+CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
+ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
+CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   11.820   (29.0% logic, 71.0% route), 7 logic levels.
 
  Clock Skew Details: 
 
       Source Clock Path C14M to SLICE_34:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R4C9C.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
                   --------
                     3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_35:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C4B.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
                   --------
                     3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 58.757ns
+Passed: The following path meets requirements by 58.190ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[12]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              FS[15]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              11.193ns  (30.6% logic, 69.4% route), 7 logic levels.
+   Delay:              11.574ns  (25.3% logic, 74.7% route), 6 logic levels.
 
  Constraint Details:
 
-     11.193ns physical path delay SLICE_3 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 58.757ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_3 (from C14M_c)
-ROUTE        22     1.463       R2C8C.Q1 to       R3C6A.A1 FS[12]
-CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 SLICE_97
-ROUTE         2     0.702       R3C6A.F1 to       R3C6A.B0 N_456
-CTOF_DEL    ---     0.495       R3C6A.B0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     0.453       R3C9C.F1 to       R3C9C.C0 N_628
-CTOF_DEL    ---     0.495       R3C9C.C0 to       R3C9C.F0 SLICE_75
-ROUTE         2     0.993       R3C9C.F0 to       R5C9A.A1 N_640
-CTOF_DEL    ---     0.495       R5C9A.A1 to       R5C9A.F1 SLICE_71
-ROUTE         1     0.623       R5C9A.F1 to      R5C10B.D0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495      R5C10B.D0 to      R5C10B.F0 SLICE_115
-ROUTE         1     2.192      R5C10B.F0 to   IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   11.193   (30.6% logic, 69.4% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R7D.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.784ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        wb_adr[0]  (to C14M_c +)
-
-   Delay:              10.980ns  (26.7% logic, 73.3% route), 6 logic levels.
-
- Constraint Details:
-
-     10.980ns physical path delay SLICE_33 to SLICE_35 meets
+     11.574ns physical path delay SLICE_1 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
       0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.784ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.190ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to SLICE_35:
+      Data path SLICE_1 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R4C9D.CLK to       R4C9D.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     1.676       R4C9D.Q0 to       R6C9B.C0 S[0]
-CTOF_DEL    ---     0.495       R6C9B.C0 to       R6C9B.F0 SLICE_47
-ROUTE         7     2.435       R6C9B.F0 to       R4C5B.B0 S_RNII9DO1[1]
-CTOF_DEL    ---     0.495       R4C5B.B0 to       R4C5B.F0 SLICE_73
-ROUTE         8     1.931       R4C5B.F0 to       R4C4C.D0 N_455
-CTOF_DEL    ---     0.495       R4C4C.D0 to       R4C4C.F0 SLICE_89
-ROUTE         1     0.626       R4C4C.F0 to       R4C4A.D0 N_378
-CTOF_DEL    ---     0.495       R4C4A.D0 to       R4C4A.F0 SLICE_85
-ROUTE         1     1.385       R4C4A.F0 to       R2C4B.D0 wb_adr_7_0_4[0]
-CTOF_DEL    ---     0.495       R2C4B.D0 to       R2C4B.F0 SLICE_35
-ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 wb_adr_7[0] (to C14M_c)
+REG_DEL     ---     0.452     R2C11A.CLK to      R2C11A.Q0 SLICE_1 (from C14M_c)
+ROUTE         9     2.239      R2C11A.Q0 to       R6C9B.C1 FS[15]
+CTOF_DEL    ---     0.495       R6C9B.C1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
+ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
+CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
+ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
+CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   10.980   (26.7% logic, 73.3% route), 6 logic levels.
+                   11.574   (25.3% logic, 74.7% route), 6 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_33:
+      Source Clock Path C14M to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R4C9D.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to     R2C11A.CLK C14M_c
                   --------
                     3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_35:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C4B.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
                   --------
                     3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 29.415ns (weighted slack = 58.830ns)
+Passed: The following path meets requirements by 58.271ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              11.493ns  (29.8% logic, 70.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.493ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.271ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q0 SLICE_34 (from C14M_c)
+ROUTE        50     0.674      R6C10D.Q0 to      R6C10A.D0 S[2]
+CTOF_DEL    ---     0.495      R6C10A.D0 to      R6C10A.F0 SLICE_35
+ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
+CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
+ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
+CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
+ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
+CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   11.493   (29.8% logic, 70.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.733ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
    Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        Dout_0io[0]  (to C14M_c -)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[2]  (to C14M_c +)
 
-   Delay:               5.676ns  (16.7% logic, 83.3% route), 2 logic levels.
+   Delay:              11.031ns  (26.5% logic, 73.5% route), 6 logic levels.
 
  Constraint Details:
 
-      5.676ns physical path delay SLICE_33 to Dout[0]_MGIOL meets
-     34.965ns delay constraint less
-     -0.173ns skew and
-      0.047ns CE_SET requirement (totaling 35.091ns) by 29.415ns
+     11.031ns physical path delay SLICE_33 to ram2e_ufm/SLICE_53 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.733ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to Dout[0]_MGIOL:
+      Data path SLICE_33 to ram2e_ufm/SLICE_53:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R4C9D.CLK to       R4C9D.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     1.881       R4C9D.Q0 to       R6C8A.A1 S[0]
-CTOF_DEL    ---     0.495       R6C8A.A1 to       R6C8A.F1 SLICE_20
-ROUTE        17     2.848       R6C8A.F1 to     IOL_B4D.CE N_576_i (to C14M_c)
+REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
+CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
+ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
+CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
+ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
+CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
+ROUTE         2     0.758       R3C4C.F1 to       R2C4B.C0 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
+CTOF_DEL    ---     0.495       R2C4B.C0 to       R2C4B.F0 ram2e_ufm/SLICE_53
+ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 ram2e_ufm/wb_dati_7[2] (to C14M_c)
                   --------
-                    5.676   (16.7% logic, 83.3% route), 2 logic levels.
+                   11.031   (26.5% logic, 73.5% route), 6 logic levels.
 
  Clock Skew Details: 
 
       Source Clock Path C14M to SLICE_33:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R4C9D.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
                   --------
                     3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to Dout[0]_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_53:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_B4D.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to      R2C4B.CLK C14M_c
                   --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
-Report:   79.592MHz is the maximum frequency for this preference.
+
+Passed: The following path meets requirements by 58.733ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[5]  (to C14M_c +)
+
+   Delay:              11.031ns  (26.5% logic, 73.5% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.031ns physical path delay SLICE_33 to ram2e_ufm/SLICE_54 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.733ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to ram2e_ufm/SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
+CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
+ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
+CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
+ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
+CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
+ROUTE         2     0.758       R3C4C.F1 to       R2C4D.C1 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
+CTOF_DEL    ---     0.495       R2C4D.C1 to       R2C4D.F1 ram2e_ufm/SLICE_54
+ROUTE         1     0.000       R2C4D.F1 to      R2C4D.DI1 ram2e_ufm/wb_dati_7[5] (to C14M_c)
+                  --------
+                   11.031   (26.5% logic, 73.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R2C4D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.739ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[5]  (to C14M_c +)
+
+   Delay:              11.025ns  (31.0% logic, 69.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.025ns physical path delay SLICE_34 to ram2e_ufm/SLICE_54 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.739ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
+CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
+ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
+CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
+ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
+CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
+ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
+CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
+ROUTE         2     0.758       R3C4C.F1 to       R2C4D.C1 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
+CTOF_DEL    ---     0.495       R2C4D.C1 to       R2C4D.F1 ram2e_ufm/SLICE_54
+ROUTE         1     0.000       R2C4D.F1 to      R2C4D.DI1 ram2e_ufm/wb_dati_7[5] (to C14M_c)
+                  --------
+                   11.025   (31.0% logic, 69.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R2C4D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.739ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[2]  (to C14M_c +)
+
+   Delay:              11.025ns  (31.0% logic, 69.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.025ns physical path delay SLICE_34 to ram2e_ufm/SLICE_53 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.739ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_53:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
+CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
+ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
+CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
+ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
+CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
+ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
+CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
+ROUTE         2     0.758       R3C4C.F1 to       R2C4B.C0 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
+CTOF_DEL    ---     0.495       R2C4B.C0 to       R2C4B.F0 ram2e_ufm/SLICE_53
+ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 ram2e_ufm/wb_dati_7[2] (to C14M_c)
+                  --------
+                   11.025   (31.0% logic, 69.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_53:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R2C4B.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.780ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              10.984ns  (26.6% logic, 73.4% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.984ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.780ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
+CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.182       R6C9B.F1 to       R2C5A.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C5A.C1 to       R2C5A.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.413       R2C5A.F1 to       R4C5B.D0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R4C5B.D0 to       R4C5B.F0 ram2e_ufm/SLICE_126
+ROUTE         1     0.436       R4C5B.F0 to       R4C5A.C0 ram2e_ufm/N_753
+CTOF_DEL    ---     0.495       R4C5A.C0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   10.984   (26.6% logic, 73.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.786ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              10.978ns  (31.2% logic, 68.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.978ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.786ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
+CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
+ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
+CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.182       R6C9B.F1 to       R2C5A.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C5A.C1 to       R2C5A.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.413       R2C5A.F1 to       R4C5B.D0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R4C5B.D0 to       R4C5B.F0 ram2e_ufm/SLICE_126
+ROUTE         1     0.436       R4C5B.F0 to       R4C5A.C0 ram2e_ufm/N_753
+CTOF_DEL    ---     0.495       R4C5A.C0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   10.978   (31.2% logic, 68.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   83.389MHz is the maximum frequency for this preference.
 
 Report Summary
 --------------
@@ -575,7 +589,7 @@ Report Summary
 Preference                              |   Constraint|       Actual|Levels
 ----------------------------------------------------------------------------
                                         |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   79.592 MHz|   7  
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   83.389 MHz|   6  
                                         |             |             |
 ----------------------------------------------------------------------------
 
@@ -588,7 +602,7 @@ Clock Domains Analysis
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -598,11 +612,11 @@ Timing summary (Setup):
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Sep 21 05:35:07 2023
+Thu Dec 28 23:10:16 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -612,7 +626,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 Report Information
 ------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
 Design file:     ram2e_lcmxo2_640hc_impl1.ncd
 Preference file: ram2e_lcmxo2_640hc_impl1.prf
 Device,speed:    LCMXO2-640HC,m
@@ -627,137 +641,51 @@ BLOCK RESETPATHS
 
 ================================================================================
 Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 0.346ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              wb_dati[3]  (from C14M_c +)
-   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
-
-   Delay:               0.305ns  (43.6% logic, 56.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.305ns physical path delay SLICE_41 to ufmefb/EFBInst_0 meets
-     -0.095ns WBDATI_HLD and
-      0.000ns delay constraint less
-     -0.054ns skew requirement (totaling -0.041ns) by 0.346ns
-
- Physical Path Details:
-
-      Data path SLICE_41 to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C3B.CLK to       R2C3B.Q1 SLICE_41 (from C14M_c)
-ROUTE         1     0.172       R2C3B.Q1 to    EFB.WBDATI3 wb_dati[3] (to C14M_c)
-                  --------
-                    0.305   (43.6% logic, 56.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_41:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C3B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.113       62.PADDI to     EFB.WBCLKI C14M_c
-                  --------
-                    1.113   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.348ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              wb_dati[4]  (from C14M_c +)
-   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
-
-   Delay:               0.305ns  (43.6% logic, 56.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.305ns physical path delay SLICE_42 to ufmefb/EFBInst_0 meets
-     -0.097ns WBDATI_HLD and
-      0.000ns delay constraint less
-     -0.054ns skew requirement (totaling -0.043ns) by 0.348ns
-
- Physical Path Details:
-
-      Data path SLICE_42 to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C3D.CLK to       R2C3D.Q0 SLICE_42 (from C14M_c)
-ROUTE         1     0.172       R2C3D.Q0 to    EFB.WBDATI4 wb_dati[4] (to C14M_c)
-                  --------
-                    0.305   (43.6% logic, 56.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_42:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C3D.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.113       62.PADDI to     EFB.WBCLKI C14M_c
-                  --------
-                    1.113   (0.0% logic, 100.0% route), 0 logic levels.
-
-
 Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[0]  (from C14M_c +)
-   Destination:    FF         Data in        FS[0]  (to C14M_c +)
+   Source:         FF         Q              FS[15]  (from C14M_c +)
+   Destination:    FF         Data in        FS[15]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
  Constraint Details:
 
-      0.366ns physical path delay SLICE_0 to SLICE_0 meets
+      0.366ns physical path delay SLICE_1 to SLICE_1 meets
      -0.013ns DIN_HLD and
       0.000ns delay constraint less
       0.000ns skew requirement (totaling -0.013ns) by 0.379ns
 
  Physical Path Details:
 
-      Data path SLICE_0 to SLICE_0:
+      Data path SLICE_1 to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C7A.CLK to       R2C7A.Q1 SLICE_0 (from C14M_c)
-ROUTE         5     0.132       R2C7A.Q1 to       R2C7A.A1 FS[0]
-CTOF_DEL    ---     0.101       R2C7A.A1 to       R2C7A.F1 SLICE_0
-ROUTE         1     0.000       R2C7A.F1 to      R2C7A.DI1 FS_s[0] (to C14M_c)
+REG_DEL     ---     0.133     R2C11A.CLK to      R2C11A.Q0 SLICE_1 (from C14M_c)
+ROUTE         9     0.132      R2C11A.Q0 to      R2C11A.A0 FS[15]
+CTOF_DEL    ---     0.101      R2C11A.A0 to      R2C11A.F0 SLICE_1
+ROUTE         1     0.000      R2C11A.F0 to     R2C11A.DI0 FS_s[15] (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_0:
+      Source Clock Path C14M to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C7A.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C11A.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_0:
+      Destination Clock Path C14M to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C7A.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C11A.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -766,188 +694,8 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              CmdBitbangMXO2  (from C14M_c +)
-   Destination:    FF         Data in        CmdBitbangMXO2  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_12 to SLICE_12 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_12 to SLICE_12:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C6C.CLK to       R4C6C.Q0 SLICE_12 (from C14M_c)
-ROUTE         2     0.132       R4C6C.Q0 to       R4C6C.A0 CmdBitbangMXO2
-CTOF_DEL    ---     0.101       R4C6C.A0 to       R4C6C.F0 SLICE_12
-ROUTE         1     0.000       R4C6C.F0 to      R4C6C.DI0 CmdBitbangMXO2_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_12:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R4C6C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_12:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R4C6C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdLEDSet  (from C14M_c +)
-   Destination:    FF         Data in        CmdLEDSet  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_15 to SLICE_15 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_15 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C5B.CLK to       R5C5B.Q0 SLICE_15 (from C14M_c)
-ROUTE         2     0.132       R5C5B.Q0 to       R5C5B.A0 CmdLEDSet
-CTOF_DEL    ---     0.101       R5C5B.A0 to       R5C5B.F0 SLICE_15
-ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 CmdLEDSet_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R5C5B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R5C5B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdRWMaskSet  (from C14M_c +)
-   Destination:    FF         Data in        CmdRWMaskSet  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_16 to SLICE_16 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_16 to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C5C.CLK to       R5C5C.Q0 SLICE_16 (from C14M_c)
-ROUTE         2     0.132       R5C5C.Q0 to       R5C5C.A0 CmdRWMaskSet
-CTOF_DEL    ---     0.101       R5C5C.A0 to       R5C5C.F0 SLICE_16
-ROUTE         1     0.000       R5C5C.F0 to      R5C5C.DI0 CmdRWMaskSet_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R5C5C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R5C5C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdSetRWBankFFLED  (from C14M_c +)
-   Destination:    FF         Data in        CmdSetRWBankFFLED  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_17 to SLICE_17 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_17 to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C5C.CLK to       R6C5C.Q0 SLICE_17 (from C14M_c)
-ROUTE         2     0.132       R6C5C.Q0 to       R6C5C.A0 CmdSetRWBankFFLED
-CTOF_DEL    ---     0.101       R6C5C.A0 to       R6C5C.F0 SLICE_17
-ROUTE         1     0.000       R6C5C.F0 to      R6C5C.DI0 CmdSetRWBankFFLED_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R6C5C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R6C5C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdSetRWBankFFMXO2  (from C14M_c +)
-   Destination:    FF         Data in        CmdSetRWBankFFMXO2  (to C14M_c +)
+   Source:         FF         Q              CmdTout[2]  (from C14M_c +)
+   Destination:    FF         Data in        CmdTout[2]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -963,10 +711,10 @@ Passed: The following path meets requirements by 0.379ns
       Data path SLICE_18 to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C6D.CLK to       R6C6D.Q0 SLICE_18 (from C14M_c)
-ROUTE         2     0.132       R6C6D.Q0 to       R6C6D.A0 CmdSetRWBankFFMXO2
-CTOF_DEL    ---     0.101       R6C6D.A0 to       R6C6D.F0 SLICE_18
-ROUTE         1     0.000       R6C6D.F0 to      R6C6D.DI0 CmdSetRWBankFFMXO2_4 (to C14M_c)
+REG_DEL     ---     0.133      R5C9B.CLK to       R5C9B.Q1 SLICE_18 (from C14M_c)
+ROUTE         2     0.132       R5C9B.Q1 to       R5C9B.A1 CmdTout[2]
+CTOF_DEL    ---     0.101       R5C9B.A1 to       R5C9B.F1 SLICE_18
+ROUTE         1     0.000       R5C9B.F1 to      R5C9B.DI1 N_369_i (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -975,14 +723,14 @@ ROUTE         1     0.000       R6C6D.F0 to      R6C6D.DI0 CmdSetRWBankFFMXO2_4
       Source Clock Path C14M to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R6C6D.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
       Destination Clock Path C14M to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R6C6D.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -991,8 +739,188 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        FS[11]  (to C14M_c +)
+   Source:         FF         Q              CmdTout[1]  (from C14M_c +)
+   Destination:    FF         Data in        CmdTout[1]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_18 to SLICE_18 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9B.CLK to       R5C9B.Q0 SLICE_18 (from C14M_c)
+ROUTE         3     0.132       R5C9B.Q0 to       R5C9B.A0 CmdTout[1]
+CTOF_DEL    ---     0.101       R5C9B.A0 to       R5C9B.F0 SLICE_18
+ROUTE         1     0.000       R5C9B.F0 to      R5C9B.DI0 N_368_i (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[13]  (from C14M_c +)
+   Destination:    FF         Data in        FS[13]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_2 to SLICE_2 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R2C10D.CLK to      R2C10D.Q0 SLICE_2 (from C14M_c)
+ROUTE        19     0.132      R2C10D.Q0 to      R2C10D.A0 FS[13]
+CTOF_DEL    ---     0.101      R2C10D.A0 to      R2C10D.F0 SLICE_2
+ROUTE         1     0.000      R2C10D.F0 to     R2C10D.DI0 FS_s[13] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R2C10D.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R2C10D.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA[9]  (from C14M_c +)
+   Destination:    FF         Data in        RA[9]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_24 to SLICE_24 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_24 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11A.CLK to      R5C11A.Q1 SLICE_24 (from C14M_c)
+ROUTE         2     0.132      R5C11A.Q1 to      R5C11A.A1 RA[9]
+CTOF_DEL    ---     0.101      R5C11A.A1 to      R5C11A.F1 SLICE_24
+ROUTE         1     0.000      R5C11A.F1 to     R5C11A.DI1 RA_35[9] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R5C11A.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R5C11A.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA[11]  (from C14M_c +)
+   Destination:    FF         Data in        RA[11]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_25 to SLICE_25 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_25 to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10B.CLK to      R5C10B.Q1 SLICE_25 (from C14M_c)
+ROUTE         2     0.132      R5C10B.Q1 to      R5C10B.A1 RA[11]
+CTOF_DEL    ---     0.101      R5C10B.A1 to      R5C10B.F1 SLICE_25
+ROUTE         1     0.000      R5C10B.F1 to     R5C10B.DI1 RA_35[11] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R5C10B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R5C10B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[12]  (from C14M_c +)
+   Destination:    FF         Data in        FS[12]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -1008,10 +936,10 @@ Passed: The following path meets requirements by 0.379ns
       Data path SLICE_3 to SLICE_3:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     0.132       R2C8C.Q0 to       R2C8C.A0 FS[11]
-CTOF_DEL    ---     0.101       R2C8C.A0 to       R2C8C.F0 SLICE_3
-ROUTE         1     0.000       R2C8C.F0 to      R2C8C.DI0 FS_s[11] (to C14M_c)
+REG_DEL     ---     0.133     R2C10C.CLK to      R2C10C.Q1 SLICE_3 (from C14M_c)
+ROUTE        24     0.132      R2C10C.Q1 to      R2C10C.A1 FS[12]
+CTOF_DEL    ---     0.101      R2C10C.A1 to      R2C10C.F1 SLICE_3
+ROUTE         1     0.000      R2C10C.F1 to     R2C10C.DI1 FS_s[12] (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -1020,14 +948,14 @@ ROUTE         1     0.000       R2C8C.F0 to      R2C8C.DI0 FS_s[11] (to C14M_c)
       Source Clock Path C14M to SLICE_3:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C8C.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C10C.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
       Destination Clock Path C14M to SLICE_3:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C8C.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C10C.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -1036,43 +964,133 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              Ready  (from C14M_c +)
-   Destination:    FF         Data in        Ready  (to C14M_c +)
+   Source:         FF         Q              FS[10]  (from C14M_c +)
+   Destination:    FF         Data in        FS[10]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
  Constraint Details:
 
-      0.366ns physical path delay SLICE_32 to SLICE_32 meets
+      0.366ns physical path delay SLICE_4 to SLICE_4 meets
      -0.013ns DIN_HLD and
       0.000ns delay constraint less
       0.000ns skew requirement (totaling -0.013ns) by 0.379ns
 
  Physical Path Details:
 
-      Data path SLICE_32 to SLICE_32:
+      Data path SLICE_4 to SLICE_4:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C9C.CLK to       R2C9C.Q0 SLICE_32 (from C14M_c)
-ROUTE         2     0.132       R2C9C.Q0 to       R2C9C.A0 Ready
-CTOF_DEL    ---     0.101       R2C9C.A0 to       R2C9C.F0 SLICE_32
-ROUTE         1     0.000       R2C9C.F0 to      R2C9C.DI0 N_876_0 (to C14M_c)
+REG_DEL     ---     0.133     R2C10B.CLK to      R2C10B.Q1 SLICE_4 (from C14M_c)
+ROUTE        19     0.132      R2C10B.Q1 to      R2C10B.A1 FS[10]
+CTOF_DEL    ---     0.101      R2C10B.A1 to      R2C10B.F1 SLICE_4
+ROUTE         1     0.000      R2C10B.F1 to     R2C10B.DI1 FS_s[10] (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_32:
+      Source Clock Path C14M to SLICE_4:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C9C.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C10B.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_32:
+      Destination Clock Path C14M to SLICE_4:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C9C.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C10B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[7]  (from C14M_c +)
+   Destination:    FF         Data in        FS[7]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_5 to SLICE_5 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R2C10A.CLK to      R2C10A.Q0 SLICE_5 (from C14M_c)
+ROUTE         4     0.132      R2C10A.Q0 to      R2C10A.A0 FS[7]
+CTOF_DEL    ---     0.101      R2C10A.A0 to      R2C10A.F0 SLICE_5
+ROUTE         1     0.000      R2C10A.F0 to     R2C10A.DI0 FS_s[7] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R2C10A.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R2C10A.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[6]  (from C14M_c +)
+   Destination:    FF         Data in        FS[6]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_6 to SLICE_6 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C9D.CLK to       R2C9D.Q1 SLICE_6 (from C14M_c)
+ROUTE         4     0.132       R2C9D.Q1 to       R2C9D.A1 FS[6]
+CTOF_DEL    ---     0.101       R2C9D.A1 to       R2C9D.F1 SLICE_6
+ROUTE         1     0.000       R2C9D.F1 to      R2C9D.DI1 FS_s[6] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to      R2C9D.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to      R2C9D.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -1082,7 +1100,7 @@ Report Summary
 Preference(MIN Delays)                  |   Constraint|       Actual|Levels
 ----------------------------------------------------------------------------
                                         |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   1  
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   2  
                                         |             |             |
 ----------------------------------------------------------------------------
 
@@ -1095,7 +1113,7 @@ Clock Domains Analysis
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -1105,7 +1123,7 @@ Timing summary (Hold):
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html
index b99737b..d8cbb0f 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html
@@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Sep 21 05:35:15 2023
+Thu Dec 28 23:10:24 2023
 
 
-Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC -w -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
 
 Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
 Design name: RAM2E
@@ -81,8 +81,8 @@ Creating bit map...
 Bitstream Status: Final           Version 1.95.
  
 Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.bit".
-Total CPU Time: 4 secs 
-Total REAL Time: 5 secs 
+Total CPU Time: 3 secs 
+Total REAL Time: 4 secs 
 Peak Memory Usage: 267 MB
 
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt
index 0d70461..9464162 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt
@@ -13,12 +13,12 @@ Hostname: ZANEMACWIN11
 
 Implementation : impl1
 
-# Written on Thu Sep 21 05:34:37 2023
+# Written on Thu Dec 28 23:09:49 2023
 
 ##### DESIGN INFO #######################################################
 
 Top View:                "RAM2E"
-Constraint File(s):      "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
+Constraint File(s):      "\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc"
 
 
 
@@ -58,7 +58,7 @@ p:Ain[6]
 p:Ain[7]
 p:BA[0]
 p:BA[1]
-p:CKE
+p:CKEout
 p:DQMH
 p:DQML
 p:Din[0]
@@ -79,18 +79,18 @@ p:Dout[6]
 p:Dout[7]
 p:LED
 p:PHI1
-p:RA[0]
-p:RA[1]
-p:RA[2]
-p:RA[3]
-p:RA[4]
-p:RA[5]
-p:RA[6]
-p:RA[7]
-p:RA[8]
-p:RA[9]
-p:RA[10]
-p:RA[11]
+p:RAout[0]
+p:RAout[1]
+p:RAout[2]
+p:RAout[3]
+p:RAout[4]
+p:RAout[5]
+p:RAout[6]
+p:RAout[7]
+p:RAout[8]
+p:RAout[9]
+p:RAout[10]
+p:RAout[11]
 p:RD[0] (bidir end point)
 p:RD[0] (bidir start point)
 p:RD[1] (bidir end point)
@@ -116,12 +116,12 @@ p:Vout[5]
 p:Vout[6]
 p:Vout[7]
 p:nC07X
-p:nCAS
-p:nCS
+p:nCASout
+p:nCSout
 p:nDOE
 p:nEN80
-p:nRAS
-p:nRWE
+p:nRASout
+p:nRWEout
 p:nVOE
 p:nWE
 p:nWE80
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_iotiming.html
index d93cff5..9f56fda 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_iotiming.html
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_iotiming.html
@@ -38,9 +38,9 @@ Performance Hardware Data Status:   Final          Version 34.4.
 // Package: TQFP100
 // ncd File: ram2e_lcmxo2_640hc_impl1.ncd
 // Version: Diamond (64-bit) 3.12.1.454
-// Written on Thu Sep 21 05:35:10 2023
+// Written on Thu Dec 28 23:10:19 2023
 // M: Minimum Performance Grade
-// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
+// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml
 
 I/O Timing Report (All units are in ns)
 
@@ -50,81 +50,82 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
 
 Port   Clock Edge  Setup Performance_Grade  Hold Performance_Grade
 ----------------------------------------------------------------------
-Ain[0] C14M  R     0.502      4       0.868     4
-Ain[1] C14M  R     2.364      4      -0.126     M
-Ain[2] C14M  R     2.421      4      -0.129     M
-Ain[3] C14M  R     0.574      4       0.786     4
-Ain[4] C14M  R     1.452      4       0.140     M
-Ain[5] C14M  R     2.076      4      -0.039     M
-Ain[6] C14M  R     1.515      4       0.124     M
-Ain[7] C14M  R     2.270      4      -0.095     M
-Din[0] C14M  R     9.252      4       1.162     4
-Din[1] C14M  R     8.868      4       0.657     4
-Din[2] C14M  R     8.368      4       0.864     4
-Din[3] C14M  R     8.749      4       1.339     4
-Din[4] C14M  R     9.095      4       0.770     4
-Din[5] C14M  R     8.195      4       1.176     4
-Din[6] C14M  R     6.162      4       0.760     4
-Din[7] C14M  R     7.060      4       1.093     4
-PHI1   C14M  R     2.045      4       3.047     4
-RD[0]  C14M  F     0.267      4       0.866     4
-RD[1]  C14M  F     0.173      4       1.383     4
-RD[2]  C14M  F     0.924      4       1.018     4
-RD[3]  C14M  F     0.267      4       0.866     4
-RD[4]  C14M  F     0.173      4       0.937     4
-RD[5]  C14M  F     0.267      4       0.866     4
-RD[6]  C14M  F     0.766      4       0.866     4
-RD[7]  C14M  F     0.267      4       1.312     4
-nC07X  C14M  R     0.077      4       1.144     4
-nEN80  C14M  R     6.415      4      -0.286     M
-nWE    C14M  R     0.691      4       0.684     4
-nWE80  C14M  R     2.845      4      -0.260     M
+Ain[0] C14M  R     2.463      4      -0.066     M
+Ain[1] C14M  R     1.330      4       0.135     6
+Ain[2] C14M  R     1.221      4       0.223     4
+Ain[3] C14M  R     2.776      4      -0.165     M
+Ain[4] C14M  R     1.603      4       0.140     M
+Ain[5] C14M  R     0.021      6       1.287     4
+Ain[6] C14M  R     1.444      4       0.205     M
+Ain[7] C14M  R     1.816      4       0.114     M
+Din[0] C14M  R     8.919      4       0.723     4
+Din[1] C14M  R     8.410      4       1.156     4
+Din[2] C14M  R     8.503      4       1.181     4
+Din[3] C14M  R     8.783      4       0.110     M
+Din[4] C14M  R    10.420      4       1.022     4
+Din[5] C14M  R     8.001      4       0.566     4
+Din[6] C14M  R     9.731      4       1.050     4
+Din[7] C14M  R    10.052      4       0.862     4
+PHI1   C14M  R     2.579      4       3.047     4
+RD[0]  C14M  R     0.267      4       0.866     4
+RD[1]  C14M  R     0.173      4       0.937     4
+RD[2]  C14M  R     0.100      4       1.018     4
+RD[3]  C14M  R     0.267      4       0.866     4
+RD[4]  C14M  R     0.172      4       0.936     4
+RD[5]  C14M  R     0.267      4       0.866     4
+RD[6]  C14M  R     0.766      4       0.420     4
+RD[7]  C14M  R     0.267      4       0.866     4
+nC07X  C14M  R     0.998      4       0.405     6
+nEN80  C14M  R     6.107      4       0.114     M
+nWE    C14M  R     6.726      4       0.069     M
 
 
 // Clock to Output Delay
 
-Port    Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+Port      Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
 ------------------------------------------------------------------------
-BA[0]   C14M  R     8.629         4        2.885          M
-BA[1]   C14M  R     8.629         4        2.885          M
-CKE     C14M  R     8.629         4        2.885          M
-DQMH    C14M  R     8.609         4        2.892          M
-DQML    C14M  R     8.609         4        2.892          M
-Dout[0] C14M  F     8.955         4        3.164          M
-Dout[1] C14M  F     8.955         4        3.164          M
-Dout[2] C14M  F     8.944         4        3.158          M
-Dout[3] C14M  F     8.955         4        3.164          M
-Dout[4] C14M  F     8.944         4        3.158          M
-Dout[5] C14M  F     8.944         4        3.158          M
-Dout[6] C14M  F     8.955         4        3.164          M
-Dout[7] C14M  F     8.955         4        3.164          M
-LED     C14M  R    19.941         4        8.191          M
-RA[0]   C14M  R    10.013         4        3.186          M
-RA[10]  C14M  R     8.629         4        2.885          M
-RA[11]  C14M  R     8.629         4        2.885          M
-RA[1]   C14M  R     8.695         4        2.890          M
-RA[2]   C14M  R     8.695         4        2.890          M
-RA[3]   C14M  R    10.013         4        3.186          M
-RA[4]   C14M  R     8.695         4        2.890          M
-RA[5]   C14M  R     8.695         4        2.890          M
-RA[6]   C14M  R     8.695         4        2.890          M
-RA[7]   C14M  R     8.695         4        2.890          M
-RA[8]   C14M  R     8.629         4        2.885          M
-RA[9]   C14M  R     8.629         4        2.885          M
-Vout[0] C14M  F     9.553         4        3.402          M
-Vout[1] C14M  F     9.553         4        3.402          M
-Vout[2] C14M  F     9.553         4        3.402          M
-Vout[3] C14M  F     9.553         4        3.402          M
-Vout[4] C14M  F     9.553         4        3.402          M
-Vout[5] C14M  F     9.553         4        3.402          M
-Vout[6] C14M  F     9.553         4        3.402          M
-Vout[7] C14M  F     9.553         4        3.402          M
-nCAS    C14M  R     8.629         4        2.885          M
-nCS     C14M  R     8.629         4        2.885          M
-nDOE    C14M  R    11.976         4        3.776          M
-nRAS    C14M  R     8.629         4        2.885          M
-nRWE    C14M  R     8.629         4        2.885          M
+BA[0]     C14M  R     8.629         4        2.885          M
+BA[1]     C14M  R     8.629         4        2.885          M
+CKEout    C14M  F     8.629         4        2.885          M
+DQMH      C14M  R     8.609         4        2.892          M
+DQML      C14M  R     8.609         4        2.892          M
+LED       C14M  R    19.935         4        8.161          M
+RAout[0]  C14M  F     8.695         4        2.890          M
+RAout[10] C14M  F     8.629         4        2.885          M
+RAout[11] C14M  F     8.629         4        2.885          M
+RAout[1]  C14M  F     8.695         4        2.890          M
+RAout[2]  C14M  F     8.695         4        2.890          M
+RAout[3]  C14M  F     8.695         4        2.890          M
+RAout[4]  C14M  F     8.695         4        2.890          M
+RAout[5]  C14M  F     8.695         4        2.890          M
+RAout[6]  C14M  F     8.695         4        2.890          M
+RAout[7]  C14M  F     8.695         4        2.890          M
+RAout[8]  C14M  F     8.629         4        2.885          M
+RAout[9]  C14M  F     8.629         4        2.885          M
+RD[0]     C14M  R    11.414         4        3.265          M
+RD[1]     C14M  R    11.811         4        3.265          M
+RD[2]     C14M  R    11.925         4        3.265          M
+RD[3]     C14M  R    11.384         4        3.265          M
+RD[4]     C14M  R    12.301         4        3.371          M
+RD[5]     C14M  R    12.767         4        3.371          M
+RD[6]     C14M  R    12.010         4        3.371          M
+RD[7]     C14M  R    12.313         4        3.371          M
+Vout[0]   C14M  R     9.553         4        3.402          M
+Vout[1]   C14M  R     9.553         4        3.402          M
+Vout[2]   C14M  R     9.553         4        3.402          M
+Vout[3]   C14M  R     9.553         4        3.402          M
+Vout[4]   C14M  R     9.553         4        3.402          M
+Vout[5]   C14M  R     9.553         4        3.402          M
+Vout[6]   C14M  R     9.553         4        3.402          M
+Vout[7]   C14M  R     9.553         4        3.402          M
+nCASout   C14M  F     8.629         4        2.885          M
+nDOE      C14M  R    12.048         4        3.811          M
+nRASout   C14M  F     8.629         4        2.885          M
+nRWEout   C14M  F     8.629         4        2.885          M
+nVOE      C14M  R    12.164         4        3.783          M
 WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with setup speed: 6
+WARNING: you must also run trce with hold speed: 6
 
 
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf
index 85e4f67..492a1c7 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf
@@ -1,7 +1,7 @@
 (DELAYFILE
   (SDFVERSION "3.0")
   (DESIGN "RAM2E")
-  (DATE "Thu Sep 21 05:34:50 2023")
+  (DATE "Thu Dec 28 23:10:01 2023")
   (VENDOR "Lattice")
   (PROGRAM "ldbanno")
   (VERSION "Diamond (64-bit) 3.12.1.454")
@@ -233,9 +233,30 @@
     (INSTANCE SLICE_9)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_10")
+    (INSTANCE SLICE_10)
+    (DELAY
+      (ABSOLUTE
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -251,14 +272,37 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_10")
-    (INSTANCE SLICE_10)
+    (CELLTYPE "SLICE_11")
+    (INSTANCE SLICE_11)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_12")
+    (INSTANCE SLICE_12)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -279,13 +323,15 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_11")
-    (INSTANCE SLICE_11)
+    (CELLTYPE "SLICE_13")
+    (INSTANCE SLICE_13)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -303,60 +349,11 @@
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
   )
-  (CELL
-    (CELLTYPE "SLICE_12")
-    (INSTANCE SLICE_12)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_13")
-    (INSTANCE SLICE_13)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
   (CELL
     (CELLTYPE "SLICE_14")
     (INSTANCE SLICE_14)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -381,10 +378,10 @@
     (INSTANCE SLICE_15)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -405,6 +402,7 @@
     (INSTANCE SLICE_16)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -427,30 +425,6 @@
   (CELL
     (CELLTYPE "SLICE_17")
     (INSTANCE SLICE_17)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_18")
-    (INSTANCE SLICE_18)
     (DELAY
       (ABSOLUTE
         (IOPATH C1 F1 (367:431:495)(367:431:495))
@@ -473,8 +447,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19)
+    (CELLTYPE "SLICE_18")
+    (INSTANCE SLICE_18)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -498,6 +472,29 @@
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
   )
+  (CELL
+    (CELLTYPE "SLICE_19")
+    (INSTANCE SLICE_19)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
+      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (4000:4000:4000))
+      (WIDTH (negedge LSR) (4000:4000:4000))
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
   (CELL
     (CELLTYPE "SLICE_20")
     (INSTANCE SLICE_20)
@@ -512,10 +509,13 @@
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -530,13 +530,16 @@
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
@@ -550,6 +553,7 @@
     (INSTANCE SLICE_22)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -603,6 +607,7 @@
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -625,9 +630,11 @@
     (INSTANCE SLICE_25)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -775,6 +782,7 @@
     (INSTANCE SLICE_31)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -877,20 +885,18 @@
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
     )
     (TIMINGCHECK
+      (WIDTH (posedge LSR) (4000:4000:4000))
+      (WIDTH (negedge LSR) (4000:4000:4000))
       (WIDTH (posedge CLK) (1250:1250:1250))
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
@@ -900,18 +906,19 @@
     (INSTANCE SLICE_36)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -923,20 +930,19 @@
     (INSTANCE SLICE_37)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -948,6 +954,127 @@
     (INSTANCE SLICE_38)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_39")
+    (INSTANCE ram2e_ufm\/SLICE_39)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_40")
+    (INSTANCE ram2e_ufm\/SLICE_40)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_41")
+    (INSTANCE ram2e_ufm\/SLICE_41)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_42")
+    (INSTANCE ram2e_ufm\/SLICE_42)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_43")
+    (INSTANCE ram2e_ufm\/SLICE_43)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -968,11 +1095,10 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39)
+    (CELLTYPE "ram2e_ufm_SLICE_44")
+    (INSTANCE ram2e_ufm\/SLICE_44)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -980,9 +1106,11 @@
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
@@ -992,8 +1120,58 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_40")
-    (INSTANCE SLICE_40)
+    (CELLTYPE "ram2e_ufm_SLICE_45")
+    (INSTANCE ram2e_ufm\/SLICE_45)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_46")
+    (INSTANCE ram2e_ufm\/SLICE_46)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_47")
+    (INSTANCE ram2e_ufm\/SLICE_47)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1019,14 +1197,36 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41)
+    (CELLTYPE "ram2e_ufm_SLICE_48")
+    (INSTANCE ram2e_ufm\/SLICE_48)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_49")
+    (INSTANCE ram2e_ufm\/SLICE_49)
     (DELAY
       (ABSOLUTE
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1045,8 +1245,56 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42)
+    (CELLTYPE "ram2e_ufm_SLICE_50")
+    (INSTANCE ram2e_ufm\/SLICE_50)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_51")
+    (INSTANCE ram2e_ufm\/SLICE_51)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_52")
+    (INSTANCE ram2e_ufm\/SLICE_52)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1072,14 +1320,15 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43)
+    (CELLTYPE "ram2e_ufm_SLICE_53")
+    (INSTANCE ram2e_ufm\/SLICE_53)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -1098,10 +1347,65 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44)
+    (CELLTYPE "ram2e_ufm_SLICE_54")
+    (INSTANCE ram2e_ufm\/SLICE_54)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_55")
+    (INSTANCE ram2e_ufm\/SLICE_55)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_56")
+    (INSTANCE ram2e_ufm\/SLICE_56)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -1125,10 +1429,12 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_45")
-    (INSTANCE SLICE_45)
+    (CELLTYPE "ram2e_ufm_SLICE_57")
+    (INSTANCE ram2e_ufm\/SLICE_57)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -1148,8 +1454,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_46")
-    (INSTANCE SLICE_46)
+    (CELLTYPE "ram2e_ufm_SLICE_58")
+    (INSTANCE ram2e_ufm\/SLICE_58)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1173,8 +1479,54 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_47")
-    (INSTANCE SLICE_47)
+    (CELLTYPE "ram2e_ufm_SUM0_i_m3_0_SLICE_59")
+    (INSTANCE ram2e_ufm\/SUM0_i_m3_0\/SLICE_59)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60")
+    (INSTANCE ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_CKE_7_SLICE_61")
+    (INSTANCE ram2e_ufm\/CKE_7\/SLICE_61)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_62")
+    (INSTANCE ram2e_ufm\/SLICE_62)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1189,8 +1541,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_48")
-    (INSTANCE SLICE_48)
+    (CELLTYPE "ram2e_ufm_SLICE_63")
+    (INSTANCE ram2e_ufm\/SLICE_63)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1205,8 +1557,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_49")
-    (INSTANCE SLICE_49)
+    (CELLTYPE "ram2e_ufm_SLICE_64")
+    (INSTANCE ram2e_ufm\/SLICE_64)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_65")
+    (INSTANCE ram2e_ufm\/SLICE_65)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1221,8 +1588,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50)
+    (CELLTYPE "ram2e_ufm_SLICE_66")
+    (INSTANCE ram2e_ufm\/SLICE_66)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1237,8 +1604,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51)
+    (CELLTYPE "ram2e_ufm_SLICE_67")
+    (INSTANCE ram2e_ufm\/SLICE_67)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_68")
+    (INSTANCE ram2e_ufm\/SLICE_68)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1253,8 +1635,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52)
+    (CELLTYPE "ram2e_ufm_SLICE_69")
+    (INSTANCE ram2e_ufm\/SLICE_69)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1269,8 +1651,52 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_53")
-    (INSTANCE SLICE_53)
+    (CELLTYPE "ram2e_ufm_SLICE_70")
+    (INSTANCE ram2e_ufm\/SLICE_70)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_71")
+    (INSTANCE ram2e_ufm\/SLICE_71)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_72")
+    (INSTANCE ram2e_ufm\/SLICE_72)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_73")
+    (INSTANCE ram2e_ufm\/SLICE_73)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1285,8 +1711,81 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_54")
-    (INSTANCE SLICE_54)
+    (CELLTYPE "ram2e_ufm_SLICE_74")
+    (INSTANCE ram2e_ufm\/SLICE_74)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_75")
+    (INSTANCE ram2e_ufm\/SLICE_75)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_76")
+    (INSTANCE ram2e_ufm\/SLICE_76)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_77")
+    (INSTANCE ram2e_ufm\/SLICE_77)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_78")
+    (INSTANCE ram2e_ufm\/SLICE_78)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_79")
+    (INSTANCE ram2e_ufm\/SLICE_79)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1301,8 +1800,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55)
+    (CELLTYPE "ram2e_ufm_SLICE_80")
+    (INSTANCE ram2e_ufm\/SLICE_80)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1317,22 +1816,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57)
+    (CELLTYPE "ram2e_ufm_SLICE_81")
+    (INSTANCE ram2e_ufm\/SLICE_81)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1347,8 +1832,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58)
+    (CELLTYPE "ram2e_ufm_SLICE_82")
+    (INSTANCE ram2e_ufm\/SLICE_82)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1363,8 +1848,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59)
+    (CELLTYPE "ram2e_ufm_SLICE_83")
+    (INSTANCE ram2e_ufm\/SLICE_83)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_84")
+    (INSTANCE ram2e_ufm\/SLICE_84)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1379,126 +1879,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_65")
-    (INSTANCE SLICE_65)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68)
+    (CELLTYPE "ram2e_ufm_SLICE_85")
+    (INSTANCE ram2e_ufm\/SLICE_85)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1513,8 +1895,66 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69)
+    (CELLTYPE "ram2e_ufm_SLICE_86")
+    (INSTANCE ram2e_ufm\/SLICE_86)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_87")
+    (INSTANCE ram2e_ufm\/SLICE_87)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_88")
+    (INSTANCE ram2e_ufm\/SLICE_88)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_89")
+    (INSTANCE ram2e_ufm\/SLICE_89)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_90")
+    (INSTANCE ram2e_ufm\/SLICE_90)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1529,8 +1969,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70)
+    (CELLTYPE "ram2e_ufm_SLICE_91")
+    (INSTANCE ram2e_ufm\/SLICE_91)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1545,8 +1985,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71)
+    (CELLTYPE "ram2e_ufm_SLICE_92")
+    (INSTANCE ram2e_ufm\/SLICE_92)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1561,8 +2001,37 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72)
+    (CELLTYPE "ram2e_ufm_SLICE_93")
+    (INSTANCE ram2e_ufm\/SLICE_93)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_94")
+    (INSTANCE ram2e_ufm\/SLICE_94)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_95")
+    (INSTANCE ram2e_ufm\/SLICE_95)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1577,8 +2046,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73)
+    (CELLTYPE "ram2e_ufm_SLICE_96")
+    (INSTANCE ram2e_ufm\/SLICE_96)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1593,8 +2062,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74)
+    (CELLTYPE "ram2e_ufm_SLICE_97")
+    (INSTANCE ram2e_ufm\/SLICE_97)
     (DELAY
       (ABSOLUTE
         (IOPATH C1 F1 (367:431:495)(367:431:495))
@@ -1608,23 +2077,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76)
+    (CELLTYPE "ram2e_ufm_SLICE_98")
+    (INSTANCE ram2e_ufm\/SLICE_98)
     (DELAY
       (ABSOLUTE
         (IOPATH B1 F1 (367:431:495)(367:431:495))
@@ -1637,8 +2091,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77)
+    (CELLTYPE "ram2e_ufm_SLICE_99")
+    (INSTANCE ram2e_ufm\/SLICE_99)
     (DELAY
       (ABSOLUTE
         (IOPATH C1 F1 (367:431:495)(367:431:495))
@@ -1652,50 +2106,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81)
+    (CELLTYPE "ram2e_ufm_SLICE_100")
+    (INSTANCE ram2e_ufm\/SLICE_100)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1710,8 +2122,93 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82)
+    (CELLTYPE "ram2e_ufm_SLICE_101")
+    (INSTANCE ram2e_ufm\/SLICE_101)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_102")
+    (INSTANCE ram2e_ufm\/SLICE_102)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_103")
+    (INSTANCE ram2e_ufm\/SLICE_103)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_104")
+    (INSTANCE ram2e_ufm\/SLICE_104)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_105")
+    (INSTANCE ram2e_ufm\/SLICE_105)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_106")
+    (INSTANCE ram2e_ufm\/SLICE_106)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_107")
+    (INSTANCE ram2e_ufm\/SLICE_107)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1726,8 +2223,140 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83)
+    (CELLTYPE "ram2e_ufm_SLICE_108")
+    (INSTANCE ram2e_ufm\/SLICE_108)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_109")
+    (INSTANCE ram2e_ufm\/SLICE_109)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_110")
+    (INSTANCE ram2e_ufm\/SLICE_110)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_111")
+    (INSTANCE ram2e_ufm\/SLICE_111)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_112")
+    (INSTANCE ram2e_ufm\/SLICE_112)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_113")
+    (INSTANCE ram2e_ufm\/SLICE_113)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_114")
+    (INSTANCE ram2e_ufm\/SLICE_114)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_115")
+    (INSTANCE ram2e_ufm\/SLICE_115)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_116")
+    (INSTANCE ram2e_ufm\/SLICE_116)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_117")
+    (INSTANCE ram2e_ufm\/SLICE_117)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1742,8 +2371,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84)
+    (CELLTYPE "ram2e_ufm_SLICE_118")
+    (INSTANCE ram2e_ufm\/SLICE_118)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1758,8 +2387,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85)
+    (CELLTYPE "ram2e_ufm_SLICE_119")
+    (INSTANCE ram2e_ufm\/SLICE_119)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1774,8 +2403,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86)
+    (CELLTYPE "ram2e_ufm_SLICE_120")
+    (INSTANCE ram2e_ufm\/SLICE_120)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1790,81 +2419,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92)
+    (CELLTYPE "ram2e_ufm_SLICE_121")
+    (INSTANCE ram2e_ufm\/SLICE_121)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1879,8 +2435,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93)
+    (CELLTYPE "ram2e_ufm_SLICE_122")
+    (INSTANCE ram2e_ufm\/SLICE_122)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1895,8 +2451,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94)
+    (CELLTYPE "ram2e_ufm_SLICE_123")
+    (INSTANCE ram2e_ufm\/SLICE_123)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_124")
+    (INSTANCE ram2e_ufm\/SLICE_124)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1911,8 +2482,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_95")
-    (INSTANCE SLICE_95)
+    (CELLTYPE "ram2e_ufm_SLICE_125")
+    (INSTANCE ram2e_ufm\/SLICE_125)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1927,80 +2498,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_96")
-    (INSTANCE SLICE_96)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_97")
-    (INSTANCE SLICE_97)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_98")
-    (INSTANCE SLICE_98)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_99")
-    (INSTANCE SLICE_99)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_100")
-    (INSTANCE SLICE_100)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_101")
-    (INSTANCE SLICE_101)
+    (CELLTYPE "ram2e_ufm_SLICE_126")
+    (INSTANCE ram2e_ufm\/SLICE_126)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2015,8 +2514,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_102")
-    (INSTANCE SLICE_102)
+    (CELLTYPE "ram2e_ufm_SLICE_127")
+    (INSTANCE ram2e_ufm\/SLICE_127)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2031,8 +2530,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_103")
-    (INSTANCE SLICE_103)
+    (CELLTYPE "ram2e_ufm_SLICE_128")
+    (INSTANCE ram2e_ufm\/SLICE_128)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_129")
+    (INSTANCE ram2e_ufm\/SLICE_129)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2047,8 +2561,22 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_104")
-    (INSTANCE SLICE_104)
+    (CELLTYPE "ram2e_ufm_SLICE_130")
+    (INSTANCE ram2e_ufm\/SLICE_130)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_131")
+    (INSTANCE ram2e_ufm\/SLICE_131)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2063,8 +2591,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_105")
-    (INSTANCE SLICE_105)
+    (CELLTYPE "ram2e_ufm_SLICE_132")
+    (INSTANCE ram2e_ufm\/SLICE_132)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2079,41 +2607,14 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_106")
-    (INSTANCE SLICE_106)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_107")
-    (INSTANCE SLICE_107)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_108")
-    (INSTANCE SLICE_108)
+    (CELLTYPE "ram2e_ufm_SLICE_133")
+    (INSTANCE ram2e_ufm\/SLICE_133)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -2121,8 +2622,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_109")
-    (INSTANCE SLICE_109)
+    (CELLTYPE "ram2e_ufm_SLICE_134")
+    (INSTANCE ram2e_ufm\/SLICE_134)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2137,8 +2638,152 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_110")
-    (INSTANCE SLICE_110)
+    (CELLTYPE "ram2e_ufm_SLICE_135")
+    (INSTANCE ram2e_ufm\/SLICE_135)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_136")
+    (INSTANCE ram2e_ufm\/SLICE_136)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_137")
+    (INSTANCE ram2e_ufm\/SLICE_137)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_138")
+    (INSTANCE SLICE_138)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_139")
+    (INSTANCE SLICE_139)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_140")
+    (INSTANCE ram2e_ufm\/SLICE_140)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_141")
+    (INSTANCE ram2e_ufm\/SLICE_141)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_142")
+    (INSTANCE ram2e_ufm\/SLICE_142)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_143")
+    (INSTANCE ram2e_ufm\/SLICE_143)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_144")
+    (INSTANCE ram2e_ufm\/SLICE_144)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_145")
+    (INSTANCE ram2e_ufm\/SLICE_145)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_146")
+    (INSTANCE ram2e_ufm\/SLICE_146)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2153,125 +2798,14 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_111")
-    (INSTANCE SLICE_111)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_112")
-    (INSTANCE SLICE_112)
+    (CELLTYPE "ram2e_ufm_SLICE_147")
+    (INSTANCE ram2e_ufm\/SLICE_147)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_113")
-    (INSTANCE SLICE_113)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_114")
-    (INSTANCE SLICE_114)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_115")
-    (INSTANCE SLICE_115)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_116")
-    (INSTANCE SLICE_116)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_117")
-    (INSTANCE SLICE_117)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_118")
-    (INSTANCE SLICE_118)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_119")
-    (INSTANCE SLICE_119)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
       )
@@ -2315,56 +2849,6 @@
       (WIDTH (negedge C14M) (3330:3330:3330))
     )
   )
-  (CELL
-    (CELLTYPE "DQMH")
-    (INSTANCE DQMH_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO DQMH (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "DQMH_MGIOL")
-    (INSTANCE DQMH_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "DQML")
-    (INSTANCE DQML_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO DQML (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "DQML_MGIOL")
-    (INSTANCE DQML_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
   (CELL
     (CELLTYPE "RD_7_")
     (INSTANCE RD\[7\]_I)
@@ -2478,117 +2962,17 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_11_")
-    (INSTANCE RA\[11\]_I)
+    (CELLTYPE "DQMH")
+    (INSTANCE DQMH_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA11 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO DQMH (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_11__MGIOL")
-    (INSTANCE RA\[11\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_")
-    (INSTANCE RA\[10\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA10 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10__MGIOL")
-    (INSTANCE RA\[10\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_")
-    (INSTANCE RA\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA9 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9__MGIOL")
-    (INSTANCE RA\[9\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_")
-    (INSTANCE RA\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA8 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8__MGIOL")
-    (INSTANCE RA\[8\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_")
-    (INSTANCE RA\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA7 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7__MGIOL")
-    (INSTANCE RA\[7\]_MGIOL)
+    (CELLTYPE "DQMH_MGIOL")
+    (INSTANCE DQMH_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
@@ -2604,17 +2988,17 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_6_")
-    (INSTANCE RA\[6\]_I)
+    (CELLTYPE "DQML")
+    (INSTANCE DQML_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA6 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO DQML (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_6__MGIOL")
-    (INSTANCE RA\[6\]_MGIOL)
+    (CELLTYPE "DQML_MGIOL")
+    (INSTANCE DQML_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
@@ -2630,127 +3014,305 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_5_")
-    (INSTANCE RA\[5\]_I)
+    (CELLTYPE "RAout_11_")
+    (INSTANCE RAout\[11\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA5 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO RAout11 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_5__MGIOL")
-    (INSTANCE RA\[5\]_MGIOL)
+    (CELLTYPE "RAout_11__MGIOL")
+    (INSTANCE RAout\[11\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_4_")
-    (INSTANCE RA\[4\]_I)
+    (CELLTYPE "RAout_10_")
+    (INSTANCE RAout\[10\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA4 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO RAout10 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_4__MGIOL")
-    (INSTANCE RA\[4\]_MGIOL)
+    (CELLTYPE "RAout_10__MGIOL")
+    (INSTANCE RAout\[10\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_3_")
-    (INSTANCE RA\[3\]_I)
+    (CELLTYPE "RAout_9_")
+    (INSTANCE RAout\[9\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH PADDO RA3 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO RAout9 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_2_")
-    (INSTANCE RA\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA2 (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2__MGIOL")
-    (INSTANCE RA\[2\]_MGIOL)
+    (CELLTYPE "RAout_9__MGIOL")
+    (INSTANCE RAout\[9\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_1_")
-    (INSTANCE RA\[1\]_I)
+    (CELLTYPE "RAout_8_")
+    (INSTANCE RAout\[8\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA1 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO RAout8 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_1__MGIOL")
-    (INSTANCE RA\[1\]_MGIOL)
+    (CELLTYPE "RAout_8__MGIOL")
+    (INSTANCE RAout\[8\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_7_")
+    (INSTANCE RAout\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout7 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_7__MGIOL")
+    (INSTANCE RAout\[7\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_0_")
-    (INSTANCE RA\[0\]_I)
+    (CELLTYPE "RAout_6_")
+    (INSTANCE RAout\[6\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH PADDO RA0 (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO RAout6 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
+  (CELL
+    (CELLTYPE "RAout_6__MGIOL")
+    (INSTANCE RAout\[6\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_5_")
+    (INSTANCE RAout\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout5 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_5__MGIOL")
+    (INSTANCE RAout\[5\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_4_")
+    (INSTANCE RAout\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout4 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_4__MGIOL")
+    (INSTANCE RAout\[4\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_3_")
+    (INSTANCE RAout\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout3 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_3__MGIOL")
+    (INSTANCE RAout\[3\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_2_")
+    (INSTANCE RAout\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout2 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_2__MGIOL")
+    (INSTANCE RAout\[2\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_1_")
+    (INSTANCE RAout\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout1 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_1__MGIOL")
+    (INSTANCE RAout\[1\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_0_")
+    (INSTANCE RAout\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout0 (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_0__MGIOL")
+    (INSTANCE RAout\[0\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
   (CELL
     (CELLTYPE "BA_1_")
     (INSTANCE BA\[1\]_I)
@@ -2770,6 +3332,7 @@
     )
     (TIMINGCHECK
       (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
       (SETUPHOLD LSR (posedge CLK) (100:100:100)(-90:-90:-90))
     )
     (TIMINGCHECK
@@ -2796,6 +3359,7 @@
     )
     (TIMINGCHECK
       (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
       (SETUPHOLD LSR (posedge CLK) (100:100:100)(-90:-90:-90))
     )
     (TIMINGCHECK
@@ -2804,128 +3368,112 @@
     )
   )
   (CELL
-    (CELLTYPE "nRWE")
-    (INSTANCE nRWE_I)
+    (CELLTYPE "nRWEout")
+    (INSTANCE nRWEout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nRWE (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO nRWEout (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "nRWE_MGIOL")
-    (INSTANCE nRWE_MGIOL)
+    (CELLTYPE "nRWEout_MGIOL")
+    (INSTANCE nRWEout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nCAS")
-    (INSTANCE nCAS_I)
+    (CELLTYPE "nCASout")
+    (INSTANCE nCASout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nCAS (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO nCASout (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "nCAS_MGIOL")
-    (INSTANCE nCAS_MGIOL)
+    (CELLTYPE "nCASout_MGIOL")
+    (INSTANCE nCASout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nRAS")
-    (INSTANCE nRAS_I)
+    (CELLTYPE "nRASout")
+    (INSTANCE nRASout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nRAS (2927:3031:3136)(2927:3031:3136))
+        (IOPATH IOLDO nRASout (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "nRAS_MGIOL")
-    (INSTANCE nRAS_MGIOL)
+    (CELLTYPE "nRASout_MGIOL")
+    (INSTANCE nRASout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nCS")
-    (INSTANCE nCS_I)
+    (CELLTYPE "nCSout")
+    (INSTANCE nCSout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nCS (2927:3031:3136)(2927:3031:3136))
+        (IOPATH PADDO nCSout (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
   (CELL
-    (CELLTYPE "nCS_MGIOL")
-    (INSTANCE nCS_MGIOL)
+    (CELLTYPE "CKEout")
+    (INSTANCE CKEout_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO CKEout (2927:3031:3136)(2927:3031:3136))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "CKEout_MGIOL")
+    (INSTANCE CKEout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
-  )
-  (CELL
-    (CELLTYPE "CKE")
-    (INSTANCE CKE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO CKE (2927:3031:3136)(2927:3031:3136))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "CKE_MGIOL")
-    (INSTANCE CKE_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
     )
   )
   (CELL
@@ -2955,12 +3503,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -2981,12 +3529,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3007,12 +3555,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3033,12 +3581,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3059,12 +3607,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3085,12 +3633,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3111,12 +3659,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3137,12 +3685,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3159,209 +3707,73 @@
     (INSTANCE Dout\[7\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout7 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout7 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_7__MGIOL")
-    (INSTANCE Dout\[7\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_6_")
     (INSTANCE Dout\[6\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout6 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout6 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_6__MGIOL")
-    (INSTANCE Dout\[6\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_5_")
     (INSTANCE Dout\[5\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout5 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout5 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_5__MGIOL")
-    (INSTANCE Dout\[5\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_4_")
     (INSTANCE Dout\[4\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout4 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout4 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_4__MGIOL")
-    (INSTANCE Dout\[4\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_3_")
     (INSTANCE Dout\[3\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout3 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout3 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_3__MGIOL")
-    (INSTANCE Dout\[3\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_2_")
     (INSTANCE Dout\[2\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout2 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout2 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_2__MGIOL")
-    (INSTANCE Dout\[2\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_1_")
     (INSTANCE Dout\[1\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout1 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout1 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_1__MGIOL")
-    (INSTANCE Dout\[1\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_0_")
     (INSTANCE Dout\[0\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout0 (2293:2420:2548)(2293:2420:2548))
+        (IOPATH PADDO Dout0 (2927:3031:3136)(2927:3031:3136))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_0__MGIOL")
-    (INSTANCE Dout\[0\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Din_7_")
     (INSTANCE Din\[7\]_I)
@@ -3596,19 +4008,6 @@
       (WIDTH (negedge nEN80) (3330:3330:3330))
     )
   )
-  (CELL
-    (CELLTYPE "nWE80")
-    (INSTANCE nWE80_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nWE80 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nWE80) (3330:3330:3330))
-      (WIDTH (negedge nWE80) (3330:3330:3330))
-    )
-  )
   (CELL
     (CELLTYPE "nWE")
     (INSTANCE nWE_I)
@@ -3653,7 +4052,7 @@
   )
   (CELL
     (CELLTYPE "EFB_Buffer_Block")
-    (INSTANCE ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20)
+    (INSTANCE ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20)
     (DELAY
       (ABSOLUTE
         (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278))
@@ -3700,10 +4099,11 @@
     (DELAY
       (ABSOLUTE
         (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_39/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_52/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_75/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_0/Q1 SLICE_119/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_51/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_69/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_105/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_108/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_146/A0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0))
@@ -3744,33 +4144,46 @@
         (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_39/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI SLICE_46/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_39/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_40/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_41/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_42/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_43/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_44/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_45/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_46/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_47/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_48/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_49/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_50/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_51/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_52/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_53/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_54/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_55/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_56/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_57/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_58/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI DQMH_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI DQML_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[11\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[10\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[9\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[8\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[7\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[6\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[5\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[4\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[2\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI RA\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[11\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[10\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[9\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[8\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[7\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[6\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[5\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[4\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[3\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[2\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI RAout\[0\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI BA\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI BA\[0\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI nRWE_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI nCAS_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI nRAS_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI nCS_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI CKE_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI nRWEout_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI nCASout_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI nRASout_MGIOL/CLK (0:0:0)(0:0:0))
+        (INTERCONNECT C14M_I/PADDI CKEout_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI Vout\[7\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI Vout\[6\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI Vout\[5\]_MGIOL/CLK (0:0:0)(0:0:0))
@@ -3779,1057 +4192,1300 @@
         (INTERCONNECT C14M_I/PADDI Vout\[2\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI Vout\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI Vout\[0\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[7\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[6\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[5\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[4\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[3\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[2\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[1\]_MGIOL/CLK (0:0:0)(0:0:0))
-        (INTERCONNECT C14M_I/PADDI Dout\[0\]_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI PHI1_MGIOL/CLK (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (0:0:0)(0:0:0))
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin 
+          (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_45/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_51/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_53/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_56/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_72/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_73/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_75/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_83/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_86/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_103/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 SLICE_9/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_69/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_80/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_105/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/A0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_37/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_37/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_38/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_39/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_44/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_45/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_45/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_56/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_66/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_73/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_86/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q1 SLICE_97/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 SLICE_23/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_50/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_51/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_56/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_66/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_70/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_81/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_85/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_89/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_98/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_109/A1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_35/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_44/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_46/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_56/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_60/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_61/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_65/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_66/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_73/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_74/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_88/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_90/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_92/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_97/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_108/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_2/Q0 SLICE_116/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 SLICE_23/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_56/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_58/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_64/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_70/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_75/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_76/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_81/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_85/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_89/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_97/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_103/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_111/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_125/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_128/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_128/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_131/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_131/B0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_44/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_46/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_56/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_58/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_60/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_61/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_62/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_64/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_65/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_66/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_70/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_73/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_74/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_84/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_88/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_90/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_92/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_95/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_97/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_108/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_108/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_56/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_58/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_68/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_70/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_75/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_76/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_81/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_85/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_90/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_93/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_97/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_99/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_103/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_104/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_111/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_114/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_124/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_126/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_126/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_128/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_128/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_131/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_131/A0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_44/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_50/D1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_58/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_61/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_62/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_64/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_65/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_66/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_68/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_70/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_73/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_74/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_89/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_90/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_92/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_104/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_104/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q0 SLICE_116/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 SLICE_22/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_56/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_64/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_64/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_68/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_73/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_75/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_76/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_88/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_90/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_93/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_99/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_104/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_109/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_110/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_114/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_123/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_123/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_125/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_125/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_128/B1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_46/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_50/C1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_58/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_60/C0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_61/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_62/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_64/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_65/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_68/A0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_70/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_74/D0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_84/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_89/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_90/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_95/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_97/A1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_104/B0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_108/B1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_4/Q1 SLICE_108/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 SLICE_21/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_47/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_68/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_73/B0 (0:0:0)(0:0:0))
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+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/B0 (0:0:0)(0:0:0))
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+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_29/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/B0 (0:0:0)(0:0:0))
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         (INTERCONNECT SLICE_27/F1 SLICE_27/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0))
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-        (INTERCONNECT SLICE_114/F0 SLICE_28/CE (0:0:0)(0:0:0))
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-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO2 SLICE_28/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/B0 (0:0:0)(0:0:0))
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+        (INTERCONNECT ram2e_ufm\/SLICE_44/Q1 SLICE_28/C1 (0:0:0)(0:0:0))
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         (INTERCONNECT SLICE_28/F1 SLICE_28/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_28/F0 SLICE_28/DI0 (0:0:0)(0:0:0))
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-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO4 SLICE_29/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_28/Q0 ram2e_ufm\/SLICE_146/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_28/Q1 ram2e_ufm\/SLICE_74/C1 (0:0:0)(0:0:0))
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         (INTERCONNECT SLICE_29/F1 SLICE_29/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0))
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-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO6 SLICE_30/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_29/Q1 ram2e_ufm\/SLICE_72/C1 (0:0:0)(0:0:0))
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+        (INTERCONNECT ram2e_ufm\/SLICE_46/Q0 SLICE_30/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_30/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_40/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_42/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_46/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_50/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/C1 
+          (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_62/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_65/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_82/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_83/B1 (0:0:0)(0:0:0))
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         (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT nWE_I/PADDI SLICE_31/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_30/Q0 ram2e_ufm\/SLICE_129/C1 (0:0:0)(0:0:0))
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+        (INTERCONNECT Ain\[3\]_I/PADDI SLICE_31/A1 (0:0:0)(0:0:0))
         (INTERCONNECT nWE_I/PADDI SLICE_31/D0 (0:0:0)(0:0:0))
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-        (INTERCONNECT nEN80_I/PADDI SLICE_117/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT nWE_I/PADDI SLICE_36/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/CKE_7\/SLICE_61/C0 (0:0:0)(0:0:0))
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+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_136/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_137/C1 (0:0:0)(0:0:0))
         (INTERCONNECT nC07X_I/PADDI SLICE_31/C0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0))
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-        (INTERCONNECT SLICE_102/F1 SLICE_33/D0 (0:0:0)(0:0:0))
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         (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0))
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+        (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_131/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_76/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_88/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_90/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_76/F0 ram2e_ufm\/SLICE_98/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_77/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_80/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_82/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_130/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_130/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_133/F1 ram2e_ufm\/SLICE_82/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_101/F0 ram2e_ufm\/SLICE_82/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_83/F0 ram2e_ufm\/SLICE_82/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_82/F1 ram2e_ufm\/SLICE_82/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_83/F1 ram2e_ufm\/SLICE_83/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_87/F0 ram2e_ufm\/SLICE_83/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_110/F0 ram2e_ufm\/SLICE_85/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_99/F0 ram2e_ufm\/SLICE_86/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_126/F0 ram2e_ufm\/SLICE_86/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_86/F1 ram2e_ufm\/SLICE_86/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_86/F1 ram2e_ufm\/SLICE_109/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_88/F1 ram2e_ufm\/SLICE_88/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_88/F1 ram2e_ufm\/SLICE_111/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_104/F0 ram2e_ufm\/SLICE_89/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_90/F1 ram2e_ufm\/SLICE_90/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_91/F1 ram2e_ufm\/SLICE_91/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_91/F1 ram2e_ufm\/SLICE_92/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_92/F1 ram2e_ufm\/SLICE_92/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_92/F1 ram2e_ufm\/SLICE_102/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_93/F1 ram2e_ufm\/SLICE_93/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_100/F1 ram2e_ufm\/SLICE_94/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_100/F1 ram2e_ufm\/SLICE_100/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT Ain\[4\]_I/PADDI ram2e_ufm\/SLICE_95/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT Ain\[6\]_I/PADDI ram2e_ufm\/SLICE_96/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_97/F1 ram2e_ufm\/SLICE_97/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_99/F1 ram2e_ufm\/SLICE_99/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_125/F1 ram2e_ufm\/SLICE_99/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_115/F0 ram2e_ufm\/SLICE_102/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_128/F0 ram2e_ufm\/SLICE_103/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_123/F1 ram2e_ufm\/SLICE_103/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_104/F1 ram2e_ufm\/SLICE_104/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_122/F1 ram2e_ufm\/SLICE_105/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_107/F1 ram2e_ufm\/SLICE_107/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_107/F1 ram2e_ufm\/SLICE_134/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_134/F1 ram2e_ufm\/SLICE_108/D1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_111/F0 ram2e_ufm\/SLICE_111/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_112/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_113/C1 (0:0:0)(0:0:0))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_115/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_135/D0 (0:0:0)(0:0:0))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_136/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_136/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_137/B1 (0:0:0)(0:0:0))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_137/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_114/F1 ram2e_ufm\/SLICE_114/C0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_116/F0 ram2e_ufm\/SLICE_116/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_117/F0 BA\[1\]_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_117/F0 BA\[0\]_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQMH_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQML_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_120/F0 DQML_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_120/F1 DQMH_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[7\]_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[6\]_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[5\]_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[4\]_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[3\]_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[2\]_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[1\]_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[0\]_MGIOL/CE (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_129/F1 BA\[1\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT Ain\[0\]_I/PADDI ram2e_ufm\/SLICE_132/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT Ain\[7\]_I/PADDI ram2e_ufm\/SLICE_132/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_136/F0 nDOE_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F0 LED_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0))
+        (INTERCONNECT PHI1_I/PADDI SLICE_139/A1 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI1_I/PADDI SLICE_139/A0 (0:0:0)(0:0:0))
+        (INTERCONNECT PHI1_I/PADDI PHI1_MGIOL/DI (0:0:0)(0:0:0))
+        (INTERCONNECT PHI1_MGIOL/IN SLICE_139/B0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_139/F1 nVOE_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_141/F0 RD\[3\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_141/F1 RD\[0\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_142/F0 RD\[4\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_143/F0 RD\[7\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_143/F1 RD\[1\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_144/F0 RD\[6\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_144/F1 RD\[2\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F0 RD\[5\]_I/PADDO (0:0:0)(0:0:0))
         (INTERCONNECT RD\[0\]_I/PADDI Vout\[0\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0))
+        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0))
         (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[9\]_MGIOL/IOLDO RA\[9\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[8\]_MGIOL/IOLDO RA\[8\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[7\]_MGIOL/IOLDO RA\[7\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[6\]_MGIOL/IOLDO RA\[6\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[5\]_MGIOL/IOLDO RA\[5\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[4\]_MGIOL/IOLDO RA\[4\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[2\]_MGIOL/IOLDO RA\[2\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT RA\[1\]_MGIOL/IOLDO RA\[1\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[11\]_MGIOL/IOLDO RAout\[11\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[10\]_MGIOL/IOLDO RAout\[10\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[9\]_MGIOL/IOLDO RAout\[9\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[8\]_MGIOL/IOLDO RAout\[8\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[7\]_MGIOL/IOLDO RAout\[7\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[6\]_MGIOL/IOLDO RAout\[6\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[5\]_MGIOL/IOLDO RAout\[5\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[4\]_MGIOL/IOLDO RAout\[4\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[3\]_MGIOL/IOLDO RAout\[3\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[2\]_MGIOL/IOLDO RAout\[2\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[1\]_MGIOL/IOLDO RAout\[1\]_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT RAout\[0\]_MGIOL/IOLDO RAout\[0\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nCAS_MGIOL/IOLDO nCAS_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nRAS_MGIOL/IOLDO nRAS_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT nCS_MGIOL/IOLDO nCS_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT CKE_MGIOL/IOLDO CKE_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT nRWEout_MGIOL/IOLDO nRWEout_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT nCASout_MGIOL/IOLDO nCASout_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT nRASout_MGIOL/IOLDO nRASout_I/IOLDO (0:0:0)(0:0:0))
+        (INTERCONNECT CKEout_MGIOL/IOLDO CKEout_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (0:0:0)(0:0:0))
@@ -4838,14 +5494,6 @@
         (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (0:0:0)(0:0:0))
         (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[7\]_MGIOL/IOLDO Dout\[7\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[6\]_MGIOL/IOLDO Dout\[6\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[5\]_MGIOL/IOLDO Dout\[5\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[4\]_MGIOL/IOLDO Dout\[4\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[3\]_MGIOL/IOLDO Dout\[3\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[2\]_MGIOL/IOLDO Dout\[2\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[1\]_MGIOL/IOLDO Dout\[1\]_I/IOLDO (0:0:0)(0:0:0))
-        (INTERCONNECT Dout\[0\]_MGIOL/IOLDO Dout\[0\]_I/IOLDO (0:0:0)(0:0:0))
       )
     )
   )
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo
index 6a9b257..cbca1b6 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo
@@ -1,9 +1,9 @@
 
 // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
 
-// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd 
-// Netlist created on Thu Sep 21 05:34:46 2023
-// Netlist written on Thu Sep 21 05:34:50 2023
+// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd 
+// Netlist created on Thu Dec 28 23:09:57 2023
+// Netlist written on Thu Dec 28 23:10:01 2023
 // Design is for device LCMXO2-640HC
 // Design is for package TQFP100
 // Design is for performance grade 4
@@ -11,7 +11,8 @@
 `timescale 1 ns / 1 ps
 
 module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, 
-               Vout, nVOE, CKE, nCS, nRAS, nCAS, nRWE, BA, RA, RD, DQML, DQMH );
+               Vout, nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout, BA, 
+               RAout, DQML, DQMH, RD );
   input  C14M, PHI1, nWE, nWE80, nEN80, nC07X;
   input  [7:0] Ain;
   input  [7:0] Din;
@@ -19,9 +20,9 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   output [7:0] Dout;
   output nDOE;
   output [7:0] Vout;
-  output nVOE, CKE, nCS, nRAS, nCAS, nRWE;
+  output nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout;
   output [1:0] BA;
-  output [11:0] RA;
+  output [11:0] RAout;
   output DQML, DQMH;
   inout  [7:0] RD;
   wire   \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , 
@@ -30,77 +31,141 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
          \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , 
          \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , 
          \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , 
-         \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , Ready, 
-         PHI1reg, PHI1_c, RWSel, CO0_1, \CmdTout_3[0] , N_576_i, S_1, \CS[0] , 
-         N_461, \S_RNII9DO1_0[1] , \CS[1] , N_511_i, N_504_i, 
-         un1_CS_0_sqmuxa_i, N_637, \CS[2] , N_510_i, \Din_c[3] , \Din_c[2] , 
-         \Din_c[0] , N_643, CmdBitbangMXO2_4_u_0_0_a2_0_1, CmdBitbangMXO2, 
-         CmdBitbangMXO2_4, \Din_c[7] , \Din_c[5] , N_629, CmdExecMXO2, 
-         CmdExecMXO2_4, N_466, N_478, \Din_c[4] , \Din_c[1] , N_476, 
-         CmdLEDGet_4_u_0_0_a2_0_2, CmdLEDGet, CmdLEDGet_4, N_626, N_605, 
-         CmdLEDSet, CmdLEDSet_4, CmdRWMaskSet, CmdRWMaskSet_4, N_401, 
-         CmdSetRWBankFFLED, CmdSetRWBankFFLED_4, N_474, 
-         CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0, CmdSetRWBankFFMXO2, 
-         CmdSetRWBankFFMXO2_4, \CmdTout[1] , \CmdTout[2] , N_556_i, N_555_i, 
-         \S[0] , \S[1] , \S[2] , \S[3] , N_6_i, DOEEN, \Ain_c[1] , 
-         \wb_dato[0] , LEDEN_RNO, \un1_LEDEN_0_sqmuxa_1_i_0[0] , LEDEN, 
-         N_558_i, \Ain_c[3] , \Ain_c[0] , N_552_i, N_127_i, \S_RNII9DO1_1[1] , 
-         \RA_c[0] , \RA_c[3] , \RWMask[1] , N_591, \RWMask[0] , \RWBank_5[1] , 
-         \RWBank_5[0] , LEDEN13, \RWBank[0] , \RWBank[1] , \RWMask[3] , 
-         \RWMask[2] , \RWBank_5[3] , \RWBank_5[2] , \RWBank[2] , \RWBank[3] , 
-         \RWMask[5] , \RWMask[4] , \RWBank_5[5] , \RWBank_5[4] , \RWBank[4] , 
-         \RWBank[5] , \RWMask[7] , \RWMask[6] , \Din_c[6] , \RWBank_5[7] , 
-         \RWBank_5[6] , \RWBank[6] , \RWBank[7] , \wb_dato[1] , N_291_i, 
-         N_292_i, N_88, \wb_dato[3] , \wb_dato[2] , N_289_i, N_290_i, 
-         \wb_dato[5] , \wb_dato[4] , N_287_i, N_288_i, \wb_dato[7] , 
-         \wb_dato[6] , N_285, N_286_i, nWE_c, nEN80_c, nC07X_c, RWSel_2, nCS61, 
-         nDOE_c, Ready_0_sqmuxa_0_a2_6_a2_4, N_489, Ready_0_sqmuxa, N_876_0, 
-         wb_reqc_1, N_575, N_572, \S_s_0_1[0] , N_133_i, \S_s_0[0] , N_129_i, 
-         N_131_i, wb_adr_7_5_214_0_1, N_388, \wb_adr_7_0_4[0] , N_642, N_376, 
-         \wb_adr_RNO[1] , \wb_adr_7[0] , \un1_wb_adr_0_sqmuxa_2_i[0] , 
-         \wb_adr[0] , \wb_adr[1] , N_41_i, N_43_i, \wb_adr[2] , \wb_adr[3] , 
-         N_295, N_294, \wb_adr[4] , \wb_adr[5] , N_39_i, N_296, \wb_adr[6] , 
-         \wb_adr[7] , wb_ack, N_300, N_395, wb_cyc_stb_RNO, N_104, wb_cyc_stb, 
-         \wb_dati_7_0_0[1] , N_627, N_621, N_336, \wb_dati_7_0_a2_1[0] , N_484, 
-         \wb_dati_7[1] , \wb_dati_7[0] , \wb_dati[0] , \wb_dati[1] , 
-         \wb_dati_7_0_2[3] , \wb_dati_7_0_0[3] , \wb_dati_7_0_o2_0[2] , N_345, 
-         \wb_dati_7[3] , \wb_dati_7[2] , \wb_dati[2] , \wb_dati[3] , 
-         \wb_dati_7_0_0[4] , N_349, N_346, \wb_dati_7[5] , \wb_dati_7[4] , 
-         \wb_dati[4] , \wb_dati[5] , \wb_dati_7_0_0[7] , \wb_dati_7_0_RNO[7] , 
-         N_424, N_422, \wb_dati_7_0_1[6] , \wb_dati_7[7] , \wb_dati_7[6] , 
-         \wb_dati[6] , \wb_dati[7] , N_397, wb_reqc_i, wb_adr_0_sqmuxa_i, 
-         wb_req, wb_rst8, \S_RNII9DO1[1] , wb_rst, N_586, wb_we_7_iv_0_0_0_1, 
-         N_584, N_475, wb_we_RNO, \un1_wb_cyc_stb_0_sqmuxa_1_i[0] , wb_we, 
-         N_255, N_358_i, N_635, N_254, Vout3, nCAS_s_i_tz_0, 
-         un1_CS_0_sqmuxa_0_0_a2_1_4, N_327, un1_CS_0_sqmuxa_0_0_0, 
-         \wb_dati_7_0_a2_0_1[7] , N_579, CKE_6_iv_i_a2_0, CKE_6_iv_i_0_1, 
-         CKE_6_iv_i_0, N_449, N_365, N_364, \un1_wb_adr_0_sqmuxa_2_1[0] , 
-         N_623, N_616, N_279, N_633, N_264, N_570, N_452, 
-         \wb_dati_7_0_a2_2_1[3] , N_644, N_455, DQML_s_i_a2_0, N_28_i, 
-         wb_adr_7_5_214_a2_2_0, N_577, N_569, N_634, \wb_dati_7_0_a2_2_0[1] , 
-         N_265_i, \un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] , \wb_dati_7_0_a2_0[6] , 
-         \wb_dati_7_0_a2_4_0[7] , N_393, nCAS_0_sqmuxa, N_639, \RA_42[10] , 
-         N_640, un1_nCS61_1_i, Ready_0_sqmuxa_0_a2_6_a2_2, N_562, N_377, N_628, 
-         un1_CS_0_sqmuxa_0_0_a2_3_2, un1_CS_0_sqmuxa_0_0_3, 
-         un1_CS_0_sqmuxa_0_0_2, N_567, N_561_i, nCS_6_u_i_0, N_559_1, N_559_i, 
-         nRAS_2_iv_i, un1_CS_0_sqmuxa_0_0_a2_1, N_330, N_328, nCS_6_u_i_a2_1, 
-         N_429, N_351, \wb_adr_7_0_a2_5_0[0] , \wb_adr_7_0_1[0] , 
-         \wb_adr_7_0_0[0] , N_378, \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] , 
-         un1_CS_0_sqmuxa_0_0_a2_4_2, un1_CS_0_sqmuxa_0_0_a2_4_4, N_565, 
-         un1_CS_0_sqmuxa_0_0_a2_2_2, un1_CS_0_sqmuxa_0_0_a2_2_4, 
-         \wb_adr_7_0_a2_0[0] , un1_CS_0_sqmuxa_0_0_a2_1_2, 
-         un1_CS_0_sqmuxa_0_0_a2_3_0, N_394, N_49_i, N_456, N_477, N_566_i, 
-         \BA_4[0] , \RA_42[11] , \BA_4[1] , N_59_i, \Ain_c[5] , \Ain_c[4] , 
-         N_551_i, \RA_42_3_0[5] , \Ain_c[6] , N_550_i, \Ain_c[2] , \Ain_c[7] , 
-         N_549_i, N_553_i, nWE80_c, nRWE_r_0, RDOE_i, LED_c, \RD_in[0] , 
-         DQMH_c, DQML_c, \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , 
-         \RD_in[3] , \RD_in[2] , \RD_in[1] , \RA_c[11] , \RA_c[10] , \RA_c[9] , 
-         \RA_c[8] , \RA_c[7] , \RA_c[6] , \RA_c[5] , \RA_c[4] , \RA_c[2] , 
-         \RA_c[1] , \BA_c[1] , \BA_c[0] , nRWE_c, nCAS_c, nRAS_c, nCS_c, CKE_c, 
+         \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_551, 
+         \S[1] , \S[0] , \ram2e_ufm/CKE_7 , CKE_7_RNIS77M1, CKE, 
+         \ram2e_ufm/wb_adr_0_sqmuxa_1_i , RWSel, CO0_0, \CmdTout_3[0] , 
+         N_185_i, GND, \RC[2] , CO0_1, \RC[1] , N_360_i, RC12, 
+         \ram2e_ufm/N_821 , \ram2e_ufm/SUM1_0_0 , \ram2e_ufm/SUM0_i_a3_4_0 , 
+         \ram2e_ufm/N_886 , \ram2e_ufm/N_215 , \ram2e_ufm/SUM0_i_4 , \CS[2] , 
+         \CS[1] , CmdExecMXO2_3_0_a3_0_RNI6S1P8, N_547_i, un1_CS_0_sqmuxa_i, 
+         \CS[0] , \ram2e_ufm/N_234 , CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514, 
+         \ram2e_ufm/N_800 , \Din_c[5] , \Din_c[3] , 
+         \ram2e_ufm/CmdLEDGet_3_0_a3_1 , \ram2e_ufm/N_847 , \Din_c[2] , 
+         \Din_c[1] , CmdLEDGet_3, N_187_i, CmdLEDGet, \Din_c[7] , \Din_c[4] , 
+         \ram2e_ufm/N_883 , CmdLEDSet_3, CmdLEDSet, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 , CmdRWMaskSet_3, CmdRWMaskSet, 
+         \ram2e_ufm/N_850 , \Din_c[0] , CmdSetRWBankFFLED_4, CmdSetRWBankFFLED, 
+         \CmdTout[2] , \CmdTout[1] , N_369_i, N_368_i, \RA[1] , 
+         \ram2e_ufm/N_186 , \S[3] , N_1080_0, \ram2e_ufm/N_660 , DOEEN, 
+         \ram2e_ufm/N_193 , \ram2e_ufm/N_659 , \ram2e_ufm/N_182 , \Ain_c[1] , 
+         \ram2e_ufm/RA_35_0_0_1[0] , \ram2e_ufm/N_801 , \ram2e_ufm/N_684 , 
+         N_223, \RA_35[0] , N_126, \RA[0] , \ram2e_ufm/RA_35_0_0_0[3] , 
+         \ram2e_ufm/N_680 , \ram2e_ufm/N_679 , \Ain_c[2] , \RA_35[3] , 
+         \RA_35[2] , \RA[2] , \RA[3] , \ram2e_ufm/RA_35_0_0_0[5] , 
+         \ram2e_ufm/N_621 , \Ain_c[5] , \ram2e_ufm/RA_35_0_0_0[4] , \RA_35[5] , 
+         \RA_35[4] , \RA[4] , \RA[5] , \ram2e_ufm/RA_35_0_0_0_0[7] , 
+         \ram2e_ufm/RA_35_0_0_0_0[6] , \RA_35[7] , \RA_35[6] , \RA[6] , 
+         \RA[7] , \ram2e_ufm/RA_35_0_0_0[9] , \RA[9] , \ram2e_ufm/N_242 , 
+         \RA[8] , \ram2e_ufm/N_699 , \ram2e_ufm/N_698 , \ram2e_ufm/N_221 , 
+         \RA_35[9] , un2_S_2_i_0_0_o3_RNIHFHN3, \RWBank[4] , \RA[11] , 
+         \ram2e_ufm/N_845 , \ram2e_ufm/RA_35_2_0_0[10] , \ram2e_ufm/N_628 , 
+         \ram2e_ufm/N_627 , \ram2e_ufm/N_624 , \RA_35[11] , \RA_35[10] , 
+         \RA[10] , \RC_3[2] , \RC_3[1] , \ram2e_ufm/RWMask[1] , 
+         \ram2e_ufm/N_188 , \ram2e_ufm/RWMask[0] , \RWBank_3[1] , 
+         \RWBank_3[0] , \RWBank[0] , \RWBank[1] , \ram2e_ufm/RWMask[3] , 
+         \ram2e_ufm/RWMask[2] , \RWBank_3[3] , \RWBank_3[2] , \RWBank[2] , 
+         \RWBank[3] , \ram2e_ufm/RWMask[5] , \ram2e_ufm/RWMask[4] , 
+         \RWBank_3[5] , \RWBank_3[4] , \RWBank[5] , \ram2e_ufm/RWMask[7] , 
+         \ram2e_ufm/RWMask[6] , \Din_c[6] , \RWBank_3[7] , \RWBank_3[6] , 
+         \RWBank[6] , \RWBank[7] , \Ain_c[3] , nWE_c, nC07X_c, RWSel_2, 
+         un9_VOEEN_0_a2_0_a3_0_a3, \ram2e_ufm/Ready3_0_a3_5 , 
+         \ram2e_ufm/Ready3_0_a3_4 , \ram2e_ufm/Ready3_0_a3_3 , 
+         \ram2e_ufm/N_885 , Ready, Ready3, N_1026_0, \ram2e_ufm/S_r_i_0_o2[1] , 
+         \ram2e_ufm/N_271 , \ram2e_ufm/N_194 , S_1, \ram2e_ufm/N_643 , N_362_i, 
+         \S_s_0_0[0] , \S[2] , N_372_i, N_361_i, N_1078_0, VOEEN, BA_0_sqmuxa, 
+         \ram2e_ufm/N_285_i , \ram2e_ufm/N_804 , \ram2e_ufm/N_872 , 
+         \ram2e_ufm/N_641 , \ram2e_ufm/N_640 , N_370_i, nCAS, 
+         \ram2e_ufm/nRAS_s_i_0_0 , \ram2e_ufm/N_617 , \ram2e_ufm/N_616 , 
+         \ram2e_ufm/N_615 , N_358_i, nRAS, \ram2e_ufm/N_226 , 
+         \ram2e_ufm/N_866 , \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] , N_359_i, nRWE, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 , 
+         \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 , \ram2e_ufm/CmdBitbangMXO2_3 , 
+         \ram2e_ufm/CmdBitbangMXO2 , \ram2e_ufm/N_851 , 
+         \ram2e_ufm/CmdExecMXO2_3 , \ram2e_ufm/CmdExecMXO2 , 
+         \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 , \ram2e_ufm/N_190 , 
+         \ram2e_ufm/CmdSetRWBankFFChip_3 , \ram2e_ufm/CmdSetRWBankFFChip , 
+         \ram2e_ufm/wb_dato[0] , \ram2e_ufm/N_295 , 
+         \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] , \ram2e_ufm/LEDEN , 
+         \ram2e_ufm/N_212 , \ram2e_ufm/wb_dato[1] , \ram2e_ufm/N_307_i , 
+         \ram2e_ufm/N_309_i , \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] , 
+         \ram2e_ufm/wb_dato[3] , \ram2e_ufm/wb_dato[2] , \ram2e_ufm/N_302_i , 
+         \ram2e_ufm/N_304_i , \ram2e_ufm/wb_dato[5] , \ram2e_ufm/wb_dato[4] , 
+         \ram2e_ufm/N_301_i , \ram2e_ufm/N_310_i , \ram2e_ufm/wb_dato[7] , 
+         \ram2e_ufm/wb_dato[6] , \ram2e_ufm/N_296 , \ram2e_ufm/N_300_i , 
+         \ram2e_ufm/wb_adr_7_5_41_0_1 , \ram2e_ufm/N_768 , 
+         \ram2e_ufm/wb_adr_7_i_i_5[0] , \ram2e_ufm/wb_adr_7_i_i_4[0] , 
+         \ram2e_ufm/N_793 , \ram2e_ufm/wb_adr_RNO[1] , 
+         \ram2e_ufm/wb_adr_7_i_i[0] , \ram2e_ufm/CmdBitbangMXO2_RNINSM62 , 
+         \ram2e_ufm/wb_adr[0] , \ram2e_ufm/wb_adr[1] , \ram2e_ufm/N_268_i , 
+         \ram2e_ufm/N_80_i , \ram2e_ufm/wb_adr[2] , \ram2e_ufm/wb_adr[3] , 
+         \ram2e_ufm/N_290 , \ram2e_ufm/N_294 , \ram2e_ufm/wb_adr[4] , 
+         \ram2e_ufm/wb_adr[5] , \ram2e_ufm/N_267_i , \ram2e_ufm/N_284 , 
+         \ram2e_ufm/wb_adr[6] , \ram2e_ufm/wb_adr[7] , \ram2e_ufm/wb_ack , 
+         \ram2e_ufm/N_336 , \ram2e_ufm/N_687 , \ram2e_ufm/wb_cyc_stb_RNO , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] , 
+         \ram2e_ufm/wb_cyc_stb , \ram2e_ufm/wb_dati_7_0_0_0[1] , 
+         \ram2e_ufm/N_849 , \ram2e_ufm/N_611 , 
+         \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] , \ram2e_ufm/N_856 , 
+         \ram2e_ufm/wb_dati_7[1] , \ram2e_ufm/wb_dati_7[0] , 
+         \ram2e_ufm/wb_dati[0] , \ram2e_ufm/wb_dati[1] , 
+         \ram2e_ufm/wb_dati_7_0_0_0_0[3] , \ram2e_ufm/N_783 , 
+         \ram2e_ufm/wb_dati_7_0_0_o3_0[2] , \ram2e_ufm/N_760 , 
+         \ram2e_ufm/wb_dati_7[3] , \ram2e_ufm/wb_dati_7[2] , 
+         \ram2e_ufm/wb_dati[2] , \ram2e_ufm/wb_dati[3] , 
+         \ram2e_ufm/wb_dati_7_0_0_0[4] , \ram2e_ufm/N_763 , \ram2e_ufm/N_757 , 
+         \ram2e_ufm/wb_dati_7[5] , \ram2e_ufm/wb_dati_7[4] , 
+         \ram2e_ufm/wb_dati[4] , \ram2e_ufm/wb_dati[5] , 
+         \ram2e_ufm/wb_dati_7_0_0_0_0[7] , \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] , 
+         \ram2e_ufm/N_604 , \ram2e_ufm/N_602 , \ram2e_ufm/wb_dati_7_0_0_0[6] , 
+         \ram2e_ufm/wb_dati_7[7] , \ram2e_ufm/wb_dati_7[6] , 
+         \ram2e_ufm/wb_dati[6] , \ram2e_ufm/wb_dati[7] , \ram2e_ufm/wb_reqc_1 , 
+         \ram2e_ufm/wb_reqc_i , \ram2e_ufm/wb_req , \ram2e_ufm/wb_rst8 , 
+         \ram2e_ufm/wb_rst16_i , \ram2e_ufm/wb_rst , 
+         \ram2e_ufm/wb_we_7_iv_0_0_3_0_0 , \ram2e_ufm/N_799 , 
+         \ram2e_ufm/wb_we_7_iv_0_0_3_0_1 , \ram2e_ufm/N_208 , 
+         \ram2e_ufm/wb_we_RNO , \ram2e_ufm/wb_we_RNO_0 , \ram2e_ufm/wb_we , 
+         \ram2e_ufm/N_338 , \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 , \ram2e_ufm/N_817 , 
+         \ram2e_ufm/CKE_7_sm0 , \ram2e_ufm/N_720_tz , \ram2e_ufm/SUM0_i_0 , 
+         \ram2e_ufm/N_350 , \ram2e_ufm/SUM0_i_3 , \ram2e_ufm/SUM0_i_1 , 
+         \ram2e_ufm/N_187 , \ram2e_ufm/N_755 , \ram2e_ufm/N_735 , 
+         \ram2e_ufm/N_345 , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] , 
+         \ram2e_ufm/N_777 , \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] , 
+         \ram2e_ufm/N_250 , \ram2e_ufm/N_256 , \ram2e_ufm/wb_adr_7_i_i_3_1[0] , 
+         \ram2e_ufm/wb_adr_7_i_i_3[0] , \ram2e_ufm/N_254 , \ram2e_ufm/N_807 , 
+         \ram2e_ufm/N_876 , \ram2e_ufm/N_784 , \ram2e_ufm/N_560 , \BA_4[0] , 
+         \ram2e_ufm/N_873 , \ram2e_ufm/N_781 , \ram2e_ufm/N_184 , 
+         \ram2e_ufm/N_625 , \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] , 
+         \ram2e_ufm/N_811 , \ram2e_ufm/N_206 , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] , \ram2e_ufm/N_185 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S , \ram2e_ufm/N_637 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 , \ram2e_ufm/N_592 , 
+         \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] , 
+         \ram2e_ufm/wb_adr_7_i_i_1[0] , \ram2e_ufm/N_753 , \ram2e_ufm/N_634 , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] , 
+         \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_1[6] , \ram2e_ufm/N_890 , 
+         \ram2e_ufm/N_220 , \ram2e_ufm/N_196 , \ram2e_ufm/N_243 , \Ain_c[4] , 
+         \Ain_c[6] , \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] , 
+         \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] , \ram2e_ufm/N_565 , 
+         \ram2e_ufm/CKE_7s2_0_0_0 , \ram2e_ufm/wb_adr_7_5_41_a3_3_0 , 
+         \ram2e_ufm/N_204 , \ram2e_ufm/N_595 , \ram2e_ufm/nRWE_s_i_0_63_1 , 
+         \ram2e_ufm/N_792 , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] , 
+         \ram2e_ufm/N_553 , nEN80_c, \ram2e_ufm/N_241_i , \ram2e_ufm/N_814 , 
+         N_225_i, N_201_i, N_507_i, N_508, Vout3, \BA_4[1] , \Ain_c[0] , 
+         \Ain_c[7] , nDOE_c, LED_c, RDOE_i, PHI1_c, PHI1r, nVOE_c, N_263_i, 
+         N_667, N_648, N_662, N_666, N_663, N_665, N_664, \RD_in[0] , 
+         \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , 
+         \RD_in[2] , \RD_in[1] , DQMH_c, DQML_c, \RAout_c[11] , \RAout_c[10] , 
+         \RAout_c[9] , \RAout_c[8] , \RAout_c[7] , \RAout_c[6] , \RAout_c[5] , 
+         \RAout_c[4] , \RAout_c[3] , \RAout_c[2] , \RAout_c[1] , \RAout_c[0] , 
+         \BA_c[1] , \BA_c[0] , nRWEout_c, nCASout_c, nRASout_c, CKEout_c, 
          \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] , 
-         \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , \Dout_c[7] , \Dout_c[6] , 
-         \Dout_c[5] , \Dout_c[4] , \Dout_c[3] , \Dout_c[2] , \Dout_c[1] , 
-         \Dout_c[0] , VCCI;
+         \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , VCCI;
 
   SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), 
     .Q1(\FS[0] ), .FCO(\FS_cry[0] ));
@@ -127,426 +192,679 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), 
     .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), 
     .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
-  SLICE_9 SLICE_9( .C1(Ready), .B1(PHI1reg), .A1(PHI1_c), .B0(RWSel), 
-    .A0(CO0_1), .DI0(\CmdTout_3[0] ), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(\CmdTout_3[0] ), .Q0(CO0_1), .F1(S_1));
-  SLICE_10 SLICE_10( .D1(\CS[0] ), .C1(N_461), .B1(\S_RNII9DO1_0[1] ), 
-    .A1(\CS[1] ), .C0(\S_RNII9DO1_0[1] ), .B0(N_461), .A0(\CS[0] ), 
-    .DI1(N_511_i), .DI0(N_504_i), .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), 
-    .F0(N_504_i), .Q0(\CS[0] ), .F1(N_511_i), .Q1(\CS[1] ));
-  SLICE_11 SLICE_11( .C1(\S_RNII9DO1_0[1] ), .B1(N_461), .A1(\CS[0] ), 
-    .C0(N_637), .B0(\CS[2] ), .A0(\CS[1] ), .DI0(N_510_i), 
-    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_510_i), .Q0(\CS[2] ), 
-    .F1(N_637));
-  SLICE_12 SLICE_12( .C1(\Din_c[3] ), .B1(\Din_c[2] ), .A1(\Din_c[0] ), 
-    .D0(RWSel), .C0(N_643), .B0(CmdBitbangMXO2_4_u_0_0_a2_0_1), 
-    .A0(CmdBitbangMXO2), .DI0(CmdBitbangMXO2_4), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(CmdBitbangMXO2_4), .Q0(CmdBitbangMXO2), 
-    .F1(CmdBitbangMXO2_4_u_0_0_a2_0_1));
-  SLICE_13 SLICE_13( .C1(RWSel), .B1(\Din_c[7] ), .A1(\Din_c[5] ), .D0(RWSel), 
-    .C0(N_643), .B0(N_629), .A0(CmdExecMXO2), .DI0(CmdExecMXO2_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdExecMXO2_4), .Q0(CmdExecMXO2), 
-    .F1(N_466));
-  SLICE_14 SLICE_14( .D1(N_478), .C1(\Din_c[4] ), .B1(\Din_c[1] ), 
-    .A1(\Din_c[0] ), .D0(RWSel), .C0(N_476), .B0(CmdLEDGet_4_u_0_0_a2_0_2), 
-    .A0(CmdLEDGet), .DI0(CmdLEDGet_4), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(CmdLEDGet_4), .Q0(CmdLEDGet), .F1(CmdLEDGet_4_u_0_0_a2_0_2));
-  SLICE_15 SLICE_15( .D1(N_626), .C1(N_476), .B1(\Din_c[4] ), .A1(\Din_c[1] ), 
-    .C0(RWSel), .B0(N_605), .A0(CmdLEDSet), .DI0(CmdLEDSet_4), .CE(N_576_i), 
-    .CLK(C14M_c), .F0(CmdLEDSet_4), .Q0(CmdLEDSet), .F1(N_605));
-  SLICE_16 SLICE_16( .C1(\Din_c[1] ), .B1(\Din_c[4] ), .A1(N_476), .D0(RWSel), 
-    .C0(N_643), .B0(N_626), .A0(CmdRWMaskSet), .DI0(CmdRWMaskSet_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdRWMaskSet_4), .Q0(CmdRWMaskSet), 
-    .F1(N_643));
-  SLICE_17 SLICE_17( .D1(N_626), .C1(N_476), .B1(\Din_c[4] ), .A1(\Din_c[1] ), 
-    .C0(RWSel), .B0(N_401), .A0(CmdSetRWBankFFLED), .DI0(CmdSetRWBankFFLED_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdSetRWBankFFLED_4), 
-    .Q0(CmdSetRWBankFFLED), .F1(N_401));
-  SLICE_18 SLICE_18( .C1(N_474), .B1(\CS[2] ), .A1(\CS[1] ), .D0(RWSel), 
-    .C0(N_476), .B0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), 
-    .A0(CmdSetRWBankFFMXO2), .DI0(CmdSetRWBankFFMXO2_4), .CE(N_576_i), 
-    .CLK(C14M_c), .F0(CmdSetRWBankFFMXO2_4), .Q0(CmdSetRWBankFFMXO2), 
-    .F1(N_476));
-  SLICE_19 SLICE_19( .D1(RWSel), .C1(CO0_1), .B1(\CmdTout[1] ), 
-    .A1(\CmdTout[2] ), .C0(RWSel), .B0(\CmdTout[1] ), .A0(CO0_1), 
-    .DI1(N_556_i), .DI0(N_555_i), .CE(N_576_i), .CLK(C14M_c), .F0(N_555_i), 
-    .Q0(\CmdTout[1] ), .F1(N_556_i), .Q1(\CmdTout[2] ));
-  SLICE_20 SLICE_20( .D1(\S[0] ), .C1(\S[1] ), .B1(\S[2] ), .A1(\S[3] ), 
-    .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), .DI0(N_6_i), 
-    .CLK(C14M_c), .F0(N_6_i), .Q0(DOEEN), .F1(N_576_i));
-  SLICE_21 SLICE_21( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[1] ), 
-    .C0(\wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), .DI0(LEDEN_RNO), 
-    .CE(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .CLK(C14M_c), .F0(LEDEN_RNO), 
-    .Q0(LEDEN), .F1(N_558_i));
-  SLICE_22 SLICE_22( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[3] ), .C0(\S[3] ), 
-    .B0(\S[0] ), .A0(\Ain_c[0] ), .DI1(N_552_i), .DI0(N_127_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c), .F0(N_127_i), .Q0(\RA_c[0] ), 
-    .F1(N_552_i), .Q1(\RA_c[3] ));
-  SLICE_23 SLICE_23( .C1(\RWMask[1] ), .B1(N_591), .A1(\Din_c[1] ), 
-    .C0(\RWMask[0] ), .B0(N_591), .A0(\Din_c[0] ), .DI1(\RWBank_5[1] ), 
-    .DI0(\RWBank_5[0] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[0] ), 
-    .Q0(\RWBank[0] ), .F1(\RWBank_5[1] ), .Q1(\RWBank[1] ));
-  SLICE_24 SLICE_24( .C1(\RWMask[3] ), .B1(N_591), .A1(\Din_c[3] ), 
-    .C0(\RWMask[2] ), .B0(N_591), .A0(\Din_c[2] ), .DI1(\RWBank_5[3] ), 
-    .DI0(\RWBank_5[2] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[2] ), 
-    .Q0(\RWBank[2] ), .F1(\RWBank_5[3] ), .Q1(\RWBank[3] ));
-  SLICE_25 SLICE_25( .C1(\RWMask[5] ), .B1(N_591), .A1(\Din_c[5] ), 
-    .C0(\RWMask[4] ), .B0(N_591), .A0(\Din_c[4] ), .DI1(\RWBank_5[5] ), 
-    .DI0(\RWBank_5[4] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[4] ), 
-    .Q0(\RWBank[4] ), .F1(\RWBank_5[5] ), .Q1(\RWBank[5] ));
-  SLICE_26 SLICE_26( .C1(\RWMask[7] ), .B1(N_591), .A1(\Din_c[7] ), 
-    .C0(\RWMask[6] ), .B0(N_591), .A0(\Din_c[6] ), .DI1(\RWBank_5[7] ), 
-    .DI0(\RWBank_5[6] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[6] ), 
-    .Q0(\RWBank[6] ), .F1(\RWBank_5[7] ), .Q1(\RWBank[7] ));
-  SLICE_27 SLICE_27( .C1(\wb_dato[1] ), .B1(\S[3] ), .A1(\Din_c[1] ), 
-    .C0(\wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), .DI1(N_291_i), 
-    .DI0(N_292_i), .CE(N_88), .CLK(C14M_c), .F0(N_292_i), .Q0(\RWMask[0] ), 
-    .F1(N_291_i), .Q1(\RWMask[1] ));
-  SLICE_28 SLICE_28( .C1(\wb_dato[3] ), .B1(\S[3] ), .A1(\Din_c[3] ), 
-    .C0(\wb_dato[2] ), .B0(\S[3] ), .A0(\Din_c[2] ), .DI1(N_289_i), 
-    .DI0(N_290_i), .CE(N_88), .CLK(C14M_c), .F0(N_290_i), .Q0(\RWMask[2] ), 
-    .F1(N_289_i), .Q1(\RWMask[3] ));
-  SLICE_29 SLICE_29( .C1(\wb_dato[5] ), .B1(\S[3] ), .A1(\Din_c[5] ), 
-    .C0(\wb_dato[4] ), .B0(\S[3] ), .A0(\Din_c[4] ), .DI1(N_287_i), 
-    .DI0(N_288_i), .CE(N_88), .CLK(C14M_c), .F0(N_288_i), .Q0(\RWMask[4] ), 
-    .F1(N_287_i), .Q1(\RWMask[5] ));
-  SLICE_30 SLICE_30( .C1(\wb_dato[7] ), .B1(\S[3] ), .A1(\Din_c[7] ), 
-    .C0(\wb_dato[6] ), .B0(\S[3] ), .A0(\Din_c[6] ), .DI1(N_285), 
-    .DI0(N_286_i), .CE(N_88), .CLK(C14M_c), .F0(N_286_i), .Q0(\RWMask[6] ), 
-    .F1(N_285), .Q1(\RWMask[7] ));
-  SLICE_31 SLICE_31( .C1(nWE_c), .B1(nEN80_c), .A1(DOEEN), .D0(nWE_c), 
-    .C0(nC07X_c), .B0(\RA_c[3] ), .A0(\RA_c[0] ), .DI0(RWSel_2), .CE(nCS61), 
-    .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(nDOE_c));
-  SLICE_32 SLICE_32( .D1(Ready_0_sqmuxa_0_a2_6_a2_4), .C1(N_489), .B1(\FS[7] ), 
-    .A1(\FS[6] ), .B0(Ready), .A0(Ready_0_sqmuxa), .DI0(N_876_0), .CLK(C14M_c), 
-    .F0(N_876_0), .Q0(Ready), .F1(Ready_0_sqmuxa));
-  SLICE_33 SLICE_33( .D1(wb_reqc_1), .C1(N_575), .B1(N_572), .A1(S_1), 
-    .D0(\S_s_0_1[0] ), .C0(\S[1] ), .B0(\S[0] ), .A0(S_1), .DI1(N_133_i), 
-    .DI0(\S_s_0[0] ), .CLK(C14M_c), .F0(\S_s_0[0] ), .Q0(\S[0] ), .F1(N_133_i), 
-    .Q1(\S[1] ));
-  SLICE_34 SLICE_34( .D1(\S[3] ), .C1(\S[2] ), .B1(N_575), .A1(S_1), 
-    .D0(\S[3] ), .C0(\S[2] ), .B0(N_575), .A0(S_1), .DI1(N_129_i), 
-    .DI0(N_131_i), .CLK(C14M_c), .F0(N_131_i), .Q0(\S[2] ), .F1(N_129_i), 
-    .Q1(\S[3] ));
-  SLICE_35 SLICE_35( .D1(wb_adr_7_5_214_0_1), .C1(\S[2] ), .B1(N_388), 
-    .A1(\Din_c[1] ), .D0(\wb_adr_7_0_4[0] ), .C0(N_642), .B0(N_376), 
-    .A0(\FS[13] ), .DI1(\wb_adr_RNO[1] ), .DI0(\wb_adr_7[0] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_adr_7[0] ), 
-    .Q0(\wb_adr[0] ), .F1(\wb_adr_RNO[1] ), .Q1(\wb_adr[1] ));
-  SLICE_36 SLICE_36( .B1(\S[2] ), .A1(\Din_c[3] ), .B0(\S[2] ), 
-    .A0(\Din_c[2] ), .DI1(N_41_i), .DI0(N_43_i), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_43_i), 
-    .Q0(\wb_adr[2] ), .F1(N_41_i), .Q1(\wb_adr[3] ));
-  SLICE_37 SLICE_37( .C1(\S[2] ), .B1(\FS[14] ), .A1(\Din_c[5] ), .C0(\S[2] ), 
-    .B0(\FS[14] ), .A0(\Din_c[4] ), .DI1(N_295), .DI0(N_294), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_294), 
-    .Q0(\wb_adr[4] ), .F1(N_295), .Q1(\wb_adr[5] ));
-  SLICE_38 SLICE_38( .B1(\S[2] ), .A1(\Din_c[7] ), .C0(\S[2] ), .B0(\FS[14] ), 
-    .A0(\Din_c[6] ), .DI1(N_39_i), .DI0(N_296), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_296), 
-    .Q0(\wb_adr[6] ), .F1(N_39_i), .Q1(\wb_adr[7] ));
-  SLICE_39 SLICE_39( .D1(\FS[14] ), .C1(wb_ack), .B1(\FS[0] ), .A1(N_300), 
-    .C0(\S[3] ), .B0(N_395), .A0(CmdExecMXO2), .DI0(wb_cyc_stb_RNO), 
-    .CE(N_104), .CLK(C14M_c), .F0(wb_cyc_stb_RNO), .Q0(wb_cyc_stb), .F1(N_395));
-  SLICE_40 SLICE_40( .D1(\wb_dati_7_0_0[1] ), .C1(N_627), .B1(N_621), 
-    .A1(N_336), .D0(\wb_dati_7_0_a2_1[0] ), .C0(\wb_adr[0] ), .B0(\S[2] ), 
-    .A0(N_484), .DI1(\wb_dati_7[1] ), .DI0(\wb_dati_7[0] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[0] ), 
-    .Q0(\wb_dati[0] ), .F1(\wb_dati_7[1] ), .Q1(\wb_dati[1] ));
-  SLICE_41 SLICE_41( .C1(\wb_dati_7_0_2[3] ), .B1(\wb_dati_7_0_0[3] ), 
-    .A1(N_336), .D0(\wb_dati_7_0_o2_0[2] ), .C0(\wb_adr[2] ), .B0(\S[2] ), 
-    .A0(N_345), .DI1(\wb_dati_7[3] ), .DI0(\wb_dati_7[2] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[2] ), 
-    .Q0(\wb_dati[2] ), .F1(\wb_dati_7[3] ), .Q1(\wb_dati[3] ));
-  SLICE_42 SLICE_42( .D1(\wb_dati_7_0_o2_0[2] ), .C1(\wb_adr[5] ), .B1(\S[2] ), 
-    .A1(N_345), .D0(\wb_dati_7_0_0[4] ), .C0(N_349), .B0(N_346), .A0(N_345), 
-    .DI1(\wb_dati_7[5] ), .DI0(\wb_dati_7[4] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[4] ), 
-    .Q0(\wb_dati[4] ), .F1(\wb_dati_7[5] ), .Q1(\wb_dati[5] ));
-  SLICE_43 SLICE_43( .D1(\wb_dati_7_0_0[7] ), .C1(\wb_dati_7_0_RNO[7] ), 
-    .B1(N_424), .A1(N_422), .C0(\wb_dati_7_0_1[6] ), .B0(N_627), .A0(N_621), 
-    .DI1(\wb_dati_7[7] ), .DI0(\wb_dati_7[6] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[6] ), 
-    .Q0(\wb_dati[6] ), .F1(\wb_dati_7[7] ), .Q1(\wb_dati[7] ));
-  SLICE_44 SLICE_44( .C1(\FS[13] ), .B1(\FS[12] ), .A1(\FS[11] ), 
-    .D0(wb_reqc_1), .C0(\S[3] ), .B0(N_397), .A0(\FS[14] ), .DI0(wb_reqc_i), 
-    .CE(wb_adr_0_sqmuxa_i), .LSR(\S[2] ), .CLK(C14M_c), .F0(wb_reqc_i), 
-    .Q0(wb_req), .F1(N_397));
-  SLICE_45 SLICE_45( .B1(wb_ack), .A1(\FS[14] ), .B0(\FS[15] ), .A0(\FS[14] ), 
-    .DI0(wb_rst8), .LSR(\S_RNII9DO1[1] ), .CLK(C14M_c), .F0(wb_rst8), 
-    .Q0(wb_rst), .F1(N_586));
-  SLICE_46 SLICE_46( .D1(\FS[8] ), .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[12] ), 
-    .D0(wb_we_7_iv_0_0_0_1), .C0(N_584), .B0(N_475), .A0(\FS[13] ), 
-    .DI0(wb_we_RNO), .CE(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), .CLK(C14M_c), 
-    .F0(wb_we_RNO), .Q0(wb_we), .F1(N_584));
-  SLICE_47 SLICE_47( .D1(N_255), .C1(\S[0] ), .B1(\S_RNII9DO1[1] ), 
-    .A1(\RWBank[6] ), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), 
-    .F0(\S_RNII9DO1[1] ), .F1(N_358_i));
-  SLICE_48 SLICE_48( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[1] ), .A1(\S[0] ), 
-    .D0(N_635), .C0(\S[0] ), .B0(N_254), .A0(Vout3), .F0(nCAS_s_i_tz_0), 
-    .F1(Vout3));
-  SLICE_49 SLICE_49( .D1(un1_CS_0_sqmuxa_0_0_a2_1_4), .C1(RWSel), 
-    .B1(\Din_c[6] ), .A1(\CS[0] ), .D0(RWSel), .C0(N_327), .B0(\CS[2] ), 
-    .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_0), .F1(N_327));
-  SLICE_50 SLICE_50( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[9] ), .A1(\FS[8] ), 
-    .D0(\wb_dati_7_0_a2_0_1[7] ), .C0(N_621), .B0(N_579), .A0(\FS[9] ), 
-    .F0(\wb_dati_7_0_RNO[7] ), .F1(\wb_dati_7_0_a2_0_1[7] ));
-  SLICE_51 SLICE_51( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), 
-    .A1(CKE_6_iv_i_a2_0), .D0(\S[3] ), .C0(N_489), .B0(\FS[15] ), 
-    .A0(CKE_6_iv_i_0_1), .F0(CKE_6_iv_i_0), .F1(CKE_6_iv_i_0_1));
-  SLICE_52 SLICE_52( .D1(wb_req), .C1(N_449), .B1(N_300), .A1(\FS[0] ), 
-    .D0(N_586), .C0(N_449), .B0(N_365), .A0(N_364), .F0(N_104), .F1(N_365));
-  SLICE_53 SLICE_53( .D1(\S[3] ), .C1(\S[2] ), .B1(RWSel), .A1(\FS[15] ), 
-    .D0(wb_reqc_1), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .B0(\S[2] ), 
-    .A0(CmdExecMXO2), .F0(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), 
-    .F1(\un1_wb_adr_0_sqmuxa_2_1[0] ));
-  SLICE_54 SLICE_54( .D1(\Din_c[2] ), .C1(\Din_c[1] ), .B1(\Din_c[0] ), 
-    .A1(\CS[1] ), .D0(N_623), .C0(N_616), .B0(\Din_c[1] ), .A0(\CS[2] ), 
-    .F0(N_279), .F1(N_623));
-  SLICE_55 SLICE_55( .D1(\FS[4] ), .C1(N_633), .B1(\FS[5] ), .A1(N_264), 
-    .D0(\FS[1] ), .C0(\FS[2] ), .B0(\FS[3] ), .A0(\FS[5] ), .F0(N_633), 
-    .F1(N_570));
-  SLICE_56 SLICE_56( .C1(\FS[15] ), .B1(\S_RNII9DO1[1] ), .A1(\FS[14] ), 
-    .C0(\FS[13] ), .B0(N_452), .A0(\FS[12] ), .F0(N_621), .F1(N_452));
-  SLICE_57 SLICE_57( .D1(\S_RNII9DO1_0[1] ), .C1(RWSel), .B1(CmdExecMXO2), 
-    .A1(wb_ack), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[3] ), .A0(\S[2] ), 
-    .F0(\S_RNII9DO1_0[1] ), .F1(N_364));
-  SLICE_58 SLICE_58( .D1(\wb_dati_7_0_a2_2_1[3] ), .C1(N_644), .B1(N_455), 
-    .A1(\FS[12] ), .D0(\FS[10] ), .C0(\FS[11] ), .B0(\FS[8] ), .A0(\FS[9] ), 
-    .F0(\wb_dati_7_0_a2_2_1[3] ), .F1(\wb_dati_7_0_2[3] ));
-  SLICE_59 SLICE_59( .D1(nCS61), .C1(\RWBank[6] ), .B1(\S_RNII9DO1[1] ), 
-    .A1(DQML_s_i_a2_0), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), 
-    .F0(DQML_s_i_a2_0), .F1(N_28_i));
-  SLICE_60 SLICE_60( .D1(wb_adr_7_5_214_a2_2_0), .C1(N_577), .B1(N_569), 
-    .A1(N_475), .C0(\FS[10] ), .B0(\FS[12] ), .A0(\FS[13] ), 
-    .F0(wb_adr_7_5_214_a2_2_0), .F1(wb_adr_7_5_214_0_1));
-  SLICE_61 SLICE_61( .C1(N_634), .B1(\FS[13] ), .A1(\FS[12] ), .D0(\FS[10] ), 
-    .C0(\FS[11] ), .B0(\FS[8] ), .A0(\FS[9] ), .F0(N_634), 
-    .F1(\wb_dati_7_0_a2_2_0[1] ));
-  SLICE_62 SLICE_62( .D1(N_475), .C1(N_265_i), .B1(\FS[12] ), .A1(\FS[11] ), 
-    .C0(\FS[8] ), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_265_i), .F1(N_388));
-  SLICE_63 SLICE_63( .D1(N_264), .C1(N_254), .B1(\FS[7] ), .A1(\FS[6] ), 
-    .C0(\FS[1] ), .B0(\FS[2] ), .A0(\FS[3] ), .F0(N_264), .F1(N_300));
-  SLICE_64 SLICE_64( .C1(\FS[8] ), .B1(\FS[9] ), .A1(\FS[11] ), .D0(\FS[10] ), 
-    .C0(\FS[12] ), .B0(N_577), .A0(wb_ack), 
-    .F0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .F1(N_577));
-  SLICE_65 SLICE_65( .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[10] ), 
-    .C0(\FS[12] ), .B0(\FS[13] ), .A0(\wb_dati_7_0_a2_0[6] ), 
-    .F0(\wb_dati_7_0_a2_4_0[7] ), .F1(\wb_dati_7_0_a2_0[6] ));
-  SLICE_66 SLICE_66( .B1(\S[2] ), .A1(\FS[14] ), .D0(\FS[12] ), .C0(\FS[13] ), 
-    .B0(\FS[11] ), .A0(N_475), .F0(N_393), .F1(N_475));
-  SLICE_67 SLICE_67( .B1(\S[1] ), .A1(\S[0] ), .D0(wb_reqc_1), .C0(\S[3] ), 
-    .B0(\S[2] ), .A0(RWSel), .F0(LEDEN13), .F1(wb_reqc_1));
-  SLICE_68 SLICE_68( .D1(\wb_adr[3] ), .C1(\S[2] ), .B1(N_627), .A1(N_455), 
-    .D0(\FS[11] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[10] ), .F0(N_627), 
-    .F1(\wb_dati_7_0_0[3] ));
-  SLICE_69 SLICE_69( .D1(nCAS_0_sqmuxa), .C1(\RWBank[2] ), .B1(N_639), 
-    .A1(N_255), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), .F0(N_639), 
-    .F1(\RA_42[10] ));
-  SLICE_70 SLICE_70( .D1(N_644), .C1(N_627), .B1(N_455), .A1(\FS[12] ), 
-    .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), .F0(N_644), 
-    .F1(N_345));
-  SLICE_71 SLICE_71( .D1(nCS61), .C1(N_640), .B1(N_633), .A1(\FS[4] ), 
-    .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), .F0(nCS61), 
-    .F1(un1_nCS61_1_i));
-  SLICE_72 SLICE_72( .D1(Ready_0_sqmuxa_0_a2_6_a2_2), .C1(N_449), .B1(\FS[5] ), 
-    .A1(\FS[3] ), .D0(\S[2] ), .C0(\S[3] ), .B0(wb_reqc_1), .A0(\FS[15] ), 
-    .F0(N_449), .F1(Ready_0_sqmuxa_0_a2_6_a2_4));
-  SLICE_73 SLICE_73( .D1(N_562), .C1(N_455), .B1(\FS[12] ), .A1(\FS[11] ), 
-    .D0(\FS[14] ), .C0(\S_RNII9DO1[1] ), .B0(\FS[15] ), .A0(\FS[13] ), 
-    .F0(N_455), .F1(N_377));
-  SLICE_74 SLICE_74( .C1(N_484), .B1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[10] ), 
-    .C0(\FS[12] ), .B0(\FS[13] ), .A0(N_642), .F0(N_346), .F1(N_642));
-  SLICE_75 SLICE_75( .D1(N_489), .C1(\FS[7] ), .B1(\FS[6] ), .A1(\FS[0] ), 
-    .C0(\FS[15] ), .B0(\S_RNII9DO1[1] ), .A0(N_628), .F0(N_640), .F1(N_628));
-  SLICE_76 SLICE_76( .B1(\FS[5] ), .A1(\FS[4] ), .D0(N_449), .C0(N_628), 
-    .B0(N_254), .A0(N_264), .F0(nCAS_0_sqmuxa), .F1(N_254));
-  SLICE_77 SLICE_77( .C1(N_466), .B1(\Din_c[6] ), .A1(\CS[0] ), 
-    .D0(un1_CS_0_sqmuxa_0_0_a2_3_2), .C0(un1_CS_0_sqmuxa_0_0_3), 
-    .B0(un1_CS_0_sqmuxa_0_0_2), .A0(N_474), .F0(un1_CS_0_sqmuxa_i), .F1(N_474));
-  SLICE_78 SLICE_78( .B1(N_633), .A1(\FS[4] ), .D0(nCAS_s_i_tz_0), .C0(N_640), 
-    .B0(N_567), .A0(nCAS_0_sqmuxa), .F0(N_561_i), .F1(N_567));
-  SLICE_79 SLICE_79( .D1(nEN80_c), .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), 
-    .B0(nCS_6_u_i_0), .A0(N_559_1), .F0(N_559_i), .F1(nCS_6_u_i_0));
-  SLICE_80 SLICE_80( .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), .C0(\S[0] ), 
-    .B0(N_635), .A0(N_559_1), .F0(nRAS_2_iv_i), .F1(N_635));
-  SLICE_81 SLICE_81( .D1(\Din_c[6] ), .C1(\Din_c[4] ), .B1(\Din_c[3] ), 
-    .A1(\CS[0] ), .D0(un1_CS_0_sqmuxa_0_0_a2_1), .C0(un1_CS_0_sqmuxa_0_0_0), 
-    .B0(N_466), .A0(N_279), .F0(un1_CS_0_sqmuxa_0_0_2), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_1));
-  SLICE_82 SLICE_82( .D1(RWSel), .C1(\CmdTout[2] ), .B1(\CmdTout[1] ), 
-    .A1(CO0_1), .D0(\S_RNII9DO1_0[1] ), .C0(N_461), .B0(N_330), .A0(N_328), 
-    .F0(un1_CS_0_sqmuxa_0_0_3), .F1(N_461));
-  SLICE_83 SLICE_83( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[0] ), .A1(\FS[15] ), 
-    .D0(nCS_6_u_i_a2_1), .C0(N_628), .B0(N_570), .A0(N_429), .F0(N_559_1), 
-    .F1(nCS_6_u_i_a2_1));
-  SLICE_84 SLICE_84( .D1(\wb_dati_7_0_a2_0[6] ), .C1(N_455), .B1(\FS[12] ), 
-    .A1(\FS[10] ), .D0(\wb_adr[6] ), .C0(\S[2] ), .B0(N_351), .A0(N_346), 
-    .F0(\wb_dati_7_0_1[6] ), .F1(N_351));
-  SLICE_85 SLICE_85( .D1(\wb_adr_7_0_a2_5_0[0] ), .C1(N_579), .B1(N_452), 
-    .A1(\FS[8] ), .D0(\wb_adr_7_0_1[0] ), .C0(\wb_adr_7_0_0[0] ), .B0(N_378), 
-    .A0(N_377), .F0(\wb_adr_7_0_4[0] ), .F1(\wb_adr_7_0_1[0] ));
-  SLICE_86 SLICE_86( .D1(\FS[14] ), .C1(\S_RNII9DO1[1] ), .B1(\FS[15] ), 
-    .A1(\FS[8] ), .D0(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ), .C0(N_484), 
-    .B0(LEDEN13), .A0(CmdLEDSet), .F0(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), 
-    .F1(N_484));
-  SLICE_87 SLICE_87( .D1(un1_CS_0_sqmuxa_0_0_a2_4_2), .C1(RWSel), 
-    .B1(\Din_c[6] ), .A1(\CS[0] ), .C0(un1_CS_0_sqmuxa_0_0_a2_4_4), 
-    .B0(\CS[2] ), .A0(\CS[1] ), .F0(N_330), .F1(un1_CS_0_sqmuxa_0_0_a2_4_4));
-  SLICE_88 SLICE_88( .B1(\FS[13] ), .A1(\FS[12] ), .D0(N_634), .C0(N_569), 
-    .B0(N_452), .A0(N_336), .F0(\wb_dati_7_0_o2_0[2] ), .F1(N_569));
-  SLICE_89 SLICE_89( .B1(\FS[11] ), .A1(\FS[10] ), .D0(N_579), .C0(N_455), 
-    .B0(\FS[9] ), .A0(\FS[8] ), .F0(N_378), .F1(N_579));
-  SLICE_90 SLICE_90( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), 
-    .C0(N_565), .B0(N_484), .A0(\FS[12] ), .F0(N_336), .F1(N_565));
-  SLICE_91 SLICE_91( .D1(un1_CS_0_sqmuxa_0_0_a2_2_2), .C1(\Din_c[6] ), 
-    .B1(\CS[2] ), .A1(\CS[0] ), .C0(un1_CS_0_sqmuxa_0_0_a2_2_4), .B0(RWSel), 
-    .A0(\Din_c[7] ), .F0(N_328), .F1(un1_CS_0_sqmuxa_0_0_a2_2_4));
-  SLICE_92 SLICE_92( .D1(N_562), .C1(\FS[13] ), .B1(\FS[12] ), .A1(\FS[11] ), 
-    .D0(\wb_adr_7_0_a2_0[0] ), .C0(\S[2] ), .B0(N_452), .A0(\Din_c[0] ), 
-    .F0(\wb_adr_7_0_0[0] ), .F1(\wb_adr_7_0_a2_0[0] ));
-  SLICE_93 SLICE_93( .D1(N_616), .C1(\Din_c[5] ), .B1(\Din_c[4] ), 
-    .A1(\Din_c[1] ), .D0(un1_CS_0_sqmuxa_0_0_a2_1_2), .C0(\Din_c[7] ), 
-    .B0(\Din_c[3] ), .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_a2_1_4), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_1_2));
-  SLICE_94 SLICE_94( .D1(\Din_c[3] ), .C1(\Din_c[2] ), .B1(\Din_c[0] ), 
-    .A1(\Din_c[1] ), .D0(un1_CS_0_sqmuxa_0_0_a2_3_0), .C0(\Din_c[4] ), 
-    .B0(\CS[2] ), .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_a2_3_2), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_3_0));
-  SLICE_95 SLICE_95( .D1(N_577), .C1(N_475), .B1(\FS[12] ), .A1(\FS[10] ), 
-    .D0(\S[2] ), .C0(N_394), .B0(N_393), .A0(\Din_c[0] ), 
-    .F0(wb_we_7_iv_0_0_0_1), .F1(N_394));
-  SLICE_96 SLICE_96( .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), .D0(\S[0] ), 
-    .C0(\RWBank[7] ), .B0(\RWBank[0] ), .A0(N_255), .F0(N_49_i), .F1(N_255));
-  SLICE_97 SLICE_97( .B1(\FS[12] ), .A1(\FS[10] ), .D0(N_577), .C0(N_456), 
-    .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_489), .F1(N_456));
-  SLICE_98 SLICE_98( .C1(\Din_c[2] ), .B1(\Din_c[3] ), .A1(\Din_c[0] ), 
-    .D0(N_626), .C0(N_477), .B0(\Din_c[7] ), .A0(\Din_c[5] ), 
-    .F0(un1_CS_0_sqmuxa_0_0_a2_4_2), .F1(N_626));
-  SLICE_99 SLICE_99( .B1(\Din_c[3] ), .A1(\Din_c[2] ), .D0(N_478), .C0(N_477), 
-    .B0(\Din_c[5] ), .A0(\Din_c[0] ), .F0(un1_CS_0_sqmuxa_0_0_a2_2_2), 
-    .F1(N_478));
-  SLICE_100 SLICE_100( .C1(\Din_c[0] ), .B1(\Din_c[2] ), .A1(\Din_c[3] ), 
-    .C0(N_629), .B0(\Din_c[4] ), .A0(\Din_c[1] ), 
-    .F0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), .F1(N_629));
-  SLICE_101 SLICE_101( .D1(\S[2] ), .C1(\S[3] ), .B1(\S[1] ), .A1(\S[0] ), 
-    .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), .A0(\S[0] ), .F0(\S_RNII9DO1_1[1] ), 
-    .F1(N_566_i));
-  SLICE_102 SLICE_102( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[1] ), .A1(\S[0] ), 
-    .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\RWBank[4] ), .F0(\BA_4[0] ), 
-    .F1(\S_s_0_1[0] ));
-  SLICE_103 SLICE_103( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), 
-    .A1(\RWBank[3] ), .D0(\S[2] ), .C0(\S[3] ), .B0(wb_reqc_1), .A0(\FS[15] ), 
-    .F0(wb_adr_0_sqmuxa_i), .F1(\RA_42[11] ));
-  SLICE_104 SLICE_104( .D1(N_621), .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[8] ), 
-    .D0(N_621), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[9] ), .F0(N_376), 
-    .F1(N_349));
-  SLICE_105 SLICE_105( .D1(wb_ack), .C1(N_579), .B1(N_569), .A1(\FS[9] ), 
-    .D0(N_579), .C0(N_569), .B0(N_484), .A0(\FS[9] ), .F0(N_424), 
-    .F1(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ));
-  SLICE_106 SLICE_106( .B1(\S[1] ), .A1(\S[0] ), .C0(\S[0] ), .B0(\S[1] ), 
-    .A0(nEN80_c), .F0(CKE_6_iv_i_a2_0), .F1(N_575));
-  SLICE_107 SLICE_107( .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), 
-    .B0(\S[3] ), .A0(\RWBank[5] ), .F0(\BA_4[1] ), .F1(N_572));
-  SLICE_108 SLICE_108( .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), .D0(N_642), 
-    .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ), .F0(N_422), 
-    .F1(\wb_adr_7_0_a2_5_0[0] ));
-  SLICE_109 SLICE_109( .D1(\wb_dati_7_0_a2_4_0[7] ), .C1(\wb_adr[7] ), 
-    .B1(\S[2] ), .A1(N_452), .D0(\wb_dati_7_0_a2_2_0[1] ), .C0(\wb_adr[1] ), 
-    .B0(\S[2] ), .A0(N_452), .F0(\wb_dati_7_0_0[1] ), .F1(\wb_dati_7_0_0[7] ));
-  SLICE_110 SLICE_110( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), 
-    .A1(\RWBank[1] ), .D0(wb_reqc_1), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), 
-    .B0(\S[2] ), .A0(CmdBitbangMXO2), .F0(\un1_wb_adr_0_sqmuxa_2_i[0] ), 
-    .F1(N_59_i));
-  SLICE_111 SLICE_111( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[5] ), .C0(\S[3] ), 
-    .B0(\S[0] ), .A0(\Ain_c[4] ), .F0(N_551_i), .F1(\RA_42_3_0[5] ));
-  SLICE_112 SLICE_112( .D1(\S[3] ), .C1(\S[1] ), .B1(\S[0] ), .A1(N_254), 
-    .C0(\S[3] ), .B0(\S[0] ), .A0(\Ain_c[6] ), .F0(N_550_i), .F1(N_429));
-  SLICE_113 SLICE_113( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[2] ), .C0(\S[3] ), 
-    .B0(\S[0] ), .A0(\Ain_c[7] ), .F0(N_549_i), .F1(N_553_i));
-  SLICE_114 SLICE_114( .D1(\wb_adr[4] ), .C1(\S[2] ), .B1(N_634), .A1(N_455), 
-    .D0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .C0(N_455), .B0(LEDEN13), 
-    .A0(CmdRWMaskSet), .F0(N_88), .F1(\wb_dati_7_0_0[4] ));
-  SLICE_115 SLICE_115( .B1(nWE80_c), .A1(nEN80_c), .D0(nWE80_c), .C0(\S[0] ), 
-    .B0(nCAS_0_sqmuxa), .A0(un1_nCS61_1_i), .F0(nRWE_r_0), .F1(RDOE_i));
-  SLICE_116 SLICE_116( .B1(\FS[9] ), .A1(\FS[8] ), .D0(N_456), .C0(\FS[13] ), 
-    .B0(\FS[11] ), .A0(\FS[9] ), .F0(\wb_dati_7_0_a2_1[0] ), .F1(N_562));
-  SLICE_117 SLICE_117( .D1(LEDEN), .C1(CmdSetRWBankFFMXO2), 
-    .B1(CmdSetRWBankFFLED), .A1(CmdLEDGet), .B0(nEN80_c), .A0(LEDEN), 
-    .F0(LED_c), .F1(N_591));
-  SLICE_118 SLICE_118( .B1(\Din_c[4] ), .A1(\Din_c[1] ), .B0(\Din_c[2] ), 
-    .A0(\Din_c[0] ), .F0(N_616), .F1(N_477));
-  SLICE_119 SLICE_119( .D0(\FS[4] ), .C0(\FS[2] ), .B0(\FS[1] ), .A0(\FS[0] ), 
-    .F0(Ready_0_sqmuxa_0_a2_6_a2_2));
-  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(\Din_c[0] ), 
+  SLICE_9 SLICE_9( .D1(N_551), .C1(\S[1] ), .B1(\S[0] ), .A1(\FS[15] ), 
+    .D0(N_551), .C0(\S[1] ), .B0(\S[0] ), .A0(\ram2e_ufm/CKE_7 ), 
+    .DI0(CKE_7_RNIS77M1), .CLK(C14M_c), .F0(CKE_7_RNIS77M1), .Q0(CKE), 
+    .F1(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ));
+  SLICE_10 SLICE_10( .B0(RWSel), .A0(CO0_0), .DI0(\CmdTout_3[0] ), 
+    .CE(N_185_i), .CLK(C14M_c), .F0(\CmdTout_3[0] ), .Q0(CO0_0), .F1(GND));
+  SLICE_11 SLICE_11( .B1(\RC[2] ), .A1(CO0_1), .C0(\RC[2] ), .B0(\RC[1] ), 
+    .A0(CO0_1), .DI0(N_360_i), .CE(RC12), .CLK(C14M_c), .F0(N_360_i), 
+    .Q0(CO0_1), .F1(\ram2e_ufm/N_821 ));
+  SLICE_12 SLICE_12( .D1(\ram2e_ufm/SUM1_0_0 ), .C1(\ram2e_ufm/SUM0_i_a3_4_0 ), 
+    .B1(\ram2e_ufm/N_886 ), .A1(\ram2e_ufm/N_215 ), .D0(\ram2e_ufm/SUM0_i_4 ), 
+    .C0(\ram2e_ufm/N_215 ), .B0(\CS[2] ), .A0(\CS[1] ), 
+    .DI1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .DI0(N_547_i), 
+    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_547_i), .Q0(\CS[0] ), 
+    .F1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .Q1(\CS[1] ));
+  SLICE_13 SLICE_13( .D1(\ram2e_ufm/N_234 ), .C1(\ram2e_ufm/N_215 ), 
+    .B1(\CS[2] ), .A1(\CS[1] ), .D0(\ram2e_ufm/N_234 ), .C0(\ram2e_ufm/N_215 ), 
+    .B0(\CS[2] ), .A0(\CS[1] ), .DI0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), 
+    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), 
+    .F0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), .Q0(\CS[2] ), 
+    .F1(\ram2e_ufm/SUM1_0_0 ));
+  SLICE_14 SLICE_14( .C1(\ram2e_ufm/N_800 ), .B1(\Din_c[5] ), .A1(\Din_c[3] ), 
+    .D0(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ), .C0(\ram2e_ufm/N_847 ), 
+    .B0(\Din_c[2] ), .A0(\Din_c[1] ), .DI0(CmdLEDGet_3), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(CmdLEDGet_3), .Q0(CmdLEDGet), .F1(\ram2e_ufm/N_847 ));
+  SLICE_15 SLICE_15( .C1(\Din_c[7] ), .B1(\Din_c[1] ), .A1(\CS[2] ), 
+    .D0(\Din_c[4] ), .C0(\Din_c[7] ), .B0(\Din_c[1] ), .A0(\ram2e_ufm/N_883 ), 
+    .DI0(CmdLEDSet_3), .CE(N_187_i), .CLK(C14M_c), .F0(CmdLEDSet_3), 
+    .Q0(CmdLEDSet), .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ));
+  SLICE_16 SLICE_16( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[3] ), 
+    .A1(\Din_c[1] ), .D0(\Din_c[4] ), .C0(\Din_c[7] ), .B0(\Din_c[1] ), 
+    .A0(\ram2e_ufm/N_883 ), .DI0(CmdRWMaskSet_3), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(CmdRWMaskSet_3), .Q0(CmdRWMaskSet), .F1(\ram2e_ufm/N_850 ));
+  SLICE_17 SLICE_17( .C1(\ram2e_ufm/N_847 ), .B1(\Din_c[2] ), .A1(\Din_c[0] ), 
+    .D0(\ram2e_ufm/N_883 ), .C0(\Din_c[7] ), .B0(\Din_c[4] ), .A0(\Din_c[1] ), 
+    .DI0(CmdSetRWBankFFLED_4), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(CmdSetRWBankFFLED_4), .Q0(CmdSetRWBankFFLED), .F1(\ram2e_ufm/N_883 ));
+  SLICE_18 SLICE_18( .D1(RWSel), .C1(\CmdTout[2] ), .B1(\CmdTout[1] ), 
+    .A1(CO0_0), .C0(RWSel), .B0(\CmdTout[1] ), .A0(CO0_0), .DI1(N_369_i), 
+    .DI0(N_368_i), .CE(N_185_i), .CLK(C14M_c), .F0(N_368_i), .Q0(\CmdTout[1] ), 
+    .F1(N_369_i), .Q1(\CmdTout[2] ));
+  SLICE_19 SLICE_19( .B1(\CS[2] ), .A1(\CS[1] ), .B0(\RA[1] ), 
+    .A0(\ram2e_ufm/N_186 ), .M0(\S[3] ), .LSR(N_1080_0), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_660 ), .Q0(DOEEN), .F1(\ram2e_ufm/N_193 ));
+  SLICE_20 SLICE_20( .D1(\ram2e_ufm/N_660 ), .C1(\ram2e_ufm/N_659 ), 
+    .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[1] ), .D0(\ram2e_ufm/RA_35_0_0_1[0] ), 
+    .C0(\ram2e_ufm/N_801 ), .B0(\ram2e_ufm/N_684 ), .A0(\FS[7] ), .DI1(N_223), 
+    .DI0(\RA_35[0] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[0] ), .Q0(\RA[0] ), 
+    .F1(N_223), .Q1(\RA[1] ));
+  SLICE_21 SLICE_21( .C1(\ram2e_ufm/RA_35_0_0_0[3] ), .B1(\ram2e_ufm/N_801 ), 
+    .A1(\FS[10] ), .D0(\ram2e_ufm/N_680 ), .C0(\ram2e_ufm/N_679 ), 
+    .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[2] ), .DI1(\RA_35[3] ), 
+    .DI0(\RA_35[2] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[2] ), .Q0(\RA[2] ), 
+    .F1(\RA_35[3] ), .Q1(\RA[3] ));
+  SLICE_22 SLICE_22( .D1(\ram2e_ufm/RA_35_0_0_0[5] ), .C1(\ram2e_ufm/N_621 ), 
+    .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[5] ), .C0(\ram2e_ufm/RA_35_0_0_0[4] ), 
+    .B0(\ram2e_ufm/N_801 ), .A0(\FS[11] ), .DI1(\RA_35[5] ), .DI0(\RA_35[4] ), 
+    .CE(N_126), .CLK(C14M_c), .F0(\RA_35[4] ), .Q0(\RA[4] ), .F1(\RA_35[5] ), 
+    .Q1(\RA[5] ));
+  SLICE_23 SLICE_23( .C1(\ram2e_ufm/RA_35_0_0_0_0[7] ), .B1(\ram2e_ufm/N_801 ), 
+    .A1(\FS[14] ), .C0(\ram2e_ufm/RA_35_0_0_0_0[6] ), .B0(\ram2e_ufm/N_801 ), 
+    .A0(\FS[13] ), .DI1(\RA_35[7] ), .DI0(\RA_35[6] ), .CE(N_126), 
+    .CLK(C14M_c), .F0(\RA_35[6] ), .Q0(\RA[6] ), .F1(\RA_35[7] ), .Q1(\RA[7] ));
+  SLICE_24 SLICE_24( .C1(\ram2e_ufm/RA_35_0_0_0[9] ), .B1(\RA[9] ), 
+    .A1(\ram2e_ufm/N_242 ), .D0(\RA[8] ), .C0(\ram2e_ufm/N_699 ), 
+    .B0(\ram2e_ufm/N_698 ), .A0(\ram2e_ufm/N_221 ), .DI1(\RA_35[9] ), 
+    .DI0(un2_S_2_i_0_0_o3_RNIHFHN3), .CE(N_126), .CLK(C14M_c), 
+    .F0(un2_S_2_i_0_0_o3_RNIHFHN3), .Q0(\RA[8] ), .F1(\RA_35[9] ), 
+    .Q1(\RA[9] ));
+  SLICE_25 SLICE_25( .D1(\RWBank[4] ), .C1(\RA[11] ), .B1(\ram2e_ufm/N_845 ), 
+    .A1(\ram2e_ufm/N_242 ), .D0(\ram2e_ufm/RA_35_2_0_0[10] ), 
+    .C0(\ram2e_ufm/N_628 ), .B0(\ram2e_ufm/N_627 ), .A0(\ram2e_ufm/N_624 ), 
+    .DI1(\RA_35[11] ), .DI0(\RA_35[10] ), .CE(N_126), .CLK(C14M_c), 
+    .F0(\RA_35[10] ), .Q0(\RA[10] ), .F1(\RA_35[11] ), .Q1(\RA[11] ));
+  SLICE_26 SLICE_26( .C1(\RC[2] ), .B1(\RC[1] ), .A1(CO0_1), .C0(\RC[2] ), 
+    .B0(CO0_1), .A0(\RC[1] ), .DI1(\RC_3[2] ), .DI0(\RC_3[1] ), .CE(RC12), 
+    .CLK(C14M_c), .F0(\RC_3[1] ), .Q0(\RC[1] ), .F1(\RC_3[2] ), .Q1(\RC[2] ));
+  SLICE_27 SLICE_27( .C1(\ram2e_ufm/RWMask[1] ), .B1(\ram2e_ufm/N_188 ), 
+    .A1(\Din_c[1] ), .C0(\ram2e_ufm/RWMask[0] ), .B0(\ram2e_ufm/N_188 ), 
+    .A0(\Din_c[0] ), .DI1(\RWBank_3[1] ), .DI0(\RWBank_3[0] ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\RWBank_3[0] ), .Q0(\RWBank[0] ), .F1(\RWBank_3[1] ), 
+    .Q1(\RWBank[1] ));
+  SLICE_28 SLICE_28( .C1(\ram2e_ufm/RWMask[3] ), .B1(\ram2e_ufm/N_188 ), 
+    .A1(\Din_c[3] ), .C0(\ram2e_ufm/RWMask[2] ), .B0(\ram2e_ufm/N_188 ), 
+    .A0(\Din_c[2] ), .DI1(\RWBank_3[3] ), .DI0(\RWBank_3[2] ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\RWBank_3[2] ), .Q0(\RWBank[2] ), .F1(\RWBank_3[3] ), 
+    .Q1(\RWBank[3] ));
+  SLICE_29 SLICE_29( .C1(\ram2e_ufm/RWMask[5] ), .B1(\ram2e_ufm/N_188 ), 
+    .A1(\Din_c[5] ), .C0(\ram2e_ufm/RWMask[4] ), .B0(\ram2e_ufm/N_188 ), 
+    .A0(\Din_c[4] ), .DI1(\RWBank_3[5] ), .DI0(\RWBank_3[4] ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\RWBank_3[4] ), .Q0(\RWBank[4] ), .F1(\RWBank_3[5] ), 
+    .Q1(\RWBank[5] ));
+  SLICE_30 SLICE_30( .C1(\ram2e_ufm/RWMask[7] ), .B1(\ram2e_ufm/N_188 ), 
+    .A1(\Din_c[7] ), .C0(\ram2e_ufm/RWMask[6] ), .B0(\ram2e_ufm/N_188 ), 
+    .A0(\Din_c[6] ), .DI1(\RWBank_3[7] ), .DI0(\RWBank_3[6] ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\RWBank_3[6] ), .Q0(\RWBank[6] ), .F1(\RWBank_3[7] ), 
+    .Q1(\RWBank[7] ));
+  SLICE_31 SLICE_31( .D1(\RA[3] ), .C1(\ram2e_ufm/N_186 ), 
+    .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[3] ), .D0(nWE_c), .C0(nC07X_c), 
+    .B0(\RA[3] ), .A0(\RA[0] ), .DI0(RWSel_2), .CE(un9_VOEEN_0_a2_0_a3_0_a3), 
+    .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(\ram2e_ufm/RA_35_0_0_0[3] ));
+  SLICE_32 SLICE_32( .D1(\ram2e_ufm/Ready3_0_a3_5 ), 
+    .C1(\ram2e_ufm/Ready3_0_a3_4 ), .B1(\ram2e_ufm/Ready3_0_a3_3 ), 
+    .A1(\ram2e_ufm/N_885 ), .B0(Ready), .A0(Ready3), .DI0(N_1026_0), 
+    .CLK(C14M_c), .F0(N_1026_0), .Q0(Ready), .F1(Ready3));
+  SLICE_33 SLICE_33( .D1(\ram2e_ufm/S_r_i_0_o2[1] ), .C1(\ram2e_ufm/N_271 ), 
+    .B1(\ram2e_ufm/N_194 ), .A1(S_1), .D0(\S[1] ), .C0(\ram2e_ufm/N_643 ), 
+    .B0(\ram2e_ufm/N_271 ), .A0(S_1), .DI1(N_362_i), .DI0(\S_s_0_0[0] ), 
+    .CLK(C14M_c), .F0(\S_s_0_0[0] ), .Q0(\S[0] ), .F1(N_362_i), .Q1(\S[1] ));
+  SLICE_34 SLICE_34( .D1(\S[2] ), .C1(S_1), .B1(\ram2e_ufm/N_194 ), 
+    .A1(\S[3] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\ram2e_ufm/N_194 ), .A0(S_1), 
+    .DI1(N_372_i), .DI0(N_361_i), .CLK(C14M_c), .F0(N_361_i), .Q0(\S[2] ), 
+    .F1(N_372_i), .Q1(\S[3] ));
+  SLICE_35 SLICE_35( .D1(N_551), .C1(\S[1] ), .B1(\S[0] ), .A1(\FS[4] ), 
+    .B0(\S[3] ), .A0(\S[2] ), .DI0(N_551), .LSR(N_1078_0), .CLK(C14M_c), 
+    .F0(N_551), .Q0(VOEEN), .F1(BA_0_sqmuxa));
+  SLICE_36 SLICE_36( .D1(\ram2e_ufm/N_285_i ), .C1(\S[0] ), .B1(\S[1] ), 
+    .A1(\ram2e_ufm/N_804 ), .D0(nWE_c), .C0(\ram2e_ufm/N_872 ), 
+    .B0(\ram2e_ufm/N_641 ), .A0(\ram2e_ufm/N_640 ), .DI0(N_370_i), 
+    .CLK(C14M_c), .F0(N_370_i), .Q0(nCAS), .F1(\ram2e_ufm/N_872 ));
+  SLICE_37 SLICE_37( .D1(\S[0] ), .C1(\S[1] ), .B1(\ram2e_ufm/N_285_i ), 
+    .A1(\ram2e_ufm/N_804 ), .D0(\ram2e_ufm/nRAS_s_i_0_0 ), 
+    .C0(\ram2e_ufm/N_617 ), .B0(\ram2e_ufm/N_616 ), .A0(\ram2e_ufm/N_615 ), 
+    .DI0(N_358_i), .CLK(C14M_c), .F0(N_358_i), .Q0(nRAS), 
+    .F1(\ram2e_ufm/N_617 ));
+  SLICE_38 SLICE_38( .D1(\S[2] ), .C1(\ram2e_ufm/S_r_i_0_o2[1] ), 
+    .B1(\ram2e_ufm/N_226 ), .A1(\ram2e_ufm/N_285_i ), .D0(\ram2e_ufm/N_804 ), 
+    .C0(\ram2e_ufm/N_866 ), .B0(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ), 
+    .A0(\ram2e_ufm/N_615 ), .DI0(N_359_i), .CLK(C14M_c), .F0(N_359_i), 
+    .Q0(nRWE), .F1(\ram2e_ufm/N_615 ));
+  ram2e_ufm_SLICE_39 \ram2e_ufm/SLICE_39 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ), 
+    .B1(\Din_c[0] ), .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), 
+    .D0(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ), .C0(\ram2e_ufm/N_800 ), 
+    .B0(\Din_c[2] ), .A0(\Din_c[1] ), .DI0(\ram2e_ufm/CmdBitbangMXO2_3 ), 
+    .CE(N_187_i), .CLK(C14M_c), .F0(\ram2e_ufm/CmdBitbangMXO2_3 ), 
+    .Q0(\ram2e_ufm/CmdBitbangMXO2 ), .F1(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ));
+  ram2e_ufm_SLICE_40 \ram2e_ufm/SLICE_40 ( .D1(\CS[1] ), .C1(\CS[2] ), 
+    .B1(\CS[0] ), .A1(\Din_c[6] ), .B0(\ram2e_ufm/N_851 ), 
+    .A0(\ram2e_ufm/N_800 ), .DI0(\ram2e_ufm/CmdExecMXO2_3 ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/CmdExecMXO2_3 ), .Q0(\ram2e_ufm/CmdExecMXO2 ), 
+    .F1(\ram2e_ufm/N_800 ));
+  ram2e_ufm_SLICE_41 \ram2e_ufm/SLICE_41 ( .D1(\Din_c[0] ), .C1(\Din_c[1] ), 
+    .B1(\Din_c[2] ), .A1(\Din_c[4] ), 
+    .D0(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ), .C0(\ram2e_ufm/N_800 ), 
+    .B0(\ram2e_ufm/N_190 ), .A0(\Din_c[7] ), 
+    .DI0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .Q0(\ram2e_ufm/CmdSetRWBankFFChip ), 
+    .F1(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ));
+  ram2e_ufm_SLICE_42 \ram2e_ufm/SLICE_42 ( .C1(\Din_c[6] ), .B1(\Din_c[2] ), 
+    .A1(\Din_c[0] ), .C0(\ram2e_ufm/wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), 
+    .DI0(\ram2e_ufm/N_295 ), .CE(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_295 ), .Q0(\ram2e_ufm/LEDEN ), 
+    .F1(\ram2e_ufm/N_212 ));
+  ram2e_ufm_SLICE_43 \ram2e_ufm/SLICE_43 ( .C1(\ram2e_ufm/wb_dato[1] ), 
+    .B1(\S[3] ), .A1(\Din_c[1] ), .C0(\ram2e_ufm/wb_dato[0] ), .B0(\S[3] ), 
+    .A0(\Din_c[0] ), .DI1(\ram2e_ufm/N_307_i ), .DI0(\ram2e_ufm/N_309_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_309_i ), .Q0(\ram2e_ufm/RWMask[0] ), 
+    .F1(\ram2e_ufm/N_307_i ), .Q1(\ram2e_ufm/RWMask[1] ));
+  ram2e_ufm_SLICE_44 \ram2e_ufm/SLICE_44 ( .C1(\ram2e_ufm/wb_dato[3] ), 
+    .B1(\S[3] ), .A1(\Din_c[3] ), .C0(\ram2e_ufm/wb_dato[2] ), .B0(\S[3] ), 
+    .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_302_i ), .DI0(\ram2e_ufm/N_304_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_304_i ), .Q0(\ram2e_ufm/RWMask[2] ), 
+    .F1(\ram2e_ufm/N_302_i ), .Q1(\ram2e_ufm/RWMask[3] ));
+  ram2e_ufm_SLICE_45 \ram2e_ufm/SLICE_45 ( .C1(\ram2e_ufm/wb_dato[5] ), 
+    .B1(\S[3] ), .A1(\Din_c[5] ), .C0(\ram2e_ufm/wb_dato[4] ), .B0(\S[3] ), 
+    .A0(\Din_c[4] ), .DI1(\ram2e_ufm/N_301_i ), .DI0(\ram2e_ufm/N_310_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_310_i ), .Q0(\ram2e_ufm/RWMask[4] ), 
+    .F1(\ram2e_ufm/N_301_i ), .Q1(\ram2e_ufm/RWMask[5] ));
+  ram2e_ufm_SLICE_46 \ram2e_ufm/SLICE_46 ( .C1(\ram2e_ufm/wb_dato[7] ), 
+    .B1(\S[3] ), .A1(\Din_c[7] ), .C0(\ram2e_ufm/wb_dato[6] ), .B0(\S[3] ), 
+    .A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_296 ), .DI0(\ram2e_ufm/N_300_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_300_i ), .Q0(\ram2e_ufm/RWMask[6] ), 
+    .F1(\ram2e_ufm/N_296 ), .Q1(\ram2e_ufm/RWMask[7] ));
+  ram2e_ufm_SLICE_47 \ram2e_ufm/SLICE_47 ( .D1(\ram2e_ufm/wb_adr_7_5_41_0_1 ), 
+    .C1(\S[2] ), .B1(\ram2e_ufm/N_768 ), .A1(\Din_c[1] ), 
+    .D0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), 
+    .B0(\ram2e_ufm/N_793 ), .A0(\FS[10] ), .DI1(\ram2e_ufm/wb_adr_RNO[1] ), 
+    .DI0(\ram2e_ufm/wb_adr_7_i_i[0] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i[0] ), .Q0(\ram2e_ufm/wb_adr[0] ), 
+    .F1(\ram2e_ufm/wb_adr_RNO[1] ), .Q1(\ram2e_ufm/wb_adr[1] ));
+  ram2e_ufm_SLICE_48 \ram2e_ufm/SLICE_48 ( .B1(\S[2] ), .A1(\Din_c[3] ), 
+    .B0(\S[2] ), .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_268_i ), 
+    .DI0(\ram2e_ufm/N_80_i ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_80_i ), .Q0(\ram2e_ufm/wb_adr[2] ), 
+    .F1(\ram2e_ufm/N_268_i ), .Q1(\ram2e_ufm/wb_adr[3] ));
+  ram2e_ufm_SLICE_49 \ram2e_ufm/SLICE_49 ( .C1(\S[2] ), .B1(\FS[14] ), 
+    .A1(\Din_c[5] ), .C0(\S[2] ), .B0(\FS[14] ), .A0(\Din_c[4] ), 
+    .DI1(\ram2e_ufm/N_290 ), .DI0(\ram2e_ufm/N_294 ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_294 ), .Q0(\ram2e_ufm/wb_adr[4] ), .F1(\ram2e_ufm/N_290 ), 
+    .Q1(\ram2e_ufm/wb_adr[5] ));
+  ram2e_ufm_SLICE_50 \ram2e_ufm/SLICE_50 ( .B1(\S[2] ), .A1(\Din_c[7] ), 
+    .C0(\S[2] ), .B0(\FS[14] ), .A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_267_i ), 
+    .DI0(\ram2e_ufm/N_284 ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_284 ), .Q0(\ram2e_ufm/wb_adr[6] ), 
+    .F1(\ram2e_ufm/N_267_i ), .Q1(\ram2e_ufm/wb_adr[7] ));
+  ram2e_ufm_SLICE_51 \ram2e_ufm/SLICE_51 ( .D1(\ram2e_ufm/wb_ack ), 
+    .C1(\ram2e_ufm/N_336 ), .B1(\FS[14] ), .A1(\FS[0] ), 
+    .C0(\ram2e_ufm/CmdExecMXO2 ), .B0(\S[3] ), .A0(\ram2e_ufm/N_687 ), 
+    .DI0(\ram2e_ufm/wb_cyc_stb_RNO ), 
+    .CE(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_cyc_stb_RNO ), .Q0(\ram2e_ufm/wb_cyc_stb ), 
+    .F1(\ram2e_ufm/N_687 ));
+  ram2e_ufm_SLICE_52 \ram2e_ufm/SLICE_52 ( .D1(\ram2e_ufm/wb_dati_7_0_0_0[1] ), 
+    .C1(\ram2e_ufm/N_849 ), .B1(\ram2e_ufm/N_793 ), .A1(\ram2e_ufm/N_611 ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ), .C0(\ram2e_ufm/wb_adr[0] ), 
+    .B0(\S[2] ), .A0(\ram2e_ufm/N_856 ), .DI1(\ram2e_ufm/wb_dati_7[1] ), 
+    .DI0(\ram2e_ufm/wb_dati_7[0] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[0] ), .Q0(\ram2e_ufm/wb_dati[0] ), 
+    .F1(\ram2e_ufm/wb_dati_7[1] ), .Q1(\ram2e_ufm/wb_dati[1] ));
+  ram2e_ufm_SLICE_53 \ram2e_ufm/SLICE_53 ( 
+    .D1(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .C1(\ram2e_ufm/N_849 ), 
+    .B1(\ram2e_ufm/N_783 ), .A1(\ram2e_ufm/N_611 ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C0(\ram2e_ufm/wb_adr[2] ), 
+    .B0(\S[2] ), .A0(\ram2e_ufm/N_760 ), .DI1(\ram2e_ufm/wb_dati_7[3] ), 
+    .DI0(\ram2e_ufm/wb_dati_7[2] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[2] ), .Q0(\ram2e_ufm/wb_dati[2] ), 
+    .F1(\ram2e_ufm/wb_dati_7[3] ), .Q1(\ram2e_ufm/wb_dati[3] ));
+  ram2e_ufm_SLICE_54 \ram2e_ufm/SLICE_54 ( 
+    .D1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C1(\ram2e_ufm/wb_adr[5] ), 
+    .B1(\S[2] ), .A1(\ram2e_ufm/N_760 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0[4] ), 
+    .C0(\ram2e_ufm/N_763 ), .B0(\ram2e_ufm/N_760 ), .A0(\ram2e_ufm/N_757 ), 
+    .DI1(\ram2e_ufm/wb_dati_7[5] ), .DI0(\ram2e_ufm/wb_dati_7[4] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_dati_7[4] ), .Q0(\ram2e_ufm/wb_dati[4] ), 
+    .F1(\ram2e_ufm/wb_dati_7[5] ), .Q1(\ram2e_ufm/wb_dati[5] ));
+  ram2e_ufm_SLICE_55 \ram2e_ufm/SLICE_55 ( 
+    .D1(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), 
+    .C1(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), .B1(\ram2e_ufm/N_604 ), 
+    .A1(\ram2e_ufm/N_602 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), 
+    .C0(\ram2e_ufm/N_849 ), .B0(\ram2e_ufm/N_793 ), .A0(\ram2e_ufm/N_757 ), 
+    .DI1(\ram2e_ufm/wb_dati_7[7] ), .DI0(\ram2e_ufm/wb_dati_7[6] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_dati_7[6] ), .Q0(\ram2e_ufm/wb_dati[6] ), 
+    .F1(\ram2e_ufm/wb_dati_7[7] ), .Q1(\ram2e_ufm/wb_dati[7] ));
+  ram2e_ufm_SLICE_56 \ram2e_ufm/SLICE_56 ( .D1(\S[3] ), .C1(\S[1] ), 
+    .B1(\S[0] ), .A1(\FS[14] ), .D0(\ram2e_ufm/wb_reqc_1 ), .C0(\FS[13] ), 
+    .B0(\FS[12] ), .A0(\FS[11] ), .DI0(\ram2e_ufm/wb_reqc_i ), 
+    .CE(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ), .LSR(\S[2] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_reqc_i ), .Q0(\ram2e_ufm/wb_req ), 
+    .F1(\ram2e_ufm/wb_reqc_1 ));
+  ram2e_ufm_SLICE_57 \ram2e_ufm/SLICE_57 ( .D1(\FS[15] ), .C1(\FS[14] ), 
+    .B1(\FS[4] ), .A1(\FS[2] ), .B0(\FS[15] ), .A0(\FS[14] ), 
+    .DI0(\ram2e_ufm/wb_rst8 ), .LSR(\ram2e_ufm/wb_rst16_i ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_rst8 ), .Q0(\ram2e_ufm/wb_rst ), 
+    .F1(\ram2e_ufm/Ready3_0_a3_4 ));
+  ram2e_ufm_SLICE_58 \ram2e_ufm/SLICE_58 ( 
+    .D1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), .C1(\ram2e_ufm/N_885 ), 
+    .B1(\ram2e_ufm/N_799 ), .A1(\FS[12] ), 
+    .D0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ), .C0(\ram2e_ufm/N_799 ), 
+    .B0(\ram2e_ufm/N_208 ), .A0(\FS[13] ), .DI0(\ram2e_ufm/wb_we_RNO ), 
+    .CE(\ram2e_ufm/wb_we_RNO_0 ), .CLK(C14M_c), .F0(\ram2e_ufm/wb_we_RNO ), 
+    .Q0(\ram2e_ufm/wb_we ), .F1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ));
+  ram2e_ufm_SUM0_i_m3_0_SLICE_59 \ram2e_ufm/SUM0_i_m3_0/SLICE_59 ( 
+    .C1(\CS[1] ), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .C0(\Din_c[7] ), 
+    .B0(\Din_c[5] ), .A0(\Din_c[3] ), .M0(\Din_c[1] ), 
+    .OFX0(\ram2e_ufm/N_338 ));
+  ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 
+    \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60 ( .D1(\CS[0] ), .C1(\Din_c[6] ), 
+    .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), .A1(\ram2e_ufm/N_193 ), 
+    .C0(CO0_0), .B0(\CmdTout[1] ), .A0(\CmdTout[2] ), .M0(RWSel), 
+    .OFX0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ));
+  ram2e_ufm_CKE_7_SLICE_61 \ram2e_ufm/CKE_7/SLICE_61 ( .C1(\RC[1] ), 
+    .B1(\ram2e_ufm/N_821 ), .A1(\ram2e_ufm/N_817 ), .C0(nWE_c), .B0(\S[1] ), 
+    .A0(\ram2e_ufm/N_804 ), .M0(\ram2e_ufm/CKE_7_sm0 ), 
+    .OFX0(\ram2e_ufm/CKE_7 ));
+  ram2e_ufm_SLICE_62 \ram2e_ufm/SLICE_62 ( .D1(\ram2e_ufm/N_851 ), 
+    .C1(\Din_c[6] ), .B1(\CS[2] ), .A1(\CS[1] ), 
+    .D0(\ram2e_ufm/SUM0_i_a3_4_0 ), .C0(\ram2e_ufm/N_234 ), .B0(\CS[2] ), 
+    .A0(\CS[1] ), .F0(\ram2e_ufm/N_720_tz ), .F1(\ram2e_ufm/SUM0_i_a3_4_0 ));
+  ram2e_ufm_SLICE_63 \ram2e_ufm/SLICE_63 ( .D1(\ram2e_ufm/SUM0_i_0 ), 
+    .C1(\ram2e_ufm/N_350 ), .B1(\CS[2] ), .A1(\CS[0] ), 
+    .D0(\ram2e_ufm/SUM0_i_3 ), .C0(\ram2e_ufm/SUM0_i_1 ), 
+    .B0(\ram2e_ufm/N_187 ), .A0(\CS[0] ), .F0(\ram2e_ufm/SUM0_i_4 ), 
+    .F1(\ram2e_ufm/SUM0_i_1 ));
+  ram2e_ufm_SLICE_64 \ram2e_ufm/SLICE_64 ( .C1(\ram2e_ufm/N_793 ), 
+    .B1(\FS[11] ), .A1(\FS[9] ), .D0(\ram2e_ufm/N_856 ), 
+    .C0(\ram2e_ufm/N_755 ), .B0(\FS[13] ), .A0(\FS[11] ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .F1(\ram2e_ufm/N_755 ));
+  ram2e_ufm_SLICE_65 \ram2e_ufm/SLICE_65 ( .D1(\ram2e_ufm/N_193 ), 
+    .C1(\Din_c[6] ), .B1(\Din_c[0] ), .A1(\CS[0] ), .D0(\ram2e_ufm/N_735 ), 
+    .C0(\ram2e_ufm/N_345 ), .B0(\CS[1] ), .A0(\CS[0] ), 
+    .F0(\ram2e_ufm/SUM0_i_0 ), .F1(\ram2e_ufm/N_735 ));
+  ram2e_ufm_SLICE_66 \ram2e_ufm/SLICE_66 ( .D1(\ram2e_ufm/wb_ack ), 
+    .C1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), 
+    .B1(\ram2e_ufm/N_777 ), .A1(\FS[14] ), .D0(\ram2e_ufm/wb_ack ), 
+    .C0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ), 
+    .B0(\ram2e_ufm/CmdExecMXO2 ), .A0(\ram2e_ufm/N_187 ), 
+    .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), 
+    .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ));
+  ram2e_ufm_SLICE_67 \ram2e_ufm/SLICE_67 ( .C1(\FS[3] ), .B1(\FS[2] ), 
+    .A1(\FS[1] ), .D0(\S[1] ), .C0(\ram2e_ufm/N_250 ), .B0(\FS[4] ), 
+    .A0(\FS[3] ), .F0(\ram2e_ufm/N_256 ), .F1(\ram2e_ufm/N_250 ));
+  ram2e_ufm_SLICE_68 \ram2e_ufm/SLICE_68 ( 
+    .D1(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .C1(\ram2e_ufm/N_783 ), .B1(\FS[9] ), 
+    .A1(\FS[8] ), .D0(\FS[12] ), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[8] ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .F1(\ram2e_ufm/wb_adr_7_i_i_3[0] ));
+  ram2e_ufm_SLICE_69 \ram2e_ufm/SLICE_69 ( .D1(\ram2e_ufm/N_254 ), 
+    .C1(\ram2e_ufm/wb_rst16_i ), .B1(\FS[15] ), .A1(\FS[0] ), .D0(\S[2] ), 
+    .C0(\S[3] ), .B0(\S[1] ), .A0(\S[0] ), .F0(\ram2e_ufm/wb_rst16_i ), 
+    .F1(\ram2e_ufm/N_641 ));
+  ram2e_ufm_SLICE_70 \ram2e_ufm/SLICE_70 ( .C1(\FS[14] ), 
+    .B1(\ram2e_ufm/N_777 ), .A1(\FS[8] ), .D0(\FS[12] ), .C0(\FS[13] ), 
+    .B0(\ram2e_ufm/N_807 ), .A0(\ram2e_ufm/N_876 ), .F0(\ram2e_ufm/N_604 ), 
+    .F1(\ram2e_ufm/N_807 ));
+  ram2e_ufm_SLICE_71 \ram2e_ufm/SLICE_71 ( .C1(\FS[4] ), 
+    .B1(\ram2e_ufm/N_784 ), .A1(\FS[3] ), .C0(\S[2] ), .B0(\S[3] ), 
+    .A0(\S[0] ), .F0(\ram2e_ufm/N_784 ), .F1(\ram2e_ufm/N_801 ));
+  ram2e_ufm_SLICE_72 \ram2e_ufm/SLICE_72 ( .D1(\S[0] ), .C1(\RWBank[5] ), 
+    .B1(\ram2e_ufm/N_560 ), .A1(\FS[4] ), .C0(\S[2] ), .B0(\S[3] ), 
+    .A0(\S[1] ), .F0(\ram2e_ufm/N_560 ), .F1(\BA_4[0] ));
+  ram2e_ufm_SLICE_73 \ram2e_ufm/SLICE_73 ( .D1(\ram2e_ufm/N_873 ), 
+    .C1(\ram2e_ufm/N_781 ), .B1(\ram2e_ufm/N_611 ), .A1(\ram2e_ufm/N_184 ), 
+    .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), 
+    .F0(\ram2e_ufm/N_873 ), .F1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ));
+  ram2e_ufm_SLICE_74 \ram2e_ufm/SLICE_74 ( .C1(\RWBank[3] ), 
+    .B1(\ram2e_ufm/N_845 ), .A1(\ram2e_ufm/N_625 ), .D0(\S[0] ), .C0(\S[1] ), 
+    .B0(\S[2] ), .A0(\S[3] ), .F0(\ram2e_ufm/N_845 ), 
+    .F1(\ram2e_ufm/RA_35_2_0_0[10] ));
+  ram2e_ufm_SLICE_75 \ram2e_ufm/SLICE_75 ( .C1(\FS[11] ), .B1(\FS[10] ), 
+    .A1(\FS[9] ), .D0(\FS[12] ), .C0(\FS[13] ), .B0(\ram2e_ufm/N_876 ), 
+    .A0(\ram2e_ufm/wb_ack ), 
+    .F0(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), 
+    .F1(\ram2e_ufm/N_876 ));
+  ram2e_ufm_SLICE_76 \ram2e_ufm/SLICE_76 ( .B1(\FS[11] ), .A1(\FS[10] ), 
+    .D0(\FS[12] ), .C0(\FS[13] ), .B0(\ram2e_ufm/N_811 ), 
+    .A0(\ram2e_ufm/N_206 ), .F0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), 
+    .F1(\ram2e_ufm/N_811 ));
+  ram2e_ufm_SLICE_77 \ram2e_ufm/SLICE_77 ( .C1(\ram2e_ufm/N_185 ), .B1(RWSel), 
+    .A1(\CS[0] ), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), 
+    .F0(\ram2e_ufm/N_185 ), .F1(\ram2e_ufm/N_215 ));
+  ram2e_ufm_SLICE_78 \ram2e_ufm/SLICE_78 ( .B1(\S[1] ), .A1(\S[0] ), 
+    .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\RWBank[1] ), 
+    .F0(\ram2e_ufm/N_699 ), .F1(\ram2e_ufm/S_r_i_0_o2[1] ));
+  ram2e_ufm_SLICE_79 \ram2e_ufm/SLICE_79 ( 
+    .D1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), 
+    .C1(\ram2e_ufm/N_807 ), .B1(\ram2e_ufm/N_187 ), .A1(CmdLEDSet), 
+    .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(RWSel), 
+    .F0(\ram2e_ufm/N_187 ), .F1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ));
+  ram2e_ufm_SLICE_80 \ram2e_ufm/SLICE_80 ( .D1(N_551), .C1(\S[1] ), 
+    .B1(\S[0] ), .A1(\FS[15] ), .D0(\ram2e_ufm/N_185 ), .C0(RWSel), 
+    .B0(\ram2e_ufm/N_777 ), .A0(\ram2e_ufm/CmdBitbangMXO2 ), 
+    .F0(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .F1(\ram2e_ufm/N_777 ));
+  ram2e_ufm_SLICE_81 \ram2e_ufm/SLICE_81 ( .D1(\FS[8] ), 
+    .C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), .A1(\FS[9] ), .D0(\FS[12] ), 
+    .C0(\FS[13] ), .B0(\ram2e_ufm/N_811 ), .A0(\ram2e_ufm/N_856 ), 
+    .F0(\ram2e_ufm/N_757 ), .F1(\ram2e_ufm/N_856 ));
+  ram2e_ufm_SLICE_82 \ram2e_ufm/SLICE_82 ( 
+    .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ), 
+    .C1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .B1(\Din_c[6] ), .A1(\CS[0] ), 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ), 
+    .C0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), 
+    .B0(\ram2e_ufm/N_637 ), .A0(\ram2e_ufm/N_185 ), .F0(un1_CS_0_sqmuxa_i), 
+    .F1(\ram2e_ufm/N_637 ));
+  ram2e_ufm_SLICE_83 \ram2e_ufm/SLICE_83 ( .C1(\ram2e_ufm/N_851 ), 
+    .B1(\Din_c[6] ), .A1(\CS[2] ), .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ), 
+    .C0(RWSel), .B0(\ram2e_ufm/N_592 ), .A0(\CS[0] ), 
+    .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ));
+  ram2e_ufm_SLICE_84 \ram2e_ufm/SLICE_84 ( .D1(\ram2e_ufm/N_850 ), 
+    .C1(\ram2e_ufm/N_212 ), .B1(\Din_c[4] ), .A1(\CS[2] ), 
+    .D0(\ram2e_ufm/N_886 ), .C0(\ram2e_ufm/N_720_tz ), .B0(\ram2e_ufm/N_187 ), 
+    .A0(\CS[1] ), .F0(\ram2e_ufm/SUM0_i_3 ), .F1(\ram2e_ufm/N_886 ));
+  ram2e_ufm_SLICE_85 \ram2e_ufm/SLICE_85 ( .D1(\FS[13] ), 
+    .C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), .A1(\FS[12] ), 
+    .D0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), 
+    .C0(\ram2e_ufm/N_793 ), .B0(\ram2e_ufm/N_187 ), .A0(CmdRWMaskSet), 
+    .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .F1(\ram2e_ufm/N_793 ));
+  ram2e_ufm_SLICE_86 \ram2e_ufm/SLICE_86 ( .B1(\S[2] ), .A1(\Din_c[0] ), 
+    .D0(\ram2e_ufm/wb_adr_7_i_i_3[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), 
+    .B0(\ram2e_ufm/N_753 ), .A0(\ram2e_ufm/N_634 ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), .F1(\ram2e_ufm/N_634 ));
+  ram2e_ufm_SLICE_87 \ram2e_ufm/SLICE_87 ( 
+    .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C1(\ram2e_ufm/N_212 ), 
+    .B1(\ram2e_ufm/N_190 ), .A1(\Din_c[1] ), .C0(\ram2e_ufm/N_886 ), 
+    .B0(\ram2e_ufm/N_234 ), .A0(\CS[1] ), .F0(\ram2e_ufm/N_592 ), 
+    .F1(\ram2e_ufm/N_234 ));
+  ram2e_ufm_SLICE_88 \ram2e_ufm/SLICE_88 ( .B1(\FS[11] ), .A1(\FS[10] ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\ram2e_ufm/N_876 ), 
+    .B0(\ram2e_ufm/N_793 ), .A0(\ram2e_ufm/N_206 ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ));
+  ram2e_ufm_SLICE_89 \ram2e_ufm/SLICE_89 ( .C1(\FS[14] ), 
+    .B1(\ram2e_ufm/N_777 ), .A1(\FS[13] ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .C0(\ram2e_ufm/wb_adr[3] ), 
+    .B0(\S[2] ), .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), 
+    .F1(\ram2e_ufm/N_783 ));
+  ram2e_ufm_SLICE_90 \ram2e_ufm/SLICE_90 ( .D1(\ram2e_ufm/N_206 ), 
+    .C1(\FS[12] ), .B1(\FS[11] ), .A1(\FS[10] ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ), .C0(\ram2e_ufm/wb_adr[6] ), 
+    .B0(\S[2] ), .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ));
+  ram2e_ufm_SLICE_91 \ram2e_ufm/SLICE_91 ( .D1(CO0_1), .C1(\RC[2] ), 
+    .B1(\ram2e_ufm/N_817 ), .A1(\RC[1] ), .D0(\ram2e_ufm/N_890 ), 
+    .C0(\ram2e_ufm/N_784 ), .B0(\ram2e_ufm/N_256 ), .A0(\ram2e_ufm/N_285_i ), 
+    .F0(\ram2e_ufm/nRAS_s_i_0_0 ), .F1(\ram2e_ufm/N_890 ));
+  ram2e_ufm_SLICE_92 \ram2e_ufm/SLICE_92 ( .D1(nWE_c), .C1(\S[1] ), 
+    .B1(\ram2e_ufm/N_804 ), .A1(N_551), .D0(\S[0] ), .C0(\ram2e_ufm/N_890 ), 
+    .B0(\ram2e_ufm/N_220 ), .A0(\ram2e_ufm/N_285_i ), .F0(\ram2e_ufm/N_640 ), 
+    .F1(\ram2e_ufm/N_220 ));
+  ram2e_ufm_SLICE_93 \ram2e_ufm/SLICE_93 ( .D1(\FS[11] ), .C1(\FS[10] ), 
+    .B1(\FS[9] ), .A1(\FS[8] ), .C0(\ram2e_ufm/N_783 ), .B0(\ram2e_ufm/N_196 ), 
+    .A0(\FS[12] ), .F0(\ram2e_ufm/N_760 ), .F1(\ram2e_ufm/N_196 ));
+  ram2e_ufm_SLICE_94 \ram2e_ufm/SLICE_94 ( .B1(\Din_c[7] ), .A1(\Din_c[4] ), 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C0(\ram2e_ufm/N_243 ), 
+    .B0(\Din_c[0] ), .A0(\CS[2] ), .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ));
+  ram2e_ufm_SLICE_95 \ram2e_ufm/SLICE_95 ( .D1(\S[3] ), .C1(\S[2] ), 
+    .B1(\S[1] ), .A1(\S[0] ), .D0(\RA[4] ), .C0(\ram2e_ufm/N_186 ), 
+    .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[4] ), .F0(\ram2e_ufm/RA_35_0_0_0[4] ), 
+    .F1(\ram2e_ufm/N_182 ));
+  ram2e_ufm_SLICE_96 \ram2e_ufm/SLICE_96 ( .D1(\S[3] ), .C1(\S[2] ), 
+    .B1(\S[1] ), .A1(\S[0] ), .D0(\RA[6] ), .C0(\ram2e_ufm/N_186 ), 
+    .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[6] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[6] ), 
+    .F1(\ram2e_ufm/N_186 ));
+  ram2e_ufm_SLICE_97 \ram2e_ufm/SLICE_97 ( .C1(\ram2e_ufm/N_873 ), 
+    .B1(\FS[13] ), .A1(\FS[12] ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ), 
+    .C0(\ram2e_ufm/wb_adr[1] ), .B0(\S[2] ), .A0(\ram2e_ufm/N_781 ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0[1] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ));
+  ram2e_ufm_SLICE_98 \ram2e_ufm/SLICE_98 ( .B1(\ram2e_ufm/N_777 ), 
+    .A1(\FS[14] ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), 
+    .C0(\ram2e_ufm/wb_adr[7] ), .B0(\S[2] ), .A0(\ram2e_ufm/N_781 ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), .F1(\ram2e_ufm/N_781 ));
+  ram2e_ufm_SLICE_99 \ram2e_ufm/SLICE_99 ( .C1(\FS[11] ), .B1(\FS[10] ), 
+    .A1(\FS[8] ), .D0(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ), 
+    .C0(\ram2e_ufm/N_781 ), .B0(\ram2e_ufm/N_565 ), .A0(\FS[12] ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), 
+    .F1(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ));
+  ram2e_ufm_SLICE_100 \ram2e_ufm/SLICE_100 ( .D1(\Din_c[5] ), .C1(\Din_c[3] ), 
+    .B1(\Din_c[2] ), .A1(\Din_c[1] ), .D0(\ram2e_ufm/N_243 ), .C0(\Din_c[7] ), 
+    .B0(\Din_c[4] ), .A0(\CS[2] ), .F0(\ram2e_ufm/N_345 ), 
+    .F1(\ram2e_ufm/N_243 ));
+  ram2e_ufm_SLICE_101 \ram2e_ufm/SLICE_101 ( .B1(\Din_c[5] ), .A1(\Din_c[3] ), 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ), .C0(\ram2e_ufm/N_850 ), 
+    .B0(\ram2e_ufm/N_190 ), .A0(\CS[1] ), 
+    .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .F1(\ram2e_ufm/N_190 ));
+  ram2e_ufm_SLICE_102 \ram2e_ufm/SLICE_102 ( .C1(\S[3] ), .B1(\S[2] ), 
+    .A1(\S[1] ), .C0(\ram2e_ufm/CKE_7s2_0_0_0 ), .B0(\ram2e_ufm/N_817 ), 
+    .A0(\ram2e_ufm/N_220 ), .F0(\ram2e_ufm/CKE_7_sm0 ), .F1(\ram2e_ufm/N_817 ));
+  ram2e_ufm_SLICE_103 \ram2e_ufm/SLICE_103 ( .B1(\FS[13] ), .A1(\FS[12] ), 
+    .D0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), .C0(\ram2e_ufm/N_799 ), 
+    .B0(\ram2e_ufm/N_204 ), .A0(\ram2e_ufm/N_184 ), 
+    .F0(\ram2e_ufm/wb_adr_7_5_41_0_1 ), .F1(\ram2e_ufm/N_184 ));
+  ram2e_ufm_SLICE_104 \ram2e_ufm/SLICE_104 ( .D1(\FS[11] ), .C1(\FS[10] ), 
+    .B1(\FS[9] ), .A1(\FS[8] ), .B0(\ram2e_ufm/N_595 ), .A0(\FS[12] ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .F1(\ram2e_ufm/N_595 ));
+  ram2e_ufm_SLICE_105 \ram2e_ufm/SLICE_105 ( .D1(\ram2e_ufm/nRWE_s_i_0_63_1 ), 
+    .C1(\S[3] ), .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\ram2e_ufm/N_285_i ), 
+    .C0(\ram2e_ufm/wb_rst16_i ), .B0(\FS[15] ), .A0(\FS[0] ), 
+    .F0(\ram2e_ufm/N_285_i ), .F1(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ));
+  ram2e_ufm_SLICE_106 \ram2e_ufm/SLICE_106 ( .B1(\S[1] ), .A1(\S[0] ), 
+    .D0(\S[2] ), .C0(\RA[10] ), .B0(\ram2e_ufm/S_r_i_0_o2[1] ), 
+    .A0(\ram2e_ufm/N_194 ), .F0(\ram2e_ufm/N_624 ), .F1(\ram2e_ufm/N_194 ));
+  ram2e_ufm_SLICE_107 \ram2e_ufm/SLICE_107 ( .D1(\S[0] ), .C1(\FS[4] ), 
+    .B1(\S[3] ), .A1(\S[2] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[8] ), 
+    .B0(\FS[5] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_659 ), .F1(\ram2e_ufm/N_792 ));
+  ram2e_ufm_SLICE_108 \ram2e_ufm/SLICE_108 ( 
+    .D1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ), .C1(\FS[7] ), 
+    .B1(\FS[5] ), .A1(\FS[4] ), .C0(\ram2e_ufm/wb_req ), 
+    .B0(\ram2e_ufm/N_336 ), .A0(\FS[0] ), 
+    .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), 
+    .F1(\ram2e_ufm/N_336 ));
+  ram2e_ufm_SLICE_109 \ram2e_ufm/SLICE_109 ( .B1(\S[2] ), .A1(\FS[14] ), 
+    .D0(\ram2e_ufm/N_799 ), .C0(\ram2e_ufm/N_634 ), .B0(\ram2e_ufm/N_184 ), 
+    .A0(\FS[11] ), .F0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), 
+    .F1(\ram2e_ufm/N_799 ));
+  ram2e_ufm_SLICE_110 \ram2e_ufm/SLICE_110 ( .D1(\FS[8] ), .C1(\FS[9] ), 
+    .B1(\FS[11] ), .A1(\FS[10] ), .B0(\ram2e_ufm/wb_ack ), 
+    .A0(\ram2e_ufm/N_885 ), 
+    .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), 
+    .F1(\ram2e_ufm/N_885 ));
+  ram2e_ufm_SLICE_111 \ram2e_ufm/SLICE_111 ( .C1(\ram2e_ufm/N_807 ), 
+    .B1(\ram2e_ufm/N_553 ), .A1(\FS[12] ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\ram2e_ufm/N_811 ), 
+    .B0(\FS[13] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_553 ), 
+    .F1(\ram2e_ufm/N_611 ));
+  ram2e_ufm_SLICE_112 \ram2e_ufm/SLICE_112 ( .C1(\S[1] ), .B1(\S[0] ), 
+    .A1(\ram2e_ufm/N_285_i ), .D0(nWE_c), .C0(nEN80_c), .B0(\S[2] ), 
+    .A0(\ram2e_ufm/N_866 ), .F0(\ram2e_ufm/N_616 ), .F1(\ram2e_ufm/N_866 ));
+  ram2e_ufm_SLICE_113 \ram2e_ufm/SLICE_113 ( .C1(nEN80_c), .B1(\S[3] ), 
+    .A1(\S[2] ), .D0(nWE_c), .C0(\S[1] ), .B0(\S[0] ), .A0(\ram2e_ufm/N_804 ), 
+    .F0(\ram2e_ufm/N_628 ), .F1(\ram2e_ufm/N_804 ));
+  ram2e_ufm_SLICE_114 \ram2e_ufm/SLICE_114 ( .C1(\FS[10] ), .B1(\FS[9] ), 
+    .A1(\FS[8] ), .D0(\ram2e_ufm/N_799 ), .C0(\ram2e_ufm/N_241_i ), 
+    .B0(\FS[12] ), .A0(\FS[11] ), .F0(\ram2e_ufm/N_768 ), 
+    .F1(\ram2e_ufm/N_241_i ));
+  ram2e_ufm_SLICE_115 \ram2e_ufm/SLICE_115 ( .B1(\S[2] ), .A1(\S[1] ), 
+    .D0(nEN80_c), .C0(\S[3] ), .B0(\S[0] ), .A0(\ram2e_ufm/N_221 ), 
+    .F0(\ram2e_ufm/CKE_7s2_0_0_0 ), .F1(\ram2e_ufm/N_221 ));
+  ram2e_ufm_SLICE_116 \ram2e_ufm/SLICE_116 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ), 
+    .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .A1(\ram2e_ufm/N_814 ), 
+    .C0(\Din_c[2] ), .B0(\Din_c[1] ), .A0(\Din_c[0] ), .F0(\ram2e_ufm/N_814 ), 
+    .F1(\ram2e_ufm/N_851 ));
+  ram2e_ufm_SLICE_117 \ram2e_ufm/SLICE_117 ( .D1(\S[1] ), .C1(\S[0] ), 
+    .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[0] ), 
+    .A0(\S[3] ), .F0(N_225_i), .F1(\ram2e_ufm/N_643 ));
+  ram2e_ufm_SLICE_118 \ram2e_ufm/SLICE_118 ( .D1(\S[1] ), .C1(\S[0] ), 
+    .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[0] ), 
+    .A0(\S[3] ), .F0(N_201_i), .F1(RC12));
+  ram2e_ufm_SLICE_119 \ram2e_ufm/SLICE_119 ( .D1(\S[2] ), .C1(\S[3] ), 
+    .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), 
+    .A0(\S[0] ), .F0(N_126), .F1(N_185_i));
+  ram2e_ufm_SLICE_120 \ram2e_ufm/SLICE_120 ( .D1(\S[3] ), .C1(\S[0] ), 
+    .B1(\RWBank[0] ), .A1(\FS[15] ), .D0(\S[3] ), .C0(\S[0] ), 
+    .B0(\RWBank[0] ), .A0(\FS[15] ), .F0(N_507_i), .F1(N_508));
+  ram2e_ufm_SLICE_121 \ram2e_ufm/SLICE_121 ( .D1(\S[3] ), .C1(\S[2] ), 
+    .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), 
+    .A0(\S[0] ), .F0(\ram2e_ufm/N_242 ), .F1(Vout3));
+  ram2e_ufm_SLICE_122 \ram2e_ufm/SLICE_122 ( .D1(\FS[4] ), .C1(\FS[3] ), 
+    .B1(\FS[2] ), .A1(\FS[1] ), .D0(\FS[4] ), .C0(\FS[3] ), .B0(\FS[2] ), 
+    .A0(\FS[1] ), .F0(\ram2e_ufm/N_254 ), .F1(\ram2e_ufm/nRWE_s_i_0_63_1 ));
+  ram2e_ufm_SLICE_123 \ram2e_ufm/SLICE_123 ( .C1(\FS[11] ), .B1(\FS[9] ), 
+    .A1(\FS[8] ), .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[10] ), 
+    .F0(\ram2e_ufm/N_849 ), .F1(\ram2e_ufm/N_204 ));
+  ram2e_ufm_SLICE_124 \ram2e_ufm/SLICE_124 ( .D1(\ram2e_ufm/N_784 ), 
+    .C1(\FS[12] ), .B1(\FS[4] ), .A1(\FS[3] ), .D0(\FS[4] ), 
+    .C0(\ram2e_ufm/N_784 ), .B0(\FS[1] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_684 ), 
+    .F1(\ram2e_ufm/RA_35_0_0_0[5] ));
+  ram2e_ufm_SLICE_125 \ram2e_ufm/SLICE_125 ( .D1(\FS[13] ), .C1(\FS[11] ), 
+    .B1(\FS[9] ), .A1(\FS[8] ), .D0(\ram2e_ufm/N_793 ), .C0(\FS[11] ), 
+    .B0(\FS[9] ), .A0(\FS[8] ), .F0(\ram2e_ufm/N_763 ), .F1(\ram2e_ufm/N_565 ));
+  ram2e_ufm_SLICE_126 \ram2e_ufm/SLICE_126 ( .D1(\FS[12] ), .C1(\FS[10] ), 
+    .B1(\FS[9] ), .A1(\FS[8] ), .D0(\ram2e_ufm/N_781 ), .C0(\FS[12] ), 
+    .B0(\FS[10] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_753 ), 
+    .F1(\ram2e_ufm/N_208 ));
+  ram2e_ufm_SLICE_127 \ram2e_ufm/SLICE_127 ( .D1(\S[3] ), .C1(\S[2] ), 
+    .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[0] ), 
+    .A0(\RWBank[7] ), .F0(\ram2e_ufm/N_698 ), .F1(un9_VOEEN_0_a2_0_a3_0_a3));
+  ram2e_ufm_SLICE_128 \ram2e_ufm/SLICE_128 ( .D1(\FS[13] ), .C1(\FS[12] ), 
+    .B1(\FS[11] ), .A1(\FS[10] ), .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ), 
+    .F0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ));
+  ram2e_ufm_SLICE_129 \ram2e_ufm/SLICE_129 ( .D1(\S[0] ), .C1(\RWBank[6] ), 
+    .B1(\ram2e_ufm/N_560 ), .A1(\FS[4] ), .D0(N_551), .C0(\S[0] ), 
+    .B0(\FS[1] ), .A0(\FS[4] ), .F0(\ram2e_ufm/N_627 ), .F1(\BA_4[1] ));
+  ram2e_ufm_SLICE_130 \ram2e_ufm/SLICE_130 ( .B1(\ram2e_ufm/N_185 ), 
+    .A1(RWSel), .D0(\ram2e_ufm/N_185 ), .C0(RWSel), .B0(\ram2e_ufm/N_777 ), 
+    .A0(\ram2e_ufm/CmdExecMXO2 ), .F0(\ram2e_ufm/wb_we_RNO_0 ), .F1(N_187_i));
+  ram2e_ufm_SLICE_131 \ram2e_ufm/SLICE_131 ( .D1(\FS[13] ), .C1(\FS[12] ), 
+    .B1(\FS[3] ), .A1(\FS[1] ), .D0(\ram2e_ufm/N_856 ), .C0(\ram2e_ufm/N_811 ), 
+    .B0(\FS[13] ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_602 ), 
+    .F1(\ram2e_ufm/Ready3_0_a3_5 ));
+  ram2e_ufm_SLICE_132 \ram2e_ufm/SLICE_132 ( .D1(\RA[0] ), 
+    .C1(\ram2e_ufm/N_186 ), .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[0] ), 
+    .D0(\RA[7] ), .C0(\ram2e_ufm/N_186 ), .B0(\ram2e_ufm/N_182 ), 
+    .A0(\Ain_c[7] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[7] ), 
+    .F1(\ram2e_ufm/RA_35_0_0_1[0] ));
+  ram2e_ufm_SLICE_133 \ram2e_ufm/SLICE_133 ( .D1(RWSel), .C1(\Din_c[4] ), 
+    .B1(\Din_c[2] ), .A1(\Din_c[0] ), .C0(\ram2e_ufm/N_338 ), .B0(\Din_c[4] ), 
+    .A0(\Din_c[2] ), .F0(\ram2e_ufm/N_350 ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ));
+  ram2e_ufm_SLICE_134 \ram2e_ufm/SLICE_134 ( .D1(\FS[6] ), .C1(\FS[3] ), 
+    .B1(\FS[2] ), .A1(\FS[1] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[9] ), 
+    .B0(\FS[6] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_679 ), 
+    .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ));
+  ram2e_ufm_SLICE_135 \ram2e_ufm/SLICE_135 ( .B1(\S[3] ), .A1(\S[2] ), 
+    .D0(nEN80_c), .C0(\S[3] ), .B0(\S[2] ), .A0(\ram2e_ufm/S_r_i_0_o2[1] ), 
+    .F0(\ram2e_ufm/N_625 ), .F1(\ram2e_ufm/N_271 ));
+  ram2e_ufm_SLICE_136 \ram2e_ufm/SLICE_136 ( .C1(nWE_c), .B1(nEN80_c), 
+    .A1(\S[3] ), .C0(nWE_c), .B0(nEN80_c), .A0(DOEEN), .F0(nDOE_c), 
+    .F1(\ram2e_ufm/N_226 ));
+  ram2e_ufm_SLICE_137 \ram2e_ufm/SLICE_137 ( .C1(nWE_c), .B1(nEN80_c), 
+    .A1(Ready), .C0(nEN80_c), .B0(Ready), .A0(\ram2e_ufm/LEDEN ), .F0(LED_c), 
+    .F1(RDOE_i));
+  SLICE_138 SLICE_138( .C1(\S[0] ), .B1(\S[1] ), .A1(\S[3] ), .C0(\S[0] ), 
+    .B0(\S[1] ), .A0(\S[2] ), .F0(N_1080_0), .F1(N_1078_0));
+  SLICE_139 SLICE_139( .B1(VOEEN), .A1(PHI1_c), .C0(Ready), .B0(PHI1r), 
+    .A0(PHI1_c), .F0(S_1), .F1(nVOE_c));
+  ram2e_ufm_SLICE_140 \ram2e_ufm/SLICE_140 ( .B1(\RA[2] ), 
+    .A1(\ram2e_ufm/N_186 ), .B0(\RA[5] ), .A0(\ram2e_ufm/N_186 ), 
+    .F0(\ram2e_ufm/N_621 ), .F1(\ram2e_ufm/N_680 ));
+  ram2e_ufm_SLICE_141 \ram2e_ufm/SLICE_141 ( .B1(Ready), .A1(\Din_c[0] ), 
+    .B0(Ready), .A0(\Din_c[3] ), .F0(N_263_i), .F1(N_667));
+  ram2e_ufm_SLICE_142 \ram2e_ufm/SLICE_142 ( .C1(\Din_c[4] ), .B1(\Din_c[7] ), 
+    .A1(\Din_c[0] ), .B0(Ready), .A0(\Din_c[4] ), .F0(N_648), 
+    .F1(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ));
+  ram2e_ufm_SLICE_143 \ram2e_ufm/SLICE_143 ( .B1(Ready), .A1(\Din_c[1] ), 
+    .B0(Ready), .A0(\Din_c[7] ), .F0(N_662), .F1(N_666));
+  ram2e_ufm_SLICE_144 \ram2e_ufm/SLICE_144 ( .B1(Ready), .A1(\Din_c[2] ), 
+    .B0(Ready), .A0(\Din_c[6] ), .F0(N_663), .F1(N_665));
+  ram2e_ufm_SLICE_145 \ram2e_ufm/SLICE_145 ( .D1(\ram2e_ufm/wb_adr[4] ), 
+    .C1(\S[2] ), .B1(\ram2e_ufm/N_873 ), .A1(\ram2e_ufm/N_783 ), .B0(\FS[9] ), 
+    .A0(\FS[8] ), .F0(\ram2e_ufm/N_206 ), .F1(\ram2e_ufm/wb_dati_7_0_0_0[4] ));
+  ram2e_ufm_SLICE_146 \ram2e_ufm/SLICE_146 ( .D1(\RWBank[2] ), 
+    .C1(\ram2e_ufm/N_845 ), .B1(\ram2e_ufm/N_784 ), .A1(\FS[4] ), .D0(\FS[7] ), 
+    .C0(\FS[6] ), .B0(\FS[5] ), .A0(\FS[0] ), .F0(\ram2e_ufm/Ready3_0_a3_3 ), 
+    .F1(\ram2e_ufm/RA_35_0_0_0[9] ));
+  ram2e_ufm_SLICE_147 \ram2e_ufm/SLICE_147 ( .D1(\ram2e_ufm/LEDEN ), 
+    .C1(CmdSetRWBankFFLED), .B1(\ram2e_ufm/CmdSetRWBankFFChip ), 
+    .A1(CmdLEDGet), .B0(Ready), .A0(\Din_c[5] ), .F0(N_664), 
+    .F1(\ram2e_ufm/N_188 ));
+  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(N_667), 
     .RD0(RD[0]));
   LED LED_I( .PADDO(LED_c), .LED(LED));
   C14M C14M_I( .PADDI(C14M_c), .C14M(C14M));
-  DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH));
-  DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_358_i), .CLK(C14M_c));
-  DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML));
-  DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_28_i), .CLK(C14M_c));
-  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(\Din_c[7] ), 
+  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(N_662), 
     .RD7(RD[7]));
-  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(\Din_c[6] ), 
+  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(N_663), 
     .RD6(RD[6]));
-  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(\Din_c[5] ), 
+  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(N_664), 
     .RD5(RD[5]));
-  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(\Din_c[4] ), 
+  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(N_648), 
     .RD4(RD[4]));
-  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(\Din_c[3] ), 
+  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(N_263_i), 
     .RD3(RD[3]));
-  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(\Din_c[2] ), 
+  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(N_665), 
     .RD2(RD[2]));
-  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(\Din_c[1] ), 
+  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(N_666), 
     .RD1(RD[1]));
-  RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11]));
-  RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(\RA_42[11] ), 
+  DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH));
+  DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_508), .CE(N_201_i), 
     .CLK(C14M_c));
-  RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10]));
-  RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(\RA_42[10] ), 
+  DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML));
+  DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_507_i), .CE(N_201_i), 
+    .CLK(C14M_c));
+  RAout_11_ \RAout[11]_I ( .IOLDO(\RAout_c[11] ), .RAout11(RAout[11]));
+  RAout_11__MGIOL \RAout[11]_MGIOL ( .IOLDO(\RAout_c[11] ), .OPOS(\RA[11] ), 
+    .CLK(C14M_c));
+  RAout_10_ \RAout[10]_I ( .IOLDO(\RAout_c[10] ), .RAout10(RAout[10]));
+  RAout_10__MGIOL \RAout[10]_MGIOL ( .IOLDO(\RAout_c[10] ), .OPOS(\RA[10] ), 
+    .CLK(C14M_c));
+  RAout_9_ \RAout[9]_I ( .IOLDO(\RAout_c[9] ), .RAout9(RAout[9]));
+  RAout_9__MGIOL \RAout[9]_MGIOL ( .IOLDO(\RAout_c[9] ), .OPOS(\RA[9] ), 
+    .CLK(C14M_c));
+  RAout_8_ \RAout[8]_I ( .IOLDO(\RAout_c[8] ), .RAout8(RAout[8]));
+  RAout_8__MGIOL \RAout[8]_MGIOL ( .IOLDO(\RAout_c[8] ), .OPOS(\RA[8] ), 
+    .CLK(C14M_c));
+  RAout_7_ \RAout[7]_I ( .IOLDO(\RAout_c[7] ), .RAout7(RAout[7]));
+  RAout_7__MGIOL \RAout[7]_MGIOL ( .IOLDO(\RAout_c[7] ), .OPOS(\RA[7] ), 
+    .CLK(C14M_c));
+  RAout_6_ \RAout[6]_I ( .IOLDO(\RAout_c[6] ), .RAout6(RAout[6]));
+  RAout_6__MGIOL \RAout[6]_MGIOL ( .IOLDO(\RAout_c[6] ), .OPOS(\RA[6] ), 
+    .CLK(C14M_c));
+  RAout_5_ \RAout[5]_I ( .IOLDO(\RAout_c[5] ), .RAout5(RAout[5]));
+  RAout_5__MGIOL \RAout[5]_MGIOL ( .IOLDO(\RAout_c[5] ), .OPOS(\RA[5] ), 
+    .CLK(C14M_c));
+  RAout_4_ \RAout[4]_I ( .IOLDO(\RAout_c[4] ), .RAout4(RAout[4]));
+  RAout_4__MGIOL \RAout[4]_MGIOL ( .IOLDO(\RAout_c[4] ), .OPOS(\RA[4] ), 
+    .CLK(C14M_c));
+  RAout_3_ \RAout[3]_I ( .IOLDO(\RAout_c[3] ), .RAout3(RAout[3]));
+  RAout_3__MGIOL \RAout[3]_MGIOL ( .IOLDO(\RAout_c[3] ), .OPOS(\RA[3] ), 
+    .CLK(C14M_c));
+  RAout_2_ \RAout[2]_I ( .IOLDO(\RAout_c[2] ), .RAout2(RAout[2]));
+  RAout_2__MGIOL \RAout[2]_MGIOL ( .IOLDO(\RAout_c[2] ), .OPOS(\RA[2] ), 
+    .CLK(C14M_c));
+  RAout_1_ \RAout[1]_I ( .IOLDO(\RAout_c[1] ), .RAout1(RAout[1]));
+  RAout_1__MGIOL \RAout[1]_MGIOL ( .IOLDO(\RAout_c[1] ), .OPOS(\RA[1] ), 
+    .CLK(C14M_c));
+  RAout_0_ \RAout[0]_I ( .IOLDO(\RAout_c[0] ), .RAout0(RAout[0]));
+  RAout_0__MGIOL \RAout[0]_MGIOL ( .IOLDO(\RAout_c[0] ), .OPOS(\RA[0] ), 
     .CLK(C14M_c));
-  RA_9_ \RA[9]_I ( .IOLDO(\RA_c[9] ), .RA9(RA[9]));
-  RA_9__MGIOL \RA[9]_MGIOL ( .IOLDO(\RA_c[9] ), .OPOS(N_59_i), .CLK(C14M_c));
-  RA_8_ \RA[8]_I ( .IOLDO(\RA_c[8] ), .RA8(RA[8]));
-  RA_8__MGIOL \RA[8]_MGIOL ( .IOLDO(\RA_c[8] ), .OPOS(N_49_i), .CLK(C14M_c));
-  RA_7_ \RA[7]_I ( .IOLDO(\RA_c[7] ), .RA7(RA[7]));
-  RA_7__MGIOL \RA[7]_MGIOL ( .IOLDO(\RA_c[7] ), .OPOS(N_549_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_6_ \RA[6]_I ( .IOLDO(\RA_c[6] ), .RA6(RA[6]));
-  RA_6__MGIOL \RA[6]_MGIOL ( .IOLDO(\RA_c[6] ), .OPOS(N_550_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_5_ \RA[5]_I ( .IOLDO(\RA_c[5] ), .RA5(RA[5]));
-  RA_5__MGIOL \RA[5]_MGIOL ( .IOLDO(\RA_c[5] ), .OPOS(\RA_42_3_0[5] ), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_4_ \RA[4]_I ( .IOLDO(\RA_c[4] ), .RA4(RA[4]));
-  RA_4__MGIOL \RA[4]_MGIOL ( .IOLDO(\RA_c[4] ), .OPOS(N_551_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
-  RA_2_ \RA[2]_I ( .IOLDO(\RA_c[2] ), .RA2(RA[2]));
-  RA_2__MGIOL \RA[2]_MGIOL ( .IOLDO(\RA_c[2] ), .OPOS(N_553_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_1_ \RA[1]_I ( .IOLDO(\RA_c[1] ), .RA1(RA[1]));
-  RA_1__MGIOL \RA[1]_MGIOL ( .IOLDO(\RA_c[1] ), .OPOS(N_558_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
   BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1]));
-  BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), 
-    .LSR(N_566_i), .CLK(C14M_c));
+  BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), .CE(N_225_i), 
+    .LSR(BA_0_sqmuxa), .CLK(C14M_c));
   BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0]));
-  BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), 
-    .LSR(N_566_i), .CLK(C14M_c));
-  nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE));
-  nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(nRWE_r_0), .CLK(C14M_c));
-  nCAS nCAS_I( .IOLDO(nCAS_c), .nCAS(nCAS));
-  nCAS_MGIOL nCAS_MGIOL( .IOLDO(nCAS_c), .OPOS(N_561_i), .CLK(C14M_c));
-  nRAS nRAS_I( .IOLDO(nRAS_c), .nRAS(nRAS));
-  nRAS_MGIOL nRAS_MGIOL( .IOLDO(nRAS_c), .OPOS(nRAS_2_iv_i), .CLK(C14M_c));
-  nCS nCS_I( .IOLDO(nCS_c), .nCS(nCS));
-  nCS_MGIOL nCS_MGIOL( .IOLDO(nCS_c), .OPOS(N_559_i), .CLK(C14M_c));
-  CKE CKE_I( .IOLDO(CKE_c), .CKE(CKE));
-  CKE_MGIOL CKE_MGIOL( .IOLDO(CKE_c), .OPOS(CKE_6_iv_i_0), .CLK(C14M_c));
-  nVOE nVOE_I( .PADDO(PHI1_c), .nVOE(nVOE));
+  BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), .CE(N_225_i), 
+    .LSR(BA_0_sqmuxa), .CLK(C14M_c));
+  nRWEout nRWEout_I( .IOLDO(nRWEout_c), .nRWEout(nRWEout));
+  nRWEout_MGIOL nRWEout_MGIOL( .IOLDO(nRWEout_c), .OPOS(nRWE), .CLK(C14M_c));
+  nCASout nCASout_I( .IOLDO(nCASout_c), .nCASout(nCASout));
+  nCASout_MGIOL nCASout_MGIOL( .IOLDO(nCASout_c), .OPOS(nCAS), .CLK(C14M_c));
+  nRASout nRASout_I( .IOLDO(nRASout_c), .nRASout(nRASout));
+  nRASout_MGIOL nRASout_MGIOL( .IOLDO(nRASout_c), .OPOS(nRAS), .CLK(C14M_c));
+  nCSout nCSout_I( .PADDO(GND), .nCSout(nCSout));
+  CKEout CKEout_I( .IOLDO(CKEout_c), .CKEout(CKEout));
+  CKEout_MGIOL CKEout_MGIOL( .IOLDO(CKEout_c), .OPOS(CKE), .CLK(C14M_c));
+  nVOE nVOE_I( .PADDO(nVOE_c), .nVOE(nVOE));
   Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7]));
   Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), 
     .CE(Vout3), .CLK(C14M_c));
@@ -572,30 +890,14 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), 
     .CE(Vout3), .CLK(C14M_c));
   nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE));
-  Dout_7_ \Dout[7]_I ( .IOLDO(\Dout_c[7] ), .Dout7(Dout[7]));
-  Dout_7__MGIOL \Dout[7]_MGIOL ( .IOLDO(\Dout_c[7] ), .OPOS(\RD_in[7] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_6_ \Dout[6]_I ( .IOLDO(\Dout_c[6] ), .Dout6(Dout[6]));
-  Dout_6__MGIOL \Dout[6]_MGIOL ( .IOLDO(\Dout_c[6] ), .OPOS(\RD_in[6] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_5_ \Dout[5]_I ( .IOLDO(\Dout_c[5] ), .Dout5(Dout[5]));
-  Dout_5__MGIOL \Dout[5]_MGIOL ( .IOLDO(\Dout_c[5] ), .OPOS(\RD_in[5] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_4_ \Dout[4]_I ( .IOLDO(\Dout_c[4] ), .Dout4(Dout[4]));
-  Dout_4__MGIOL \Dout[4]_MGIOL ( .IOLDO(\Dout_c[4] ), .OPOS(\RD_in[4] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_3_ \Dout[3]_I ( .IOLDO(\Dout_c[3] ), .Dout3(Dout[3]));
-  Dout_3__MGIOL \Dout[3]_MGIOL ( .IOLDO(\Dout_c[3] ), .OPOS(\RD_in[3] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_2_ \Dout[2]_I ( .IOLDO(\Dout_c[2] ), .Dout2(Dout[2]));
-  Dout_2__MGIOL \Dout[2]_MGIOL ( .IOLDO(\Dout_c[2] ), .OPOS(\RD_in[2] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_1_ \Dout[1]_I ( .IOLDO(\Dout_c[1] ), .Dout1(Dout[1]));
-  Dout_1__MGIOL \Dout[1]_MGIOL ( .IOLDO(\Dout_c[1] ), .OPOS(\RD_in[1] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_0_ \Dout[0]_I ( .IOLDO(\Dout_c[0] ), .Dout0(Dout[0]));
-  Dout_0__MGIOL \Dout[0]_MGIOL ( .IOLDO(\Dout_c[0] ), .OPOS(\RD_in[0] ), 
-    .CE(N_576_i), .CLK(C14M_c));
+  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
+  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
+  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
+  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
+  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
+  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
+  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
+  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
   Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
   Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
   Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
@@ -614,21 +916,25 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0]));
   nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X));
   nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80));
-  nWE80 nWE80_I( .PADDI(nWE80_c), .nWE80(nWE80));
   nWE nWE_I( .PADDI(nWE_c), .nWE(nWE));
   PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1));
-  PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1reg));
-  ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), .WBRSTI(wb_rst), 
-    .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), 
-    .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), 
-    .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), 
-    .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), 
-    .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), 
-    .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), 
-    .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), 
-    .WBDATO2(\wb_dato[2] ), .WBDATO3(\wb_dato[3] ), .WBDATO4(\wb_dato[4] ), 
-    .WBDATO5(\wb_dato[5] ), .WBDATO6(\wb_dato[6] ), .WBDATO7(\wb_dato[7] ), 
-    .WBACKO(wb_ack));
+  PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1r));
+  ram2e_ufm_ufmefb_EFBInst_0 \ram2e_ufm/ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), 
+    .WBRSTI(\ram2e_ufm/wb_rst ), .WBCYCI(\ram2e_ufm/wb_cyc_stb ), 
+    .WBSTBI(\ram2e_ufm/wb_cyc_stb ), .WBWEI(\ram2e_ufm/wb_we ), 
+    .WBADRI0(\ram2e_ufm/wb_adr[0] ), .WBADRI1(\ram2e_ufm/wb_adr[1] ), 
+    .WBADRI2(\ram2e_ufm/wb_adr[2] ), .WBADRI3(\ram2e_ufm/wb_adr[3] ), 
+    .WBADRI4(\ram2e_ufm/wb_adr[4] ), .WBADRI5(\ram2e_ufm/wb_adr[5] ), 
+    .WBADRI6(\ram2e_ufm/wb_adr[6] ), .WBADRI7(\ram2e_ufm/wb_adr[7] ), 
+    .WBDATI0(\ram2e_ufm/wb_dati[0] ), .WBDATI1(\ram2e_ufm/wb_dati[1] ), 
+    .WBDATI2(\ram2e_ufm/wb_dati[2] ), .WBDATI3(\ram2e_ufm/wb_dati[3] ), 
+    .WBDATI4(\ram2e_ufm/wb_dati[4] ), .WBDATI5(\ram2e_ufm/wb_dati[5] ), 
+    .WBDATI6(\ram2e_ufm/wb_dati[6] ), .WBDATI7(\ram2e_ufm/wb_dati[7] ), 
+    .WBDATO0(\ram2e_ufm/wb_dato[0] ), .WBDATO1(\ram2e_ufm/wb_dato[1] ), 
+    .WBDATO2(\ram2e_ufm/wb_dato[2] ), .WBDATO3(\ram2e_ufm/wb_dato[3] ), 
+    .WBDATO4(\ram2e_ufm/wb_dato[4] ), .WBDATO5(\ram2e_ufm/wb_dato[5] ), 
+    .WBDATO6(\ram2e_ufm/wb_dato[6] ), .WBDATO7(\ram2e_ufm/wb_dato[7] ), 
+    .WBACKO(\ram2e_ufm/wb_ack ));
   VHI VHI_INST( .Z(VCCI));
   PUR PUR_INST( .PUR(VCCI));
   GSR GSR_INST( .GSR(VCCI));
@@ -939,20 +1245,62 @@ module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
 
 endmodule
 
-module SLICE_9 ( input C1, B1, A1, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
+module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut4 \ram2e_ufm/wb_req_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40003 \ram2e_ufm/CKE_7_RNIS77M1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0004 CKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut4 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40003 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAAAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_10 ( input B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut4 S_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40005 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40003 \CmdTout_3_0_a2[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  lut40006 \ram2e_ufm/CmdTout_3_0_a3_0_a3[0] ( .A(A0), .B(B0), .C(GNDI), 
+    .D(GNDI), .Z(F0));
   vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
@@ -964,27 +1312,59 @@ module SLICE_9 ( input C1, B1, A1, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
 
 endmodule
 
-module lut4 ( input A, B, C, D, output Z );
+module lut40005 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40003 ( input A, B, C, D, output Z );
+module lut40006 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly;
+module SLICE_11 ( input B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40004 \CS_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40005 \CS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40006 \ram2e_ufm/RC_3_0_0_a3_1[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre0006 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
+  lut40007 \ram2e_ufm/N_360_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \RC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40007 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_12 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly;
+
+  lut40008 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNI6S1P8 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40009 \ram2e_ufm/S_r_i_0_o2_RNIVM0LF[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0010 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre0006 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+  vmuxregsre0010 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
 
   specify
@@ -992,6 +1372,7 @@ module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK,
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1008,37 +1389,40 @@ module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK,
 
 endmodule
 
-module lut40004 ( input A, B, C, D, output Z );
+module lut40008 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hA9AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40005 ( input A, B, C, D, output Z );
+module lut40009 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h00F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q );
+module vmuxregsre0010 ( input D0, D1, SD, SP, CK, LSR, output Q );
 
   FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module SLICE_11 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
+module SLICE_13 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
 
-  lut40007 \CS_RNO_0[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40008 \CS_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0006 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+  lut40011 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 ( .A(A1), 
+    .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40012 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0010 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1053,138 +1437,34 @@ module SLICE_11 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0,
 
 endmodule
 
-module lut40007 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40008 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h6C6C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_12 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40009 CmdBitbangMXO2_4_u_0_0_a2_0_1( .A(A1), .B(B1), .C(C1), .D(GNDI), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40010 CmdBitbangMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdBitbangMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40009 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40010 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_13 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40011 un1_CS_0_sqmuxa_0_0_a2_7( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40010 CmdExecMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdExecMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
 module lut40011 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40012 CmdLEDGet_4_u_0_0_a2_0_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40010 CmdLEDGet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hA2A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40012 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hC4C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_15 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
+module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
     Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40013 CmdLEDSet_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40014 CmdLEDSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40013 \ram2e_ufm/CmdLEDGet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40014 \ram2e_ufm/CmdLEDGet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1199,23 +1479,24 @@ endmodule
 
 module lut40013 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40014 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_16 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
+module SLICE_15 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
     Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40007 CmdBitbangMXO2_4_u_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(GNDI), 
-    .Z(F1));
+  lut40013 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40010 CmdRWMaskSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40015 \ram2e_ufm/CmdLEDSet_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
@@ -1236,24 +1517,30 @@ module SLICE_16 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
-module SLICE_17 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+module lut40015 ( input A, B, C, D, output Z );
 
-  lut40015 CmdSetRWBankFFLED_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), 
-    .Z(F1));
-  lut40014 CmdSetRWBankFFLED_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_16 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40017 \ram2e_ufm/CmdRWMaskSet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
-    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1266,21 +1553,26 @@ module SLICE_17 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40015 ( input A, B, C, D, output Z );
+module lut40016 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_18 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
+module lut40017 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_17 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
     Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40011 CmdSetRWBankFFLED_4_u_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+  lut40018 \ram2e_ufm/CmdRWMaskSet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
     .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40010 CmdSetRWBankFFMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
-  vmuxregsre CmdSetRWBankFFMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+  lut40019 \ram2e_ufm/CmdSetRWBankFFLED_4_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
     .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
@@ -1301,12 +1593,22 @@ module SLICE_18 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
-module SLICE_19 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output 
+module lut40018 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40019 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output 
     F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40016 \CmdTout_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40017 \CmdTout_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40020 \ram2e_ufm/N_369_i ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40021 \ram2e_ufm/N_368_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
   vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
@@ -1333,26 +1635,65 @@ module SLICE_19 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output
 
 endmodule
 
-module lut40016 ( input A, B, C, D, output Z );
+module lut40020 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h006A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0078) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40017 ( input A, B, C, D, output Z );
+module lut40021 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h0606) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+module SLICE_19 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, M0_dly, CLK_dly, LSR_dly;
 
-  lut40018 \S_RNII9DO1_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40019 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre DOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  lut40022 \ram2e_ufm/SUM0_i_o2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/RA_35_i_i_0_a3_0[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre0010 DOEEN( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40022 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40023 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40024 \ram2e_ufm/RA_35_i_i_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40025 \ram2e_ufm/RA_35_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \RA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -1364,42 +1705,8 @@ module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40018 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40019 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hA888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_21 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40020 \RA_0io_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40021 LEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
     $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
@@ -1408,30 +1715,68 @@ module SLICE_21 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
 
 endmodule
 
-module lut40020 ( input A, B, C, D, output Z );
+module lut40024 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40021 ( input A, B, C, D, output Z );
+module lut40025 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hECFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_22 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
+module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40020 \RA_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40026 \ram2e_ufm/RA_35_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40020 \RA_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40024 \ram2e_ufm/RA_35_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
   vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40026 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_22 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40024 \ram2e_ufm/RA_35_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40026 \ram2e_ufm/RA_35_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \RA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -1453,9 +1798,160 @@ module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40014 \RWBank_5_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40026 \ram2e_ufm/RA_35_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40014 \RWBank_5_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40026 \ram2e_ufm/RA_35_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre \RA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40026 \ram2e_ufm/RA_35_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40027 \ram2e_ufm/un2_S_2_i_0_0_o3_RNIHFHN3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre \RA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40027 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_25 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40028 \ram2e_ufm/RA_35_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut4 \ram2e_ufm/RA_35_2_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \RA[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \RA[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40028 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_26 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40029 \ram2e_ufm/RC_3_0_0[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40030 \ram2e_ufm/RC_3_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \RC[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RC[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40029 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h3838) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40030 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4646) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_27 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40031 \ram2e_ufm/RWBank_3_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40031 \ram2e_ufm/RWBank_3_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
   vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1480,13 +1976,18 @@ module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module SLICE_24 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+module lut40031 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_28 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40014 \RWBank_5_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40031 \ram2e_ufm/RWBank_3_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40014 \RWBank_5_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40031 \ram2e_ufm/RWBank_3_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
   vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1511,13 +2012,14 @@ module SLICE_24 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module SLICE_25 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40014 \RWBank_5_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40031 \ram2e_ufm/RWBank_3_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40014 \RWBank_5_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40031 \ram2e_ufm/RWBank_3_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
   vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1542,13 +2044,13 @@ module SLICE_25 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module SLICE_26 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40022 \RWBank_5_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40032 \ram2e_ufm/RWBank_3_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40014 \RWBank_5_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40031 \ram2e_ufm/RWBank_3_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
   vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1573,152 +2075,25 @@ module SLICE_26 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40022 ( input A, B, C, D, output Z );
+module lut40032 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_27 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40023 \RWMask_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 \RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40023 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h7474) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_28 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40023 \RWMask_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 \RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40023 \RWMask_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 \RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40021 \RWMask_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 \RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40024 nDOE_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40025 RWSel_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40033 \ram2e_ufm/RA_35_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40034 \ram2e_ufm/RWSel_2_0_a3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
   vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -1735,12 +2110,12 @@ module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40024 ( input A, B, C, D, output Z );
+module lut40033 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40025 ( input A, B, C, D, output Z );
+module lut40034 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
@@ -1748,8 +2123,8 @@ endmodule
 module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly;
 
-  lut40026 Ready_0_sqmuxa_0_a2_6_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40027 Ready_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  lut40035 \ram2e_ufm/Ready3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40036 Ready_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
   vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
@@ -1770,12 +2145,12 @@ module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
 
 endmodule
 
-module lut40026 ( input A, B, C, D, output Z );
+module lut40035 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40027 ( input A, B, C, D, output Z );
+module lut40036 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
@@ -1784,8 +2159,9 @@ module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
     F0, Q0, F1, Q1 );
   wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
 
-  lut40028 \S_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40029 \S_s_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40037 \ram2e_ufm/S_r_i_0_o2_0_RNI36E21[1] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40038 \ram2e_ufm/S_s_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
   vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1812,22 +2188,24 @@ module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
 
 endmodule
 
-module lut40028 ( input A, B, C, D, output Z );
+module lut40037 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h5100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40029 ( input A, B, C, D, output Z );
+module lut40038 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFBA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFBFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output 
     F0, Q0, F1, Q1 );
   wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
 
-  lut40030 \S_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40031 \S_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40039 \ram2e_ufm/S_r_i_0_o2_RNIFNP81_0[2] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40040 \ram2e_ufm/S_r_i_0_o2_RNIFNP81[2] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
   vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1854,354 +2232,62 @@ module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
 
 endmodule
 
-module lut40030 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5510) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40031 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40032 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40032 \wb_adr_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40032 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_36 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40033 \wb_adr_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40033 \wb_adr_RNO[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40033 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_37 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40034 \wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40034 \wb_adr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40034 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_38 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40033 \wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40034 \wb_adr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_39 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40035 wb_cyc_stb_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40022 wb_cyc_stb_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40035 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h000E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40036 \wb_dati_7_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40037 \wb_dati_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40036 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40037 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_41 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40038 \wb_dati_7_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40036 \wb_dati_7_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40038 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40036 \wb_dati_7_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 \wb_dati_7_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
 module lut40039 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_43 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40039 \wb_dati_7_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40040 \wb_dati_7_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0B0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40040 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_44 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output 
-    F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
+module SLICE_35 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
 
-  lut40011 wb_req_RNO_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40016 \ram2e_ufm/CKE_7_m1_0_0_o2_RNICM8E1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40036 \ram2e_ufm/CKE_7_m1_0_0_o2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40041 wb_req_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0006 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre0010 VOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40041 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40042 \ram2e_ufm/nCAS_s_i_0_a3_RNIO1UQ3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0004 nCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -2211,10 +2297,6 @@ module SLICE_44 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge LSR, 0:0:0);
-    $width (negedge LSR, 0:0:0);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
@@ -2223,43 +2305,93 @@ endmodule
 
 module lut40041 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_45 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
+module lut40042 ( input A, B, C, D, output Z );
 
-  lut40027 \un1_LEDEN13_2_i_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40003 wb_rst8_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  vmuxregsre0006 wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  ROM16X1A #(16'h1101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40034 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40016 \ram2e_ufm/nRAS_s_i_0_0_RNI0PC64 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0004 nRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge LSR, 0:0:0);
-    $width (negedge LSR, 0:0:0);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
-module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
+module SLICE_38 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40043 \ram2e_ufm/nRAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40044 \ram2e_ufm/nRAS_s_i_0_a3_0_RNIIR094 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre0004 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40043 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40044 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_39 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
   wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40042 wb_we_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40043 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  lut40045 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40019 \ram2e_ufm/CmdBitbangMXO2_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/CmdBitbangMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
 
@@ -2281,122 +2413,254 @@ module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
 
 endmodule
 
-module lut40042 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40043 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40044 DQMH_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 \S_RNII9DO1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40044 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40045 Vout3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40046 nCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
 module lut40045 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_40 ( input D1, C1, B1, A1, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40014 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40023 \ram2e_ufm/CmdExecMXO2_3_0_a3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/CmdExecMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40046 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0_0 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40014 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/CmdSetRWBankFFChip ( .D0(VCCI), .D1(DI0_dly), 
+    .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40046 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_42 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40015 un1_CS_0_sqmuxa_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40047 un1_CS_0_sqmuxa_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40047 \ram2e_ufm/SUM1_0_o3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40048 \ram2e_ufm/LEDEN_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/LEDEN ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40047 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40048 \wb_dati_7_0_a2_0_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40049 \wb_dati_7_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40048 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0D00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_43 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40049 \ram2e_ufm/RWMask_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 \ram2e_ufm/RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40049 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7474) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_44 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40050 CKE_6_iv_i_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40051 CKE_6_iv_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40049 \ram2e_ufm/RWMask_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 \ram2e_ufm/RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_45 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40049 \ram2e_ufm/RWMask_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 \ram2e_ufm/RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_46 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40048 \ram2e_ufm/RWMask_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40049 \ram2e_ufm/RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40050 \ram2e_ufm/wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40024 \ram2e_ufm/wb_adr_7_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2407,53 +2671,174 @@ module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40050 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2F2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_48 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40023 \ram2e_ufm/wb_adr_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/wb_adr_RNO[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_49 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40051 \ram2e_ufm/wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40051 \ram2e_ufm/wb_adr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40051 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_50 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40052 \un1_LEDEN13_2_i_a2_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40053 \un1_LEDEN13_2_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40023 \ram2e_ufm/wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40051 \ram2e_ufm/wb_adr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_51 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40052 \ram2e_ufm/wb_cyc_stb_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40053 \ram2e_ufm/wb_cyc_stb_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_cyc_stb ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40052 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40053 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40054 \un1_wb_adr_0_sqmuxa_2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+  lut40054 \ram2e_ufm/wb_dati_7_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
     .Z(F1));
-  lut40055 wb_we_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40055 \ram2e_ufm/wb_dati_7_0_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2464,24 +2849,41 @@ module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40054 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3FF5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40055 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40056 un1_CS_0_sqmuxa_0_0_a2_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40057 un1_CS_0_sqmuxa_0_0_o2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40054 \ram2e_ufm/wb_dati_7_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40054 \ram2e_ufm/wb_dati_7_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2492,24 +2894,161 @@ module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40054 \ram2e_ufm/wb_dati_7_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut4 \ram2e_ufm/wb_dati_7_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut4 \ram2e_ufm/wb_dati_7_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40054 \ram2e_ufm/wb_dati_7_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, 
+    CLK, output F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
+
+  lut4 \ram2e_ufm/wb_reqc_1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40056 \ram2e_ufm/wb_req_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0010 \ram2e_ufm/wb_req ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40056 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40057 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_57 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40035 \ram2e_ufm/Ready3_0_a3_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40006 \ram2e_ufm/wb_rst8_0_a3_0_a3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre0010 \ram2e_ufm/wb_rst ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
 
-  ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40058 nCS_6_u_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40018 un1_nCS61_1_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40057 \ram2e_ufm/wb_we_RNO_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40057 \ram2e_ufm/wb_we_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_we ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2520,98 +3059,154 @@ module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40057 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SUM0_i_m3_0_SLICE_59 ( input C1, B1, A1, C0, B0, A0, M0, 
+    output OFX0 );
+  wire   GNDI, 
+         \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 , 
+         \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ;
+
+  lut40058 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), 
+    .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40059 \ram2e_ufm/SUM0_i_m3_0/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ));
+  selmux2 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K0K1MUX ( 
+    .D0(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ), 
+    .D1(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ), 
+    .SD(M0), .Z(OFX0));
+
+  specify
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40058 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFF1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_56 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40059 \wb_dati_7_0_a2_5[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40060 \wb_dati_7_0_a2_6[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40059 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module selmux2 ( input D0, D1, SD, output Z );
+
+  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
+endmodule
+
+module ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 ( input D1, C1, B1, A1, C0, B0, 
+    A0, M0, output OFX0 );
+  wire   
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 
+         , GNDI, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 
+         ;
+
+  lut40060 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), 
+    .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 )
+    );
+  lut40061 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE ( .A(A0), .B(B0), .C(C0), 
+    .D(GNDI), 
+    .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 )
+    );
+  gnd DRIVEGND( .PWR0(GNDI));
+  selmux2 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K0K1MUX ( 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 )
+    , 
+    .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 )
+    , .SD(M0), .Z(OFX0));
+
+  specify
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40060 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40061 \un1_LEDEN13_2_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40062 \S_RNII9DO1_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h55D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40061 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40062 ( input A, B, C, D, output Z );
+module ram2e_ufm_CKE_7_SLICE_61 ( input C1, B1, A1, C0, B0, A0, M0, output 
+    OFX0 );
+  wire   GNDI, \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 , 
+         \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ;
 
-  ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40063 \wb_dati_7_0_2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40025 \wb_dati_7_0_2_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40062 \ram2e_ufm/CKE_7/SLICE_61_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40063 \ram2e_ufm/CKE_7/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ));
+  selmux2 \ram2e_ufm/CKE_7/SLICE_61_K0K1MUX ( 
+    .D0(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ), 
+    .D1(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ), .SD(M0), 
+    .Z(OFX0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module lut40063 ( input A, B, C, D, output Z );
+module lut40062 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h4440) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5D5D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40063 ( input A, B, C, D, output Z );
 
-  lut40064 DQML_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40065 DQML_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40043 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIAJ811 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40064 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIPG3P2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2628,26 +3223,23 @@ endmodule
 
 module lut40064 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h7377) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40065 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_60 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40066 \wb_adr_RNO_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40009 \wb_adr_RNO_3[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40065 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40066 \ram2e_ufm/S_r_i_0_o2_RNI3VQTC[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -2655,17 +3247,24 @@ module SLICE_60 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40066 ( input A, B, C, D, output Z );
+module lut40065 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2A20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_61 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40066 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40011 \wb_dati_7_0_a2_2_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40067 \ram2e_ufm/wb_adr_7_i_i_a3_6[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40067 \FS_RNIOD6E_1[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40068 \ram2e_ufm/wb_adr_7_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
@@ -2681,50 +3280,27 @@ endmodule
 
 module lut40067 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_62 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40068 \wb_adr_RNO_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40069 \wb_adr_RNO_2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40068 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40069 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'h9595) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40039 \un1_LEDEN13_2_i_o2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40038 \FS_RNI9FGA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40069 \ram2e_ufm/SUM0_i_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40065 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -2732,15 +3308,21 @@ module SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module lut40069 ( input A, B, C, D, output Z );
 
-  lut40070 \FS_RNI6JJA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40013 \un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
+  ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40070 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40071 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -2754,59 +3336,23 @@ endmodule
 
 module lut40070 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_65 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40007 \wb_dati_7_0_a2_0_0[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40026 \wb_dati_7_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_66 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40003 \FS_RNIJ9MH[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40071 wb_we_RNO_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40071 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF5F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_67 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40027 wb_reqc_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  lut40072 \ram2e_ufm/nRAS_s_i_0_m3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40072 wb_reqc_1_RNIRU4M1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40073 \ram2e_ufm/nRAS_s_i_0_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -2819,36 +3365,21 @@ endmodule
 
 module lut40072 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40073 \wb_dati_7_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40015 \FS_RNIOD6E_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40073 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFF6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40074 \RA_42_0[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40075 \RA_42_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40074 \ram2e_ufm/wb_adr_7_i_i_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40075 \ram2e_ufm/wb_adr_7_i_i_3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2865,18 +3396,19 @@ endmodule
 
 module lut40074 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40075 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0208) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h01A1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40063 \wb_dati_7_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40076 \FS_RNIOD6E[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40076 \ram2e_ufm/nCAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut4 \ram2e_ufm/wb_rst16_i_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2893,16 +3425,19 @@ endmodule
 
 module lut40076 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h4888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_70 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40077 nRWE_r_0_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40018 \S_RNII9DO1_3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40077 \ram2e_ufm/wb_dati_7_0_0_a3_12[7] ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40078 \ram2e_ufm/wb_dati_7_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -2916,120 +3451,27 @@ endmodule
 
 module lut40077 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40026 Ready_0_sqmuxa_0_a2_6_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40025 \FS_RNI5OOF1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40078 \wb_adr_7_0_a2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40067 \FS_RNIK5632[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40078 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_71 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut4 \wb_dati_7_0_a2_5[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40013 \ram2e_ufm/RA_35_0_0_a3_4[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40026 \wb_dati_7_0_a2_5_RNIC22J[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40079 \ram2e_ufm/nRAS_s_i_0_a3_4 ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
     .Z(F0));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_75 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40015 nCS_6_u_i_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut4 nCS_6_u_i_a2_4_RNI3A062( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40027 nCS_6_u_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40065 nCS_6_u_i_a2_4_RNICJKD2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40009 un1_CS_0_sqmuxa_0_0_a2_10( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40079 un1_CS_0_sqmuxa_0_0_2_RNIQS7F( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -3039,20 +3481,22 @@ endmodule
 
 module lut40079 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0103) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40027 nCAS_s_i_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  lut40080 \ram2e_ufm/BA_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40047 \ram2e_ufm/un1_RC12_i_0_o3 ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40080 nCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -3062,21 +3506,24 @@ endmodule
 
 module lut40080 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hC0D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_79 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40081 nCS_6_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40003 nCS_0io_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40081 \ram2e_ufm/wb_dati_7_0_0_o3_0[2] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40082 \ram2e_ufm/wb_dati_7_0_0_a3_3[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
@@ -3085,44 +3532,24 @@ endmodule
 
 module lut40081 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0212) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_80 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40082 nRAS_2_iv_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40083 nRAS_2_iv_i( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40082 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1212) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40083 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40018 un1_CS_0_sqmuxa_0_0_a2_1_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40047 un1_CS_0_sqmuxa_0_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40053 \ram2e_ufm/RA_35_2_0_0[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40034 \ram2e_ufm/RA_35_2_0_a3_5[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -3134,13 +3561,60 @@ module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40084 un1_CS_0_sqmuxa_0_0_a2_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 un1_CS_0_sqmuxa_0_0_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40079 \ram2e_ufm/wb_dati_7_0_0_a3_15[7] ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40015 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0] ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40083 \ram2e_ufm/wb_dati_7_0_0_a3_13[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40019 \ram2e_ufm/wb_dati_7_0_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40083 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40084 \ram2e_ufm/SUM2_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40085 \ram2e_ufm/N_314_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -3154,17 +3628,24 @@ endmodule
 
 module lut40084 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40085 ( input A, B, C, D, output Z );
 
-  lut40025 nCS_6_u_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40085 nCS_6_u_i_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40036 \ram2e_ufm/S_r_i_0_o2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40041 \ram2e_ufm/S_r_i_0_o2_RNIP4KI1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3175,15 +3656,13 @@ module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40085 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_79 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40086 \wb_dati_7_0_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40053 \wb_dati_7_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40086 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40087 \ram2e_ufm/S_r_i_0_o2_RNIOGTF1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3200,36 +3679,20 @@ endmodule
 
 module lut40086 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40087 \wb_adr_7_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 \wb_adr_7_0_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40087 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCC08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40067 \wb_dati_7_0_a2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40073 \un1_LEDEN_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40034 \ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40088 \ram2e_ufm/CmdBitbangMXO2_RNINSM62 ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
 
   specify
@@ -3245,56 +3708,22 @@ module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40013 un1_CS_0_sqmuxa_0_0_a2_4_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40059 un1_CS_0_sqmuxa_0_0_a2_4( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40088 \FS_RNI9Q57[13] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40085 \wb_dati_7_0_o2_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
 module lut40088 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_89 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40027 \wb_adr_7_0_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40065 \wb_adr_7_0_a2_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40017 \ram2e_ufm/wb_dati_7_0_0_a3_14[7] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40035 \ram2e_ufm/wb_dati_7_0_0_a3_13_RNI81UL[7] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3305,18 +3734,41 @@ module SLICE_89 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40089 \wb_dati_7_0_o2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40011 \wb_dati_7_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40019 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_83 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40067 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40089 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -3326,32 +3778,16 @@ endmodule
 
 module lut40089 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_91 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40015 un1_CS_0_sqmuxa_0_0_a2_2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40011 un1_CS_0_sqmuxa_0_0_a2_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40090 \wb_adr_7_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40091 \wb_adr_7_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40082 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40090 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3368,63 +3804,90 @@ endmodule
 
 module lut40090 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h3130) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40017 \ram2e_ufm/wb_dati_7_0_0_a3_10[7] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40086 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_86 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40023 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_1 ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut4 \ram2e_ufm/wb_adr_7_i_i_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40091 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40092 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_m3 ( .A(A0), .B(B0), .C(C0), 
+    .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40091 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40092 un1_CS_0_sqmuxa_0_0_a2_1_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40068 un1_CS_0_sqmuxa_0_0_a2_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40092 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8D8D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40026 un1_CS_0_sqmuxa_0_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40065 un1_CS_0_sqmuxa_0_0_a2_3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40093 \ram2e_ufm/wb_dati_7_0_0_a3_4_1_0[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40094 \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40056 wb_we_RNO_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40093 wb_we_RNO_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3437,15 +3900,22 @@ endmodule
 
 module lut40093 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40094 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hC8C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_89 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40094 \RA_42_i_o2[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40077 \ram2e_ufm/wb_dati_7_0_0_a3_7[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40095 \RA_0io_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40055 \ram2e_ufm/wb_dati_7_0_0_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
@@ -3459,24 +3929,17 @@ module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40094 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'hEFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40095 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h5044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_97 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40033 \wb_dati_7_0_a2_1[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40072 CKE_6_iv_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40095 \ram2e_ufm/wb_dati_7_0_0_a3_1_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40055 \ram2e_ufm/wb_dati_7_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3487,14 +3950,19 @@ module SLICE_97 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_98 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module lut40095 ( input A, B, C, D, output Z );
 
-  lut40096 un1_CS_0_sqmuxa_0_0_a2_16( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40065 un1_CS_0_sqmuxa_0_0_a2_4_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'h0021) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40096 \ram2e_ufm/nRAS_s_i_0_a3_8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40097 \ram2e_ufm/nRAS_s_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -3508,127 +3976,57 @@ endmodule
 
 module lut40096 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_99 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40003 un1_CS_0_sqmuxa_0_0_a2_12( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40013 un1_CS_0_sqmuxa_0_0_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_100 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40011 un1_CS_0_sqmuxa_0_0_a2_17( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40009 CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), 
-    .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40097 wb_reqc_1_RNIEO5C1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40098 \S_RNII9DO1_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40097 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40098 \ram2e_ufm/CKE_7s2_0_0_o3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40099 \ram2e_ufm/nCAS_s_i_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40098 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hC289) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40099 \S_s_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40018 \BA_0io_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h5C50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40099 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hD550) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_93 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40056 \RA_0io_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40039 wb_req_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40100 \ram2e_ufm/wb_dati_7_0_0_o2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40013 \ram2e_ufm/wb_dati_7_0_0_a3[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40065 \wb_dati_7_0_a2_3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40100 \wb_adr_7_0_a2_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -3638,18 +4036,19 @@ endmodule
 
 module lut40100 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40101 \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
-    .Z(F1));
-  lut40045 \wb_dati_7_0_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40101 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40041 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3662,44 +4061,18 @@ endmodule
 
 module lut40101 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_106 ( input B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40102 \S_RNINI6S[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40103 CKE_6_iv_i_0_1_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40102 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40103 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_107 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40102 \S_r_i_o2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40018 \BA_0io_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40102 \ram2e_ufm/RA_35_0_0_o2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40033 \ram2e_ufm/RA_35_0_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3710,12 +4083,45 @@ module SLICE_107 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_108 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40102 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hEAE8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40103 \ram2e_ufm/RA_35_0_0_o2_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40033 \ram2e_ufm/RA_35_0_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40103 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1512) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_97 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40007 \wb_adr_7_0_a2_5_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40104 \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40104 \wb_dati_7_0_a2[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40055 \ram2e_ufm/wb_dati_7_0_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
@@ -3731,17 +4137,19 @@ endmodule
 
 module lut40104 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_98 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40037 \wb_dati_7_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40037 \wb_dati_7_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40093 \ram2e_ufm/wb_dati_7_0_0_a3_9[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40055 \ram2e_ufm/wb_dati_7_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3752,13 +4160,16 @@ module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_99 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40105 \RA_0io_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40055 CmdBitbangMXO2_RNI8CSO1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40105 \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40106 \ram2e_ufm/wb_adr_7_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -3772,79 +4183,21 @@ endmodule
 
 module lut40105 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0023) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_111 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40106 \RA_42_3_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40020 \RA_0io_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40106 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hABAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_112 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40107 nCS_6_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40020 \RA_0io_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40107 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40020 \RA_0io_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40020 \RA_0io_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40073 \wb_dati_7_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40073 \un1_RWMask_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
+  lut4 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40107 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3859,12 +4212,19 @@ module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40107 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hBF8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_101 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40027 nWE80_pad_RNI3ICD( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  lut40022 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3 ( .A(A1), .B(B1), 
+    .C(GNDI), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40108 nRWE_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40108 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (B1 => F1) = (0:0:0,0:0:0);
@@ -3879,15 +4239,35 @@ endmodule
 
 module lut40108 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hB1A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_116 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_102 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40102 \wb_adr_7_0_o2_2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  lut40077 \ram2e_ufm/CKE_7s2_0_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40109 \wb_dati_7_0_a2_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40047 \ram2e_ufm/CKE_7s2_0_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_103 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40101 \ram2e_ufm/wb_dati_7_0_0_0_o2[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40109 \ram2e_ufm/wb_adr_RNO_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (B1 => F1) = (0:0:0,0:0:0);
@@ -3902,14 +4282,16 @@ endmodule
 
 module lut40109 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_117 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_104 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40093 \RWBank_5_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40110 LED_pad_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  lut40110 \ram2e_ufm/wb_dati_7_0_0_o2_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40093 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ( .A(A0), .B(B0), .C(GNDI), 
+    .D(GNDI), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
@@ -3925,16 +4307,870 @@ endmodule
 
 module lut40110 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_118 ( input B1, A1, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_105 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40003 un1_CS_0_sqmuxa_0_0_a2_11( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+  lut40016 \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40111 \ram2e_ufm/N_285_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40111 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_106 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40022 \ram2e_ufm/S_r_i_0_o2[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
     .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40033 un1_CS_0_sqmuxa_0_0_a2_13( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+  lut40112 \ram2e_ufm/RA_35_2_0_a3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40112 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hD050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_107 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40113 \ram2e_ufm/CKE_7_m1_0_0_o2_RNIGC501 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40114 \ram2e_ufm/RA_35_i_i_0_a3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40113 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40114 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hD800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_108 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut4 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40115 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ( .A(A0), 
+    .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40115 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h3131) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_109 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40006 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_6 ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40068 \ram2e_ufm/wb_we_RNO_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_110 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40035 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_7 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40023 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ( .A(A0), .B(B0), 
+    .C(GNDI), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_111 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40104 \ram2e_ufm/wb_dati_7_0_0_a3_2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40116 \ram2e_ufm/wb_dati_7_0_0_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40116 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h9180) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_112 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40018 \ram2e_ufm/nRAS_s_i_0_a3_6 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40117 \ram2e_ufm/nRAS_s_i_0_a3_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40117 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_113 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40077 \ram2e_ufm/nRAS_s_i_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40014 \ram2e_ufm/RA_35_2_0_a3_3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_114 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40118 \ram2e_ufm/wb_adr_RNO_2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40117 \ram2e_ufm/wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40118 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8787) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40036 \ram2e_ufm/un2_S_2_i_0_0_o3 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40119 \ram2e_ufm/CKE_7s2_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40119 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0C4C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_116 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40014 \ram2e_ufm/CmdExecMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40067 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ( .A(A0), .B(B0), 
+    .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_117 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40120 \ram2e_ufm/S_s_0_0_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40121 \ram2e_ufm/N_225_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40120 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0F0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40121 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_118 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40113 \ram2e_ufm/CKE_7_m1_0_0_o2_RNI7FOA1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40122 \ram2e_ufm/N_201_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40122 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_119 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40123 \ram2e_ufm/S_r_i_0_o2_RNIBAU51[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40124 \ram2e_ufm/un1_CKE75_0_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40123 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40124 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hD79B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_120 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40125 \ram2e_ufm/DQMH_4_iv_0_0_i_i_a3_0_a3 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40126 \ram2e_ufm/N_507_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40125 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h31F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40126 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hCD05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_121 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40127 \ram2e_ufm/Vout3_0_a3_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40128 \ram2e_ufm/RA_35_0_0_o2[11] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40127 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40128 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFCF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_122 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40129 \ram2e_ufm/nRWE_s_i_0_63_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40130 \ram2e_ufm/nCAS_s_i_0_m2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40129 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4FFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40130 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h37FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_123 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40131 \ram2e_ufm/wb_adr_RNO_3[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40019 \ram2e_ufm/wb_dati_7_0_0_a3_8[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40131 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_124 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40132 \ram2e_ufm/RA_35_0_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40035 \ram2e_ufm/RA_35_0_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40132 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_125 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40133 \ram2e_ufm/wb_adr_7_i_i_o2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40045 \ram2e_ufm/wb_dati_7_0_0_a3_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40133 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7F70) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_126 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40134 \ram2e_ufm/wb_we_RNO_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40117 \ram2e_ufm/wb_adr_7_i_i_a3_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40134 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h7F07) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_127 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40117 \ram2e_ufm/un9_VOEEN_0_a2_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40046 \ram2e_ufm/RA_35_2_30_a3_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_128 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40135 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40136 \ram2e_ufm/wb_adr_RNO_4[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40135 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h2080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40136 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40080 \ram2e_ufm/BA_4[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40016 \ram2e_ufm/RA_35_2_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_130 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40083 \ram2e_ufm/N_187_i ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40088 \ram2e_ufm/wb_we_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_131 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40035 \ram2e_ufm/Ready3_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40137 \ram2e_ufm/wb_dati_7_0_0_0_a3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40137 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_132 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40138 \ram2e_ufm/RA_35_0_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40033 \ram2e_ufm/RA_35_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40138 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_133 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40035 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40084 \ram2e_ufm/SUM0_i_o2_2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_134 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut4 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40114 \ram2e_ufm/RA_35_0_0_a3[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_135 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40022 \ram2e_ufm/S_r_i_0_o2_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40139 \ram2e_ufm/RA_35_2_0_a3_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40139 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_136 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40140 \ram2e_ufm/nRAS_s_i_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40141 \ram2e_ufm/un1_nDOE_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40140 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5757) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40141 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_137 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40142 \ram2e_ufm/RDOE_i ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40084 \ram2e_ufm/LEDEN_RNI6G6M ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40142 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_138 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40007 VOEEN_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40007 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module SLICE_139 ( input B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40101 nVOE_pad_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40067 S_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_140 ( input B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40023 \ram2e_ufm/RA_35_0_0_a3_0[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/RA_35_0_0_a3[5] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
     .Z(F0));
 
   specify
@@ -3946,12 +5182,114 @@ module SLICE_118 ( input B1, A1, B0, A0, output F0, F1 );
 
 endmodule
 
-module SLICE_119 ( input D0, C0, B0, A0, output F0 );
+module ram2e_ufm_SLICE_141 ( input B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40026 Ready_0_sqmuxa_0_a2_6_a2_2_0( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/N_263_i ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_142 ( input C1, B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40136 \ram2e_ufm/CmdLEDGet_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/RDout_i_i_a3[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
     .Z(F0));
 
   specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_143 ( input B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[7] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_144 ( input B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_145 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40033 \ram2e_ufm/wb_dati_7_0_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40143 \ram2e_ufm/wb_dati_7_0_0_o2_0[7] ( .A(A0), .B(B0), .C(GNDI), 
+    .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40143 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_146 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40144 \ram2e_ufm/RA_35_0_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40035 \ram2e_ufm/Ready3_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -3960,6 +5298,31 @@ module SLICE_119 ( input D0, C0, B0, A0, output F0 );
 
 endmodule
 
+module lut40144 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_147 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40027 \ram2e_ufm/RWBank_3_0_0_o3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40023 \ram2e_ufm/RDout_i_0_i_a3[5] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
 module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
 
   xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
@@ -3982,7 +5345,7 @@ endmodule
 
 module LED ( input PADDO, output LED );
 
-  xo2iobuf0111 LED_pad( .I(PADDO), .PAD(LED));
+  xo2iobuf0145 LED_pad( .I(PADDO), .PAD(LED));
 
   specify
     (PADDO => LED) = (0:0:0,0:0:0);
@@ -3990,14 +5353,14 @@ module LED ( input PADDO, output LED );
 
 endmodule
 
-module xo2iobuf0111 ( input I, output PAD );
+module xo2iobuf0145 ( input I, output PAD );
 
   OB INST5( .I(I), .O(PAD));
 endmodule
 
 module C14M ( output PADDI, input C14M );
 
-  xo2iobuf0112 C14M_pad( .Z(PADDI), .PAD(C14M));
+  xo2iobuf0146 C14M_pad( .Z(PADDI), .PAD(C14M));
 
   specify
     (C14M => PADDI) = (0:0:0,0:0:0);
@@ -4007,71 +5370,11 @@ module C14M ( output PADDI, input C14M );
 
 endmodule
 
-module xo2iobuf0112 ( output Z, input PAD );
+module xo2iobuf0146 ( output Z, input PAD );
 
   IB INST1( .I(PAD), .O(Z));
 endmodule
 
-module DQMH ( input IOLDO, output DQMH );
-
-  xo2iobuf0111 DQMH_pad( .I(IOLDO), .PAD(DQMH));
-
-  specify
-    (IOLDO => DQMH) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module DQMH_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre DQMH_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module mfflsre ( input D0, SP, CK, LSR, output Q );
-
-  FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module DQML ( input IOLDO, output DQML );
-
-  xo2iobuf0111 DQML_pad( .I(IOLDO), .PAD(DQML));
-
-  specify
-    (IOLDO => DQML) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module DQML_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre DQML_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
 module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
 
   xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
@@ -4170,305 +5473,416 @@ module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
 
 endmodule
 
-module RA_11_ ( input IOLDO, output RA11 );
+module DQMH ( input IOLDO, output DQMH );
 
-  xo2iobuf0111 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));
+  xo2iobuf0145 DQMH_pad( .I(IOLDO), .PAD(DQMH));
 
   specify
-    (IOLDO => RA11) = (0:0:0,0:0:0);
+    (IOLDO => DQMH) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_11__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module DQMH_MGIOL ( output IOLDO, input OPOS, CE, CLK );
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \RA_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre DQMH_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), 
     .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
-module mfflsre0113 ( input D0, SP, CK, LSR, output Q );
+module mfflsre ( input D0, SP, CK, LSR, output Q );
+
+  FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module DQML ( input IOLDO, output DQML );
+
+  xo2iobuf0145 DQML_pad( .I(IOLDO), .PAD(DQML));
+
+  specify
+    (IOLDO => DQML) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module DQML_MGIOL ( output IOLDO, input OPOS, CE, CLK );
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+
+  mfflsre DQML_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), 
+    .Q(IOLDO));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_11_ ( input IOLDO, output RAout11 );
+
+  xo2iobuf0145 \RAout_pad[11] ( .I(IOLDO), .PAD(RAout11));
+
+  specify
+    (IOLDO => RAout11) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_11__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0147 \RAout_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+  endspecify
+
+endmodule
+
+module mfflsre0147 ( input D0, SP, CK, LSR, output Q );
 
   FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module RA_10_ ( input IOLDO, output RA10 );
+module inverter ( input I, output Z );
 
-  xo2iobuf0111 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));
+  INV INST1( .A(I), .Z(Z));
+endmodule
+
+module RAout_10_ ( input IOLDO, output RAout10 );
+
+  xo2iobuf0145 \RAout_pad[10] ( .I(IOLDO), .PAD(RAout10));
 
   specify
-    (IOLDO => RA10) = (0:0:0,0:0:0);
+    (IOLDO => RAout10) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_10__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_10__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0147 \RAout_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_9_ ( input IOLDO, output RA9 );
+module RAout_9_ ( input IOLDO, output RAout9 );
 
-  xo2iobuf0111 \RA_pad[9] ( .I(IOLDO), .PAD(RA9));
+  xo2iobuf0145 \RAout_pad[9] ( .I(IOLDO), .PAD(RAout9));
 
   specify
-    (IOLDO => RA9) = (0:0:0,0:0:0);
+    (IOLDO => RAout9) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_9__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_9__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0147 \RAout_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_8_ ( input IOLDO, output RA8 );
+module RAout_8_ ( input IOLDO, output RAout8 );
 
-  xo2iobuf0111 \RA_pad[8] ( .I(IOLDO), .PAD(RA8));
+  xo2iobuf0145 \RAout_pad[8] ( .I(IOLDO), .PAD(RAout8));
 
   specify
-    (IOLDO => RA8) = (0:0:0,0:0:0);
+    (IOLDO => RAout8) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_8__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_8__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0147 \RAout_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_7_ ( input IOLDO, output RA7 );
+module RAout_7_ ( input IOLDO, output RAout7 );
 
-  xo2iobuf0111 \RA_pad[7] ( .I(IOLDO), .PAD(RA7));
+  xo2iobuf0145 \RAout_pad[7] ( .I(IOLDO), .PAD(RAout7));
 
   specify
-    (IOLDO => RA7) = (0:0:0,0:0:0);
+    (IOLDO => RAout7) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_7__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_6_ ( input IOLDO, output RA6 );
+module RAout_6_ ( input IOLDO, output RAout6 );
 
-  xo2iobuf0111 \RA_pad[6] ( .I(IOLDO), .PAD(RA6));
+  xo2iobuf0145 \RAout_pad[6] ( .I(IOLDO), .PAD(RAout6));
 
   specify
-    (IOLDO => RA6) = (0:0:0,0:0:0);
+    (IOLDO => RAout6) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_6__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_5_ ( input IOLDO, output RA5 );
+module RAout_5_ ( input IOLDO, output RAout5 );
 
-  xo2iobuf0111 \RA_pad[5] ( .I(IOLDO), .PAD(RA5));
+  xo2iobuf0145 \RAout_pad[5] ( .I(IOLDO), .PAD(RAout5));
 
   specify
-    (IOLDO => RA5) = (0:0:0,0:0:0);
+    (IOLDO => RAout5) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_5__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_4_ ( input IOLDO, output RA4 );
+module RAout_4_ ( input IOLDO, output RAout4 );
 
-  xo2iobuf0111 \RA_pad[4] ( .I(IOLDO), .PAD(RA4));
+  xo2iobuf0145 \RAout_pad[4] ( .I(IOLDO), .PAD(RAout4));
 
   specify
-    (IOLDO => RA4) = (0:0:0,0:0:0);
+    (IOLDO => RAout4) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_4__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_3_ ( input PADDO, output RA3 );
+module RAout_3_ ( input IOLDO, output RAout3 );
 
-  xo2iobuf0111 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
+  xo2iobuf0145 \RAout_pad[3] ( .I(IOLDO), .PAD(RAout3));
 
   specify
-    (PADDO => RA3) = (0:0:0,0:0:0);
+    (IOLDO => RAout3) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_2_ ( input IOLDO, output RA2 );
+module RAout_3__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  xo2iobuf0111 \RA_pad[2] ( .I(IOLDO), .PAD(RA2));
-
-  specify
-    (IOLDO => RA2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \RA_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_1_ ( input IOLDO, output RA1 );
+module RAout_2_ ( input IOLDO, output RAout2 );
 
-  xo2iobuf0111 \RA_pad[1] ( .I(IOLDO), .PAD(RA1));
+  xo2iobuf0145 \RAout_pad[2] ( .I(IOLDO), .PAD(RAout2));
 
   specify
-    (IOLDO => RA1) = (0:0:0,0:0:0);
+    (IOLDO => RAout2) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_2__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0113 \RA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0147 \RAout_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_0_ ( input PADDO, output RA0 );
+module RAout_1_ ( input IOLDO, output RAout1 );
 
-  xo2iobuf0111 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
+  xo2iobuf0145 \RAout_pad[1] ( .I(IOLDO), .PAD(RAout1));
 
   specify
-    (PADDO => RA0) = (0:0:0,0:0:0);
+    (IOLDO => RAout1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_1__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0147 \RAout_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+  endspecify
+
+endmodule
+
+module RAout_0_ ( input IOLDO, output RAout0 );
+
+  xo2iobuf0145 \RAout_pad[0] ( .I(IOLDO), .PAD(RAout0));
+
+  specify
+    (IOLDO => RAout0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_0__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0147 \RAout_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
 module BA_1_ ( input IOLDO, output BA1 );
 
-  xo2iobuf0111 \BA_pad[1] ( .I(IOLDO), .PAD(BA1));
+  xo2iobuf0145 \BA_pad[1] ( .I(IOLDO), .PAD(BA1));
 
   specify
     (IOLDO => BA1) = (0:0:0,0:0:0);
@@ -4476,16 +5890,16 @@ module BA_1_ ( input IOLDO, output BA1 );
 
 endmodule
 
-module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
-  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;
+module BA_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK );
+  wire   OPOS_dly, CLK_dly, CE_dly, LSR_dly;
 
-  mfflsre0114 \BA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), 
+  mfflsre0148 \BA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(LSR_dly), .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
@@ -4493,7 +5907,7 @@ module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
 
 endmodule
 
-module mfflsre0114 ( input D0, SP, CK, LSR, output Q );
+module mfflsre0148 ( input D0, SP, CK, LSR, output Q );
 
   FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
@@ -4501,7 +5915,7 @@ endmodule
 
 module BA_0_ ( input IOLDO, output BA0 );
 
-  xo2iobuf0111 \BA_pad[0] ( .I(IOLDO), .PAD(BA0));
+  xo2iobuf0145 \BA_pad[0] ( .I(IOLDO), .PAD(BA0));
 
   specify
     (IOLDO => BA0) = (0:0:0,0:0:0);
@@ -4509,16 +5923,16 @@ module BA_0_ ( input IOLDO, output BA0 );
 
 endmodule
 
-module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
-  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;
+module BA_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK );
+  wire   OPOS_dly, CLK_dly, CE_dly, LSR_dly;
 
-  mfflsre0114 \BA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), 
+  mfflsre0148 \BA_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(LSR_dly), .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
@@ -4526,144 +5940,131 @@ module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
 
 endmodule
 
-module nRWE ( input IOLDO, output nRWE );
+module nRWEout ( input IOLDO, output nRWEout );
 
-  xo2iobuf0111 nRWE_pad( .I(IOLDO), .PAD(nRWE));
+  xo2iobuf0145 nRWEout_pad( .I(IOLDO), .PAD(nRWEout));
 
   specify
-    (IOLDO => nRWE) = (0:0:0,0:0:0);
+    (IOLDO => nRWEout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nRWE_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nRWEout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nRWEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nCAS ( input IOLDO, output nCAS );
+module nCASout ( input IOLDO, output nCASout );
 
-  xo2iobuf0111 nCAS_pad( .I(IOLDO), .PAD(nCAS));
+  xo2iobuf0145 nCASout_pad( .I(IOLDO), .PAD(nCASout));
 
   specify
-    (IOLDO => nCAS) = (0:0:0,0:0:0);
+    (IOLDO => nCASout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nCAS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nCASout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nCASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nRAS ( input IOLDO, output nRAS );
+module nRASout ( input IOLDO, output nRASout );
 
-  xo2iobuf0111 nRAS_pad( .I(IOLDO), .PAD(nRAS));
+  xo2iobuf0145 nRASout_pad( .I(IOLDO), .PAD(nRASout));
 
   specify
-    (IOLDO => nRAS) = (0:0:0,0:0:0);
+    (IOLDO => nRASout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nRAS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nRASout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nRASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nCS ( input IOLDO, output nCS );
+module nCSout ( input PADDO, output nCSout );
 
-  xo2iobuf0111 nCS_pad( .I(IOLDO), .PAD(nCS));
+  xo2iobuf0145 nCSout_pad( .I(PADDO), .PAD(nCSout));
 
   specify
-    (IOLDO => nCS) = (0:0:0,0:0:0);
+    (PADDO => nCSout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nCS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module CKEout ( input IOLDO, output CKEout );
 
-  mfflsre nCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  xo2iobuf0145 CKEout_pad( .I(IOLDO), .PAD(CKEout));
+
+  specify
+    (IOLDO => CKEout) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module CKEout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0147 CKEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module CKE ( input IOLDO, output CKE );
-
-  xo2iobuf0111 CKE_pad( .I(IOLDO), .PAD(CKE));
-
-  specify
-    (IOLDO => CKE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module CKE_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre0113 CKE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
 module nVOE ( input PADDO, output nVOE );
 
-  xo2iobuf0111 nVOE_pad( .I(PADDO), .PAD(nVOE));
+  xo2iobuf0145 nVOE_pad( .I(PADDO), .PAD(nVOE));
 
   specify
     (PADDO => nVOE) = (0:0:0,0:0:0);
@@ -4673,7 +6074,7 @@ endmodule
 
 module Vout_7_ ( input IOLDO, output Vout7 );
 
-  xo2iobuf0111 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7));
+  xo2iobuf0145 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7));
 
   specify
     (IOLDO => Vout7) = (0:0:0,0:0:0);
@@ -4682,31 +6083,25 @@ module Vout_7_ ( input IOLDO, output Vout7 );
 endmodule
 
 module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
-module inverter ( input I, output Z );
-
-  INV INST1( .A(I), .Z(Z));
-endmodule
-
 module Vout_6_ ( input IOLDO, output Vout6 );
 
-  xo2iobuf0111 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6));
+  xo2iobuf0145 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6));
 
   specify
     (IOLDO => Vout6) = (0:0:0,0:0:0);
@@ -4715,26 +6110,25 @@ module Vout_6_ ( input IOLDO, output Vout6 );
 endmodule
 
 module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_5_ ( input IOLDO, output Vout5 );
 
-  xo2iobuf0111 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5));
+  xo2iobuf0145 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5));
 
   specify
     (IOLDO => Vout5) = (0:0:0,0:0:0);
@@ -4743,26 +6137,25 @@ module Vout_5_ ( input IOLDO, output Vout5 );
 endmodule
 
 module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_4_ ( input IOLDO, output Vout4 );
 
-  xo2iobuf0111 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4));
+  xo2iobuf0145 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4));
 
   specify
     (IOLDO => Vout4) = (0:0:0,0:0:0);
@@ -4771,26 +6164,25 @@ module Vout_4_ ( input IOLDO, output Vout4 );
 endmodule
 
 module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_3_ ( input IOLDO, output Vout3 );
 
-  xo2iobuf0111 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3));
+  xo2iobuf0145 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3));
 
   specify
     (IOLDO => Vout3) = (0:0:0,0:0:0);
@@ -4799,26 +6191,25 @@ module Vout_3_ ( input IOLDO, output Vout3 );
 endmodule
 
 module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_2_ ( input IOLDO, output Vout2 );
 
-  xo2iobuf0111 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2));
+  xo2iobuf0145 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2));
 
   specify
     (IOLDO => Vout2) = (0:0:0,0:0:0);
@@ -4827,26 +6218,25 @@ module Vout_2_ ( input IOLDO, output Vout2 );
 endmodule
 
 module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_1_ ( input IOLDO, output Vout1 );
 
-  xo2iobuf0111 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1));
+  xo2iobuf0145 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1));
 
   specify
     (IOLDO => Vout1) = (0:0:0,0:0:0);
@@ -4855,26 +6245,25 @@ module Vout_1_ ( input IOLDO, output Vout1 );
 endmodule
 
 module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_0_ ( input IOLDO, output Vout0 );
 
-  xo2iobuf0111 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0));
+  xo2iobuf0145 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0));
 
   specify
     (IOLDO => Vout0) = (0:0:0,0:0:0);
@@ -4883,26 +6272,25 @@ module Vout_0_ ( input IOLDO, output Vout0 );
 endmodule
 
 module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0113 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0147 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module nDOE ( input PADDO, output nDOE );
 
-  xo2iobuf0111 nDOE_pad( .I(PADDO), .PAD(nDOE));
+  xo2iobuf0145 nDOE_pad( .I(PADDO), .PAD(nDOE));
 
   specify
     (PADDO => nDOE) = (0:0:0,0:0:0);
@@ -4910,238 +6298,89 @@ module nDOE ( input PADDO, output nDOE );
 
 endmodule
 
-module Dout_7_ ( input IOLDO, output Dout7 );
+module Dout_7_ ( input PADDO, output Dout7 );
 
-  xo2iobuf0115 \Dout_pad[7] ( .I(IOLDO), .PAD(Dout7));
+  xo2iobuf0145 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
 
   specify
-    (IOLDO => Dout7) = (0:0:0,0:0:0);
+    (PADDO => Dout7) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module xo2iobuf0115 ( input I, output PAD );
+module Dout_6_ ( input PADDO, output Dout6 );
 
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module Dout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \Dout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0145 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout6) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_6_ ( input IOLDO, output Dout6 );
+module Dout_5_ ( input PADDO, output Dout5 );
 
-  xo2iobuf0115 \Dout_pad[6] ( .I(IOLDO), .PAD(Dout6));
+  xo2iobuf0145 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
 
   specify
-    (IOLDO => Dout6) = (0:0:0,0:0:0);
+    (PADDO => Dout5) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_4_ ( input PADDO, output Dout4 );
 
-  mfflsre0113 \Dout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0145 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout4) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_5_ ( input IOLDO, output Dout5 );
+module Dout_3_ ( input PADDO, output Dout3 );
 
-  xo2iobuf0115 \Dout_pad[5] ( .I(IOLDO), .PAD(Dout5));
+  xo2iobuf0145 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
 
   specify
-    (IOLDO => Dout5) = (0:0:0,0:0:0);
+    (PADDO => Dout3) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_2_ ( input PADDO, output Dout2 );
 
-  mfflsre0113 \Dout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0145 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout2) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_4_ ( input IOLDO, output Dout4 );
+module Dout_1_ ( input PADDO, output Dout1 );
 
-  xo2iobuf0115 \Dout_pad[4] ( .I(IOLDO), .PAD(Dout4));
+  xo2iobuf0145 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
 
   specify
-    (IOLDO => Dout4) = (0:0:0,0:0:0);
+    (PADDO => Dout1) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_0_ ( input PADDO, output Dout0 );
 
-  mfflsre0113 \Dout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0145 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_3_ ( input IOLDO, output Dout3 );
-
-  xo2iobuf0115 \Dout_pad[3] ( .I(IOLDO), .PAD(Dout3));
-
-  specify
-    (IOLDO => Dout3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \Dout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_2_ ( input IOLDO, output Dout2 );
-
-  xo2iobuf0115 \Dout_pad[2] ( .I(IOLDO), .PAD(Dout2));
-
-  specify
-    (IOLDO => Dout2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \Dout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_1_ ( input IOLDO, output Dout1 );
-
-  xo2iobuf0115 \Dout_pad[1] ( .I(IOLDO), .PAD(Dout1));
-
-  specify
-    (IOLDO => Dout1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \Dout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_0_ ( input IOLDO, output Dout0 );
-
-  xo2iobuf0115 \Dout_pad[0] ( .I(IOLDO), .PAD(Dout0));
-
-  specify
-    (IOLDO => Dout0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0113 \Dout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module Din_7_ ( output PADDI, input Din7 );
 
-  xo2iobuf0112 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
+  xo2iobuf0146 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
 
   specify
     (Din7 => PADDI) = (0:0:0,0:0:0);
@@ -5153,7 +6392,7 @@ endmodule
 
 module Din_6_ ( output PADDI, input Din6 );
 
-  xo2iobuf0112 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
+  xo2iobuf0146 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
 
   specify
     (Din6 => PADDI) = (0:0:0,0:0:0);
@@ -5165,7 +6404,7 @@ endmodule
 
 module Din_5_ ( output PADDI, input Din5 );
 
-  xo2iobuf0112 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
+  xo2iobuf0146 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
 
   specify
     (Din5 => PADDI) = (0:0:0,0:0:0);
@@ -5177,7 +6416,7 @@ endmodule
 
 module Din_4_ ( output PADDI, input Din4 );
 
-  xo2iobuf0112 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
+  xo2iobuf0146 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
 
   specify
     (Din4 => PADDI) = (0:0:0,0:0:0);
@@ -5189,7 +6428,7 @@ endmodule
 
 module Din_3_ ( output PADDI, input Din3 );
 
-  xo2iobuf0112 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
+  xo2iobuf0146 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
 
   specify
     (Din3 => PADDI) = (0:0:0,0:0:0);
@@ -5201,7 +6440,7 @@ endmodule
 
 module Din_2_ ( output PADDI, input Din2 );
 
-  xo2iobuf0112 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
+  xo2iobuf0146 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
 
   specify
     (Din2 => PADDI) = (0:0:0,0:0:0);
@@ -5213,7 +6452,7 @@ endmodule
 
 module Din_1_ ( output PADDI, input Din1 );
 
-  xo2iobuf0112 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
+  xo2iobuf0146 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
 
   specify
     (Din1 => PADDI) = (0:0:0,0:0:0);
@@ -5225,7 +6464,7 @@ endmodule
 
 module Din_0_ ( output PADDI, input Din0 );
 
-  xo2iobuf0112 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
+  xo2iobuf0146 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
 
   specify
     (Din0 => PADDI) = (0:0:0,0:0:0);
@@ -5237,7 +6476,7 @@ endmodule
 
 module Ain_7_ ( output PADDI, input Ain7 );
 
-  xo2iobuf0112 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7));
+  xo2iobuf0146 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7));
 
   specify
     (Ain7 => PADDI) = (0:0:0,0:0:0);
@@ -5249,7 +6488,7 @@ endmodule
 
 module Ain_6_ ( output PADDI, input Ain6 );
 
-  xo2iobuf0112 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6));
+  xo2iobuf0146 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6));
 
   specify
     (Ain6 => PADDI) = (0:0:0,0:0:0);
@@ -5261,7 +6500,7 @@ endmodule
 
 module Ain_5_ ( output PADDI, input Ain5 );
 
-  xo2iobuf0112 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5));
+  xo2iobuf0146 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5));
 
   specify
     (Ain5 => PADDI) = (0:0:0,0:0:0);
@@ -5273,7 +6512,7 @@ endmodule
 
 module Ain_4_ ( output PADDI, input Ain4 );
 
-  xo2iobuf0112 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4));
+  xo2iobuf0146 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4));
 
   specify
     (Ain4 => PADDI) = (0:0:0,0:0:0);
@@ -5285,7 +6524,7 @@ endmodule
 
 module Ain_3_ ( output PADDI, input Ain3 );
 
-  xo2iobuf0112 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3));
+  xo2iobuf0146 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3));
 
   specify
     (Ain3 => PADDI) = (0:0:0,0:0:0);
@@ -5297,7 +6536,7 @@ endmodule
 
 module Ain_2_ ( output PADDI, input Ain2 );
 
-  xo2iobuf0112 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2));
+  xo2iobuf0146 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2));
 
   specify
     (Ain2 => PADDI) = (0:0:0,0:0:0);
@@ -5309,7 +6548,7 @@ endmodule
 
 module Ain_1_ ( output PADDI, input Ain1 );
 
-  xo2iobuf0112 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1));
+  xo2iobuf0146 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1));
 
   specify
     (Ain1 => PADDI) = (0:0:0,0:0:0);
@@ -5321,7 +6560,7 @@ endmodule
 
 module Ain_0_ ( output PADDI, input Ain0 );
 
-  xo2iobuf0112 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0));
+  xo2iobuf0146 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0));
 
   specify
     (Ain0 => PADDI) = (0:0:0,0:0:0);
@@ -5333,7 +6572,7 @@ endmodule
 
 module nC07X ( output PADDI, input nC07X );
 
-  xo2iobuf0112 nC07X_pad( .Z(PADDI), .PAD(nC07X));
+  xo2iobuf0146 nC07X_pad( .Z(PADDI), .PAD(nC07X));
 
   specify
     (nC07X => PADDI) = (0:0:0,0:0:0);
@@ -5345,7 +6584,7 @@ endmodule
 
 module nEN80 ( output PADDI, input nEN80 );
 
-  xo2iobuf0112 nEN80_pad( .Z(PADDI), .PAD(nEN80));
+  xo2iobuf0146 nEN80_pad( .Z(PADDI), .PAD(nEN80));
 
   specify
     (nEN80 => PADDI) = (0:0:0,0:0:0);
@@ -5355,21 +6594,9 @@ module nEN80 ( output PADDI, input nEN80 );
 
 endmodule
 
-module nWE80 ( output PADDI, input nWE80 );
-
-  xo2iobuf0112 nWE80_pad( .Z(PADDI), .PAD(nWE80));
-
-  specify
-    (nWE80 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nWE80, 0:0:0);
-    $width (negedge nWE80, 0:0:0);
-  endspecify
-
-endmodule
-
 module nWE ( output PADDI, input nWE );
 
-  xo2iobuf0112 nWE_pad( .Z(PADDI), .PAD(nWE));
+  xo2iobuf0146 nWE_pad( .Z(PADDI), .PAD(nWE));
 
   specify
     (nWE => PADDI) = (0:0:0,0:0:0);
@@ -5381,7 +6608,7 @@ endmodule
 
 module PHI1 ( output PADDI, input PHI1 );
 
-  xo2iobuf0112 PHI1_pad( .Z(PADDI), .PAD(PHI1));
+  xo2iobuf0146 PHI1_pad( .Z(PADDI), .PAD(PHI1));
 
   specify
     (PHI1 => PADDI) = (0:0:0,0:0:0);
@@ -5394,7 +6621,7 @@ endmodule
 module PHI1_MGIOL ( input DI, CLK, output IN );
   wire   VCCI, GNDI, DI_dly, CLK_dly;
 
-  smuxlregsre PHI1reg_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  smuxlregsre PHI1r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
     .Q(IN));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
@@ -5414,14 +6641,14 @@ module smuxlregsre ( input D0, SP, CK, LSR, output Q );
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, 
-    WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, 
-    WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output 
-    WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, 
-    WBACKO );
+module ram2e_ufm_ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, 
+    WBWEI, WBADRI0, WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, 
+    WBADRI7, WBDATI0, WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, 
+    WBDATI7, output WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, 
+    WBDATO6, WBDATO7, WBACKO );
   wire   VCCI, GNDI;
 
-  EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), 
+  EFB_B \ram2e_ufm/ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), 
     .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), 
     .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), 
     .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html
index 506e8ec..83ff24e 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html
@@ -16,30 +16,30 @@
 Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
      RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
      RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
-     loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
-     lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
-     //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml 
+     loud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
+     lpf -lpf //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
+     //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml 
 Target Vendor:  LATTICE
 Target Device:  LCMXO2-640HCTQFP100
 Target Performance:   4
 Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  09/21/23  05:34:46
+Mapped on:  12/28/23  23:09:57
 
 
 <A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
-   Number of registers:    111 out of   877 (13%)
-      PFU registers:           75 out of   640 (12%)
-      PIO registers:           36 out of   237 (15%)
-   Number of SLICEs:       120 out of   320 (38%)
-      SLICEs as Logic/ROM:    120 out of   320 (38%)
+   Number of registers:    122 out of   877 (14%)
+      PFU registers:           93 out of   640 (15%)
+      PIO registers:           29 out of   237 (12%)
+   Number of SLICEs:       148 out of   320 (46%)
+      SLICEs as Logic/ROM:    148 out of   320 (46%)
       SLICEs as RAM:            0 out of   240 (0%)
       SLICEs as Carry:          9 out of   320 (3%)
-   Number of LUT4s:        239 out of   640 (37%)
-      Number used as logic LUTs:        221
+   Number of LUT4s:        296 out of   640 (46%)
+      Number used as logic LUTs:        278
       Number used as distributed RAM:     0
       Number used as ripple logic:       18
       Number used as shift registers:     0
-   Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%)
+   Number of PIO sites used: 69 + 4(JTAG) out of 79 (92%)
    Number of block RAMs:  0 out of 2 (0%)
    Number of GSRs:        0 out of 1 (0%)
    EFB used :        Yes
@@ -59,43 +59,48 @@ Mapped on:  09/21/23  05:34:46
       2. Number of logic LUT4s does not include count of distributed RAM and
      ripple logic.
    Number of clocks:  1
-     Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
-   Number of Clock Enables:  11
-     Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
-     Net N_576_i: 17 loads, 9 LSLICEs
-     Net LEDEN13: 4 loads, 4 LSLICEs
-     Net nCS61: 1 loads, 1 LSLICEs
-     Net Vout3: 8 loads, 0 LSLICEs
-     Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
+     Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M )
+   Number of Clock Enables:  14
+     Net N_225_i: 2 loads, 0 LSLICEs
+     Net N_201_i: 2 loads, 0 LSLICEs
+     Net N_187_i: 11 loads, 11 LSLICEs
+     Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
+     Net RC12: 2 loads, 2 LSLICEs
+     Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs
 
-     Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
-     Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
-     Net N_104: 1 loads, 1 LSLICEs
-     Net N_88: 4 loads, 4 LSLICEs
-     Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
-   Number of LSRs:  5
+     Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs
+     Net N_185_i: 2 loads, 2 LSLICEs
+     Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs
+     Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs
+     Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs
+     Net N_126: 6 loads, 6 LSLICEs
+     Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs
+     Net Vout3: 8 loads, 0 LSLICEs
+   Number of LSRs:  7
      Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
+     Net BA_0_sqmuxa: 2 loads, 0 LSLICEs
      Net S[2]: 1 loads, 1 LSLICEs
-     Net N_566_i: 2 loads, 0 LSLICEs
-     Net wb_rst: 1 loads, 0 LSLICEs
-     Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
+     Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
+     Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs
+     Net N_1080_0: 1 loads, 1 LSLICEs
+     Net N_1078_0: 1 loads, 1 LSLICEs
    Number of nets driven by tri-state buffers:  0
    Top 10 highest fanout non-clock nets:
-     Net S[2]: 48 loads
-     Net S[3]: 48 loads
-     Net S[0]: 30 loads
-     Net FS[12]: 22 loads
-     Net FS[9]: 21 loads
-     Net S[1]: 21 loads
-     Net FS[10]: 20 loads
-     Net FS[11]: 19 loads
-     Net RWSel: 19 loads
-     Net FS[13]: 17 loads
+     Net S[2]: 50 loads
+     Net S[3]: 45 loads
+     Net S[0]: 37 loads
+     Net S[1]: 34 loads
+     Net FS[12]: 24 loads
+     Net FS[11]: 22 loads
+     Net FS[10]: 19 loads
+     Net FS[13]: 19 loads
+     Net FS[9]: 19 loads
+     Net FS[8]: 18 loads
 
 
 
 
-   Number of warnings:  1
+   Number of warnings:  3
    Number of errors:    0
      
 
@@ -104,12 +109,17 @@ Mapped on:  09/21/23  05:34:46
 
 <A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
 
+WARNING - map: //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf(93): Semantic
+     error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
+     "nWE80" does not exist in the design. This preference has been disabled.
 WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
      temporarily disable certain features of the device including Power
      Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
      Functionality is restored after the Flash Memory (UFM/Configuration)
      Interface is disabled using Disable Configuration Interface command 0x26
      followed by Bypass command 0xFF. 
+WARNING - map: IO buffer missing for top level port nWE80...logic will be
+     discarded.
 
 
 
@@ -117,6 +127,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 
 +---------------------+-----------+-----------+------------+
 | IO Name             | Direction | Levelmode | IO         |
+
 |                     |           |  IO_TYPE  | Register   |
 +---------------------+-----------+-----------+------------+
 | RD[0]               | BIDIR     | LVCMOS33  |            |
@@ -125,11 +136,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | C14M                | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-
-| DQML                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
 | RD[7]               | BIDIR     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | RD[6]               | BIDIR     | LVCMOS33  |            |
@@ -144,47 +150,51 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | RD[1]               | BIDIR     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| RA[11]              | OUTPUT    | LVCMOS33  | OUT        |
+| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[10]              | OUTPUT    | LVCMOS33  | OUT        |
+| DQML                | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[9]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[11]           | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[8]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[10]           | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[7]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[9]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[6]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[8]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[5]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[7]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[4]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[6]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[3]               | OUTPUT    | LVCMOS33  |            |
+| RAout[5]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[2]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[4]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[1]               | OUTPUT    | LVCMOS33  | OUT        |
+| RAout[3]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| RA[0]               | OUTPUT    | LVCMOS33  |            |
+| RAout[2]            | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RAout[1]            | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RAout[0]            | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | BA[1]               | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | BA[0]               | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| nRWE                | OUTPUT    | LVCMOS33  | OUT        |
+| nRWEout             | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| nCAS                | OUTPUT    | LVCMOS33  | OUT        |
+
+| nCASout             | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| nRAS                | OUTPUT    | LVCMOS33  | OUT        |
+| nRASout             | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
-| nCS                 | OUTPUT    | LVCMOS33  | OUT        |
+| nCSout              | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| CKE                 | OUTPUT    | LVCMOS33  | OUT        |
+| CKEout              | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | nVOE                | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-
 | Vout[7]             | OUTPUT    | LVCMOS33  | OUT        |
 +---------------------+-----------+-----------+------------+
 | Vout[6]             | OUTPUT    | LVCMOS33  | OUT        |
@@ -203,21 +213,21 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | nDOE                | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[7]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[7]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[6]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[6]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[5]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[5]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[4]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[4]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[3]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[3]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[2]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[2]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[1]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[1]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| Dout[0]             | OUTPUT    | LVCMOS33  | OUT        |
+| Dout[0]             | OUTPUT    | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Din[7]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
@@ -231,6 +241,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | Din[2]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
+
 | Din[1]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Din[0]              | INPUT     | LVCMOS33  |            |
@@ -241,7 +252,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | Ain[5]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-
 | Ain[4]              | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | Ain[3]              | INPUT     | LVCMOS33  |            |
@@ -256,8 +266,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 +---------------------+-----------+-----------+------------+
 | nEN80               | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
-| nWE80               | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
 | nWE                 | INPUT     | LVCMOS33  |            |
 +---------------------+-----------+-----------+------------+
 | PHI1                | INPUT     | LVCMOS33  | IN         |
@@ -268,68 +276,75 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
 <A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
 
 Block GSR_INST undriven or does not drive anything - clipped.
-Signal Dout_0_.CN was merged into signal C14M_c
-Signal GND undriven or does not drive anything - clipped.
-Signal ufmefb/VCC undriven or does not drive anything - clipped.
-Signal ufmefb/GND undriven or does not drive anything - clipped.
+Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
+Block ram2e_ufm/GND undriven or does not drive anything - clipped.
+Signal CKEout.CN was merged into signal C14M_c
+Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
 Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
 Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
-Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
-Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
-Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
-Signal ufmefb/TCOC undriven or does not drive anything - clipped.
-Signal ufmefb/TCINT undriven or does not drive anything - clipped.
-Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
-Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
-Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
-Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
 
-Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
-Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
-Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
-Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
-Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
-Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
+     
+Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
+     
+Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
+     clipped.
+Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
+Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
 Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
 Signal N_1 undriven or does not drive anything - clipped.
-Block Vout_0_.CN was optimized away.
-Block GND was optimized away.
-Block ufmefb/VCC was optimized away.
-Block ufmefb/GND was optimized away.
+Block nCASout.CN was optimized away.
+Block ram2e_ufm/ufmefb/VCC was optimized away.
+Block ram2e_ufm/ufmefb/GND was optimized away.
 
      
 
@@ -339,9 +354,10 @@ Block ufmefb/GND was optimized away.
 
    Desired WISHBONE clock frequency: 14.4 MHz
    Clock source:                     C14M_c
-   Reset source:                     wb_rst
+   Reset source:                     ram2e_ufm/wb_rst
    Functions mode:
       I2C #1 (Primary) Function:     DISABLED
+
       I2C #2 (Secondary) Function:   DISABLED
       SPI Function:                  DISABLED
       Timer/Counter Function:        DISABLED
@@ -357,7 +373,6 @@ Block ufmefb/GND was optimized away.
       None
    Timer/Counter Function Summary:
    ------------------------------
-
       None
    UFM Function Summary:
    --------------------
@@ -378,7 +393,7 @@ Block ufmefb/GND was optimized away.
 <A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
 ---------------
 
-Instance Name: ufmefb/EFBInst_0
+Instance Name: ram2e_ufm/ufmefb/EFBInst_0
          Type: EFB
 
 
@@ -388,7 +403,7 @@ Instance Name: ufmefb/EFBInst_0
 
    Total CPU Time: 0 secs  
    Total REAL Time: 0 secs  
-   Peak Memory Usage: 58 MB
+   Peak Memory Usage: 59 MB
         
 
 
@@ -400,21 +415,6 @@ Instance Name: ufmefb/EFBInst_0
 
 
 
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
 
 
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html
index 64c8bcb..330925e 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html
@@ -14,7 +14,7 @@ Performance Grade:      4
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.39
 
-Thu Sep 21 05:35:00 2023
+Thu Dec 28 23:10:10 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -31,7 +31,7 @@ Pinout by Port Name:
 | BA[0]     | 58/1     | LVCMOS33_OUT  | PR6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | BA[1]     | 60/1     | LVCMOS33_OUT  | PR6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | C14M      | 62/1     | LVCMOS33_IN   | PR5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| CKE       | 53/1     | LVCMOS33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| CKEout    | 53/1     | LVCMOS33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | DQMH      | 49/2     | LVCMOS33_OUT  | PB14D |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | DQML      | 48/2     | LVCMOS33_OUT  | PB14C |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | Din[0]    | 96/0     | LVCMOS33_IN   | PT6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
@@ -42,28 +42,28 @@ Pinout by Port Name:
 | Din[5]    | 99/0     | LVCMOS33_IN   | PT6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 | Din[6]    | 88/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 | Din[7]    | 87/0     | LVCMOS33_IN   | PT9B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4A  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL7D  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4B  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL7C  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL7B  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6A  |           |           | DRIVE:4mA SLEW:FAST                                        |
-| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | LED       | 35/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | PHI1      | 85/0     | LVCMOS33_IN   | PT9D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| RA[0]     | 66/1     | LVCMOS33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[10]    | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[11]    | 59/1     | LVCMOS33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[1]     | 68/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[2]     | 70/1     | LVCMOS33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[3]     | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[4]     | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[5]     | 71/1     | LVCMOS33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[6]     | 69/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[7]     | 67/1     | LVCMOS33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[8]     | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RA[9]     | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[0]  | 66/1     | LVCMOS33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[10] | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[11] | 59/1     | LVCMOS33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[1]  | 68/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[2]  | 70/1     | LVCMOS33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[3]  | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[4]  | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[5]  | 71/1     | LVCMOS33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[6]  | 69/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[7]  | 67/1     | LVCMOS33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[8]  | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RAout[9]  | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | RD[0]     | 36/2     | LVCMOS33_BIDI | PB10A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[1]     | 37/2     | LVCMOS33_BIDI | PB10B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
 | RD[2]     | 38/2     | LVCMOS33_BIDI | PB10C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
@@ -81,15 +81,14 @@ Pinout by Port Name:
 | Vout[6]   | 14/3     | LVCMOS33_OUT  | PL5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | Vout[7]   | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nC07X     | 34/2     | LVCMOS33_IN   | PB6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nCAS      | 52/1     | LVCMOS33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nCS       | 57/1     | LVCMOS33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nCASout   | 52/1     | LVCMOS33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nCSout    | 57/1     | LVCMOS33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nDOE      | 20/3     | LVCMOS33_OUT  | PL7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nEN80     | 82/0     | LVCMOS33_IN   | PT10C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nRAS      | 54/1     | LVCMOS33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nRWE      | 51/1     | LVCMOS33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRASout   | 54/1     | LVCMOS33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWEout   | 51/1     | LVCMOS33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nVOE      | 10/3     | LVCMOS33_OUT  | PL3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
 | nWE       | 29/2     | LVCMOS33_IN   | PB4C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nWE80     | 83/0     | LVCMOS33_IN   | PT10B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
 +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
 
 Vccio by Bank:
@@ -153,32 +152,32 @@ Vccio by Bank:
 | 47/2     |     unused, PULL:DOWN |            |               | PB14B |               |           |           |
 | 48/2     | DQML                  | LOCATED    | LVCMOS33_OUT  | PB14C | SN            |           |           |
 | 49/2     | DQMH                  | LOCATED    | LVCMOS33_OUT  | PB14D | SI/SISPI      |           |           |
-| 51/1     | nRWE                  | LOCATED    | LVCMOS33_OUT  | PR7D  |               |           |           |
-| 52/1     | nCAS                  | LOCATED    | LVCMOS33_OUT  | PR7C  |               |           |           |
-| 53/1     | CKE                   | LOCATED    | LVCMOS33_OUT  | PR7B  |               |           |           |
-| 54/1     | nRAS                  | LOCATED    | LVCMOS33_OUT  | PR7A  |               |           |           |
-| 57/1     | nCS                   | LOCATED    | LVCMOS33_OUT  | PR6D  |               |           |           |
+| 51/1     | nRWEout               | LOCATED    | LVCMOS33_OUT  | PR7D  |               |           |           |
+| 52/1     | nCASout               | LOCATED    | LVCMOS33_OUT  | PR7C  |               |           |           |
+| 53/1     | CKEout                | LOCATED    | LVCMOS33_OUT  | PR7B  |               |           |           |
+| 54/1     | nRASout               | LOCATED    | LVCMOS33_OUT  | PR7A  |               |           |           |
+| 57/1     | nCSout                | LOCATED    | LVCMOS33_OUT  | PR6D  |               |           |           |
 | 58/1     | BA[0]                 | LOCATED    | LVCMOS33_OUT  | PR6C  |               |           |           |
-| 59/1     | RA[11]                | LOCATED    | LVCMOS33_OUT  | PR6B  |               |           |           |
+| 59/1     | RAout[11]             | LOCATED    | LVCMOS33_OUT  | PR6B  |               |           |           |
 | 60/1     | BA[1]                 | LOCATED    | LVCMOS33_OUT  | PR6A  |               |           |           |
 | 62/1     | C14M                  | LOCATED    | LVCMOS33_IN   | PR5D  | PCLKC1_0      |           |           |
-| 63/1     | RA[9]                 | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0      |           |           |
-| 64/1     | RA[10]                | LOCATED    | LVCMOS33_OUT  | PR5B  |               |           |           |
-| 65/1     | RA[8]                 | LOCATED    | LVCMOS33_OUT  | PR5A  |               |           |           |
-| 66/1     | RA[0]                 | LOCATED    | LVCMOS33_OUT  | PR3D  |               |           |           |
-| 67/1     | RA[7]                 | LOCATED    | LVCMOS33_OUT  | PR3C  |               |           |           |
-| 68/1     | RA[1]                 | LOCATED    | LVCMOS33_OUT  | PR3B  |               |           |           |
-| 69/1     | RA[6]                 | LOCATED    | LVCMOS33_OUT  | PR3A  |               |           |           |
-| 70/1     | RA[2]                 | LOCATED    | LVCMOS33_OUT  | PR2D  |               |           |           |
-| 71/1     | RA[5]                 | LOCATED    | LVCMOS33_OUT  | PR2C  |               |           |           |
-| 74/1     | RA[3]                 | LOCATED    | LVCMOS33_OUT  | PR2B  |               |           |           |
-| 75/1     | RA[4]                 | LOCATED    | LVCMOS33_OUT  | PR2A  |               |           |           |
+| 63/1     | RAout[9]              | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0      |           |           |
+| 64/1     | RAout[10]             | LOCATED    | LVCMOS33_OUT  | PR5B  |               |           |           |
+| 65/1     | RAout[8]              | LOCATED    | LVCMOS33_OUT  | PR5A  |               |           |           |
+| 66/1     | RAout[0]              | LOCATED    | LVCMOS33_OUT  | PR3D  |               |           |           |
+| 67/1     | RAout[7]              | LOCATED    | LVCMOS33_OUT  | PR3C  |               |           |           |
+| 68/1     | RAout[1]              | LOCATED    | LVCMOS33_OUT  | PR3B  |               |           |           |
+| 69/1     | RAout[6]              | LOCATED    | LVCMOS33_OUT  | PR3A  |               |           |           |
+| 70/1     | RAout[2]              | LOCATED    | LVCMOS33_OUT  | PR2D  |               |           |           |
+| 71/1     | RAout[5]              | LOCATED    | LVCMOS33_OUT  | PR2C  |               |           |           |
+| 74/1     | RAout[3]              | LOCATED    | LVCMOS33_OUT  | PR2B  |               |           |           |
+| 75/1     | RAout[4]              | LOCATED    | LVCMOS33_OUT  | PR2A  |               |           |           |
 | 76/0     |     unused, PULL:DOWN |            |               | PT11D | DONE          |           |           |
 | 77/0     |     unused, PULL:DOWN |            |               | PT11C | INITN         |           |           |
 | 78/0     | Ain[4]                | LOCATED    | LVCMOS33_IN   | PT11A |               |           |           |
 | 81/0     |     unused, PULL:DOWN |            |               | PT10D | PROGRAMN      |           |           |
 | 82/0     | nEN80                 | LOCATED    | LVCMOS33_IN   | PT10C | JTAGENB       |           |           |
-| 83/0     | nWE80                 | LOCATED    | LVCMOS33_IN   | PT10B |               |           |           |
+| 83/0     |     unused, PULL:DOWN |            |               | PT10B |               |           |           |
 | 84/0     | Ain[5]                | LOCATED    | LVCMOS33_IN   | PT10A |               |           |           |
 | 85/0     | PHI1                  | LOCATED    | LVCMOS33_IN   | PT9D  | SDA/PCLKC0_0  |           |           |
 | 86/0     | Ain[6]                | LOCATED    | LVCMOS33_IN   | PT9C  | SCL/PCLKT0_0  |           |           |
@@ -222,7 +221,7 @@ LOCATE  COMP  "Ain[7]"  SITE  "8";
 LOCATE  COMP  "BA[0]"  SITE  "58";
 LOCATE  COMP  "BA[1]"  SITE  "60";
 LOCATE  COMP  "C14M"  SITE  "62";
-LOCATE  COMP  "CKE"  SITE  "53";
+LOCATE  COMP  "CKEout"  SITE  "53";
 LOCATE  COMP  "DQMH"  SITE  "49";
 LOCATE  COMP  "DQML"  SITE  "48";
 LOCATE  COMP  "Din[0]"  SITE  "96";
@@ -243,18 +242,18 @@ LOCATE  COMP  "Dout[6]"  SITE  "31";
 LOCATE  COMP  "Dout[7]"  SITE  "32";
 LOCATE  COMP  "LED"  SITE  "35";
 LOCATE  COMP  "PHI1"  SITE  "85";
-LOCATE  COMP  "RA[0]"  SITE  "66";
-LOCATE  COMP  "RA[10]"  SITE  "64";
-LOCATE  COMP  "RA[11]"  SITE  "59";
-LOCATE  COMP  "RA[1]"  SITE  "68";
-LOCATE  COMP  "RA[2]"  SITE  "70";
-LOCATE  COMP  "RA[3]"  SITE  "74";
-LOCATE  COMP  "RA[4]"  SITE  "75";
-LOCATE  COMP  "RA[5]"  SITE  "71";
-LOCATE  COMP  "RA[6]"  SITE  "69";
-LOCATE  COMP  "RA[7]"  SITE  "67";
-LOCATE  COMP  "RA[8]"  SITE  "65";
-LOCATE  COMP  "RA[9]"  SITE  "63";
+LOCATE  COMP  "RAout[0]"  SITE  "66";
+LOCATE  COMP  "RAout[10]"  SITE  "64";
+LOCATE  COMP  "RAout[11]"  SITE  "59";
+LOCATE  COMP  "RAout[1]"  SITE  "68";
+LOCATE  COMP  "RAout[2]"  SITE  "70";
+LOCATE  COMP  "RAout[3]"  SITE  "74";
+LOCATE  COMP  "RAout[4]"  SITE  "75";
+LOCATE  COMP  "RAout[5]"  SITE  "71";
+LOCATE  COMP  "RAout[6]"  SITE  "69";
+LOCATE  COMP  "RAout[7]"  SITE  "67";
+LOCATE  COMP  "RAout[8]"  SITE  "65";
+LOCATE  COMP  "RAout[9]"  SITE  "63";
 LOCATE  COMP  "RD[0]"  SITE  "36";
 LOCATE  COMP  "RD[1]"  SITE  "37";
 LOCATE  COMP  "RD[2]"  SITE  "38";
@@ -272,15 +271,14 @@ LOCATE  COMP  "Vout[5]"  SITE  "16";
 LOCATE  COMP  "Vout[6]"  SITE  "14";
 LOCATE  COMP  "Vout[7]"  SITE  "12";
 LOCATE  COMP  "nC07X"  SITE  "34";
-LOCATE  COMP  "nCAS"  SITE  "52";
-LOCATE  COMP  "nCS"  SITE  "57";
+LOCATE  COMP  "nCASout"  SITE  "52";
+LOCATE  COMP  "nCSout"  SITE  "57";
 LOCATE  COMP  "nDOE"  SITE  "20";
 LOCATE  COMP  "nEN80"  SITE  "82";
-LOCATE  COMP  "nRAS"  SITE  "54";
-LOCATE  COMP  "nRWE"  SITE  "51";
+LOCATE  COMP  "nRASout"  SITE  "54";
+LOCATE  COMP  "nRWEout"  SITE  "51";
 LOCATE  COMP  "nVOE"  SITE  "10";
 LOCATE  COMP  "nWE"  SITE  "29";
-LOCATE  COMP  "nWE80"  SITE  "83";
 
 
 
@@ -292,7 +290,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Sep 21 05:35:04 2023
+Thu Dec 28 23:10:13 2023
 
 
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html
index 1dd7442..e121eb7 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html
@@ -12,12 +12,12 @@ Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Sep 21 05:34:51 2023
+Thu Dec 28 23:10:01 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
 RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
 RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset
-//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
+//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml
 
 
 Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
@@ -26,7 +26,7 @@ Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            57.366       0            0.346        0            15           Completed
+5_1   *      0            57.938       0            0.379        0            15           Completed
 * : Design saved.
 
 Total (real) run time for 1-seed: 15 secs 
@@ -36,12 +36,12 @@ par done!
 Note: user must run &apos;Trace&apos; for timing closure signoff.
 
 Lattice Place and Route Report for Design &quot;RAM2E_LCMXO2_640HC_impl1_map.ncd&quot;
-Thu Sep 21 05:34:51 2023
+Thu Dec 28 23:10:01 2023
 
 
 <A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
 PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
 Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
 Placement level-cost: 5-1.
 Routing Iterations: 6
@@ -63,43 +63,43 @@ Ignore Preference Error(s):  True
 
 <A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
 
-   PIO (prelim)   70+4(JTAG)/80      93% used
-                  70+4(JTAG)/79      94% bonded
-   IOLOGIC           36/80           45% used
+   PIO (prelim)   69+4(JTAG)/80      91% used
+                  69+4(JTAG)/79      92% bonded
+   IOLOGIC           29/80           36% used
 
-   SLICE            120/320          37% used
+   SLICE            148/320          46% used
 
    EFB                1/1           100% used
 
 
-Number of Signals: 395
-Number of Connections: 1126
+Number of Signals: 459
+Number of Connections: 1330
 
 Pin Constraint Summary:
-   70 out of 70 pins locked (100% locked).
+   69 out of 69 pins locked (100% locked).
 
 The following 1 signal is selected to use the primary clock routing resources:
-    C14M_c (driver: C14M, clk load #: 84)
+    C14M_c (driver: C14M, clk load #: 89)
 
 WARNING - par: Signal &quot;C14M_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;C14M&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
 
 The following 1 signal is selected to use the secondary clock routing resources:
-    N_576_i (driver: SLICE_20, clk load #: 0, sr load #: 0, ce load #: 17)
+    N_187_i (driver: ram2e_ufm/SLICE_130, clk load #: 0, sr load #: 0, ce load #: 11)
 
 No signal is selected as Global Set/Reset.
 Starting Placer Phase 0.
-............
-Finished Placer Phase 0.  REAL time: 0 secs 
+...........
+Finished Placer Phase 0.  REAL time: 2 secs 
 
 Starting Placer Phase 1.
-.....................
-Placer score = 63243.
-Finished Placer Phase 1.  REAL time: 8 secs 
+....................
+Placer score = 69810.
+Finished Placer Phase 1.  REAL time: 9 secs 
 
 Starting Placer Phase 2.
 .
-Placer score =  62715
-Finished Placer Phase 2.  REAL time: 8 secs 
+Placer score =  69262
+Finished Placer Phase 2.  REAL time: 9 secs 
 
 
 
@@ -112,8 +112,8 @@ Global Clock Resources:
   DCC        : 0 out of 8 (0%)
 
 Global Clocks:
-  PRIMARY &quot;C14M_c&quot; from comp &quot;C14M&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 84
-  SECONDARY &quot;N_576_i&quot; from F1 on comp &quot;SLICE_20&quot; on site &quot;R6C8A&quot;, clk load = 0, ce load = 17, sr load = 0
+  PRIMARY &quot;C14M_c&quot; from comp &quot;C14M&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 89
+  SECONDARY &quot;N_187_i&quot; from F1 on comp &quot;ram2e_ufm/SLICE_130&quot; on site &quot;R6C8B&quot;, clk load = 0, ce load = 11, sr load = 0
 
   PRIMARY  : 1 out of 8 (12%)
   SECONDARY: 1 out of 8 (12%)
@@ -122,32 +122,32 @@ Global Clocks:
 
 
 I/O Usage Summary (final):
-   70 + 4(JTAG) out of 80 (92.5%) PIO sites used.
-   70 + 4(JTAG) out of 79 (93.7%) bonded PIO sites used.
-   Number of PIO comps: 70; differential: 0.
+   69 + 4(JTAG) out of 80 (91.3%) PIO sites used.
+   69 + 4(JTAG) out of 79 (92.4%) bonded PIO sites used.
+   Number of PIO comps: 69; differential: 0.
    Number of Vref pins used: 0.
 
 I/O Bank Usage Summary:
 +----------+----------------+------------+-----------+
 | I/O Bank | Usage          | Bank Vccio | Bank Vref |
 +----------+----------------+------------+-----------+
-| 0        | 12 / 19 ( 63%) | 3.3V       | -         |
+| 0        | 11 / 19 ( 57%) | 3.3V       | -         |
 | 1        | 20 / 20 (100%) | 3.3V       | -         |
 | 2        | 18 / 20 ( 90%) | 3.3V       | -         |
 | 3        | 20 / 20 (100%) | 3.3V       | -         |
 +----------+----------------+------------+-----------+
 
-Total placer CPU time: 8 secs 
+Total placer CPU time: 7 secs 
 
 Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
 
-0 connections routed; 1126 unrouted.
+0 connections routed; 1330 unrouted.
 Starting router resource preassignment
 WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
 
 Completed router resource preassignment. Real time: 13 secs 
 
-Start NBR router at 05:35:04 09/21/23
+Start NBR router at 23:10:14 12/28/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -162,32 +162,35 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:35:05 09/21/23
+Start NBR special constraint process at 23:10:14 12/28/23
 
-Start NBR section for initial routing at 05:35:05 09/21/23
+Start NBR section for initial routing at 23:10:14 12/28/23
 Level 4, iteration 1
-14(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack&lt;setup&gt;: 57.366ns/0.000ns; real time: 14 secs 
+19(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: 58.137ns/0.000ns; real time: 13 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:35:05 09/21/23
+Start NBR section for normal routing at 23:10:14 12/28/23
 Level 4, iteration 1
-4(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack&lt;setup&gt;: 57.366ns/0.000ns; real time: 14 secs 
+8(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: 57.938ns/0.000ns; real time: 13 secs 
 Level 4, iteration 2
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack&lt;setup&gt;: 57.938ns/0.000ns; real time: 13 secs 
+Level 4, iteration 3
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack&lt;setup&gt;: 57.366ns/0.000ns; real time: 14 secs 
+Estimated worst slack/total negative slack&lt;setup&gt;: 57.938ns/0.000ns; real time: 13 secs 
 
-Start NBR section for setup/hold timing optimization with effort level 3 at 05:35:05 09/21/23
+Start NBR section for setup/hold timing optimization with effort level 3 at 23:10:14 12/28/23
 
-Start NBR section for re-routing at 05:35:05 09/21/23
+Start NBR section for re-routing at 23:10:15 12/28/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack&lt;setup&gt;: 57.366ns/0.000ns; real time: 14 secs 
+Estimated worst slack/total negative slack&lt;setup&gt;: 57.938ns/0.000ns; real time: 14 secs 
 
-Start NBR section for post-routing at 05:35:05 09/21/23
+Start NBR section for post-routing at 23:10:15 12/28/23
 
 End NBR router with 0 unrouted connection
 
@@ -195,17 +198,17 @@ NBR Summary
 -----------
   Number of unrouted connections : 0 (0.00%)
   Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack&lt;setup&gt; : 57.366ns
+  Estimated worst slack&lt;setup&gt; : 57.938ns
   Timing score&lt;setup&gt; : 0
 -----------
 Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
 
 
 
-Total CPU time 14 secs 
-Total REAL time: 15 secs 
+Total CPU time 13 secs 
+Total REAL time: 14 secs 
 Completely routed.
-End of route.  1126 routed (100.00%); 0 unrouted.
+End of route.  1330 routed (100.00%); 0 unrouted.
 
 Hold time timing score: 0, hold timing errors: 0
 
@@ -219,13 +222,13 @@ All signals are completely routed.
 
 PAR_SUMMARY::Run status = Completed
 PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack&lt;setup/&lt;ns&gt;&gt; = 57.366
+PAR_SUMMARY::Worst  slack&lt;setup/&lt;ns&gt;&gt; = 57.938
 PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
-PAR_SUMMARY::Worst  slack&lt;hold /&lt;ns&gt;&gt; = 0.346
+PAR_SUMMARY::Worst  slack&lt;hold /&lt;ns&gt;&gt; = 0.379
 PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 15 secs 
+Total CPU  time to completion: 13 secs 
 Total REAL time to completion: 15 secs 
 
 par done!
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt
index 1e28830..649ec92 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt
@@ -13,10 +13,10 @@ Hostname: ZANEMACWIN11
 
 Implementation : impl1
 
-# Written on Thu Sep 21 05:34:35 2023
+# Written on Thu Dec 28 23:09:48 2023
 
 ##### FILES SYNTAX CHECKED ##############################################
-Constraint File(s):      "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
+Constraint File(s):      "\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc"
 
 #Run constraint checker to find more issues with constraints.
 #########################################################################
@@ -33,7 +33,7 @@ Clock Summary
           Start      Requested     Requested     Clock        Clock                Clock
 Level     Clock      Frequency     Period        Type         Group                Load 
 ----------------------------------------------------------------------------------------
-0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     111  
+0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     122  
                                                                                         
 0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
 ========================================================================================
@@ -45,7 +45,7 @@ Clock Load Summary
            Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin     
 Clock      Load      Pin            Seq Example     Seq Example       Comb Example      
 ----------------------------------------------------------------------------------------
-C14M       111       C14M(port)     wb_rst.C        -                 un1_C14M.I[0](inv)
+C14M       122       C14M(port)     DOEEN.C         -                 un1_C14M.I[0](inv)
                                                                                         
 System     0         -              -               -                 -                 
 ========================================================================================
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html
index 0aea46c..0f147ac 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html
@@ -62,15 +62,15 @@
 </TR>
 <TR>
 <TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
-<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/09/21 05:35:24</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/12/28 23:10:32</SPAN></TD>
 </TR>
 <TR>
 <TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
-<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1</SPAN></TD>
 </TR>
 <TR>
 <TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
-<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf</SPAN></TD>
 </TR>
 </small></TABLE>
 <BR>
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html
index e39a6e5..c31b427 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html
@@ -12,7 +12,7 @@
 #OS: Windows 8 6.2
 #Hostname: ZANEMACWIN11
 
-# Thu Sep 21 05:34:32 2023
+# Thu Dec 28 23:09:44 2023
 
 #Implementation: impl1
 
@@ -57,30 +57,35 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
 @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
-@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work)
+@I::"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v" (library work)
+@I::"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v" (library work)
+@I::"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v" (library work)
 Verilog syntax check successful!
-
-Compiler output is up to date.  No re-compile necessary
-
 Selecting top level module RAM2E
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
 Running optimization stage 1 on VHI .......
-Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
 Running optimization stage 1 on VLO .......
-Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
 @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
 Running optimization stage 1 on EFB .......
-Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
 Running optimization stage 1 on REFB .......
-Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
+Running optimization stage 1 on RAM2E_UFM .......
+Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
+@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
 Running optimization stage 1 on RAM2E .......
 Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
 Running optimization stage 2 on RAM2E .......
-Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
+Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
+Running optimization stage 2 on RAM2E_UFM .......
+@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
+Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
 Running optimization stage 2 on REFB .......
 Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
 Running optimization stage 2 on EFB .......
@@ -90,12 +95,12 @@ Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current:
 Running optimization stage 2 on VHI .......
 Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
 
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB)
+At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:32 2023
+# Thu Dec 28 23:09:45 2023
 
 ###########################################################]
 ###########################################################[
@@ -117,58 +122,58 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
 
 @N|Running in 64-bit mode
 
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Sep 21 05:34:33 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Sep 21 05:34:33 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
-
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
 
 Process completed successfully.
-# Thu Sep 21 05:34:34 2023
+# Thu Dec 28 23:09:45 2023
 
 ###########################################################]
-# Thu Sep 21 05:34:34 2023
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: A:\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Dec 28 23:09:46 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Dec 28 23:09:47 2023
+
+###########################################################]
+# Thu Dec 28 23:09:47 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -187,14 +192,14 @@ Implementation : impl1
 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
 
-Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
-@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt 
-See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
+Reading constraint file: \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc
+@L: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt 
+See clock summary report "\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@@ -208,33 +213,32 @@ Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0
 Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB)
 
-@N: FX493 |Applying initial value "0" on instance PHI1reg.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance DOEEN.
-@N: FX493 |Applying initial value "0" on instance RWSel.
-@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
-@N: FX493 |Applying initial value "1" on instance DQMH.
-@N: FX493 |Applying initial value "0" on instance Ready.
 @N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 @N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
+@N: FX493 |Applying initial value "0" on instance PHI1r.
+@N: FX493 |Applying initial value "0" on instance RWSel.
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
 @N: FX493 |Applying initial value "0" on instance CmdLEDGet.
 @N: FX493 |Applying initial value "0" on instance CmdLEDSet.
 @N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
 @N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
-@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-@N: FX493 |Applying initial value "0" on instance LEDEN.
-@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "0000" on instance S[3:0].
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "1" on instance DQMH.
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
 @N: FX493 |Applying initial value "1" on instance DQML.
-@N: FX493 |Applying initial value "0" on instance CKE.
-@N: FX493 |Applying initial value "1" on instance nCS.
-@N: FX493 |Applying initial value "1" on instance nRAS.
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "0000" on instance S[3:0].
+@N: FX493 |Applying initial value "1" on instance CKE.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+@N: FX493 |Applying initial value "1" on instance nRWEout.
 @N: FX493 |Applying initial value "1" on instance nCAS.
+@N: FX493 |Applying initial value "1" on instance nCASout.
+@N: FX493 |Applying initial value "1" on instance nRAS.
+@N: FX493 |Applying initial value "1" on instance nRASout.
 
 Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
 
@@ -245,11 +249,11 @@ Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapse
 Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
 
 
-Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
 
 @N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E 
 
-Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
 
 
 
@@ -259,7 +263,7 @@ Clock Summary
           Start      Requested     Requested     Clock        Clock                Clock
 Level     Clock      Frequency     Period        Type         Group                Load 
 ----------------------------------------------------------------------------------------
-0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     111  
+0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     122  
                                                                                         
 0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
 ========================================================================================
@@ -272,7 +276,7 @@ Clock Load Summary
            Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin     
 Clock      Load      Pin            Seq Example     Seq Example       Comb Example      
 ----------------------------------------------------------------------------------------
-C14M       111       C14M(port)     wb_rst.C        -                 un1_C14M.I[0](inv)
+C14M       122       C14M(port)     DOEEN.C         -                 un1_C14M.I[0](inv)
                                                                                         
 System     0         -              -               -                 -                 
 ========================================================================================
@@ -289,14 +293,14 @@ For details review file gcc_ICG_report.rpt
 
 #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
 
-1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
+1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
 0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
 =========================== Non-Gated/Non-Generated Clocks ============================
 Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
 ---------------------------------------------------------------------------------------
-@KP:ckid0_0       C14M                port                   111        nCAS           
+@KP:ckid0_0       C14M                port                   122        nRAS           
 =======================================================================================
 
 
@@ -305,23 +309,23 @@ Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample I
 @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
 Finished Pre Mapping Phase.
 
-Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
 
 
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
 
 
-Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB)
 
 Pre-mapping successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
 
-Process took 0h:00m:02s realtime, 0h:00m:01s cputime
-# Thu Sep 21 05:34:37 2023
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Thu Dec 28 23:09:49 2023
 
 ###########################################################]
-# Thu Sep 21 05:34:37 2023
+# Thu Dec 28 23:09:49 2023
 
 
 Copyright (C) 1994-2021 Synopsys, Inc.
@@ -340,97 +344,97 @@ Implementation : impl1
 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
 
 
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
 
 @N: MF916 |Option synthesis_strategy=base is enabled. 
 @N: MF248 |Running in 64-bit mode.
 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
 
 
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
 
 
 Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
 
 
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
 
 
 
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
 
-@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
-@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
 
-Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
 
-@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
+@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
 @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
 
 Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
 
 
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
 Available hyper_sources - for debug and ip models
 	None Found
 
 
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
 
 
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
 
 
-Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
 
 
-Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
 
 Pass		 CPU time		Worst Slack		Luts / Registers
 ------------------------------------------------------------
-   1		0h:00m:02s		    29.35ns		 222 /       111
+   1		0h:00m:02s		    33.71ns		 284 /       122
 
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
 
 @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
+@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
 
-Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
+Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
 
 
-Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
+Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
 
-Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
+Writing Analyst data base \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
 
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 206MB peak: 206MB)
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB)
 
 Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
+@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
 
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
 
 
-Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
+Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
 
 
-Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
+Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB)
 
 @W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
 @N: MT615 |Found clock C14M with period 69.84ns 
 
 
 ##### START OF TIMING REPORT #####[
-# Timing report written on Thu Sep 21 05:34:43 2023
+# Timing report written on Thu Dec 28 23:09:54 2023
 #
 
 
@@ -438,7 +442,7 @@ Top view:               RAM2E
 Requested Frequency:    14.3 MHz
 Wire load mode:         top
 Paths requested:        5
-Constraint File(s):    \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
+Constraint File(s):    \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc
                        
 @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
 
@@ -450,12 +454,12 @@ Performance Summary
 *******************
 
 
-Worst slack in design: 31.782
+Worst slack in design: 33.707
 
                    Requested     Estimated     Requested     Estimated                Clock        Clock           
 Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
 -------------------------------------------------------------------------------------------------------------------
-C14M               14.3 MHz      131.4 MHz     69.841        7.610         31.782     declared     default_clkgroup
+C14M               14.3 MHz      128.0 MHz     69.841        7.813         33.707     declared     default_clkgroup
 System             100.0 MHz     NA            10.000        NA            67.088     system       system_clkgroup 
 ===================================================================================================================
 Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
@@ -473,7 +477,7 @@ Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  sl
 ----------------------------------------------------------------------------------------------------------
 System    C14M    |  69.841      67.088  |  No paths    -      |  No paths    -       |  No paths    -    
 C14M      System  |  69.841      68.797  |  No paths    -      |  No paths    -       |  No paths    -    
-C14M      C14M    |  69.841      62.231  |  No paths    -      |  34.920      31.782  |  No paths    -    
+C14M      C14M    |  69.841      62.028  |  No paths    -      |  34.920      33.707  |  No paths    -    
 ==========================================================================================================
  Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
        'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
@@ -496,41 +500,41 @@ Detailed Report for Clock: C14M
 Starting Points with Worst Slack
 ********************************
 
-             Starting                                     Arrival           
-Instance     Reference     Type        Pin     Net        Time        Slack 
-             Clock                                                          
-----------------------------------------------------------------------------
-S[2]         C14M          FD1S3AX     Q       S[2]       1.350       31.782
-S[3]         C14M          FD1S3AX     Q       S[3]       1.350       31.782
-S[0]         C14M          FD1S3AX     Q       S[0]       1.312       31.820
-S[1]         C14M          FD1S3AX     Q       S[1]       1.280       31.852
-FS[9]        C14M          FD1S3AX     Q       FS[9]      1.284       62.425
-FS[11]       C14M          FD1S3AX     Q       FS[11]     1.276       62.433
-FS[8]        C14M          FD1S3AX     Q       FS[8]      1.260       62.449
-FS[12]       C14M          FD1S3AX     Q       FS[12]     1.288       62.525
-FS[10]       C14M          FD1S3AX     Q       FS[10]     1.280       62.533
-RWSel        C14M          FD1P3AX     Q       RWSel      1.276       63.482
-============================================================================
+             Starting                                    Arrival           
+Instance     Reference     Type        Pin     Net       Time        Slack 
+             Clock                                                         
+---------------------------------------------------------------------------
+RA[0]        C14M          FD1P3AX     Q       RA[0]     1.108       33.707
+RA[3]        C14M          FD1P3AX     Q       RA[3]     1.108       33.707
+RA[1]        C14M          FD1P3AX     Q       RA[1]     1.044       33.771
+RA[2]        C14M          FD1P3AX     Q       RA[2]     1.044       33.771
+RA[4]        C14M          FD1P3AX     Q       RA[4]     1.044       33.771
+RA[5]        C14M          FD1P3AX     Q       RA[5]     1.044       33.771
+RA[6]        C14M          FD1P3AX     Q       RA[6]     1.044       33.771
+RA[7]        C14M          FD1P3AX     Q       RA[7]     1.044       33.771
+RA[8]        C14M          FD1P3AX     Q       RA[8]     1.044       33.771
+RA[9]        C14M          FD1P3AX     Q       RA[9]     1.044       33.771
+===========================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-                Starting                                       Required           
-Instance        Reference     Type         Pin     Net         Time         Slack 
-                Clock                                                             
-----------------------------------------------------------------------------------
-Dout_0io[0]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[1]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[2]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[3]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[4]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[5]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[6]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Dout_0io[7]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
-Vout_0io[0]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
-Vout_0io[1]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
-==================================================================================
+                 Starting                                     Required           
+Instance         Reference     Type         Pin     Net       Time         Slack 
+                 Clock                                                           
+---------------------------------------------------------------------------------
+RAout_0io[0]     C14M          OFS1P3DX     D       RA[0]     34.815       33.707
+RAout_0io[3]     C14M          OFS1P3DX     D       RA[3]     34.815       33.707
+RAout_0io[1]     C14M          OFS1P3DX     D       RA[1]     34.815       33.771
+RAout_0io[2]     C14M          OFS1P3DX     D       RA[2]     34.815       33.771
+RAout_0io[4]     C14M          OFS1P3DX     D       RA[4]     34.815       33.771
+RAout_0io[5]     C14M          OFS1P3DX     D       RA[5]     34.815       33.771
+RAout_0io[6]     C14M          OFS1P3DX     D       RA[6]     34.815       33.771
+RAout_0io[7]     C14M          OFS1P3DX     D       RA[7]     34.815       33.771
+RAout_0io[8]     C14M          OFS1P3DX     D       RA[8]     34.815       33.771
+RAout_0io[9]     C14M          OFS1P3DX     D       RA[9]     34.815       33.771
+=================================================================================
 
 
 
@@ -540,30 +544,27 @@ Worst Path Information
 
 Path information for path number 1: 
       Requested Period:                      34.920
-    - Setup time:                            0.472
+    - Setup time:                            0.106
     + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         34.449
+    = Required time:                         34.815
 
-    - Propagation time:                      2.667
+    - Propagation time:                      1.108
     - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     31.782
+    = Slack (critical) :                     33.707
 
-    Number of logic level(s):                1
-    Starting point:                          S[2] / Q
-    Ending point:                            Dout_0io[0] / SP
+    Number of logic level(s):                0
+    Starting point:                          RA[0] / Q
+    Ending point:                            RAout_0io[0] / D
     The start point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
     The end   point is clocked by            C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
 
-Instance / Net                   Pin      Pin               Arrival     No. of    
-Name                Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
-S[2]                FD1S3AX      Q        Out     1.350     1.350 r     -         
-S[2]                Net          -        -       -         -           48        
-S_RNII9DO1_2[1]     ORCALUT4     B        In      0.000     1.350 r     -         
-S_RNII9DO1_2[1]     ORCALUT4     Z        Out     1.317     2.667 r     -         
-N_576_i             Net          -        -       -         -           18        
-Dout_0io[0]         OFS1P3DX     SP       In      0.000     2.667 r     -         
-==================================================================================
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+RA[0]              FD1P3AX      Q        Out     1.108     1.108 r     -         
+RA[0]              Net          -        -       -         -           3         
+RAout_0io[0]       OFS1P3DX     D        In      0.000     1.108 r     -         
+=================================================================================
 
 
 
@@ -577,40 +578,40 @@ Detailed Report for Clock: System
 Starting Points with Worst Slack
 ********************************
 
-                     Starting                                          Arrival           
-Instance             Reference     Type     Pin         Net            Time        Slack 
-                     Clock                                                               
------------------------------------------------------------------------------------------
-ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
-ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
-ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
-=========================================================================================
+                               Starting                                          Arrival           
+Instance                       Reference     Type     Pin         Net            Time        Slack 
+                               Clock                                                               
+---------------------------------------------------------------------------------------------------
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
+ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
+===================================================================================================
 
 
 Ending Points with Worst Slack
 ******************************
 
-               Starting                                                          Required           
-Instance       Reference     Type        Pin     Net                             Time         Slack 
-               Clock                                                                                
-----------------------------------------------------------------------------------------------------
-RWMask[0]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[1]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[2]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[3]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[4]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[5]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[6]      System        FD1P3AX     SP      N_88                            69.369       67.088
-RWMask[7]      System        FD1P3AX     SP      N_88                            69.369       67.088
-LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0[0]     69.369       67.736
-wb_cyc_stb     System        FD1P3AX     SP      N_104                           69.369       67.736
-====================================================================================================
+                         Starting                                                                  Required           
+Instance                 Reference     Type        Pin     Net                                     Time         Slack 
+                         Clock                                                                                        
+----------------------------------------------------------------------------------------------------------------------
+ram2e_ufm.RWMask[0]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[1]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[2]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[3]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[4]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[5]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[6]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.RWMask[7]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
+ram2e_ufm.LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0_0[0]           69.369       67.736
+ram2e_ufm.wb_cyc_stb     System        FD1P3AX     SP      un1_CmdSetRWBankFFChip13_1_i_0_0[0]     69.369       67.736
+======================================================================================================================
 
 
 
@@ -630,24 +631,24 @@ Path information for path number 1:
     = Slack (non-critical) :                 67.088
 
     Number of logic level(s):                2
-    Starting point:                          ufmefb.EFBInst_0 / WBACKO
-    Ending point:                            RWMask[0] / SP
+    Starting point:                          ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
+    Ending point:                            ram2e_ufm.RWMask[0] / SP
     The start point is clocked by            System [rising]
     The end   point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
 
-Instance / Net                                     Pin        Pin               Arrival     No. of    
-Name                                  Type         Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
-ufmefb.EFBInst_0                      EFB          WBACKO     Out     0.000     0.000 r     -         
-wb_ack                                Net          -          -       -         -           5         
-un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     A          In      0.000     0.000 r     -         
-un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     Z          Out     1.017     1.017 r     -         
-un1_RWMask_0_sqmuxa_1_i_a2_0_1[0]     Net          -          -       -         -           1         
-un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
-un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
-N_88                                  Net          -          -       -         -           8         
-RWMask[0]                             FD1P3AX      SP         In      0.000     2.282 r     -         
-======================================================================================================
+Instance / Net                                                 Pin        Pin               Arrival     No. of    
+Name                                              Type         Name       Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------------------------------------
+ram2e_ufm.ufmefb.EFBInst_0                        EFB          WBACKO     Out     0.000     0.000 r     -         
+wb_ack                                            Net          -          -       -         -           5         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     B          In      0.000     0.000 r     -         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     Z          Out     1.017     1.017 r     -         
+un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]               Net          -          -       -         -           1         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
+ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
+un1_RWMask_0_sqmuxa_1_i_0_0[0]                    Net          -          -       -         -           8         
+ram2e_ufm.RWMask[0]                               FD1P3AX      SP         In      0.000     2.282 r     -         
+==================================================================================================================
 
 
 
@@ -655,46 +656,48 @@ RWMask[0]                             FD1P3AX      SP         In      0.000
 
 Timing exceptions that could not be applied
 
-Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
 
 
-Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
 
 ---------------------------------------
 Resource Usage Report
 Part: lcmxo2_640hc-4
 
-Register bits: 111 of 640 (17%)
+Register bits: 122 of 640 (19%)
 PIC Latch:       0
-I/O cells:       70
+I/O cells:       69
 
 
 Details:
 BB:             8
 CCU2D:          9
 EFB:            1
-FD1P3AX:        48
+FD1P3AX:        61
 FD1P3IX:        1
-FD1S3AX:        22
-FD1S3IX:        4
+FD1S3AX:        21
+FD1S3AY:        4
+FD1S3IX:        6
 GSR:            1
-IB:             22
+IB:             21
 IFS1P3DX:       1
 INV:            1
 OB:             40
-OFS1P3BX:       6
-OFS1P3DX:       27
+OFS1P3BX:       5
+OFS1P3DX:       21
 OFS1P3IX:       2
-ORCALUT4:       221
+ORCALUT4:       277
+PFUMX:          3
 PUR:            1
-VHI:            2
-VLO:            2
+VHI:            3
+VLO:            3
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 77MB peak: 211MB)
+At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 79MB peak: 217MB)
 
-Process took 0h:00m:06s realtime, 0h:00m:04s cputime
-# Thu Sep 21 05:34:44 2023
+Process took 0h:00m:04s realtime, 0h:00m:04s cputime
+# Thu Dec 28 23:09:54 2023
 
 ###########################################################]
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html
index 266503b..323a4c3 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 <A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
-Thu Sep 21 05:34:48 2023
+Thu Dec 28 23:09:59 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -32,7 +32,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 <A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
 ------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
 Design file:     ram2e_lcmxo2_640hc_impl1_map.ncd
 Preference file: ram2e_lcmxo2_640hc_impl1.prf
 Device,speed:    LCMXO2-640HC,4
@@ -41,8 +41,8 @@ Report level:    verbose report, limited to 1 item per preference
 
 <A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
 
-<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1491 items scored, 0 timing errors detected.
-Report:   87.268MHz is the maximum frequency for this preference.
+<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1611 items scored, 0 timing errors detected.
+Report:   90.967MHz is the maximum frequency for this preference.
 
 BLOCK ASYNCPATHS
 BLOCK RESETPATHS
@@ -52,48 +52,48 @@ BLOCK RESETPATHS
 
 ================================================================================
 <A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 58.471ns
+Passed: The following path meets requirements by 58.937ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              11.306ns  (30.3% logic, 69.7% route), 7 logic levels.
+   Delay:              10.827ns  (31.6% logic, 68.4% route), 7 logic levels.
 
  Constraint Details:
 
-     11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
-      0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns
 
  Physical Path Details:
 
-      Data path SLICE_3 to nRWE_MGIOL:
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452    SLICE_3.CLK to     SLICE_3.Q0 SLICE_3 (from C14M_c)
-ROUTE        19   e 1.234     SLICE_3.Q0 to    SLICE_64.A1 FS[11]
-CTOF_DEL    ---     0.495    SLICE_64.A1 to    SLICE_64.F1 SLICE_64
-ROUTE         4   e 1.234    SLICE_64.F1 to    SLICE_97.D0 N_577
-CTOF_DEL    ---     0.495    SLICE_97.D0 to    SLICE_97.F0 SLICE_97
-ROUTE         3   e 1.234    SLICE_97.F0 to    SLICE_75.D1 N_489
-CTOF_DEL    ---     0.495    SLICE_75.D1 to    SLICE_75.F1 SLICE_75
-ROUTE         3   e 0.480    SLICE_75.F1 to    SLICE_75.A0 N_628
-CTOF_DEL    ---     0.495    SLICE_75.A0 to    SLICE_75.F0 SLICE_75
-ROUTE         2   e 1.234    SLICE_75.F0 to    SLICE_71.C1 N_640
-CTOF_DEL    ---     0.495    SLICE_71.C1 to    SLICE_71.F1 SLICE_71
-ROUTE         1   e 1.234    SLICE_71.F1 to   SLICE_115.A0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495   SLICE_115.A0 to   SLICE_115.F0 SLICE_115
-ROUTE         1   e 1.234   SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
+REG_DEL     ---     0.452   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from C14M_c)
+ROUTE        50   e 1.234    SLICE_34.Q0 to    SLICE_35.A0 S[2]
+CTOF_DEL    ---     0.495    SLICE_35.A0 to    SLICE_35.F0 SLICE_35
+ROUTE         7   e 1.234    SLICE_35.F0 to *m/SLICE_80.D1 N_551
+CTOF_DEL    ---     0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
+ROUTE         8   e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
+ROUTE         5   e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
+ROUTE         1   e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
+CTOF_DEL    ---     0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
+ROUTE         1   e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
+ROUTE         1   e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   11.306   (30.3% logic, 69.7% route), 7 logic levels.
+                   10.827   (31.6% logic, 68.4% route), 7 logic levels.
 
-Report:   87.268MHz is the maximum frequency for this preference.
+Report:   90.967MHz is the maximum frequency for this preference.
 
 <A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
 --------------
@@ -101,7 +101,7 @@ Report:   87.268MHz is the maximum frequency for this preference.
 Preference                              |   Constraint|       Actual|Levels
 ----------------------------------------------------------------------------
                                         |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   87.268 MHz|   7  
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   90.967 MHz|   7  
                                         |             |             |
 ----------------------------------------------------------------------------
 
@@ -114,7 +114,7 @@ All preferences were met.
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -124,11 +124,11 @@ Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 --------------------------------------------------------------------------------
 <A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
-Thu Sep 21 05:34:48 2023
+Thu Dec 28 23:09:59 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -138,7 +138,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 <A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
 ------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
 Design file:     ram2e_lcmxo2_640hc_impl1_map.ncd
 Preference file: ram2e_lcmxo2_640hc_impl1.prf
 Device,speed:    LCMXO2-640HC,M
@@ -147,7 +147,7 @@ Report level:    verbose report, limited to 1 item per preference
 
 <A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
 
-<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1491 items scored, 0 timing errors detected.
+<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1611 items scored, 0 timing errors detected.
 
 BLOCK ASYNCPATHS
 BLOCK RESETPATHS
@@ -157,7 +157,7 @@ BLOCK RESETPATHS
 
 ================================================================================
 <A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
@@ -182,7 +182,7 @@ Passed: The following path meets requirements by 0.447ns
 
    Name    Fanout   Delay (ns)          Site               Resource
 REG_DEL     ---     0.133    SLICE_0.CLK to     SLICE_0.Q1 SLICE_0 (from C14M_c)
-ROUTE         5   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
+ROUTE         6   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
 CTOF_DEL    ---     0.101     SLICE_0.A1 to     SLICE_0.F1 SLICE_0
 ROUTE         1   e 0.001     SLICE_0.F1 to    SLICE_0.DI1 FS_s[0] (to C14M_c)
                   --------
@@ -207,7 +207,7 @@ All preferences were met.
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -217,7 +217,7 @@ Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html
index a7358ba..9b7e706 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 <A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
-Thu Sep 21 05:35:07 2023
+Thu Dec 28 23:10:16 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -32,7 +32,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 <A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
 ------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
 Design file:     ram2e_lcmxo2_640hc_impl1.ncd
 Preference file: ram2e_lcmxo2_640hc_impl1.prf
 Device,speed:    LCMXO2-640HC,4
@@ -41,8 +41,8 @@ Report level:    verbose report, limited to 10 items per preference
 
 <A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
 
-<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1491 items scored, 0 timing errors detected.
-Report:   79.592MHz is the maximum frequency for this preference.
+<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1611 items scored, 0 timing errors detected.
+Report:   83.389MHz is the maximum frequency for this preference.
 
 BLOCK ASYNCPATHS
 BLOCK RESETPATHS
@@ -52,536 +52,550 @@ BLOCK RESETPATHS
 
 ================================================================================
 <A name="par_twr_pref_0_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 57.366ns
+Passed: The following path meets requirements by 57.938ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              12.584ns  (27.2% logic, 72.8% route), 7 logic levels.
+   Delay:              11.826ns  (24.8% logic, 75.2% route), 6 logic levels.
 
  Constraint Details:
 
-     12.584ns physical path delay SLICE_3 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.366ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     0.453       R3C9C.F1 to       R3C9C.C0 N_628
-CTOF_DEL    ---     0.495       R3C9C.C0 to       R3C9C.F0 SLICE_75
-ROUTE         2     0.993       R3C9C.F0 to       R5C9A.A1 N_640
-CTOF_DEL    ---     0.495       R5C9A.A1 to       R5C9A.F1 SLICE_71
-ROUTE         1     0.623       R5C9A.F1 to      R5C10B.D0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495      R5C10B.D0 to      R5C10B.F0 SLICE_115
-ROUTE         1     2.192      R5C10B.F0 to   IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   12.584   (27.2% logic, 72.8% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R7D.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.494ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRAS_0io  (to C14M_c +)
-
-   Delay:              12.456ns  (23.5% logic, 76.5% route), 6 logic levels.
-
- Constraint Details:
-
-     12.456ns physical path delay SLICE_3 to nRAS_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.494ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nRAS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     1.003       R3C9C.F1 to      R3C10D.A0 N_628
-CTOF_DEL    ---     0.495      R3C10D.A0 to      R3C10D.F0 SLICE_83
-ROUTE         2     1.505      R3C10D.F0 to      R5C10A.A0 N_559_1
-CTOF_DEL    ---     0.495      R5C10A.A0 to      R5C10A.F0 SLICE_80
-ROUTE         1     2.120      R5C10A.F0 to   IOL_R7A.OPOS nRAS_2_iv_i (to C14M_c)
-                  --------
-                   12.456   (23.5% logic, 76.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRAS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R7A.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.502ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
-
-   Delay:              12.448ns  (23.5% logic, 76.5% route), 6 logic levels.
-
- Constraint Details:
-
-     12.448ns physical path delay SLICE_3 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.502ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     0.710       R3C9C.F1 to       R3C9B.B0 N_628
-CTOF_DEL    ---     0.495       R3C9B.B0 to       R3C9B.F0 SLICE_76
-ROUTE         3     1.718       R3C9B.F0 to      R5C10B.C0 nCAS_0_sqmuxa
-CTOF_DEL    ---     0.495      R5C10B.C0 to      R5C10B.F0 SLICE_115
-ROUTE         1     2.192      R5C10B.F0 to   IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   12.448   (23.5% logic, 76.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R7D.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.921ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nCS_0io  (to C14M_c +)
-
-   Delay:              12.029ns  (24.3% logic, 75.7% route), 6 logic levels.
-
- Constraint Details:
-
-     12.029ns physical path delay SLICE_3 to nCS_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 57.921ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nCS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     1.003       R3C9C.F1 to      R3C10D.A0 N_628
-CTOF_DEL    ---     0.495      R3C10D.A0 to      R3C10D.F0 SLICE_83
-ROUTE         2     1.505      R3C10D.F0 to      R6C10A.A0 N_559_1
-CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_79
-ROUTE         1     1.693      R6C10A.F0 to   IOL_R6D.OPOS N_559_i (to C14M_c)
-                  --------
-                   12.029   (24.3% logic, 75.7% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nCS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R6D.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.106ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        nCAS_0io  (to C14M_c +)
-
-   Delay:              11.844ns  (24.7% logic, 75.3% route), 6 logic levels.
-
- Constraint Details:
-
-     11.844ns physical path delay SLICE_3 to nCAS_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 58.106ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nCAS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     0.710       R3C9C.F1 to       R3C9B.B0 N_628
-CTOF_DEL    ---     0.495       R3C9B.B0 to       R3C9B.F0 SLICE_76
-ROUTE         3     1.511       R3C9B.F0 to       R5C9C.A0 nCAS_0_sqmuxa
-CTOF_DEL    ---     0.495       R5C9C.A0 to       R5C9C.F0 SLICE_78
-ROUTE         1     1.795       R5C9C.F0 to   IOL_R7C.OPOS N_561_i (to C14M_c)
-                  --------
-                   11.844   (24.7% logic, 75.3% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nCAS_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R7C.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.447ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        RA_0io[10]  (to C14M_c +)
-
-   Delay:              11.503ns  (25.4% logic, 74.6% route), 6 logic levels.
-
- Constraint Details:
-
-     11.503ns physical path delay SLICE_3 to RA[10]_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 58.447ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to RA[10]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
-CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
-ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
-CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     0.710       R3C9C.F1 to       R3C9B.B0 N_628
-CTOF_DEL    ---     0.495       R3C9B.B0 to       R3C9B.F0 SLICE_76
-ROUTE         3     1.170       R3C9B.F0 to       R5C9D.D1 nCAS_0_sqmuxa
-CTOF_DEL    ---     0.495       R5C9D.D1 to       R5C9D.F1 SLICE_69
-ROUTE         1     1.795       R5C9D.F1 to   IOL_R5B.OPOS RA_42[10] (to C14M_c)
-                  --------
-                   11.503   (25.4% logic, 74.6% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to RA[10]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R5B.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.587ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[2]  (from C14M_c +)
-   Destination:    FF         Data in        wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.177ns  (26.2% logic, 73.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.177ns physical path delay SLICE_34 to SLICE_35 meets
+     11.826ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
       0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.587ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.938ns
 
  Physical Path Details:
 
-      Data path SLICE_34 to SLICE_35:
+      Data path SLICE_33 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R4C9C.CLK to       R4C9C.Q0 SLICE_34 (from C14M_c)
-ROUTE        48     1.873       R4C9C.Q0 to       R6C9B.B0 S[2]
-CTOF_DEL    ---     0.495       R6C9B.B0 to       R6C9B.F0 SLICE_47
-ROUTE         7     2.435       R6C9B.F0 to       R4C5B.B0 S_RNII9DO1[1]
-CTOF_DEL    ---     0.495       R4C5B.B0 to       R4C5B.F0 SLICE_73
-ROUTE         8     1.931       R4C5B.F0 to       R4C4C.D0 N_455
-CTOF_DEL    ---     0.495       R4C4C.D0 to       R4C4C.F0 SLICE_89
-ROUTE         1     0.626       R4C4C.F0 to       R4C4A.D0 N_378
-CTOF_DEL    ---     0.495       R4C4A.D0 to       R4C4A.F0 SLICE_85
-ROUTE         1     1.385       R4C4A.F0 to       R2C4B.D0 wb_adr_7_0_4[0]
-CTOF_DEL    ---     0.495       R2C4B.D0 to       R2C4B.F0 SLICE_35
-ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 wb_adr_7[0] (to C14M_c)
+REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
+CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
+ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
+CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
+ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
+CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   11.177   (26.2% logic, 73.8% route), 6 logic levels.
+                   11.826   (24.8% logic, 75.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 57.944ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              11.820ns  (29.0% logic, 71.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.820ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.944ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
+CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
+ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
+CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
+ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
+CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
+ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
+CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   11.820   (29.0% logic, 71.0% route), 7 logic levels.
 
  Clock Skew Details: 
 
       Source Clock Path C14M to SLICE_34:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R4C9C.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
                   --------
                     3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_35:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C4B.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
                   --------
                     3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 58.757ns
+Passed: The following path meets requirements by 58.190ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[12]  (from C14M_c +)
-   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+   Source:         FF         Q              FS[15]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
 
-   Delay:              11.193ns  (30.6% logic, 69.4% route), 7 logic levels.
+   Delay:              11.574ns  (25.3% logic, 74.7% route), 6 logic levels.
 
  Constraint Details:
 
-     11.193ns physical path delay SLICE_3 to nRWE_MGIOL meets
-     69.930ns delay constraint less
-     -0.173ns skew and
-      0.153ns DO_SET requirement (totaling 69.950ns) by 58.757ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_3 (from C14M_c)
-ROUTE        22     1.463       R2C8C.Q1 to       R3C6A.A1 FS[12]
-CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 SLICE_97
-ROUTE         2     0.702       R3C6A.F1 to       R3C6A.B0 N_456
-CTOF_DEL    ---     0.495       R3C6A.B0 to       R3C6A.F0 SLICE_97
-ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
-CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
-ROUTE         3     0.453       R3C9C.F1 to       R3C9C.C0 N_628
-CTOF_DEL    ---     0.495       R3C9C.C0 to       R3C9C.F0 SLICE_75
-ROUTE         2     0.993       R3C9C.F0 to       R5C9A.A1 N_640
-CTOF_DEL    ---     0.495       R5C9A.A1 to       R5C9A.F1 SLICE_71
-ROUTE         1     0.623       R5C9A.F1 to      R5C10B.D0 un1_nCS61_1_i
-CTOF_DEL    ---     0.495      R5C10B.D0 to      R5C10B.F0 SLICE_115
-ROUTE         1     2.192      R5C10B.F0 to   IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
-                  --------
-                   11.193   (30.6% logic, 69.4% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to nRWE_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_R7D.CLK C14M_c
-                  --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.784ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        wb_adr[0]  (to C14M_c +)
-
-   Delay:              10.980ns  (26.7% logic, 73.3% route), 6 logic levels.
-
- Constraint Details:
-
-     10.980ns physical path delay SLICE_33 to SLICE_35 meets
+     11.574ns physical path delay SLICE_1 to ram2e_ufm/SLICE_47 meets
      69.930ns delay constraint less
       0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.784ns
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.190ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to SLICE_35:
+      Data path SLICE_1 to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R4C9D.CLK to       R4C9D.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     1.676       R4C9D.Q0 to       R6C9B.C0 S[0]
-CTOF_DEL    ---     0.495       R6C9B.C0 to       R6C9B.F0 SLICE_47
-ROUTE         7     2.435       R6C9B.F0 to       R4C5B.B0 S_RNII9DO1[1]
-CTOF_DEL    ---     0.495       R4C5B.B0 to       R4C5B.F0 SLICE_73
-ROUTE         8     1.931       R4C5B.F0 to       R4C4C.D0 N_455
-CTOF_DEL    ---     0.495       R4C4C.D0 to       R4C4C.F0 SLICE_89
-ROUTE         1     0.626       R4C4C.F0 to       R4C4A.D0 N_378
-CTOF_DEL    ---     0.495       R4C4A.D0 to       R4C4A.F0 SLICE_85
-ROUTE         1     1.385       R4C4A.F0 to       R2C4B.D0 wb_adr_7_0_4[0]
-CTOF_DEL    ---     0.495       R2C4B.D0 to       R2C4B.F0 SLICE_35
-ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 wb_adr_7[0] (to C14M_c)
+REG_DEL     ---     0.452     R2C11A.CLK to      R2C11A.Q0 SLICE_1 (from C14M_c)
+ROUTE         9     2.239      R2C11A.Q0 to       R6C9B.C1 FS[15]
+CTOF_DEL    ---     0.495       R6C9B.C1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
+ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
+CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
+ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
+CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                   --------
-                   10.980   (26.7% logic, 73.3% route), 6 logic levels.
+                   11.574   (25.3% logic, 74.7% route), 6 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_33:
+      Source Clock Path C14M to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R4C9D.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to     R2C11A.CLK C14M_c
                   --------
                     3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_35:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R2C4B.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
                   --------
                     3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
 
-Passed: The following path meets requirements by 29.415ns (weighted slack = 58.830ns)
+Passed: The following path meets requirements by 58.271ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              11.493ns  (29.8% logic, 70.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.493ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.271ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q0 SLICE_34 (from C14M_c)
+ROUTE        50     0.674      R6C10D.Q0 to      R6C10A.D0 S[2]
+CTOF_DEL    ---     0.495      R6C10A.D0 to      R6C10A.F0 SLICE_35
+ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
+CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
+ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
+CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
+ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
+CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   11.493   (29.8% logic, 70.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.733ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
    Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        Dout_0io[0]  (to C14M_c -)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[2]  (to C14M_c +)
 
-   Delay:               5.676ns  (16.7% logic, 83.3% route), 2 logic levels.
+   Delay:              11.031ns  (26.5% logic, 73.5% route), 6 logic levels.
 
  Constraint Details:
 
-      5.676ns physical path delay SLICE_33 to Dout[0]_MGIOL meets
-     34.965ns delay constraint less
-     -0.173ns skew and
-      0.047ns CE_SET requirement (totaling 35.091ns) by 29.415ns
+     11.031ns physical path delay SLICE_33 to ram2e_ufm/SLICE_53 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.733ns
 
  Physical Path Details:
 
-      Data path SLICE_33 to Dout[0]_MGIOL:
+      Data path SLICE_33 to ram2e_ufm/SLICE_53:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452      R4C9D.CLK to       R4C9D.Q0 SLICE_33 (from C14M_c)
-ROUTE        30     1.881       R4C9D.Q0 to       R6C8A.A1 S[0]
-CTOF_DEL    ---     0.495       R6C8A.A1 to       R6C8A.F1 SLICE_20
-ROUTE        17     2.848       R6C8A.F1 to     IOL_B4D.CE N_576_i (to C14M_c)
+REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
+CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
+ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
+CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
+ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
+CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
+ROUTE         2     0.758       R3C4C.F1 to       R2C4B.C0 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
+CTOF_DEL    ---     0.495       R2C4B.C0 to       R2C4B.F0 ram2e_ufm/SLICE_53
+ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 ram2e_ufm/wb_dati_7[2] (to C14M_c)
                   --------
-                    5.676   (16.7% logic, 83.3% route), 2 logic levels.
+                   11.031   (26.5% logic, 73.5% route), 6 logic levels.
 
  Clock Skew Details: 
 
       Source Clock Path C14M to SLICE_33:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.070       62.PADDI to      R4C9D.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
                   --------
                     3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to Dout[0]_MGIOL:
+      Destination Clock Path C14M to ram2e_ufm/SLICE_53:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     3.243       62.PADDI to    IOL_B4D.CLK C14M_c
+ROUTE        89     3.070       62.PADDI to      R2C4B.CLK C14M_c
                   --------
-                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
 
-Report:   79.592MHz is the maximum frequency for this preference.
+
+Passed: The following path meets requirements by 58.733ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[5]  (to C14M_c +)
+
+   Delay:              11.031ns  (26.5% logic, 73.5% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.031ns physical path delay SLICE_33 to ram2e_ufm/SLICE_54 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.733ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to ram2e_ufm/SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
+CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
+ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
+CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
+ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
+CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
+ROUTE         2     0.758       R3C4C.F1 to       R2C4D.C1 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
+CTOF_DEL    ---     0.495       R2C4D.C1 to       R2C4D.F1 ram2e_ufm/SLICE_54
+ROUTE         1     0.000       R2C4D.F1 to      R2C4D.DI1 ram2e_ufm/wb_dati_7[5] (to C14M_c)
+                  --------
+                   11.031   (26.5% logic, 73.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R2C4D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.739ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[5]  (to C14M_c +)
+
+   Delay:              11.025ns  (31.0% logic, 69.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.025ns physical path delay SLICE_34 to ram2e_ufm/SLICE_54 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.739ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
+CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
+ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
+CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
+ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
+CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
+ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
+CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
+ROUTE         2     0.758       R3C4C.F1 to       R2C4D.C1 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
+CTOF_DEL    ---     0.495       R2C4D.C1 to       R2C4D.F1 ram2e_ufm/SLICE_54
+ROUTE         1     0.000       R2C4D.F1 to      R2C4D.DI1 ram2e_ufm/wb_dati_7[5] (to C14M_c)
+                  --------
+                   11.025   (31.0% logic, 69.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_54:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R2C4D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.739ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_dati[2]  (to C14M_c +)
+
+   Delay:              11.025ns  (31.0% logic, 69.0% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.025ns physical path delay SLICE_34 to ram2e_ufm/SLICE_53 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.739ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_53:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
+CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
+ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
+CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
+ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
+CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
+ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
+CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
+ROUTE         2     0.758       R3C4C.F1 to       R2C4B.C0 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
+CTOF_DEL    ---     0.495       R2C4B.C0 to       R2C4B.F0 ram2e_ufm/SLICE_53
+ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 ram2e_ufm/wb_dati_7[2] (to C14M_c)
+                  --------
+                   11.025   (31.0% logic, 69.0% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_53:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R2C4B.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.780ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              10.984ns  (26.6% logic, 73.4% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.984ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.780ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
+ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
+CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.182       R6C9B.F1 to       R2C5A.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C5A.C1 to       R2C5A.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.413       R2C5A.F1 to       R4C5B.D0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R4C5B.D0 to       R4C5B.F0 ram2e_ufm/SLICE_126
+ROUTE         1     0.436       R4C5B.F0 to       R4C5A.C0 ram2e_ufm/N_753
+CTOF_DEL    ---     0.495       R4C5A.C0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   10.984   (26.6% logic, 73.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.786ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[3]  (from C14M_c +)
+   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
+
+   Delay:              10.978ns  (31.2% logic, 68.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     10.978ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.786ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
+ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
+CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
+ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
+CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
+ROUTE         8     2.182       R6C9B.F1 to       R2C5A.C1 ram2e_ufm/N_777
+CTOF_DEL    ---     0.495       R2C5A.C1 to       R2C5A.F1 ram2e_ufm/SLICE_98
+ROUTE         5     1.413       R2C5A.F1 to       R4C5B.D0 ram2e_ufm/N_781
+CTOF_DEL    ---     0.495       R4C5B.D0 to       R4C5B.F0 ram2e_ufm/SLICE_126
+ROUTE         1     0.436       R4C5B.F0 to       R4C5A.C0 ram2e_ufm/N_753
+CTOF_DEL    ---     0.495       R4C5A.C0 to       R4C5A.F0 ram2e_ufm/SLICE_86
+ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
+CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
+ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
+                  --------
+                   10.978   (31.2% logic, 68.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   83.389MHz is the maximum frequency for this preference.
 
 <A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
 --------------
@@ -589,7 +603,7 @@ Report:   79.592MHz is the maximum frequency for this preference.
 Preference                              |   Constraint|       Actual|Levels
 ----------------------------------------------------------------------------
                                         |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   79.592 MHz|   7  
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   83.389 MHz|   6  
                                         |             |             |
 ----------------------------------------------------------------------------
 
@@ -602,7 +616,7 @@ All preferences were met.
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -612,11 +626,11 @@ Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 --------------------------------------------------------------------------------
 <A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
-Thu Sep 21 05:35:07 2023
+Thu Dec 28 23:10:16 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -626,7 +640,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
 
 <A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
 ------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
 Design file:     ram2e_lcmxo2_640hc_impl1.ncd
 Preference file: ram2e_lcmxo2_640hc_impl1.prf
 Device,speed:    LCMXO2-640HC,m
@@ -635,7 +649,7 @@ Report level:    verbose report, limited to 10 items per preference
 
 <A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
 
-<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1491 items scored, 0 timing errors detected.
+<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI>            1611 items scored, 0 timing errors detected.
 
 BLOCK ASYNCPATHS
 BLOCK RESETPATHS
@@ -645,137 +659,51 @@ BLOCK RESETPATHS
 
 ================================================================================
 <A name="par_twr_pref_1_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1491 items scored, 0 timing errors detected.
+            1611 items scored, 0 timing errors detected.
 --------------------------------------------------------------------------------
 
 
-Passed: The following path meets requirements by 0.346ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              wb_dati[3]  (from C14M_c +)
-   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
-
-   Delay:               0.305ns  (43.6% logic, 56.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.305ns physical path delay SLICE_41 to ufmefb/EFBInst_0 meets
-     -0.095ns WBDATI_HLD and
-      0.000ns delay constraint less
-     -0.054ns skew requirement (totaling -0.041ns) by 0.346ns
-
- Physical Path Details:
-
-      Data path SLICE_41 to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C3B.CLK to       R2C3B.Q1 SLICE_41 (from C14M_c)
-ROUTE         1     0.172       R2C3B.Q1 to    EFB.WBDATI3 wb_dati[3] (to C14M_c)
-                  --------
-                    0.305   (43.6% logic, 56.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_41:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C3B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.113       62.PADDI to     EFB.WBCLKI C14M_c
-                  --------
-                    1.113   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.348ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              wb_dati[4]  (from C14M_c +)
-   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
-
-   Delay:               0.305ns  (43.6% logic, 56.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.305ns physical path delay SLICE_42 to ufmefb/EFBInst_0 meets
-     -0.097ns WBDATI_HLD and
-      0.000ns delay constraint less
-     -0.054ns skew requirement (totaling -0.043ns) by 0.348ns
-
- Physical Path Details:
-
-      Data path SLICE_42 to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C3D.CLK to       R2C3D.Q0 SLICE_42 (from C14M_c)
-ROUTE         1     0.172       R2C3D.Q0 to    EFB.WBDATI4 wb_dati[4] (to C14M_c)
-                  --------
-                    0.305   (43.6% logic, 56.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_42:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C3D.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.113       62.PADDI to     EFB.WBCLKI C14M_c
-                  --------
-                    1.113   (0.0% logic, 100.0% route), 0 logic levels.
-
-
 Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[0]  (from C14M_c +)
-   Destination:    FF         Data in        FS[0]  (to C14M_c +)
+   Source:         FF         Q              FS[15]  (from C14M_c +)
+   Destination:    FF         Data in        FS[15]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
  Constraint Details:
 
-      0.366ns physical path delay SLICE_0 to SLICE_0 meets
+      0.366ns physical path delay SLICE_1 to SLICE_1 meets
      -0.013ns DIN_HLD and
       0.000ns delay constraint less
       0.000ns skew requirement (totaling -0.013ns) by 0.379ns
 
  Physical Path Details:
 
-      Data path SLICE_0 to SLICE_0:
+      Data path SLICE_1 to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C7A.CLK to       R2C7A.Q1 SLICE_0 (from C14M_c)
-ROUTE         5     0.132       R2C7A.Q1 to       R2C7A.A1 FS[0]
-CTOF_DEL    ---     0.101       R2C7A.A1 to       R2C7A.F1 SLICE_0
-ROUTE         1     0.000       R2C7A.F1 to      R2C7A.DI1 FS_s[0] (to C14M_c)
+REG_DEL     ---     0.133     R2C11A.CLK to      R2C11A.Q0 SLICE_1 (from C14M_c)
+ROUTE         9     0.132      R2C11A.Q0 to      R2C11A.A0 FS[15]
+CTOF_DEL    ---     0.101      R2C11A.A0 to      R2C11A.F0 SLICE_1
+ROUTE         1     0.000      R2C11A.F0 to     R2C11A.DI0 FS_s[15] (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_0:
+      Source Clock Path C14M to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C7A.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C11A.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_0:
+      Destination Clock Path C14M to SLICE_1:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C7A.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C11A.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -784,188 +712,8 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              CmdBitbangMXO2  (from C14M_c +)
-   Destination:    FF         Data in        CmdBitbangMXO2  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_12 to SLICE_12 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_12 to SLICE_12:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R4C6C.CLK to       R4C6C.Q0 SLICE_12 (from C14M_c)
-ROUTE         2     0.132       R4C6C.Q0 to       R4C6C.A0 CmdBitbangMXO2
-CTOF_DEL    ---     0.101       R4C6C.A0 to       R4C6C.F0 SLICE_12
-ROUTE         1     0.000       R4C6C.F0 to      R4C6C.DI0 CmdBitbangMXO2_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_12:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R4C6C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_12:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R4C6C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdLEDSet  (from C14M_c +)
-   Destination:    FF         Data in        CmdLEDSet  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_15 to SLICE_15 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_15 to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C5B.CLK to       R5C5B.Q0 SLICE_15 (from C14M_c)
-ROUTE         2     0.132       R5C5B.Q0 to       R5C5B.A0 CmdLEDSet
-CTOF_DEL    ---     0.101       R5C5B.A0 to       R5C5B.F0 SLICE_15
-ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 CmdLEDSet_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R5C5B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_15:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R5C5B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdRWMaskSet  (from C14M_c +)
-   Destination:    FF         Data in        CmdRWMaskSet  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_16 to SLICE_16 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_16 to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C5C.CLK to       R5C5C.Q0 SLICE_16 (from C14M_c)
-ROUTE         2     0.132       R5C5C.Q0 to       R5C5C.A0 CmdRWMaskSet
-CTOF_DEL    ---     0.101       R5C5C.A0 to       R5C5C.F0 SLICE_16
-ROUTE         1     0.000       R5C5C.F0 to      R5C5C.DI0 CmdRWMaskSet_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R5C5C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_16:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R5C5C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdSetRWBankFFLED  (from C14M_c +)
-   Destination:    FF         Data in        CmdSetRWBankFFLED  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_17 to SLICE_17 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_17 to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C5C.CLK to       R6C5C.Q0 SLICE_17 (from C14M_c)
-ROUTE         2     0.132       R6C5C.Q0 to       R6C5C.A0 CmdSetRWBankFFLED
-CTOF_DEL    ---     0.101       R6C5C.A0 to       R6C5C.F0 SLICE_17
-ROUTE         1     0.000       R6C5C.F0 to      R6C5C.DI0 CmdSetRWBankFFLED_4 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R6C5C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_17:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R6C5C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdSetRWBankFFMXO2  (from C14M_c +)
-   Destination:    FF         Data in        CmdSetRWBankFFMXO2  (to C14M_c +)
+   Source:         FF         Q              CmdTout[2]  (from C14M_c +)
+   Destination:    FF         Data in        CmdTout[2]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -981,10 +729,10 @@ Passed: The following path meets requirements by 0.379ns
       Data path SLICE_18 to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R6C6D.CLK to       R6C6D.Q0 SLICE_18 (from C14M_c)
-ROUTE         2     0.132       R6C6D.Q0 to       R6C6D.A0 CmdSetRWBankFFMXO2
-CTOF_DEL    ---     0.101       R6C6D.A0 to       R6C6D.F0 SLICE_18
-ROUTE         1     0.000       R6C6D.F0 to      R6C6D.DI0 CmdSetRWBankFFMXO2_4 (to C14M_c)
+REG_DEL     ---     0.133      R5C9B.CLK to       R5C9B.Q1 SLICE_18 (from C14M_c)
+ROUTE         2     0.132       R5C9B.Q1 to       R5C9B.A1 CmdTout[2]
+CTOF_DEL    ---     0.101       R5C9B.A1 to       R5C9B.F1 SLICE_18
+ROUTE         1     0.000       R5C9B.F1 to      R5C9B.DI1 N_369_i (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -993,14 +741,14 @@ ROUTE         1     0.000       R6C6D.F0 to      R6C6D.DI0 CmdSetRWBankFFMXO2_4
       Source Clock Path C14M to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R6C6D.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
       Destination Clock Path C14M to SLICE_18:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R6C6D.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -1009,8 +757,188 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              FS[11]  (from C14M_c +)
-   Destination:    FF         Data in        FS[11]  (to C14M_c +)
+   Source:         FF         Q              CmdTout[1]  (from C14M_c +)
+   Destination:    FF         Data in        CmdTout[1]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_18 to SLICE_18 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9B.CLK to       R5C9B.Q0 SLICE_18 (from C14M_c)
+ROUTE         3     0.132       R5C9B.Q0 to       R5C9B.A0 CmdTout[1]
+CTOF_DEL    ---     0.101       R5C9B.A0 to       R5C9B.F0 SLICE_18
+ROUTE         1     0.000       R5C9B.F0 to      R5C9B.DI0 N_368_i (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[13]  (from C14M_c +)
+   Destination:    FF         Data in        FS[13]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_2 to SLICE_2 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R2C10D.CLK to      R2C10D.Q0 SLICE_2 (from C14M_c)
+ROUTE        19     0.132      R2C10D.Q0 to      R2C10D.A0 FS[13]
+CTOF_DEL    ---     0.101      R2C10D.A0 to      R2C10D.F0 SLICE_2
+ROUTE         1     0.000      R2C10D.F0 to     R2C10D.DI0 FS_s[13] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R2C10D.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R2C10D.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA[9]  (from C14M_c +)
+   Destination:    FF         Data in        RA[9]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_24 to SLICE_24 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_24 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C11A.CLK to      R5C11A.Q1 SLICE_24 (from C14M_c)
+ROUTE         2     0.132      R5C11A.Q1 to      R5C11A.A1 RA[9]
+CTOF_DEL    ---     0.101      R5C11A.A1 to      R5C11A.F1 SLICE_24
+ROUTE         1     0.000      R5C11A.F1 to     R5C11A.DI1 RA_35[9] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R5C11A.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R5C11A.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RA[11]  (from C14M_c +)
+   Destination:    FF         Data in        RA[11]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_25 to SLICE_25 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_25 to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10B.CLK to      R5C10B.Q1 SLICE_25 (from C14M_c)
+ROUTE         2     0.132      R5C10B.Q1 to      R5C10B.A1 RA[11]
+CTOF_DEL    ---     0.101      R5C10B.A1 to      R5C10B.F1 SLICE_25
+ROUTE         1     0.000      R5C10B.F1 to     R5C10B.DI1 RA_35[11] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R5C10B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R5C10B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[12]  (from C14M_c +)
+   Destination:    FF         Data in        FS[12]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -1026,10 +954,10 @@ Passed: The following path meets requirements by 0.379ns
       Data path SLICE_3 to SLICE_3:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
-ROUTE        19     0.132       R2C8C.Q0 to       R2C8C.A0 FS[11]
-CTOF_DEL    ---     0.101       R2C8C.A0 to       R2C8C.F0 SLICE_3
-ROUTE         1     0.000       R2C8C.F0 to      R2C8C.DI0 FS_s[11] (to C14M_c)
+REG_DEL     ---     0.133     R2C10C.CLK to      R2C10C.Q1 SLICE_3 (from C14M_c)
+ROUTE        24     0.132      R2C10C.Q1 to      R2C10C.A1 FS[12]
+CTOF_DEL    ---     0.101      R2C10C.A1 to      R2C10C.F1 SLICE_3
+ROUTE         1     0.000      R2C10C.F1 to     R2C10C.DI1 FS_s[12] (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
@@ -1038,14 +966,14 @@ ROUTE         1     0.000       R2C8C.F0 to      R2C8C.DI0 FS_s[11] (to C14M_c)
       Source Clock Path C14M to SLICE_3:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C8C.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C10C.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
       Destination Clock Path C14M to SLICE_3:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C8C.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C10C.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -1054,43 +982,133 @@ Passed: The following path meets requirements by 0.379ns
 
  Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
-   Source:         FF         Q              Ready  (from C14M_c +)
-   Destination:    FF         Data in        Ready  (to C14M_c +)
+   Source:         FF         Q              FS[10]  (from C14M_c +)
+   Destination:    FF         Data in        FS[10]  (to C14M_c +)
 
    Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
 
  Constraint Details:
 
-      0.366ns physical path delay SLICE_32 to SLICE_32 meets
+      0.366ns physical path delay SLICE_4 to SLICE_4 meets
      -0.013ns DIN_HLD and
       0.000ns delay constraint less
       0.000ns skew requirement (totaling -0.013ns) by 0.379ns
 
  Physical Path Details:
 
-      Data path SLICE_32 to SLICE_32:
+      Data path SLICE_4 to SLICE_4:
 
    Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C9C.CLK to       R2C9C.Q0 SLICE_32 (from C14M_c)
-ROUTE         2     0.132       R2C9C.Q0 to       R2C9C.A0 Ready
-CTOF_DEL    ---     0.101       R2C9C.A0 to       R2C9C.F0 SLICE_32
-ROUTE         1     0.000       R2C9C.F0 to      R2C9C.DI0 N_876_0 (to C14M_c)
+REG_DEL     ---     0.133     R2C10B.CLK to      R2C10B.Q1 SLICE_4 (from C14M_c)
+ROUTE        19     0.132      R2C10B.Q1 to      R2C10B.A1 FS[10]
+CTOF_DEL    ---     0.101      R2C10B.A1 to      R2C10B.F1 SLICE_4
+ROUTE         1     0.000      R2C10B.F1 to     R2C10B.DI1 FS_s[10] (to C14M_c)
                   --------
                     0.366   (63.9% logic, 36.1% route), 2 logic levels.
 
  Clock Skew Details: 
 
-      Source Clock Path C14M to SLICE_32:
+      Source Clock Path C14M to SLICE_4:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C9C.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C10B.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
-      Destination Clock Path C14M to SLICE_32:
+      Destination Clock Path C14M to SLICE_4:
 
    Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        84     1.059       62.PADDI to      R2C9C.CLK C14M_c
+ROUTE        89     1.059       62.PADDI to     R2C10B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[7]  (from C14M_c +)
+   Destination:    FF         Data in        FS[7]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_5 to SLICE_5 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R2C10A.CLK to      R2C10A.Q0 SLICE_5 (from C14M_c)
+ROUTE         4     0.132      R2C10A.Q0 to      R2C10A.A0 FS[7]
+CTOF_DEL    ---     0.101      R2C10A.A0 to      R2C10A.F0 SLICE_5
+ROUTE         1     0.000      R2C10A.F0 to     R2C10A.DI0 FS_s[7] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R2C10A.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to     R2C10A.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[6]  (from C14M_c +)
+   Destination:    FF         Data in        FS[6]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_6 to SLICE_6 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_6 to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C9D.CLK to       R2C9D.Q1 SLICE_6 (from C14M_c)
+ROUTE         4     0.132       R2C9D.Q1 to       R2C9D.A1 FS[6]
+CTOF_DEL    ---     0.101       R2C9D.A1 to       R2C9D.F1 SLICE_6
+ROUTE         1     0.000       R2C9D.F1 to      R2C9D.DI1 FS_s[6] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to      R2C9D.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_6:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        89     1.059       62.PADDI to      R2C9D.CLK C14M_c
                   --------
                     1.059   (0.0% logic, 100.0% route), 0 logic levels.
 
@@ -1100,7 +1118,7 @@ ROUTE        84     1.059       62.PADDI to      R2C9C.CLK C14M_c
 Preference(MIN Delays)                  |   Constraint|       Actual|Levels
 ----------------------------------------------------------------------------
                                         |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   1  
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   2  
                                         |             |             |
 ----------------------------------------------------------------------------
 
@@ -1113,7 +1131,7 @@ All preferences were met.
 
 Found 1 clocks:
 
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
    Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
 
 
@@ -1123,7 +1141,7 @@ Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
 Timing errors: 0  Score: 0
 Cumulative negative slack: 0
 
-Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
 
 
 
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf
index 5fa7701..a190de7 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf
@@ -1,7 +1,7 @@
 (DELAYFILE
   (SDFVERSION "3.0")
   (DESIGN "RAM2E")
-  (DATE "Thu Sep 21 05:35:15 2023")
+  (DATE "Thu Dec 28 23:10:23 2023")
   (VENDOR "Lattice")
   (PROGRAM "ldbanno")
   (VERSION "Diamond (64-bit) 3.12.1.454")
@@ -233,9 +233,30 @@
     (INSTANCE SLICE_9)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_10")
+    (INSTANCE SLICE_10)
+    (DELAY
+      (ABSOLUTE
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -251,8 +272,30 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_10")
-    (INSTANCE SLICE_10)
+    (CELLTYPE "SLICE_11")
+    (INSTANCE SLICE_11)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_12")
+    (INSTANCE SLICE_12)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -261,6 +304,7 @@
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -279,13 +323,15 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_11")
-    (INSTANCE SLICE_11)
+    (CELLTYPE "SLICE_13")
+    (INSTANCE SLICE_13)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
@@ -303,60 +349,11 @@
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
   )
-  (CELL
-    (CELLTYPE "SLICE_12")
-    (INSTANCE SLICE_12)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_13")
-    (INSTANCE SLICE_13)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
   (CELL
     (CELLTYPE "SLICE_14")
     (INSTANCE SLICE_14)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -381,12 +378,12 @@
     (INSTANCE SLICE_15)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
       )
@@ -406,6 +403,7 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
@@ -429,12 +427,12 @@
     (INSTANCE SLICE_17)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
       )
@@ -451,30 +449,6 @@
   (CELL
     (CELLTYPE "SLICE_18")
     (INSTANCE SLICE_18)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-        (IOPATH CLK Q0 (392:422:452)(392:422:452))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1250:1250:1250))
-      (WIDTH (negedge CLK) (1250:1250:1250))
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_19")
-    (INSTANCE SLICE_19)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -498,6 +472,29 @@
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
   )
+  (CELL
+    (CELLTYPE "SLICE_19")
+    (INSTANCE SLICE_19)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37))
+      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge LSR) (4000:4000:4000))
+      (WIDTH (negedge LSR) (4000:4000:4000))
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
   (CELL
     (CELLTYPE "SLICE_20")
     (INSTANCE SLICE_20)
@@ -512,10 +509,13 @@
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -531,12 +531,15 @@
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
@@ -552,9 +555,10 @@
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -575,11 +579,11 @@
     (INSTANCE SLICE_23)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -600,10 +604,11 @@
     (INSTANCE SLICE_24)
     (DELAY
       (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -625,11 +630,13 @@
     (INSTANCE SLICE_25)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -651,9 +658,9 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -676,7 +683,7 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -700,11 +707,11 @@
     (INSTANCE SLICE_28)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -725,8 +732,8 @@
     (INSTANCE SLICE_29)
     (DELAY
       (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -751,9 +758,9 @@
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -775,6 +782,7 @@
     (INSTANCE SLICE_31)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
@@ -878,19 +886,17 @@
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+      (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141))
     )
     (TIMINGCHECK
+      (WIDTH (posedge LSR) (4000:4000:4000))
+      (WIDTH (negedge LSR) (4000:4000:4000))
       (WIDTH (posedge CLK) (1250:1250:1250))
       (WIDTH (negedge CLK) (1250:1250:1250))
     )
@@ -900,18 +906,19 @@
     (INSTANCE SLICE_36)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -923,20 +930,19 @@
     (INSTANCE SLICE_37)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
-        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
-      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1250:1250:1250))
@@ -948,8 +954,154 @@
     (INSTANCE SLICE_38)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_39")
+    (INSTANCE ram2e_ufm\/SLICE_39)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_40")
+    (INSTANCE ram2e_ufm\/SLICE_40)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_41")
+    (INSTANCE ram2e_ufm\/SLICE_41)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_42")
+    (INSTANCE ram2e_ufm\/SLICE_42)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_43")
+    (INSTANCE ram2e_ufm\/SLICE_43)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_44")
+    (INSTANCE ram2e_ufm\/SLICE_44)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
@@ -968,21 +1120,22 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_39")
-    (INSTANCE SLICE_39)
+    (CELLTYPE "ram2e_ufm_SLICE_45")
+    (INSTANCE ram2e_ufm\/SLICE_45)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
       )
     )
     (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
       (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
     )
@@ -992,8 +1145,33 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_40")
-    (INSTANCE SLICE_40)
+    (CELLTYPE "ram2e_ufm_SLICE_46")
+    (INSTANCE ram2e_ufm\/SLICE_46)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_47")
+    (INSTANCE ram2e_ufm\/SLICE_47)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1019,8 +1197,31 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_41")
-    (INSTANCE SLICE_41)
+    (CELLTYPE "ram2e_ufm_SLICE_48")
+    (INSTANCE ram2e_ufm\/SLICE_48)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_49")
+    (INSTANCE ram2e_ufm\/SLICE_49)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1028,6 +1229,29 @@
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_50")
+    (INSTANCE ram2e_ufm\/SLICE_50)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
@@ -1045,8 +1269,32 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_42")
-    (INSTANCE SLICE_42)
+    (CELLTYPE "ram2e_ufm_SLICE_51")
+    (INSTANCE ram2e_ufm\/SLICE_51)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_52")
+    (INSTANCE ram2e_ufm\/SLICE_52)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1072,8 +1320,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_43")
-    (INSTANCE SLICE_43)
+    (CELLTYPE "ram2e_ufm_SLICE_53")
+    (INSTANCE ram2e_ufm\/SLICE_53)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1082,6 +1330,7 @@
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH A0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
         (IOPATH CLK Q1 (392:422:452)(392:422:452))
@@ -1098,12 +1347,67 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_44")
-    (INSTANCE SLICE_44)
+    (CELLTYPE "ram2e_ufm_SLICE_54")
+    (INSTANCE ram2e_ufm\/SLICE_54)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_55")
+    (INSTANCE ram2e_ufm\/SLICE_55)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+        (IOPATH CLK Q0 (392:422:452)(392:422:452))
+        (IOPATH CLK Q1 (392:422:452)(392:422:452))
+      )
+    )
+    (TIMINGCHECK
+      (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11))
+      (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79))
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1250:1250:1250))
+      (WIDTH (negedge CLK) (1250:1250:1250))
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_56")
+    (INSTANCE ram2e_ufm\/SLICE_56)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1125,13 +1429,15 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_45")
-    (INSTANCE SLICE_45)
+    (CELLTYPE "ram2e_ufm_SLICE_57")
+    (INSTANCE ram2e_ufm\/SLICE_57)
     (DELAY
       (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
         (IOPATH CLK Q0 (392:422:452)(392:422:452))
       )
@@ -1148,8 +1454,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_46")
-    (INSTANCE SLICE_46)
+    (CELLTYPE "ram2e_ufm_SLICE_58")
+    (INSTANCE ram2e_ufm\/SLICE_58)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1173,8 +1479,54 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_47")
-    (INSTANCE SLICE_47)
+    (CELLTYPE "ram2e_ufm_SUM0_i_m3_0_SLICE_59")
+    (INSTANCE ram2e_ufm\/SUM0_i_m3_0\/SLICE_59)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH D0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60")
+    (INSTANCE ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_CKE_7_SLICE_61")
+    (INSTANCE ram2e_ufm\/CKE_7\/SLICE_61)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH C1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A1 OFX0 (457:589:721)(457:589:721))
+        (IOPATH D0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH B0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH A0 OFX0 (457:589:721)(457:589:721))
+        (IOPATH M0 OFX0 (322:349:376)(322:349:376))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_62")
+    (INSTANCE ram2e_ufm\/SLICE_62)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1189,8 +1541,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_48")
-    (INSTANCE SLICE_48)
+    (CELLTYPE "ram2e_ufm_SLICE_63")
+    (INSTANCE ram2e_ufm\/SLICE_63)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1205,8 +1557,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_49")
-    (INSTANCE SLICE_49)
+    (CELLTYPE "ram2e_ufm_SLICE_64")
+    (INSTANCE ram2e_ufm\/SLICE_64)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_65")
+    (INSTANCE ram2e_ufm\/SLICE_65)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1221,8 +1588,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_50")
-    (INSTANCE SLICE_50)
+    (CELLTYPE "ram2e_ufm_SLICE_66")
+    (INSTANCE ram2e_ufm\/SLICE_66)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1237,8 +1604,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_51")
-    (INSTANCE SLICE_51)
+    (CELLTYPE "ram2e_ufm_SLICE_67")
+    (INSTANCE ram2e_ufm\/SLICE_67)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_68")
+    (INSTANCE ram2e_ufm\/SLICE_68)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1253,8 +1635,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_52")
-    (INSTANCE SLICE_52)
+    (CELLTYPE "ram2e_ufm_SLICE_69")
+    (INSTANCE ram2e_ufm\/SLICE_69)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1269,8 +1651,52 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_53")
-    (INSTANCE SLICE_53)
+    (CELLTYPE "ram2e_ufm_SLICE_70")
+    (INSTANCE ram2e_ufm\/SLICE_70)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_71")
+    (INSTANCE ram2e_ufm\/SLICE_71)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_72")
+    (INSTANCE ram2e_ufm\/SLICE_72)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_73")
+    (INSTANCE ram2e_ufm\/SLICE_73)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1285,8 +1711,81 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_54")
-    (INSTANCE SLICE_54)
+    (CELLTYPE "ram2e_ufm_SLICE_74")
+    (INSTANCE ram2e_ufm\/SLICE_74)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_75")
+    (INSTANCE ram2e_ufm\/SLICE_75)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_76")
+    (INSTANCE ram2e_ufm\/SLICE_76)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_77")
+    (INSTANCE ram2e_ufm\/SLICE_77)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_78")
+    (INSTANCE ram2e_ufm\/SLICE_78)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_79")
+    (INSTANCE ram2e_ufm\/SLICE_79)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1301,8 +1800,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_55")
-    (INSTANCE SLICE_55)
+    (CELLTYPE "ram2e_ufm_SLICE_80")
+    (INSTANCE ram2e_ufm\/SLICE_80)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1317,22 +1816,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_56")
-    (INSTANCE SLICE_56)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_57")
-    (INSTANCE SLICE_57)
+    (CELLTYPE "ram2e_ufm_SLICE_81")
+    (INSTANCE ram2e_ufm\/SLICE_81)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1347,8 +1832,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_58")
-    (INSTANCE SLICE_58)
+    (CELLTYPE "ram2e_ufm_SLICE_82")
+    (INSTANCE ram2e_ufm\/SLICE_82)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1363,8 +1848,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_59")
-    (INSTANCE SLICE_59)
+    (CELLTYPE "ram2e_ufm_SLICE_83")
+    (INSTANCE ram2e_ufm\/SLICE_83)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_84")
+    (INSTANCE ram2e_ufm\/SLICE_84)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1379,126 +1879,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_60")
-    (INSTANCE SLICE_60)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_61")
-    (INSTANCE SLICE_61)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_62")
-    (INSTANCE SLICE_62)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_63")
-    (INSTANCE SLICE_63)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_64")
-    (INSTANCE SLICE_64)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_65")
-    (INSTANCE SLICE_65)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_66")
-    (INSTANCE SLICE_66)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_67")
-    (INSTANCE SLICE_67)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_68")
-    (INSTANCE SLICE_68)
+    (CELLTYPE "ram2e_ufm_SLICE_85")
+    (INSTANCE ram2e_ufm\/SLICE_85)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1513,8 +1895,66 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_69")
-    (INSTANCE SLICE_69)
+    (CELLTYPE "ram2e_ufm_SLICE_86")
+    (INSTANCE ram2e_ufm\/SLICE_86)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_87")
+    (INSTANCE ram2e_ufm\/SLICE_87)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_88")
+    (INSTANCE ram2e_ufm\/SLICE_88)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_89")
+    (INSTANCE ram2e_ufm\/SLICE_89)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_90")
+    (INSTANCE ram2e_ufm\/SLICE_90)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1529,8 +1969,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_70")
-    (INSTANCE SLICE_70)
+    (CELLTYPE "ram2e_ufm_SLICE_91")
+    (INSTANCE ram2e_ufm\/SLICE_91)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1545,8 +1985,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_71")
-    (INSTANCE SLICE_71)
+    (CELLTYPE "ram2e_ufm_SLICE_92")
+    (INSTANCE ram2e_ufm\/SLICE_92)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1561,8 +2001,37 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_72")
-    (INSTANCE SLICE_72)
+    (CELLTYPE "ram2e_ufm_SLICE_93")
+    (INSTANCE ram2e_ufm\/SLICE_93)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_94")
+    (INSTANCE ram2e_ufm\/SLICE_94)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_95")
+    (INSTANCE ram2e_ufm\/SLICE_95)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1577,8 +2046,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_73")
-    (INSTANCE SLICE_73)
+    (CELLTYPE "ram2e_ufm_SLICE_96")
+    (INSTANCE ram2e_ufm\/SLICE_96)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1593,52 +2062,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_74")
-    (INSTANCE SLICE_74)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_75")
-    (INSTANCE SLICE_75)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_76")
-    (INSTANCE SLICE_76)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_77")
-    (INSTANCE SLICE_77)
+    (CELLTYPE "ram2e_ufm_SLICE_97")
+    (INSTANCE ram2e_ufm\/SLICE_97)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1652,11 +2077,26 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_78")
-    (INSTANCE SLICE_78)
+    (CELLTYPE "ram2e_ufm_SLICE_98")
+    (INSTANCE ram2e_ufm\/SLICE_98)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_99")
+    (INSTANCE ram2e_ufm\/SLICE_99)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
@@ -1666,36 +2106,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_79")
-    (INSTANCE SLICE_79)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_80")
-    (INSTANCE SLICE_80)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_81")
-    (INSTANCE SLICE_81)
+    (CELLTYPE "ram2e_ufm_SLICE_100")
+    (INSTANCE ram2e_ufm\/SLICE_100)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1710,8 +2122,93 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_82")
-    (INSTANCE SLICE_82)
+    (CELLTYPE "ram2e_ufm_SLICE_101")
+    (INSTANCE ram2e_ufm\/SLICE_101)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_102")
+    (INSTANCE ram2e_ufm\/SLICE_102)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_103")
+    (INSTANCE ram2e_ufm\/SLICE_103)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_104")
+    (INSTANCE ram2e_ufm\/SLICE_104)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_105")
+    (INSTANCE ram2e_ufm\/SLICE_105)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_106")
+    (INSTANCE ram2e_ufm\/SLICE_106)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_107")
+    (INSTANCE ram2e_ufm\/SLICE_107)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1726,8 +2223,140 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_83")
-    (INSTANCE SLICE_83)
+    (CELLTYPE "ram2e_ufm_SLICE_108")
+    (INSTANCE ram2e_ufm\/SLICE_108)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_109")
+    (INSTANCE ram2e_ufm\/SLICE_109)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_110")
+    (INSTANCE ram2e_ufm\/SLICE_110)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_111")
+    (INSTANCE ram2e_ufm\/SLICE_111)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_112")
+    (INSTANCE ram2e_ufm\/SLICE_112)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_113")
+    (INSTANCE ram2e_ufm\/SLICE_113)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_114")
+    (INSTANCE ram2e_ufm\/SLICE_114)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_115")
+    (INSTANCE ram2e_ufm\/SLICE_115)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_116")
+    (INSTANCE ram2e_ufm\/SLICE_116)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_117")
+    (INSTANCE ram2e_ufm\/SLICE_117)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1742,8 +2371,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_84")
-    (INSTANCE SLICE_84)
+    (CELLTYPE "ram2e_ufm_SLICE_118")
+    (INSTANCE ram2e_ufm\/SLICE_118)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1758,8 +2387,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_85")
-    (INSTANCE SLICE_85)
+    (CELLTYPE "ram2e_ufm_SLICE_119")
+    (INSTANCE ram2e_ufm\/SLICE_119)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1774,8 +2403,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_86")
-    (INSTANCE SLICE_86)
+    (CELLTYPE "ram2e_ufm_SLICE_120")
+    (INSTANCE ram2e_ufm\/SLICE_120)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1790,81 +2419,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_87")
-    (INSTANCE SLICE_87)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_88")
-    (INSTANCE SLICE_88)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_89")
-    (INSTANCE SLICE_89)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_90")
-    (INSTANCE SLICE_90)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_91")
-    (INSTANCE SLICE_91)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_92")
-    (INSTANCE SLICE_92)
+    (CELLTYPE "ram2e_ufm_SLICE_121")
+    (INSTANCE ram2e_ufm\/SLICE_121)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1879,8 +2435,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_93")
-    (INSTANCE SLICE_93)
+    (CELLTYPE "ram2e_ufm_SLICE_122")
+    (INSTANCE ram2e_ufm\/SLICE_122)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1895,8 +2451,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_94")
-    (INSTANCE SLICE_94)
+    (CELLTYPE "ram2e_ufm_SLICE_123")
+    (INSTANCE ram2e_ufm\/SLICE_123)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_124")
+    (INSTANCE ram2e_ufm\/SLICE_124)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1911,8 +2482,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_95")
-    (INSTANCE SLICE_95)
+    (CELLTYPE "ram2e_ufm_SLICE_125")
+    (INSTANCE ram2e_ufm\/SLICE_125)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -1927,80 +2498,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_96")
-    (INSTANCE SLICE_96)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_97")
-    (INSTANCE SLICE_97)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_98")
-    (INSTANCE SLICE_98)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_99")
-    (INSTANCE SLICE_99)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_100")
-    (INSTANCE SLICE_100)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_101")
-    (INSTANCE SLICE_101)
+    (CELLTYPE "ram2e_ufm_SLICE_126")
+    (INSTANCE ram2e_ufm\/SLICE_126)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2015,8 +2514,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_102")
-    (INSTANCE SLICE_102)
+    (CELLTYPE "ram2e_ufm_SLICE_127")
+    (INSTANCE ram2e_ufm\/SLICE_127)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2031,8 +2530,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_103")
-    (INSTANCE SLICE_103)
+    (CELLTYPE "ram2e_ufm_SLICE_128")
+    (INSTANCE ram2e_ufm\/SLICE_128)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_129")
+    (INSTANCE ram2e_ufm\/SLICE_129)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2047,8 +2561,22 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_104")
-    (INSTANCE SLICE_104)
+    (CELLTYPE "ram2e_ufm_SLICE_130")
+    (INSTANCE ram2e_ufm\/SLICE_130)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_131")
+    (INSTANCE ram2e_ufm\/SLICE_131)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2063,8 +2591,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_105")
-    (INSTANCE SLICE_105)
+    (CELLTYPE "ram2e_ufm_SLICE_132")
+    (INSTANCE ram2e_ufm\/SLICE_132)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2079,50 +2607,23 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_106")
-    (INSTANCE SLICE_106)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_107")
-    (INSTANCE SLICE_107)
+    (CELLTYPE "ram2e_ufm_SLICE_133")
+    (INSTANCE ram2e_ufm\/SLICE_133)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_108")
-    (INSTANCE SLICE_108)
-    (DELAY
-      (ABSOLUTE
         (IOPATH C1 F1 (367:431:495)(367:431:495))
         (IOPATH B1 F1 (367:431:495)(367:431:495))
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH D0 F0 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
       )
     )
   )
   (CELL
-    (CELLTYPE "SLICE_109")
-    (INSTANCE SLICE_109)
+    (CELLTYPE "ram2e_ufm_SLICE_134")
+    (INSTANCE ram2e_ufm\/SLICE_134)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2137,8 +2638,152 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_110")
-    (INSTANCE SLICE_110)
+    (CELLTYPE "ram2e_ufm_SLICE_135")
+    (INSTANCE ram2e_ufm\/SLICE_135)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_136")
+    (INSTANCE ram2e_ufm\/SLICE_136)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_137")
+    (INSTANCE ram2e_ufm\/SLICE_137)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_138")
+    (INSTANCE SLICE_138)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "SLICE_139")
+    (INSTANCE SLICE_139)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+        (IOPATH A0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_140")
+    (INSTANCE ram2e_ufm\/SLICE_140)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_141")
+    (INSTANCE ram2e_ufm\/SLICE_141)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_142")
+    (INSTANCE ram2e_ufm\/SLICE_142)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_143")
+    (INSTANCE ram2e_ufm\/SLICE_143)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_144")
+    (INSTANCE ram2e_ufm\/SLICE_144)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH D0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_145")
+    (INSTANCE ram2e_ufm\/SLICE_145)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH D1 F1 (367:431:495)(367:431:495))
+        (IOPATH C1 F1 (367:431:495)(367:431:495))
+        (IOPATH B1 F1 (367:431:495)(367:431:495))
+        (IOPATH A1 F1 (367:431:495)(367:431:495))
+        (IOPATH C0 F0 (367:431:495)(367:431:495))
+        (IOPATH B0 F0 (367:431:495)(367:431:495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "ram2e_ufm_SLICE_146")
+    (INSTANCE ram2e_ufm\/SLICE_146)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2153,22 +2798,8 @@
     )
   )
   (CELL
-    (CELLTYPE "SLICE_111")
-    (INSTANCE SLICE_111)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_112")
-    (INSTANCE SLICE_112)
+    (CELLTYPE "ram2e_ufm_SLICE_147")
+    (INSTANCE ram2e_ufm\/SLICE_147)
     (DELAY
       (ABSOLUTE
         (IOPATH D1 F1 (367:431:495)(367:431:495))
@@ -2177,103 +2808,6 @@
         (IOPATH A1 F1 (367:431:495)(367:431:495))
         (IOPATH C0 F0 (367:431:495)(367:431:495))
         (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_113")
-    (INSTANCE SLICE_113)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_114")
-    (INSTANCE SLICE_114)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_115")
-    (INSTANCE SLICE_115)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_116")
-    (INSTANCE SLICE_116)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_117")
-    (INSTANCE SLICE_117)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B1 F1 (367:431:495)(367:431:495))
-        (IOPATH A1 F1 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_118")
-    (INSTANCE SLICE_118)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D1 F1 (367:431:495)(367:431:495))
-        (IOPATH C1 F1 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "SLICE_119")
-    (INSTANCE SLICE_119)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH D0 F0 (367:431:495)(367:431:495))
-        (IOPATH C0 F0 (367:431:495)(367:431:495))
-        (IOPATH B0 F0 (367:431:495)(367:431:495))
-        (IOPATH A0 F0 (367:431:495)(367:431:495))
       )
     )
   )
@@ -2315,56 +2849,6 @@
       (WIDTH (negedge C14M) (3330:3330:3330))
     )
   )
-  (CELL
-    (CELLTYPE "DQMH")
-    (INSTANCE DQMH_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO DQMH (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "DQMH_MGIOL")
-    (INSTANCE DQMH_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "DQML")
-    (INSTANCE DQML_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO DQML (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "DQML_MGIOL")
-    (INSTANCE DQML_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
   (CELL
     (CELLTYPE "RD_7_")
     (INSTANCE RD\[7\]_I)
@@ -2478,117 +2962,17 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_11_")
-    (INSTANCE RA\[11\]_I)
+    (CELLTYPE "DQMH")
+    (INSTANCE DQMH_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA11 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO DQMH (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_11__MGIOL")
-    (INSTANCE RA\[11\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10_")
-    (INSTANCE RA\[10\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA10 (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_10__MGIOL")
-    (INSTANCE RA\[10\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9_")
-    (INSTANCE RA\[9\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA9 (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_9__MGIOL")
-    (INSTANCE RA\[9\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8_")
-    (INSTANCE RA\[8\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA8 (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_8__MGIOL")
-    (INSTANCE RA\[8\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7_")
-    (INSTANCE RA\[7\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA7 (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_7__MGIOL")
-    (INSTANCE RA\[7\]_MGIOL)
+    (CELLTYPE "DQMH_MGIOL")
+    (INSTANCE DQMH_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
@@ -2604,17 +2988,17 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_6_")
-    (INSTANCE RA\[6\]_I)
+    (CELLTYPE "DQML")
+    (INSTANCE DQML_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA6 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO DQML (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_6__MGIOL")
-    (INSTANCE RA\[6\]_MGIOL)
+    (CELLTYPE "DQML_MGIOL")
+    (INSTANCE DQML_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
@@ -2630,127 +3014,305 @@
     )
   )
   (CELL
-    (CELLTYPE "RA_5_")
-    (INSTANCE RA\[5\]_I)
+    (CELLTYPE "RAout_11_")
+    (INSTANCE RAout\[11\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA5 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO RAout11 (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_5__MGIOL")
-    (INSTANCE RA\[5\]_MGIOL)
+    (CELLTYPE "RAout_11__MGIOL")
+    (INSTANCE RAout\[11\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_4_")
-    (INSTANCE RA\[4\]_I)
+    (CELLTYPE "RAout_10_")
+    (INSTANCE RAout\[10\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA4 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO RAout10 (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_4__MGIOL")
-    (INSTANCE RA\[4\]_MGIOL)
+    (CELLTYPE "RAout_10__MGIOL")
+    (INSTANCE RAout\[10\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_3_")
-    (INSTANCE RA\[3\]_I)
+    (CELLTYPE "RAout_9_")
+    (INSTANCE RAout\[9\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH PADDO RA3 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO RAout9 (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_2_")
-    (INSTANCE RA\[2\]_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO RA2 (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "RA_2__MGIOL")
-    (INSTANCE RA\[2\]_MGIOL)
+    (CELLTYPE "RAout_9__MGIOL")
+    (INSTANCE RAout\[9\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_1_")
-    (INSTANCE RA\[1\]_I)
+    (CELLTYPE "RAout_8_")
+    (INSTANCE RAout\[8\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO RA1 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO RAout8 (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "RA_1__MGIOL")
-    (INSTANCE RA\[1\]_MGIOL)
+    (CELLTYPE "RAout_8__MGIOL")
+    (INSTANCE RAout\[8\]_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_7_")
+    (INSTANCE RAout\[7\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout7 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_7__MGIOL")
+    (INSTANCE RAout\[7\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
     )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "RA_0_")
-    (INSTANCE RA\[0\]_I)
+    (CELLTYPE "RAout_6_")
+    (INSTANCE RAout\[6\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH PADDO RA0 (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO RAout6 (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
+  (CELL
+    (CELLTYPE "RAout_6__MGIOL")
+    (INSTANCE RAout\[6\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_5_")
+    (INSTANCE RAout\[5\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout5 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_5__MGIOL")
+    (INSTANCE RAout\[5\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_4_")
+    (INSTANCE RAout\[4\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout4 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_4__MGIOL")
+    (INSTANCE RAout\[4\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_3_")
+    (INSTANCE RAout\[3\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout3 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_3__MGIOL")
+    (INSTANCE RAout\[3\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_2_")
+    (INSTANCE RAout\[2\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout2 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_2__MGIOL")
+    (INSTANCE RAout\[2\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_1_")
+    (INSTANCE RAout\[1\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout1 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_1__MGIOL")
+    (INSTANCE RAout\[1\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_0_")
+    (INSTANCE RAout\[0\]_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO RAout0 (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "RAout_0__MGIOL")
+    (INSTANCE RAout\[0\]_MGIOL)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
+      )
+    )
+    (TIMINGCHECK
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
+    )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
+  )
   (CELL
     (CELLTYPE "BA_1_")
     (INSTANCE BA\[1\]_I)
@@ -2770,6 +3332,7 @@
     )
     (TIMINGCHECK
       (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
       (SETUPHOLD LSR (posedge CLK) (100:100:100)(-90:-90:-90))
     )
     (TIMINGCHECK
@@ -2796,6 +3359,7 @@
     )
     (TIMINGCHECK
       (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
       (SETUPHOLD LSR (posedge CLK) (100:100:100)(-90:-90:-90))
     )
     (TIMINGCHECK
@@ -2804,128 +3368,112 @@
     )
   )
   (CELL
-    (CELLTYPE "nRWE")
-    (INSTANCE nRWE_I)
+    (CELLTYPE "nRWEout")
+    (INSTANCE nRWEout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nRWE (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO nRWEout (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "nRWE_MGIOL")
-    (INSTANCE nRWE_MGIOL)
+    (CELLTYPE "nRWEout_MGIOL")
+    (INSTANCE nRWEout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nCAS")
-    (INSTANCE nCAS_I)
+    (CELLTYPE "nCASout")
+    (INSTANCE nCASout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nCAS (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO nCASout (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "nCAS_MGIOL")
-    (INSTANCE nCAS_MGIOL)
+    (CELLTYPE "nCASout_MGIOL")
+    (INSTANCE nCASout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nRAS")
-    (INSTANCE nRAS_I)
+    (CELLTYPE "nRASout")
+    (INSTANCE nRASout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nRAS (3411:3517:3624)(3411:3517:3624))
+        (IOPATH IOLDO nRASout (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "nRAS_MGIOL")
-    (INSTANCE nRAS_MGIOL)
+    (CELLTYPE "nRASout_MGIOL")
+    (INSTANCE nRASout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
+    (TIMINGCHECK
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
+    )
   )
   (CELL
-    (CELLTYPE "nCS")
-    (INSTANCE nCS_I)
+    (CELLTYPE "nCSout")
+    (INSTANCE nCSout_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO nCS (3411:3517:3624)(3411:3517:3624))
+        (IOPATH PADDO nCSout (3411:3517:3624)(3411:3517:3624))
       )
     )
   )
   (CELL
-    (CELLTYPE "nCS_MGIOL")
-    (INSTANCE nCS_MGIOL)
+    (CELLTYPE "CKEout")
+    (INSTANCE CKEout_I)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH IOLDO CKEout (3411:3517:3624)(3411:3517:3624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "CKEout_MGIOL")
+    (INSTANCE CKEout_MGIOL)
     (DELAY
       (ABSOLUTE
         (IOPATH CLK IOLDO (546:556:567)(546:556:567))
       )
     )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
     (TIMINGCHECK
       (WIDTH (posedge CLK) (1855:1855:1855))
       (WIDTH (negedge CLK) (1855:1855:1855))
     )
-  )
-  (CELL
-    (CELLTYPE "CKE")
-    (INSTANCE CKE_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH IOLDO CKE (3411:3517:3624)(3411:3517:3624))
-      )
-    )
-  )
-  (CELL
-    (CELLTYPE "CKE_MGIOL")
-    (INSTANCE CKE_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
     )
   )
   (CELL
@@ -2955,12 +3503,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -2981,12 +3529,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3007,12 +3555,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3033,12 +3581,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3059,12 +3607,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3085,12 +3633,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3111,12 +3659,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3137,12 +3685,12 @@
       )
     )
     (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
+      (SETUPHOLD OPOS (posedge CLK) (153:153:153)(-86:-86:-86))
+      (SETUPHOLD CE (posedge CLK) (47:47:47)(-36:-36:-36))
     )
     (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
+      (WIDTH (posedge CLK) (1855:1855:1855))
+      (WIDTH (negedge CLK) (1855:1855:1855))
     )
   )
   (CELL
@@ -3159,209 +3707,73 @@
     (INSTANCE Dout\[7\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout7 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout7 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_7__MGIOL")
-    (INSTANCE Dout\[7\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_6_")
     (INSTANCE Dout\[6\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout6 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout6 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_6__MGIOL")
-    (INSTANCE Dout\[6\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_5_")
     (INSTANCE Dout\[5\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout5 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout5 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_5__MGIOL")
-    (INSTANCE Dout\[5\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_4_")
     (INSTANCE Dout\[4\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout4 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout4 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_4__MGIOL")
-    (INSTANCE Dout\[4\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_3_")
     (INSTANCE Dout\[3\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout3 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout3 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_3__MGIOL")
-    (INSTANCE Dout\[3\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_2_")
     (INSTANCE Dout\[2\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout2 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout2 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_2__MGIOL")
-    (INSTANCE Dout\[2\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_1_")
     (INSTANCE Dout\[1\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout1 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout1 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_1__MGIOL")
-    (INSTANCE Dout\[1\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Dout_0_")
     (INSTANCE Dout\[0\]_I)
     (DELAY
       (ABSOLUTE
-        (IOPATH IOLDO Dout0 (3725:3847:3970)(3725:3847:3970))
+        (IOPATH PADDO Dout0 (4370:4474:4579)(4370:4474:4579))
       )
     )
   )
-  (CELL
-    (CELLTYPE "Dout_0__MGIOL")
-    (INSTANCE Dout\[0\]_MGIOL)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH CLK IOLDO (546:556:567)(546:556:567))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge CLK) (1855:1855:1855))
-      (WIDTH (negedge CLK) (1855:1855:1855))
-    )
-    (TIMINGCHECK
-      (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86))
-      (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36))
-    )
-  )
   (CELL
     (CELLTYPE "Din_7_")
     (INSTANCE Din\[7\]_I)
@@ -3596,19 +4008,6 @@
       (WIDTH (negedge nEN80) (3330:3330:3330))
     )
   )
-  (CELL
-    (CELLTYPE "nWE80")
-    (INSTANCE nWE80_I)
-    (DELAY
-      (ABSOLUTE
-        (IOPATH nWE80 PADDI (1007:1069:1132)(1007:1069:1132))
-      )
-    )
-    (TIMINGCHECK
-      (WIDTH (posedge nWE80) (3330:3330:3330))
-      (WIDTH (negedge nWE80) (3330:3330:3330))
-    )
-  )
   (CELL
     (CELLTYPE "nWE")
     (INSTANCE nWE_I)
@@ -3653,7 +4052,7 @@
   )
   (CELL
     (CELLTYPE "EFB_Buffer_Block")
-    (INSTANCE ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20)
+    (INSTANCE ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20)
     (DELAY
       (ABSOLUTE
         (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278))
@@ -3699,11 +4098,12 @@
     (INSTANCE )
     (DELAY
       (ABSOLUTE
-        (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_0/Q1 SLICE_39/D1 (805:898:992)(805:898:992))
-        (INTERCONNECT SLICE_0/Q1 SLICE_52/C1 (816:964:1113)(816:964:1113))
-        (INTERCONNECT SLICE_0/Q1 SLICE_75/C1 (1180:1360:1540)(1180:1360:1540))
-        (INTERCONNECT SLICE_0/Q1 SLICE_119/C0 (805:952:1100)(805:952:1100))
+        (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_51/B1 (1363:1554:1746)(1363:1554:1746))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_69/C1 (1291:1472:1653)(1291:1472:1653))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_105/B0 (1522:1716:1910)(1522:1716:1910))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_108/B0 (788:918:1049)(788:918:1049))
+        (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_146/D0 (546:608:671)(546:608:671))
         (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT C14M_I/PADDI SLICE_0/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_1/CLK (2666:2868:3070)(2666:2868:3070))
@@ -3723,18 +4123,20 @@
         (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_9/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_11/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (2666:2868:3070)(2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_13/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_14/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_15/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_16/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_17/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (2666:2868:3070)(2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (2666:2868:3070)(2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (2666:2868:3070)(2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (2666:2868:3070)(2666:2868:3070))
@@ -3761,44 +4163,93 @@
         (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (2666:2868:3070)(2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_39/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_44/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_45/CLK (2666:2868:3070)(2666:2868:3070))
-        (INTERCONNECT C14M_I/PADDI SLICE_46/CLK (2666:2868:3070)(2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_39/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_40/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_41/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_42/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_43/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_43/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_44/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_44/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_45/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_45/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_46/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_46/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_47/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_47/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_48/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_48/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_49/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_49/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_50/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_50/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_51/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_52/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_52/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_53/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_53/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_54/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_54/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_55/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_55/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_56/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_57/CLK (2666:2868:3070)
+          (2666:2868:3070))
+        (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_58/CLK (2666:2868:3070)
+          (2666:2868:3070))
         (INTERCONNECT C14M_I/PADDI DQMH_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
         (INTERCONNECT C14M_I/PADDI DQML_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI RA\[11\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI RA\[10\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI RA\[9\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI RA\[8\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI RA\[7\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI RA\[6\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI RA\[5\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI RA\[4\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI RA\[2\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI RA\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[11\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[10\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[9\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[8\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[7\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[6\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[5\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[4\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[3\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[2\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI RAout\[0\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
         (INTERCONNECT C14M_I/PADDI BA\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
         (INTERCONNECT C14M_I/PADDI BA\[0\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI nRWE_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI nCAS_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI nRAS_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI nCS_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI CKE_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI nRWEout_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI nCASout_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI nRASout_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
+        (INTERCONNECT C14M_I/PADDI CKEout_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
         (INTERCONNECT C14M_I/PADDI Vout\[7\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
         (INTERCONNECT C14M_I/PADDI Vout\[6\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
         (INTERCONNECT C14M_I/PADDI Vout\[5\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
@@ -3807,1123 +4258,1722 @@
         (INTERCONNECT C14M_I/PADDI Vout\[2\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
         (INTERCONNECT C14M_I/PADDI Vout\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
         (INTERCONNECT C14M_I/PADDI Vout\[0\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI Dout\[7\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI Dout\[6\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI Dout\[5\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI Dout\[4\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI Dout\[3\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI Dout\[2\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI Dout\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
-        (INTERCONNECT C14M_I/PADDI Dout\[0\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
         (INTERCONNECT C14M_I/PADDI PHI1_MGIOL/CLK (2813:3028:3243)(2813:3028:3243))
         (INTERCONNECT C14M_I/PADDI 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (2813:3028:3243)
-          (2813:3028:3243))
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin 
+          (2813:3028:3243)(2813:3028:3243))
         (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (483:579:675)(483:579:675))
-        (INTERCONNECT SLICE_1/Q0 SLICE_45/B0 (1154:1318:1482)(1154:1318:1482))
-        (INTERCONNECT SLICE_1/Q0 SLICE_51/A0 (1090:1255:1421)(1090:1255:1421))
-        (INTERCONNECT SLICE_1/Q0 SLICE_53/C1 (1293:1476:1659)(1293:1476:1659))
-        (INTERCONNECT SLICE_1/Q0 SLICE_56/A1 (1824:2054:2284)(1824:2054:2284))
-        (INTERCONNECT SLICE_1/Q0 SLICE_72/B0 (769:896:1023)(769:896:1023))
-        (INTERCONNECT SLICE_1/Q0 SLICE_73/A0 (1824:2054:2284)(1824:2054:2284))
-        (INTERCONNECT SLICE_1/Q0 SLICE_75/A0 (763:893:1024)(763:893:1024))
-        (INTERCONNECT SLICE_1/Q0 SLICE_83/D1 (1244:1375:1507)(1244:1375:1507))
-        (INTERCONNECT SLICE_1/Q0 SLICE_86/D1 (1609:1772:1935)(1609:1772:1935))
-        (INTERCONNECT SLICE_1/Q0 SLICE_103/C0 (928:1079:1231)(928:1079:1231))
+        (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_1/Q0 SLICE_9/B1 (1593:1795:1997)(1593:1795:1997))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/B1 (1675:1872:2069)(1675:1872:2069))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/B0 (1675:1872:2069)(1675:1872:2069))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_69/D1 (982:1084:1186)(982:1084:1186))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_80/C1 (1808:2023:2239)(1808:2023:2239))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_105/C0 (993:1150:1307)(993:1150:1307))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/B1 (1593:1795:1997)(1593:1795:1997))
+        (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/B0 (1593:1795:1997)(1593:1795:1997))
         (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (481:575:669)(481:575:669))
-        (INTERCONNECT SLICE_2/Q1 SLICE_37/B1 (1059:1223:1388)(1059:1223:1388))
-        (INTERCONNECT SLICE_2/Q1 SLICE_37/B0 (1059:1223:1388)(1059:1223:1388))
-        (INTERCONNECT SLICE_2/Q1 SLICE_38/C0 (1155:1341:1528)(1155:1341:1528))
-        (INTERCONNECT SLICE_2/Q1 SLICE_39/C1 (557:674:792)(557:674:792))
-        (INTERCONNECT SLICE_2/Q1 SLICE_44/D0 (546:608:671)(546:608:671))
-        (INTERCONNECT SLICE_2/Q1 SLICE_45/C1 (813:963:1113)(813:963:1113))
-        (INTERCONNECT SLICE_2/Q1 SLICE_45/C0 (813:963:1113)(813:963:1113))
-        (INTERCONNECT SLICE_2/Q1 SLICE_56/D1 (1192:1321:1450)(1192:1321:1450))
-        (INTERCONNECT SLICE_2/Q1 SLICE_66/B1 (1059:1223:1388)(1059:1223:1388))
-        (INTERCONNECT SLICE_2/Q1 SLICE_73/C0 (1203:1387:1571)(1203:1387:1571))
-        (INTERCONNECT SLICE_2/Q1 SLICE_86/B1 (1761:1993:2225)(1761:1993:2225))
-        (INTERCONNECT SLICE_2/Q1 SLICE_97/D0 (910:1004:1098)(910:1004:1098))
-        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (483:579:675)(483:579:675))
-        (INTERCONNECT SLICE_2/Q0 SLICE_35/A0 (1202:1373:1544)(1202:1373:1544))
-        (INTERCONNECT SLICE_2/Q0 SLICE_44/A1 (1074:1238:1402)(1074:1238:1402))
-        (INTERCONNECT SLICE_2/Q0 SLICE_46/D0 (543:607:671)(543:607:671))
-        (INTERCONNECT SLICE_2/Q0 SLICE_56/A0 (1217:1389:1562)(1217:1389:1562))
-        (INTERCONNECT SLICE_2/Q0 SLICE_60/A0 (1566:1768:1971)(1566:1768:1971))
-        (INTERCONNECT SLICE_2/Q0 SLICE_61/D1 (1007:1114:1221)(1007:1114:1221))
-        (INTERCONNECT SLICE_2/Q0 SLICE_65/A0 (1202:1373:1544)(1202:1373:1544))
-        (INTERCONNECT SLICE_2/Q0 SLICE_66/D0 (543:607:671)(543:607:671))
-        (INTERCONNECT SLICE_2/Q0 SLICE_73/D0 (1007:1114:1221)(1007:1114:1221))
-        (INTERCONNECT SLICE_2/Q0 SLICE_74/A0 (1202:1373:1544)(1202:1373:1544))
-        (INTERCONNECT SLICE_2/Q0 SLICE_88/A1 (1587:1791:1996)(1587:1791:1996))
-        (INTERCONNECT SLICE_2/Q0 SLICE_90/A1 (2366:2646:2926)(2366:2646:2926))
-        (INTERCONNECT SLICE_2/Q0 SLICE_92/C1 (1018:1180:1342)(1018:1180:1342))
-        (INTERCONNECT SLICE_2/Q0 SLICE_97/A0 (1581:1785:1989)(1581:1785:1989))
-        (INTERCONNECT SLICE_2/Q0 SLICE_108/C0 (1715:1944:2173)(1715:1944:2173))
-        (INTERCONNECT SLICE_2/Q0 SLICE_116/A0 (2366:2646:2926)(2366:2646:2926))
+        (INTERCONNECT SLICE_2/Q1 SLICE_23/B1 (793:924:1055)(793:924:1055))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/D1 (995:1098:1201)(995:1098:1201))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/D0 (995:1098:1201)(995:1098:1201))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_50/B0 (1607:1810:2013)(1607:1810:2013))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_51/D1 (921:1016:1111)(921:1016:1111))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_56/C1 (889:1042:1195)(889:1042:1195))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/D1 (926:1021:1117)(926:1021:1117))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/D0 (926:1021:1117)(926:1021:1117))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_66/B1 (1490:1688:1886)(1490:1688:1886))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_70/B1 (1607:1810:2013)(1607:1810:2013))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_81/D1 (995:1098:1201)(995:1098:1201))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_85/D1 (1290:1417:1544)(1290:1417:1544))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_89/A1 (1575:1775:1976)(1575:1775:1976))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_98/D1 (995:1098:1201)(995:1098:1201))
+        (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_109/C1 (1376:1566:1756)(1376:1566:1756))
+        (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_2/Q0 SLICE_23/B0 (786:914:1043)(786:914:1043))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_56/B0 (786:914:1043)(786:914:1043))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_58/D0 (1283:1407:1532)(1283:1407:1532))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_64/D0 (2000:2193:2387)(2000:2193:2387))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_70/D0 (2053:2244:2436)(2053:2244:2436))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_75/D0 (2053:2244:2436)(2053:2244:2436))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_76/D0 (1673:1831:1990)(1673:1831:1990))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_81/C0 (2011:2259:2508)(2011:2259:2508))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_85/B1 (1852:2079:2307)(1852:2079:2307))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_89/D1 (2063:2255:2448)(2063:2255:2448))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_97/D1 (2063:2255:2448)(2063:2255:2448))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_103/D1 (2063:2255:2448)(2063:2255:2448))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_111/C0 (1684:1897:2111)(1684:1897:2111))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_125/B1 (2669:2961:3253)(2669:2961:3253))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_128/D1 (2063:2255:2448)(2063:2255:2448))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_128/D0 (2063:2255:2448)(2063:2255:2448))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_131/C1 (2391:2672:2954)(2391:2672:2954))
+        (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_131/D0 (2053:2244:2436)(2053:2244:2436))
         (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (481:575:669)(481:575:669))
-        (INTERCONNECT SLICE_3/Q1 SLICE_44/C1 (552:669:786)(552:669:786))
-        (INTERCONNECT SLICE_3/Q1 SLICE_46/A1 (776:906:1036)(776:906:1036))
-        (INTERCONNECT SLICE_3/Q1 SLICE_56/C0 (1280:1460:1640)(1280:1460:1640))
-        (INTERCONNECT SLICE_3/Q1 SLICE_58/D1 (1351:1491:1632)(1351:1491:1632))
-        (INTERCONNECT SLICE_3/Q1 SLICE_60/C0 (972:1126:1280)(972:1126:1280))
-        (INTERCONNECT SLICE_3/Q1 SLICE_61/B1 (1583:1783:1983)(1583:1783:1983))
-        (INTERCONNECT SLICE_3/Q1 SLICE_62/C1 (972:1126:1280)(972:1126:1280))
-        (INTERCONNECT SLICE_3/Q1 SLICE_64/A0 (776:906:1036)(776:906:1036))
-        (INTERCONNECT SLICE_3/Q1 SLICE_65/C0 (972:1126:1280)(972:1126:1280))
-        (INTERCONNECT SLICE_3/Q1 SLICE_66/A0 (776:906:1036)(776:906:1036))
-        (INTERCONNECT SLICE_3/Q1 SLICE_70/D1 (1351:1491:1632)(1351:1491:1632))
-        (INTERCONNECT SLICE_3/Q1 SLICE_73/B1 (1583:1783:1983)(1583:1783:1983))
-        (INTERCONNECT SLICE_3/Q1 SLICE_74/C0 (972:1126:1280)(972:1126:1280))
-        (INTERCONNECT SLICE_3/Q1 SLICE_84/C1 (972:1126:1280)(972:1126:1280))
-        (INTERCONNECT SLICE_3/Q1 SLICE_88/D1 (1336:1467:1599)(1336:1467:1599))
-        (INTERCONNECT SLICE_3/Q1 SLICE_90/A0 (1551:1748:1946)(1551:1748:1946))
-        (INTERCONNECT SLICE_3/Q1 SLICE_92/A1 (1551:1748:1946)(1551:1748:1946))
-        (INTERCONNECT SLICE_3/Q1 SLICE_95/A1 (776:906:1036)(776:906:1036))
-        (INTERCONNECT SLICE_3/Q1 SLICE_97/A1 (1140:1301:1463)(1140:1301:1463))
-        (INTERCONNECT SLICE_3/Q1 SLICE_108/B1 (1578:1777:1977)(1578:1777:1977))
-        (INTERCONNECT SLICE_3/Q1 SLICE_108/B0 (1578:1777:1977)(1578:1777:1977))
-        (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_3/Q0 SLICE_44/D1 (866:961:1056)(866:961:1056))
-        (INTERCONNECT SLICE_3/Q0 SLICE_50/A1 (1498:1688:1879)(1498:1688:1879))
-        (INTERCONNECT SLICE_3/Q0 SLICE_58/A0 (2248:2503:2759)(2248:2503:2759))
-        (INTERCONNECT SLICE_3/Q0 SLICE_61/D0 (1673:1831:1990)(1673:1831:1990))
-        (INTERCONNECT SLICE_3/Q0 SLICE_62/A1 (1883:2107:2331)(1883:2107:2331))
-        (INTERCONNECT SLICE_3/Q0 SLICE_64/A1 (2253:2509:2765)(2253:2509:2765))
-        (INTERCONNECT SLICE_3/Q0 SLICE_65/C1 (1674:1886:2099)(1674:1886:2099))
-        (INTERCONNECT SLICE_3/Q0 SLICE_66/C0 (2381:2661:2942)(2381:2661:2942))
-        (INTERCONNECT SLICE_3/Q0 SLICE_68/B0 (2655:2945:3236)(2655:2945:3236))
-        (INTERCONNECT SLICE_3/Q0 SLICE_70/A0 (2248:2503:2759)(2248:2503:2759))
-        (INTERCONNECT SLICE_3/Q0 SLICE_73/A1 (1498:1688:1879)(1498:1688:1879))
-        (INTERCONNECT SLICE_3/Q0 SLICE_74/C1 (2001:2248:2496)(2001:2248:2496))
-        (INTERCONNECT SLICE_3/Q0 SLICE_89/A1 (1498:1688:1879)(1498:1688:1879))
-        (INTERCONNECT SLICE_3/Q0 SLICE_90/C1 (1684:1897:2111)(1684:1897:2111))
-        (INTERCONNECT SLICE_3/Q0 SLICE_92/D1 (2458:2692:2927)(2458:2692:2927))
-        (INTERCONNECT SLICE_3/Q0 SLICE_104/D1 (2413:2635:2858)(2413:2635:2858))
-        (INTERCONNECT SLICE_3/Q0 SLICE_104/D0 (2413:2635:2858)(2413:2635:2858))
-        (INTERCONNECT SLICE_3/Q0 SLICE_116/D0 (2785:3054:3324)(2785:3054:3324))
+        (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_56/D0 (803:890:978)(803:890:978))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_58/C1 (2000:2253:2506)(2000:2253:2506))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_68/D0 (2316:2549:2782)(2316:2549:2782))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_70/B0 (2226:2491:2757)(2226:2491:2757))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_75/A0 (2194:2457:2720)(2194:2457:2720))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_76/A0 (2579:2875:3172)(2579:2875:3172))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_81/D0 (2696:2962:3228)(2696:2962:3228))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_85/C1 (1947:2202:2457)(1947:2202:2457))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_90/B1 (2933:3266:3600)(2933:3266:3600))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_93/B0 (3391:3765:4140)(3391:3765:4140))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_97/A1 (3739:4144:4549)(3739:4144:4549))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_99/A0 (3739:4144:4549)(3739:4144:4549))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_103/A1 (2912:3245:3578)(2912:3245:3578))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_104/B0 (2944:3279:3615)(2944:3279:3615))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_111/D1 (2369:2600:2831)(2369:2600:2831))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_114/B0 (2611:2910:3209)(2611:2910:3209))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_124/C1 (814:956:1099)(814:956:1099))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_126/A1 (2189:2451:2714)(2189:2451:2714))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_126/A0 (2189:2451:2714)(2189:2451:2714))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_128/A1 (4066:4506:4946)(4066:4506:4946))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_128/C0 (3540:3934:4329)(3540:3934:4329))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_131/B1 (2923:3255:3588)(2923:3255:3588))
+        (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_131/A0 (2564:2859:3154)(2564:2859:3154))
+        (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_3/Q0 SLICE_22/B0 (770:892:1014)(770:892:1014))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_56/A0 (751:878:1006)(751:878:1006))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_64/C1 (1633:1850:2068)(1633:1850:2068))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_64/A0 (1505:1698:1891)(1505:1698:1891))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_68/A0 (2270:2529:2789)(2270:2529:2789))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_73/C0 (1701:1918:2135)(1701:1918:2135))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_75/A1 (1875:2100:2325)(1875:2100:2325))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_76/A1 (2255:2513:2771)(2255:2513:2771))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_88/A1 (2255:2513:2771)(2255:2513:2771))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_90/A1 (2255:2513:2771)(2255:2513:2771))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_93/A1 (2619:2908:3198)(2619:2908:3198))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_99/D1 (2065:2259:2454)(2065:2259:2454))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_104/C1 (1701:1918:2135)(1701:1918:2135))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_109/D0 (2060:2254:2448)(2060:2254:2448))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_110/B1 (1901:2128:2355)(1901:2128:2355))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_114/A0 (1505:1698:1891)(1505:1698:1891))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_123/C1 (1701:1918:2135)(1701:1918:2135))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_123/C0 (1701:1918:2135)(1701:1918:2135))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_125/C1 (2076:2325:2575)(2076:2325:2575))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_125/C0 (2076:2325:2575)(2076:2325:2575))
+        (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_128/C1 (1701:1918:2135)(1701:1918:2135))
         (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_4/Q1 SLICE_46/B1 (796:925:1055)(796:925:1055))
-        (INTERCONNECT SLICE_4/Q1 SLICE_50/C1 (1345:1529:1714)(1345:1529:1714))
-        (INTERCONNECT SLICE_4/Q1 SLICE_58/D0 (1329:1458:1587)(1329:1458:1587))
-        (INTERCONNECT SLICE_4/Q1 SLICE_60/D0 (954:1050:1147)(954:1050:1147))
-        (INTERCONNECT SLICE_4/Q1 SLICE_61/A0 (1534:1728:1922)(1534:1728:1922))
-        (INTERCONNECT SLICE_4/Q1 SLICE_62/D0 (954:1050:1147)(954:1050:1147))
-        (INTERCONNECT SLICE_4/Q1 SLICE_64/B0 (796:925:1055)(796:925:1055))
-        (INTERCONNECT SLICE_4/Q1 SLICE_65/D0 (954:1050:1147)(954:1050:1147))
-        (INTERCONNECT SLICE_4/Q1 SLICE_68/C0 (1710:1926:2142)(1710:1926:2142))
-        (INTERCONNECT SLICE_4/Q1 SLICE_70/D0 (1329:1458:1587)(1329:1458:1587))
-        (INTERCONNECT SLICE_4/Q1 SLICE_74/D0 (954:1050:1147)(954:1050:1147))
-        (INTERCONNECT SLICE_4/Q1 SLICE_84/D1 (954:1050:1147)(954:1050:1147))
-        (INTERCONNECT SLICE_4/Q1 SLICE_89/D1 (1334:1463:1593)(1334:1463:1593))
-        (INTERCONNECT SLICE_4/Q1 SLICE_90/D1 (1324:1452:1581)(1324:1452:1581))
-        (INTERCONNECT SLICE_4/Q1 SLICE_95/B1 (796:925:1055)(796:925:1055))
-        (INTERCONNECT SLICE_4/Q1 SLICE_97/D1 (918:1011:1104)(918:1011:1104))
-        (INTERCONNECT SLICE_4/Q1 SLICE_104/A0 (1909:2135:2362)(1909:2135:2362))
-        (INTERCONNECT SLICE_4/Q1 SLICE_108/A1 (1544:1739:1934)(1544:1739:1934))
-        (INTERCONNECT SLICE_4/Q1 SLICE_108/A0 (1544:1739:1934)(1544:1739:1934))
-        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_4/Q0 SLICE_46/C1 (892:1043:1195)(892:1043:1195))
-        (INTERCONNECT SLICE_4/Q0 SLICE_50/B1 (1556:1751:1947)(1556:1751:1947))
-        (INTERCONNECT SLICE_4/Q0 SLICE_50/B0 (1556:1751:1947)(1556:1751:1947))
-        (INTERCONNECT SLICE_4/Q0 SLICE_58/C0 (1355:1549:1743)(1355:1549:1743))
-        (INTERCONNECT SLICE_4/Q0 SLICE_61/B0 (1546:1740:1935)(1546:1740:1935))
-        (INTERCONNECT SLICE_4/Q0 SLICE_62/B0 (1171:1333:1495)(1171:1333:1495))
-        (INTERCONNECT SLICE_4/Q0 SLICE_64/B1 (796:925:1055)(796:925:1055))
-        (INTERCONNECT SLICE_4/Q0 SLICE_65/B1 (1171:1333:1495)(1171:1333:1495))
-        (INTERCONNECT SLICE_4/Q0 SLICE_68/D0 (1349:1488:1628)(1349:1488:1628))
-        (INTERCONNECT SLICE_4/Q0 SLICE_70/C0 (1355:1549:1743)(1355:1549:1743))
-        (INTERCONNECT SLICE_4/Q0 SLICE_74/B1 (1171:1333:1495)(1171:1333:1495))
-        (INTERCONNECT SLICE_4/Q0 SLICE_89/B0 (1556:1751:1947)(1556:1751:1947))
-        (INTERCONNECT SLICE_4/Q0 SLICE_90/B1 (1546:1740:1935)(1546:1740:1935))
-        (INTERCONNECT SLICE_4/Q0 SLICE_104/B1 (1591:1798:2006)(1591:1798:2006))
-        (INTERCONNECT SLICE_4/Q0 SLICE_104/B0 (1591:1798:2006)(1591:1798:2006))
-        (INTERCONNECT SLICE_4/Q0 SLICE_105/B1 (1546:1740:1935)(1546:1740:1935))
-        (INTERCONNECT SLICE_4/Q0 SLICE_105/B0 (1546:1740:1935)(1546:1740:1935))
-        (INTERCONNECT SLICE_4/Q0 SLICE_108/C1 (1652:1869:2087)(1652:1869:2087))
-        (INTERCONNECT SLICE_4/Q0 SLICE_116/B1 (1556:1751:1947)(1556:1751:1947))
-        (INTERCONNECT SLICE_4/Q0 SLICE_116/B0 (1556:1751:1947)(1556:1751:1947))
+        (INTERCONNECT SLICE_4/Q1 SLICE_21/A1 (738:861:985)(738:861:985))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_47/D0 (1944:2145:2347)(1944:2145:2347))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_68/B0 (1510:1714:1919)(1510:1714:1919))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_73/B0 (1885:2122:2359)(1885:2122:2359))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_75/B1 (1495:1698:1901)(1495:1698:1901))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_76/B1 (1495:1698:1901)(1495:1698:1901))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_88/B1 (1495:1698:1901)(1495:1698:1901))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_90/D1 (1612:1778:1944)(1612:1778:1944))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_93/B1 (1484:1686:1888)(1484:1686:1888))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_99/B1 (1874:2110:2346)(1874:2110:2346))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_104/A1 (1822:2053:2285)(1822:2053:2285))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_110/D1 (1981:2179:2377)(1981:2179:2377))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_114/C1 (1628:1849:2071)(1628:1849:2071))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_123/D0 (1268:1404:1541)(1268:1404:1541))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_126/C1 (1279:1470:1662)(1279:1470:1662))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_126/C0 (1279:1470:1662)(1279:1470:1662))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_128/B1 (1885:2122:2359)(1885:2122:2359))
+        (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_128/B0 (1885:2122:2359)(1885:2122:2359))
+        (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_64/B1 (1617:1822:2027)(1617:1822:2027))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_68/C1 (1703:1929:2155)(1703:1929:2155))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_73/D0 (1750:1919:2089)(1750:1919:2089))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_75/C1 (805:948:1092)(805:948:1092))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_81/B1 (1222:1392:1563)(1222:1392:1563))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_93/D1 (2452:2690:2928)(2452:2690:2928))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_104/B1 (1617:1822:2027)(1617:1822:2027))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_110/C1 (1703:1929:2155)(1703:1929:2155))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_111/B0 (1222:1392:1563)(1222:1392:1563))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_114/B1 (1617:1822:2027)(1617:1822:2027))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_123/B1 (1617:1822:2027)(1617:1822:2027))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_123/B0 (1617:1822:2027)(1617:1822:2027))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_125/D1 (2447:2683:2920)(2447:2683:2920))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_125/B0 (2362:2631:2901)(2362:2631:2901))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_126/B1 (1607:1811:2015)(1607:1811:2015))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_126/B0 (1607:1811:2015)(1607:1811:2015))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_134/B0 (1591:1793:1996)(1591:1793:1996))
+        (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_145/B0 (2694:3000:3306)(2694:3000:3306))
         (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_5/Q1 SLICE_46/D1 (871:966:1062)(871:966:1062))
-        (INTERCONNECT SLICE_5/Q1 SLICE_50/D1 (1641:1803:1966)(1641:1803:1966))
-        (INTERCONNECT SLICE_5/Q1 SLICE_58/B0 (1868:2098:2328)(1868:2098:2328))
-        (INTERCONNECT SLICE_5/Q1 SLICE_61/C0 (2022:2271:2521)(2022:2271:2521))
-        (INTERCONNECT SLICE_5/Q1 SLICE_62/A0 (1134:1293:1452)(1134:1293:1452))
-        (INTERCONNECT SLICE_5/Q1 SLICE_64/C1 (555:670:786)(555:670:786))
-        (INTERCONNECT SLICE_5/Q1 SLICE_65/A1 (1134:1293:1452)(1134:1293:1452))
-        (INTERCONNECT SLICE_5/Q1 SLICE_68/A0 (1894:2119:2344)(1894:2119:2344))
-        (INTERCONNECT SLICE_5/Q1 SLICE_70/B0 (1868:2098:2328)(1868:2098:2328))
-        (INTERCONNECT SLICE_5/Q1 SLICE_85/A1 (1524:1717:1910)(1524:1717:1910))
-        (INTERCONNECT SLICE_5/Q1 SLICE_86/A1 (1894:2119:2344)(1894:2119:2344))
-        (INTERCONNECT SLICE_5/Q1 SLICE_89/C0 (1325:1507:1690)(1325:1507:1690))
-        (INTERCONNECT SLICE_5/Q1 SLICE_104/A1 (1894:2119:2344)(1894:2119:2344))
-        (INTERCONNECT SLICE_5/Q1 SLICE_116/A1 (1888:2112:2337)(1888:2112:2337))
-        (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (481:575:669)(481:575:669))
-        (INTERCONNECT SLICE_5/Q0 SLICE_32/C1 (539:648:757)(539:648:757))
-        (INTERCONNECT SLICE_5/Q0 SLICE_63/B1 (1473:1665:1858)(1473:1665:1858))
-        (INTERCONNECT SLICE_5/Q0 SLICE_75/D1 (1558:1717:1877)(1558:1717:1877))
+        (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_68/D1 (1879:2074:2269)(1879:2074:2269))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_68/C0 (1366:1555:1744)(1366:1555:1744))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_70/A1 (1012:1172:1333)(1012:1172:1333))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_73/A0 (1195:1362:1530)(1195:1362:1530))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_81/A1 (1387:1580:1773)(1387:1580:1773))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_93/C1 (1890:2141:2392)(1890:2141:2392))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_99/A1 (1533:1737:1942)(1533:1737:1942))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_104/D1 (1698:1869:2041)(1698:1869:2041))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_107/B0 (1038:1200:1363)(1038:1200:1363))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_110/A1 (1892:2126:2361)(1892:2126:2361))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_114/A1 (1897:2132:2367)(1897:2132:2367))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_123/D1 (1698:1869:2041)(1698:1869:2041))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_123/A0 (1897:2132:2367)(1897:2132:2367))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_125/A1 (2126:2383:2640)(2126:2383:2640))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_125/D0 (1323:1462:1601)(1323:1462:1601))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_126/D1 (1552:1712:1872)(1552:1712:1872))
+        (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_145/C0 (1890:2141:2392)(1890:2141:2392))
+        (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_5/Q0 SLICE_20/B0 (781:909:1037)(781:909:1037))
+        (INTERCONNECT SLICE_5/Q0 ram2e_ufm\/SLICE_108/C1 (920:1067:1214)(920:1067:1214))
+        (INTERCONNECT SLICE_5/Q0 ram2e_ufm\/SLICE_146/A0 (1446:1638:1831)(1446:1638:1831))
         (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_5/F0 SLICE_5/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_6/Q1 SLICE_32/D1 (539:599:659)(539:599:659))
-        (INTERCONNECT SLICE_6/Q1 SLICE_63/D1 (1241:1369:1498)(1241:1369:1498))
-        (INTERCONNECT SLICE_6/Q1 SLICE_75/A1 (1451:1645:1839)(1451:1645:1839))
-        (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_6/Q0 SLICE_55/B1 (1156:1316:1477)(1156:1316:1477))
-        (INTERCONNECT SLICE_6/Q0 SLICE_55/B0 (1156:1316:1477)(1156:1316:1477))
-        (INTERCONNECT SLICE_6/Q0 SLICE_72/D1 (539:599:659)(539:599:659))
-        (INTERCONNECT SLICE_6/Q0 SLICE_76/A1 (1124:1282:1440)(1124:1282:1440))
+        (INTERCONNECT SLICE_6/Q1 ram2e_ufm\/SLICE_134/D1 (544:604:665)(544:604:665))
+        (INTERCONNECT SLICE_6/Q1 ram2e_ufm\/SLICE_134/D0 (544:604:665)(544:604:665))
+        (INTERCONNECT SLICE_6/Q1 ram2e_ufm\/SLICE_146/C0 (555:670:786)(555:670:786))
+        (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_6/Q0 ram2e_ufm\/SLICE_107/D0 (528:582:636)(528:582:636))
+        (INTERCONNECT SLICE_6/Q0 ram2e_ufm\/SLICE_108/A1 (1184:1351:1519)(1184:1351:1519))
+        (INTERCONNECT SLICE_6/Q0 ram2e_ufm\/SLICE_146/B0 (1216:1386:1556)(1216:1386:1556))
         (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_7/Q1 SLICE_55/A1 (1124:1282:1440)(1124:1282:1440))
-        (INTERCONNECT SLICE_7/Q1 SLICE_71/B1 (1858:2087:2316)(1858:2087:2316))
-        (INTERCONNECT SLICE_7/Q1 SLICE_76/D1 (914:1006:1099)(914:1006:1099))
-        (INTERCONNECT SLICE_7/Q1 SLICE_78/D1 (1616:1777:1938)(1616:1777:1938))
-        (INTERCONNECT SLICE_7/Q1 SLICE_119/A0 (749:874:1000)(749:874:1000))
-        (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_7/Q0 SLICE_55/A0 (1119:1276:1434)(1119:1276:1434))
-        (INTERCONNECT SLICE_7/Q0 SLICE_63/B0 (1151:1311:1471)(1151:1311:1471))
-        (INTERCONNECT SLICE_7/Q0 SLICE_72/A1 (749:874:1000)(749:874:1000))
+        (INTERCONNECT SLICE_7/Q1 SLICE_35/B1 (2395:2672:2950)(2395:2672:2950))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_57/A1 (1183:1347:1512)(1183:1347:1512))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_67/D0 (1783:1960:2138)(1783:1960:2138))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_71/A1 (2363:2638:2913)(2363:2638:2913))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_72/B1 (2389:2666:2943)(2389:2666:2943))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_107/D1 (2528:2770:3012)(2528:2770:3012))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_108/B1 (3097:3442:3787)(3097:3442:3787))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_122/A1 (2331:2611:2891)(2331:2611:2891))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_122/A0 (2331:2611:2891)(2331:2611:2891))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_124/D1 (1783:1960:2138)(1783:1960:2138))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_124/D0 (1783:1960:2138)(1783:1960:2138))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_129/B1 (3097:3443:3789)(3097:3443:3789))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_129/B0 (3097:3443:3789)(3097:3443:3789))
+        (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_146/D1 (2528:2770:3012)(2528:2770:3012))
+        (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (483:579:675)(483:579:675))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_67/B1 (1164:1329:1494)(1164:1329:1494))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_67/B0 (1164:1329:1494)(1164:1329:1494))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_71/D1 (922:1019:1116)(922:1019:1116))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_107/A0 (758:888:1018)(758:888:1018))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_122/D1 (1260:1394:1528)(1260:1394:1528))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_122/D0 (1260:1394:1528)(1260:1394:1528))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_124/A1 (1502:1696:1891)(1502:1696:1891))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_124/A0 (1502:1696:1891)(1502:1696:1891))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_131/A1 (740:861:983)(740:861:983))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_134/C1 (559:678:798)(559:678:798))
+        (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_134/C0 (559:678:798)(559:678:798))
         (INTERCONNECT SLICE_7/F1 SLICE_7/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_8/Q1 SLICE_55/D0 (909:1001:1093)(909:1001:1093))
-        (INTERCONNECT SLICE_8/Q1 SLICE_63/A0 (1119:1276:1434)(1119:1276:1434))
-        (INTERCONNECT SLICE_8/Q1 SLICE_119/B0 (781:909:1037)(781:909:1037))
-        (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_8/Q0 SLICE_55/C0 (1353:1539:1725)(1353:1539:1725))
-        (INTERCONNECT SLICE_8/Q0 SLICE_63/C0 (1353:1539:1725)(1353:1539:1725))
-        (INTERCONNECT SLICE_8/Q0 SLICE_119/D0 (1706:1868:2031)(1706:1868:2031))
+        (INTERCONNECT SLICE_8/Q1 ram2e_ufm\/SLICE_57/C1 (989:1143:1298)(989:1143:1298))
+        (INTERCONNECT SLICE_8/Q1 ram2e_ufm\/SLICE_67/C1 (1364:1551:1738)(1364:1551:1738))
+        (INTERCONNECT SLICE_8/Q1 ram2e_ufm\/SLICE_122/C1 (1364:1551:1738)(1364:1551:1738))
+        (INTERCONNECT SLICE_8/Q1 ram2e_ufm\/SLICE_122/C0 (1364:1551:1738)(1364:1551:1738))
+        (INTERCONNECT SLICE_8/Q1 ram2e_ufm\/SLICE_134/A1 (1188:1353:1518)(1188:1353:1518))
+        (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (483:579:675)(483:579:675))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_67/A1 (1133:1295:1458)(1133:1295:1458))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_122/B1 (1165:1330:1495)(1165:1330:1495))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_122/B0 (1165:1330:1495)(1165:1330:1495))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_124/C0 (918:1068:1219)(918:1068:1219))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_129/A0 (1497:1691:1885)(1497:1691:1885))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_131/D1 (530:586:642)(530:586:642))
+        (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_134/B1 (779:910:1042)(779:910:1042))
         (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT PHI1_I/PADDI SLICE_9/C1 (1532:1704:1876)(1532:1704:1876))
-        (INTERCONNECT PHI1_I/PADDI nVOE_I/PADDO (2804:3086:3368)(2804:3086:3368))
-        (INTERCONNECT PHI1_I/PADDI PHI1_MGIOL/DI (544:554:565)(544:554:565))
-        (INTERCONNECT PHI1_MGIOL/IN SLICE_9/B1 (1392:1572:1753)(1392:1572:1753))
-        (INTERCONNECT SLICE_32/Q0 SLICE_9/A1 (1433:1620:1808)(1433:1620:1808))
-        (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_31/Q0 SLICE_9/D0 (984:1084:1185)(984:1084:1185))
-        (INTERCONNECT SLICE_31/Q0 SLICE_12/D0 (1440:1568:1696)(1440:1568:1696))
-        (INTERCONNECT SLICE_31/Q0 SLICE_13/D1 (1440:1568:1696)(1440:1568:1696))
-        (INTERCONNECT SLICE_31/Q0 SLICE_13/C0 (1778:1996:2214)(1778:1996:2214))
-        (INTERCONNECT SLICE_31/Q0 SLICE_14/A0 (2040:2267:2495)(2040:2267:2495))
-        (INTERCONNECT SLICE_31/Q0 SLICE_15/D0 (2200:2394:2588)(2200:2394:2588))
-        (INTERCONNECT SLICE_31/Q0 SLICE_16/D0 (2200:2394:2588)(2200:2394:2588))
-        (INTERCONNECT SLICE_31/Q0 SLICE_17/D0 (2194:2387:2581)(2194:2387:2581))
-        (INTERCONNECT SLICE_31/Q0 SLICE_18/D0 (2157:2354:2551)(2157:2354:2551))
-        (INTERCONNECT SLICE_31/Q0 SLICE_19/A1 (2035:2262:2489)(2035:2262:2489))
-        (INTERCONNECT SLICE_31/Q0 SLICE_19/A0 (2035:2262:2489)(2035:2262:2489))
-        (INTERCONNECT SLICE_31/Q0 SLICE_49/A1 (2040:2267:2495)(2040:2267:2495))
-        (INTERCONNECT SLICE_31/Q0 SLICE_49/A0 (2040:2267:2495)(2040:2267:2495))
-        (INTERCONNECT SLICE_31/Q0 SLICE_53/D1 (973:1072:1172)(973:1072:1172))
-        (INTERCONNECT SLICE_31/Q0 SLICE_57/C1 (995:1150:1306)(995:1150:1306))
-        (INTERCONNECT SLICE_31/Q0 SLICE_67/B0 (1590:1790:1990)(1590:1790:1990))
-        (INTERCONNECT SLICE_31/Q0 SLICE_82/C1 (1836:2052:2269)(1836:2052:2269))
-        (INTERCONNECT SLICE_31/Q0 SLICE_87/D1 (1825:1986:2148)(1825:1986:2148))
-        (INTERCONNECT SLICE_31/Q0 SLICE_91/C0 (1836:2052:2269)(1836:2052:2269))
-        (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_9/Q0 SLICE_19/B1 (1382:1575:1769)(1382:1575:1769))
-        (INTERCONNECT SLICE_9/Q0 SLICE_19/B0 (1382:1575:1769)(1382:1575:1769))
-        (INTERCONNECT SLICE_9/Q0 SLICE_82/D1 (1140:1265:1391)(1140:1265:1391))
+        (INTERCONNECT SLICE_33/Q1 SLICE_9/D1 (885:985:1086)(885:985:1086))
+        (INTERCONNECT SLICE_33/Q1 SLICE_9/B0 (1127:1295:1464)(1127:1295:1464))
+        (INTERCONNECT SLICE_33/Q1 SLICE_33/D0 (538:599:660)(538:599:660))
+        (INTERCONNECT SLICE_33/Q1 SLICE_35/D1 (538:599:660)(538:599:660))
+        (INTERCONNECT SLICE_33/Q1 SLICE_36/D1 (1276:1411:1547)(1276:1411:1547))
+        (INTERCONNECT SLICE_33/Q1 SLICE_37/A1 (2975:3305:3635)(2975:3305:3635))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_56/B1 (1143:1314:1485)(1143:1314:1485))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/CKE_7\/SLICE_61/B0 (1518:1721:1925)
+          (1518:1721:1925))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_67/A0 (1533:1730:1928)(1533:1730:1928))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_69/C0 (1661:1883:2105)(1661:1883:2105))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_72/A0 (768:899:1030)(768:899:1030))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_74/D0 (890:991:1092)(890:991:1092))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_77/B0 (1502:1703:1904)(1502:1703:1904))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_78/C1 (912:1070:1228)(912:1070:1228))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_80/B1 (1123:1292:1461)(1123:1292:1461))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_92/A1 (1148:1312:1476)(1148:1312:1476))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_95/C1 (2025:2278:2532)(2025:2278:2532))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_96/C1 (1704:1923:2142)(1704:1923:2142))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_102/C1 (949:1102:1256)(949:1102:1256))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_106/C1 (574:695:816)(574:695:816))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_112/D1 (2765:3029:3294)(2765:3029:3294))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_113/D0 (1693:1857:2021)(1693:1857:2021))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_115/C1 (1704:1923:2142)(1704:1923:2142))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_117/C1 (927:1088:1250)(927:1088:1250))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_117/C0 (927:1088:1250)(927:1088:1250))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_118/C1 (927:1088:1250)(927:1088:1250))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_118/C0 (927:1088:1250)(927:1088:1250))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_119/C1 (574:695:816)(574:695:816))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_119/C0 (574:695:816)(574:695:816))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_121/C1 (1282:1472:1662)(1282:1472:1662))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_121/C0 (1282:1472:1662)(1282:1472:1662))
+        (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_127/A1 (2273:2534:2796)(2273:2534:2796))
+        (INTERCONNECT SLICE_33/Q1 SLICE_138/A1 (753:882:1012)(753:882:1012))
+        (INTERCONNECT SLICE_33/Q1 SLICE_138/B0 (1123:1292:1461)(1123:1292:1461))
+        (INTERCONNECT SLICE_35/F0 SLICE_9/C1 (559:681:804)(559:681:804))
+        (INTERCONNECT SLICE_35/F0 SLICE_9/C0 (559:681:804)(559:681:804))
+        (INTERCONNECT SLICE_35/F0 SLICE_35/A1 (483:582:681)(483:582:681))
+        (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (7:16:25)(7:16:25))
+        (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_80/A1 (740:864:989)(740:864:989))
+        (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_92/C1 (929:1083:1238)(929:1083:1238))
+        (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_129/C0 (1293:1479:1665)(1293:1479:1665))
+        (INTERCONNECT SLICE_33/Q0 SLICE_9/A1 (786:917:1048)(786:917:1048))
+        (INTERCONNECT SLICE_33/Q0 SLICE_9/A0 (786:917:1048)(786:917:1048))
+        (INTERCONNECT SLICE_33/Q0 SLICE_35/C1 (536:648:760)(536:648:760))
+        (INTERCONNECT SLICE_33/Q0 SLICE_36/B1 (1198:1364:1531)(1198:1364:1531))
+        (INTERCONNECT SLICE_33/Q0 SLICE_37/D1 (956:1054:1153)(956:1054:1153))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_56/D1 (825:916:1008)(825:916:1008))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_69/B0 (1442:1634:1826)(1442:1634:1826))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_71/C0 (1581:1792:2003)(1581:1792:2003))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_72/A1 (786:917:1048)(786:917:1048))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_74/A0 (1551:1748:1946)(1551:1748:1946))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_77/A0 (1931:2161:2392)(1931:2161:2392))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_78/A1 (1035:1192:1349)(1035:1192:1349))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_80/D1 (2096:2293:2491)(2096:2293:2491))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_92/A0 (1166:1330:1494)(1166:1330:1494))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_95/B1 (2160:2423:2686)(2160:2423:2686))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_96/B1 (1067:1226:1386)(1067:1226:1386))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_106/A1 (1551:1748:1946)(1551:1748:1946))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_107/B1 (1431:1622:1813)(1431:1622:1813))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_112/B1 (1442:1634:1826)(1442:1634:1826))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_113/A0 (1551:1748:1946)(1551:1748:1946))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_115/D0 (1689:1860:2031)(1689:1860:2031))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_117/A1 (786:917:1048)(786:917:1048))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_117/A0 (786:917:1048)(786:917:1048))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_118/B1 (1156:1326:1497)(1156:1326:1497))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_118/B0 (1156:1326:1497)(1156:1326:1497))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_119/B1 (1067:1226:1386)(1067:1226:1386))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_119/B0 (1067:1226:1386)(1067:1226:1386))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_120/A1 (786:917:1048)(786:917:1048))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_120/A0 (786:917:1048)(786:917:1048))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_121/A1 (1931:2161:2392)(1931:2161:2392))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_121/A0 (1931:2161:2392)(1931:2161:2392))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_127/C1 (1929:2179:2429)(1929:2179:2429))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_127/C0 (1929:2179:2429)(1929:2179:2429))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_129/D1 (1689:1860:2031)(1689:1860:2031))
+        (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_129/D0 (1689:1860:2031)(1689:1860:2031))
+        (INTERCONNECT SLICE_33/Q0 SLICE_138/C1 (2107:2359:2612)(2107:2359:2612))
+        (INTERCONNECT SLICE_33/Q0 SLICE_138/C0 (2107:2359:2612)(2107:2359:2612))
+        (INTERCONNECT ram2e_ufm\/CKE_7\/SLICE_61/OFX0 SLICE_9/D0 (857:949:1042)
+          (857:949:1042))
         (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20/F1 SLICE_9/CE (2142:2382:2622)(2142:2382:2622))
-        (INTERCONNECT SLICE_20/F1 SLICE_12/CE (2142:2382:2622)(2142:2382:2622))
-        (INTERCONNECT SLICE_20/F1 SLICE_13/CE (2142:2382:2622)(2142:2382:2622))
-        (INTERCONNECT SLICE_20/F1 SLICE_14/CE (2142:2382:2622)(2142:2382:2622))
-        (INTERCONNECT SLICE_20/F1 SLICE_15/CE (2142:2382:2622)(2142:2382:2622))
-        (INTERCONNECT SLICE_20/F1 SLICE_16/CE (2142:2382:2622)(2142:2382:2622))
-        (INTERCONNECT SLICE_20/F1 SLICE_17/CE (2142:2382:2622)(2142:2382:2622))
-        (INTERCONNECT SLICE_20/F1 SLICE_18/CE (2142:2382:2622)(2142:2382:2622))
-        (INTERCONNECT SLICE_20/F1 SLICE_19/CE (2142:2382:2622)(2142:2382:2622))
-        (INTERCONNECT SLICE_20/F1 SLICE_19/CE (2142:2382:2622)(2142:2382:2622))
-        (INTERCONNECT SLICE_20/F1 Dout\[7\]_MGIOL/CE (2324:2586:2848)(2324:2586:2848))
-        (INTERCONNECT SLICE_20/F1 Dout\[6\]_MGIOL/CE (2324:2586:2848)(2324:2586:2848))
-        (INTERCONNECT SLICE_20/F1 Dout\[5\]_MGIOL/CE (2324:2586:2848)(2324:2586:2848))
-        (INTERCONNECT SLICE_20/F1 Dout\[4\]_MGIOL/CE (2324:2586:2848)(2324:2586:2848))
-        (INTERCONNECT SLICE_20/F1 Dout\[3\]_MGIOL/CE (2324:2586:2848)(2324:2586:2848))
-        (INTERCONNECT SLICE_20/F1 Dout\[2\]_MGIOL/CE (2324:2586:2848)(2324:2586:2848))
-        (INTERCONNECT SLICE_20/F1 Dout\[1\]_MGIOL/CE (2324:2586:2848)(2324:2586:2848))
-        (INTERCONNECT SLICE_20/F1 Dout\[0\]_MGIOL/CE (2324:2586:2848)(2324:2586:2848))
-        (INTERCONNECT SLICE_9/F1 SLICE_33/B1 (1222:1388:1554)(1222:1388:1554))
-        (INTERCONNECT SLICE_9/F1 SLICE_33/B0 (1222:1388:1554)(1222:1388:1554))
-        (INTERCONNECT SLICE_9/F1 SLICE_34/B1 (1222:1388:1554)(1222:1388:1554))
-        (INTERCONNECT SLICE_9/F1 SLICE_34/B0 (1222:1388:1554)(1222:1388:1554))
-        (INTERCONNECT SLICE_57/F0 SLICE_10/D1 (808:897:986)(808:897:986))
-        (INTERCONNECT SLICE_57/F0 SLICE_10/D0 (808:897:986)(808:897:986))
-        (INTERCONNECT SLICE_57/F0 SLICE_11/B1 (1050:1207:1364)(1050:1207:1364))
-        (INTERCONNECT SLICE_57/F0 SLICE_57/D1 (523:579:635)(523:579:635))
-        (INTERCONNECT SLICE_57/F0 SLICE_82/A0 (1018:1172:1327)(1018:1172:1327))
-        (INTERCONNECT SLICE_82/F1 SLICE_10/C1 (555:670:785)(555:670:785))
-        (INTERCONNECT SLICE_82/F1 SLICE_10/C0 (555:670:785)(555:670:785))
-        (INTERCONNECT SLICE_82/F1 SLICE_11/C1 (555:670:785)(555:670:785))
-        (INTERCONNECT SLICE_82/F1 SLICE_82/D0 (523:579:635)(523:579:635))
-        (INTERCONNECT SLICE_10/Q0 SLICE_10/B1 (780:909:1038)(780:909:1038))
-        (INTERCONNECT SLICE_10/Q0 SLICE_10/A0 (483:579:675)(483:579:675))
-        (INTERCONNECT SLICE_10/Q0 SLICE_11/D1 (538:599:660)(538:599:660))
-        (INTERCONNECT SLICE_10/Q0 SLICE_49/C1 (554:673:792)(554:673:792))
-        (INTERCONNECT SLICE_10/Q0 SLICE_77/D1 (881:982:1083)(881:982:1083))
-        (INTERCONNECT SLICE_10/Q0 SLICE_81/D1 (881:982:1083)(881:982:1083))
-        (INTERCONNECT SLICE_10/Q0 SLICE_87/A1 (753:882:1012)(753:882:1012))
-        (INTERCONNECT SLICE_10/Q0 SLICE_91/D1 (543:607:671)(543:607:671))
-        (INTERCONNECT SLICE_10/Q1 SLICE_10/A1 (483:579:675)(483:579:675))
-        (INTERCONNECT SLICE_10/Q1 SLICE_11/B0 (769:896:1023)(769:896:1023))
-        (INTERCONNECT SLICE_10/Q1 SLICE_18/C1 (811:974:1138)(811:974:1138))
-        (INTERCONNECT SLICE_10/Q1 SLICE_49/D0 (534:608:682)(534:608:682))
-        (INTERCONNECT SLICE_10/Q1 SLICE_54/A1 (1016:1190:1365)(1016:1190:1365))
-        (INTERCONNECT SLICE_10/Q1 SLICE_87/A0 (747:876:1005)(747:876:1005))
-        (INTERCONNECT SLICE_10/Q1 SLICE_93/A0 (1016:1190:1365)(1016:1190:1365))
-        (INTERCONNECT SLICE_10/Q1 SLICE_94/D0 (534:608:682)(534:608:682))
-        (INTERCONNECT SLICE_10/F1 SLICE_10/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_9/Q0 CKEout_MGIOL/OPOS (1081:1188:1296)(1081:1188:1296))
+        (INTERCONNECT SLICE_9/F1 ram2e_ufm\/SLICE_56/CE (1172:1292:1412)(1172:1292:1412))
+        (INTERCONNECT SLICE_31/Q0 SLICE_10/D0 (795:880:965)(795:880:965))
+        (INTERCONNECT SLICE_31/Q0 SLICE_18/B1 (1437:1625:1813)(1437:1625:1813))
+        (INTERCONNECT SLICE_31/Q0 SLICE_18/B0 (1437:1625:1813)(1437:1625:1813))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/M0 
+          (1487:1630:1774)(1487:1630:1774))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_77/B1 (1437:1625:1813)(1437:1625:1813))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_79/C0 (2267:2540:2814)(2267:2540:2814))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_80/D0 (1886:2072:2259)(1886:2072:2259))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_83/B0 (1437:1625:1813)(1437:1625:1813))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_130/C1 (1576:1783:1990)(1576:1783:1990))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_130/C0 (1576:1783:1990)(1576:1783:1990))
+        (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_133/A1 (2139:2388:2637)(2139:2388:2637))
+        (INTERCONNECT SLICE_10/Q0 SLICE_10/A0 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_10/Q0 SLICE_18/C1 (552:669:786)(552:669:786))
+        (INTERCONNECT SLICE_10/Q0 SLICE_18/D0 (528:582:636)(528:582:636))
+        (INTERCONNECT SLICE_10/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/C0 
+          (552:669:786)(552:669:786))
         (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77/F0 SLICE_10/LSR (887:985:1084)(887:985:1084))
-        (INTERCONNECT SLICE_77/F0 SLICE_10/LSR (887:985:1084)(887:985:1084))
-        (INTERCONNECT SLICE_77/F0 SLICE_11/LSR (887:985:1084)(887:985:1084))
-        (INTERCONNECT SLICE_11/F1 SLICE_11/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_11/Q0 SLICE_11/A0 (481:575:669)(481:575:669))
-        (INTERCONNECT SLICE_11/Q0 SLICE_18/A1 (1012:1172:1333)(1012:1172:1333))
-        (INTERCONNECT SLICE_11/Q0 SLICE_49/B0 (1110:1275:1440)(1110:1275:1440))
-        (INTERCONNECT SLICE_11/Q0 SLICE_54/A0 (751:878:1006)(751:878:1006))
-        (INTERCONNECT SLICE_11/Q0 SLICE_87/B0 (1414:1609:1804)(1414:1609:1804))
-        (INTERCONNECT SLICE_11/Q0 SLICE_91/B1 (1414:1609:1804)(1414:1609:1804))
-        (INTERCONNECT SLICE_11/Q0 SLICE_94/A0 (740:865:991)(740:865:991))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_10/CE (882:979:1076)(882:979:1076))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_18/CE (1647:1803:1960)(1647:1803:1960))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_18/CE (1647:1803:1960)(1647:1803:1960))
+        (INTERCONNECT SLICE_10/F1 nCSout_I/PADDO (1694:1892:2090)(1694:1892:2090))
+        (INTERCONNECT SLICE_11/Q0 SLICE_11/B1 (796:925:1054)(796:925:1054))
+        (INTERCONNECT SLICE_11/Q0 SLICE_11/B0 (796:925:1054)(796:925:1054))
+        (INTERCONNECT SLICE_11/Q0 SLICE_26/D1 (554:615:676)(554:615:676))
+        (INTERCONNECT SLICE_11/Q0 SLICE_26/D0 (554:615:676)(554:615:676))
+        (INTERCONNECT SLICE_11/Q0 ram2e_ufm\/SLICE_91/D1 (533:592:652)(533:592:652))
+        (INTERCONNECT SLICE_26/Q1 SLICE_11/A1 (756:882:1009)(756:882:1009))
+        (INTERCONNECT SLICE_26/Q1 SLICE_11/A0 (756:882:1009)(756:882:1009))
+        (INTERCONNECT SLICE_26/Q1 SLICE_26/A1 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_26/Q1 SLICE_26/A0 (756:882:1009)(756:882:1009))
+        (INTERCONNECT SLICE_26/Q1 ram2e_ufm\/SLICE_91/B1 (777:906:1036)(777:906:1036))
+        (INTERCONNECT SLICE_26/Q0 SLICE_11/D0 (525:582:639)(525:582:639))
+        (INTERCONNECT SLICE_26/Q0 SLICE_26/B1 (778:905:1032)(778:905:1032))
+        (INTERCONNECT SLICE_26/Q0 SLICE_26/B0 (778:905:1032)(778:905:1032))
+        (INTERCONNECT SLICE_26/Q0 ram2e_ufm\/CKE_7\/SLICE_61/A1 (751:878:1006)
+          (751:878:1006))
+        (INTERCONNECT SLICE_26/Q0 ram2e_ufm\/SLICE_91/C1 (879:1031:1183)(879:1031:1183))
         (INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_12/D1 (1655:1773:1892)(1655:1773:1892))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_14/D1 (2443:2640:2837)(2443:2640:2837))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_21/D0 (1655:1773:1892)(1655:1773:1892))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_23/A0 (1865:2049:2233)(1865:2049:2233))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_27/B0 (2224:2445:2667)(2224:2445:2667))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_54/C1 (2781:3068:3355)(2781:3068:3355))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_92/A0 (2556:2806:3057)(2556:2806:3057))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_94/C1 (2041:2247:2453)(2041:2247:2453))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_95/A0 (1463:1605:1747)(1463:1605:1747))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_98/D1 (2400:2583:2766)(2400:2583:2766))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_99/A0 (2948:3233:3519)(2948:3233:3519))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_100/B1 (2272:2491:2710)(2272:2491:2710))
-        (INTERCONNECT Din\[0\]_I/PADDI SLICE_118/A0 (2948:3233:3519)(2948:3233:3519))
-        (INTERCONNECT Din\[0\]_I/PADDI RD\[0\]_I/PADDO (3036:3277:3518)(3036:3277:3518))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_12/B1 (1969:2167:2366)(1969:2167:2366))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_24/D0 (2418:2615:2812)(2418:2615:2812))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_28/B0 (1953:2150:2347)(1953:2150:2347))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_36/C0 (2168:2378:2589)(2168:2378:2589))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_54/B1 (2333:2563:2793)(2333:2563:2793))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_94/B1 (2296:2529:2763)(2296:2529:2763))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_98/B1 (1964:2162:2360)(1964:2162:2360))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_99/B1 (1964:2162:2360)(1964:2162:2360))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_100/A1 (2291:2517:2744)(2291:2517:2744))
-        (INTERCONNECT Din\[2\]_I/PADDI SLICE_118/B0 (1964:2162:2360)(1964:2162:2360))
-        (INTERCONNECT Din\[2\]_I/PADDI RD\[2\]_I/PADDO (2592:2802:3012)(2592:2802:3012))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_12/A1 (1810:2009:2208)(1810:2009:2208))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_24/B1 (2533:2801:3069)(2533:2801:3069))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_28/B1 (1821:2020:2220)(1821:2020:2220))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_36/C1 (1478:1659:1840)(1478:1659:1840))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_81/A1 (1810:2009:2208)(1810:2009:2208))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_93/C0 (1981:2201:2422)(1981:2201:2422))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_94/D1 (1600:1733:1867)(1600:1733:1867))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_98/C1 (2356:2609:2862)(2356:2609:2862))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_99/D1 (2345:2543:2741)(2345:2543:2741))
-        (INTERCONNECT Din\[3\]_I/PADDI SLICE_100/C1 (2726:3011:3296)(2726:3011:3296))
-        (INTERCONNECT Din\[3\]_I/PADDI RD\[3\]_I/PADDO (3968:4326:4684)(3968:4326:4684))
-        (INTERCONNECT SLICE_12/F1 SLICE_12/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_16/F1 SLICE_12/B0 (1040:1196:1352)(1040:1196:1352))
-        (INTERCONNECT SLICE_16/F1 SLICE_13/D0 (798:886:974)(798:886:974))
-        (INTERCONNECT SLICE_16/F1 SLICE_16/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_12/Q0 SLICE_12/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_12/Q0 SLICE_110/A0 (733:853:974)(733:853:974))
-        (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_13/C1 (2164:2373:2582)(2164:2373:2582))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_26/D1 (2088:2248:2409)(2088:2248:2409))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_30/C1 (1724:1907:2090)(1724:1907:2090))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_38/C1 (2452:2698:2944)(2452:2698:2944))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_91/A0 (2255:2484:2713)(2255:2484:2713))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_93/D0 (2816:3039:3263)(2816:3039:3263))
-        (INTERCONNECT Din\[7\]_I/PADDI SLICE_98/C0 (2420:2670:2920)(2420:2670:2920))
-        (INTERCONNECT Din\[7\]_I/PADDI RD\[7\]_I/PADDO (2582:2790:2998)(2582:2790:2998))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_13/A1 (1856:2039:2222)(1856:2039:2222))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_25/B1 (2579:2831:3083)(2579:2831:3083))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_29/C1 (1641:1812:1983)(1641:1812:1983))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_37/A1 (1729:1905:2082)(1729:1905:2082))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_93/C1 (2354:2593:2833)(2354:2593:2833))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_98/A0 (2596:2843:3090)(2596:2843:3090))
-        (INTERCONNECT Din\[5\]_I/PADDI SLICE_99/B0 (2628:2877:3127)(2628:2877:3127))
-        (INTERCONNECT Din\[5\]_I/PADDI RD\[5\]_I/PADDO (3018:3255:3492)(3018:3255:3492))
-        (INTERCONNECT SLICE_100/F1 SLICE_13/B0 (1034:1189:1345)(1034:1189:1345))
-        (INTERCONNECT SLICE_100/F1 SLICE_100/B0 (511:606:702)(511:606:702))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_11/CE (1245:1369:1494)(1245:1369:1494))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_26/CE (1245:1369:1494)(1245:1369:1494))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_26/CE (1245:1369:1494)(1245:1369:1494))
+        (INTERCONNECT SLICE_11/F1 ram2e_ufm\/CKE_7\/SLICE_61/C1 (541:653:766)(541:653:766))
+        (INTERCONNECT SLICE_13/F1 SLICE_12/D1 (520:573:626)(520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_62/F1 SLICE_12/C1 (534:645:756)(534:645:756))
+        (INTERCONNECT ram2e_ufm\/SLICE_62/F1 ram2e_ufm\/SLICE_62/D0 (523:579:635)
+          (523:579:635))
+        (INTERCONNECT ram2e_ufm\/SLICE_84/F1 SLICE_12/B1 (781:910:1039)(781:910:1039))
+        (INTERCONNECT ram2e_ufm\/SLICE_84/F1 ram2e_ufm\/SLICE_84/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_84/F1 ram2e_ufm\/SLICE_87/B0 (1108:1272:1436)
+          (1108:1272:1436))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_12/A1 (751:875:999)(751:875:999))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_12/B0 (1110:1271:1433)(1110:1271:1433))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_13/C1 (890:1040:1191)(890:1040:1191))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_13/C0 (890:1040:1191)(890:1040:1191))
+        (INTERCONNECT SLICE_12/Q1 SLICE_12/D0 (550:615:680)(550:615:680))
+        (INTERCONNECT SLICE_12/Q1 SLICE_13/B1 (792:925:1058)(792:925:1058))
+        (INTERCONNECT SLICE_12/Q1 SLICE_13/B0 (792:925:1058)(792:925:1058))
+        (INTERCONNECT SLICE_12/Q1 SLICE_19/C1 (817:971:1125)(817:971:1125))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_40/D1 (532:590:648)(532:590:648))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/D1 (534:598:662)
+          (534:598:662))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_62/C1 (561:681:801)(561:681:801))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_62/C0 (561:681:801)(561:681:801))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_65/B0 (1375:1577:1779)(1375:1577:1779))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_84/B0 (776:908:1040)(776:908:1040))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_87/A0 (760:890:1021)(760:890:1021))
+        (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_101/B0 (776:908:1040)(776:908:1040))
+        (INTERCONNECT ram2e_ufm\/SLICE_63/F0 SLICE_12/C0 (541:653:766)(541:653:766))
+        (INTERCONNECT SLICE_13/Q0 SLICE_12/A0 (766:894:1023)(766:894:1023))
+        (INTERCONNECT SLICE_13/Q0 SLICE_13/A1 (766:894:1023)(766:894:1023))
         (INTERCONNECT SLICE_13/Q0 SLICE_13/A0 (481:575:669)(481:575:669))
-        (INTERCONNECT SLICE_13/Q0 SLICE_39/A0 (1010:1164:1319)(1010:1164:1319))
-        (INTERCONNECT SLICE_13/Q0 SLICE_53/D0 (535:596:658)(535:596:658))
-        (INTERCONNECT SLICE_13/Q0 SLICE_57/A1 (1010:1164:1319)(1010:1164:1319))
+        (INTERCONNECT SLICE_13/Q0 SLICE_15/B1 (1042:1199:1356)(1042:1199:1356))
+        (INTERCONNECT SLICE_13/Q0 SLICE_19/A1 (1754:1973:2192)(1754:1973:2192))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_40/B1 (1797:2019:2242)(1797:2019:2242))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_62/A1 (766:894:1023)(766:894:1023))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_62/A0 (766:894:1023)(766:894:1023))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_63/B1 (1760:1987:2214)(1760:1987:2214))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_83/D1 (1555:1709:1864)(1555:1709:1864))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_84/B1 (1760:1987:2214)(1760:1987:2214))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_94/C0 (1566:1775:1985)(1566:1775:1985))
+        (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_100/C0 (1191:1368:1545)(1191:1368:1545))
+        (INTERCONNECT SLICE_12/F1 SLICE_12/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_12/LSR (887:985:1084)(887:985:1084))
+        (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_12/LSR (887:985:1084)(887:985:1084))
+        (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_13/LSR (887:985:1084)(887:985:1084))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_40/C1 (570:687:804)(570:687:804))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/C1 
+          (570:687:804)(570:687:804))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_63/D1 (1625:1786:1947)(1625:1786:1947))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_63/A0 (736:853:971)(736:853:971))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_65/D1 (934:1028:1123)(934:1028:1123))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_65/D0 (934:1028:1123)(934:1028:1123))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_77/D1 (886:983:1080)(886:983:1080))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_82/C1 (570:687:804)(570:687:804))
+        (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_83/C0 (570:687:804)(570:687:804))
+        (INTERCONNECT ram2e_ufm\/SLICE_87/F1 SLICE_13/D1 (273:306:340)(273:306:340))
+        (INTERCONNECT ram2e_ufm\/SLICE_87/F1 SLICE_13/D0 (527:589:651)(527:589:651))
+        (INTERCONNECT ram2e_ufm\/SLICE_87/F1 ram2e_ufm\/SLICE_62/B0 (769:899:1029)
+          (769:899:1029))
+        (INTERCONNECT ram2e_ufm\/SLICE_87/F1 ram2e_ufm\/SLICE_87/C0 (284:372:461)
+          (284:372:461))
         (INTERCONNECT SLICE_13/F0 SLICE_13/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_13/F1 SLICE_77/C1 (547:660:773)(547:660:773))
-        (INTERCONNECT SLICE_13/F1 SLICE_81/A0 (746:869:993)(746:869:993))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_14/C1 (1735:1918:2101)(1735:1918:2101))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_15/A1 (2652:2915:3179)(2652:2915:3179))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_16/B1 (2346:2575:2804)(2346:2575:2804))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_17/B1 (2716:2977:3238)(2716:2977:3238))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_23/A1 (2631:2891:3152)(2631:2891:3152))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_27/D1 (2421:2616:2811)(2421:2616:2811))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_35/C1 (2160:2367:2575)(2160:2367:2575))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_54/D1 (2442:2640:2838)(2442:2640:2838))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_54/D0 (2442:2640:2838)(2442:2640:2838))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_93/A1 (2652:2915:3179)(2652:2915:3179))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_94/A1 (1934:2127:2321)(1934:2127:2321))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_100/D0 (1724:1852:1980)(1724:1852:1980))
-        (INTERCONNECT Din\[1\]_I/PADDI SLICE_118/C1 (2485:2733:2981)(2485:2733:2981))
-        (INTERCONNECT Din\[1\]_I/PADDI RD\[1\]_I/PADDO (2214:2389:2564)(2214:2389:2564))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_14/B1 (2287:2517:2747)(2287:2517:2747))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_15/D1 (2378:2576:2775)(2378:2576:2775))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_16/D1 (2378:2576:2775)(2378:2576:2775))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_17/D1 (2747:2977:3208)(2747:2977:3208))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_25/C0 (2047:2262:2477)(2047:2262:2477))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_29/B0 (2605:2868:3131)(2605:2868:3131))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_37/D0 (2768:2992:3217)(2768:2992:3217))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_81/B1 (2283:2511:2740)(2283:2511:2740))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_93/B1 (2283:2511:2740)(2283:2511:2740))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_94/B0 (2283:2511:2740)(2283:2511:2740))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_100/C0 (2056:2273:2490)(2056:2273:2490))
-        (INTERCONNECT Din\[4\]_I/PADDI SLICE_118/D1 (2747:2977:3208)(2747:2977:3208))
-        (INTERCONNECT Din\[4\]_I/PADDI RD\[4\]_I/PADDO (2954:3194:3434)(2954:3194:3434))
-        (INTERCONNECT SLICE_99/F1 SLICE_14/A1 (479:572:665)(479:572:665))
-        (INTERCONNECT SLICE_99/F1 SLICE_99/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_14/F1 SLICE_14/D0 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_18/F1 SLICE_14/C0 (536:650:764)(536:650:764))
-        (INTERCONNECT SLICE_18/F1 SLICE_15/B1 (1044:1209:1374)(1044:1209:1374))
-        (INTERCONNECT SLICE_18/F1 SLICE_16/A1 (1012:1174:1337)(1012:1174:1337))
-        (INTERCONNECT SLICE_18/F1 SLICE_17/C1 (541:658:775)(541:658:775))
-        (INTERCONNECT SLICE_18/F1 SLICE_18/C0 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_14/Q0 SLICE_14/B0 (773:896:1019)(773:896:1019))
-        (INTERCONNECT SLICE_14/Q0 SLICE_117/A1 (741:861:982)(741:861:982))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/F1 SLICE_14/C1 (811:957:1103)(811:957:1103))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_39/B0 (777:908:1040)
+          (777:908:1040))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_40/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_41/D0 (800:891:982)
+          (800:891:982))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_14/B1 (1956:2151:2346)(1956:2151:2346))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_16/A1 (1929:2122:2315)(1929:2122:2315))
+        (INTERCONNECT Din\[5\]_I/PADDI SLICE_29/A1 (2251:2478:2706)(2251:2478:2706))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_39/B1 (1956:2151:2346)
+          (1956:2151:2346))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_45/B1 (2326:2553:2780)
+          (2326:2553:2780))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_49/B1 (2690:2948:3207)
+          (2690:2948:3207))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/A1 
+          (2267:2497:2727)(2267:2497:2727))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/D0 
+          (1719:1846:1974)(1719:1846:1974))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_100/B1 (2320:2546:2773)
+          (2320:2546:2773))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_101/B1 (2299:2531:2764)
+          (2299:2531:2764))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_116/B1 (1961:2156:2352)
+          (1961:2156:2352))
+        (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_147/C0 (2052:2269:2486)
+          (2052:2269:2486))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_14/A1 (2246:2470:2695)(2246:2470:2695))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_16/B1 (3038:3331:3624)(3038:3331:3624))
+        (INTERCONNECT Din\[3\]_I/PADDI SLICE_28/B1 (3408:3733:4058)(3408:3733:4058))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_39/D1 (2733:2959:3185)
+          (2733:2959:3185))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_44/B1 (3408:3733:4058)
+          (3408:3733:4058))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_48/A1 (3006:3296:3587)
+          (3006:3296:3587))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/B1 
+          (2663:2923:3184)(2663:2923:3184))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/B0 
+          (2663:2923:3184)(2663:2923:3184))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_100/C1 (2036:2249:2462)
+          (2036:2249:2462))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_101/C1 (2759:3041:3324)
+          (2759:3041:3324))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_116/A1 (2958:3251:3544)
+          (2958:3251:3544))
+        (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_141/B0 (2648:2907:3166)
+          (2648:2907:3166))
+        (INTERCONNECT ram2e_ufm\/SLICE_142/F1 SLICE_14/D0 (266:290:315)(266:290:315))
+        (INTERCONNECT SLICE_14/F1 SLICE_14/C0 (280:362:445)(280:362:445))
+        (INTERCONNECT SLICE_14/F1 SLICE_17/C1 (537:645:753)(537:645:753))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_14/B0 (2210:2433:2656)(2210:2433:2656))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_15/A1 (1871:2055:2240)(1871:2055:2240))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_15/A0 (1871:2055:2240)(1871:2055:2240))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_16/D1 (1661:1780:1899)(1661:1780:1899))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_16/D0 (1661:1780:1899)(1661:1780:1899))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_17/D0 (2031:2182:2333)(2031:2182:2333))
+        (INTERCONNECT Din\[1\]_I/PADDI SLICE_27/A1 (2173:2393:2613)(2173:2393:2613))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_39/D0 (2401:2584:2767)
+          (2401:2584:2767))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_41/A1 (2505:2760:3016)
+          (2505:2760:3016))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_43/B1 (1872:2056:2240)
+          (1872:2056:2240))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_47/A1 (2162:2380:2598)
+          (2162:2380:2598))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/M0 
+          (1626:1733:1841)(1626:1733:1841))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_87/B1 (2537:2795:3053)
+          (2537:2795:3053))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_100/D1 (2290:2479:2669)
+          (2290:2479:2669))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_116/A0 (1871:2055:2240)
+          (1871:2055:2240))
+        (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_143/D1 (2765:2979:3194)
+          (2765:2979:3194))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_14/A0 (2284:2506:2729)(2284:2506:2729))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_17/A1 (1915:2105:2296)(1915:2105:2296))
+        (INTERCONNECT Din\[2\]_I/PADDI SLICE_28/D0 (1636:1752:1869)(1636:1752:1869))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_39/A0 (2981:3270:3560)
+          (2981:3270:3560))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_41/B1 (2316:2541:2766)
+          (2316:2541:2766))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_42/D1 (1641:1758:1875)
+          (1641:1758:1875))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_44/B0 (3037:3330:3623)
+          (3037:3330:3623))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_48/C0 (2016:2219:2423)
+          (2016:2219:2423))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_100/A1 (2210:2423:2637)
+          (2210:2423:2637))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_116/B0 (1947:2140:2333)
+          (1947:2140:2333))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_133/D1 (2016:2165:2315)
+          (2016:2165:2315))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_133/D0 (2016:2165:2315)
+          (2016:2165:2315))
+        (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_144/A1 (2981:3270:3560)
+          (2981:3270:3560))
         (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_98/F1 SLICE_15/C1 (541:655:769)(541:655:769))
-        (INTERCONNECT SLICE_98/F1 SLICE_16/B0 (1106:1275:1445)(1106:1275:1445))
-        (INTERCONNECT SLICE_98/F1 SLICE_17/A1 (483:582:681)(483:582:681))
-        (INTERCONNECT SLICE_98/F1 SLICE_98/B0 (515:616:718)(515:616:718))
-        (INTERCONNECT SLICE_15/F1 SLICE_15/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_15/Q0 SLICE_15/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_15/Q0 SLICE_86/D0 (1119:1240:1362)(1119:1240:1362))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_14/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_15/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_16/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_17/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_27/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_27/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_28/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_28/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_29/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_29/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_30/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_30/CE (1815:2020:2225)(1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_39/CE (1815:2020:2225)
+          (1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_40/CE (1815:2020:2225)
+          (1815:2020:2225))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_41/CE (1815:2020:2225)
+          (1815:2020:2225))
+        (INTERCONNECT SLICE_14/Q0 ram2e_ufm\/SLICE_147/D1 (520:573:626)(520:573:626))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_15/C1 (2190:2401:2613)(2190:2401:2613))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_15/C0 (2190:2401:2613)(2190:2401:2613))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_16/C1 (2517:2763:3010)(2517:2763:3010))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_16/B0 (2421:2645:2870)(2421:2645:2870))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_17/B0 (2785:3041:3297)(2785:3041:3297))
+        (INTERCONNECT Din\[7\]_I/PADDI SLICE_30/B1 (2406:2629:2852)(2406:2629:2852))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_41/B0 (1955:2151:2347)
+          (1955:2151:2347))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_46/B1 (2776:3031:3286)
+          (2776:3031:3286))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_50/B1 (3140:3426:3713)
+          (3140:3426:3713))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/A0 
+          (2389:2611:2833)(2389:2611:2833))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_94/D1 (2534:2721:2908)
+          (2534:2721:2908))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_100/B0 (2776:3031:3286)
+          (2776:3031:3286))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_142/B1 (1955:2151:2347)
+          (1955:2151:2347))
+        (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_143/D0 (2071:2230:2389)
+          (2071:2230:2389))
+        (INTERCONNECT SLICE_17/F1 SLICE_15/D0 (539:600:661)(539:600:661))
+        (INTERCONNECT SLICE_17/F1 SLICE_16/C0 (550:666:782)(550:666:782))
+        (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (280:362:445)(280:362:445))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_15/B0 (1827:2026:2225)(1827:2026:2225))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_16/A0 (1795:1991:2188)(1795:1991:2188))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_17/A0 (2165:2393:2622)(2165:2393:2622))
+        (INTERCONNECT Din\[4\]_I/PADDI SLICE_29/A0 (3295:3621:3948)(3295:3621:3948))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_41/D1 (2678:2912:3147)
+          (2678:2912:3147))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_45/C0 (3423:3774:4125)
+          (3423:3774:4125))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_49/C0 (3460:3807:4155)
+          (3460:3807:4155))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_84/D1 (2710:2938:3167)
+          (2710:2938:3167))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_94/C1 (2711:2993:3276)
+          (2711:2993:3276))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_100/A0 (2910:3203:3496)
+          (2910:3203:3496))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_133/B1 (2952:3248:3545)
+          (2952:3248:3545))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_133/B0 (2952:3248:3545)
+          (2952:3248:3545))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_142/D1 (2678:2912:3147)
+          (2678:2912:3147))
+        (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_142/D0 (2678:2912:3147)
+          (2678:2912:3147))
         (INTERCONNECT SLICE_15/F0 SLICE_15/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_16/Q0 SLICE_16/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_16/Q0 SLICE_114/C0 (803:944:1086)(803:944:1086))
+        (INTERCONNECT SLICE_15/Q0 ram2e_ufm\/SLICE_79/D1 (1116:1235:1355)(1116:1235:1355))
+        (INTERCONNECT SLICE_15/F1 ram2e_ufm\/SLICE_101/C0 (868:1015:1163)(868:1015:1163))
         (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_17/Q0 SLICE_17/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_17/Q0 SLICE_117/B1 (768:888:1008)(768:888:1008))
+        (INTERCONNECT SLICE_16/Q0 ram2e_ufm\/SLICE_85/A0 (740:863:986)(740:863:986))
+        (INTERCONNECT SLICE_16/F1 ram2e_ufm\/SLICE_84/A1 (736:854:973)(736:854:973))
+        (INTERCONNECT SLICE_16/F1 ram2e_ufm\/SLICE_101/A0 (1070:1231:1392)(1070:1231:1392))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_17/B1 (1956:2151:2346)(1956:2151:2346))
+        (INTERCONNECT Din\[0\]_I/PADDI SLICE_27/A0 (2256:2484:2712)(2256:2484:2712))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_39/C1 (2438:2689:2941)
+          (2438:2689:2941))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_41/C1 (2438:2689:2941)
+          (2438:2689:2941))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_42/A1 (2631:2891:3152)
+          (2631:2891:3152))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_42/D0 (2094:2254:2414)
+          (2094:2254:2414))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_43/D0 (2785:3011:3238)
+          (2785:3011:3238))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_65/C1 (1730:1912:2095)
+          (1730:1912:2095))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_86/C1 (1714:1895:2076)
+          (1714:1895:2076))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_94/D0 (2453:2644:2835)
+          (2453:2644:2835))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_116/C0 (1725:1907:2089)
+          (1725:1907:2089))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_133/C1 (1730:1912:2095)
+          (1730:1912:2095))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_141/C1 (2438:2689:2941)
+          (2438:2689:2941))
+        (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_142/C1 (2438:2689:2941)
+          (2438:2689:2941))
         (INTERCONNECT SLICE_17/F0 SLICE_17/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_77/F1 SLICE_18/D1 (533:593:654)(533:593:654))
-        (INTERCONNECT SLICE_77/F1 SLICE_77/B0 (511:606:702)(511:606:702))
-        (INTERCONNECT SLICE_100/F0 SLICE_18/B0 (762:883:1004)(762:883:1004))
+        (INTERCONNECT SLICE_17/Q0 ram2e_ufm\/SLICE_147/B1 (765:883:1001)(765:883:1001))
+        (INTERCONNECT SLICE_18/Q0 SLICE_18/D1 (534:591:648)(534:591:648))
         (INTERCONNECT SLICE_18/Q0 SLICE_18/A0 (479:571:663)(479:571:663))
-        (INTERCONNECT SLICE_18/Q0 SLICE_117/D1 (523:578:633)(523:578:633))
+        (INTERCONNECT SLICE_18/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/A0 
+          (744:866:989)(744:866:989))
+        (INTERCONNECT SLICE_18/Q1 SLICE_18/A1 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_18/Q1 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/B0 
+          (765:888:1011)(765:888:1011))
+        (INTERCONNECT SLICE_18/F1 SLICE_18/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19/Q0 SLICE_19/D1 (541:598:655)(541:598:655))
-        (INTERCONNECT SLICE_19/Q0 SLICE_19/D0 (541:598:655)(541:598:655))
-        (INTERCONNECT SLICE_19/Q0 SLICE_82/B1 (783:908:1033)(783:908:1033))
-        (INTERCONNECT SLICE_19/Q1 SLICE_19/C1 (542:652:762)(542:652:762))
-        (INTERCONNECT SLICE_19/Q1 SLICE_82/A1 (741:861:982)(741:861:982))
-        (INTERCONNECT SLICE_19/F1 SLICE_19/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_34/Q0 SLICE_20/D1 (821:941:1061)(821:941:1061))
-        (INTERCONNECT SLICE_34/Q0 SLICE_20/D0 (821:941:1061)(821:941:1061))
-        (INTERCONNECT SLICE_34/Q0 SLICE_34/C1 (986:1147:1309)(986:1147:1309))
-        (INTERCONNECT SLICE_34/Q0 SLICE_34/A0 (487:587:687)(487:587:687))
-        (INTERCONNECT SLICE_34/Q0 SLICE_35/B1 (1899:2158:2417)(1899:2158:2417))
-        (INTERCONNECT SLICE_34/Q0 SLICE_36/B1 (2274:2565:2857)(2274:2565:2857))
-        (INTERCONNECT SLICE_34/Q0 SLICE_36/B0 (2274:2565:2857)(2274:2565:2857))
-        (INTERCONNECT SLICE_34/Q0 SLICE_37/C1 (1278:1490:1702)(1278:1490:1702))
-        (INTERCONNECT SLICE_34/Q0 SLICE_37/C0 (1278:1490:1702)(1278:1490:1702))
-        (INTERCONNECT SLICE_34/Q0 SLICE_38/B1 (1509:1734:1959)(1509:1734:1959))
-        (INTERCONNECT SLICE_34/Q0 SLICE_38/B0 (1509:1734:1959)(1509:1734:1959))
-        (INTERCONNECT SLICE_34/Q0 SLICE_40/C0 (2048:2327:2606)(2048:2327:2606))
-        (INTERCONNECT SLICE_34/Q0 SLICE_41/B0 (1899:2158:2417)(1899:2158:2417))
-        (INTERCONNECT SLICE_34/Q0 SLICE_42/B1 (1899:2158:2417)(1899:2158:2417))
-        (INTERCONNECT SLICE_34/Q0 SLICE_44/LSR (887:993:1100)(887:993:1100))
-        (INTERCONNECT SLICE_34/Q0 SLICE_47/B0 (1433:1653:1873)(1433:1653:1873))
-        (INTERCONNECT SLICE_34/Q0 SLICE_48/D1 (562:631:701)(562:631:701))
-        (INTERCONNECT SLICE_34/Q0 SLICE_51/D1 (531:594:657)(531:594:657))
-        (INTERCONNECT SLICE_34/Q0 SLICE_53/B1 (1889:2147:2405)(1889:2147:2405))
-        (INTERCONNECT SLICE_34/Q0 SLICE_53/B0 (1889:2147:2405)(1889:2147:2405))
-        (INTERCONNECT SLICE_34/Q0 SLICE_57/D0 (2022:2244:2467)(2022:2244:2467))
-        (INTERCONNECT SLICE_34/Q0 SLICE_59/A0 (772:907:1042)(772:907:1042))
-        (INTERCONNECT SLICE_34/Q0 SLICE_66/A1 (2227:2514:2802)(2227:2514:2802))
-        (INTERCONNECT SLICE_34/Q0 SLICE_67/A0 (749:898:1048)(749:898:1048))
-        (INTERCONNECT SLICE_34/Q0 SLICE_68/A1 (2242:2531:2820)(2242:2531:2820))
-        (INTERCONNECT SLICE_34/Q0 SLICE_69/B0 (804:941:1079)(804:941:1079))
-        (INTERCONNECT SLICE_34/Q0 SLICE_71/A0 (772:907:1042)(772:907:1042))
-        (INTERCONNECT SLICE_34/Q0 SLICE_72/A0 (2596:2915:3235)(2596:2915:3235))
-        (INTERCONNECT SLICE_34/Q0 SLICE_79/B1 (1433:1653:1873)(1433:1653:1873))
-        (INTERCONNECT SLICE_34/Q0 SLICE_80/A1 (1136:1302:1469)(1136:1302:1469))
-        (INTERCONNECT SLICE_34/Q0 SLICE_83/B1 (2644:2967:3291)(2644:2967:3291))
-        (INTERCONNECT SLICE_34/Q0 SLICE_84/B0 (1899:2158:2417)(1899:2158:2417))
-        (INTERCONNECT SLICE_34/Q0 SLICE_92/B0 (2654:2978:3303)(2654:2978:3303))
-        (INTERCONNECT SLICE_34/Q0 SLICE_95/B0 (2259:2549:2839)(2259:2549:2839))
-        (INTERCONNECT SLICE_34/Q0 SLICE_96/B1 (1063:1251:1439)(1063:1251:1439))
-        (INTERCONNECT SLICE_34/Q0 SLICE_101/B1 (2644:2967:3291)(2644:2967:3291))
-        (INTERCONNECT SLICE_34/Q0 SLICE_101/B0 (2644:2967:3291)(2644:2967:3291))
-        (INTERCONNECT SLICE_34/Q0 SLICE_102/D1 (2782:3070:3359)(2782:3070:3359))
-        (INTERCONNECT SLICE_34/Q0 SLICE_102/D0 (2782:3070:3359)(2782:3070:3359))
-        (INTERCONNECT SLICE_34/Q0 SLICE_103/A1 (749:898:1048)(749:898:1048))
-        (INTERCONNECT SLICE_34/Q0 SLICE_103/A0 (749:898:1048)(749:898:1048))
-        (INTERCONNECT SLICE_34/Q0 SLICE_107/C1 (2793:3136:3480)(2793:3136:3480))
-        (INTERCONNECT SLICE_34/Q0 SLICE_107/C0 (2793:3136:3480)(2793:3136:3480))
-        (INTERCONNECT SLICE_34/Q0 SLICE_109/D1 (2037:2261:2485)(2037:2261:2485))
-        (INTERCONNECT SLICE_34/Q0 SLICE_109/D0 (2037:2261:2485)(2037:2261:2485))
-        (INTERCONNECT SLICE_34/Q0 SLICE_110/B1 (2654:2978:3303)(2654:2978:3303))
-        (INTERCONNECT SLICE_34/Q0 SLICE_110/B0 (2654:2978:3303)(2654:2978:3303))
-        (INTERCONNECT SLICE_34/Q0 SLICE_114/D1 (1267:1424:1581)(1267:1424:1581))
-        (INTERCONNECT SLICE_33/Q1 SLICE_20/C1 (1265:1451:1638)(1265:1451:1638))
-        (INTERCONNECT SLICE_33/Q1 SLICE_20/C0 (1265:1451:1638)(1265:1451:1638))
-        (INTERCONNECT SLICE_33/Q1 SLICE_33/C0 (557:673:789)(557:673:789))
-        (INTERCONNECT SLICE_33/Q1 SLICE_47/A0 (756:884:1012)(756:884:1012))
-        (INTERCONNECT SLICE_33/Q1 SLICE_48/C1 (2019:2270:2521)(2019:2270:2521))
-        (INTERCONNECT SLICE_33/Q1 SLICE_57/A0 (1447:1641:1836)(1447:1641:1836))
-        (INTERCONNECT SLICE_33/Q1 SLICE_59/B0 (788:918:1049)(788:918:1049))
-        (INTERCONNECT SLICE_33/Q1 SLICE_67/D1 (546:608:671)(546:608:671))
-        (INTERCONNECT SLICE_33/Q1 SLICE_69/A0 (2218:2479:2741)(2218:2479:2741))
-        (INTERCONNECT SLICE_33/Q1 SLICE_71/D0 (1681:1842:2003)(1681:1842:2003))
-        (INTERCONNECT SLICE_33/Q1 SLICE_79/A1 (1453:1648:1843)(1453:1648:1843))
-        (INTERCONNECT SLICE_33/Q1 SLICE_80/B1 (1548:1744:1941)(1548:1744:1941))
-        (INTERCONNECT SLICE_33/Q1 SLICE_96/A1 (1453:1648:1843)(1453:1648:1843))
-        (INTERCONNECT SLICE_33/Q1 SLICE_101/D1 (1681:1842:2003)(1681:1842:2003))
-        (INTERCONNECT SLICE_33/Q1 SLICE_101/D0 (1681:1842:2003)(1681:1842:2003))
-        (INTERCONNECT SLICE_33/Q1 SLICE_102/B1 (1548:1744:1941)(1548:1744:1941))
-        (INTERCONNECT SLICE_33/Q1 SLICE_102/B0 (1548:1744:1941)(1548:1744:1941))
-        (INTERCONNECT SLICE_33/Q1 SLICE_106/C1 (557:673:789)(557:673:789))
-        (INTERCONNECT SLICE_33/Q1 SLICE_106/C0 (557:673:789)(557:673:789))
-        (INTERCONNECT SLICE_33/Q1 SLICE_107/A0 (1516:1710:1904)(1516:1710:1904))
-        (INTERCONNECT SLICE_33/Q1 SLICE_112/B1 (1923:2152:2381)(1923:2152:2381))
-        (INTERCONNECT SLICE_34/Q1 SLICE_20/B1 (1060:1260:1460)(1060:1260:1460))
-        (INTERCONNECT SLICE_34/Q1 SLICE_20/B0 (1060:1260:1460)(1060:1260:1460))
-        (INTERCONNECT SLICE_34/Q1 SLICE_21/A1 (1503:1742:1982)(1503:1742:1982))
-        (INTERCONNECT SLICE_34/Q1 SLICE_21/A0 (1503:1742:1982)(1503:1742:1982))
-        (INTERCONNECT SLICE_34/Q1 SLICE_22/A1 (1858:2128:2398)(1858:2128:2398))
-        (INTERCONNECT SLICE_34/Q1 SLICE_22/A0 (1858:2128:2398)(1858:2128:2398))
-        (INTERCONNECT SLICE_34/Q1 SLICE_27/A1 (1503:1742:1982)(1503:1742:1982))
-        (INTERCONNECT SLICE_34/Q1 SLICE_27/A0 (1503:1742:1982)(1503:1742:1982))
-        (INTERCONNECT SLICE_34/Q1 SLICE_28/A1 (1503:1742:1982)(1503:1742:1982))
-        (INTERCONNECT SLICE_34/Q1 SLICE_28/A0 (1503:1742:1982)(1503:1742:1982))
-        (INTERCONNECT SLICE_34/Q1 SLICE_29/A1 (1503:1742:1982)(1503:1742:1982))
-        (INTERCONNECT SLICE_34/Q1 SLICE_29/A0 (1503:1742:1982)(1503:1742:1982))
-        (INTERCONNECT SLICE_34/Q1 SLICE_30/A1 (1503:1742:1982)(1503:1742:1982))
-        (INTERCONNECT SLICE_34/Q1 SLICE_30/A0 (1503:1742:1982)(1503:1742:1982))
-        (INTERCONNECT SLICE_34/Q1 SLICE_34/A1 (481:575:669)(481:575:669))
-        (INTERCONNECT SLICE_34/Q1 SLICE_34/C0 (557:673:789)(557:673:789))
-        (INTERCONNECT SLICE_34/Q1 SLICE_39/B0 (1050:1249:1448)(1050:1249:1448))
-        (INTERCONNECT SLICE_34/Q1 SLICE_44/B0 (778:942:1106)(778:942:1106))
-        (INTERCONNECT SLICE_34/Q1 SLICE_47/D0 (1198:1363:1528)(1198:1363:1528))
-        (INTERCONNECT SLICE_34/Q1 SLICE_48/A1 (1788:2051:2315)(1788:2051:2315))
-        (INTERCONNECT SLICE_34/Q1 SLICE_51/C1 (557:673:789)(557:673:789))
-        (INTERCONNECT SLICE_34/Q1 SLICE_51/C0 (557:673:789)(557:673:789))
-        (INTERCONNECT SLICE_34/Q1 SLICE_53/A1 (1503:1742:1982)(1503:1742:1982))
-        (INTERCONNECT SLICE_34/Q1 SLICE_57/C0 (819:1005:1191)(819:1005:1191))
-        (INTERCONNECT SLICE_34/Q1 SLICE_59/D0 (1198:1363:1528)(1198:1363:1528))
-        (INTERCONNECT SLICE_34/Q1 SLICE_67/D0 (536:632:728)(536:632:728))
-        (INTERCONNECT SLICE_34/Q1 SLICE_69/C0 (1589:1842:2095)(1589:1842:2095))
-        (INTERCONNECT SLICE_34/Q1 SLICE_71/B0 (1820:2086:2352)(1820:2086:2352))
-        (INTERCONNECT SLICE_34/Q1 SLICE_72/D0 (1642:1846:2050)(1642:1846:2050))
-        (INTERCONNECT SLICE_34/Q1 SLICE_79/D1 (1198:1363:1528)(1198:1363:1528))
-        (INTERCONNECT SLICE_34/Q1 SLICE_80/D1 (1942:2171:2401)(1942:2171:2401))
-        (INTERCONNECT SLICE_34/Q1 SLICE_83/A1 (1488:1726:1964)(1488:1726:1964))
-        (INTERCONNECT SLICE_34/Q1 SLICE_96/D1 (818:950:1082)(818:950:1082))
-        (INTERCONNECT SLICE_34/Q1 SLICE_101/A1 (1488:1726:1964)(1488:1726:1964))
-        (INTERCONNECT SLICE_34/Q1 SLICE_101/A0 (1488:1726:1964)(1488:1726:1964))
-        (INTERCONNECT SLICE_34/Q1 SLICE_102/A1 (1868:2139:2410)(1868:2139:2410))
-        (INTERCONNECT SLICE_34/Q1 SLICE_102/A0 (1868:2139:2410)(1868:2139:2410))
-        (INTERCONNECT SLICE_34/Q1 SLICE_103/D1 (536:632:728)(536:632:728))
-        (INTERCONNECT SLICE_34/Q1 SLICE_103/D0 (536:632:728)(536:632:728))
-        (INTERCONNECT SLICE_34/Q1 SLICE_107/D1 (1658:1863:2069)(1658:1863:2069))
-        (INTERCONNECT SLICE_34/Q1 SLICE_107/D0 (1658:1863:2069)(1658:1863:2069))
-        (INTERCONNECT SLICE_34/Q1 SLICE_110/D1 (802:932:1063)(802:932:1063))
-        (INTERCONNECT SLICE_34/Q1 SLICE_111/D1 (1699:1895:2092)(1699:1895:2092))
-        (INTERCONNECT SLICE_34/Q1 SLICE_111/D0 (1699:1895:2092)(1699:1895:2092))
-        (INTERCONNECT SLICE_34/Q1 SLICE_112/A1 (1488:1726:1964)(1488:1726:1964))
-        (INTERCONNECT SLICE_34/Q1 SLICE_112/A0 (1488:1726:1964)(1488:1726:1964))
-        (INTERCONNECT SLICE_34/Q1 SLICE_113/A1 (2279:2573:2867)(2279:2573:2867))
-        (INTERCONNECT SLICE_34/Q1 SLICE_113/A0 (2279:2573:2867)(2279:2573:2867))
-        (INTERCONNECT SLICE_33/Q0 SLICE_20/A1 (1477:1679:1881)(1477:1679:1881))
-        (INTERCONNECT SLICE_33/Q0 SLICE_20/A0 (1477:1679:1881)(1477:1679:1881))
-        (INTERCONNECT SLICE_33/Q0 SLICE_21/C1 (984:1143:1303)(984:1143:1303))
-        (INTERCONNECT SLICE_33/Q0 SLICE_22/D1 (832:939:1047)(832:939:1047))
-        (INTERCONNECT SLICE_33/Q0 SLICE_22/D0 (832:939:1047)(832:939:1047))
-        (INTERCONNECT SLICE_33/Q0 SLICE_33/A0 (485:583:681)(485:583:681))
-        (INTERCONNECT SLICE_33/Q0 SLICE_47/A1 (775:908:1042)(775:908:1042))
-        (INTERCONNECT SLICE_33/Q0 SLICE_47/C0 (1304:1490:1676)(1304:1490:1676))
-        (INTERCONNECT SLICE_33/Q0 SLICE_48/B1 (1155:1330:1505)(1155:1330:1505))
-        (INTERCONNECT SLICE_33/Q0 SLICE_48/A0 (775:908:1042)(775:908:1042))
-        (INTERCONNECT SLICE_33/Q0 SLICE_57/B0 (1444:1651:1859)(1444:1651:1859))
-        (INTERCONNECT SLICE_33/Q0 SLICE_59/C0 (903:1061:1219)(903:1061:1219))
-        (INTERCONNECT SLICE_33/Q0 SLICE_67/C1 (1583:1809:2036)(1583:1809:2036))
-        (INTERCONNECT SLICE_33/Q0 SLICE_69/D0 (913:1020:1127)(913:1020:1127))
-        (INTERCONNECT SLICE_33/Q0 SLICE_71/C0 (924:1086:1248)(924:1086:1248))
-        (INTERCONNECT SLICE_33/Q0 SLICE_80/C0 (818:978:1138)(818:978:1138))
-        (INTERCONNECT SLICE_33/Q0 SLICE_83/C1 (1181:1380:1580)(1181:1380:1580))
-        (INTERCONNECT SLICE_33/Q0 SLICE_96/B0 (1814:2053:2293)(1814:2053:2293))
-        (INTERCONNECT SLICE_33/Q0 SLICE_101/C1 (1181:1380:1580)(1181:1380:1580))
-        (INTERCONNECT SLICE_33/Q0 SLICE_101/C0 (1181:1380:1580)(1181:1380:1580))
-        (INTERCONNECT SLICE_33/Q0 SLICE_102/C1 (546:671:796)(546:671:796))
-        (INTERCONNECT SLICE_33/Q0 SLICE_106/B1 (782:913:1044)(782:913:1044))
-        (INTERCONNECT SLICE_33/Q0 SLICE_106/B0 (782:913:1044)(782:913:1044))
-        (INTERCONNECT SLICE_33/Q0 SLICE_111/B1 (1813:2052:2292)(1813:2052:2292))
-        (INTERCONNECT SLICE_33/Q0 SLICE_111/B0 (1813:2052:2292)(1813:2052:2292))
-        (INTERCONNECT SLICE_33/Q0 SLICE_112/D1 (832:939:1047)(832:939:1047))
-        (INTERCONNECT SLICE_33/Q0 SLICE_112/B0 (1412:1624:1837)(1412:1624:1837))
-        (INTERCONNECT SLICE_33/Q0 SLICE_113/C1 (1952:2210:2469)(1952:2210:2469))
-        (INTERCONNECT SLICE_33/Q0 SLICE_113/C0 (1952:2210:2469)(1952:2210:2469))
-        (INTERCONNECT SLICE_33/Q0 SLICE_115/B0 (1049:1222:1395)(1049:1222:1395))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 SLICE_19/C0 (809:960:1112)(809:960:1112))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 SLICE_31/C1 (546:675:804)(546:675:804))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_95/C0 (546:675:804)
+          (546:675:804))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_96/C0 (286:377:469)
+          (286:377:469))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_132/B1 (517:621:726)
+          (517:621:726))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_132/A0 (485:587:689)
+          (485:587:689))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_140/C1 (818:982:1146)
+          (818:982:1146))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_140/C0 (818:982:1146)
+          (818:982:1146))
+        (INTERCONNECT SLICE_20/Q1 SLICE_19/A0 (1002:1154:1306)(1002:1154:1306))
+        (INTERCONNECT SLICE_20/Q1 RAout\[1\]_MGIOL/OPOS (1411:1555:1700)(1411:1555:1700))
+        (INTERCONNECT SLICE_34/Q1 SLICE_19/M0 (1132:1257:1382)(1132:1257:1382))
+        (INTERCONNECT SLICE_34/Q1 SLICE_34/A1 (483:579:675)(483:579:675))
+        (INTERCONNECT SLICE_34/Q1 SLICE_34/A0 (748:874:1001)(748:874:1001))
+        (INTERCONNECT SLICE_34/Q1 SLICE_35/A0 (748:874:1001)(748:874:1001))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_42/A0 (2182:2464:2746)(2182:2464:2746))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_43/A1 (1799:2030:2261)(1799:2030:2261))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_43/A0 (1799:2030:2261)(1799:2030:2261))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_44/A1 (2182:2464:2746)(2182:2464:2746))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_44/D0 (1624:1801:1979)(1624:1801:1979))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_45/A1 (1799:2030:2261)(1799:2030:2261))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_45/A0 (1799:2030:2261)(1799:2030:2261))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_46/A1 (1799:2030:2261)(1799:2030:2261))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_46/A0 (1799:2030:2261)(1799:2030:2261))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_51/D0 (1624:1801:1979)(1624:1801:1979))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_56/A1 (1439:1639:1839)(1439:1639:1839))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_69/A0 (1439:1639:1839)(1439:1639:1839))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_71/D0 (1609:1776:1944)(1609:1776:1944))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_72/B0 (772:896:1020)(772:896:1020))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_74/B0 (1851:2086:2322)(1851:2086:2322))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_77/C0 (840:994:1149)(840:994:1149))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_78/A0 (1439:1639:1839)(1439:1639:1839))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_79/A0 (2182:2464:2746)(2182:2464:2746))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_95/A1 (1819:2052:2285)(1819:2052:2285))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_96/A1 (1823:2065:2307)(1823:2065:2307))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_102/A1 (2199:2465:2731)(2199:2465:2731))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_105/A1 (1439:1639:1839)(1439:1639:1839))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_107/A1 (1409:1606:1803)(1409:1606:1803))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_113/A1 (2199:2465:2731)(2199:2465:2731))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_115/A0 (2199:2465:2731)(2199:2465:2731))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_117/B1 (2621:2923:3226)(2621:2923:3226))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_117/B0 (2621:2923:3226)(2621:2923:3226))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_118/A1 (2589:2889:3189)(2589:2889:3189))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_118/A0 (2589:2889:3189)(2589:2889:3189))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_119/A1 (1439:1639:1839)(1439:1639:1839))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_119/A0 (1439:1639:1839)(1439:1639:1839))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_120/D1 (2379:2613:2848)(2379:2613:2848))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_120/D0 (2379:2613:2848)(2379:2613:2848))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_121/B1 (1071:1238:1406)(1071:1238:1406))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_121/B0 (1071:1238:1406)(1071:1238:1406))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_127/B1 (1851:2086:2322)(1851:2086:2322))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_127/B0 (1851:2086:2322)(1851:2086:2322))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_135/D1 (1609:1776:1944)(1609:1776:1944))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_135/D0 (1609:1776:1944)(1609:1776:1944))
+        (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_136/C1 (1178:1369:1561)(1178:1369:1561))
+        (INTERCONNECT SLICE_34/Q1 SLICE_138/B1 (774:904:1034)(774:904:1034))
+        (INTERCONNECT SLICE_138/F0 SLICE_19/LSR (1135:1258:1382)(1135:1258:1382))
+        (INTERCONNECT SLICE_19/F0 SLICE_20/C1 (800:939:1079)(800:939:1079))
+        (INTERCONNECT SLICE_19/Q0 ram2e_ufm\/SLICE_136/A0 (730:848:967)(730:848:967))
+        (INTERCONNECT SLICE_19/F1 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/B1 
+          (775:903:1032)(775:903:1032))
+        (INTERCONNECT SLICE_19/F1 ram2e_ufm\/SLICE_65/A1 (736:854:973)(736:854:973))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_20/D1 (897:1007:1118)(897:1007:1118))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_21/B0 (774:904:1034)(774:904:1034))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_22/A1 (749:884:1019)(749:884:1019))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_31/A1 (485:587:689)(485:587:689))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_95/B0 (517:621:726)
+          (517:621:726))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_96/D0 (897:1007:1118)
+          (897:1007:1118))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_132/D1 (897:1007:1118)
+          (897:1007:1118))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_132/D0 (897:1007:1118)
+          (897:1007:1118))
+        (INTERCONNECT Ain\[1\]_I/PADDI SLICE_20/B1 (2708:2959:3210)(2708:2959:3210))
+        (INTERCONNECT ram2e_ufm\/SLICE_107/F0 SLICE_20/A1 (733:848:964)(733:848:964))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_20/D0 (528:584:640)(528:584:640))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_21/C1 (541:658:775)(541:658:775))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_22/A0 (740:867:995)(740:867:995))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_23/A1 (1083:1249:1415)(1083:1249:1415))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_23/A0 (1083:1249:1415)(1083:1249:1415))
+        (INTERCONNECT ram2e_ufm\/SLICE_124/F0 SLICE_20/C0 (534:639:744)(534:639:744))
+        (INTERCONNECT ram2e_ufm\/SLICE_132/F1 SLICE_20/A0 (730:848:967)(730:848:967))
+        (INTERCONNECT SLICE_20/F1 SLICE_20/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_20/Q0 SLICE_31/A1 (730:848:967)(730:848:967))
-        (INTERCONNECT Ain\[1\]_I/PADDI SLICE_21/B1 (2143:2376:2609)(2143:2376:2609))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_21/B0 (1398:1579:1760)
-          (1398:1579:1760))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO0 SLICE_27/C0 (1167:1335:1503)
-          (1167:1335:1503))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_20/CE (901:1003:1106)(901:1003:1106))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_20/CE (901:1003:1106)(901:1003:1106))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_21/CE (1265:1399:1533)(1265:1399:1533))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_21/CE (1265:1399:1533)(1265:1399:1533))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_22/CE (1265:1399:1533)(1265:1399:1533))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_22/CE (1265:1399:1533)(1265:1399:1533))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_23/CE (901:1003:1106)(901:1003:1106))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_23/CE (901:1003:1106)(901:1003:1106))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_24/CE (1618:1781:1945)(1618:1781:1945))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_24/CE (1618:1781:1945)(1618:1781:1945))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_25/CE (1242:1369:1496)(1242:1369:1496))
+        (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_25/CE (1242:1369:1496)(1242:1369:1496))
+        (INTERCONNECT SLICE_20/Q0 SLICE_31/B0 (770:896:1022)(770:896:1022))
+        (INTERCONNECT SLICE_20/Q0 ram2e_ufm\/SLICE_132/A1 (733:853:974)(733:853:974))
+        (INTERCONNECT SLICE_20/Q0 RAout\[0\]_MGIOL/OPOS (1342:1481:1620)(1342:1481:1620))
+        (INTERCONNECT SLICE_31/F1 SLICE_21/B1 (772:897:1023)(772:897:1023))
+        (INTERCONNECT ram2e_ufm\/SLICE_140/F1 SLICE_21/D0 (266:290:315)(266:290:315))
+        (INTERCONNECT ram2e_ufm\/SLICE_134/F0 SLICE_21/C0 (800:939:1079)(800:939:1079))
+        (INTERCONNECT Ain\[2\]_I/PADDI SLICE_21/A0 (2594:2847:3101)(2594:2847:3101))
+        (INTERCONNECT SLICE_21/F1 SLICE_21/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_86/F0 SLICE_21/CE (876:972:1069)(876:972:1069))
-        (INTERCONNECT SLICE_21/Q0 SLICE_117/C1 (981:1133:1285)(981:1133:1285))
-        (INTERCONNECT SLICE_21/Q0 SLICE_117/C0 (981:1133:1285)(981:1133:1285))
-        (INTERCONNECT SLICE_21/F1 RA\[1\]_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
-        (INTERCONNECT Ain\[3\]_I/PADDI SLICE_22/C1 (2031:2242:2454)(2031:2242:2454))
-        (INTERCONNECT Ain\[0\]_I/PADDI SLICE_22/C0 (1949:2165:2382)(1949:2165:2382))
+        (INTERCONNECT SLICE_21/Q0 ram2e_ufm\/SLICE_140/A1 (733:853:974)(733:853:974))
+        (INTERCONNECT SLICE_21/Q0 RAout\[2\]_MGIOL/OPOS (1340:1473:1606)(1340:1473:1606))
+        (INTERCONNECT SLICE_21/Q1 SLICE_31/D1 (539:599:659)(539:599:659))
+        (INTERCONNECT SLICE_21/Q1 SLICE_31/D0 (539:599:659)(539:599:659))
+        (INTERCONNECT SLICE_21/Q1 RAout\[3\]_MGIOL/OPOS (1084:1193:1303)(1084:1193:1303))
+        (INTERCONNECT ram2e_ufm\/SLICE_140/F0 SLICE_22/D1 (520:573:626)(520:573:626))
+        (INTERCONNECT Ain\[5\]_I/PADDI SLICE_22/C1 (1530:1696:1862)(1530:1696:1862))
+        (INTERCONNECT ram2e_ufm\/SLICE_124/F1 SLICE_22/B1 (1136:1293:1450)(1136:1293:1450))
+        (INTERCONNECT ram2e_ufm\/SLICE_95/F0 SLICE_22/C0 (868:1015:1163)(868:1015:1163))
         (INTERCONNECT SLICE_22/F1 SLICE_22/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_101/F0 SLICE_22/CE (879:978:1078)(879:978:1078))
-        (INTERCONNECT SLICE_101/F0 SLICE_22/CE (879:978:1078)(879:978:1078))
-        (INTERCONNECT SLICE_101/F0 RA\[7\]_MGIOL/CE (1440:1590:1741)(1440:1590:1741))
-        (INTERCONNECT SLICE_101/F0 RA\[6\]_MGIOL/CE (1440:1590:1741)(1440:1590:1741))
-        (INTERCONNECT SLICE_101/F0 RA\[5\]_MGIOL/CE (1923:2108:2293)(1923:2108:2293))
-        (INTERCONNECT SLICE_101/F0 RA\[4\]_MGIOL/CE (1923:2108:2293)(1923:2108:2293))
-        (INTERCONNECT SLICE_101/F0 RA\[2\]_MGIOL/CE (1923:2108:2293)(1923:2108:2293))
-        (INTERCONNECT SLICE_101/F0 RA\[1\]_MGIOL/CE (1440:1590:1741)(1440:1590:1741))
-        (INTERCONNECT SLICE_22/Q0 SLICE_31/C0 (1342:1527:1712)(1342:1527:1712))
-        (INTERCONNECT SLICE_22/Q0 RA\[0\]_I/PADDO (1365:1550:1735)(1365:1550:1735))
-        (INTERCONNECT SLICE_22/Q1 SLICE_31/A0 (1541:1736:1932)(1541:1736:1932))
-        (INTERCONNECT SLICE_22/Q1 RA\[3\]_I/PADDO (1365:1550:1735)(1365:1550:1735))
-        (INTERCONNECT SLICE_117/F1 SLICE_23/D1 (541:599:658)(541:599:658))
-        (INTERCONNECT SLICE_117/F1 SLICE_23/D0 (541:599:658)(541:599:658))
-        (INTERCONNECT SLICE_117/F1 SLICE_24/A1 (1141:1299:1457)(1141:1299:1457))
-        (INTERCONNECT SLICE_117/F1 SLICE_24/A0 (1141:1299:1457)(1141:1299:1457))
-        (INTERCONNECT SLICE_117/F1 SLICE_25/A1 (1141:1299:1457)(1141:1299:1457))
-        (INTERCONNECT SLICE_117/F1 SLICE_25/A0 (1141:1299:1457)(1141:1299:1457))
-        (INTERCONNECT SLICE_117/F1 SLICE_26/A1 (1141:1299:1457)(1141:1299:1457))
-        (INTERCONNECT SLICE_117/F1 SLICE_26/A0 (1141:1299:1457)(1141:1299:1457))
-        (INTERCONNECT SLICE_27/Q1 SLICE_23/C1 (541:653:766)(541:653:766))
-        (INTERCONNECT SLICE_27/Q0 SLICE_23/C0 (541:653:766)(541:653:766))
+        (INTERCONNECT SLICE_22/Q0 ram2e_ufm\/SLICE_95/A0 (1177:1341:1505)(1177:1341:1505))
+        (INTERCONNECT SLICE_22/Q0 RAout\[4\]_MGIOL/OPOS (1667:1835:2003)(1667:1835:2003))
+        (INTERCONNECT SLICE_22/Q1 ram2e_ufm\/SLICE_140/D0 (523:578:633)(523:578:633))
+        (INTERCONNECT SLICE_22/Q1 RAout\[5\]_MGIOL/OPOS (1084:1193:1303)(1084:1193:1303))
+        (INTERCONNECT ram2e_ufm\/SLICE_132/F0 SLICE_23/C1 (531:639:747)(531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_96/F0 SLICE_23/C0 (531:639:747)(531:639:747))
         (INTERCONNECT SLICE_23/F1 SLICE_23/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_67/F0 SLICE_23/CE (887:984:1082)(887:984:1082))
-        (INTERCONNECT SLICE_67/F0 SLICE_23/CE (887:984:1082)(887:984:1082))
-        (INTERCONNECT SLICE_67/F0 SLICE_24/CE (908:1009:1111)(908:1009:1111))
-        (INTERCONNECT SLICE_67/F0 SLICE_24/CE (908:1009:1111)(908:1009:1111))
-        (INTERCONNECT SLICE_67/F0 SLICE_25/CE (908:1009:1111)(908:1009:1111))
-        (INTERCONNECT SLICE_67/F0 SLICE_25/CE (908:1009:1111)(908:1009:1111))
-        (INTERCONNECT SLICE_67/F0 SLICE_26/CE (908:1009:1111)(908:1009:1111))
-        (INTERCONNECT SLICE_67/F0 SLICE_26/CE (908:1009:1111)(908:1009:1111))
-        (INTERCONNECT SLICE_67/F0 SLICE_86/B0 (1517:1707:1897)(1517:1707:1897))
-        (INTERCONNECT SLICE_67/F0 SLICE_114/A0 (1812:2034:2257)(1812:2034:2257))
-        (INTERCONNECT SLICE_23/Q0 SLICE_96/D0 (1221:1345:1469)(1221:1345:1469))
-        (INTERCONNECT SLICE_23/Q1 SLICE_110/A1 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_28/Q1 SLICE_24/C1 (868:1015:1163)(868:1015:1163))
-        (INTERCONNECT SLICE_28/Q0 SLICE_24/B0 (1099:1259:1420)(1099:1259:1420))
+        (INTERCONNECT SLICE_23/Q0 ram2e_ufm\/SLICE_96/B0 (765:888:1011)(765:888:1011))
+        (INTERCONNECT SLICE_23/Q0 RAout\[6\]_MGIOL/OPOS (1786:1945:2105)(1786:1945:2105))
+        (INTERCONNECT SLICE_23/Q1 ram2e_ufm\/SLICE_132/B0 (765:888:1011)(765:888:1011))
+        (INTERCONNECT SLICE_23/Q1 RAout\[7\]_MGIOL/OPOS (1411:1555:1700)(1411:1555:1700))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F0 SLICE_24/D1 (536:594:652)(536:594:652))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F0 SLICE_25/D1 (536:594:652)(536:594:652))
+        (INTERCONNECT ram2e_ufm\/SLICE_146/F1 SLICE_24/B1 (1136:1293:1450)(1136:1293:1450))
+        (INTERCONNECT SLICE_24/Q1 SLICE_24/A1 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_24/Q1 RAout\[9\]_MGIOL/OPOS (1340:1473:1606)(1340:1473:1606))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F0 SLICE_24/D0 (964:1060:1157)(964:1060:1157))
+        (INTERCONNECT SLICE_24/Q0 SLICE_24/C0 (534:644:754)(534:644:754))
+        (INTERCONNECT SLICE_24/Q0 RAout\[8\]_MGIOL/OPOS (1411:1555:1700)(1411:1555:1700))
+        (INTERCONNECT ram2e_ufm\/SLICE_127/F0 SLICE_24/B0 (772:897:1023)(772:897:1023))
+        (INTERCONNECT ram2e_ufm\/SLICE_115/F1 SLICE_24/A0 (733:854:976)(733:854:976))
+        (INTERCONNECT ram2e_ufm\/SLICE_115/F1 ram2e_ufm\/SLICE_115/C0 (280:362:445)
+          (280:362:445))
         (INTERCONNECT SLICE_24/F1 SLICE_24/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_24/Q0 SLICE_69/B1 (1500:1688:1877)(1500:1688:1877))
-        (INTERCONNECT SLICE_24/Q1 SLICE_103/B1 (1099:1259:1420)(1099:1259:1420))
-        (INTERCONNECT SLICE_29/Q1 SLICE_25/C1 (868:1015:1163)(868:1015:1163))
-        (INTERCONNECT SLICE_29/Q0 SLICE_25/D0 (964:1060:1157)(964:1060:1157))
+        (INTERCONNECT SLICE_29/Q0 SLICE_25/C1 (1269:1444:1620)(1269:1444:1620))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F0 SLICE_25/B1 (513:611:710)(513:611:710))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F0 ram2e_ufm\/SLICE_74/C1 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F0 ram2e_ufm\/SLICE_146/A1 (1331:1522:1713)
+          (1331:1522:1713))
+        (INTERCONNECT SLICE_25/Q1 SLICE_25/A1 (479:571:663)(479:571:663))
+        (INTERCONNECT SLICE_25/Q1 RAout\[11\]_MGIOL/OPOS (1775:1951:2127)(1775:1951:2127))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F0 SLICE_25/D0 (523:573:623)(523:573:623))
+        (INTERCONNECT ram2e_ufm\/SLICE_74/F1 SLICE_25/C0 (531:639:747)(531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_106/F0 SLICE_25/B0 (762:883:1004)(762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_129/F0 SLICE_25/A0 (733:848:964)(733:848:964))
         (INTERCONNECT SLICE_25/F1 SLICE_25/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_25/Q0 SLICE_102/C0 (800:939:1079)(800:939:1079))
-        (INTERCONNECT SLICE_25/Q1 SLICE_107/B0 (1136:1293:1450)(1136:1293:1450))
-        (INTERCONNECT SLICE_30/Q1 SLICE_26/C1 (868:1015:1163)(868:1015:1163))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_26/C0 (2057:2274:2492)(2057:2274:2492))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_30/B0 (2689:2947:3206)(2689:2947:3206))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_38/D0 (2447:2637:2828)(2447:2637:2828))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_49/B1 (2397:2618:2839)(2397:2618:2839))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/A1 (2703:2958:3214)(2703:2958:3214))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_81/C1 (2504:2749:2994)(2504:2749:2994))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_87/B1 (2331:2558:2786)(2331:2558:2786))
-        (INTERCONNECT Din\[6\]_I/PADDI SLICE_91/C1 (2427:2676:2926)(2427:2676:2926))
-        (INTERCONNECT Din\[6\]_I/PADDI RD\[6\]_I/PADDO (2214:2389:2564)(2214:2389:2564))
-        (INTERCONNECT SLICE_30/Q0 SLICE_26/B0 (1099:1259:1420)(1099:1259:1420))
+        (INTERCONNECT SLICE_25/Q0 ram2e_ufm\/SLICE_106/B0 (765:888:1011)(765:888:1011))
+        (INTERCONNECT SLICE_25/Q0 RAout\[10\]_MGIOL/OPOS (1756:1937:2118)(1756:1937:2118))
         (INTERCONNECT SLICE_26/F1 SLICE_26/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_26/Q0 SLICE_47/B1 (1142:1299:1457)(1142:1299:1457))
-        (INTERCONNECT SLICE_26/Q0 SLICE_59/D1 (1227:1351:1476)(1227:1351:1476))
-        (INTERCONNECT SLICE_26/Q1 SLICE_96/A0 (1104:1258:1413)(1104:1258:1413))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO1 SLICE_27/C1 (1455:1646:1838)
-          (1455:1646:1838))
+        (INTERCONNECT ram2e_ufm\/SLICE_43/Q1 SLICE_27/D1 (964:1060:1157)(964:1060:1157))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_27/B1 (1042:1195:1349)(1042:1195:1349))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_27/B0 (1042:1195:1349)(1042:1195:1349))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/A1 (1395:1579:1764)(1395:1579:1764))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/A0 (1395:1579:1764)(1395:1579:1764))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_29/B1 (1797:2016:2235)(1797:2016:2235))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_29/B0 (1797:2016:2235)(1797:2016:2235))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/D1 (1185:1304:1423)(1185:1304:1423))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/D0 (1185:1304:1423)(1185:1304:1423))
+        (INTERCONNECT ram2e_ufm\/SLICE_43/Q0 SLICE_27/C0 (541:653:766)(541:653:766))
         (INTERCONNECT SLICE_27/F1 SLICE_27/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_114/F0 SLICE_27/CE (882:979:1076)(882:979:1076))
-        (INTERCONNECT SLICE_114/F0 SLICE_27/CE (882:979:1076)(882:979:1076))
-        (INTERCONNECT SLICE_114/F0 SLICE_28/CE (903:1004:1105)(903:1004:1105))
-        (INTERCONNECT SLICE_114/F0 SLICE_28/CE (903:1004:1105)(903:1004:1105))
-        (INTERCONNECT SLICE_114/F0 SLICE_29/CE (903:1004:1105)(903:1004:1105))
-        (INTERCONNECT SLICE_114/F0 SLICE_29/CE (903:1004:1105)(903:1004:1105))
-        (INTERCONNECT SLICE_114/F0 SLICE_30/CE (903:1004:1105)(903:1004:1105))
-        (INTERCONNECT SLICE_114/F0 SLICE_30/CE (903:1004:1105)(903:1004:1105))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO3 SLICE_28/D1 (1596:1735:1874)
-          (1596:1735:1874))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO2 SLICE_28/C0 (1607:1801:1995)
-          (1607:1801:1995))
+        (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/C1 (1345:1528:1712)(1345:1528:1712))
+        (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/C0 (1345:1528:1712)(1345:1528:1712))
+        (INTERCONNECT SLICE_27/Q1 ram2e_ufm\/SLICE_78/B0 (1031:1183:1336)(1031:1183:1336))
+        (INTERCONNECT ram2e_ufm\/SLICE_44/Q1 SLICE_28/C1 (541:653:766)(541:653:766))
+        (INTERCONNECT ram2e_ufm\/SLICE_44/Q0 SLICE_28/C0 (541:653:766)(541:653:766))
         (INTERCONNECT SLICE_28/F1 SLICE_28/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_28/F0 SLICE_28/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO5 SLICE_29/D1 (1596:1735:1874)
-          (1596:1735:1874))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO4 SLICE_29/C0 (1607:1801:1995)
-          (1607:1801:1995))
+        (INTERCONNECT SLICE_28/Q0 ram2e_ufm\/SLICE_146/C1 (868:1015:1163)(868:1015:1163))
+        (INTERCONNECT SLICE_28/Q1 ram2e_ufm\/SLICE_74/D1 (894:983:1072)(894:983:1072))
+        (INTERCONNECT ram2e_ufm\/SLICE_45/Q1 SLICE_29/C1 (975:1126:1278)(975:1126:1278))
+        (INTERCONNECT ram2e_ufm\/SLICE_45/Q0 SLICE_29/C0 (541:653:766)(541:653:766))
         (INTERCONNECT SLICE_29/F1 SLICE_29/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO7 SLICE_30/D1 (1596:1735:1874)
-          (1596:1735:1874))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBDATO6 SLICE_30/C0 (1607:1801:1995)
-          (1607:1801:1995))
+        (INTERCONNECT SLICE_29/Q1 ram2e_ufm\/SLICE_72/D1 (1410:1533:1656)(1410:1533:1656))
+        (INTERCONNECT ram2e_ufm\/SLICE_46/Q1 SLICE_30/A1 (740:863:986)(740:863:986))
+        (INTERCONNECT Din\[6\]_I/PADDI SLICE_30/B0 (1767:1946:2126)(1767:1946:2126))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_40/A1 (2544:2801:3059)
+          (2544:2801:3059))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_42/B1 (3316:3640:3964)
+          (3316:3640:3964))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_46/B0 (2946:3238:3530)
+          (2946:3238:3530))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_50/C0 (3449:3791:4134)
+          (3449:3791:4134))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/D1 
+          (3010:3267:3524)(3010:3267:3524))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_62/D1 (2698:2921:3145)
+          (2698:2921:3145))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_65/B1 (2561:2819:3078)
+          (2561:2819:3078))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_82/D1 (2334:2526:2718)
+          (2334:2526:2718))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_83/C1 (2345:2592:2839)
+          (2345:2592:2839))
+        (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_144/D0 (2313:2503:2693)
+          (2313:2503:2693))
+        (INTERCONNECT ram2e_ufm\/SLICE_46/Q0 SLICE_30/A0 (740:863:986)(740:863:986))
         (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT nEN80_I/PADDI SLICE_31/C1 (1716:1896:2076)(1716:1896:2076))
-        (INTERCONNECT nEN80_I/PADDI SLICE_79/C1 (2085:2297:2509)(2085:2297:2509))
-        (INTERCONNECT nEN80_I/PADDI SLICE_106/A0 (3012:3297:3583)(3012:3297:3583))
-        (INTERCONNECT nEN80_I/PADDI SLICE_115/B1 (2316:2541:2766)(2316:2541:2766))
-        (INTERCONNECT nEN80_I/PADDI SLICE_117/A0 (2279:2501:2723)(2279:2501:2723))
-        (INTERCONNECT nWE_I/PADDI SLICE_31/B1 (2133:2352:2571)(2133:2352:2571))
-        (INTERCONNECT nWE_I/PADDI SLICE_31/B0 (2133:2352:2571)(2133:2352:2571))
-        (INTERCONNECT nC07X_I/PADDI SLICE_31/D0 (1673:1815:1957)(1673:1815:1957))
+        (INTERCONNECT SLICE_30/Q0 ram2e_ufm\/SLICE_129/A1 (1174:1336:1498)(1174:1336:1498))
+        (INTERCONNECT SLICE_30/Q1 ram2e_ufm\/SLICE_127/A0 (999:1149:1299)(999:1149:1299))
+        (INTERCONNECT Ain\[3\]_I/PADDI SLICE_31/B1 (2626:2882:3138)(2626:2882:3138))
+        (INTERCONNECT nC07X_I/PADDI SLICE_31/C0 (2424:2651:2878)(2424:2651:2878))
+        (INTERCONNECT nWE_I/PADDI SLICE_31/A0 (2889:3153:3417)(2889:3153:3417))
+        (INTERCONNECT nWE_I/PADDI SLICE_36/A0 (3270:3567:3864)(3270:3567:3864))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/CKE_7\/SLICE_61/D0 (3398:3666:3935)
+          (3398:3666:3935))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_92/D1 (3398:3666:3935)(3398:3666:3935))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_112/B0 (3780:4129:4479)(3780:4129:4479))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_113/B0 (3629:3963:4298)(3629:3963:4298))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_136/B1 (4416:4832:5248)(4416:4832:5248))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_136/B0 (4416:4832:5248)(4416:4832:5248))
+        (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_137/D1 (1782:1926:2070)(1782:1926:2070))
         (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_71/F0 SLICE_31/CE (1140:1269:1399)(1140:1269:1399))
-        (INTERCONNECT SLICE_71/F0 SLICE_59/C1 (546:664:783)(546:664:783))
-        (INTERCONNECT SLICE_71/F0 SLICE_71/D1 (525:584:643)(525:584:643))
-        (INTERCONNECT SLICE_31/F1 nDOE_I/PADDO (1456:1605:1755)(1456:1605:1755))
-        (INTERCONNECT SLICE_97/F0 SLICE_32/B1 (1214:1383:1552)(1214:1383:1552))
-        (INTERCONNECT SLICE_97/F0 SLICE_51/D0 (972:1073:1174)(972:1073:1174))
-        (INTERCONNECT SLICE_97/F0 SLICE_75/B1 (1034:1189:1345)(1034:1189:1345))
-        (INTERCONNECT SLICE_72/F1 SLICE_32/A1 (730:848:967)(730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_127/F1 SLICE_31/CE (539:596:653)(539:596:653))
+        (INTERCONNECT ram2e_ufm\/SLICE_110/F1 SLICE_32/D1 (535:598:662)(535:598:662))
+        (INTERCONNECT ram2e_ufm\/SLICE_110/F1 ram2e_ufm\/SLICE_58/B1 (767:894:1021)
+          (767:894:1021))
+        (INTERCONNECT ram2e_ufm\/SLICE_110/F1 ram2e_ufm\/SLICE_110/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_57/F1 SLICE_32/C1 (541:653:766)(541:653:766))
+        (INTERCONNECT ram2e_ufm\/SLICE_131/F1 SLICE_32/B1 (1099:1259:1420)(1099:1259:1420))
+        (INTERCONNECT ram2e_ufm\/SLICE_146/F0 SLICE_32/A1 (999:1149:1299)(999:1149:1299))
         (INTERCONNECT SLICE_32/F1 SLICE_32/C0 (277:356:436)(277:356:436))
+        (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (481:575:669)(481:575:669))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_137/A1 (771:900:1030)(771:900:1030))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_137/A0 (771:900:1030)(771:900:1030))
+        (INTERCONNECT SLICE_32/Q0 SLICE_139/D0 (528:582:636)(528:582:636))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_141/D1 (561:625:689)(561:625:689))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_141/D0 (561:625:689)(561:625:689))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_142/B0 (1173:1337:1501)(1173:1337:1501))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_143/B1 (1183:1348:1513)(1183:1348:1513))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_143/B0 (1183:1348:1513)(1183:1348:1513))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_144/B1 (1183:1348:1513)(1183:1348:1513))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_144/B0 (1183:1348:1513)(1183:1348:1513))
+        (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_147/B0 (1173:1337:1501)(1173:1337:1501))
         (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_107/F1 SLICE_33/D1 (523:573:623)(523:573:623))
-        (INTERCONNECT SLICE_106/F1 SLICE_33/C1 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_106/F1 SLICE_34/D1 (271:301:332)(271:301:332))
-        (INTERCONNECT SLICE_106/F1 SLICE_34/D0 (525:584:643)(525:584:643))
-        (INTERCONNECT SLICE_67/F1 SLICE_33/A1 (749:894:1040)(749:894:1040))
-        (INTERCONNECT SLICE_67/F1 SLICE_44/C0 (290:387:485)(290:387:485))
-        (INTERCONNECT SLICE_67/F1 SLICE_51/B1 (778:914:1050)(778:914:1050))
-        (INTERCONNECT SLICE_67/F1 SLICE_53/A0 (1446:1661:1877)(1446:1661:1877))
-        (INTERCONNECT SLICE_67/F1 SLICE_67/C0 (290:387:485)(290:387:485))
-        (INTERCONNECT SLICE_67/F1 SLICE_72/C0 (816:985:1155)(816:985:1155))
-        (INTERCONNECT SLICE_67/F1 SLICE_103/C1 (290:387:485)(290:387:485))
-        (INTERCONNECT SLICE_67/F1 SLICE_103/B0 (775:914:1053)(775:914:1053))
-        (INTERCONNECT SLICE_67/F1 SLICE_110/C1 (892:1059:1227)(892:1059:1227))
-        (INTERCONNECT SLICE_67/F1 SLICE_110/C0 (892:1059:1227)(892:1059:1227))
-        (INTERCONNECT SLICE_102/F1 SLICE_33/D0 (266:290:315)(266:290:315))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 SLICE_33/D1 (548:615:683)(548:615:683))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 SLICE_38/B1 (1038:1199:1361)(1038:1199:1361))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_78/D0 (527:589:651)
+          (527:589:651))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_79/B0 (1471:1674:1877)
+          (1471:1674:1877))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_105/B1 (1471:1674:1877)
+          (1471:1674:1877))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_106/D0 (548:615:683)
+          (548:615:683))
+        (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_135/A0 (758:891:1024)
+          (758:891:1024))
+        (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_33/C1 (550:666:782)(550:666:782))
+        (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_34/C1 (888:1041:1194)(888:1041:1194))
+        (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_34/C0 (888:1041:1194)(888:1041:1194))
+        (INTERCONNECT ram2e_ufm\/SLICE_106/F1 ram2e_ufm\/SLICE_106/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_135/F1 SLICE_33/B1 (765:889:1013)(765:889:1013))
+        (INTERCONNECT ram2e_ufm\/SLICE_135/F1 SLICE_33/C0 (280:362:445)(280:362:445))
+        (INTERCONNECT SLICE_139/F0 SLICE_33/A1 (1010:1161:1312)(1010:1161:1312))
+        (INTERCONNECT SLICE_139/F0 SLICE_33/A0 (1010:1161:1312)(1010:1161:1312))
+        (INTERCONNECT SLICE_139/F0 SLICE_34/B1 (1380:1570:1761)(1380:1570:1761))
+        (INTERCONNECT SLICE_139/F0 SLICE_34/B0 (1380:1570:1761)(1380:1570:1761))
+        (INTERCONNECT ram2e_ufm\/SLICE_117/F1 SLICE_33/B0 (1099:1259:1420)(1099:1259:1420))
         (INTERCONNECT SLICE_33/F1 SLICE_33/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_34/Q0 SLICE_34/D1 (548:611:674)(548:611:674))
+        (INTERCONNECT SLICE_34/Q0 SLICE_34/D0 (548:611:674)(548:611:674))
+        (INTERCONNECT SLICE_34/Q0 SLICE_35/D0 (548:611:674)(548:611:674))
+        (INTERCONNECT SLICE_34/Q0 SLICE_38/C1 (954:1108:1262)(954:1108:1262))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_47/C1 (2210:2470:2730)(2210:2470:2730))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_48/B1 (2441:2714:2987)(2441:2714:2987))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_48/B0 (2441:2714:2987)(2441:2714:2987))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_49/A1 (2809:3114:3420)(2809:3114:3420))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_49/A0 (2809:3114:3420)(2809:3114:3420))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_50/A1 (2784:3087:3390)(2784:3087:3390))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_50/A0 (2784:3087:3390)(2784:3087:3390))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_52/A0 (3179:3516:3854)(3179:3516:3854))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_53/A0 (2809:3114:3420)(2809:3114:3420))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_54/A1 (2809:3114:3420)(2809:3114:3420))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_56/LSR (845:960:1075)(845:960:1075))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_69/D0 (1196:1339:1482)(1196:1339:1482))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_71/A0 (1948:2190:2433)(1948:2190:2433))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_72/D0 (563:629:695)(563:629:695))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_74/C0 (545:674:803)(545:674:803))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_77/D0 (816:926:1036)(816:926:1036))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_78/C0 (837:1003:1169)(837:1003:1169))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_79/D0 (2938:3207:3476)(2938:3207:3476))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_86/A1 (3549:3918:4288)(3549:3918:4288))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_89/A0 (2779:3081:3384)(2779:3081:3384))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_90/A0 (2809:3114:3420)(2809:3114:3420))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_95/D1 (2086:2302:2518)(2086:2302:2518))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_96/D1 (826:937:1048)(826:937:1048))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_97/A0 (2779:3081:3384)(2779:3081:3384))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_98/A0 (2809:3114:3420)(2809:3114:3420))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_102/D1 (943:1042:1141)(943:1042:1141))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_106/A0 (744:883:1023)(744:883:1023))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_107/C1 (2113:2376:2640)(2113:2376:2640))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_109/A1 (3549:3918:4288)(3549:3918:4288))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_112/D0 (1196:1339:1482)(1196:1339:1482))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_113/D1 (1313:1444:1575)(1313:1444:1575))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_115/D1 (1313:1444:1575)(1313:1444:1575))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_117/D1 (563:629:695)(563:629:695))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_117/D0 (563:629:695)(563:629:695))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_118/D1 (563:629:695)(563:629:695))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_118/D0 (563:629:695)(563:629:695))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_119/D1 (826:937:1048)(826:937:1048))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_119/D0 (826:937:1048)(826:937:1048))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_121/D1 (816:926:1036)(816:926:1036))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_121/D0 (816:926:1036)(816:926:1036))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_127/D1 (2086:2302:2518)(2086:2302:2518))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_127/D0 (2086:2302:2518)(2086:2302:2518))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_135/C1 (549:665:781)(549:665:781))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_135/C0 (549:665:781)(549:665:781))
+        (INTERCONNECT SLICE_34/Q0 SLICE_138/D0 (1180:1321:1463)(1180:1321:1463))
+        (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_145/A1 (2809:3114:3420)(2809:3114:3420))
         (INTERCONNECT SLICE_34/F1 SLICE_34/DI1 (0:0:0)(0:0:0))
         (INTERCONNECT SLICE_34/F0 SLICE_34/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_62/F1 SLICE_35/D1 (523:573:623)(523:573:623))
-        (INTERCONNECT SLICE_60/F1 SLICE_35/A1 (733:848:964)(733:848:964))
-        (INTERCONNECT SLICE_85/F0 SLICE_35/D0 (1153:1269:1385)(1153:1269:1385))
-        (INTERCONNECT SLICE_104/F0 SLICE_35/C0 (800:939:1079)(800:939:1079))
-        (INTERCONNECT SLICE_74/F1 SLICE_35/B0 (776:902:1028)(776:902:1028))
-        (INTERCONNECT SLICE_74/F1 SLICE_74/B0 (776:902:1028)(776:902:1028))
-        (INTERCONNECT SLICE_74/F1 SLICE_108/D0 (967:1066:1166)(967:1066:1166))
-        (INTERCONNECT SLICE_35/F1 SLICE_35/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_110/F0 SLICE_35/CE (1257:1386:1516)(1257:1386:1516))
-        (INTERCONNECT SLICE_110/F0 SLICE_35/CE (1257:1386:1516)(1257:1386:1516))
-        (INTERCONNECT SLICE_110/F0 SLICE_36/CE (1627:1789:1952)(1627:1789:1952))
-        (INTERCONNECT SLICE_110/F0 SLICE_36/CE (1627:1789:1952)(1627:1789:1952))
-        (INTERCONNECT SLICE_110/F0 SLICE_37/CE (1268:1399:1531)(1268:1399:1531))
-        (INTERCONNECT SLICE_110/F0 SLICE_37/CE (1268:1399:1531)(1268:1399:1531))
-        (INTERCONNECT SLICE_110/F0 SLICE_38/CE (1268:1399:1531)(1268:1399:1531))
-        (INTERCONNECT SLICE_110/F0 SLICE_38/CE (1268:1399:1531)(1268:1399:1531))
-        (INTERCONNECT SLICE_110/F0 SLICE_40/CE (1252:1381:1510)(1252:1381:1510))
-        (INTERCONNECT SLICE_110/F0 SLICE_40/CE (1252:1381:1510)(1252:1381:1510))
-        (INTERCONNECT SLICE_110/F0 SLICE_41/CE (1632:1795:1958)(1632:1795:1958))
-        (INTERCONNECT SLICE_110/F0 SLICE_41/CE (1632:1795:1958)(1632:1795:1958))
-        (INTERCONNECT SLICE_110/F0 SLICE_42/CE (1632:1795:1958)(1632:1795:1958))
-        (INTERCONNECT SLICE_110/F0 SLICE_42/CE (1632:1795:1958)(1632:1795:1958))
-        (INTERCONNECT SLICE_110/F0 SLICE_43/CE (1627:1789:1952)(1627:1789:1952))
-        (INTERCONNECT SLICE_110/F0 SLICE_43/CE (1627:1789:1952)(1627:1789:1952))
-        (INTERCONNECT SLICE_35/Q0 SLICE_40/B0 (1209:1375:1542)(1209:1375:1542))
-        (INTERCONNECT SLICE_35/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in (1236:1368:1501)
-          (1236:1368:1501))
-        (INTERCONNECT SLICE_35/Q1 SLICE_109/C0 (1682:1885:2088)(1682:1885:2088))
-        (INTERCONNECT SLICE_35/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in (1342:1474:1607)
-          (1342:1474:1607))
-        (INTERCONNECT SLICE_36/F1 SLICE_36/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_138/F1 SLICE_35/LSR (876:972:1069)(876:972:1069))
+        (INTERCONNECT SLICE_35/Q0 SLICE_139/C1 (905:1049:1193)(905:1049:1193))
+        (INTERCONNECT SLICE_35/F1 BA\[1\]_MGIOL/LSR (1438:1586:1735)(1438:1586:1735))
+        (INTERCONNECT SLICE_35/F1 BA\[0\]_MGIOL/LSR (1438:1586:1735)(1438:1586:1735))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_36/C1 (986:1144:1302)(986:1144:1302))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_37/B1 (783:915:1047)(783:915:1047))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_38/A1 (1099:1267:1436)(1099:1267:1436))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_91/A0 (1099:1267:1436)
+          (1099:1267:1436))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_92/C0 (986:1144:1302)
+          (986:1144:1302))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_105/C1 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_112/A1 (1099:1267:1436)
+          (1099:1267:1436))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_36/A1 (741:874:1008)(741:874:1008))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_37/C1 (814:972:1130)(814:972:1130))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_38/A0 (1013:1181:1350)(1013:1181:1350))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/CKE_7\/SLICE_61/A0 (741:874:1008)
+          (741:874:1008))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/SLICE_92/B1 (777:908:1040)
+          (777:908:1040))
+        (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/SLICE_113/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_69/F1 SLICE_36/D0 (789:873:958)(789:873:958))
+        (INTERCONNECT ram2e_ufm\/SLICE_92/F0 SLICE_36/C0 (531:639:747)(531:639:747))
+        (INTERCONNECT SLICE_36/F1 SLICE_36/B0 (762:883:1004)(762:883:1004))
         (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_36/Q0 SLICE_41/A0 (1073:1231:1390)(1073:1231:1390))
-        (INTERCONNECT SLICE_36/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI2in (1344:1479:1615)
-          (1344:1479:1615))
-        (INTERCONNECT SLICE_36/Q1 SLICE_68/D1 (523:578:633)(523:578:633))
-        (INTERCONNECT SLICE_36/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI3in (1084:1193:1303)
-          (1084:1193:1303))
-        (INTERCONNECT SLICE_37/F1 SLICE_37/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_36/Q0 nCASout_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
+        (INTERCONNECT ram2e_ufm\/SLICE_112/F0 SLICE_37/D0 (266:290:315)(266:290:315))
+        (INTERCONNECT SLICE_38/F1 SLICE_37/C0 (534:645:756)(534:645:756))
+        (INTERCONNECT SLICE_38/F1 SLICE_38/B0 (765:889:1013)(765:889:1013))
+        (INTERCONNECT SLICE_37/F1 SLICE_37/B0 (762:883:1004)(762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_91/F0 SLICE_37/A0 (730:848:967)(730:848:967))
         (INTERCONNECT SLICE_37/F0 SLICE_37/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_37/Q0 SLICE_114/A1 (1070:1230:1390)(1070:1230:1390))
-        (INTERCONNECT SLICE_37/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI4in (1084:1193:1303)
-          (1084:1193:1303))
-        (INTERCONNECT SLICE_37/Q1 SLICE_42/A1 (1433:1620:1808)(1433:1620:1808))
-        (INTERCONNECT SLICE_37/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI5in (1340:1473:1606)
-          (1340:1473:1606))
-        (INTERCONNECT SLICE_38/F1 SLICE_38/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT SLICE_37/Q0 nRASout_MGIOL/OPOS (1445:1584:1723)(1445:1584:1723))
+        (INTERCONNECT ram2e_ufm\/SLICE_136/F1 SLICE_38/D1 (1116:1235:1355)(1116:1235:1355))
+        (INTERCONNECT ram2e_ufm\/SLICE_105/F1 SLICE_38/D0 (523:573:623)(523:573:623))
+        (INTERCONNECT ram2e_ufm\/SLICE_112/F1 SLICE_38/C0 (534:645:756)(534:645:756))
+        (INTERCONNECT ram2e_ufm\/SLICE_112/F1 ram2e_ufm\/SLICE_112/C0 (280:362:445)
+          (280:362:445))
         (INTERCONNECT SLICE_38/F0 SLICE_38/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_38/Q0 SLICE_84/D0 (863:956:1049)(863:956:1049))
-        (INTERCONNECT SLICE_38/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI6in (1381:1513:1645)
-          (1381:1513:1645))
-        (INTERCONNECT SLICE_38/Q1 SLICE_109/C1 (1275:1451:1627)(1275:1451:1627))
-        (INTERCONNECT SLICE_38/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBADRI7in (1708:1875:2042)
-          (1708:1875:2042))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_39/B1 (1859:2070:2281)
-          (1859:2070:2281))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_45/B1 (1859:2070:2281)
-          (1859:2070:2281))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_57/B1 (1859:2070:2281)
-          (1859:2070:2281))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_64/C0 (1617:1814:2011)
-          (1617:1814:2011))
-        (INTERCONNECT ufmefb\/EFBInst_0/WBACKO SLICE_105/C1 (1166:1335:1504)
-          (1166:1335:1504))
-        (INTERCONNECT SLICE_63/F1 SLICE_39/A1 (736:854:973)(736:854:973))
-        (INTERCONNECT SLICE_63/F1 SLICE_52/B1 (768:889:1010)(768:889:1010))
-        (INTERCONNECT SLICE_39/F1 SLICE_39/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_39/F0 SLICE_39/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_52/F0 SLICE_39/CE (539:596:653)(539:596:653))
-        (INTERCONNECT SLICE_39/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCYCIin 
-          (1533:1667:1802)(1533:1667:1802))
-        (INTERCONNECT SLICE_39/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBSTBIin 
-          (1879:2052:2226)(1879:2052:2226))
-        (INTERCONNECT SLICE_90/F0 SLICE_40/D1 (526:588:650)(526:588:650))
-        (INTERCONNECT SLICE_90/F0 SLICE_41/A1 (1433:1630:1828)(1433:1630:1828))
-        (INTERCONNECT SLICE_90/F0 SLICE_88/D0 (526:588:650)(526:588:650))
-        (INTERCONNECT SLICE_68/F0 SLICE_40/C1 (875:1031:1188)(875:1031:1188))
-        (INTERCONNECT SLICE_68/F0 SLICE_43/A0 (737:864:992)(737:864:992))
-        (INTERCONNECT SLICE_68/F0 SLICE_68/C1 (284:372:461)(284:372:461))
-        (INTERCONNECT SLICE_68/F0 SLICE_70/C1 (875:1031:1188)(875:1031:1188))
-        (INTERCONNECT SLICE_56/F0 SLICE_40/B1 (1148:1306:1464)(1148:1306:1464))
-        (INTERCONNECT SLICE_56/F0 SLICE_43/C0 (1292:1469:1647)(1292:1469:1647))
-        (INTERCONNECT SLICE_56/F0 SLICE_50/A0 (1073:1231:1390)(1073:1231:1390))
-        (INTERCONNECT SLICE_56/F0 SLICE_104/C1 (1292:1469:1647)(1292:1469:1647))
-        (INTERCONNECT SLICE_56/F0 SLICE_104/C0 (1292:1469:1647)(1292:1469:1647))
-        (INTERCONNECT SLICE_109/F0 SLICE_40/A1 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_116/F0 SLICE_40/D0 (789:873:958)(789:873:958))
-        (INTERCONNECT SLICE_86/F1 SLICE_40/A0 (741:874:1008)(741:874:1008))
-        (INTERCONNECT SLICE_86/F1 SLICE_74/D1 (797:899:1002)(797:899:1002))
-        (INTERCONNECT SLICE_86/F1 SLICE_86/C0 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_86/F1 SLICE_90/B0 (513:611:710)(513:611:710))
-        (INTERCONNECT SLICE_86/F1 SLICE_105/C0 (542:665:788)(542:665:788))
-        (INTERCONNECT SLICE_40/F1 SLICE_40/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40/F0 SLICE_40/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_40/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI0in (1408:1550:1693)
-          (1408:1550:1693))
-        (INTERCONNECT SLICE_40/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI1in (1011:1111:1211)
-          (1011:1111:1211))
-        (INTERCONNECT SLICE_58/F1 SLICE_41/D1 (266:290:315)(266:290:315))
-        (INTERCONNECT SLICE_68/F1 SLICE_41/B1 (765:883:1001)(765:883:1001))
-        (INTERCONNECT SLICE_88/F0 SLICE_41/D0 (795:880:965)(795:880:965))
-        (INTERCONNECT SLICE_88/F0 SLICE_42/D1 (795:880:965)(795:880:965))
-        (INTERCONNECT SLICE_70/F1 SLICE_41/C0 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_70/F1 SLICE_42/C1 (536:650:764)(536:650:764))
-        (INTERCONNECT SLICE_70/F1 SLICE_42/B0 (767:894:1021)(767:894:1021))
-        (INTERCONNECT SLICE_41/F1 SLICE_41/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_41/F0 SLICE_41/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_41/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI2in (906:1001:1097)
-          (906:1001:1097))
-        (INTERCONNECT SLICE_41/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI3in (647:715:784)
-          (647:715:784))
-        (INTERCONNECT SLICE_74/F0 SLICE_42/D0 (526:579:632)(526:579:632))
-        (INTERCONNECT SLICE_74/F0 SLICE_84/C0 (534:645:756)(534:645:756))
-        (INTERCONNECT SLICE_104/F1 SLICE_42/C0 (534:639:744)(534:639:744))
-        (INTERCONNECT SLICE_114/F1 SLICE_42/A0 (1326:1511:1696)(1326:1511:1696))
-        (INTERCONNECT SLICE_42/F1 SLICE_42/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/F0 SLICE_42/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_42/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI4in (647:715:784)
-          (647:715:784))
-        (INTERCONNECT SLICE_42/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI5in (974:1077:1181)
-          (974:1077:1181))
-        (INTERCONNECT SLICE_50/F0 SLICE_43/D1 (789:873:958)(789:873:958))
-        (INTERCONNECT SLICE_105/F0 SLICE_43/C1 (534:639:744)(534:639:744))
-        (INTERCONNECT SLICE_109/F1 SLICE_43/B1 (765:883:1001)(765:883:1001))
-        (INTERCONNECT SLICE_108/F0 SLICE_43/A1 (999:1149:1299)(999:1149:1299))
-        (INTERCONNECT SLICE_84/F0 SLICE_43/D0 (789:873:958)(789:873:958))
-        (INTERCONNECT SLICE_43/F1 SLICE_43/DI1 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_43/Q0 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in (974:1077:1181)
-          (974:1077:1181))
-        (INTERCONNECT SLICE_43/Q1 
-          ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBDATI7in (1011:1111:1211)
-          (1011:1111:1211))
-        (INTERCONNECT SLICE_44/F1 SLICE_44/A0 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_103/F0 SLICE_44/CE (539:596:653)(539:596:653))
-        (INTERCONNECT SLICE_44/Q0 SLICE_52/A1 (733:848:964)(733:848:964))
-        (INTERCONNECT SLICE_45/F0 SLICE_45/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_47/F0 SLICE_45/LSR (1326:1469:1613)(1326:1469:1613))
-        (INTERCONNECT SLICE_47/F0 SLICE_47/C1 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_47/F0 SLICE_56/C1 (1731:1954:2178)(1731:1954:2178))
-        (INTERCONNECT SLICE_47/F0 SLICE_59/B1 (513:611:710)(513:611:710))
-        (INTERCONNECT SLICE_47/F0 SLICE_73/B0 (1962:2198:2435)(1962:2198:2435))
-        (INTERCONNECT SLICE_47/F0 SLICE_75/B0 (1216:1388:1560)(1216:1388:1560))
-        (INTERCONNECT SLICE_47/F0 SLICE_86/C1 (1361:1552:1744)(1361:1552:1744))
-        (INTERCONNECT SLICE_45/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBRSTIin 
-          (1611:1760:1909)(1611:1760:1909))
-        (INTERCONNECT SLICE_45/F1 SLICE_52/C0 (534:639:744)(534:639:744))
-        (INTERCONNECT SLICE_46/F1 SLICE_46/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_66/F1 SLICE_46/B0 (778:907:1036)(778:907:1036))
-        (INTERCONNECT SLICE_66/F1 SLICE_60/A1 (740:867:995)(740:867:995))
-        (INTERCONNECT SLICE_66/F1 SLICE_62/B1 (1729:1960:2191)(1729:1960:2191))
-        (INTERCONNECT SLICE_66/F1 SLICE_66/B0 (778:907:1036)(778:907:1036))
-        (INTERCONNECT SLICE_66/F1 SLICE_95/D1 (271:301:332)(271:301:332))
-        (INTERCONNECT SLICE_95/F0 SLICE_46/A0 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_46/F0 SLICE_46/DI0 (0:0:0)(0:0:0))
-        (INTERCONNECT SLICE_53/F0 SLICE_46/CE (876:972:1069)(876:972:1069))
-        (INTERCONNECT SLICE_46/Q0 ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin 
-          (1337:1468:1599)(1337:1468:1599))
-        (INTERCONNECT SLICE_96/F1 SLICE_47/D1 (794:884:975)(794:884:975))
-        (INTERCONNECT SLICE_96/F1 SLICE_69/A1 (738:859:981)(738:859:981))
-        (INTERCONNECT SLICE_96/F1 SLICE_96/C0 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_47/F1 DQMH_MGIOL/OPOS (1772:1946:2120)(1772:1946:2120))
-        (INTERCONNECT SLICE_76/F1 SLICE_48/D0 (864:965:1067)(864:965:1067))
-        (INTERCONNECT SLICE_76/F1 SLICE_63/A1 (737:864:992)(737:864:992))
-        (INTERCONNECT SLICE_76/F1 SLICE_76/D0 (527:589:651)(527:589:651))
-        (INTERCONNECT SLICE_76/F1 SLICE_112/C1 (541:655:769)(541:655:769))
-        (INTERCONNECT SLICE_48/F1 SLICE_48/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_48/F1 Vout\[7\]_MGIOL/CE (1189:1316:1444)(1189:1316:1444))
-        (INTERCONNECT SLICE_48/F1 Vout\[6\]_MGIOL/CE (1189:1316:1444)(1189:1316:1444))
-        (INTERCONNECT SLICE_48/F1 Vout\[5\]_MGIOL/CE (1569:1729:1890)(1569:1729:1890))
-        (INTERCONNECT SLICE_48/F1 Vout\[4\]_MGIOL/CE (1569:1729:1890)(1569:1729:1890))
-        (INTERCONNECT SLICE_48/F1 Vout\[3\]_MGIOL/CE (1189:1316:1444)(1189:1316:1444))
-        (INTERCONNECT SLICE_48/F1 Vout\[2\]_MGIOL/CE (1569:1729:1890)(1569:1729:1890))
-        (INTERCONNECT SLICE_48/F1 Vout\[1\]_MGIOL/CE (1189:1316:1444)(1189:1316:1444))
-        (INTERCONNECT SLICE_48/F1 Vout\[0\]_MGIOL/CE (1569:1729:1890)(1569:1729:1890))
-        (INTERCONNECT SLICE_80/F1 SLICE_48/B0 (1102:1265:1429)(1102:1265:1429))
-        (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (511:606:702)(511:606:702))
-        (INTERCONNECT SLICE_48/F0 SLICE_78/B0 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_93/F0 SLICE_49/D1 (523:573:623)(523:573:623))
-        (INTERCONNECT SLICE_49/F1 SLICE_49/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_49/F0 SLICE_81/D0 (266:290:315)(266:290:315))
-        (INTERCONNECT SLICE_50/F1 SLICE_50/D0 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_89/F1 SLICE_50/C0 (986:1144:1302)(986:1144:1302))
-        (INTERCONNECT SLICE_89/F1 SLICE_85/C1 (1313:1506:1699)(1313:1506:1699))
-        (INTERCONNECT SLICE_89/F1 SLICE_89/A0 (735:859:984)(735:859:984))
-        (INTERCONNECT SLICE_89/F1 SLICE_105/A1 (1083:1249:1415)(1083:1249:1415))
-        (INTERCONNECT SLICE_89/F1 SLICE_105/A0 (1083:1249:1415)(1083:1249:1415))
-        (INTERCONNECT SLICE_106/F0 SLICE_51/A1 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_51/F1 SLICE_51/B0 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_51/F0 CKE_MGIOL/OPOS (1891:2056:2222)(1891:2056:2222))
-        (INTERCONNECT SLICE_72/F0 SLICE_52/D1 (800:891:982)(800:891:982))
-        (INTERCONNECT SLICE_72/F0 SLICE_52/D0 (800:891:982)(800:891:982))
-        (INTERCONNECT SLICE_72/F0 SLICE_72/C1 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_72/F0 SLICE_76/C0 (546:664:783)(546:664:783))
-        (INTERCONNECT SLICE_52/F1 SLICE_52/B0 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_57/F1 SLICE_52/A0 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_53/F1 SLICE_53/C0 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_53/F1 SLICE_110/D0 (860:955:1051)(860:955:1051))
-        (INTERCONNECT SLICE_54/F1 SLICE_54/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_118/F0 SLICE_54/B0 (767:891:1015)(767:891:1015))
-        (INTERCONNECT SLICE_118/F0 SLICE_93/D1 (525:581:637)(525:581:637))
-        (INTERCONNECT SLICE_54/F0 SLICE_81/B0 (1099:1259:1420)(1099:1259:1420))
-        (INTERCONNECT SLICE_55/F0 SLICE_55/D1 (523:579:635)(523:579:635))
-        (INTERCONNECT SLICE_55/F0 SLICE_71/C1 (550:666:782)(550:666:782))
-        (INTERCONNECT SLICE_55/F0 SLICE_78/A1 (749:875:1002)(749:875:1002))
-        (INTERCONNECT SLICE_63/F0 SLICE_55/C1 (536:650:764)(536:650:764))
-        (INTERCONNECT SLICE_63/F0 SLICE_63/C1 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_63/F0 SLICE_76/A0 (735:859:984)(735:859:984))
-        (INTERCONNECT SLICE_55/F1 SLICE_83/D0 (523:573:623)(523:573:623))
-        (INTERCONNECT SLICE_56/F1 SLICE_56/B0 (513:611:710)(513:611:710))
-        (INTERCONNECT SLICE_56/F1 SLICE_85/B1 (772:902:1032)(772:902:1032))
-        (INTERCONNECT SLICE_56/F1 SLICE_88/C0 (1249:1437:1625)(1249:1437:1625))
-        (INTERCONNECT SLICE_56/F1 SLICE_92/D0 (525:584:643)(525:584:643))
-        (INTERCONNECT SLICE_56/F1 SLICE_109/B1 (1480:1681:1882)(1480:1681:1882))
-        (INTERCONNECT SLICE_56/F1 SLICE_109/B0 (1480:1681:1882)(1480:1681:1882))
-        (INTERCONNECT SLICE_58/F0 SLICE_58/C1 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_73/F0 SLICE_58/B1 (1166:1328:1491)(1166:1328:1491))
-        (INTERCONNECT SLICE_73/F0 SLICE_68/B1 (1161:1323:1485)(1161:1323:1485))
-        (INTERCONNECT SLICE_73/F0 SLICE_70/B1 (1166:1328:1491)(1166:1328:1491))
-        (INTERCONNECT SLICE_73/F0 SLICE_73/C1 (280:362:445)(280:362:445))
-        (INTERCONNECT SLICE_73/F0 SLICE_84/B1 (1166:1328:1491)(1166:1328:1491))
-        (INTERCONNECT SLICE_73/F0 SLICE_89/D0 (1610:1770:1931)(1610:1770:1931))
-        (INTERCONNECT SLICE_73/F0 SLICE_114/B1 (1118:1283:1448)(1118:1283:1448))
-        (INTERCONNECT SLICE_73/F0 SLICE_114/D0 (549:611:673)(549:611:673))
-        (INTERCONNECT SLICE_70/F0 SLICE_58/A1 (733:854:976)(733:854:976))
-        (INTERCONNECT SLICE_70/F0 SLICE_70/A1 (479:572:665)(479:572:665))
-        (INTERCONNECT SLICE_59/F0 SLICE_59/A1 (476:566:656)(476:566:656))
-        (INTERCONNECT SLICE_59/F1 DQML_MGIOL/OPOS (1772:1946:2120)(1772:1946:2120))
-        (INTERCONNECT SLICE_60/F0 SLICE_60/D1 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_88/F1 SLICE_60/C1 (807:955:1104)(807:955:1104))
-        (INTERCONNECT SLICE_88/F1 SLICE_88/A0 (737:864:992)(737:864:992))
-        (INTERCONNECT SLICE_88/F1 SLICE_105/D1 (273:306:340)(273:306:340))
-        (INTERCONNECT SLICE_88/F1 SLICE_105/D0 (527:589:651)(527:589:651))
-        (INTERCONNECT SLICE_64/F1 SLICE_60/B1 (515:616:718)(515:616:718))
-        (INTERCONNECT SLICE_64/F1 SLICE_64/D0 (527:589:651)(527:589:651))
-        (INTERCONNECT SLICE_64/F1 SLICE_95/C1 (538:655:772)(538:655:772))
-        (INTERCONNECT SLICE_64/F1 SLICE_97/C0 (548:669:791)(548:669:791))
-        (INTERCONNECT SLICE_61/F0 SLICE_61/C1 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_61/F0 SLICE_88/B0 (1211:1381:1552)(1211:1381:1552))
-        (INTERCONNECT SLICE_61/F0 SLICE_114/C1 (536:650:764)(536:650:764))
-        (INTERCONNECT SLICE_61/F1 SLICE_109/A0 (1067:1225:1383)(1067:1225:1383))
-        (INTERCONNECT SLICE_62/F0 SLICE_62/D1 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_64/F0 SLICE_114/B0 (1031:1183:1336)(1031:1183:1336))
-        (INTERCONNECT SLICE_65/F1 SLICE_65/B0 (765:889:1013)(765:889:1013))
-        (INTERCONNECT SLICE_65/F1 SLICE_84/A1 (733:854:976)(733:854:976))
-        (INTERCONNECT SLICE_65/F0 SLICE_109/A1 (740:863:986)(740:863:986))
-        (INTERCONNECT SLICE_66/F0 SLICE_95/D0 (266:290:315)(266:290:315))
-        (INTERCONNECT SLICE_76/F0 SLICE_69/D1 (975:1072:1170)(975:1072:1170))
-        (INTERCONNECT SLICE_76/F0 SLICE_78/A0 (1185:1348:1511)(1185:1348:1511))
-        (INTERCONNECT SLICE_76/F0 SLICE_115/C0 (1350:1534:1718)(1350:1534:1718))
-        (INTERCONNECT SLICE_69/F0 SLICE_69/C1 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_69/F1 RA\[10\]_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
-        (INTERCONNECT SLICE_75/F0 SLICE_71/A1 (746:869:993)(746:869:993))
-        (INTERCONNECT SLICE_75/F0 SLICE_78/C0 (547:660:773)(547:660:773))
-        (INTERCONNECT SLICE_71/F1 SLICE_115/D0 (523:573:623)(523:573:623))
-        (INTERCONNECT SLICE_119/F0 SLICE_72/B1 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_116/F1 SLICE_73/D1 (523:579:635)(523:579:635))
-        (INTERCONNECT SLICE_116/F1 SLICE_92/B1 (765:889:1013)(765:889:1013))
-        (INTERCONNECT SLICE_73/F1 SLICE_85/C0 (534:639:744)(534:639:744))
-        (INTERCONNECT SLICE_75/F1 SLICE_75/C0 (282:367:453)(282:367:453))
-        (INTERCONNECT SLICE_75/F1 SLICE_76/B0 (513:611:710)(513:611:710))
-        (INTERCONNECT SLICE_75/F1 SLICE_83/A0 (745:874:1003)(745:874:1003))
-        (INTERCONNECT SLICE_82/F0 SLICE_77/D0 (530:587:645)(530:587:645))
-        (INTERCONNECT SLICE_81/F0 SLICE_77/C0 (531:639:747)(531:639:747))
-        (INTERCONNECT SLICE_94/F0 SLICE_77/A0 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_78/F1 SLICE_78/D0 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_78/F0 nCAS_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
-        (INTERCONNECT SLICE_79/F1 SLICE_79/B0 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_83/F0 SLICE_79/A0 (1180:1342:1505)(1180:1342:1505))
-        (INTERCONNECT SLICE_83/F0 SLICE_80/A0 (1180:1342:1505)(1180:1342:1505))
-        (INTERCONNECT SLICE_79/F0 nCS_MGIOL/OPOS (1408:1550:1693)(1408:1550:1693))
-        (INTERCONNECT SLICE_80/F0 nRAS_MGIOL/OPOS (1772:1946:2120)(1772:1946:2120))
-        (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_91/F0 SLICE_82/C0 (534:639:744)(534:639:744))
-        (INTERCONNECT SLICE_87/F0 SLICE_82/B0 (765:883:1001)(765:883:1001))
-        (INTERCONNECT SLICE_83/F1 SLICE_83/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_112/F1 SLICE_83/B0 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_84/F1 SLICE_84/A0 (730:848:967)(730:848:967))
-        (INTERCONNECT SLICE_108/F1 SLICE_85/D1 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_89/F0 SLICE_85/D0 (520:573:626)(520:573:626))
-        (INTERCONNECT SLICE_85/F1 SLICE_85/B0 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_92/F0 SLICE_85/A0 (740:863:986)(740:863:986))
-        (INTERCONNECT SLICE_105/F1 SLICE_86/A0 (733:848:964)(733:848:964))
-        (INTERCONNECT SLICE_98/F0 SLICE_87/C1 (541:653:766)(541:653:766))
-        (INTERCONNECT SLICE_87/F1 SLICE_87/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_90/F1 SLICE_90/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_99/F0 SLICE_91/A1 (1067:1225:1383)(1067:1225:1383))
-        (INTERCONNECT SLICE_91/F1 SLICE_91/B0 (762:883:1004)(762:883:1004))
-        (INTERCONNECT SLICE_92/F1 SLICE_92/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_93/F1 SLICE_93/B0 (508:600:693)(508:600:693))
-        (INTERCONNECT SLICE_94/F1 SLICE_94/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_95/F1 SLICE_95/C0 (277:356:436)(277:356:436))
-        (INTERCONNECT SLICE_96/F0 RA\[8\]_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
-        (INTERCONNECT SLICE_97/F1 SLICE_97/B0 (511:606:702)(511:606:702))
-        (INTERCONNECT SLICE_97/F1 SLICE_116/C0 (803:945:1088)(803:945:1088))
-        (INTERCONNECT SLICE_118/F1 SLICE_98/D0 (269:296:324)(269:296:324))
-        (INTERCONNECT SLICE_118/F1 SLICE_99/D0 (269:296:324)(269:296:324))
-        (INTERCONNECT SLICE_101/F1 BA\[1\]_MGIOL/LSR (1884:2059:2234)(1884:2059:2234))
-        (INTERCONNECT SLICE_101/F1 BA\[0\]_MGIOL/LSR (1884:2059:2234)(1884:2059:2234))
-        (INTERCONNECT SLICE_102/F0 BA\[0\]_MGIOL/OPOS (1854:2023:2192)(1854:2023:2192))
-        (INTERCONNECT SLICE_103/F1 RA\[11\]_MGIOL/OPOS (1891:2056:2222)(1891:2056:2222))
-        (INTERCONNECT SLICE_107/F0 BA\[1\]_MGIOL/OPOS (1772:1946:2120)(1772:1946:2120))
-        (INTERCONNECT SLICE_110/F1 RA\[9\]_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
-        (INTERCONNECT Ain\[5\]_I/PADDI SLICE_111/A1 (2376:2598:2820)(2376:2598:2820))
-        (INTERCONNECT Ain\[4\]_I/PADDI SLICE_111/A0 (1904:2092:2281)(1904:2092:2281))
-        (INTERCONNECT SLICE_111/F0 RA\[4\]_MGIOL/OPOS (1011:1111:1211)(1011:1111:1211))
-        (INTERCONNECT SLICE_111/F1 RA\[5\]_MGIOL/OPOS (1081:1188:1296)(1081:1188:1296))
-        (INTERCONNECT Ain\[6\]_I/PADDI SLICE_112/C0 (1530:1696:1862)(1530:1696:1862))
-        (INTERCONNECT SLICE_112/F0 RA\[6\]_MGIOL/OPOS (1408:1550:1693)(1408:1550:1693))
-        (INTERCONNECT Ain\[2\]_I/PADDI SLICE_113/B1 (2262:2486:2711)(2262:2486:2711))
-        (INTERCONNECT Ain\[7\]_I/PADDI SLICE_113/B0 (2262:2486:2711)(2262:2486:2711))
-        (INTERCONNECT SLICE_113/F0 RA\[7\]_MGIOL/OPOS (1337:1468:1599)(1337:1468:1599))
-        (INTERCONNECT SLICE_113/F1 RA\[2\]_MGIOL/OPOS (1483:1616:1750)(1483:1616:1750))
-        (INTERCONNECT nWE80_I/PADDI SLICE_115/A1 (2242:2467:2693)(2242:2467:2693))
-        (INTERCONNECT nWE80_I/PADDI SLICE_115/A0 (2242:2467:2693)(2242:2467:2693))
-        (INTERCONNECT SLICE_115/F0 nRWE_MGIOL/OPOS (1854:2023:2192)(1854:2023:2192))
-        (INTERCONNECT SLICE_115/F1 RD\[0\]_I/PADDT (1279:1424:1569)(1279:1424:1569))
-        (INTERCONNECT SLICE_115/F1 RD\[7\]_I/PADDT (1057:1170:1284)(1057:1170:1284))
-        (INTERCONNECT SLICE_115/F1 RD\[6\]_I/PADDT (1057:1170:1284)(1057:1170:1284))
-        (INTERCONNECT SLICE_115/F1 RD\[5\]_I/PADDT (1759:1941:2123)(1759:1941:2123))
-        (INTERCONNECT SLICE_115/F1 RD\[4\]_I/PADDT (1759:1941:2123)(1759:1941:2123))
-        (INTERCONNECT SLICE_115/F1 RD\[3\]_I/PADDT (688:769:851)(688:769:851))
-        (INTERCONNECT SLICE_115/F1 RD\[2\]_I/PADDT (688:769:851)(688:769:851))
-        (INTERCONNECT SLICE_115/F1 RD\[1\]_I/PADDT (1279:1424:1569)(1279:1424:1569))
-        (INTERCONNECT SLICE_117/F0 LED_I/PADDO (936:1038:1140)(936:1038:1140))
+        (INTERCONNECT SLICE_38/Q0 nRWEout_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795))
+        (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_39/A1 (747:879:1011)
+          (747:879:1011))
+        (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_87/A1 (740:864:989)
+          (740:864:989))
+        (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_94/B0 (515:616:718)
+          (515:616:718))
+        (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_116/D1 (1160:1285:1410)
+          (1160:1285:1410))
+        (INTERCONNECT ram2e_ufm\/SLICE_39/F1 ram2e_ufm\/SLICE_39/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_39/F0 ram2e_ufm\/SLICE_39/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_39/Q0 ram2e_ufm\/SLICE_80/B0 (1395:1579:1763)
+          (1395:1579:1763))
+        (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_40/B0 (783:909:1036)
+          (783:909:1036))
+        (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_62/B1 (783:909:1036)
+          (783:909:1036))
+        (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_83/B1 (783:909:1036)
+          (783:909:1036))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/F0 ram2e_ufm\/SLICE_40/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_51/A0 (1008:1160:1313)
+          (1008:1160:1313))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_66/D0 (798:885:972)
+          (798:885:972))
+        (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_130/B0 (1209:1375:1542)
+          (1209:1375:1542))
+        (INTERCONNECT ram2e_ufm\/SLICE_41/F1 ram2e_ufm\/SLICE_41/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_41/A0 (1109:1269:1430)
+          (1109:1269:1430))
+        (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_87/D1 (528:584:640)
+          (528:584:640))
+        (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_101/D0 (525:584:643)
+          (525:584:643))
+        (INTERCONNECT ram2e_ufm\/SLICE_41/F0 ram2e_ufm\/SLICE_41/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_41/Q0 ram2e_ufm\/SLICE_147/A1 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO0 ram2e_ufm\/SLICE_42/C0 
+          (1531:1730:1930)(1531:1730:1930))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO0 ram2e_ufm\/SLICE_43/C0 
+          (1895:2126:2357)(1895:2126:2357))
+        (INTERCONNECT ram2e_ufm\/SLICE_42/F0 ram2e_ufm\/SLICE_42/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F1 ram2e_ufm\/SLICE_42/CE (539:596:653)
+          (539:596:653))
+        (INTERCONNECT ram2e_ufm\/SLICE_42/Q0 ram2e_ufm\/SLICE_137/D0 (969:1067:1165)
+          (969:1067:1165))
+        (INTERCONNECT ram2e_ufm\/SLICE_42/Q0 ram2e_ufm\/SLICE_147/C1 (1344:1528:1713)
+          (1344:1528:1713))
+        (INTERCONNECT ram2e_ufm\/SLICE_42/F1 ram2e_ufm\/SLICE_84/C1 (547:660:773)
+          (547:660:773))
+        (INTERCONNECT ram2e_ufm\/SLICE_42/F1 ram2e_ufm\/SLICE_87/C1 (874:1022:1170)
+          (874:1022:1170))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO1 ram2e_ufm\/SLICE_43/D1 
+          (1495:1644:1793)(1495:1644:1793))
+        (INTERCONNECT ram2e_ufm\/SLICE_43/F1 ram2e_ufm\/SLICE_43/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_43/F0 ram2e_ufm\/SLICE_43/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_43/CE (1157:1283:1410)
+          (1157:1283:1410))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_43/CE (1157:1283:1410)
+          (1157:1283:1410))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_44/CE (1510:1666:1822)
+          (1510:1666:1822))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_44/CE (1510:1666:1822)
+          (1510:1666:1822))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_45/CE (1510:1666:1822)
+          (1510:1666:1822))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_45/CE (1510:1666:1822)
+          (1510:1666:1822))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_46/CE (1157:1283:1410)
+          (1157:1283:1410))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_46/CE (1157:1283:1410)
+          (1157:1283:1410))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO3 ram2e_ufm\/SLICE_44/D1 
+          (1596:1735:1874)(1596:1735:1874))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO2 ram2e_ufm\/SLICE_44/C0 
+          (1607:1801:1995)(1607:1801:1995))
+        (INTERCONNECT ram2e_ufm\/SLICE_44/F1 ram2e_ufm\/SLICE_44/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_44/F0 ram2e_ufm\/SLICE_44/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO5 ram2e_ufm\/SLICE_45/D1 
+          (1514:1658:1802)(1514:1658:1802))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO4 ram2e_ufm\/SLICE_45/D0 
+          (1596:1735:1874)(1596:1735:1874))
+        (INTERCONNECT ram2e_ufm\/SLICE_45/F1 ram2e_ufm\/SLICE_45/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_45/F0 ram2e_ufm\/SLICE_45/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO7 ram2e_ufm\/SLICE_46/D1 
+          (1514:1658:1802)(1514:1658:1802))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO6 ram2e_ufm\/SLICE_46/D0 
+          (1495:1644:1793)(1495:1644:1793))
+        (INTERCONNECT ram2e_ufm\/SLICE_46/F1 ram2e_ufm\/SLICE_46/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_46/F0 ram2e_ufm\/SLICE_46/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_103/F0 ram2e_ufm\/SLICE_47/D1 (530:587:645)
+          (530:587:645))
+        (INTERCONNECT ram2e_ufm\/SLICE_114/F0 ram2e_ufm\/SLICE_47/B1 (508:600:693)
+          (508:600:693))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_47/C0 (824:968:1113)
+          (824:968:1113))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_52/A1 (1393:1580:1767)
+          (1393:1580:1767))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_55/A0 (1387:1573:1760)
+          (1387:1573:1760))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_64/A1 (1023:1178:1333)
+          (1023:1178:1333))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_85/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_88/A0 (1350:1540:1730)
+          (1350:1540:1730))
+        (INTERCONNECT ram2e_ufm\/SLICE_85/F1 ram2e_ufm\/SLICE_125/A0 (1757:1975:2194)
+          (1757:1975:2194))
+        (INTERCONNECT ram2e_ufm\/SLICE_86/F0 ram2e_ufm\/SLICE_47/B0 (1206:1370:1535)
+          (1206:1370:1535))
+        (INTERCONNECT ram2e_ufm\/SLICE_64/F0 ram2e_ufm\/SLICE_47/A0 (476:566:656)
+          (476:566:656))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/F1 ram2e_ufm\/SLICE_47/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/F0 ram2e_ufm\/SLICE_47/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_47/CE (1440:1568:1696)
+          (1440:1568:1696))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_47/CE (1440:1568:1696)
+          (1440:1568:1696))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_48/CE (1440:1568:1696)
+          (1440:1568:1696))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_48/CE (1440:1568:1696)
+          (1440:1568:1696))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_49/CE (2190:2383:2576)
+          (2190:2383:2576))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_49/CE (2190:2383:2576)
+          (2190:2383:2576))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_50/CE (2554:2778:3003)
+          (2554:2778:3003))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_50/CE (2554:2778:3003)
+          (2554:2778:3003))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_52/CE (1810:1970:2130)
+          (1810:1970:2130))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_52/CE (1810:1970:2130)
+          (1810:1970:2130))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_53/CE (2560:2785:3010)
+          (2560:2785:3010))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_53/CE (2560:2785:3010)
+          (2560:2785:3010))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_54/CE (2560:2785:3010)
+          (2560:2785:3010))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_54/CE (2560:2785:3010)
+          (2560:2785:3010))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_55/CE (2190:2383:2576)
+          (2190:2383:2576))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_55/CE (2190:2383:2576)
+          (2190:2383:2576))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/Q0 ram2e_ufm\/SLICE_52/B0 (1364:1552:1740)
+          (1364:1552:1740))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in 
+          (1967:2161:2355)(1967:2161:2355))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/Q1 ram2e_ufm\/SLICE_97/D0 (1225:1346:1468)
+          (1225:1346:1468))
+        (INTERCONNECT ram2e_ufm\/SLICE_47/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in 
+          (1669:1836:2004)(1669:1836:2004))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/F1 ram2e_ufm\/SLICE_48/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/F0 ram2e_ufm\/SLICE_48/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/Q0 ram2e_ufm\/SLICE_53/B0 (1037:1190:1343)
+          (1037:1190:1343))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI2in 
+          (1640:1799:1958)(1640:1799:1958))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/Q1 ram2e_ufm\/SLICE_89/B0 (1105:1266:1427)
+          (1105:1266:1427))
+        (INTERCONNECT ram2e_ufm\/SLICE_48/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI3in 
+          (1708:1875:2042)(1708:1875:2042))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/F1 ram2e_ufm\/SLICE_49/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/F0 ram2e_ufm\/SLICE_49/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/Q0 ram2e_ufm\/SLICE_145/C1 (536:647:758)
+          (536:647:758))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI4in 
+          (1272:1405:1538)(1272:1405:1538))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/Q1 ram2e_ufm\/SLICE_54/B1 (1468:1656:1845)
+          (1468:1656:1845))
+        (INTERCONNECT ram2e_ufm\/SLICE_49/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI5in 
+          (2071:2265:2460)(2071:2265:2460))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/F1 ram2e_ufm\/SLICE_50/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/F0 ram2e_ufm\/SLICE_50/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/Q0 ram2e_ufm\/SLICE_90/D0 (1159:1275:1392)
+          (1159:1275:1392))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI6in 
+          (2004:2194:2385)(2004:2194:2385))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/Q1 ram2e_ufm\/SLICE_98/D0 (863:956:1049)
+          (863:956:1049))
+        (INTERCONNECT ram2e_ufm\/SLICE_50/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI7in 
+          (1759:1938:2118)(1759:1938:2118))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBACKO ram2e_ufm\/SLICE_51/C1 
+          (1628:1825:2022)(1628:1825:2022))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBACKO ram2e_ufm\/SLICE_66/D1 
+          (1944:2121:2298)(1944:2121:2298))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBACKO ram2e_ufm\/SLICE_66/C0 
+          (1628:1825:2022)(1628:1825:2022))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBACKO ram2e_ufm\/SLICE_75/C0 
+          (1992:2220:2449)(1992:2220:2449))
+        (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBACKO ram2e_ufm\/SLICE_110/D0 
+          (1601:1741:1882)(1601:1741:1882))
+        (INTERCONNECT ram2e_ufm\/SLICE_108/F1 ram2e_ufm\/SLICE_51/A1 (736:854:973)
+          (736:854:973))
+        (INTERCONNECT ram2e_ufm\/SLICE_108/F1 ram2e_ufm\/SLICE_108/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_51/F1 ram2e_ufm\/SLICE_51/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_51/F0 ram2e_ufm\/SLICE_51/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_66/F0 ram2e_ufm\/SLICE_51/CE (539:596:653)
+          (539:596:653))
+        (INTERCONNECT ram2e_ufm\/SLICE_51/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBCYCIin 
+          (1451:1590:1730)(1451:1590:1730))
+        (INTERCONNECT ram2e_ufm\/SLICE_51/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBSTBIin 
+          (1797:1975:2154)(1797:1975:2154))
+        (INTERCONNECT ram2e_ufm\/SLICE_123/F0 ram2e_ufm\/SLICE_52/D1 (862:960:1059)
+          (862:960:1059))
+        (INTERCONNECT ram2e_ufm\/SLICE_123/F0 ram2e_ufm\/SLICE_53/A1 (1331:1522:1713)
+          (1331:1522:1713))
+        (INTERCONNECT ram2e_ufm\/SLICE_123/F0 ram2e_ufm\/SLICE_55/B0 (770:894:1018)
+          (770:894:1018))
+        (INTERCONNECT ram2e_ufm\/SLICE_97/F0 ram2e_ufm\/SLICE_52/C1 (531:639:747)
+          (531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_111/F1 ram2e_ufm\/SLICE_52/B1 (1509:1701:1893)
+          (1509:1701:1893))
+        (INTERCONNECT ram2e_ufm\/SLICE_111/F1 ram2e_ufm\/SLICE_53/D1 (533:593:654)
+          (533:593:654))
+        (INTERCONNECT ram2e_ufm\/SLICE_111/F1 ram2e_ufm\/SLICE_73/A1 (1804:2028:2253)
+          (1804:2028:2253))
+        (INTERCONNECT ram2e_ufm\/SLICE_128/F1 ram2e_ufm\/SLICE_52/D0 (266:290:315)
+          (266:290:315))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F1 ram2e_ufm\/SLICE_52/C0 (912:1065:1218)
+          (912:1065:1218))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F1 ram2e_ufm\/SLICE_64/C0 (548:669:791)
+          (548:669:791))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F1 ram2e_ufm\/SLICE_81/B0 (515:616:718)
+          (515:616:718))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F1 ram2e_ufm\/SLICE_131/C0 (548:669:791)
+          (548:669:791))
+        (INTERCONNECT ram2e_ufm\/SLICE_52/F1 ram2e_ufm\/SLICE_52/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_52/F0 ram2e_ufm\/SLICE_52/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_52/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI0in 
+          (906:1001:1097)(906:1001:1097))
+        (INTERCONNECT ram2e_ufm\/SLICE_52/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI1in 
+          (1081:1188:1296)(1081:1188:1296))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F0 ram2e_ufm\/SLICE_53/C1 (905:1049:1193)
+          (905:1049:1193))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_53/B1 (1052:1212:1372)
+          (1052:1212:1372))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_68/B1 (777:908:1040)
+          (777:908:1040))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_89/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_90/C0 (1185:1363:1542)
+          (1185:1363:1542))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_93/C0 (821:968:1115)
+          (821:968:1115))
+        (INTERCONNECT ram2e_ufm\/SLICE_89/F1 ram2e_ufm\/SLICE_145/B1 (1379:1574:1769)
+          (1379:1574:1769))
+        (INTERCONNECT ram2e_ufm\/SLICE_93/F0 ram2e_ufm\/SLICE_53/D0 (269:296:324)
+          (269:296:324))
+        (INTERCONNECT ram2e_ufm\/SLICE_93/F0 ram2e_ufm\/SLICE_54/D1 (534:592:650)
+          (534:592:650))
+        (INTERCONNECT ram2e_ufm\/SLICE_93/F0 ram2e_ufm\/SLICE_54/D0 (534:592:650)
+          (534:592:650))
+        (INTERCONNECT ram2e_ufm\/SLICE_73/F1 ram2e_ufm\/SLICE_53/C0 (536:647:758)
+          (536:647:758))
+        (INTERCONNECT ram2e_ufm\/SLICE_73/F1 ram2e_ufm\/SLICE_54/C1 (536:647:758)
+          (536:647:758))
+        (INTERCONNECT ram2e_ufm\/SLICE_53/F1 ram2e_ufm\/SLICE_53/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_53/F0 ram2e_ufm\/SLICE_53/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_53/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI2in 
+          (1081:1188:1296)(1081:1188:1296))
+        (INTERCONNECT ram2e_ufm\/SLICE_53/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI3in 
+          (906:1001:1097)(906:1001:1097))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F0 ram2e_ufm\/SLICE_54/C0 (547:660:773)
+          (547:660:773))
+        (INTERCONNECT ram2e_ufm\/SLICE_81/F0 ram2e_ufm\/SLICE_55/C0 (547:660:773)
+          (547:660:773))
+        (INTERCONNECT ram2e_ufm\/SLICE_125/F0 ram2e_ufm\/SLICE_54/B0 (1031:1183:1336)
+          (1031:1183:1336))
+        (INTERCONNECT ram2e_ufm\/SLICE_145/F1 ram2e_ufm\/SLICE_54/A0 (476:566:656)
+          (476:566:656))
+        (INTERCONNECT ram2e_ufm\/SLICE_54/F1 ram2e_ufm\/SLICE_54/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_54/F0 ram2e_ufm\/SLICE_54/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_54/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI4in 
+          (1081:1188:1296)(1081:1188:1296))
+        (INTERCONNECT ram2e_ufm\/SLICE_54/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI5in 
+          (906:1001:1097)(906:1001:1097))
+        (INTERCONNECT ram2e_ufm\/SLICE_70/F0 ram2e_ufm\/SLICE_55/D1 (530:587:645)
+          (530:587:645))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F0 ram2e_ufm\/SLICE_55/C1 (531:639:747)
+          (531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_131/F0 ram2e_ufm\/SLICE_55/B1 (1358:1545:1733)
+          (1358:1545:1733))
+        (INTERCONNECT ram2e_ufm\/SLICE_88/F0 ram2e_ufm\/SLICE_55/A1 (733:848:964)
+          (733:848:964))
+        (INTERCONNECT ram2e_ufm\/SLICE_90/F0 ram2e_ufm\/SLICE_55/D0 (520:573:626)
+          (520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_55/F1 ram2e_ufm\/SLICE_55/DI1 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_55/F0 ram2e_ufm\/SLICE_55/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_55/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in 
+          (1233:1363:1494)(1233:1363:1494))
+        (INTERCONNECT ram2e_ufm\/SLICE_55/Q1 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI7in 
+          (906:1001:1097)(906:1001:1097))
+        (INTERCONNECT ram2e_ufm\/SLICE_56/F1 ram2e_ufm\/SLICE_56/C0 (531:639:747)
+          (531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_56/F0 ram2e_ufm\/SLICE_56/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_56/Q0 ram2e_ufm\/SLICE_108/D0 (1116:1235:1355)
+          (1116:1235:1355))
+        (INTERCONNECT ram2e_ufm\/SLICE_57/F0 ram2e_ufm\/SLICE_57/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_69/F0 ram2e_ufm\/SLICE_57/LSR (881:983:1086)
+          (881:983:1086))
+        (INTERCONNECT ram2e_ufm\/SLICE_69/F0 ram2e_ufm\/SLICE_69/A1 (481:577:673)
+          (481:577:673))
+        (INTERCONNECT ram2e_ufm\/SLICE_69/F0 ram2e_ufm\/SLICE_105/D0 (271:301:332)
+          (271:301:332))
+        (INTERCONNECT ram2e_ufm\/SLICE_57/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBRSTIin 
+          (1938:2122:2306)(1938:2122:2306))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F0 ram2e_ufm\/SLICE_58/D1 (266:290:315)
+          (266:290:315))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_58/A1 (1074:1241:1408)
+          (1074:1241:1408))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_58/A0 (483:582:681)
+          (483:582:681))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_103/B0 (774:907:1040)
+          (774:907:1040))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_109/B0 (769:899:1029)
+          (769:899:1029))
+        (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_114/C0 (809:963:1118)
+          (809:963:1118))
+        (INTERCONNECT ram2e_ufm\/SLICE_126/F1 ram2e_ufm\/SLICE_58/C0 (534:639:744)
+          (534:639:744))
+        (INTERCONNECT ram2e_ufm\/SLICE_58/F1 ram2e_ufm\/SLICE_58/B0 (508:600:693)
+          (508:600:693))
+        (INTERCONNECT ram2e_ufm\/SLICE_58/F0 ram2e_ufm\/SLICE_58/DI0 (0:0:0)(0:0:0))
+        (INTERCONNECT ram2e_ufm\/SLICE_130/F0 ram2e_ufm\/SLICE_58/CE (1240:1368:1496)
+          (1240:1368:1496))
+        (INTERCONNECT ram2e_ufm\/SLICE_58/Q0 
+          ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin 
+          (1527:1661:1795)(1527:1661:1795))
+        (INTERCONNECT ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/OFX0 ram2e_ufm\/SLICE_133/C0 
+          (800:939:1079)(800:939:1079))
+        (INTERCONNECT ram2e_ufm\/SLICE_94/F0 
+          ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/A1 (1067:1225:1383)(1067:1225:1383))
+        (INTERCONNECT ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/OFX0 
+          ram2e_ufm\/SLICE_82/A0 (1067:1225:1383)(1067:1225:1383))
+        (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/CKE_7\/SLICE_61/D1 (271:301:332)
+          (271:301:332))
+        (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/SLICE_91/A1 (738:859:981)
+          (738:859:981))
+        (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/SLICE_102/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_102/F0 ram2e_ufm\/CKE_7\/SLICE_61/M0 (485:526:568)
+          (485:526:568))
+        (INTERCONNECT ram2e_ufm\/SLICE_62/F0 ram2e_ufm\/SLICE_84/D0 (1220:1340:1460)
+          (1220:1340:1460))
+        (INTERCONNECT ram2e_ufm\/SLICE_65/F0 ram2e_ufm\/SLICE_63/C1 (534:639:744)
+          (534:639:744))
+        (INTERCONNECT ram2e_ufm\/SLICE_133/F0 ram2e_ufm\/SLICE_63/A1 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_63/D0 (546:610:675)
+          (546:610:675))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_66/B0 (770:894:1018)
+          (770:894:1018))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_79/C1 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_84/A0 (756:886:1016)
+          (756:886:1016))
+        (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_85/D0 (873:972:1072)
+          (873:972:1072))
+        (INTERCONNECT ram2e_ufm\/SLICE_84/F0 ram2e_ufm\/SLICE_63/C0 (531:639:747)
+          (531:639:747))
+        (INTERCONNECT ram2e_ufm\/SLICE_63/F1 ram2e_ufm\/SLICE_63/B0 (508:600:693)
+          (508:600:693))
+        (INTERCONNECT ram2e_ufm\/SLICE_64/F1 ram2e_ufm\/SLICE_64/B0 (508:600:693)
+          (508:600:693))
+        (INTERCONNECT ram2e_ufm\/SLICE_65/F1 ram2e_ufm\/SLICE_65/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_100/F0 ram2e_ufm\/SLICE_65/A0 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_66/C1 (991:1149:1308)
+          (991:1149:1308))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_70/D1 (1350:1485:1621)
+          (1350:1485:1621))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_80/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_81/C1 (1736:1959:2182)
+          (1736:1959:2182))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_85/A1 (1554:1754:1955)
+          (1554:1754:1955))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_89/B1 (2331:2598:2866)
+          (2331:2598:2866))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_98/C1 (1736:1959:2182)
+          (1736:1959:2182))
+        (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_130/D0 (528:584:640)
+          (528:584:640))
+        (INTERCONNECT ram2e_ufm\/SLICE_108/F0 ram2e_ufm\/SLICE_66/A1 (1067:1225:1383)
+          (1067:1225:1383))
+        (INTERCONNECT ram2e_ufm\/SLICE_66/F1 ram2e_ufm\/SLICE_66/A0 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_67/F1 ram2e_ufm\/SLICE_67/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_67/F0 ram2e_ufm\/SLICE_91/D0 (530:587:645)
+          (530:587:645))
+        (INTERCONNECT ram2e_ufm\/SLICE_68/F0 ram2e_ufm\/SLICE_68/A1 (1430:1615:1801)
+          (1430:1615:1801))
+        (INTERCONNECT ram2e_ufm\/SLICE_68/F1 ram2e_ufm\/SLICE_86/A0 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_122/F0 ram2e_ufm\/SLICE_69/B1 (762:883:1004)
+          (762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_70/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_79/A1 (745:874:1003)
+          (745:874:1003))
+        (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_111/A1 (738:859:981)
+          (738:859:981))
+        (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_70/A0 (735:859:984)
+          (735:859:984))
+        (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_75/B0 (513:611:710)
+          (513:611:710))
+        (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_88/D0 (528:584:640)
+          (528:584:640))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_71/C1 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_91/C0 (811:957:1103)
+          (811:957:1103))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_124/B1 (1744:1971:2199)
+          (1744:1971:2199))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_124/B0 (1744:1971:2199)
+          (1744:1971:2199))
+        (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_146/B1 (777:908:1040)
+          (777:908:1040))
+        (INTERCONNECT ram2e_ufm\/SLICE_72/F0 ram2e_ufm\/SLICE_72/C1 (534:645:756)
+          (534:645:756))
+        (INTERCONNECT ram2e_ufm\/SLICE_72/F0 ram2e_ufm\/SLICE_129/C1 (537:645:753)
+          (537:645:753))
+        (INTERCONNECT ram2e_ufm\/SLICE_72/F1 BA\[0\]_MGIOL/OPOS (1337:1468:1599)
+          (1337:1468:1599))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_73/D1 (808:897:986)
+          (808:897:986))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_97/C0 (819:963:1107)
+          (819:963:1107))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_98/B0 (511:606:702)
+          (511:606:702))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_99/C0 (819:963:1107)
+          (819:963:1107))
+        (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_126/D0 (1172:1292:1413)
+          (1172:1292:1413))
+        (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_73/C1 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_97/C1 (536:650:764)
+          (536:650:764))
+        (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_145/D1 (528:584:640)
+          (528:584:640))
+        (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_73/B1 (770:894:1018)
+          (770:894:1018))
+        (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_103/C0 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_109/C0 (546:664:783)
+          (546:664:783))
+        (INTERCONNECT ram2e_ufm\/SLICE_135/F0 ram2e_ufm\/SLICE_74/A1 (740:863:986)
+          (740:863:986))
+        (INTERCONNECT ram2e_ufm\/SLICE_75/F0 ram2e_ufm\/SLICE_79/B1 (772:897:1023)
+          (772:897:1023))
+        (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_76/C0 (284:372:461)
+          (284:372:461))
+        (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_81/A0 (737:864:992)
+          (737:864:992))
+        (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_111/A0 (483:582:681)
+          (483:582:681))
+        (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_131/B0 (1038:1199:1361)
+          (1038:1199:1361))
+        (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_76/B0 (1116:1279:1442)
+          (1116:1279:1442))
+        (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_88/B0 (1116:1279:1442)
+          (1116:1279:1442))
+        (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_90/C1 (874:1022:1170)
+          (874:1022:1170))
+        (INTERCONNECT ram2e_ufm\/SLICE_76/F0 ram2e_ufm\/SLICE_98/C0 (1164:1335:1506)
+          (1164:1335:1506))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_77/C1 (282:367:453)
+          (282:367:453))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_80/A0 (1179:1347:1515)
+          (1179:1347:1515))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_82/B0 (772:902:1032)
+          (772:902:1032))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_130/A1 (1012:1174:1337)
+          (1012:1174:1337))
+        (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_130/A0 (1012:1174:1337)
+          (1012:1174:1337))
+        (INTERCONNECT ram2e_ufm\/SLICE_133/F1 ram2e_ufm\/SLICE_82/B1 (1206:1370:1535)
+          (1206:1370:1535))
+        (INTERCONNECT ram2e_ufm\/SLICE_101/F0 ram2e_ufm\/SLICE_82/A1 (740:863:986)
+          (740:863:986))
+        (INTERCONNECT ram2e_ufm\/SLICE_83/F0 ram2e_ufm\/SLICE_82/D0 (266:290:315)
+          (266:290:315))
+        (INTERCONNECT ram2e_ufm\/SLICE_82/F1 ram2e_ufm\/SLICE_82/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_83/F1 ram2e_ufm\/SLICE_83/D0 (520:573:626)
+          (520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_87/F0 ram2e_ufm\/SLICE_83/A0 (733:848:964)
+          (733:848:964))
+        (INTERCONNECT ram2e_ufm\/SLICE_110/F0 ram2e_ufm\/SLICE_85/B0 (765:883:1001)
+          (765:883:1001))
+        (INTERCONNECT ram2e_ufm\/SLICE_86/F1 ram2e_ufm\/SLICE_86/D0 (531:586:641)
+          (531:586:641))
+        (INTERCONNECT ram2e_ufm\/SLICE_86/F1 ram2e_ufm\/SLICE_109/A0 (741:861:982)
+          (741:861:982))
+        (INTERCONNECT ram2e_ufm\/SLICE_126/F0 ram2e_ufm\/SLICE_86/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_99/F0 ram2e_ufm\/SLICE_86/B0 (508:600:693)
+          (508:600:693))
+        (INTERCONNECT ram2e_ufm\/SLICE_88/F1 ram2e_ufm\/SLICE_88/C0 (280:362:445)
+          (280:362:445))
+        (INTERCONNECT ram2e_ufm\/SLICE_88/F1 ram2e_ufm\/SLICE_111/D0 (269:296:324)
+          (269:296:324))
+        (INTERCONNECT ram2e_ufm\/SLICE_104/F0 ram2e_ufm\/SLICE_89/D0 (266:290:315)
+          (266:290:315))
+        (INTERCONNECT ram2e_ufm\/SLICE_90/F1 ram2e_ufm\/SLICE_90/B0 (762:883:1004)
+          (762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_91/F1 ram2e_ufm\/SLICE_91/B0 (511:606:702)
+          (511:606:702))
+        (INTERCONNECT ram2e_ufm\/SLICE_91/F1 ram2e_ufm\/SLICE_92/D0 (860:955:1051)
+          (860:955:1051))
+        (INTERCONNECT ram2e_ufm\/SLICE_92/F1 ram2e_ufm\/SLICE_92/B0 (511:606:702)
+          (511:606:702))
+        (INTERCONNECT ram2e_ufm\/SLICE_92/F1 ram2e_ufm\/SLICE_102/B0 (511:606:702)
+          (511:606:702))
+        (INTERCONNECT ram2e_ufm\/SLICE_93/F1 ram2e_ufm\/SLICE_93/A0 (730:848:967)
+          (730:848:967))
+        (INTERCONNECT ram2e_ufm\/SLICE_100/F1 ram2e_ufm\/SLICE_94/A0 (743:869:995)
+          (743:869:995))
+        (INTERCONNECT ram2e_ufm\/SLICE_100/F1 ram2e_ufm\/SLICE_100/D0 (523:579:635)
+          (523:579:635))
+        (INTERCONNECT Ain\[4\]_I/PADDI ram2e_ufm\/SLICE_95/D0 (1587:1706:1825)
+          (1587:1706:1825))
+        (INTERCONNECT Ain\[6\]_I/PADDI ram2e_ufm\/SLICE_96/A0 (1729:1905:2082)
+          (1729:1905:2082))
+        (INTERCONNECT ram2e_ufm\/SLICE_97/F1 ram2e_ufm\/SLICE_97/B0 (762:883:1004)
+          (762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_99/F1 ram2e_ufm\/SLICE_99/D0 (520:573:626)
+          (520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_125/F1 ram2e_ufm\/SLICE_99/B0 (762:883:1004)
+          (762:883:1004))
+        (INTERCONNECT ram2e_ufm\/SLICE_115/F0 ram2e_ufm\/SLICE_102/A0 (740:863:986)
+          (740:863:986))
+        (INTERCONNECT ram2e_ufm\/SLICE_123/F1 ram2e_ufm\/SLICE_103/D0 (520:573:626)
+          (520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_128/F0 ram2e_ufm\/SLICE_103/A0 (733:848:964)
+          (733:848:964))
+        (INTERCONNECT ram2e_ufm\/SLICE_104/F1 ram2e_ufm\/SLICE_104/C0 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_122/F1 ram2e_ufm\/SLICE_105/D1 (266:290:315)
+          (266:290:315))
+        (INTERCONNECT ram2e_ufm\/SLICE_107/F1 ram2e_ufm\/SLICE_107/C0 (542:652:762)
+          (542:652:762))
+        (INTERCONNECT ram2e_ufm\/SLICE_107/F1 ram2e_ufm\/SLICE_134/A0 (741:861:982)
+          (741:861:982))
+        (INTERCONNECT ram2e_ufm\/SLICE_134/F1 ram2e_ufm\/SLICE_108/D1 (266:290:315)
+          (266:290:315))
+        (INTERCONNECT ram2e_ufm\/SLICE_111/F0 ram2e_ufm\/SLICE_111/C1 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_112/A0 (2246:2473:2700)
+          (2246:2473:2700))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_113/B1 (2321:2547:2774)
+          (2321:2547:2774))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_115/B0 (2648:2909:3171)
+          (2648:2909:3171))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_135/B0 (1951:2145:2340)
+          (1951:2145:2340))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_136/D1 (2036:2197:2359)
+          (2036:2197:2359))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_136/C0 (1720:1901:2083)
+          (1720:1901:2083))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_137/C1 (2090:2303:2517)
+          (2090:2303:2517))
+        (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_137/C0 (2090:2303:2517)
+          (2090:2303:2517))
+        (INTERCONNECT ram2e_ufm\/SLICE_114/F1 ram2e_ufm\/SLICE_114/D0 (520:573:626)
+          (520:573:626))
+        (INTERCONNECT ram2e_ufm\/SLICE_116/F0 ram2e_ufm\/SLICE_116/C1 (277:356:436)
+          (277:356:436))
+        (INTERCONNECT ram2e_ufm\/SLICE_117/F0 BA\[1\]_MGIOL/CE (1759:1942:2125)
+          (1759:1942:2125))
+        (INTERCONNECT ram2e_ufm\/SLICE_117/F0 BA\[0\]_MGIOL/CE (1759:1942:2125)
+          (1759:1942:2125))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQMH_MGIOL/CE (1433:1585:1737)
+          (1433:1585:1737))
+        (INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQML_MGIOL/CE (1433:1585:1737)
+          (1433:1585:1737))
+        (INTERCONNECT ram2e_ufm\/SLICE_120/F0 DQML_MGIOL/OPOS (1338:1473:1608)
+          (1338:1473:1608))
+        (INTERCONNECT ram2e_ufm\/SLICE_120/F1 DQMH_MGIOL/OPOS (1338:1473:1608)
+          (1338:1473:1608))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[7\]_MGIOL/CE (1529:1693:1857)
+          (1529:1693:1857))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[6\]_MGIOL/CE (1529:1693:1857)
+          (1529:1693:1857))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[5\]_MGIOL/CE (1893:2088:2284)
+          (1893:2088:2284))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[4\]_MGIOL/CE (1893:2088:2284)
+          (1893:2088:2284))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[3\]_MGIOL/CE (1529:1693:1857)
+          (1529:1693:1857))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[2\]_MGIOL/CE (1893:2088:2284)
+          (1893:2088:2284))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[1\]_MGIOL/CE (1529:1693:1857)
+          (1529:1693:1857))
+        (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[0\]_MGIOL/CE (1893:2088:2284)
+          (1893:2088:2284))
+        (INTERCONNECT ram2e_ufm\/SLICE_129/F1 BA\[1\]_MGIOL/OPOS (1445:1584:1723)
+          (1445:1584:1723))
+        (INTERCONNECT Ain\[0\]_I/PADDI ram2e_ufm\/SLICE_132/C1 (2395:2638:2881)
+          (2395:2638:2881))
+        (INTERCONNECT Ain\[7\]_I/PADDI ram2e_ufm\/SLICE_132/C0 (2031:2242:2454)
+          (2031:2242:2454))
+        (INTERCONNECT ram2e_ufm\/SLICE_136/F0 nDOE_I/PADDO (1538:1682:1827)
+          (1538:1682:1827))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F0 LED_I/PADDO (1041:1147:1254)(1041:1147:1254))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[0\]_I/PADDT (1300:1443:1587)
+          (1300:1443:1587))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[7\]_I/PADDT (1664:1839:2014)
+          (1664:1839:2014))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[6\]_I/PADDT (1664:1839:2014)
+          (1664:1839:2014))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[5\]_I/PADDT (1664:1839:2014)
+          (1664:1839:2014))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[4\]_I/PADDT (1664:1839:2014)
+          (1664:1839:2014))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[3\]_I/PADDT (1300:1443:1587)
+          (1300:1443:1587))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[2\]_I/PADDT (1300:1443:1587)
+          (1300:1443:1587))
+        (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[1\]_I/PADDT (1300:1443:1587)
+          (1300:1443:1587))
+        (INTERCONNECT PHI1_I/PADDI SLICE_139/A1 (1840:2021:2203)(1840:2021:2203))
+        (INTERCONNECT PHI1_I/PADDI SLICE_139/A0 (1840:2021:2203)(1840:2021:2203))
+        (INTERCONNECT PHI1_I/PADDI PHI1_MGIOL/DI (544:554:565)(544:554:565))
+        (INTERCONNECT PHI1_MGIOL/IN SLICE_139/B0 (1392:1572:1753)(1392:1572:1753))
+        (INTERCONNECT SLICE_139/F1 nVOE_I/PADDO (1344:1530:1717)(1344:1530:1717))
+        (INTERCONNECT ram2e_ufm\/SLICE_141/F0 RD\[3\]_I/PADDO (1263:1400:1537)
+          (1263:1400:1537))
+        (INTERCONNECT ram2e_ufm\/SLICE_141/F1 RD\[0\]_I/PADDO (1300:1433:1567)
+          (1300:1433:1567))
+        (INTERCONNECT ram2e_ufm\/SLICE_142/F0 RD\[4\]_I/PADDO (1367:1504:1642)
+          (1367:1504:1642))
+        (INTERCONNECT ram2e_ufm\/SLICE_143/F0 RD\[7\]_I/PADDO (1367:1504:1642)
+          (1367:1504:1642))
+        (INTERCONNECT ram2e_ufm\/SLICE_143/F1 RD\[1\]_I/PADDO (936:1038:1140)
+          (936:1038:1140))
+        (INTERCONNECT ram2e_ufm\/SLICE_144/F0 RD\[6\]_I/PADDO (1111:1225:1339)
+          (1111:1225:1339))
+        (INTERCONNECT ram2e_ufm\/SLICE_144/F1 RD\[2\]_I/PADDO (1041:1147:1254)
+          (1041:1147:1254))
+        (INTERCONNECT ram2e_ufm\/SLICE_147/F0 RD\[5\]_I/PADDO (1769:1938:2108)
+          (1769:1938:2108))
         (INTERCONNECT RD\[0\]_I/PADDI Vout\[0\]_MGIOL/OPOS (2416:2609:2802)
           (2416:2609:2802))
-        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_MGIOL/OPOS (2416:2609:2802)
-          (2416:2609:2802))
-        (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (30:36:43)(30:36:43))
-        (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (30:36:43)(30:36:43))
+        (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2446:2645:2845)(2446:2645:2845))
         (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (2416:2609:2802)
           (2416:2609:2802))
-        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_MGIOL/OPOS (1970:2136:2303)
-          (1970:2136:2303))
+        (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (2000:2173:2346)(2000:2173:2346))
         (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (2862:3081:3301)
           (2862:3081:3301))
-        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_MGIOL/OPOS (2416:2609:2802)
-          (2416:2609:2802))
+        (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2446:2645:2845)(2446:2645:2845))
         (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (2416:2609:2802)
           (2416:2609:2802))
-        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_MGIOL/OPOS (2416:2609:2802)
-          (2416:2609:2802))
-        (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (2345:2526:2708)
-          (2345:2526:2708))
-        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_MGIOL/OPOS (2345:2526:2708)
-          (2345:2526:2708))
+        (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (2427:2630:2834)(2427:2630:2834))
+        (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (2346:2526:2707)
+          (2346:2526:2707))
+        (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (3085:3339:3593)(3085:3339:3593))
         (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (2416:2609:2802)
           (2416:2609:2802))
-        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_MGIOL/OPOS (2416:2609:2802)
-          (2416:2609:2802))
+        (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2446:2645:2845)(2446:2645:2845))
         (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (2264:2449:2635)
           (2264:2449:2635))
-        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_MGIOL/OPOS (2955:3207:3459)
-          (2955:3207:3459))
+        (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (3003:3262:3521)(3003:3262:3521))
         (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (2345:2526:2708)
           (2345:2526:2708))
-        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_MGIOL/OPOS (1899:2054:2209)
-          (1899:2054:2209))
-        (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT RA\[9\]_MGIOL/IOLDO RA\[9\]_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT RA\[8\]_MGIOL/IOLDO RA\[8\]_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT RA\[7\]_MGIOL/IOLDO RA\[7\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[6\]_MGIOL/IOLDO RA\[6\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[5\]_MGIOL/IOLDO RA\[5\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[4\]_MGIOL/IOLDO RA\[4\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[2\]_MGIOL/IOLDO RA\[2\]_I/IOLDO (25:77:129)(25:77:129))
-        (INTERCONNECT RA\[1\]_MGIOL/IOLDO RA\[1\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (1929:2090:2252)(1929:2090:2252))
+        (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (30:36:43)(30:36:43))
+        (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (30:36:43)(30:36:43))
+        (INTERCONNECT RAout\[11\]_MGIOL/IOLDO RAout\[11\]_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT RAout\[10\]_MGIOL/IOLDO RAout\[10\]_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT RAout\[9\]_MGIOL/IOLDO RAout\[9\]_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT RAout\[8\]_MGIOL/IOLDO RAout\[8\]_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT RAout\[7\]_MGIOL/IOLDO RAout\[7\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[6\]_MGIOL/IOLDO RAout\[6\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[5\]_MGIOL/IOLDO RAout\[5\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[4\]_MGIOL/IOLDO RAout\[4\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[3\]_MGIOL/IOLDO RAout\[3\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[2\]_MGIOL/IOLDO RAout\[2\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[1\]_MGIOL/IOLDO RAout\[1\]_I/IOLDO (25:77:129)(25:77:129))
+        (INTERCONNECT RAout\[0\]_MGIOL/IOLDO RAout\[0\]_I/IOLDO (25:77:129)(25:77:129))
         (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (9:36:63)(9:36:63))
         (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT nCAS_MGIOL/IOLDO nCAS_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT nRAS_MGIOL/IOLDO nRAS_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT nCS_MGIOL/IOLDO nCS_I/IOLDO (9:36:63)(9:36:63))
-        (INTERCONNECT CKE_MGIOL/IOLDO CKE_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT nRWEout_MGIOL/IOLDO nRWEout_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT nCASout_MGIOL/IOLDO nCASout_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT nRASout_MGIOL/IOLDO nRASout_I/IOLDO (9:36:63)(9:36:63))
+        (INTERCONNECT CKEout_MGIOL/IOLDO CKEout_I/IOLDO (9:36:63)(9:36:63))
         (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (11:21:32)(11:21:32))
         (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (11:21:32)(11:21:32))
         (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (11:21:32)(11:21:32))
@@ -4932,14 +5982,6 @@
         (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (11:21:32)(11:21:32))
         (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (11:21:32)(11:21:32))
         (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (11:21:32)(11:21:32))
-        (INTERCONNECT Dout\[7\]_MGIOL/IOLDO Dout\[7\]_I/IOLDO (30:36:43)(30:36:43))
-        (INTERCONNECT Dout\[6\]_MGIOL/IOLDO Dout\[6\]_I/IOLDO (30:36:43)(30:36:43))
-        (INTERCONNECT Dout\[5\]_MGIOL/IOLDO Dout\[5\]_I/IOLDO (11:21:32)(11:21:32))
-        (INTERCONNECT Dout\[4\]_MGIOL/IOLDO Dout\[4\]_I/IOLDO (11:21:32)(11:21:32))
-        (INTERCONNECT Dout\[3\]_MGIOL/IOLDO Dout\[3\]_I/IOLDO (30:36:43)(30:36:43))
-        (INTERCONNECT Dout\[2\]_MGIOL/IOLDO Dout\[2\]_I/IOLDO (11:21:32)(11:21:32))
-        (INTERCONNECT Dout\[1\]_MGIOL/IOLDO Dout\[1\]_I/IOLDO (30:36:43)(30:36:43))
-        (INTERCONNECT Dout\[0\]_MGIOL/IOLDO Dout\[0\]_I/IOLDO (30:36:43)(30:36:43))
       )
     )
   )
diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo
index 1248ac1..71bdabd 100644
--- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo
+++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo
@@ -1,9 +1,9 @@
 
 // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
 
-// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd 
-// Netlist created on Thu Sep 21 05:34:46 2023
-// Netlist written on Thu Sep 21 05:35:15 2023
+// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd 
+// Netlist created on Thu Dec 28 23:09:57 2023
+// Netlist written on Thu Dec 28 23:10:23 2023
 // Design is for device LCMXO2-640HC
 // Design is for package TQFP100
 // Design is for performance grade 4
@@ -11,7 +11,8 @@
 `timescale 1 ns / 1 ps
 
 module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, 
-               Vout, nVOE, CKE, nCS, nRAS, nCAS, nRWE, BA, RA, RD, DQML, DQMH );
+               Vout, nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout, BA, 
+               RAout, DQML, DQMH, RD );
   input  C14M, PHI1, nWE, nWE80, nEN80, nC07X;
   input  [7:0] Ain;
   input  [7:0] Din;
@@ -19,9 +20,9 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   output [7:0] Dout;
   output nDOE;
   output [7:0] Vout;
-  output nVOE, CKE, nCS, nRAS, nCAS, nRWE;
+  output nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout;
   output [1:0] BA;
-  output [11:0] RA;
+  output [11:0] RAout;
   output DQML, DQMH;
   inout  [7:0] RD;
   wire   \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , 
@@ -31,76 +32,140 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
          \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , 
          \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , 
          \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , 
-         PHI1_c, PHI1reg, Ready, RWSel, CO0_1, \CmdTout_3[0] , N_576_i, S_1, 
-         \S_RNII9DO1_0[1] , N_461, \CS[0] , \CS[1] , N_511_i, N_504_i, 
-         un1_CS_0_sqmuxa_i, N_637, \CS[2] , N_510_i, \Din_c[0] , \Din_c[2] , 
-         \Din_c[3] , CmdBitbangMXO2_4_u_0_0_a2_0_1, N_643, CmdBitbangMXO2, 
-         CmdBitbangMXO2_4, \Din_c[7] , \Din_c[5] , N_629, CmdExecMXO2, 
-         CmdExecMXO2_4, N_466, \Din_c[1] , \Din_c[4] , N_478, 
-         CmdLEDGet_4_u_0_0_a2_0_2, N_476, CmdLEDGet, CmdLEDGet_4, N_626, N_605, 
-         CmdLEDSet, CmdLEDSet_4, CmdRWMaskSet, CmdRWMaskSet_4, N_401, 
-         CmdSetRWBankFFLED, CmdSetRWBankFFLED_4, N_474, 
-         CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0, CmdSetRWBankFFMXO2, 
-         CmdSetRWBankFFMXO2_4, \CmdTout[1] , \CmdTout[2] , N_556_i, N_555_i, 
-         \S[2] , \S[1] , \S[3] , \S[0] , N_6_i, DOEEN, \Ain_c[1] , 
-         \wb_dato[0] , LEDEN_RNO, \un1_LEDEN_0_sqmuxa_1_i_0[0] , LEDEN, 
-         N_558_i, \Ain_c[3] , \Ain_c[0] , N_552_i, N_127_i, \S_RNII9DO1_1[1] , 
-         \RA_c[0] , \RA_c[3] , N_591, \RWMask[1] , \RWMask[0] , \RWBank_5[1] , 
-         \RWBank_5[0] , LEDEN13, \RWBank[0] , \RWBank[1] , \RWMask[3] , 
-         \RWMask[2] , \RWBank_5[3] , \RWBank_5[2] , \RWBank[2] , \RWBank[3] , 
-         \RWMask[5] , \RWMask[4] , \RWBank_5[5] , \RWBank_5[4] , \RWBank[4] , 
-         \RWBank[5] , \RWMask[7] , \Din_c[6] , \RWMask[6] , \RWBank_5[7] , 
-         \RWBank_5[6] , \RWBank[6] , \RWBank[7] , \wb_dato[1] , N_291_i, 
-         N_292_i, N_88, \wb_dato[3] , \wb_dato[2] , N_289_i, N_290_i, 
-         \wb_dato[5] , \wb_dato[4] , N_287_i, N_288_i, \wb_dato[7] , 
-         \wb_dato[6] , N_285, N_286_i, nEN80_c, nWE_c, nC07X_c, RWSel_2, nCS61, 
-         nDOE_c, N_489, Ready_0_sqmuxa_0_a2_6_a2_4, Ready_0_sqmuxa, N_876_0, 
-         N_572, N_575, wb_reqc_1, \S_s_0_1[0] , N_133_i, \S_s_0[0] , N_129_i, 
-         N_131_i, N_388, wb_adr_7_5_214_0_1, \wb_adr_7_0_4[0] , N_376, N_642, 
-         \wb_adr_RNO[1] , \wb_adr_7[0] , \un1_wb_adr_0_sqmuxa_2_i[0] , 
-         \wb_adr[0] , \wb_adr[1] , N_41_i, N_43_i, \wb_adr[2] , \wb_adr[3] , 
-         N_295, N_294, \wb_adr[4] , \wb_adr[5] , N_39_i, N_296, \wb_adr[6] , 
-         \wb_adr[7] , wb_ack, N_300, N_395, wb_cyc_stb_RNO, N_104, wb_cyc_stb, 
-         N_336, N_627, N_621, \wb_dati_7_0_0[1] , \wb_dati_7_0_a2_1[0] , N_484, 
-         \wb_dati_7[1] , \wb_dati_7[0] , \wb_dati[0] , \wb_dati[1] , 
-         \wb_dati_7_0_2[3] , \wb_dati_7_0_0[3] , \wb_dati_7_0_o2_0[2] , N_345, 
-         \wb_dati_7[3] , \wb_dati_7[2] , \wb_dati[2] , \wb_dati[3] , N_346, 
-         N_349, \wb_dati_7_0_0[4] , \wb_dati_7[5] , \wb_dati_7[4] , 
-         \wb_dati[4] , \wb_dati[5] , \wb_dati_7_0_RNO[7] , N_424, 
-         \wb_dati_7_0_0[7] , N_422, \wb_dati_7_0_1[6] , \wb_dati_7[7] , 
-         \wb_dati_7[6] , \wb_dati[6] , \wb_dati[7] , N_397, wb_reqc_i, 
-         wb_adr_0_sqmuxa_i, wb_req, wb_rst8, \S_RNII9DO1[1] , wb_rst, N_586, 
-         N_584, N_475, wb_we_7_iv_0_0_0_1, wb_we_RNO, 
-         \un1_wb_cyc_stb_0_sqmuxa_1_i[0] , wb_we, N_255, N_358_i, N_254, Vout3, 
-         N_635, nCAS_s_i_tz_0, un1_CS_0_sqmuxa_0_0_a2_1_4, N_327, 
-         un1_CS_0_sqmuxa_0_0_0, \wb_dati_7_0_a2_0_1[7] , N_579, 
-         CKE_6_iv_i_a2_0, CKE_6_iv_i_0_1, CKE_6_iv_i_0, N_449, N_365, N_364, 
-         \un1_wb_adr_0_sqmuxa_2_1[0] , N_623, N_616, N_279, N_633, N_264, 
-         N_570, N_452, \wb_dati_7_0_a2_2_1[3] , N_455, N_644, DQML_s_i_a2_0, 
-         N_28_i, wb_adr_7_5_214_a2_2_0, N_569, N_577, N_634, 
-         \wb_dati_7_0_a2_2_0[1] , N_265_i, \un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] , 
-         \wb_dati_7_0_a2_0[6] , \wb_dati_7_0_a2_4_0[7] , N_393, nCAS_0_sqmuxa, 
-         N_639, \RA_42[10] , N_640, un1_nCS61_1_i, Ready_0_sqmuxa_0_a2_6_a2_2, 
-         N_562, N_377, N_628, un1_CS_0_sqmuxa_0_0_3, un1_CS_0_sqmuxa_0_0_2, 
-         un1_CS_0_sqmuxa_0_0_a2_3_2, N_567, N_561_i, nCS_6_u_i_0, N_559_1, 
-         N_559_i, nRAS_2_iv_i, un1_CS_0_sqmuxa_0_0_a2_1, N_328, N_330, 
-         nCS_6_u_i_a2_1, N_429, N_351, \wb_adr_7_0_a2_5_0[0] , N_378, 
-         \wb_adr_7_0_1[0] , \wb_adr_7_0_0[0] , 
-         \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] , un1_CS_0_sqmuxa_0_0_a2_4_2, 
-         un1_CS_0_sqmuxa_0_0_a2_4_4, N_565, un1_CS_0_sqmuxa_0_0_a2_2_2, 
-         un1_CS_0_sqmuxa_0_0_a2_2_4, \wb_adr_7_0_a2_0[0] , 
-         un1_CS_0_sqmuxa_0_0_a2_1_2, un1_CS_0_sqmuxa_0_0_a2_3_0, N_394, N_49_i, 
-         N_456, N_477, N_566_i, \BA_4[0] , \RA_42[11] , \BA_4[1] , N_59_i, 
-         \Ain_c[5] , \Ain_c[4] , N_551_i, \RA_42_3_0[5] , \Ain_c[6] , N_550_i, 
-         \Ain_c[2] , \Ain_c[7] , N_549_i, N_553_i, nWE80_c, nRWE_r_0, RDOE_i, 
-         LED_c, \RD_in[0] , DQMH_c, DQML_c, \RD_in[7] , \RD_in[6] , \RD_in[5] , 
-         \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , \RA_c[11] , 
-         \RA_c[10] , \RA_c[9] , \RA_c[8] , \RA_c[7] , \RA_c[6] , \RA_c[5] , 
-         \RA_c[4] , \RA_c[2] , \RA_c[1] , \BA_c[1] , \BA_c[0] , nRWE_c, nCAS_c, 
-         nRAS_c, nCS_c, CKE_c, \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , 
-         \Vout_c[4] , \Vout_c[3] , \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , 
-         \Dout_c[7] , \Dout_c[6] , \Dout_c[5] , \Dout_c[4] , \Dout_c[3] , 
-         \Dout_c[2] , \Dout_c[1] , \Dout_c[0] , VCCI;
+         \S[1] , N_551, \S[0] , \ram2e_ufm/CKE_7 , CKE_7_RNIS77M1, CKE, 
+         \ram2e_ufm/wb_adr_0_sqmuxa_1_i , RWSel, CO0_0, \CmdTout_3[0] , 
+         N_185_i, GND, CO0_1, \RC[2] , \RC[1] , N_360_i, RC12, 
+         \ram2e_ufm/N_821 , \ram2e_ufm/SUM1_0_0 , \ram2e_ufm/SUM0_i_a3_4_0 , 
+         \ram2e_ufm/N_886 , \ram2e_ufm/N_215 , \CS[1] , \ram2e_ufm/SUM0_i_4 , 
+         \CS[2] , CmdExecMXO2_3_0_a3_0_RNI6S1P8, N_547_i, un1_CS_0_sqmuxa_i, 
+         \CS[0] , \ram2e_ufm/N_234 , CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514, 
+         \ram2e_ufm/N_800 , \Din_c[5] , \Din_c[3] , 
+         \ram2e_ufm/CmdLEDGet_3_0_a3_1 , \ram2e_ufm/N_847 , \Din_c[1] , 
+         \Din_c[2] , CmdLEDGet_3, N_187_i, CmdLEDGet, \Din_c[7] , 
+         \ram2e_ufm/N_883 , \Din_c[4] , CmdLEDSet_3, CmdLEDSet, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 , CmdRWMaskSet_3, CmdRWMaskSet, 
+         \ram2e_ufm/N_850 , \Din_c[0] , CmdSetRWBankFFLED_4, CmdSetRWBankFFLED, 
+         \CmdTout[1] , \CmdTout[2] , N_369_i, N_368_i, \ram2e_ufm/N_186 , 
+         \RA[1] , \S[3] , N_1080_0, \ram2e_ufm/N_660 , DOEEN, 
+         \ram2e_ufm/N_193 , \ram2e_ufm/N_182 , \Ain_c[1] , \ram2e_ufm/N_659 , 
+         \ram2e_ufm/N_801 , \ram2e_ufm/N_684 , \ram2e_ufm/RA_35_0_0_1[0] , 
+         N_223, \RA_35[0] , N_126, \RA[0] , \ram2e_ufm/RA_35_0_0_0[3] , 
+         \ram2e_ufm/N_680 , \ram2e_ufm/N_679 , \Ain_c[2] , \RA_35[3] , 
+         \RA_35[2] , \RA[2] , \RA[3] , \ram2e_ufm/N_621 , \Ain_c[5] , 
+         \ram2e_ufm/RA_35_0_0_0[5] , \ram2e_ufm/RA_35_0_0_0[4] , \RA_35[5] , 
+         \RA_35[4] , \RA[4] , \RA[5] , \ram2e_ufm/RA_35_0_0_0_0[7] , 
+         \ram2e_ufm/RA_35_0_0_0_0[6] , \RA_35[7] , \RA_35[6] , \RA[6] , 
+         \RA[7] , \ram2e_ufm/N_242 , \ram2e_ufm/RA_35_0_0_0[9] , \RA[9] , 
+         \ram2e_ufm/N_699 , \RA[8] , \ram2e_ufm/N_698 , \ram2e_ufm/N_221 , 
+         \RA_35[9] , un2_S_2_i_0_0_o3_RNIHFHN3, \RWBank[4] , \ram2e_ufm/N_845 , 
+         \RA[11] , \ram2e_ufm/N_628 , \ram2e_ufm/RA_35_2_0_0[10] , 
+         \ram2e_ufm/N_624 , \ram2e_ufm/N_627 , \RA_35[11] , \RA_35[10] , 
+         \RA[10] , \RC_3[2] , \RC_3[1] , \ram2e_ufm/RWMask[1] , 
+         \ram2e_ufm/N_188 , \ram2e_ufm/RWMask[0] , \RWBank_3[1] , 
+         \RWBank_3[0] , \RWBank[0] , \RWBank[1] , \ram2e_ufm/RWMask[3] , 
+         \ram2e_ufm/RWMask[2] , \RWBank_3[3] , \RWBank_3[2] , \RWBank[2] , 
+         \RWBank[3] , \ram2e_ufm/RWMask[5] , \ram2e_ufm/RWMask[4] , 
+         \RWBank_3[5] , \RWBank_3[4] , \RWBank[5] , \ram2e_ufm/RWMask[7] , 
+         \Din_c[6] , \ram2e_ufm/RWMask[6] , \RWBank_3[7] , \RWBank_3[6] , 
+         \RWBank[6] , \RWBank[7] , \Ain_c[3] , nC07X_c, nWE_c, RWSel_2, 
+         un9_VOEEN_0_a2_0_a3_0_a3, \ram2e_ufm/N_885 , 
+         \ram2e_ufm/Ready3_0_a3_4 , \ram2e_ufm/Ready3_0_a3_5 , 
+         \ram2e_ufm/Ready3_0_a3_3 , Ready3, Ready, N_1026_0, 
+         \ram2e_ufm/S_r_i_0_o2[1] , \ram2e_ufm/N_194 , \ram2e_ufm/N_271 , S_1, 
+         \ram2e_ufm/N_643 , N_362_i, \S_s_0_0[0] , \S[2] , N_372_i, N_361_i, 
+         N_1078_0, VOEEN, BA_0_sqmuxa, \ram2e_ufm/N_285_i , \ram2e_ufm/N_804 , 
+         \ram2e_ufm/N_641 , \ram2e_ufm/N_640 , \ram2e_ufm/N_872 , N_370_i, 
+         nCAS, \ram2e_ufm/N_616 , \ram2e_ufm/N_615 , \ram2e_ufm/N_617 , 
+         \ram2e_ufm/nRAS_s_i_0_0 , N_358_i, nRAS, \ram2e_ufm/N_226 , 
+         \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] , \ram2e_ufm/N_866 , N_359_i, nRWE, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 , 
+         \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 , \ram2e_ufm/CmdBitbangMXO2_3 , 
+         \ram2e_ufm/CmdBitbangMXO2 , \ram2e_ufm/N_851 , 
+         \ram2e_ufm/CmdExecMXO2_3 , \ram2e_ufm/CmdExecMXO2 , 
+         \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 , \ram2e_ufm/N_190 , 
+         \ram2e_ufm/CmdSetRWBankFFChip_3 , \ram2e_ufm/CmdSetRWBankFFChip , 
+         \ram2e_ufm/wb_dato[0] , \ram2e_ufm/N_295 , 
+         \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] , \ram2e_ufm/LEDEN , 
+         \ram2e_ufm/N_212 , \ram2e_ufm/wb_dato[1] , \ram2e_ufm/N_307_i , 
+         \ram2e_ufm/N_309_i , \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] , 
+         \ram2e_ufm/wb_dato[3] , \ram2e_ufm/wb_dato[2] , \ram2e_ufm/N_302_i , 
+         \ram2e_ufm/N_304_i , \ram2e_ufm/wb_dato[5] , \ram2e_ufm/wb_dato[4] , 
+         \ram2e_ufm/N_301_i , \ram2e_ufm/N_310_i , \ram2e_ufm/wb_dato[7] , 
+         \ram2e_ufm/wb_dato[6] , \ram2e_ufm/N_296 , \ram2e_ufm/N_300_i , 
+         \ram2e_ufm/wb_adr_7_5_41_0_1 , \ram2e_ufm/N_768 , \ram2e_ufm/N_793 , 
+         \ram2e_ufm/wb_adr_7_i_i_4[0] , \ram2e_ufm/wb_adr_7_i_i_5[0] , 
+         \ram2e_ufm/wb_adr_RNO[1] , \ram2e_ufm/wb_adr_7_i_i[0] , 
+         \ram2e_ufm/CmdBitbangMXO2_RNINSM62 , \ram2e_ufm/wb_adr[0] , 
+         \ram2e_ufm/wb_adr[1] , \ram2e_ufm/N_268_i , \ram2e_ufm/N_80_i , 
+         \ram2e_ufm/wb_adr[2] , \ram2e_ufm/wb_adr[3] , \ram2e_ufm/N_290 , 
+         \ram2e_ufm/N_294 , \ram2e_ufm/wb_adr[4] , \ram2e_ufm/wb_adr[5] , 
+         \ram2e_ufm/N_267_i , \ram2e_ufm/N_284 , \ram2e_ufm/wb_adr[6] , 
+         \ram2e_ufm/wb_adr[7] , \ram2e_ufm/wb_ack , \ram2e_ufm/N_336 , 
+         \ram2e_ufm/N_687 , \ram2e_ufm/wb_cyc_stb_RNO , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] , 
+         \ram2e_ufm/wb_cyc_stb , \ram2e_ufm/N_849 , 
+         \ram2e_ufm/wb_dati_7_0_0_0[1] , \ram2e_ufm/N_611 , 
+         \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] , \ram2e_ufm/N_856 , 
+         \ram2e_ufm/wb_dati_7[1] , \ram2e_ufm/wb_dati_7[0] , 
+         \ram2e_ufm/wb_dati[0] , \ram2e_ufm/wb_dati[1] , 
+         \ram2e_ufm/wb_dati_7_0_0_0_0[3] , \ram2e_ufm/N_783 , 
+         \ram2e_ufm/N_760 , \ram2e_ufm/wb_dati_7_0_0_o3_0[2] , 
+         \ram2e_ufm/wb_dati_7[3] , \ram2e_ufm/wb_dati_7[2] , 
+         \ram2e_ufm/wb_dati[2] , \ram2e_ufm/wb_dati[3] , \ram2e_ufm/N_757 , 
+         \ram2e_ufm/N_763 , \ram2e_ufm/wb_dati_7_0_0_0[4] , 
+         \ram2e_ufm/wb_dati_7[5] , \ram2e_ufm/wb_dati_7[4] , 
+         \ram2e_ufm/wb_dati[4] , \ram2e_ufm/wb_dati[5] , \ram2e_ufm/N_604 , 
+         \ram2e_ufm/wb_dati_7_0_0_0_0[7] , \ram2e_ufm/N_602 , 
+         \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] , \ram2e_ufm/wb_dati_7_0_0_0[6] , 
+         \ram2e_ufm/wb_dati_7[7] , \ram2e_ufm/wb_dati_7[6] , 
+         \ram2e_ufm/wb_dati[6] , \ram2e_ufm/wb_dati[7] , \ram2e_ufm/wb_reqc_1 , 
+         \ram2e_ufm/wb_reqc_i , \ram2e_ufm/wb_req , \ram2e_ufm/wb_rst8 , 
+         \ram2e_ufm/wb_rst16_i , \ram2e_ufm/wb_rst , 
+         \ram2e_ufm/wb_we_7_iv_0_0_3_0_0 , \ram2e_ufm/N_799 , 
+         \ram2e_ufm/N_208 , \ram2e_ufm/wb_we_7_iv_0_0_3_0_1 , 
+         \ram2e_ufm/wb_we_RNO , \ram2e_ufm/wb_we_RNO_0 , \ram2e_ufm/wb_we , 
+         \ram2e_ufm/N_338 , \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 , \ram2e_ufm/N_817 , 
+         \ram2e_ufm/CKE_7_sm0 , \ram2e_ufm/N_720_tz , \ram2e_ufm/SUM0_i_0 , 
+         \ram2e_ufm/N_350 , \ram2e_ufm/N_187 , \ram2e_ufm/SUM0_i_3 , 
+         \ram2e_ufm/SUM0_i_1 , \ram2e_ufm/N_755 , \ram2e_ufm/N_735 , 
+         \ram2e_ufm/N_345 , \ram2e_ufm/N_777 , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] , \ram2e_ufm/N_250 , 
+         \ram2e_ufm/N_256 , \ram2e_ufm/wb_adr_7_i_i_3_1[0] , 
+         \ram2e_ufm/wb_adr_7_i_i_3[0] , \ram2e_ufm/N_254 , \ram2e_ufm/N_807 , 
+         \ram2e_ufm/N_876 , \ram2e_ufm/N_784 , \ram2e_ufm/N_560 , \BA_4[0] , 
+         \ram2e_ufm/N_781 , \ram2e_ufm/N_873 , \ram2e_ufm/N_184 , 
+         \ram2e_ufm/N_625 , \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] , 
+         \ram2e_ufm/N_811 , \ram2e_ufm/N_206 , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] , \ram2e_ufm/N_185 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S , \ram2e_ufm/N_637 , 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 , \ram2e_ufm/N_592 , 
+         \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] , \ram2e_ufm/N_634 , 
+         \ram2e_ufm/N_753 , \ram2e_ufm/wb_adr_7_i_i_1[0] , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] , 
+         \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] , 
+         \ram2e_ufm/wb_dati_7_0_0_a3_1[6] , \ram2e_ufm/N_890 , 
+         \ram2e_ufm/N_220 , \ram2e_ufm/N_196 , \ram2e_ufm/N_243 , \Ain_c[4] , 
+         \Ain_c[6] , \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] , 
+         \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] , \ram2e_ufm/N_565 , 
+         \ram2e_ufm/CKE_7s2_0_0_0 , \ram2e_ufm/N_204 , 
+         \ram2e_ufm/wb_adr_7_5_41_a3_3_0 , \ram2e_ufm/N_595 , 
+         \ram2e_ufm/nRWE_s_i_0_63_1 , \ram2e_ufm/N_792 , 
+         \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] , 
+         \ram2e_ufm/N_553 , nEN80_c, \ram2e_ufm/N_241_i , \ram2e_ufm/N_814 , 
+         N_225_i, N_201_i, N_507_i, N_508, Vout3, \BA_4[1] , \Ain_c[0] , 
+         \Ain_c[7] , nDOE_c, LED_c, RDOE_i, PHI1_c, PHI1r, nVOE_c, N_263_i, 
+         N_667, N_648, N_662, N_666, N_663, N_665, N_664, \RD_in[0] , 
+         \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , 
+         \RD_in[2] , \RD_in[1] , DQMH_c, DQML_c, \RAout_c[11] , \RAout_c[10] , 
+         \RAout_c[9] , \RAout_c[8] , \RAout_c[7] , \RAout_c[6] , \RAout_c[5] , 
+         \RAout_c[4] , \RAout_c[3] , \RAout_c[2] , \RAout_c[1] , \RAout_c[0] , 
+         \BA_c[1] , \BA_c[0] , nRWEout_c, nCASout_c, nRASout_c, CKEout_c, 
+         \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] , 
+         \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , VCCI;
 
   SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), 
     .Q1(\FS[0] ), .FCO(\FS_cry[0] ));
@@ -127,427 +192,686 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), 
     .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), 
     .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
-  SLICE_9 SLICE_9( .C1(PHI1_c), .B1(PHI1reg), .A1(Ready), .D0(RWSel), 
-    .A0(CO0_1), .DI0(\CmdTout_3[0] ), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(\CmdTout_3[0] ), .Q0(CO0_1), .F1(S_1));
-  SLICE_10 SLICE_10( .D1(\S_RNII9DO1_0[1] ), .C1(N_461), .B1(\CS[0] ), 
-    .A1(\CS[1] ), .D0(\S_RNII9DO1_0[1] ), .C0(N_461), .A0(\CS[0] ), 
-    .DI1(N_511_i), .DI0(N_504_i), .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), 
-    .F0(N_504_i), .Q0(\CS[0] ), .F1(N_511_i), .Q1(\CS[1] ));
-  SLICE_11 SLICE_11( .D1(\CS[0] ), .C1(N_461), .B1(\S_RNII9DO1_0[1] ), 
-    .C0(N_637), .B0(\CS[1] ), .A0(\CS[2] ), .DI0(N_510_i), 
-    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_510_i), .Q0(\CS[2] ), 
-    .F1(N_637));
-  SLICE_12 SLICE_12( .D1(\Din_c[0] ), .B1(\Din_c[2] ), .A1(\Din_c[3] ), 
-    .D0(RWSel), .C0(CmdBitbangMXO2_4_u_0_0_a2_0_1), .B0(N_643), 
-    .A0(CmdBitbangMXO2), .DI0(CmdBitbangMXO2_4), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(CmdBitbangMXO2_4), .Q0(CmdBitbangMXO2), 
-    .F1(CmdBitbangMXO2_4_u_0_0_a2_0_1));
-  SLICE_13 SLICE_13( .D1(RWSel), .C1(\Din_c[7] ), .A1(\Din_c[5] ), .D0(N_643), 
-    .C0(RWSel), .B0(N_629), .A0(CmdExecMXO2), .DI0(CmdExecMXO2_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdExecMXO2_4), .Q0(CmdExecMXO2), 
-    .F1(N_466));
-  SLICE_14 SLICE_14( .D1(\Din_c[0] ), .C1(\Din_c[1] ), .B1(\Din_c[4] ), 
-    .A1(N_478), .D0(CmdLEDGet_4_u_0_0_a2_0_2), .C0(N_476), .B0(CmdLEDGet), 
-    .A0(RWSel), .DI0(CmdLEDGet_4), .CE(N_576_i), .CLK(C14M_c), 
-    .F0(CmdLEDGet_4), .Q0(CmdLEDGet), .F1(CmdLEDGet_4_u_0_0_a2_0_2));
-  SLICE_15 SLICE_15( .D1(\Din_c[4] ), .C1(N_626), .B1(N_476), .A1(\Din_c[1] ), 
-    .D0(RWSel), .C0(N_605), .A0(CmdLEDSet), .DI0(CmdLEDSet_4), .CE(N_576_i), 
-    .CLK(C14M_c), .F0(CmdLEDSet_4), .Q0(CmdLEDSet), .F1(N_605));
-  SLICE_16 SLICE_16( .D1(\Din_c[4] ), .B1(\Din_c[1] ), .A1(N_476), .D0(RWSel), 
-    .C0(N_643), .B0(N_626), .A0(CmdRWMaskSet), .DI0(CmdRWMaskSet_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdRWMaskSet_4), .Q0(CmdRWMaskSet), 
-    .F1(N_643));
-  SLICE_17 SLICE_17( .D1(\Din_c[4] ), .C1(N_476), .B1(\Din_c[1] ), .A1(N_626), 
-    .D0(RWSel), .C0(N_401), .A0(CmdSetRWBankFFLED), .DI0(CmdSetRWBankFFLED_4), 
-    .CE(N_576_i), .CLK(C14M_c), .F0(CmdSetRWBankFFLED_4), 
-    .Q0(CmdSetRWBankFFLED), .F1(N_401));
-  SLICE_18 SLICE_18( .D1(N_474), .C1(\CS[1] ), .A1(\CS[2] ), .D0(RWSel), 
-    .C0(N_476), .B0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), 
-    .A0(CmdSetRWBankFFMXO2), .DI0(CmdSetRWBankFFMXO2_4), .CE(N_576_i), 
-    .CLK(C14M_c), .F0(CmdSetRWBankFFMXO2_4), .Q0(CmdSetRWBankFFMXO2), 
-    .F1(N_476));
-  SLICE_19 SLICE_19( .D1(\CmdTout[1] ), .C1(\CmdTout[2] ), .B1(CO0_1), 
-    .A1(RWSel), .D0(\CmdTout[1] ), .B0(CO0_1), .A0(RWSel), .DI1(N_556_i), 
-    .DI0(N_555_i), .CE(N_576_i), .CLK(C14M_c), .F0(N_555_i), .Q0(\CmdTout[1] ), 
-    .F1(N_556_i), .Q1(\CmdTout[2] ));
-  SLICE_20 SLICE_20( .D1(\S[2] ), .C1(\S[1] ), .B1(\S[3] ), .A1(\S[0] ), 
-    .D0(\S[2] ), .C0(\S[1] ), .B0(\S[3] ), .A0(\S[0] ), .DI0(N_6_i), 
-    .CLK(C14M_c), .F0(N_6_i), .Q0(DOEEN), .F1(N_576_i));
-  SLICE_21 SLICE_21( .C1(\S[0] ), .B1(\Ain_c[1] ), .A1(\S[3] ), 
-    .D0(\Din_c[0] ), .B0(\wb_dato[0] ), .A0(\S[3] ), .DI0(LEDEN_RNO), 
-    .CE(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .CLK(C14M_c), .F0(LEDEN_RNO), 
-    .Q0(LEDEN), .F1(N_558_i));
-  SLICE_22 SLICE_22( .D1(\S[0] ), .C1(\Ain_c[3] ), .A1(\S[3] ), .D0(\S[0] ), 
-    .C0(\Ain_c[0] ), .A0(\S[3] ), .DI1(N_552_i), .DI0(N_127_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c), .F0(N_127_i), .Q0(\RA_c[0] ), 
-    .F1(N_552_i), .Q1(\RA_c[3] ));
-  SLICE_23 SLICE_23( .D1(N_591), .C1(\RWMask[1] ), .A1(\Din_c[1] ), .D0(N_591), 
-    .C0(\RWMask[0] ), .A0(\Din_c[0] ), .DI1(\RWBank_5[1] ), 
-    .DI0(\RWBank_5[0] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[0] ), 
-    .Q0(\RWBank[0] ), .F1(\RWBank_5[1] ), .Q1(\RWBank[1] ));
-  SLICE_24 SLICE_24( .C1(\RWMask[3] ), .B1(\Din_c[3] ), .A1(N_591), 
-    .D0(\Din_c[2] ), .B0(\RWMask[2] ), .A0(N_591), .DI1(\RWBank_5[3] ), 
-    .DI0(\RWBank_5[2] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[2] ), 
-    .Q0(\RWBank[2] ), .F1(\RWBank_5[3] ), .Q1(\RWBank[3] ));
-  SLICE_25 SLICE_25( .C1(\RWMask[5] ), .B1(\Din_c[5] ), .A1(N_591), 
-    .D0(\RWMask[4] ), .C0(\Din_c[4] ), .A0(N_591), .DI1(\RWBank_5[5] ), 
-    .DI0(\RWBank_5[4] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[4] ), 
-    .Q0(\RWBank[4] ), .F1(\RWBank_5[5] ), .Q1(\RWBank[5] ));
-  SLICE_26 SLICE_26( .D1(\Din_c[7] ), .C1(\RWMask[7] ), .A1(N_591), 
-    .C0(\Din_c[6] ), .B0(\RWMask[6] ), .A0(N_591), .DI1(\RWBank_5[7] ), 
-    .DI0(\RWBank_5[6] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[6] ), 
-    .Q0(\RWBank[6] ), .F1(\RWBank_5[7] ), .Q1(\RWBank[7] ));
-  SLICE_27 SLICE_27( .D1(\Din_c[1] ), .C1(\wb_dato[1] ), .A1(\S[3] ), 
-    .C0(\wb_dato[0] ), .B0(\Din_c[0] ), .A0(\S[3] ), .DI1(N_291_i), 
-    .DI0(N_292_i), .CE(N_88), .CLK(C14M_c), .F0(N_292_i), .Q0(\RWMask[0] ), 
-    .F1(N_291_i), .Q1(\RWMask[1] ));
-  SLICE_28 SLICE_28( .D1(\wb_dato[3] ), .B1(\Din_c[3] ), .A1(\S[3] ), 
-    .C0(\wb_dato[2] ), .B0(\Din_c[2] ), .A0(\S[3] ), .DI1(N_289_i), 
-    .DI0(N_290_i), .CE(N_88), .CLK(C14M_c), .F0(N_290_i), .Q0(\RWMask[2] ), 
-    .F1(N_289_i), .Q1(\RWMask[3] ));
-  SLICE_29 SLICE_29( .D1(\wb_dato[5] ), .C1(\Din_c[5] ), .A1(\S[3] ), 
-    .C0(\wb_dato[4] ), .B0(\Din_c[4] ), .A0(\S[3] ), .DI1(N_287_i), 
-    .DI0(N_288_i), .CE(N_88), .CLK(C14M_c), .F0(N_288_i), .Q0(\RWMask[4] ), 
-    .F1(N_287_i), .Q1(\RWMask[5] ));
-  SLICE_30 SLICE_30( .D1(\wb_dato[7] ), .C1(\Din_c[7] ), .A1(\S[3] ), 
-    .C0(\wb_dato[6] ), .B0(\Din_c[6] ), .A0(\S[3] ), .DI1(N_285), 
-    .DI0(N_286_i), .CE(N_88), .CLK(C14M_c), .F0(N_286_i), .Q0(\RWMask[6] ), 
-    .F1(N_285), .Q1(\RWMask[7] ));
-  SLICE_31 SLICE_31( .C1(nEN80_c), .B1(nWE_c), .A1(DOEEN), .D0(nC07X_c), 
-    .C0(\RA_c[0] ), .B0(nWE_c), .A0(\RA_c[3] ), .DI0(RWSel_2), .CE(nCS61), 
-    .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(nDOE_c));
-  SLICE_32 SLICE_32( .D1(\FS[6] ), .C1(\FS[7] ), .B1(N_489), 
-    .A1(Ready_0_sqmuxa_0_a2_6_a2_4), .C0(Ready_0_sqmuxa), .A0(Ready), 
-    .DI0(N_876_0), .CLK(C14M_c), .F0(N_876_0), .Q0(Ready), .F1(Ready_0_sqmuxa));
-  SLICE_33 SLICE_33( .D1(N_572), .C1(N_575), .B1(S_1), .A1(wb_reqc_1), 
-    .D0(\S_s_0_1[0] ), .C0(\S[1] ), .B0(S_1), .A0(\S[0] ), .DI1(N_133_i), 
-    .DI0(\S_s_0[0] ), .CLK(C14M_c), .F0(\S_s_0[0] ), .Q0(\S[0] ), .F1(N_133_i), 
-    .Q1(\S[1] ));
-  SLICE_34 SLICE_34( .D1(N_575), .C1(\S[2] ), .B1(S_1), .A1(\S[3] ), 
-    .D0(N_575), .C0(\S[3] ), .B0(S_1), .A0(\S[2] ), .DI1(N_129_i), 
-    .DI0(N_131_i), .CLK(C14M_c), .F0(N_131_i), .Q0(\S[2] ), .F1(N_129_i), 
-    .Q1(\S[3] ));
-  SLICE_35 SLICE_35( .D1(N_388), .C1(\Din_c[1] ), .B1(\S[2] ), 
-    .A1(wb_adr_7_5_214_0_1), .D0(\wb_adr_7_0_4[0] ), .C0(N_376), .B0(N_642), 
-    .A0(\FS[13] ), .DI1(\wb_adr_RNO[1] ), .DI0(\wb_adr_7[0] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_adr_7[0] ), 
-    .Q0(\wb_adr[0] ), .F1(\wb_adr_RNO[1] ), .Q1(\wb_adr[1] ));
-  SLICE_36 SLICE_36( .C1(\Din_c[3] ), .B1(\S[2] ), .C0(\Din_c[2] ), 
-    .B0(\S[2] ), .DI1(N_41_i), .DI0(N_43_i), .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), 
-    .CLK(C14M_c), .F0(N_43_i), .Q0(\wb_adr[2] ), .F1(N_41_i), .Q1(\wb_adr[3] ));
-  SLICE_37 SLICE_37( .C1(\S[2] ), .B1(\FS[14] ), .A1(\Din_c[5] ), 
-    .D0(\Din_c[4] ), .C0(\S[2] ), .B0(\FS[14] ), .DI1(N_295), .DI0(N_294), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_294), 
-    .Q0(\wb_adr[4] ), .F1(N_295), .Q1(\wb_adr[5] ));
-  SLICE_38 SLICE_38( .C1(\Din_c[7] ), .B1(\S[2] ), .D0(\Din_c[6] ), 
-    .C0(\FS[14] ), .B0(\S[2] ), .DI1(N_39_i), .DI0(N_296), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_296), 
-    .Q0(\wb_adr[6] ), .F1(N_39_i), .Q1(\wb_adr[7] ));
-  SLICE_39 SLICE_39( .D1(\FS[0] ), .C1(\FS[14] ), .B1(wb_ack), .A1(N_300), 
-    .C0(N_395), .B0(\S[3] ), .A0(CmdExecMXO2), .DI0(wb_cyc_stb_RNO), 
-    .CE(N_104), .CLK(C14M_c), .F0(wb_cyc_stb_RNO), .Q0(wb_cyc_stb), .F1(N_395));
-  SLICE_40 SLICE_40( .D1(N_336), .C1(N_627), .B1(N_621), 
-    .A1(\wb_dati_7_0_0[1] ), .D0(\wb_dati_7_0_a2_1[0] ), .C0(\S[2] ), 
-    .B0(\wb_adr[0] ), .A0(N_484), .DI1(\wb_dati_7[1] ), .DI0(\wb_dati_7[0] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[0] ), 
-    .Q0(\wb_dati[0] ), .F1(\wb_dati_7[1] ), .Q1(\wb_dati[1] ));
-  SLICE_41 SLICE_41( .D1(\wb_dati_7_0_2[3] ), .B1(\wb_dati_7_0_0[3] ), 
-    .A1(N_336), .D0(\wb_dati_7_0_o2_0[2] ), .C0(N_345), .B0(\S[2] ), 
-    .A0(\wb_adr[2] ), .DI1(\wb_dati_7[3] ), .DI0(\wb_dati_7[2] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[2] ), 
-    .Q0(\wb_dati[2] ), .F1(\wb_dati_7[3] ), .Q1(\wb_dati[3] ));
-  SLICE_42 SLICE_42( .D1(\wb_dati_7_0_o2_0[2] ), .C1(N_345), .B1(\S[2] ), 
-    .A1(\wb_adr[5] ), .D0(N_346), .C0(N_349), .B0(N_345), 
-    .A0(\wb_dati_7_0_0[4] ), .DI1(\wb_dati_7[5] ), .DI0(\wb_dati_7[4] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[4] ), 
-    .Q0(\wb_dati[4] ), .F1(\wb_dati_7[5] ), .Q1(\wb_dati[5] ));
-  SLICE_43 SLICE_43( .D1(\wb_dati_7_0_RNO[7] ), .C1(N_424), 
-    .B1(\wb_dati_7_0_0[7] ), .A1(N_422), .D0(\wb_dati_7_0_1[6] ), .C0(N_621), 
-    .A0(N_627), .DI1(\wb_dati_7[7] ), .DI0(\wb_dati_7[6] ), 
-    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[6] ), 
-    .Q0(\wb_dati[6] ), .F1(\wb_dati_7[7] ), .Q1(\wb_dati[7] ));
-  SLICE_44 SLICE_44( .D1(\FS[11] ), .C1(\FS[12] ), .A1(\FS[13] ), 
-    .D0(\FS[14] ), .C0(wb_reqc_1), .B0(\S[3] ), .A0(N_397), .DI0(wb_reqc_i), 
-    .CE(wb_adr_0_sqmuxa_i), .LSR(\S[2] ), .CLK(C14M_c), .F0(wb_reqc_i), 
-    .Q0(wb_req), .F1(N_397));
-  SLICE_45 SLICE_45( .C1(\FS[14] ), .B1(wb_ack), .C0(\FS[14] ), .B0(\FS[15] ), 
-    .DI0(wb_rst8), .LSR(\S_RNII9DO1[1] ), .CLK(C14M_c), .F0(wb_rst8), 
-    .Q0(wb_rst), .F1(N_586));
-  SLICE_46 SLICE_46( .D1(\FS[8] ), .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[12] ), 
-    .D0(\FS[13] ), .C0(N_584), .B0(N_475), .A0(wb_we_7_iv_0_0_0_1), 
-    .DI0(wb_we_RNO), .CE(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), .CLK(C14M_c), 
-    .F0(wb_we_RNO), .Q0(wb_we), .F1(N_584));
-  SLICE_47 SLICE_47( .D1(N_255), .C1(\S_RNII9DO1[1] ), .B1(\RWBank[6] ), 
-    .A1(\S[0] ), .D0(\S[3] ), .C0(\S[0] ), .B0(\S[2] ), .A0(\S[1] ), 
-    .F0(\S_RNII9DO1[1] ), .F1(N_358_i));
-  SLICE_48 SLICE_48( .D1(\S[2] ), .C1(\S[1] ), .B1(\S[0] ), .A1(\S[3] ), 
-    .D0(N_254), .C0(Vout3), .B0(N_635), .A0(\S[0] ), .F0(nCAS_s_i_tz_0), 
-    .F1(Vout3));
-  SLICE_49 SLICE_49( .D1(un1_CS_0_sqmuxa_0_0_a2_1_4), .C1(\CS[0] ), 
-    .B1(\Din_c[6] ), .A1(RWSel), .D0(\CS[1] ), .C0(N_327), .B0(\CS[2] ), 
-    .A0(RWSel), .F0(un1_CS_0_sqmuxa_0_0_0), .F1(N_327));
-  SLICE_50 SLICE_50( .D1(\FS[8] ), .C1(\FS[10] ), .B1(\FS[9] ), .A1(\FS[11] ), 
-    .D0(\wb_dati_7_0_a2_0_1[7] ), .C0(N_579), .B0(\FS[9] ), .A0(N_621), 
-    .F0(\wb_dati_7_0_RNO[7] ), .F1(\wb_dati_7_0_a2_0_1[7] ));
-  SLICE_51 SLICE_51( .D1(\S[2] ), .C1(\S[3] ), .B1(wb_reqc_1), 
-    .A1(CKE_6_iv_i_a2_0), .D0(N_489), .C0(\S[3] ), .B0(CKE_6_iv_i_0_1), 
-    .A0(\FS[15] ), .F0(CKE_6_iv_i_0), .F1(CKE_6_iv_i_0_1));
-  SLICE_52 SLICE_52( .D1(N_449), .C1(\FS[0] ), .B1(N_300), .A1(wb_req), 
-    .D0(N_449), .C0(N_586), .B0(N_365), .A0(N_364), .F0(N_104), .F1(N_365));
-  SLICE_53 SLICE_53( .D1(RWSel), .C1(\FS[15] ), .B1(\S[2] ), .A1(\S[3] ), 
-    .D0(CmdExecMXO2), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .B0(\S[2] ), 
-    .A0(wb_reqc_1), .F0(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), 
-    .F1(\un1_wb_adr_0_sqmuxa_2_1[0] ));
-  SLICE_54 SLICE_54( .D1(\Din_c[1] ), .C1(\Din_c[0] ), .B1(\Din_c[2] ), 
-    .A1(\CS[1] ), .D0(\Din_c[1] ), .C0(N_623), .B0(N_616), .A0(\CS[2] ), 
-    .F0(N_279), .F1(N_623));
-  SLICE_55 SLICE_55( .D1(N_633), .C1(N_264), .B1(\FS[5] ), .A1(\FS[4] ), 
-    .D0(\FS[2] ), .C0(\FS[1] ), .B0(\FS[5] ), .A0(\FS[3] ), .F0(N_633), 
-    .F1(N_570));
-  SLICE_56 SLICE_56( .D1(\FS[14] ), .C1(\S_RNII9DO1[1] ), .A1(\FS[15] ), 
-    .C0(\FS[12] ), .B0(N_452), .A0(\FS[13] ), .F0(N_621), .F1(N_452));
-  SLICE_57 SLICE_57( .D1(\S_RNII9DO1_0[1] ), .C1(RWSel), .B1(wb_ack), 
-    .A1(CmdExecMXO2), .D0(\S[2] ), .C0(\S[3] ), .B0(\S[0] ), .A0(\S[1] ), 
-    .F0(\S_RNII9DO1_0[1] ), .F1(N_364));
-  SLICE_58 SLICE_58( .D1(\FS[12] ), .C1(\wb_dati_7_0_a2_2_1[3] ), .B1(N_455), 
-    .A1(N_644), .D0(\FS[10] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[11] ), 
-    .F0(\wb_dati_7_0_a2_2_1[3] ), .F1(\wb_dati_7_0_2[3] ));
-  SLICE_59 SLICE_59( .D1(\RWBank[6] ), .C1(nCS61), .B1(\S_RNII9DO1[1] ), 
-    .A1(DQML_s_i_a2_0), .D0(\S[3] ), .C0(\S[0] ), .B0(\S[1] ), .A0(\S[2] ), 
-    .F0(DQML_s_i_a2_0), .F1(N_28_i));
-  SLICE_60 SLICE_60( .D1(wb_adr_7_5_214_a2_2_0), .C1(N_569), .B1(N_577), 
-    .A1(N_475), .D0(\FS[10] ), .C0(\FS[12] ), .A0(\FS[13] ), 
-    .F0(wb_adr_7_5_214_a2_2_0), .F1(wb_adr_7_5_214_0_1));
-  SLICE_61 SLICE_61( .D1(\FS[13] ), .C1(N_634), .B1(\FS[12] ), .D0(\FS[11] ), 
-    .C0(\FS[8] ), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_634), 
-    .F1(\wb_dati_7_0_a2_2_0[1] ));
-  SLICE_62 SLICE_62( .D1(N_265_i), .C1(\FS[12] ), .B1(N_475), .A1(\FS[11] ), 
-    .D0(\FS[10] ), .B0(\FS[9] ), .A0(\FS[8] ), .F0(N_265_i), .F1(N_388));
-  SLICE_63 SLICE_63( .D1(\FS[6] ), .C1(N_264), .B1(\FS[7] ), .A1(N_254), 
-    .C0(\FS[1] ), .B0(\FS[3] ), .A0(\FS[2] ), .F0(N_264), .F1(N_300));
-  SLICE_64 SLICE_64( .C1(\FS[8] ), .B1(\FS[9] ), .A1(\FS[11] ), .D0(N_577), 
-    .C0(wb_ack), .B0(\FS[10] ), .A0(\FS[12] ), 
-    .F0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .F1(N_577));
-  SLICE_65 SLICE_65( .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[10] ), 
-    .C0(\FS[12] ), .B0(\wb_dati_7_0_a2_0[6] ), .A0(\FS[13] ), 
-    .F0(\wb_dati_7_0_a2_4_0[7] ), .F1(\wb_dati_7_0_a2_0[6] ));
-  SLICE_66 SLICE_66( .B1(\FS[14] ), .A1(\S[2] ), .D0(\FS[13] ), .C0(\FS[11] ), 
-    .B0(N_475), .A0(\FS[12] ), .F0(N_393), .F1(N_475));
-  SLICE_67 SLICE_67( .D1(\S[1] ), .C1(\S[0] ), .D0(\S[3] ), .C0(wb_reqc_1), 
-    .B0(RWSel), .A0(\S[2] ), .F0(LEDEN13), .F1(wb_reqc_1));
-  SLICE_68 SLICE_68( .D1(\wb_adr[3] ), .C1(N_627), .B1(N_455), .A1(\S[2] ), 
-    .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ), .A0(\FS[8] ), .F0(N_627), 
-    .F1(\wb_dati_7_0_0[3] ));
-  SLICE_69 SLICE_69( .D1(nCAS_0_sqmuxa), .C1(N_639), .B1(\RWBank[2] ), 
-    .A1(N_255), .D0(\S[0] ), .C0(\S[3] ), .B0(\S[2] ), .A0(\S[1] ), .F0(N_639), 
-    .F1(\RA_42[10] ));
-  SLICE_70 SLICE_70( .D1(\FS[12] ), .C1(N_627), .B1(N_455), .A1(N_644), 
-    .D0(\FS[10] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[11] ), .F0(N_644), 
-    .F1(N_345));
-  SLICE_71 SLICE_71( .D1(nCS61), .C1(N_633), .B1(\FS[4] ), .A1(N_640), 
-    .D0(\S[1] ), .C0(\S[0] ), .B0(\S[3] ), .A0(\S[2] ), .F0(nCS61), 
-    .F1(un1_nCS61_1_i));
-  SLICE_72 SLICE_72( .D1(\FS[5] ), .C1(N_449), .B1(Ready_0_sqmuxa_0_a2_6_a2_2), 
-    .A1(\FS[3] ), .D0(\S[3] ), .C0(wb_reqc_1), .B0(\FS[15] ), .A0(\S[2] ), 
-    .F0(N_449), .F1(Ready_0_sqmuxa_0_a2_6_a2_4));
-  SLICE_73 SLICE_73( .D1(N_562), .C1(N_455), .B1(\FS[12] ), .A1(\FS[11] ), 
-    .D0(\FS[13] ), .C0(\FS[14] ), .B0(\S_RNII9DO1[1] ), .A0(\FS[15] ), 
-    .F0(N_455), .F1(N_377));
-  SLICE_74 SLICE_74( .D1(N_484), .C1(\FS[11] ), .B1(\FS[9] ), .D0(\FS[10] ), 
-    .C0(\FS[12] ), .B0(N_642), .A0(\FS[13] ), .F0(N_346), .F1(N_642));
-  SLICE_75 SLICE_75( .D1(\FS[7] ), .C1(\FS[0] ), .B1(N_489), .A1(\FS[6] ), 
-    .C0(N_628), .B0(\S_RNII9DO1[1] ), .A0(\FS[15] ), .F0(N_640), .F1(N_628));
-  SLICE_76 SLICE_76( .D1(\FS[4] ), .A1(\FS[5] ), .D0(N_254), .C0(N_449), 
-    .B0(N_628), .A0(N_264), .F0(nCAS_0_sqmuxa), .F1(N_254));
-  SLICE_77 SLICE_77( .D1(\CS[0] ), .C1(N_466), .A1(\Din_c[6] ), 
-    .D0(un1_CS_0_sqmuxa_0_0_3), .C0(un1_CS_0_sqmuxa_0_0_2), .B0(N_474), 
-    .A0(un1_CS_0_sqmuxa_0_0_a2_3_2), .F0(un1_CS_0_sqmuxa_i), .F1(N_474));
-  SLICE_78 SLICE_78( .D1(\FS[4] ), .A1(N_633), .D0(N_567), .C0(N_640), 
-    .B0(nCAS_s_i_tz_0), .A0(nCAS_0_sqmuxa), .F0(N_561_i), .F1(N_567));
-  SLICE_79 SLICE_79( .D1(\S[3] ), .C1(nEN80_c), .B1(\S[2] ), .A1(\S[1] ), 
-    .B0(nCS_6_u_i_0), .A0(N_559_1), .F0(N_559_i), .F1(nCS_6_u_i_0));
-  SLICE_80 SLICE_80( .D1(\S[3] ), .B1(\S[1] ), .A1(\S[2] ), .C0(\S[0] ), 
-    .B0(N_635), .A0(N_559_1), .F0(nRAS_2_iv_i), .F1(N_635));
-  SLICE_81 SLICE_81( .D1(\CS[0] ), .C1(\Din_c[6] ), .B1(\Din_c[4] ), 
-    .A1(\Din_c[3] ), .D0(un1_CS_0_sqmuxa_0_0_0), .C0(un1_CS_0_sqmuxa_0_0_a2_1), 
-    .B0(N_279), .A0(N_466), .F0(un1_CS_0_sqmuxa_0_0_2), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_1));
-  SLICE_82 SLICE_82( .D1(CO0_1), .C1(RWSel), .B1(\CmdTout[1] ), 
-    .A1(\CmdTout[2] ), .D0(N_461), .C0(N_328), .B0(N_330), 
-    .A0(\S_RNII9DO1_0[1] ), .F0(un1_CS_0_sqmuxa_0_0_3), .F1(N_461));
-  SLICE_83 SLICE_83( .D1(\FS[15] ), .C1(\S[0] ), .B1(\S[2] ), .A1(\S[3] ), 
-    .D0(N_570), .C0(nCS_6_u_i_a2_1), .B0(N_429), .A0(N_628), .F0(N_559_1), 
-    .F1(nCS_6_u_i_a2_1));
-  SLICE_84 SLICE_84( .D1(\FS[10] ), .C1(\FS[12] ), .B1(N_455), 
-    .A1(\wb_dati_7_0_a2_0[6] ), .D0(\wb_adr[6] ), .C0(N_346), .B0(\S[2] ), 
-    .A0(N_351), .F0(\wb_dati_7_0_1[6] ), .F1(N_351));
-  SLICE_85 SLICE_85( .D1(\wb_adr_7_0_a2_5_0[0] ), .C1(N_579), .B1(N_452), 
-    .A1(\FS[8] ), .D0(N_378), .C0(N_377), .B0(\wb_adr_7_0_1[0] ), 
-    .A0(\wb_adr_7_0_0[0] ), .F0(\wb_adr_7_0_4[0] ), .F1(\wb_adr_7_0_1[0] ));
-  SLICE_86 SLICE_86( .D1(\FS[15] ), .C1(\S_RNII9DO1[1] ), .B1(\FS[14] ), 
-    .A1(\FS[8] ), .D0(CmdLEDSet), .C0(N_484), .B0(LEDEN13), 
-    .A0(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ), 
-    .F0(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .F1(N_484));
-  SLICE_87 SLICE_87( .D1(RWSel), .C1(un1_CS_0_sqmuxa_0_0_a2_4_2), 
-    .B1(\Din_c[6] ), .A1(\CS[0] ), .C0(un1_CS_0_sqmuxa_0_0_a2_4_4), 
-    .B0(\CS[2] ), .A0(\CS[1] ), .F0(N_330), .F1(un1_CS_0_sqmuxa_0_0_a2_4_4));
-  SLICE_88 SLICE_88( .D1(\FS[12] ), .A1(\FS[13] ), .D0(N_336), .C0(N_452), 
-    .B0(N_634), .A0(N_569), .F0(\wb_dati_7_0_o2_0[2] ), .F1(N_569));
-  SLICE_89 SLICE_89( .D1(\FS[10] ), .A1(\FS[11] ), .D0(N_455), .C0(\FS[8] ), 
-    .B0(\FS[9] ), .A0(N_579), .F0(N_378), .F1(N_579));
-  SLICE_90 SLICE_90( .D1(\FS[10] ), .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[13] ), 
-    .C0(N_565), .B0(N_484), .A0(\FS[12] ), .F0(N_336), .F1(N_565));
-  SLICE_91 SLICE_91( .D1(\CS[0] ), .C1(\Din_c[6] ), .B1(\CS[2] ), 
-    .A1(un1_CS_0_sqmuxa_0_0_a2_2_2), .C0(RWSel), 
-    .B0(un1_CS_0_sqmuxa_0_0_a2_2_4), .A0(\Din_c[7] ), .F0(N_328), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_2_4));
-  SLICE_92 SLICE_92( .D1(\FS[11] ), .C1(\FS[13] ), .B1(N_562), .A1(\FS[12] ), 
-    .D0(N_452), .C0(\wb_adr_7_0_a2_0[0] ), .B0(\S[2] ), .A0(\Din_c[0] ), 
-    .F0(\wb_adr_7_0_0[0] ), .F1(\wb_adr_7_0_a2_0[0] ));
-  SLICE_93 SLICE_93( .D1(N_616), .C1(\Din_c[5] ), .B1(\Din_c[4] ), 
-    .A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[3] ), 
-    .B0(un1_CS_0_sqmuxa_0_0_a2_1_2), .A0(\CS[1] ), 
-    .F0(un1_CS_0_sqmuxa_0_0_a2_1_4), .F1(un1_CS_0_sqmuxa_0_0_a2_1_2));
-  SLICE_94 SLICE_94( .D1(\Din_c[3] ), .C1(\Din_c[0] ), .B1(\Din_c[2] ), 
-    .A1(\Din_c[1] ), .D0(\CS[1] ), .C0(un1_CS_0_sqmuxa_0_0_a2_3_0), 
-    .B0(\Din_c[4] ), .A0(\CS[2] ), .F0(un1_CS_0_sqmuxa_0_0_a2_3_2), 
-    .F1(un1_CS_0_sqmuxa_0_0_a2_3_0));
-  SLICE_95 SLICE_95( .D1(N_475), .C1(N_577), .B1(\FS[10] ), .A1(\FS[12] ), 
-    .D0(N_393), .C0(N_394), .B0(\S[2] ), .A0(\Din_c[0] ), 
-    .F0(wb_we_7_iv_0_0_0_1), .F1(N_394));
-  SLICE_96 SLICE_96( .D1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), .D0(\RWBank[0] ), 
-    .C0(N_255), .B0(\S[0] ), .A0(\RWBank[7] ), .F0(N_49_i), .F1(N_255));
-  SLICE_97 SLICE_97( .D1(\FS[10] ), .A1(\FS[12] ), .D0(\FS[14] ), .C0(N_577), 
-    .B0(N_456), .A0(\FS[13] ), .F0(N_489), .F1(N_456));
-  SLICE_98 SLICE_98( .D1(\Din_c[0] ), .C1(\Din_c[3] ), .B1(\Din_c[2] ), 
-    .D0(N_477), .C0(\Din_c[7] ), .B0(N_626), .A0(\Din_c[5] ), 
-    .F0(un1_CS_0_sqmuxa_0_0_a2_4_2), .F1(N_626));
-  SLICE_99 SLICE_99( .D1(\Din_c[3] ), .B1(\Din_c[2] ), .D0(N_477), .C0(N_478), 
-    .B0(\Din_c[5] ), .A0(\Din_c[0] ), .F0(un1_CS_0_sqmuxa_0_0_a2_2_2), 
-    .F1(N_478));
-  SLICE_100 SLICE_100( .C1(\Din_c[3] ), .B1(\Din_c[0] ), .A1(\Din_c[2] ), 
-    .D0(\Din_c[1] ), .C0(\Din_c[4] ), .B0(N_629), 
-    .F0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), .F1(N_629));
-  SLICE_101 SLICE_101( .D1(\S[1] ), .C1(\S[0] ), .B1(\S[2] ), .A1(\S[3] ), 
-    .D0(\S[1] ), .C0(\S[0] ), .B0(\S[2] ), .A0(\S[3] ), .F0(\S_RNII9DO1_1[1] ), 
-    .F1(N_566_i));
-  SLICE_102 SLICE_102( .D1(\S[2] ), .C1(\S[0] ), .B1(\S[1] ), .A1(\S[3] ), 
-    .D0(\S[2] ), .C0(\RWBank[4] ), .B0(\S[1] ), .A0(\S[3] ), .F0(\BA_4[0] ), 
-    .F1(\S_s_0_1[0] ));
-  SLICE_103 SLICE_103( .D1(\S[3] ), .C1(wb_reqc_1), .B1(\RWBank[3] ), 
-    .A1(\S[2] ), .D0(\S[3] ), .C0(\FS[15] ), .B0(wb_reqc_1), .A0(\S[2] ), 
-    .F0(wb_adr_0_sqmuxa_i), .F1(\RA_42[11] ));
-  SLICE_104 SLICE_104( .D1(\FS[11] ), .C1(N_621), .B1(\FS[9] ), .A1(\FS[8] ), 
-    .D0(\FS[11] ), .C0(N_621), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_376), 
-    .F1(N_349));
-  SLICE_105 SLICE_105( .D1(N_569), .C1(wb_ack), .B1(\FS[9] ), .A1(N_579), 
-    .D0(N_569), .C0(N_484), .B0(\FS[9] ), .A0(N_579), .F0(N_424), 
-    .F1(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ));
-  SLICE_106 SLICE_106( .C1(\S[1] ), .B1(\S[0] ), .C0(\S[1] ), .B0(\S[0] ), 
-    .A0(nEN80_c), .F0(CKE_6_iv_i_a2_0), .F1(N_575));
-  SLICE_107 SLICE_107( .D1(\S[3] ), .C1(\S[2] ), .D0(\S[3] ), .C0(\S[2] ), 
-    .B0(\RWBank[5] ), .A0(\S[1] ), .F0(\BA_4[1] ), .F1(N_572));
-  SLICE_108 SLICE_108( .C1(\FS[9] ), .B1(\FS[12] ), .A1(\FS[10] ), .D0(N_642), 
-    .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ), .F0(N_422), 
-    .F1(\wb_adr_7_0_a2_5_0[0] ));
-  SLICE_109 SLICE_109( .D1(\S[2] ), .C1(\wb_adr[7] ), .B1(N_452), 
-    .A1(\wb_dati_7_0_a2_4_0[7] ), .D0(\S[2] ), .C0(\wb_adr[1] ), .B0(N_452), 
-    .A0(\wb_dati_7_0_a2_2_0[1] ), .F0(\wb_dati_7_0_0[1] ), 
-    .F1(\wb_dati_7_0_0[7] ));
-  SLICE_110 SLICE_110( .D1(\S[3] ), .C1(wb_reqc_1), .B1(\S[2] ), 
-    .A1(\RWBank[1] ), .D0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .C0(wb_reqc_1), 
-    .B0(\S[2] ), .A0(CmdBitbangMXO2), .F0(\un1_wb_adr_0_sqmuxa_2_i[0] ), 
-    .F1(N_59_i));
-  SLICE_111 SLICE_111( .D1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[5] ), .D0(\S[3] ), 
-    .B0(\S[0] ), .A0(\Ain_c[4] ), .F0(N_551_i), .F1(\RA_42_3_0[5] ));
-  SLICE_112 SLICE_112( .D1(\S[0] ), .C1(N_254), .B1(\S[1] ), .A1(\S[3] ), 
-    .C0(\Ain_c[6] ), .B0(\S[0] ), .A0(\S[3] ), .F0(N_550_i), .F1(N_429));
-  SLICE_113 SLICE_113( .C1(\S[0] ), .B1(\Ain_c[2] ), .A1(\S[3] ), .C0(\S[0] ), 
-    .B0(\Ain_c[7] ), .A0(\S[3] ), .F0(N_549_i), .F1(N_553_i));
-  SLICE_114 SLICE_114( .D1(\S[2] ), .C1(N_634), .B1(N_455), .A1(\wb_adr[4] ), 
-    .D0(N_455), .C0(CmdRWMaskSet), .B0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), 
-    .A0(LEDEN13), .F0(N_88), .F1(\wb_dati_7_0_0[4] ));
-  SLICE_115 SLICE_115( .B1(nEN80_c), .A1(nWE80_c), .D0(un1_nCS61_1_i), 
-    .C0(nCAS_0_sqmuxa), .B0(\S[0] ), .A0(nWE80_c), .F0(nRWE_r_0), .F1(RDOE_i));
-  SLICE_116 SLICE_116( .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[11] ), .C0(N_456), 
-    .B0(\FS[9] ), .A0(\FS[13] ), .F0(\wb_dati_7_0_a2_1[0] ), .F1(N_562));
-  SLICE_117 SLICE_117( .D1(CmdSetRWBankFFMXO2), .C1(LEDEN), 
-    .B1(CmdSetRWBankFFLED), .A1(CmdLEDGet), .C0(LEDEN), .A0(nEN80_c), 
-    .F0(LED_c), .F1(N_591));
-  SLICE_118 SLICE_118( .D1(\Din_c[4] ), .C1(\Din_c[1] ), .B0(\Din_c[2] ), 
-    .A0(\Din_c[0] ), .F0(N_616), .F1(N_477));
-  SLICE_119 SLICE_119( .D0(\FS[1] ), .C0(\FS[0] ), .B0(\FS[2] ), .A0(\FS[4] ), 
-    .F0(Ready_0_sqmuxa_0_a2_6_a2_2));
-  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(\Din_c[0] ), 
+  SLICE_9 SLICE_9( .D1(\S[1] ), .C1(N_551), .B1(\FS[15] ), .A1(\S[0] ), 
+    .D0(\ram2e_ufm/CKE_7 ), .C0(N_551), .B0(\S[1] ), .A0(\S[0] ), 
+    .DI0(CKE_7_RNIS77M1), .CLK(C14M_c), .F0(CKE_7_RNIS77M1), .Q0(CKE), 
+    .F1(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ));
+  SLICE_10 SLICE_10( .D0(RWSel), .A0(CO0_0), .DI0(\CmdTout_3[0] ), 
+    .CE(N_185_i), .CLK(C14M_c), .F0(\CmdTout_3[0] ), .Q0(CO0_0), .F1(GND));
+  SLICE_11 SLICE_11( .B1(CO0_1), .A1(\RC[2] ), .D0(\RC[1] ), .B0(CO0_1), 
+    .A0(\RC[2] ), .DI0(N_360_i), .CE(RC12), .CLK(C14M_c), .F0(N_360_i), 
+    .Q0(CO0_1), .F1(\ram2e_ufm/N_821 ));
+  SLICE_12 SLICE_12( .D1(\ram2e_ufm/SUM1_0_0 ), .C1(\ram2e_ufm/SUM0_i_a3_4_0 ), 
+    .B1(\ram2e_ufm/N_886 ), .A1(\ram2e_ufm/N_215 ), .D0(\CS[1] ), 
+    .C0(\ram2e_ufm/SUM0_i_4 ), .B0(\ram2e_ufm/N_215 ), .A0(\CS[2] ), 
+    .DI1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .DI0(N_547_i), 
+    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_547_i), .Q0(\CS[0] ), 
+    .F1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .Q1(\CS[1] ));
+  SLICE_13 SLICE_13( .D1(\ram2e_ufm/N_234 ), .C1(\ram2e_ufm/N_215 ), 
+    .B1(\CS[1] ), .A1(\CS[2] ), .D0(\ram2e_ufm/N_234 ), .C0(\ram2e_ufm/N_215 ), 
+    .B0(\CS[1] ), .A0(\CS[2] ), .DI0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), 
+    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), 
+    .F0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), .Q0(\CS[2] ), 
+    .F1(\ram2e_ufm/SUM1_0_0 ));
+  SLICE_14 SLICE_14( .C1(\ram2e_ufm/N_800 ), .B1(\Din_c[5] ), .A1(\Din_c[3] ), 
+    .D0(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ), .C0(\ram2e_ufm/N_847 ), 
+    .B0(\Din_c[1] ), .A0(\Din_c[2] ), .DI0(CmdLEDGet_3), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(CmdLEDGet_3), .Q0(CmdLEDGet), .F1(\ram2e_ufm/N_847 ));
+  SLICE_15 SLICE_15( .C1(\Din_c[7] ), .B1(\CS[2] ), .A1(\Din_c[1] ), 
+    .D0(\ram2e_ufm/N_883 ), .C0(\Din_c[7] ), .B0(\Din_c[4] ), .A0(\Din_c[1] ), 
+    .DI0(CmdLEDSet_3), .CE(N_187_i), .CLK(C14M_c), .F0(CmdLEDSet_3), 
+    .Q0(CmdLEDSet), .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ));
+  SLICE_16 SLICE_16( .D1(\Din_c[1] ), .C1(\Din_c[7] ), .B1(\Din_c[3] ), 
+    .A1(\Din_c[5] ), .D0(\Din_c[1] ), .C0(\ram2e_ufm/N_883 ), .B0(\Din_c[7] ), 
+    .A0(\Din_c[4] ), .DI0(CmdRWMaskSet_3), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(CmdRWMaskSet_3), .Q0(CmdRWMaskSet), .F1(\ram2e_ufm/N_850 ));
+  SLICE_17 SLICE_17( .C1(\ram2e_ufm/N_847 ), .B1(\Din_c[0] ), .A1(\Din_c[2] ), 
+    .D0(\Din_c[1] ), .C0(\ram2e_ufm/N_883 ), .B0(\Din_c[7] ), .A0(\Din_c[4] ), 
+    .DI0(CmdSetRWBankFFLED_4), .CE(N_187_i), .CLK(C14M_c), 
+    .F0(CmdSetRWBankFFLED_4), .Q0(CmdSetRWBankFFLED), .F1(\ram2e_ufm/N_883 ));
+  SLICE_18 SLICE_18( .D1(\CmdTout[1] ), .C1(CO0_0), .B1(RWSel), 
+    .A1(\CmdTout[2] ), .D0(CO0_0), .B0(RWSel), .A0(\CmdTout[1] ), 
+    .DI1(N_369_i), .DI0(N_368_i), .CE(N_185_i), .CLK(C14M_c), .F0(N_368_i), 
+    .Q0(\CmdTout[1] ), .F1(N_369_i), .Q1(\CmdTout[2] ));
+  SLICE_19 SLICE_19( .C1(\CS[1] ), .A1(\CS[2] ), .C0(\ram2e_ufm/N_186 ), 
+    .A0(\RA[1] ), .M0(\S[3] ), .LSR(N_1080_0), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_660 ), .Q0(DOEEN), .F1(\ram2e_ufm/N_193 ));
+  SLICE_20 SLICE_20( .D1(\ram2e_ufm/N_182 ), .C1(\ram2e_ufm/N_660 ), 
+    .B1(\Ain_c[1] ), .A1(\ram2e_ufm/N_659 ), .D0(\ram2e_ufm/N_801 ), 
+    .C0(\ram2e_ufm/N_684 ), .B0(\FS[7] ), .A0(\ram2e_ufm/RA_35_0_0_1[0] ), 
+    .DI1(N_223), .DI0(\RA_35[0] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[0] ), 
+    .Q0(\RA[0] ), .F1(N_223), .Q1(\RA[1] ));
+  SLICE_21 SLICE_21( .C1(\ram2e_ufm/N_801 ), .B1(\ram2e_ufm/RA_35_0_0_0[3] ), 
+    .A1(\FS[10] ), .D0(\ram2e_ufm/N_680 ), .C0(\ram2e_ufm/N_679 ), 
+    .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[2] ), .DI1(\RA_35[3] ), 
+    .DI0(\RA_35[2] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[2] ), .Q0(\RA[2] ), 
+    .F1(\RA_35[3] ), .Q1(\RA[3] ));
+  SLICE_22 SLICE_22( .D1(\ram2e_ufm/N_621 ), .C1(\Ain_c[5] ), 
+    .B1(\ram2e_ufm/RA_35_0_0_0[5] ), .A1(\ram2e_ufm/N_182 ), 
+    .C0(\ram2e_ufm/RA_35_0_0_0[4] ), .B0(\FS[11] ), .A0(\ram2e_ufm/N_801 ), 
+    .DI1(\RA_35[5] ), .DI0(\RA_35[4] ), .CE(N_126), .CLK(C14M_c), 
+    .F0(\RA_35[4] ), .Q0(\RA[4] ), .F1(\RA_35[5] ), .Q1(\RA[5] ));
+  SLICE_23 SLICE_23( .C1(\ram2e_ufm/RA_35_0_0_0_0[7] ), .B1(\FS[14] ), 
+    .A1(\ram2e_ufm/N_801 ), .C0(\ram2e_ufm/RA_35_0_0_0_0[6] ), .B0(\FS[13] ), 
+    .A0(\ram2e_ufm/N_801 ), .DI1(\RA_35[7] ), .DI0(\RA_35[6] ), .CE(N_126), 
+    .CLK(C14M_c), .F0(\RA_35[6] ), .Q0(\RA[6] ), .F1(\RA_35[7] ), .Q1(\RA[7] ));
+  SLICE_24 SLICE_24( .D1(\ram2e_ufm/N_242 ), .B1(\ram2e_ufm/RA_35_0_0_0[9] ), 
+    .A1(\RA[9] ), .D0(\ram2e_ufm/N_699 ), .C0(\RA[8] ), .B0(\ram2e_ufm/N_698 ), 
+    .A0(\ram2e_ufm/N_221 ), .DI1(\RA_35[9] ), .DI0(un2_S_2_i_0_0_o3_RNIHFHN3), 
+    .CE(N_126), .CLK(C14M_c), .F0(un2_S_2_i_0_0_o3_RNIHFHN3), .Q0(\RA[8] ), 
+    .F1(\RA_35[9] ), .Q1(\RA[9] ));
+  SLICE_25 SLICE_25( .D1(\ram2e_ufm/N_242 ), .C1(\RWBank[4] ), 
+    .B1(\ram2e_ufm/N_845 ), .A1(\RA[11] ), .D0(\ram2e_ufm/N_628 ), 
+    .C0(\ram2e_ufm/RA_35_2_0_0[10] ), .B0(\ram2e_ufm/N_624 ), 
+    .A0(\ram2e_ufm/N_627 ), .DI1(\RA_35[11] ), .DI0(\RA_35[10] ), .CE(N_126), 
+    .CLK(C14M_c), .F0(\RA_35[10] ), .Q0(\RA[10] ), .F1(\RA_35[11] ), 
+    .Q1(\RA[11] ));
+  SLICE_26 SLICE_26( .D1(CO0_1), .B1(\RC[1] ), .A1(\RC[2] ), .D0(CO0_1), 
+    .B0(\RC[1] ), .A0(\RC[2] ), .DI1(\RC_3[2] ), .DI0(\RC_3[1] ), .CE(RC12), 
+    .CLK(C14M_c), .F0(\RC_3[1] ), .Q0(\RC[1] ), .F1(\RC_3[2] ), .Q1(\RC[2] ));
+  SLICE_27 SLICE_27( .D1(\ram2e_ufm/RWMask[1] ), .B1(\ram2e_ufm/N_188 ), 
+    .A1(\Din_c[1] ), .C0(\ram2e_ufm/RWMask[0] ), .B0(\ram2e_ufm/N_188 ), 
+    .A0(\Din_c[0] ), .DI1(\RWBank_3[1] ), .DI0(\RWBank_3[0] ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\RWBank_3[0] ), .Q0(\RWBank[0] ), .F1(\RWBank_3[1] ), 
+    .Q1(\RWBank[1] ));
+  SLICE_28 SLICE_28( .C1(\ram2e_ufm/RWMask[3] ), .B1(\Din_c[3] ), 
+    .A1(\ram2e_ufm/N_188 ), .D0(\Din_c[2] ), .C0(\ram2e_ufm/RWMask[2] ), 
+    .A0(\ram2e_ufm/N_188 ), .DI1(\RWBank_3[3] ), .DI0(\RWBank_3[2] ), 
+    .CE(N_187_i), .CLK(C14M_c), .F0(\RWBank_3[2] ), .Q0(\RWBank[2] ), 
+    .F1(\RWBank_3[3] ), .Q1(\RWBank[3] ));
+  SLICE_29 SLICE_29( .C1(\ram2e_ufm/RWMask[5] ), .B1(\ram2e_ufm/N_188 ), 
+    .A1(\Din_c[5] ), .C0(\ram2e_ufm/RWMask[4] ), .B0(\ram2e_ufm/N_188 ), 
+    .A0(\Din_c[4] ), .DI1(\RWBank_3[5] ), .DI0(\RWBank_3[4] ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\RWBank_3[4] ), .Q0(\RWBank[4] ), .F1(\RWBank_3[5] ), 
+    .Q1(\RWBank[5] ));
+  SLICE_30 SLICE_30( .D1(\ram2e_ufm/N_188 ), .B1(\Din_c[7] ), 
+    .A1(\ram2e_ufm/RWMask[7] ), .D0(\ram2e_ufm/N_188 ), .B0(\Din_c[6] ), 
+    .A0(\ram2e_ufm/RWMask[6] ), .DI1(\RWBank_3[7] ), .DI0(\RWBank_3[6] ), 
+    .CE(N_187_i), .CLK(C14M_c), .F0(\RWBank_3[6] ), .Q0(\RWBank[6] ), 
+    .F1(\RWBank_3[7] ), .Q1(\RWBank[7] ));
+  SLICE_31 SLICE_31( .D1(\RA[3] ), .C1(\ram2e_ufm/N_186 ), .B1(\Ain_c[3] ), 
+    .A1(\ram2e_ufm/N_182 ), .D0(\RA[3] ), .C0(nC07X_c), .B0(\RA[0] ), 
+    .A0(nWE_c), .DI0(RWSel_2), .CE(un9_VOEEN_0_a2_0_a3_0_a3), .CLK(C14M_c), 
+    .F0(RWSel_2), .Q0(RWSel), .F1(\ram2e_ufm/RA_35_0_0_0[3] ));
+  SLICE_32 SLICE_32( .D1(\ram2e_ufm/N_885 ), .C1(\ram2e_ufm/Ready3_0_a3_4 ), 
+    .B1(\ram2e_ufm/Ready3_0_a3_5 ), .A1(\ram2e_ufm/Ready3_0_a3_3 ), 
+    .C0(Ready3), .A0(Ready), .DI0(N_1026_0), .CLK(C14M_c), .F0(N_1026_0), 
+    .Q0(Ready), .F1(Ready3));
+  SLICE_33 SLICE_33( .D1(\ram2e_ufm/S_r_i_0_o2[1] ), .C1(\ram2e_ufm/N_194 ), 
+    .B1(\ram2e_ufm/N_271 ), .A1(S_1), .D0(\S[1] ), .C0(\ram2e_ufm/N_271 ), 
+    .B0(\ram2e_ufm/N_643 ), .A0(S_1), .DI1(N_362_i), .DI0(\S_s_0_0[0] ), 
+    .CLK(C14M_c), .F0(\S_s_0_0[0] ), .Q0(\S[0] ), .F1(N_362_i), .Q1(\S[1] ));
+  SLICE_34 SLICE_34( .D1(\S[2] ), .C1(\ram2e_ufm/N_194 ), .B1(S_1), 
+    .A1(\S[3] ), .D0(\S[2] ), .C0(\ram2e_ufm/N_194 ), .B0(S_1), .A0(\S[3] ), 
+    .DI1(N_372_i), .DI0(N_361_i), .CLK(C14M_c), .F0(N_361_i), .Q0(\S[2] ), 
+    .F1(N_372_i), .Q1(\S[3] ));
+  SLICE_35 SLICE_35( .D1(\S[1] ), .C1(\S[0] ), .B1(\FS[4] ), .A1(N_551), 
+    .D0(\S[2] ), .A0(\S[3] ), .DI0(N_551), .LSR(N_1078_0), .CLK(C14M_c), 
+    .F0(N_551), .Q0(VOEEN), .F1(BA_0_sqmuxa));
+  SLICE_36 SLICE_36( .D1(\S[1] ), .C1(\ram2e_ufm/N_285_i ), .B1(\S[0] ), 
+    .A1(\ram2e_ufm/N_804 ), .D0(\ram2e_ufm/N_641 ), .C0(\ram2e_ufm/N_640 ), 
+    .B0(\ram2e_ufm/N_872 ), .A0(nWE_c), .DI0(N_370_i), .CLK(C14M_c), 
+    .F0(N_370_i), .Q0(nCAS), .F1(\ram2e_ufm/N_872 ));
+  SLICE_37 SLICE_37( .D1(\S[0] ), .C1(\ram2e_ufm/N_804 ), 
+    .B1(\ram2e_ufm/N_285_i ), .A1(\S[1] ), .D0(\ram2e_ufm/N_616 ), 
+    .C0(\ram2e_ufm/N_615 ), .B0(\ram2e_ufm/N_617 ), 
+    .A0(\ram2e_ufm/nRAS_s_i_0_0 ), .DI0(N_358_i), .CLK(C14M_c), .F0(N_358_i), 
+    .Q0(nRAS), .F1(\ram2e_ufm/N_617 ));
+  SLICE_38 SLICE_38( .D1(\ram2e_ufm/N_226 ), .C1(\S[2] ), 
+    .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\ram2e_ufm/N_285_i ), 
+    .D0(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ), .C0(\ram2e_ufm/N_866 ), 
+    .B0(\ram2e_ufm/N_615 ), .A0(\ram2e_ufm/N_804 ), .DI0(N_359_i), 
+    .CLK(C14M_c), .F0(N_359_i), .Q0(nRWE), .F1(\ram2e_ufm/N_615 ));
+  ram2e_ufm_SLICE_39 \ram2e_ufm/SLICE_39 ( .D1(\Din_c[3] ), .C1(\Din_c[0] ), 
+    .B1(\Din_c[5] ), .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .D0(\Din_c[1] ), 
+    .C0(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ), .B0(\ram2e_ufm/N_800 ), 
+    .A0(\Din_c[2] ), .DI0(\ram2e_ufm/CmdBitbangMXO2_3 ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/CmdBitbangMXO2_3 ), 
+    .Q0(\ram2e_ufm/CmdBitbangMXO2 ), .F1(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ));
+  ram2e_ufm_SLICE_40 \ram2e_ufm/SLICE_40 ( .D1(\CS[1] ), .C1(\CS[0] ), 
+    .B1(\CS[2] ), .A1(\Din_c[6] ), .C0(\ram2e_ufm/N_800 ), 
+    .B0(\ram2e_ufm/N_851 ), .DI0(\ram2e_ufm/CmdExecMXO2_3 ), .CE(N_187_i), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/CmdExecMXO2_3 ), .Q0(\ram2e_ufm/CmdExecMXO2 ), 
+    .F1(\ram2e_ufm/N_800 ));
+  ram2e_ufm_SLICE_41 \ram2e_ufm/SLICE_41 ( .D1(\Din_c[4] ), .C1(\Din_c[0] ), 
+    .B1(\Din_c[2] ), .A1(\Din_c[1] ), .D0(\ram2e_ufm/N_800 ), 
+    .C0(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ), .B0(\Din_c[7] ), 
+    .A0(\ram2e_ufm/N_190 ), .DI0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), 
+    .CE(N_187_i), .CLK(C14M_c), .F0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), 
+    .Q0(\ram2e_ufm/CmdSetRWBankFFChip ), 
+    .F1(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ));
+  ram2e_ufm_SLICE_42 \ram2e_ufm/SLICE_42 ( .D1(\Din_c[2] ), .B1(\Din_c[6] ), 
+    .A1(\Din_c[0] ), .D0(\Din_c[0] ), .C0(\ram2e_ufm/wb_dato[0] ), .A0(\S[3] ), 
+    .DI0(\ram2e_ufm/N_295 ), .CE(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_295 ), .Q0(\ram2e_ufm/LEDEN ), 
+    .F1(\ram2e_ufm/N_212 ));
+  ram2e_ufm_SLICE_43 \ram2e_ufm/SLICE_43 ( .D1(\ram2e_ufm/wb_dato[1] ), 
+    .B1(\Din_c[1] ), .A1(\S[3] ), .D0(\Din_c[0] ), .C0(\ram2e_ufm/wb_dato[0] ), 
+    .A0(\S[3] ), .DI1(\ram2e_ufm/N_307_i ), .DI0(\ram2e_ufm/N_309_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_309_i ), .Q0(\ram2e_ufm/RWMask[0] ), 
+    .F1(\ram2e_ufm/N_307_i ), .Q1(\ram2e_ufm/RWMask[1] ));
+  ram2e_ufm_SLICE_44 \ram2e_ufm/SLICE_44 ( .D1(\ram2e_ufm/wb_dato[3] ), 
+    .B1(\Din_c[3] ), .A1(\S[3] ), .D0(\S[3] ), .C0(\ram2e_ufm/wb_dato[2] ), 
+    .B0(\Din_c[2] ), .DI1(\ram2e_ufm/N_302_i ), .DI0(\ram2e_ufm/N_304_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_304_i ), .Q0(\ram2e_ufm/RWMask[2] ), 
+    .F1(\ram2e_ufm/N_302_i ), .Q1(\ram2e_ufm/RWMask[3] ));
+  ram2e_ufm_SLICE_45 \ram2e_ufm/SLICE_45 ( .D1(\ram2e_ufm/wb_dato[5] ), 
+    .B1(\Din_c[5] ), .A1(\S[3] ), .D0(\ram2e_ufm/wb_dato[4] ), .C0(\Din_c[4] ), 
+    .A0(\S[3] ), .DI1(\ram2e_ufm/N_301_i ), .DI0(\ram2e_ufm/N_310_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_310_i ), .Q0(\ram2e_ufm/RWMask[4] ), 
+    .F1(\ram2e_ufm/N_301_i ), .Q1(\ram2e_ufm/RWMask[5] ));
+  ram2e_ufm_SLICE_46 \ram2e_ufm/SLICE_46 ( .D1(\ram2e_ufm/wb_dato[7] ), 
+    .B1(\Din_c[7] ), .A1(\S[3] ), .D0(\ram2e_ufm/wb_dato[6] ), .B0(\Din_c[6] ), 
+    .A0(\S[3] ), .DI1(\ram2e_ufm/N_296 ), .DI0(\ram2e_ufm/N_300_i ), 
+    .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_300_i ), .Q0(\ram2e_ufm/RWMask[6] ), 
+    .F1(\ram2e_ufm/N_296 ), .Q1(\ram2e_ufm/RWMask[7] ));
+  ram2e_ufm_SLICE_47 \ram2e_ufm/SLICE_47 ( .D1(\ram2e_ufm/wb_adr_7_5_41_0_1 ), 
+    .C1(\S[2] ), .B1(\ram2e_ufm/N_768 ), .A1(\Din_c[1] ), .D0(\FS[10] ), 
+    .C0(\ram2e_ufm/N_793 ), .B0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), 
+    .A0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .DI1(\ram2e_ufm/wb_adr_RNO[1] ), 
+    .DI0(\ram2e_ufm/wb_adr_7_i_i[0] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i[0] ), .Q0(\ram2e_ufm/wb_adr[0] ), 
+    .F1(\ram2e_ufm/wb_adr_RNO[1] ), .Q1(\ram2e_ufm/wb_adr[1] ));
+  ram2e_ufm_SLICE_48 \ram2e_ufm/SLICE_48 ( .B1(\S[2] ), .A1(\Din_c[3] ), 
+    .C0(\Din_c[2] ), .B0(\S[2] ), .DI1(\ram2e_ufm/N_268_i ), 
+    .DI0(\ram2e_ufm/N_80_i ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_80_i ), .Q0(\ram2e_ufm/wb_adr[2] ), 
+    .F1(\ram2e_ufm/N_268_i ), .Q1(\ram2e_ufm/wb_adr[3] ));
+  ram2e_ufm_SLICE_49 \ram2e_ufm/SLICE_49 ( .D1(\FS[14] ), .B1(\Din_c[5] ), 
+    .A1(\S[2] ), .D0(\FS[14] ), .C0(\Din_c[4] ), .A0(\S[2] ), 
+    .DI1(\ram2e_ufm/N_290 ), .DI0(\ram2e_ufm/N_294 ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/N_294 ), .Q0(\ram2e_ufm/wb_adr[4] ), .F1(\ram2e_ufm/N_290 ), 
+    .Q1(\ram2e_ufm/wb_adr[5] ));
+  ram2e_ufm_SLICE_50 \ram2e_ufm/SLICE_50 ( .B1(\Din_c[7] ), .A1(\S[2] ), 
+    .C0(\Din_c[6] ), .B0(\FS[14] ), .A0(\S[2] ), .DI1(\ram2e_ufm/N_267_i ), 
+    .DI0(\ram2e_ufm/N_284 ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/N_284 ), .Q0(\ram2e_ufm/wb_adr[6] ), 
+    .F1(\ram2e_ufm/N_267_i ), .Q1(\ram2e_ufm/wb_adr[7] ));
+  ram2e_ufm_SLICE_51 \ram2e_ufm/SLICE_51 ( .D1(\FS[14] ), 
+    .C1(\ram2e_ufm/wb_ack ), .B1(\FS[0] ), .A1(\ram2e_ufm/N_336 ), .D0(\S[3] ), 
+    .C0(\ram2e_ufm/N_687 ), .A0(\ram2e_ufm/CmdExecMXO2 ), 
+    .DI0(\ram2e_ufm/wb_cyc_stb_RNO ), 
+    .CE(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_cyc_stb_RNO ), .Q0(\ram2e_ufm/wb_cyc_stb ), 
+    .F1(\ram2e_ufm/N_687 ));
+  ram2e_ufm_SLICE_52 \ram2e_ufm/SLICE_52 ( .D1(\ram2e_ufm/N_849 ), 
+    .C1(\ram2e_ufm/wb_dati_7_0_0_0[1] ), .B1(\ram2e_ufm/N_611 ), 
+    .A1(\ram2e_ufm/N_793 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ), 
+    .C0(\ram2e_ufm/N_856 ), .B0(\ram2e_ufm/wb_adr[0] ), .A0(\S[2] ), 
+    .DI1(\ram2e_ufm/wb_dati_7[1] ), .DI0(\ram2e_ufm/wb_dati_7[0] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_dati_7[0] ), .Q0(\ram2e_ufm/wb_dati[0] ), 
+    .F1(\ram2e_ufm/wb_dati_7[1] ), .Q1(\ram2e_ufm/wb_dati[1] ));
+  ram2e_ufm_SLICE_53 \ram2e_ufm/SLICE_53 ( .D1(\ram2e_ufm/N_611 ), 
+    .C1(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .B1(\ram2e_ufm/N_783 ), 
+    .A1(\ram2e_ufm/N_849 ), .D0(\ram2e_ufm/N_760 ), 
+    .C0(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .B0(\ram2e_ufm/wb_adr[2] ), 
+    .A0(\S[2] ), .DI1(\ram2e_ufm/wb_dati_7[3] ), 
+    .DI0(\ram2e_ufm/wb_dati_7[2] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), 
+    .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[2] ), .Q0(\ram2e_ufm/wb_dati[2] ), 
+    .F1(\ram2e_ufm/wb_dati_7[3] ), .Q1(\ram2e_ufm/wb_dati[3] ));
+  ram2e_ufm_SLICE_54 \ram2e_ufm/SLICE_54 ( .D1(\ram2e_ufm/N_760 ), 
+    .C1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .B1(\ram2e_ufm/wb_adr[5] ), 
+    .A1(\S[2] ), .D0(\ram2e_ufm/N_760 ), .C0(\ram2e_ufm/N_757 ), 
+    .B0(\ram2e_ufm/N_763 ), .A0(\ram2e_ufm/wb_dati_7_0_0_0[4] ), 
+    .DI1(\ram2e_ufm/wb_dati_7[5] ), .DI0(\ram2e_ufm/wb_dati_7[4] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_dati_7[4] ), .Q0(\ram2e_ufm/wb_dati[4] ), 
+    .F1(\ram2e_ufm/wb_dati_7[5] ), .Q1(\ram2e_ufm/wb_dati[5] ));
+  ram2e_ufm_SLICE_55 \ram2e_ufm/SLICE_55 ( .D1(\ram2e_ufm/N_604 ), 
+    .C1(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), .B1(\ram2e_ufm/N_602 ), 
+    .A1(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), .C0(\ram2e_ufm/N_757 ), 
+    .B0(\ram2e_ufm/N_849 ), .A0(\ram2e_ufm/N_793 ), 
+    .DI1(\ram2e_ufm/wb_dati_7[7] ), .DI0(\ram2e_ufm/wb_dati_7[6] ), 
+    .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_dati_7[6] ), .Q0(\ram2e_ufm/wb_dati[6] ), 
+    .F1(\ram2e_ufm/wb_dati_7[7] ), .Q1(\ram2e_ufm/wb_dati[7] ));
+  ram2e_ufm_SLICE_56 \ram2e_ufm/SLICE_56 ( .D1(\S[0] ), .C1(\FS[14] ), 
+    .B1(\S[1] ), .A1(\S[3] ), .D0(\FS[12] ), .C0(\ram2e_ufm/wb_reqc_1 ), 
+    .B0(\FS[13] ), .A0(\FS[11] ), .DI0(\ram2e_ufm/wb_reqc_i ), 
+    .CE(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ), .LSR(\S[2] ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_reqc_i ), .Q0(\ram2e_ufm/wb_req ), 
+    .F1(\ram2e_ufm/wb_reqc_1 ));
+  ram2e_ufm_SLICE_57 \ram2e_ufm/SLICE_57 ( .D1(\FS[14] ), .C1(\FS[2] ), 
+    .B1(\FS[15] ), .A1(\FS[4] ), .D0(\FS[14] ), .B0(\FS[15] ), 
+    .DI0(\ram2e_ufm/wb_rst8 ), .LSR(\ram2e_ufm/wb_rst16_i ), .CLK(C14M_c), 
+    .F0(\ram2e_ufm/wb_rst8 ), .Q0(\ram2e_ufm/wb_rst ), 
+    .F1(\ram2e_ufm/Ready3_0_a3_4 ));
+  ram2e_ufm_SLICE_58 \ram2e_ufm/SLICE_58 ( 
+    .D1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), .C1(\FS[12] ), 
+    .B1(\ram2e_ufm/N_885 ), .A1(\ram2e_ufm/N_799 ), .D0(\FS[13] ), 
+    .C0(\ram2e_ufm/N_208 ), .B0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ), 
+    .A0(\ram2e_ufm/N_799 ), .DI0(\ram2e_ufm/wb_we_RNO ), 
+    .CE(\ram2e_ufm/wb_we_RNO_0 ), .CLK(C14M_c), .F0(\ram2e_ufm/wb_we_RNO ), 
+    .Q0(\ram2e_ufm/wb_we ), .F1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ));
+  ram2e_ufm_SUM0_i_m3_0_SLICE_59 \ram2e_ufm/SUM0_i_m3_0/SLICE_59 ( 
+    .D1(\CS[1] ), .B1(\Din_c[3] ), .A1(\Din_c[5] ), .D0(\Din_c[5] ), 
+    .B0(\Din_c[3] ), .A0(\Din_c[7] ), .M0(\Din_c[1] ), 
+    .OFX0(\ram2e_ufm/N_338 ));
+  ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 
+    \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60 ( .D1(\Din_c[6] ), .C1(\CS[0] ), 
+    .B1(\ram2e_ufm/N_193 ), .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), 
+    .C0(CO0_0), .B0(\CmdTout[2] ), .A0(\CmdTout[1] ), .M0(RWSel), 
+    .OFX0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ));
+  ram2e_ufm_CKE_7_SLICE_61 \ram2e_ufm/CKE_7/SLICE_61 ( .D1(\ram2e_ufm/N_817 ), 
+    .C1(\ram2e_ufm/N_821 ), .A1(\RC[1] ), .D0(nWE_c), .B0(\S[1] ), 
+    .A0(\ram2e_ufm/N_804 ), .M0(\ram2e_ufm/CKE_7_sm0 ), 
+    .OFX0(\ram2e_ufm/CKE_7 ));
+  ram2e_ufm_SLICE_62 \ram2e_ufm/SLICE_62 ( .D1(\Din_c[6] ), .C1(\CS[1] ), 
+    .B1(\ram2e_ufm/N_851 ), .A1(\CS[2] ), .D0(\ram2e_ufm/SUM0_i_a3_4_0 ), 
+    .C0(\CS[1] ), .B0(\ram2e_ufm/N_234 ), .A0(\CS[2] ), 
+    .F0(\ram2e_ufm/N_720_tz ), .F1(\ram2e_ufm/SUM0_i_a3_4_0 ));
+  ram2e_ufm_SLICE_63 \ram2e_ufm/SLICE_63 ( .D1(\CS[0] ), 
+    .C1(\ram2e_ufm/SUM0_i_0 ), .B1(\CS[2] ), .A1(\ram2e_ufm/N_350 ), 
+    .D0(\ram2e_ufm/N_187 ), .C0(\ram2e_ufm/SUM0_i_3 ), 
+    .B0(\ram2e_ufm/SUM0_i_1 ), .A0(\CS[0] ), .F0(\ram2e_ufm/SUM0_i_4 ), 
+    .F1(\ram2e_ufm/SUM0_i_1 ));
+  ram2e_ufm_SLICE_64 \ram2e_ufm/SLICE_64 ( .C1(\FS[11] ), .B1(\FS[9] ), 
+    .A1(\ram2e_ufm/N_793 ), .D0(\FS[13] ), .C0(\ram2e_ufm/N_856 ), 
+    .B0(\ram2e_ufm/N_755 ), .A0(\FS[11] ), .F0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), 
+    .F1(\ram2e_ufm/N_755 ));
+  ram2e_ufm_SLICE_65 \ram2e_ufm/SLICE_65 ( .D1(\CS[0] ), .C1(\Din_c[0] ), 
+    .B1(\Din_c[6] ), .A1(\ram2e_ufm/N_193 ), .D0(\CS[0] ), 
+    .C0(\ram2e_ufm/N_735 ), .B0(\CS[1] ), .A0(\ram2e_ufm/N_345 ), 
+    .F0(\ram2e_ufm/SUM0_i_0 ), .F1(\ram2e_ufm/N_735 ));
+  ram2e_ufm_SLICE_66 \ram2e_ufm/SLICE_66 ( .D1(\ram2e_ufm/wb_ack ), 
+    .C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), 
+    .A1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), 
+    .D0(\ram2e_ufm/CmdExecMXO2 ), .C0(\ram2e_ufm/wb_ack ), 
+    .B0(\ram2e_ufm/N_187 ), 
+    .A0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ), 
+    .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), 
+    .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ));
+  ram2e_ufm_SLICE_67 \ram2e_ufm/SLICE_67 ( .C1(\FS[2] ), .B1(\FS[3] ), 
+    .A1(\FS[1] ), .D0(\FS[4] ), .C0(\ram2e_ufm/N_250 ), .B0(\FS[3] ), 
+    .A0(\S[1] ), .F0(\ram2e_ufm/N_256 ), .F1(\ram2e_ufm/N_250 ));
+  ram2e_ufm_SLICE_68 \ram2e_ufm/SLICE_68 ( .D1(\FS[8] ), .C1(\FS[9] ), 
+    .B1(\ram2e_ufm/N_783 ), .A1(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), 
+    .D0(\FS[12] ), .C0(\FS[8] ), .B0(\FS[10] ), .A0(\FS[11] ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .F1(\ram2e_ufm/wb_adr_7_i_i_3[0] ));
+  ram2e_ufm_SLICE_69 \ram2e_ufm/SLICE_69 ( .D1(\FS[15] ), .C1(\FS[0] ), 
+    .B1(\ram2e_ufm/N_254 ), .A1(\ram2e_ufm/wb_rst16_i ), .D0(\S[2] ), 
+    .C0(\S[1] ), .B0(\S[0] ), .A0(\S[3] ), .F0(\ram2e_ufm/wb_rst16_i ), 
+    .F1(\ram2e_ufm/N_641 ));
+  ram2e_ufm_SLICE_70 \ram2e_ufm/SLICE_70 ( .D1(\ram2e_ufm/N_777 ), 
+    .B1(\FS[14] ), .A1(\FS[8] ), .D0(\FS[13] ), .C0(\ram2e_ufm/N_807 ), 
+    .B0(\FS[12] ), .A0(\ram2e_ufm/N_876 ), .F0(\ram2e_ufm/N_604 ), 
+    .F1(\ram2e_ufm/N_807 ));
+  ram2e_ufm_SLICE_71 \ram2e_ufm/SLICE_71 ( .D1(\FS[3] ), 
+    .C1(\ram2e_ufm/N_784 ), .A1(\FS[4] ), .D0(\S[3] ), .C0(\S[0] ), 
+    .A0(\S[2] ), .F0(\ram2e_ufm/N_784 ), .F1(\ram2e_ufm/N_801 ));
+  ram2e_ufm_SLICE_72 \ram2e_ufm/SLICE_72 ( .D1(\RWBank[5] ), 
+    .C1(\ram2e_ufm/N_560 ), .B1(\FS[4] ), .A1(\S[0] ), .D0(\S[2] ), 
+    .B0(\S[3] ), .A0(\S[1] ), .F0(\ram2e_ufm/N_560 ), .F1(\BA_4[0] ));
+  ram2e_ufm_SLICE_73 \ram2e_ufm/SLICE_73 ( .D1(\ram2e_ufm/N_781 ), 
+    .C1(\ram2e_ufm/N_873 ), .B1(\ram2e_ufm/N_184 ), .A1(\ram2e_ufm/N_611 ), 
+    .D0(\FS[9] ), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[8] ), 
+    .F0(\ram2e_ufm/N_873 ), .F1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ));
+  ram2e_ufm_SLICE_74 \ram2e_ufm/SLICE_74 ( .D1(\RWBank[3] ), 
+    .C1(\ram2e_ufm/N_845 ), .A1(\ram2e_ufm/N_625 ), .D0(\S[1] ), .C0(\S[2] ), 
+    .B0(\S[3] ), .A0(\S[0] ), .F0(\ram2e_ufm/N_845 ), 
+    .F1(\ram2e_ufm/RA_35_2_0_0[10] ));
+  ram2e_ufm_SLICE_75 \ram2e_ufm/SLICE_75 ( .C1(\FS[9] ), .B1(\FS[10] ), 
+    .A1(\FS[11] ), .D0(\FS[13] ), .C0(\ram2e_ufm/wb_ack ), 
+    .B0(\ram2e_ufm/N_876 ), .A0(\FS[12] ), 
+    .F0(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), 
+    .F1(\ram2e_ufm/N_876 ));
+  ram2e_ufm_SLICE_76 \ram2e_ufm/SLICE_76 ( .B1(\FS[10] ), .A1(\FS[11] ), 
+    .D0(\FS[13] ), .C0(\ram2e_ufm/N_811 ), .B0(\ram2e_ufm/N_206 ), 
+    .A0(\FS[12] ), .F0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), 
+    .F1(\ram2e_ufm/N_811 ));
+  ram2e_ufm_SLICE_77 \ram2e_ufm/SLICE_77 ( .D1(\CS[0] ), 
+    .C1(\ram2e_ufm/N_185 ), .B1(RWSel), .D0(\S[2] ), .C0(\S[3] ), .B0(\S[1] ), 
+    .A0(\S[0] ), .F0(\ram2e_ufm/N_185 ), .F1(\ram2e_ufm/N_215 ));
+  ram2e_ufm_SLICE_78 \ram2e_ufm/SLICE_78 ( .C1(\S[1] ), .A1(\S[0] ), 
+    .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\RWBank[1] ), .A0(\S[3] ), 
+    .F0(\ram2e_ufm/N_699 ), .F1(\ram2e_ufm/S_r_i_0_o2[1] ));
+  ram2e_ufm_SLICE_79 \ram2e_ufm/SLICE_79 ( .D1(CmdLEDSet), 
+    .C1(\ram2e_ufm/N_187 ), 
+    .B1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), 
+    .A1(\ram2e_ufm/N_807 ), .D0(\S[2] ), .C0(RWSel), 
+    .B0(\ram2e_ufm/S_r_i_0_o2[1] ), .A0(\S[3] ), .F0(\ram2e_ufm/N_187 ), 
+    .F1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ));
+  ram2e_ufm_SLICE_80 \ram2e_ufm/SLICE_80 ( .D1(\S[0] ), .C1(\FS[15] ), 
+    .B1(\S[1] ), .A1(N_551), .D0(RWSel), .C0(\ram2e_ufm/N_777 ), 
+    .B0(\ram2e_ufm/CmdBitbangMXO2 ), .A0(\ram2e_ufm/N_185 ), 
+    .F0(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .F1(\ram2e_ufm/N_777 ));
+  ram2e_ufm_SLICE_81 \ram2e_ufm/SLICE_81 ( .D1(\FS[14] ), 
+    .C1(\ram2e_ufm/N_777 ), .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[12] ), 
+    .C0(\FS[13] ), .B0(\ram2e_ufm/N_856 ), .A0(\ram2e_ufm/N_811 ), 
+    .F0(\ram2e_ufm/N_757 ), .F1(\ram2e_ufm/N_856 ));
+  ram2e_ufm_SLICE_82 \ram2e_ufm/SLICE_82 ( .D1(\Din_c[6] ), .C1(\CS[0] ), 
+    .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ), 
+    .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), 
+    .C0(\ram2e_ufm/N_637 ), .B0(\ram2e_ufm/N_185 ), 
+    .A0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ), .F0(un1_CS_0_sqmuxa_i), 
+    .F1(\ram2e_ufm/N_637 ));
+  ram2e_ufm_SLICE_83 \ram2e_ufm/SLICE_83 ( .D1(\CS[2] ), .C1(\Din_c[6] ), 
+    .B1(\ram2e_ufm/N_851 ), .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ), 
+    .C0(\CS[0] ), .B0(RWSel), .A0(\ram2e_ufm/N_592 ), 
+    .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ));
+  ram2e_ufm_SLICE_84 \ram2e_ufm/SLICE_84 ( .D1(\Din_c[4] ), 
+    .C1(\ram2e_ufm/N_212 ), .B1(\CS[2] ), .A1(\ram2e_ufm/N_850 ), 
+    .D0(\ram2e_ufm/N_720_tz ), .C0(\ram2e_ufm/N_886 ), .B0(\CS[1] ), 
+    .A0(\ram2e_ufm/N_187 ), .F0(\ram2e_ufm/SUM0_i_3 ), .F1(\ram2e_ufm/N_886 ));
+  ram2e_ufm_SLICE_85 \ram2e_ufm/SLICE_85 ( .D1(\FS[14] ), .C1(\FS[12] ), 
+    .B1(\FS[13] ), .A1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/N_187 ), 
+    .C0(\ram2e_ufm/N_793 ), 
+    .B0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), .A0(CmdRWMaskSet), 
+    .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .F1(\ram2e_ufm/N_793 ));
+  ram2e_ufm_SLICE_86 \ram2e_ufm/SLICE_86 ( .C1(\Din_c[0] ), .A1(\S[2] ), 
+    .D0(\ram2e_ufm/N_634 ), .C0(\ram2e_ufm/N_753 ), 
+    .B0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), .A0(\ram2e_ufm/wb_adr_7_i_i_3[0] ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), .F1(\ram2e_ufm/N_634 ));
+  ram2e_ufm_SLICE_87 \ram2e_ufm/SLICE_87 ( .D1(\ram2e_ufm/N_190 ), 
+    .C1(\ram2e_ufm/N_212 ), .B1(\Din_c[1] ), 
+    .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C0(\ram2e_ufm/N_234 ), 
+    .B0(\ram2e_ufm/N_886 ), .A0(\CS[1] ), .F0(\ram2e_ufm/N_592 ), 
+    .F1(\ram2e_ufm/N_234 ));
+  ram2e_ufm_SLICE_88 \ram2e_ufm/SLICE_88 ( .B1(\FS[10] ), .A1(\FS[11] ), 
+    .D0(\ram2e_ufm/N_876 ), .C0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), 
+    .B0(\ram2e_ufm/N_206 ), .A0(\ram2e_ufm/N_793 ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ));
+  ram2e_ufm_SLICE_89 \ram2e_ufm/SLICE_89 ( .D1(\FS[13] ), 
+    .B1(\ram2e_ufm/N_777 ), .A1(\FS[14] ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .C0(\ram2e_ufm/N_783 ), 
+    .B0(\ram2e_ufm/wb_adr[3] ), .A0(\S[2] ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .F1(\ram2e_ufm/N_783 ));
+  ram2e_ufm_SLICE_90 \ram2e_ufm/SLICE_90 ( .D1(\FS[10] ), 
+    .C1(\ram2e_ufm/N_206 ), .B1(\FS[12] ), .A1(\FS[11] ), 
+    .D0(\ram2e_ufm/wb_adr[6] ), .C0(\ram2e_ufm/N_783 ), 
+    .B0(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ), .A0(\S[2] ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ));
+  ram2e_ufm_SLICE_91 \ram2e_ufm/SLICE_91 ( .D1(CO0_1), .C1(\RC[1] ), 
+    .B1(\RC[2] ), .A1(\ram2e_ufm/N_817 ), .D0(\ram2e_ufm/N_256 ), 
+    .C0(\ram2e_ufm/N_784 ), .B0(\ram2e_ufm/N_890 ), .A0(\ram2e_ufm/N_285_i ), 
+    .F0(\ram2e_ufm/nRAS_s_i_0_0 ), .F1(\ram2e_ufm/N_890 ));
+  ram2e_ufm_SLICE_92 \ram2e_ufm/SLICE_92 ( .D1(nWE_c), .C1(N_551), 
+    .B1(\ram2e_ufm/N_804 ), .A1(\S[1] ), .D0(\ram2e_ufm/N_890 ), 
+    .C0(\ram2e_ufm/N_285_i ), .B0(\ram2e_ufm/N_220 ), .A0(\S[0] ), 
+    .F0(\ram2e_ufm/N_640 ), .F1(\ram2e_ufm/N_220 ));
+  ram2e_ufm_SLICE_93 \ram2e_ufm/SLICE_93 ( .D1(\FS[9] ), .C1(\FS[8] ), 
+    .B1(\FS[10] ), .A1(\FS[11] ), .C0(\ram2e_ufm/N_783 ), .B0(\FS[12] ), 
+    .A0(\ram2e_ufm/N_196 ), .F0(\ram2e_ufm/N_760 ), .F1(\ram2e_ufm/N_196 ));
+  ram2e_ufm_SLICE_94 \ram2e_ufm/SLICE_94 ( .D1(\Din_c[7] ), .C1(\Din_c[4] ), 
+    .D0(\Din_c[0] ), .C0(\CS[2] ), .B0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), 
+    .A0(\ram2e_ufm/N_243 ), .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ));
+  ram2e_ufm_SLICE_95 \ram2e_ufm/SLICE_95 ( .D1(\S[2] ), .C1(\S[1] ), 
+    .B1(\S[0] ), .A1(\S[3] ), .D0(\Ain_c[4] ), .C0(\ram2e_ufm/N_186 ), 
+    .B0(\ram2e_ufm/N_182 ), .A0(\RA[4] ), .F0(\ram2e_ufm/RA_35_0_0_0[4] ), 
+    .F1(\ram2e_ufm/N_182 ));
+  ram2e_ufm_SLICE_96 \ram2e_ufm/SLICE_96 ( .D1(\S[2] ), .C1(\S[1] ), 
+    .B1(\S[0] ), .A1(\S[3] ), .D0(\ram2e_ufm/N_182 ), .C0(\ram2e_ufm/N_186 ), 
+    .B0(\RA[6] ), .A0(\Ain_c[6] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[6] ), 
+    .F1(\ram2e_ufm/N_186 ));
+  ram2e_ufm_SLICE_97 \ram2e_ufm/SLICE_97 ( .D1(\FS[13] ), 
+    .C1(\ram2e_ufm/N_873 ), .A1(\FS[12] ), .D0(\ram2e_ufm/wb_adr[1] ), 
+    .C0(\ram2e_ufm/N_781 ), .B0(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ), 
+    .A0(\S[2] ), .F0(\ram2e_ufm/wb_dati_7_0_0_0[1] ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ));
+  ram2e_ufm_SLICE_98 \ram2e_ufm/SLICE_98 ( .D1(\FS[14] ), 
+    .C1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/wb_adr[7] ), 
+    .C0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), .B0(\ram2e_ufm/N_781 ), 
+    .A0(\S[2] ), .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), .F1(\ram2e_ufm/N_781 ));
+  ram2e_ufm_SLICE_99 \ram2e_ufm/SLICE_99 ( .D1(\FS[11] ), .B1(\FS[10] ), 
+    .A1(\FS[8] ), .D0(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ), 
+    .C0(\ram2e_ufm/N_781 ), .B0(\ram2e_ufm/N_565 ), .A0(\FS[12] ), 
+    .F0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), 
+    .F1(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ));
+  ram2e_ufm_SLICE_100 \ram2e_ufm/SLICE_100 ( .D1(\Din_c[1] ), .C1(\Din_c[3] ), 
+    .B1(\Din_c[5] ), .A1(\Din_c[2] ), .D0(\ram2e_ufm/N_243 ), .C0(\CS[2] ), 
+    .B0(\Din_c[7] ), .A0(\Din_c[4] ), .F0(\ram2e_ufm/N_345 ), 
+    .F1(\ram2e_ufm/N_243 ));
+  ram2e_ufm_SLICE_101 \ram2e_ufm/SLICE_101 ( .C1(\Din_c[3] ), .B1(\Din_c[5] ), 
+    .D0(\ram2e_ufm/N_190 ), .C0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ), 
+    .B0(\CS[1] ), .A0(\ram2e_ufm/N_850 ), 
+    .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .F1(\ram2e_ufm/N_190 ));
+  ram2e_ufm_SLICE_102 \ram2e_ufm/SLICE_102 ( .D1(\S[2] ), .C1(\S[1] ), 
+    .A1(\S[3] ), .C0(\ram2e_ufm/N_817 ), .B0(\ram2e_ufm/N_220 ), 
+    .A0(\ram2e_ufm/CKE_7s2_0_0_0 ), .F0(\ram2e_ufm/CKE_7_sm0 ), 
+    .F1(\ram2e_ufm/N_817 ));
+  ram2e_ufm_SLICE_103 \ram2e_ufm/SLICE_103 ( .D1(\FS[13] ), .A1(\FS[12] ), 
+    .D0(\ram2e_ufm/N_204 ), .C0(\ram2e_ufm/N_184 ), .B0(\ram2e_ufm/N_799 ), 
+    .A0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), .F0(\ram2e_ufm/wb_adr_7_5_41_0_1 ), 
+    .F1(\ram2e_ufm/N_184 ));
+  ram2e_ufm_SLICE_104 \ram2e_ufm/SLICE_104 ( .D1(\FS[8] ), .C1(\FS[11] ), 
+    .B1(\FS[9] ), .A1(\FS[10] ), .C0(\ram2e_ufm/N_595 ), .B0(\FS[12] ), 
+    .F0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .F1(\ram2e_ufm/N_595 ));
+  ram2e_ufm_SLICE_105 \ram2e_ufm/SLICE_105 ( .D1(\ram2e_ufm/nRWE_s_i_0_63_1 ), 
+    .C1(\ram2e_ufm/N_285_i ), .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\S[3] ), 
+    .D0(\ram2e_ufm/wb_rst16_i ), .C0(\FS[15] ), .B0(\FS[0] ), 
+    .F0(\ram2e_ufm/N_285_i ), .F1(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ));
+  ram2e_ufm_SLICE_106 \ram2e_ufm/SLICE_106 ( .C1(\S[1] ), .A1(\S[0] ), 
+    .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\ram2e_ufm/N_194 ), .B0(\RA[10] ), 
+    .A0(\S[2] ), .F0(\ram2e_ufm/N_624 ), .F1(\ram2e_ufm/N_194 ));
+  ram2e_ufm_SLICE_107 \ram2e_ufm/SLICE_107 ( .D1(\FS[4] ), .C1(\S[2] ), 
+    .B1(\S[0] ), .A1(\S[3] ), .D0(\FS[5] ), .C0(\ram2e_ufm/N_792 ), 
+    .B0(\FS[8] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_659 ), .F1(\ram2e_ufm/N_792 ));
+  ram2e_ufm_SLICE_108 \ram2e_ufm/SLICE_108 ( 
+    .D1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ), .C1(\FS[7] ), 
+    .B1(\FS[4] ), .A1(\FS[5] ), .D0(\ram2e_ufm/wb_req ), 
+    .C0(\ram2e_ufm/N_336 ), .B0(\FS[0] ), 
+    .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), 
+    .F1(\ram2e_ufm/N_336 ));
+  ram2e_ufm_SLICE_109 \ram2e_ufm/SLICE_109 ( .C1(\FS[14] ), .A1(\S[2] ), 
+    .D0(\FS[11] ), .C0(\ram2e_ufm/N_184 ), .B0(\ram2e_ufm/N_799 ), 
+    .A0(\ram2e_ufm/N_634 ), .F0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), 
+    .F1(\ram2e_ufm/N_799 ));
+  ram2e_ufm_SLICE_110 \ram2e_ufm/SLICE_110 ( .D1(\FS[10] ), .C1(\FS[9] ), 
+    .B1(\FS[11] ), .A1(\FS[8] ), .D0(\ram2e_ufm/wb_ack ), 
+    .C0(\ram2e_ufm/N_885 ), 
+    .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), 
+    .F1(\ram2e_ufm/N_885 ));
+  ram2e_ufm_SLICE_111 \ram2e_ufm/SLICE_111 ( .D1(\FS[12] ), 
+    .C1(\ram2e_ufm/N_553 ), .A1(\ram2e_ufm/N_807 ), 
+    .D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\FS[13] ), .B0(\FS[9] ), 
+    .A0(\ram2e_ufm/N_811 ), .F0(\ram2e_ufm/N_553 ), .F1(\ram2e_ufm/N_611 ));
+  ram2e_ufm_SLICE_112 \ram2e_ufm/SLICE_112 ( .D1(\S[1] ), .B1(\S[0] ), 
+    .A1(\ram2e_ufm/N_285_i ), .D0(\S[2] ), .C0(\ram2e_ufm/N_866 ), .B0(nWE_c), 
+    .A0(nEN80_c), .F0(\ram2e_ufm/N_616 ), .F1(\ram2e_ufm/N_866 ));
+  ram2e_ufm_SLICE_113 \ram2e_ufm/SLICE_113 ( .D1(\S[2] ), .B1(nEN80_c), 
+    .A1(\S[3] ), .D0(\S[1] ), .C0(\ram2e_ufm/N_804 ), .B0(nWE_c), .A0(\S[0] ), 
+    .F0(\ram2e_ufm/N_628 ), .F1(\ram2e_ufm/N_804 ));
+  ram2e_ufm_SLICE_114 \ram2e_ufm/SLICE_114 ( .C1(\FS[10] ), .B1(\FS[9] ), 
+    .A1(\FS[8] ), .D0(\ram2e_ufm/N_241_i ), .C0(\ram2e_ufm/N_799 ), 
+    .B0(\FS[12] ), .A0(\FS[11] ), .F0(\ram2e_ufm/N_768 ), 
+    .F1(\ram2e_ufm/N_241_i ));
+  ram2e_ufm_SLICE_115 \ram2e_ufm/SLICE_115 ( .D1(\S[2] ), .C1(\S[1] ), 
+    .D0(\S[0] ), .C0(\ram2e_ufm/N_221 ), .B0(nEN80_c), .A0(\S[3] ), 
+    .F0(\ram2e_ufm/CKE_7s2_0_0_0 ), .F1(\ram2e_ufm/N_221 ));
+  ram2e_ufm_SLICE_116 \ram2e_ufm/SLICE_116 ( 
+    .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C1(\ram2e_ufm/N_814 ), 
+    .B1(\Din_c[5] ), .A1(\Din_c[3] ), .C0(\Din_c[0] ), .B0(\Din_c[2] ), 
+    .A0(\Din_c[1] ), .F0(\ram2e_ufm/N_814 ), .F1(\ram2e_ufm/N_851 ));
+  ram2e_ufm_SLICE_117 \ram2e_ufm/SLICE_117 ( .D1(\S[2] ), .C1(\S[1] ), 
+    .B1(\S[3] ), .A1(\S[0] ), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[3] ), 
+    .A0(\S[0] ), .F0(N_225_i), .F1(\ram2e_ufm/N_643 ));
+  ram2e_ufm_SLICE_118 \ram2e_ufm/SLICE_118 ( .D1(\S[2] ), .C1(\S[1] ), 
+    .B1(\S[0] ), .A1(\S[3] ), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[0] ), 
+    .A0(\S[3] ), .F0(N_201_i), .F1(RC12));
+  ram2e_ufm_SLICE_119 \ram2e_ufm/SLICE_119 ( .D1(\S[2] ), .C1(\S[1] ), 
+    .B1(\S[0] ), .A1(\S[3] ), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[0] ), 
+    .A0(\S[3] ), .F0(N_126), .F1(N_185_i));
+  ram2e_ufm_SLICE_120 \ram2e_ufm/SLICE_120 ( .D1(\S[3] ), .C1(\RWBank[0] ), 
+    .B1(\FS[15] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\RWBank[0] ), .B0(\FS[15] ), 
+    .A0(\S[0] ), .F0(N_507_i), .F1(N_508));
+  ram2e_ufm_SLICE_121 \ram2e_ufm/SLICE_121 ( .D1(\S[2] ), .C1(\S[1] ), 
+    .B1(\S[3] ), .A1(\S[0] ), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[3] ), 
+    .A0(\S[0] ), .F0(\ram2e_ufm/N_242 ), .F1(Vout3));
+  ram2e_ufm_SLICE_122 \ram2e_ufm/SLICE_122 ( .D1(\FS[3] ), .C1(\FS[2] ), 
+    .B1(\FS[1] ), .A1(\FS[4] ), .D0(\FS[3] ), .C0(\FS[2] ), .B0(\FS[1] ), 
+    .A0(\FS[4] ), .F0(\ram2e_ufm/N_254 ), .F1(\ram2e_ufm/nRWE_s_i_0_63_1 ));
+  ram2e_ufm_SLICE_123 \ram2e_ufm/SLICE_123 ( .D1(\FS[8] ), .C1(\FS[11] ), 
+    .B1(\FS[9] ), .D0(\FS[10] ), .C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[8] ), 
+    .F0(\ram2e_ufm/N_849 ), .F1(\ram2e_ufm/N_204 ));
+  ram2e_ufm_SLICE_124 \ram2e_ufm/SLICE_124 ( .D1(\FS[4] ), .C1(\FS[12] ), 
+    .B1(\ram2e_ufm/N_784 ), .A1(\FS[3] ), .D0(\FS[4] ), .C0(\FS[1] ), 
+    .B0(\ram2e_ufm/N_784 ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_684 ), 
+    .F1(\ram2e_ufm/RA_35_0_0_0[5] ));
+  ram2e_ufm_SLICE_125 \ram2e_ufm/SLICE_125 ( .D1(\FS[9] ), .C1(\FS[11] ), 
+    .B1(\FS[13] ), .A1(\FS[8] ), .D0(\FS[8] ), .C0(\FS[11] ), .B0(\FS[9] ), 
+    .A0(\ram2e_ufm/N_793 ), .F0(\ram2e_ufm/N_763 ), .F1(\ram2e_ufm/N_565 ));
+  ram2e_ufm_SLICE_126 \ram2e_ufm/SLICE_126 ( .D1(\FS[8] ), .C1(\FS[10] ), 
+    .B1(\FS[9] ), .A1(\FS[12] ), .D0(\ram2e_ufm/N_781 ), .C0(\FS[10] ), 
+    .B0(\FS[9] ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_753 ), 
+    .F1(\ram2e_ufm/N_208 ));
+  ram2e_ufm_SLICE_127 \ram2e_ufm/SLICE_127 ( .D1(\S[2] ), .C1(\S[0] ), 
+    .B1(\S[3] ), .A1(\S[1] ), .D0(\S[2] ), .C0(\S[0] ), .B0(\S[3] ), 
+    .A0(\RWBank[7] ), .F0(\ram2e_ufm/N_698 ), .F1(un9_VOEEN_0_a2_0_a3_0_a3));
+  ram2e_ufm_SLICE_128 \ram2e_ufm/SLICE_128 ( .D1(\FS[13] ), .C1(\FS[11] ), 
+    .B1(\FS[10] ), .A1(\FS[12] ), .D0(\FS[13] ), .C0(\FS[12] ), .B0(\FS[10] ), 
+    .F0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ));
+  ram2e_ufm_SLICE_129 \ram2e_ufm/SLICE_129 ( .D1(\S[0] ), 
+    .C1(\ram2e_ufm/N_560 ), .B1(\FS[4] ), .A1(\RWBank[6] ), .D0(\S[0] ), 
+    .C0(N_551), .B0(\FS[4] ), .A0(\FS[1] ), .F0(\ram2e_ufm/N_627 ), 
+    .F1(\BA_4[1] ));
+  ram2e_ufm_SLICE_130 \ram2e_ufm/SLICE_130 ( .C1(RWSel), 
+    .A1(\ram2e_ufm/N_185 ), .D0(\ram2e_ufm/N_777 ), .C0(RWSel), 
+    .B0(\ram2e_ufm/CmdExecMXO2 ), .A0(\ram2e_ufm/N_185 ), 
+    .F0(\ram2e_ufm/wb_we_RNO_0 ), .F1(N_187_i));
+  ram2e_ufm_SLICE_131 \ram2e_ufm/SLICE_131 ( .D1(\FS[1] ), .C1(\FS[13] ), 
+    .B1(\FS[12] ), .A1(\FS[3] ), .D0(\FS[13] ), .C0(\ram2e_ufm/N_856 ), 
+    .B0(\ram2e_ufm/N_811 ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_602 ), 
+    .F1(\ram2e_ufm/Ready3_0_a3_5 ));
+  ram2e_ufm_SLICE_132 \ram2e_ufm/SLICE_132 ( .D1(\ram2e_ufm/N_182 ), 
+    .C1(\Ain_c[0] ), .B1(\ram2e_ufm/N_186 ), .A1(\RA[0] ), 
+    .D0(\ram2e_ufm/N_182 ), .C0(\Ain_c[7] ), .B0(\RA[7] ), 
+    .A0(\ram2e_ufm/N_186 ), .F0(\ram2e_ufm/RA_35_0_0_0_0[7] ), 
+    .F1(\ram2e_ufm/RA_35_0_0_1[0] ));
+  ram2e_ufm_SLICE_133 \ram2e_ufm/SLICE_133 ( .D1(\Din_c[2] ), .C1(\Din_c[0] ), 
+    .B1(\Din_c[4] ), .A1(RWSel), .D0(\Din_c[2] ), .C0(\ram2e_ufm/N_338 ), 
+    .B0(\Din_c[4] ), .F0(\ram2e_ufm/N_350 ), 
+    .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ));
+  ram2e_ufm_SLICE_134 \ram2e_ufm/SLICE_134 ( .D1(\FS[6] ), .C1(\FS[3] ), 
+    .B1(\FS[1] ), .A1(\FS[2] ), .D0(\FS[6] ), .C0(\FS[3] ), .B0(\FS[9] ), 
+    .A0(\ram2e_ufm/N_792 ), .F0(\ram2e_ufm/N_679 ), 
+    .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ));
+  ram2e_ufm_SLICE_135 \ram2e_ufm/SLICE_135 ( .D1(\S[3] ), .C1(\S[2] ), 
+    .D0(\S[3] ), .C0(\S[2] ), .B0(nEN80_c), .A0(\ram2e_ufm/S_r_i_0_o2[1] ), 
+    .F0(\ram2e_ufm/N_625 ), .F1(\ram2e_ufm/N_271 ));
+  ram2e_ufm_SLICE_136 \ram2e_ufm/SLICE_136 ( .D1(nEN80_c), .C1(\S[3] ), 
+    .B1(nWE_c), .C0(nEN80_c), .B0(nWE_c), .A0(DOEEN), .F0(nDOE_c), 
+    .F1(\ram2e_ufm/N_226 ));
+  ram2e_ufm_SLICE_137 \ram2e_ufm/SLICE_137 ( .D1(nWE_c), .C1(nEN80_c), 
+    .A1(Ready), .D0(\ram2e_ufm/LEDEN ), .C0(nEN80_c), .A0(Ready), .F0(LED_c), 
+    .F1(RDOE_i));
+  SLICE_138 SLICE_138( .C1(\S[0] ), .B1(\S[3] ), .A1(\S[1] ), .D0(\S[2] ), 
+    .C0(\S[0] ), .B0(\S[1] ), .F0(N_1080_0), .F1(N_1078_0));
+  SLICE_139 SLICE_139( .C1(VOEEN), .A1(PHI1_c), .D0(Ready), .B0(PHI1r), 
+    .A0(PHI1_c), .F0(S_1), .F1(nVOE_c));
+  ram2e_ufm_SLICE_140 \ram2e_ufm/SLICE_140 ( .C1(\ram2e_ufm/N_186 ), 
+    .A1(\RA[2] ), .D0(\RA[5] ), .C0(\ram2e_ufm/N_186 ), .F0(\ram2e_ufm/N_621 ), 
+    .F1(\ram2e_ufm/N_680 ));
+  ram2e_ufm_SLICE_141 \ram2e_ufm/SLICE_141 ( .D1(Ready), .C1(\Din_c[0] ), 
+    .D0(Ready), .B0(\Din_c[3] ), .F0(N_263_i), .F1(N_667));
+  ram2e_ufm_SLICE_142 \ram2e_ufm/SLICE_142 ( .D1(\Din_c[4] ), .C1(\Din_c[0] ), 
+    .B1(\Din_c[7] ), .D0(\Din_c[4] ), .B0(Ready), .F0(N_648), 
+    .F1(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ));
+  ram2e_ufm_SLICE_143 \ram2e_ufm/SLICE_143 ( .D1(\Din_c[1] ), .B1(Ready), 
+    .D0(\Din_c[7] ), .B0(Ready), .F0(N_662), .F1(N_666));
+  ram2e_ufm_SLICE_144 \ram2e_ufm/SLICE_144 ( .B1(Ready), .A1(\Din_c[2] ), 
+    .D0(\Din_c[6] ), .B0(Ready), .F0(N_663), .F1(N_665));
+  ram2e_ufm_SLICE_145 \ram2e_ufm/SLICE_145 ( .D1(\ram2e_ufm/N_873 ), 
+    .C1(\ram2e_ufm/wb_adr[4] ), .B1(\ram2e_ufm/N_783 ), .A1(\S[2] ), 
+    .C0(\FS[8] ), .B0(\FS[9] ), .F0(\ram2e_ufm/N_206 ), 
+    .F1(\ram2e_ufm/wb_dati_7_0_0_0[4] ));
+  ram2e_ufm_SLICE_146 \ram2e_ufm/SLICE_146 ( .D1(\FS[4] ), .C1(\RWBank[2] ), 
+    .B1(\ram2e_ufm/N_784 ), .A1(\ram2e_ufm/N_845 ), .D0(\FS[0] ), .C0(\FS[6] ), 
+    .B0(\FS[5] ), .A0(\FS[7] ), .F0(\ram2e_ufm/Ready3_0_a3_3 ), 
+    .F1(\ram2e_ufm/RA_35_0_0_0[9] ));
+  ram2e_ufm_SLICE_147 \ram2e_ufm/SLICE_147 ( .D1(CmdLEDGet), 
+    .C1(\ram2e_ufm/LEDEN ), .B1(CmdSetRWBankFFLED), 
+    .A1(\ram2e_ufm/CmdSetRWBankFFChip ), .C0(\Din_c[5] ), .B0(Ready), 
+    .F0(N_664), .F1(\ram2e_ufm/N_188 ));
+  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(N_667), 
     .RD0(RD[0]));
   LED LED_I( .PADDO(LED_c), .LED(LED));
   C14M C14M_I( .PADDI(C14M_c), .C14M(C14M));
-  DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH));
-  DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_358_i), .CLK(C14M_c));
-  DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML));
-  DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_28_i), .CLK(C14M_c));
-  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(\Din_c[7] ), 
+  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(N_662), 
     .RD7(RD[7]));
-  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(\Din_c[6] ), 
+  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(N_663), 
     .RD6(RD[6]));
-  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(\Din_c[5] ), 
+  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(N_664), 
     .RD5(RD[5]));
-  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(\Din_c[4] ), 
+  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(N_648), 
     .RD4(RD[4]));
-  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(\Din_c[3] ), 
+  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(N_263_i), 
     .RD3(RD[3]));
-  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(\Din_c[2] ), 
+  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(N_665), 
     .RD2(RD[2]));
-  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(\Din_c[1] ), 
+  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(N_666), 
     .RD1(RD[1]));
-  RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11]));
-  RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(\RA_42[11] ), 
+  DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH));
+  DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_508), .CE(N_201_i), 
     .CLK(C14M_c));
-  RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10]));
-  RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(\RA_42[10] ), 
+  DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML));
+  DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_507_i), .CE(N_201_i), 
+    .CLK(C14M_c));
+  RAout_11_ \RAout[11]_I ( .IOLDO(\RAout_c[11] ), .RAout11(RAout[11]));
+  RAout_11__MGIOL \RAout[11]_MGIOL ( .IOLDO(\RAout_c[11] ), .OPOS(\RA[11] ), 
+    .CLK(C14M_c));
+  RAout_10_ \RAout[10]_I ( .IOLDO(\RAout_c[10] ), .RAout10(RAout[10]));
+  RAout_10__MGIOL \RAout[10]_MGIOL ( .IOLDO(\RAout_c[10] ), .OPOS(\RA[10] ), 
+    .CLK(C14M_c));
+  RAout_9_ \RAout[9]_I ( .IOLDO(\RAout_c[9] ), .RAout9(RAout[9]));
+  RAout_9__MGIOL \RAout[9]_MGIOL ( .IOLDO(\RAout_c[9] ), .OPOS(\RA[9] ), 
+    .CLK(C14M_c));
+  RAout_8_ \RAout[8]_I ( .IOLDO(\RAout_c[8] ), .RAout8(RAout[8]));
+  RAout_8__MGIOL \RAout[8]_MGIOL ( .IOLDO(\RAout_c[8] ), .OPOS(\RA[8] ), 
+    .CLK(C14M_c));
+  RAout_7_ \RAout[7]_I ( .IOLDO(\RAout_c[7] ), .RAout7(RAout[7]));
+  RAout_7__MGIOL \RAout[7]_MGIOL ( .IOLDO(\RAout_c[7] ), .OPOS(\RA[7] ), 
+    .CLK(C14M_c));
+  RAout_6_ \RAout[6]_I ( .IOLDO(\RAout_c[6] ), .RAout6(RAout[6]));
+  RAout_6__MGIOL \RAout[6]_MGIOL ( .IOLDO(\RAout_c[6] ), .OPOS(\RA[6] ), 
+    .CLK(C14M_c));
+  RAout_5_ \RAout[5]_I ( .IOLDO(\RAout_c[5] ), .RAout5(RAout[5]));
+  RAout_5__MGIOL \RAout[5]_MGIOL ( .IOLDO(\RAout_c[5] ), .OPOS(\RA[5] ), 
+    .CLK(C14M_c));
+  RAout_4_ \RAout[4]_I ( .IOLDO(\RAout_c[4] ), .RAout4(RAout[4]));
+  RAout_4__MGIOL \RAout[4]_MGIOL ( .IOLDO(\RAout_c[4] ), .OPOS(\RA[4] ), 
+    .CLK(C14M_c));
+  RAout_3_ \RAout[3]_I ( .IOLDO(\RAout_c[3] ), .RAout3(RAout[3]));
+  RAout_3__MGIOL \RAout[3]_MGIOL ( .IOLDO(\RAout_c[3] ), .OPOS(\RA[3] ), 
+    .CLK(C14M_c));
+  RAout_2_ \RAout[2]_I ( .IOLDO(\RAout_c[2] ), .RAout2(RAout[2]));
+  RAout_2__MGIOL \RAout[2]_MGIOL ( .IOLDO(\RAout_c[2] ), .OPOS(\RA[2] ), 
+    .CLK(C14M_c));
+  RAout_1_ \RAout[1]_I ( .IOLDO(\RAout_c[1] ), .RAout1(RAout[1]));
+  RAout_1__MGIOL \RAout[1]_MGIOL ( .IOLDO(\RAout_c[1] ), .OPOS(\RA[1] ), 
+    .CLK(C14M_c));
+  RAout_0_ \RAout[0]_I ( .IOLDO(\RAout_c[0] ), .RAout0(RAout[0]));
+  RAout_0__MGIOL \RAout[0]_MGIOL ( .IOLDO(\RAout_c[0] ), .OPOS(\RA[0] ), 
     .CLK(C14M_c));
-  RA_9_ \RA[9]_I ( .IOLDO(\RA_c[9] ), .RA9(RA[9]));
-  RA_9__MGIOL \RA[9]_MGIOL ( .IOLDO(\RA_c[9] ), .OPOS(N_59_i), .CLK(C14M_c));
-  RA_8_ \RA[8]_I ( .IOLDO(\RA_c[8] ), .RA8(RA[8]));
-  RA_8__MGIOL \RA[8]_MGIOL ( .IOLDO(\RA_c[8] ), .OPOS(N_49_i), .CLK(C14M_c));
-  RA_7_ \RA[7]_I ( .IOLDO(\RA_c[7] ), .RA7(RA[7]));
-  RA_7__MGIOL \RA[7]_MGIOL ( .IOLDO(\RA_c[7] ), .OPOS(N_549_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_6_ \RA[6]_I ( .IOLDO(\RA_c[6] ), .RA6(RA[6]));
-  RA_6__MGIOL \RA[6]_MGIOL ( .IOLDO(\RA_c[6] ), .OPOS(N_550_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_5_ \RA[5]_I ( .IOLDO(\RA_c[5] ), .RA5(RA[5]));
-  RA_5__MGIOL \RA[5]_MGIOL ( .IOLDO(\RA_c[5] ), .OPOS(\RA_42_3_0[5] ), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_4_ \RA[4]_I ( .IOLDO(\RA_c[4] ), .RA4(RA[4]));
-  RA_4__MGIOL \RA[4]_MGIOL ( .IOLDO(\RA_c[4] ), .OPOS(N_551_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
-  RA_2_ \RA[2]_I ( .IOLDO(\RA_c[2] ), .RA2(RA[2]));
-  RA_2__MGIOL \RA[2]_MGIOL ( .IOLDO(\RA_c[2] ), .OPOS(N_553_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_1_ \RA[1]_I ( .IOLDO(\RA_c[1] ), .RA1(RA[1]));
-  RA_1__MGIOL \RA[1]_MGIOL ( .IOLDO(\RA_c[1] ), .OPOS(N_558_i), 
-    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
-  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
   BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1]));
-  BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), 
-    .LSR(N_566_i), .CLK(C14M_c));
+  BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), .CE(N_225_i), 
+    .LSR(BA_0_sqmuxa), .CLK(C14M_c));
   BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0]));
-  BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), 
-    .LSR(N_566_i), .CLK(C14M_c));
-  nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE));
-  nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(nRWE_r_0), .CLK(C14M_c));
-  nCAS nCAS_I( .IOLDO(nCAS_c), .nCAS(nCAS));
-  nCAS_MGIOL nCAS_MGIOL( .IOLDO(nCAS_c), .OPOS(N_561_i), .CLK(C14M_c));
-  nRAS nRAS_I( .IOLDO(nRAS_c), .nRAS(nRAS));
-  nRAS_MGIOL nRAS_MGIOL( .IOLDO(nRAS_c), .OPOS(nRAS_2_iv_i), .CLK(C14M_c));
-  nCS nCS_I( .IOLDO(nCS_c), .nCS(nCS));
-  nCS_MGIOL nCS_MGIOL( .IOLDO(nCS_c), .OPOS(N_559_i), .CLK(C14M_c));
-  CKE CKE_I( .IOLDO(CKE_c), .CKE(CKE));
-  CKE_MGIOL CKE_MGIOL( .IOLDO(CKE_c), .OPOS(CKE_6_iv_i_0), .CLK(C14M_c));
-  nVOE nVOE_I( .PADDO(PHI1_c), .nVOE(nVOE));
+  BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), .CE(N_225_i), 
+    .LSR(BA_0_sqmuxa), .CLK(C14M_c));
+  nRWEout nRWEout_I( .IOLDO(nRWEout_c), .nRWEout(nRWEout));
+  nRWEout_MGIOL nRWEout_MGIOL( .IOLDO(nRWEout_c), .OPOS(nRWE), .CLK(C14M_c));
+  nCASout nCASout_I( .IOLDO(nCASout_c), .nCASout(nCASout));
+  nCASout_MGIOL nCASout_MGIOL( .IOLDO(nCASout_c), .OPOS(nCAS), .CLK(C14M_c));
+  nRASout nRASout_I( .IOLDO(nRASout_c), .nRASout(nRASout));
+  nRASout_MGIOL nRASout_MGIOL( .IOLDO(nRASout_c), .OPOS(nRAS), .CLK(C14M_c));
+  nCSout nCSout_I( .PADDO(GND), .nCSout(nCSout));
+  CKEout CKEout_I( .IOLDO(CKEout_c), .CKEout(CKEout));
+  CKEout_MGIOL CKEout_MGIOL( .IOLDO(CKEout_c), .OPOS(CKE), .CLK(C14M_c));
+  nVOE nVOE_I( .PADDO(nVOE_c), .nVOE(nVOE));
   Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7]));
   Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), 
     .CE(Vout3), .CLK(C14M_c));
@@ -573,30 +897,14 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), 
     .CE(Vout3), .CLK(C14M_c));
   nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE));
-  Dout_7_ \Dout[7]_I ( .IOLDO(\Dout_c[7] ), .Dout7(Dout[7]));
-  Dout_7__MGIOL \Dout[7]_MGIOL ( .IOLDO(\Dout_c[7] ), .OPOS(\RD_in[7] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_6_ \Dout[6]_I ( .IOLDO(\Dout_c[6] ), .Dout6(Dout[6]));
-  Dout_6__MGIOL \Dout[6]_MGIOL ( .IOLDO(\Dout_c[6] ), .OPOS(\RD_in[6] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_5_ \Dout[5]_I ( .IOLDO(\Dout_c[5] ), .Dout5(Dout[5]));
-  Dout_5__MGIOL \Dout[5]_MGIOL ( .IOLDO(\Dout_c[5] ), .OPOS(\RD_in[5] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_4_ \Dout[4]_I ( .IOLDO(\Dout_c[4] ), .Dout4(Dout[4]));
-  Dout_4__MGIOL \Dout[4]_MGIOL ( .IOLDO(\Dout_c[4] ), .OPOS(\RD_in[4] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_3_ \Dout[3]_I ( .IOLDO(\Dout_c[3] ), .Dout3(Dout[3]));
-  Dout_3__MGIOL \Dout[3]_MGIOL ( .IOLDO(\Dout_c[3] ), .OPOS(\RD_in[3] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_2_ \Dout[2]_I ( .IOLDO(\Dout_c[2] ), .Dout2(Dout[2]));
-  Dout_2__MGIOL \Dout[2]_MGIOL ( .IOLDO(\Dout_c[2] ), .OPOS(\RD_in[2] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_1_ \Dout[1]_I ( .IOLDO(\Dout_c[1] ), .Dout1(Dout[1]));
-  Dout_1__MGIOL \Dout[1]_MGIOL ( .IOLDO(\Dout_c[1] ), .OPOS(\RD_in[1] ), 
-    .CE(N_576_i), .CLK(C14M_c));
-  Dout_0_ \Dout[0]_I ( .IOLDO(\Dout_c[0] ), .Dout0(Dout[0]));
-  Dout_0__MGIOL \Dout[0]_MGIOL ( .IOLDO(\Dout_c[0] ), .OPOS(\RD_in[0] ), 
-    .CE(N_576_i), .CLK(C14M_c));
+  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
+  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
+  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
+  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
+  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
+  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
+  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
+  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
   Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
   Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
   Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
@@ -615,21 +923,25 @@ module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
   Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0]));
   nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X));
   nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80));
-  nWE80 nWE80_I( .PADDI(nWE80_c), .nWE80(nWE80));
   nWE nWE_I( .PADDI(nWE_c), .nWE(nWE));
   PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1));
-  PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1reg));
-  ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), .WBRSTI(wb_rst), 
-    .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), 
-    .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), 
-    .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), 
-    .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), 
-    .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), 
-    .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), 
-    .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), 
-    .WBDATO2(\wb_dato[2] ), .WBDATO3(\wb_dato[3] ), .WBDATO4(\wb_dato[4] ), 
-    .WBDATO5(\wb_dato[5] ), .WBDATO6(\wb_dato[6] ), .WBDATO7(\wb_dato[7] ), 
-    .WBACKO(wb_ack));
+  PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1r));
+  ram2e_ufm_ufmefb_EFBInst_0 \ram2e_ufm/ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), 
+    .WBRSTI(\ram2e_ufm/wb_rst ), .WBCYCI(\ram2e_ufm/wb_cyc_stb ), 
+    .WBSTBI(\ram2e_ufm/wb_cyc_stb ), .WBWEI(\ram2e_ufm/wb_we ), 
+    .WBADRI0(\ram2e_ufm/wb_adr[0] ), .WBADRI1(\ram2e_ufm/wb_adr[1] ), 
+    .WBADRI2(\ram2e_ufm/wb_adr[2] ), .WBADRI3(\ram2e_ufm/wb_adr[3] ), 
+    .WBADRI4(\ram2e_ufm/wb_adr[4] ), .WBADRI5(\ram2e_ufm/wb_adr[5] ), 
+    .WBADRI6(\ram2e_ufm/wb_adr[6] ), .WBADRI7(\ram2e_ufm/wb_adr[7] ), 
+    .WBDATI0(\ram2e_ufm/wb_dati[0] ), .WBDATI1(\ram2e_ufm/wb_dati[1] ), 
+    .WBDATI2(\ram2e_ufm/wb_dati[2] ), .WBDATI3(\ram2e_ufm/wb_dati[3] ), 
+    .WBDATI4(\ram2e_ufm/wb_dati[4] ), .WBDATI5(\ram2e_ufm/wb_dati[5] ), 
+    .WBDATI6(\ram2e_ufm/wb_dati[6] ), .WBDATI7(\ram2e_ufm/wb_dati[7] ), 
+    .WBDATO0(\ram2e_ufm/wb_dato[0] ), .WBDATO1(\ram2e_ufm/wb_dato[1] ), 
+    .WBDATO2(\ram2e_ufm/wb_dato[2] ), .WBDATO3(\ram2e_ufm/wb_dato[3] ), 
+    .WBDATO4(\ram2e_ufm/wb_dato[4] ), .WBDATO5(\ram2e_ufm/wb_dato[5] ), 
+    .WBDATO6(\ram2e_ufm/wb_dato[6] ), .WBDATO7(\ram2e_ufm/wb_dato[7] ), 
+    .WBACKO(\ram2e_ufm/wb_ack ));
   VHI VHI_INST( .Z(VCCI));
   PUR PUR_INST( .PUR(VCCI));
   GSR GSR_INST( .GSR(VCCI));
@@ -940,20 +1252,62 @@ module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
 
 endmodule
 
-module SLICE_9 ( input C1, B1, A1, D0, A0, DI0, CE, CLK, output F0, Q0, F1 );
+module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
+    F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut4 \ram2e_ufm/wb_req_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40003 \ram2e_ufm/CKE_7_RNIS77M1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0004 CKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut4 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40003 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFF01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q );
+
+  FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module SLICE_10 ( input D0, A0, DI0, CE, CLK, output F0, Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut4 S_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40005 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40003 \CmdTout_3_0_a2[0] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
+  lut40006 \ram2e_ufm/CmdTout_3_0_a3_0_a3[0] ( .A(A0), .B(GNDI), .C(GNDI), 
+    .D(D0), .Z(F0));
   vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
@@ -965,27 +1319,64 @@ module SLICE_9 ( input C1, B1, A1, D0, A0, DI0, CE, CLK, output F0, Q0, F1 );
 
 endmodule
 
-module lut4 ( input A, B, C, D, output Z );
+module lut40005 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40003 ( input A, B, C, D, output Z );
+module lut40006 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_10 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, LSR, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly;
+module SLICE_11 ( input B1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40004 \CS_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40005 \CS_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  lut40007 \ram2e_ufm/RC_3_0_0_a3_1[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre0006 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
+  lut40008 \ram2e_ufm/N_360_i ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre \RC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40007 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40008 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1133) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_12 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly;
+
+  lut40009 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNI6S1P8 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40010 \ram2e_ufm/S_r_i_0_o2_RNIVM0LF[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0011 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre0006 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+  vmuxregsre0011 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
 
   specify
@@ -995,6 +1386,7 @@ module SLICE_10 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, LSR, CLK,
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     (CLK => Q1) = (0:0:0,0:0:0);
@@ -1009,30 +1401,31 @@ module SLICE_10 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, LSR, CLK,
 
 endmodule
 
-module lut40004 ( input A, B, C, D, output Z );
+module lut40009 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAAA6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40005 ( input A, B, C, D, output Z );
+module lut40010 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAAA5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0D0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q );
+module vmuxregsre0011 ( input D0, D1, SD, SP, CK, LSR, output Q );
 
   FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module SLICE_11 ( input D1, C1, B1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
+module SLICE_13 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;
 
-  lut40007 \CS_RNO_0[2] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40008 \CS_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0006 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+  lut40012 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 ( .A(A1), 
+    .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40013 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0011 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
@@ -1040,6 +1433,8 @@ module SLICE_11 ( input D1, C1, B1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0,
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1054,188 +1449,75 @@ module SLICE_11 ( input D1, C1, B1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0,
 
 endmodule
 
-module lut40007 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40008 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h6A6A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_12 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40009 CmdBitbangMXO2_4_u_0_0_a2_0_1( .A(A1), .B(B1), .C(GNDI), .D(D1), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40010 CmdBitbangMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdBitbangMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40009 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40010 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_13 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40011 un1_CS_0_sqmuxa_0_0_a2_7( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40012 CmdExecMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdExecMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40011 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
 module lut40012 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40013 CmdLEDGet_4_u_0_0_a2_0_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40014 CmdLEDGet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hC4C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40013 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA2A6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
+    Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40014 \ram2e_ufm/CmdLEDGet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40015 \ram2e_ufm/CmdLEDGet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40014 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_15 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, 
+module lut40015 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_15 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
     Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40015 CmdLEDSet_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40016 CmdLEDSet_4_u_0_0_0( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
+  lut40017 \ram2e_ufm/CmdLEDSet_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
   vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40015 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40016 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hF0FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_16 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40017 CmdBitbangMXO2_4_u_0_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(D1), 
-    .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40018 CmdRWMaskSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
@@ -1247,28 +1529,28 @@ module SLICE_16 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
+module lut40016 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
 module lut40017 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40018 ( input A, B, C, D, output Z );
+module SLICE_16 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
 
-  ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_17 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40019 CmdSetRWBankFFLED_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), 
-    .Z(F1));
-  lut40016 CmdSetRWBankFFLED_4_u_0_0_0( .A(A0), .B(GNDI), .C(C0), .D(D0), 
+  lut40018 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40019 \ram2e_ufm/CmdRWMaskSet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
-    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -1277,6 +1559,7 @@ module SLICE_17 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0,
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
@@ -1287,27 +1570,32 @@ module SLICE_17 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40019 ( input A, B, C, D, output Z );
+module lut40018 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_18 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
+module lut40019 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_17 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
     Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40020 CmdSetRWBankFFLED_4_u_0_0_a2_1( .A(A1), .B(GNDI), .C(C1), .D(D1), 
+  lut40020 \ram2e_ufm/CmdRWMaskSet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
     .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40018 CmdSetRWBankFFMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
-  vmuxregsre CmdSetRWBankFFMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+  lut40021 \ram2e_ufm/CmdSetRWBankFFLED_4_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
     .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
@@ -1324,15 +1612,20 @@ endmodule
 
 module lut40020 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_19 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output 
+module lut40021 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_18 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output 
     F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40021 \CmdTout_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40022 \CmdTout_RNO[1] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  lut40022 \ram2e_ufm/N_369_i ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40023 \ram2e_ufm/N_368_i ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
   vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
@@ -1359,110 +1652,74 @@ module SLICE_19 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output
 
 endmodule
 
-module lut40021 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1450) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
 module lut40022 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1144) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
-    Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly;
-
-  lut40023 \S_RNII9DO1_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40024 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre DOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h1222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40023 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1122) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40024 ( input A, B, C, D, output Z );
+module SLICE_19 ( input C1, A1, C0, A0, M0, LSR, CLK, output F0, Q0, F1 );
+  wire   GNDI, VCCI, M0_dly, CLK_dly, LSR_dly;
 
-  ROM16X1A #(16'hCC80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_21 ( input C1, B1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, 
-    F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40025 \RA_0io_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40024 \ram2e_ufm/SUM0_i_o2 ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40026 LEDEN_RNO( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  lut40025 \ram2e_ufm/RA_35_i_i_0_a3_0[1] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre0011 DOEEN( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
+module lut40024 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
 module lut40025 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hC8C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40026 ( input A, B, C, D, output Z );
+module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  ROM16X1A #(16'hEE44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_22 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40027 \RA_RNO[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40027 \RA_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40026 \ram2e_ufm/RA_35_i_i_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40027 \ram2e_ufm/RA_35_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \RA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
   vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     (CLK => Q1) = (0:0:0,0:0:0);
@@ -1475,30 +1732,36 @@ module SLICE_22 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40027 ( input A, B, C, D, output Z );
+module lut40026 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_23 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
+module lut40027 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFDF5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40028 \RWBank_5_0[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40028 \ram2e_ufm/RA_35_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40028 \RWBank_5_0[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40029 \ram2e_ufm/RA_35_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     (CLK => Q1) = (0:0:0,0:0:0);
@@ -1513,27 +1776,33 @@ endmodule
 
 module lut40028 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFF0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_24 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
+module lut40029 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_22 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40029 \RWBank_5_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40030 \ram2e_ufm/RA_35_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40031 \ram2e_ufm/RA_35_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40030 \RWBank_5_0[2] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
@@ -1547,35 +1816,37 @@ module SLICE_24 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40029 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
 module lut40030 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hBBAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_25 ( input C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, 
+module lut40031 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40029 \RWBank_5_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40031 \ram2e_ufm/RA_35_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40031 \RWBank_5_0[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40031 \ram2e_ufm/RA_35_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre \RA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     (CLK => Q1) = (0:0:0,0:0:0);
@@ -1588,28 +1859,25 @@ module SLICE_25 ( input C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40031 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hAAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_26 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
+module SLICE_24 ( input D1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
+    F0, Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40032 \RWBank_5_0_0[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40032 \ram2e_ufm/RA_35_0_0[9] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40033 \RWBank_5_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40033 \ram2e_ufm/un2_S_2_i_0_0_o3_RNIHFHN3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre \RA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1626,31 +1894,33 @@ endmodule
 
 module lut40032 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40033 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_27 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module SLICE_25 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40034 \RWMask_RNO[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40035 \RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40034 \ram2e_ufm/RA_35_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut4 \ram2e_ufm/RA_35_2_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \RA[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \RA[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -1667,32 +1937,27 @@ endmodule
 
 module lut40034 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h50FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40035 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h7272) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_28 ( input D1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+module SLICE_26 ( input D1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40036 \RWMask_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  lut40035 \ram2e_ufm/RC_3_0_0[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40035 \RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40036 \ram2e_ufm/RC_3_0_0[1] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre \RC[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RC[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
@@ -1706,27 +1971,33 @@ module SLICE_28 ( input D1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40036 ( input A, B, C, D, output Z );
+module lut40035 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h7722) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h6622) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_29 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+module lut40036 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h3344) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_27 ( input D1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40037 \RWMask_RNO[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40037 \ram2e_ufm/RWBank_3_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40035 \RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40038 \ram2e_ufm/RWBank_3_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -1744,25 +2015,72 @@ endmodule
 
 module lut40037 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h5F0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hCCEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_30 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+module lut40038 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_28 ( input C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, 
     Q0, F1, Q1 );
   wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40038 \RWMask_RNO[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40039 \ram2e_ufm/RWBank_3_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40035 \RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40040 \ram2e_ufm/RWBank_3_0[2] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40039 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40040 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40038 \ram2e_ufm/RWBank_3_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40038 \ram2e_ufm/RWBank_3_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -1778,23 +2096,61 @@ module SLICE_30 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40038 ( input A, B, C, D, output Z );
+module SLICE_30 ( input D1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40041 \ram2e_ufm/RWBank_3_0[7] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40042 \ram2e_ufm/RWBank_3_0[6] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
 
-  ROM16X1A #(16'hF5A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+module lut40041 ( input A, B, C, D, output Z );
 
-  lut40039 nDOE_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40040 RWSel_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'hFF88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40042 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFF44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
+    F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40043 \ram2e_ufm/RA_35_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40044 \ram2e_ufm/RWSel_2_0_a3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
   vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -1811,21 +2167,21 @@ module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
 
 endmodule
 
-module lut40039 ( input A, B, C, D, output Z );
+module lut40043 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40040 ( input A, B, C, D, output Z );
+module lut40044 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module SLICE_32 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
   wire   GNDI, VCCI, DI0_dly, CLK_dly;
 
-  lut40041 Ready_0_sqmuxa_0_a2_6_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40042 Ready_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  lut40045 \ram2e_ufm/Ready3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40046 Ready_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
   vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
@@ -1846,12 +2202,12 @@ module SLICE_32 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
 
 endmodule
 
-module lut40041 ( input A, B, C, D, output Z );
+module lut40045 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40042 ( input A, B, C, D, output Z );
+module lut40046 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
@@ -1860,8 +2216,9 @@ module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
     F0, Q0, F1, Q1 );
   wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
 
-  lut40043 \S_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40044 \S_s_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40047 \ram2e_ufm/S_r_i_0_o2_0_RNI36E21[1] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40048 \ram2e_ufm/S_s_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
   vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1888,22 +2245,24 @@ module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
 
 endmodule
 
-module lut40043 ( input A, B, C, D, output Z );
+module lut40047 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40044 ( input A, B, C, D, output Z );
+module lut40048 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output 
     F0, Q0, F1, Q1 );
   wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
 
-  lut40045 \S_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40046 \S_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40049 \ram2e_ufm/S_r_i_0_o2_RNIFNP81_0[2] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40050 \ram2e_ufm/S_r_i_0_o2_RNIFNP81[2] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
   vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
@@ -1930,178 +2289,27 @@ module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
 
 endmodule
 
-module lut40045 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40046 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2231) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40047 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40048 \wb_adr_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40047 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40048 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_36 ( input C1, B1, C0, B0, DI1, DI0, CE, CLK, output F0, Q0, F1, 
-    Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40049 \wb_adr_RNO[3] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40049 \wb_adr_RNO[2] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
 module lut40049 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_37 ( input C1, B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, 
-    Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40050 \wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40051 \wb_adr_RNO[4] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h2322) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40050 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h3203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40051 ( input A, B, C, D, output Z );
+module SLICE_35 ( input D1, C1, B1, A1, D0, A0, DI0, LSR, CLK, output F0, Q0, 
+    F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
 
-  ROM16X1A #(16'hF303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_38 ( input C1, B1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, Q0, 
-    F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40049 \wb_adr_RNO[7] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40051 \ram2e_ufm/CKE_7_m1_0_0_o2_RNICM8E1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40052 \ram2e_ufm/CKE_7_m1_0_0_o2 ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), 
+    .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40052 \wb_adr_RNO[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40052 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hCF03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_39 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
-    Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40053 wb_cyc_stb_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40054 wb_cyc_stb_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vmuxregsre0011 VOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
@@ -2109,12 +2317,53 @@ module SLICE_39 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40051 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40052 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
+
+  lut40053 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40054 \ram2e_ufm/nCAS_s_i_0_a3_RNIO1UQ3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0004 nCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
@@ -2123,26 +2372,26 @@ endmodule
 
 module lut40053 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40054 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
 
-  lut40055 \wb_dati_7_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40056 \wb_dati_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  lut40055 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40056 \ram2e_ufm/nRAS_s_i_0_0_RNI0PC64 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre0004 nRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
+    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2154,10 +2403,7 @@ module SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
@@ -2166,68 +2412,25 @@ endmodule
 
 module lut40055 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40056 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_41 ( input D1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module SLICE_38 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
+    Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly;
 
-  lut40057 \wb_dati_7_0[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40058 \wb_dati_7_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
+  lut40057 \ram2e_ufm/nRAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40058 \ram2e_ufm/nRAS_s_i_0_a3_0_RNIIR094 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre0004 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
     .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40057 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40058 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
-    output F0, Q0, F1, Q1 );
-  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
-
-  lut40058 \wb_dati_7_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40059 \wb_dati_7_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2239,8 +2442,46 @@ module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
     (CLK => Q0) = (0:0:0,0:0:0);
-    (CLK => Q1) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40057 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40058 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0013) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_39 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40059 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40021 \ram2e_ufm/CmdBitbangMXO2_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/CmdBitbangMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
     $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
@@ -2251,27 +2492,143 @@ endmodule
 
 module lut40059 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_43 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output 
-    F0, Q0, F1, Q1 );
-  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+module ram2e_ufm_SLICE_40 ( input D1, C1, B1, A1, C0, B0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40060 \wb_dati_7_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40061 \wb_dati_7_0[6] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  lut40060 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40061 \ram2e_ufm/CmdExecMXO2_3_0_a3 ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vmuxregsre \ram2e_ufm/CmdExecMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
   vcc DRIVEVCC( .PWR1(VCCI));
-  vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40060 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40061 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40062 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0_0 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40063 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/CmdSetRWBankFFChip ( .D0(VCCI), .D1(DI0_dly), 
+    .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40062 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40063 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_42 ( input D1, B1, A1, D0, C0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
+
+  lut40064 \ram2e_ufm/SUM1_0_o3_0 ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40065 \ram2e_ufm/LEDEN_RNO ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/LEDEN ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40064 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40065 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFA50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_43 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40066 \ram2e_ufm/RWMask_RNO[1] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40067 \ram2e_ufm/RWMask_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -2286,192 +2643,136 @@ module SLICE_43 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output
 
 endmodule
 
-module lut40060 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40061 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_44 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output 
-    F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
-
-  lut40062 wb_req_RNO_1( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40063 wb_req_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre0006 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge LSR, 0:0:0);
-    $width (negedge LSR, 0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40062 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40063 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_45 ( input C1, B1, C0, B0, DI0, LSR, CLK, output F0, Q0, F1 );
-  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
-
-  lut40064 \un1_LEDEN13_2_i_o2[0] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40065 wb_rst8_0_a2( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  vmuxregsre0006 wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
-    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
-    $width (posedge LSR, 0:0:0);
-    $width (negedge LSR, 0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module lut40064 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFCFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40065 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
-    F0, Q0, F1 );
-  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
-
-  lut40066 wb_we_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40067 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-  vmuxregsre wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
-    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-    (CLK => Q0) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
 module lut40066 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7722) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40067 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h50FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_44 ( input D1, B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40068 DQMH_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40069 \S_RNII9DO1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40066 \ram2e_ufm/RWMask_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40068 \ram2e_ufm/RWMask_RNO[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40068 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h33F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40069 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_45 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40070 Vout3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40071 nCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40066 \ram2e_ufm/RWMask_RNO[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40069 \ram2e_ufm/RWMask_RNO[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40069 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5F0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_46 ( input D1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40070 \ram2e_ufm/RWMask_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40066 \ram2e_ufm/RWMask_RNO[6] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40070 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hDD88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40071 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  ROM16X1A #(16'h88F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40072 un1_CS_0_sqmuxa_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40073 un1_CS_0_sqmuxa_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40071 \ram2e_ufm/wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40072 \ram2e_ufm/wb_adr_7_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2482,80 +2783,157 @@ module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
+module lut40071 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
 module lut40072 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_48 ( input B1, A1, C0, B0, DI1, DI0, CE, CLK, output F0, 
+    Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
+
+  lut40073 \ram2e_ufm/wb_adr_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40061 \ram2e_ufm/wb_adr_RNO[2] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
 endmodule
 
 module lut40073 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_49 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40074 \wb_dati_7_0_a2_0_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40075 \wb_dati_7_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40074 \ram2e_ufm/wb_adr_RNO[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40075 \ram2e_ufm/wb_adr_RNO[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40074 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h080A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h88DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40075 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAA02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA0F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_50 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, 
+    output F0, Q0, F1, Q1 );
+  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40076 CKE_6_iv_i_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40077 CKE_6_iv_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40076 \ram2e_ufm/wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40077 \ram2e_ufm/wb_adr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  vmuxregsre \ram2e_ufm/wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40076 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0FAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40077 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hB1B1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_51 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40078 \un1_LEDEN13_2_i_a2_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40079 \un1_LEDEN13_2_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40078 \ram2e_ufm/wb_cyc_stb_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40079 \ram2e_ufm/wb_cyc_stb_RNO ( .A(A0), .B(GNDI), .C(C0), .D(D0), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_cyc_stb ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2564,27 +2942,40 @@ module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40078 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h000E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40079 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40080 \un1_wb_adr_0_sqmuxa_2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+  lut40080 \ram2e_ufm/wb_dati_7_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
     .Z(F1));
-  lut40081 wb_we_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40081 \ram2e_ufm/wb_dati_7_0_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2595,24 +2986,41 @@ module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40080 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h67EF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40081 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0501) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40082 un1_CS_0_sqmuxa_0_0_a2_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40083 un1_CS_0_sqmuxa_0_0_o2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40082 \ram2e_ufm/wb_dati_7_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40083 \ram2e_ufm/wb_dati_7_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2623,24 +3031,41 @@ module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40082 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40083 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF0F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  lut40084 nCS_6_u_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40085 un1_nCS61_1_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40083 \ram2e_ufm/wb_dati_7_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40084 \ram2e_ufm/wb_dati_7_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre \ram2e_ufm/wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2651,52 +3076,36 @@ module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40084 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40085 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, 
+    CLK, output F0, Q0, F1, Q1 );
+  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
 
-  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_56 ( input D1, C1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40086 \wb_dati_7_0_a2_5[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40085 \ram2e_ufm/wb_dati_7_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40086 \ram2e_ufm/wb_dati_7_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
+  vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40087 \wb_dati_7_0_a2_6[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40086 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h000A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40087 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40088 \un1_LEDEN13_2_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40089 \S_RNII9DO1_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2707,24 +3116,113 @@ module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    (CLK => Q1) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40085 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40086 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, 
+    CLK, output F0, Q0, F1 );
+  wire   VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
+
+  lut40084 \ram2e_ufm/wb_reqc_1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40087 \ram2e_ufm/wb_req_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre0011 \ram2e_ufm/wb_req ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module lut40087 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h070F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_57 ( input D1, C1, B1, A1, D0, B0, DI0, LSR, CLK, 
+    output F0, Q0, F1 );
+  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
+
+  lut40088 \ram2e_ufm/Ready3_0_a3_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40089 \ram2e_ufm/wb_rst8_0_a3_0_a3 ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  vmuxregsre0011 \ram2e_ufm/wb_rst ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
+    $width (posedge LSR, 0:0:0);
+    $width (negedge LSR, 0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40088 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40089 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, 
+    output F0, Q0, F1 );
+  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
 
-  lut40090 \wb_dati_7_0_2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40091 \wb_dati_7_0_2_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40090 \ram2e_ufm/wb_we_RNO_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40091 \ram2e_ufm/wb_we_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  vmuxregsre \ram2e_ufm/wb_we ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
+    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2735,112 +3233,159 @@ module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
+    (CLK => Q0) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
 module lut40090 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40091 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SUM0_i_m3_0_SLICE_59 ( input D1, B1, A1, D0, B0, A0, M0, 
+    output OFX0 );
+  wire   GNDI, 
+         \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 , 
+         \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ;
 
-  lut40092 DQML_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40093 DQML_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40092 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1 ( .A(A1), .B(B1), .C(GNDI), 
+    .D(D1), 
+    .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40093 \ram2e_ufm/SUM0_i_m3_0/GATE ( .A(A0), .B(B0), .C(GNDI), .D(D0), 
+    .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ));
+  selmux2 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K0K1MUX ( 
+    .D0(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ), 
+    .D1(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ), 
+    .SD(M0), .Z(OFX0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40092 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h7737) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF77) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40093 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_60 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
-  wire   GNDI;
+module selmux2 ( input D0, D1, SD, output Z );
 
-  lut40094 \wb_adr_RNO_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40095 \wb_adr_RNO_3[1] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
+endmodule
+
+module ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 ( input D1, C1, B1, A1, C0, B0, 
+    A0, M0, output OFX0 );
+  wire   
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 
+         , GNDI, 
+         \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 
+         ;
+
+  lut40094 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), 
+    .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 )
+    );
+  lut40095 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE ( .A(A0), .B(B0), .C(C0), 
+    .D(GNDI), 
+    .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 )
+    );
   gnd DRIVEGND( .PWR0(GNDI));
+  selmux2 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K0K1MUX ( 
+    .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 )
+    , 
+    .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 )
+    , .SD(M0), .Z(OFX0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (B1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (C0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40094 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h2A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40095 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h5000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_61 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_CKE_7_SLICE_61 ( input D1, C1, A1, D0, B0, A0, M0, output 
+    OFX0 );
+  wire   GNDI, \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 , 
+         \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ;
 
-  lut40096 \wb_dati_7_0_a2_2_0[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40096 \ram2e_ufm/CKE_7/SLICE_61_K1 ( .A(A1), .B(GNDI), .C(C1), .D(D1), 
+    .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40097 \FS_RNIOD6E_1[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40097 \ram2e_ufm/CKE_7/GATE ( .A(A0), .B(B0), .C(GNDI), .D(D0), 
+    .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ));
+  selmux2 \ram2e_ufm/CKE_7/SLICE_61_K0K1MUX ( 
+    .D0(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ), 
+    .D1(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ), .SD(M0), 
+    .Z(OFX0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
+    (D1 => OFX0) = (0:0:0,0:0:0);
+    (C1 => OFX0) = (0:0:0,0:0:0);
+    (A1 => OFX0) = (0:0:0,0:0:0);
+    (D0 => OFX0) = (0:0:0,0:0:0);
+    (B0 => OFX0) = (0:0:0,0:0:0);
+    (A0 => OFX0) = (0:0:0,0:0:0);
+    (M0 => OFX0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40096 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h50FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40097 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_62 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40098 \wb_adr_RNO_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40099 \wb_adr_RNO_2[1] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40098 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIAJ811 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40099 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIPG3P2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -2848,6 +3393,7 @@ module SLICE_62 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
@@ -2861,21 +3407,23 @@ endmodule
 
 module lut40099 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8877) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40069 \un1_LEDEN13_2_i_o2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40100 \FS_RNI9FGA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
+  lut40100 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40101 \ram2e_ufm/S_r_i_0_o2_RNI3VQTC[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -2885,15 +3433,21 @@ endmodule
 
 module lut40100 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF0F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40101 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40101 \FS_RNI6JJA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40102 \ram2e_ufm/wb_adr_7_i_i_a3_6[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40102 \un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40103 \ram2e_ufm/wb_adr_7_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
 
   specify
@@ -2908,24 +3462,25 @@ module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40101 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
 module lut40102 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_65 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module lut40103 ( input A, B, C, D, output Z );
 
-  lut40103 \wb_dati_7_0_a2_0_0[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40104 \wb_dati_7_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40104 \ram2e_ufm/SUM0_i_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40100 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
@@ -2937,24 +3492,22 @@ module SLICE_65 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40103 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
 module lut40104 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h002A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_66 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40105 \FS_RNIJ9MH[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40106 wb_we_RNO_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40105 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40106 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -2967,24 +3520,25 @@ endmodule
 
 module lut40105 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40106 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h080C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hBBBA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_67 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40107 wb_reqc_1( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40107 \ram2e_ufm/nRAS_s_i_0_m3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40108 wb_reqc_1_RNIRU4M1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40108 \ram2e_ufm/nRAS_s_i_0_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -2995,18 +3549,21 @@ endmodule
 
 module lut40107 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40108 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFBFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40109 \wb_dati_7_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40110 \FS_RNIOD6E_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40109 \ram2e_ufm/wb_adr_7_i_i_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40110 \ram2e_ufm/wb_adr_7_i_i_3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3023,18 +3580,20 @@ endmodule
 
 module lut40109 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40110 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h01A1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40111 \RA_42_0[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40112 \RA_42_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40111 \ram2e_ufm/nCAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40112 \ram2e_ufm/wb_rst16_i_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3051,22 +3610,25 @@ endmodule
 
 module lut40111 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40112 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_70 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40113 \wb_dati_7_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40114 \FS_RNIOD6E[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40113 \ram2e_ufm/wb_dati_7_0_0_a3_12[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40114 \ram2e_ufm/wb_dati_7_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
@@ -3079,27 +3641,29 @@ endmodule
 
 module lut40113 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40114 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h6A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h80A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_71 ( input D1, C1, A1, D0, C0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40115 nRWE_r_0_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40116 \S_RNII9DO1_3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40115 \ram2e_ufm/RA_35_0_0_a3_4[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40116 \ram2e_ufm/nRAS_s_i_0_a3_4 ( .A(A0), .B(GNDI), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
@@ -3107,18 +3671,21 @@ endmodule
 
 module lut40115 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00DF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40116 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_72 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40117 Ready_0_sqmuxa_0_a2_6_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40118 \FS_RNI5OOF1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40117 \ram2e_ufm/BA_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40118 \ram2e_ufm/un1_RC12_i_0_o3 ( .A(A0), .B(B0), .C(GNDI), .D(D0), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3126,7 +3693,6 @@ module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
@@ -3135,18 +3701,21 @@ endmodule
 
 module lut40117 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40118 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40119 \wb_adr_7_0_a2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40120 \FS_RNIK5632[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40119 \ram2e_ufm/wb_dati_7_0_0_o3_0[2] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40120 \ram2e_ufm/wb_dati_7_0_0_a3_3[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3163,7 +3732,7 @@ endmodule
 
 module lut40119 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40120 ( input A, B, C, D, output Z );
@@ -3171,18 +3740,19 @@ module lut40120 ( input A, B, C, D, output Z );
   ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_74 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_74 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40121 \wb_dati_7_0_a2_5[4] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40121 \ram2e_ufm/RA_35_2_0_0[10] ( .A(A1), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40104 \wb_dati_7_0_a2_5_RNIC22J[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40122 \ram2e_ufm/RA_35_2_0_a3_5[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -3193,95 +3763,56 @@ endmodule
 
 module lut40121 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_75 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40110 nCS_6_u_i_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut4 nCS_6_u_i_a2_4_RNI3A062( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_76 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40122 nCS_6_u_i_o2_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40123 nCS_6_u_i_a2_4_RNICJKD2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hFAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40122 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40123 \ram2e_ufm/wb_dati_7_0_0_a3_15[7] ( .A(A1), .B(B1), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40124 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0] ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40123 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_77 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40124 un1_CS_0_sqmuxa_0_0_a2_10( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40125 un1_CS_0_sqmuxa_0_0_2_RNIQS7F( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40124 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40125 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_78 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40122 nCAS_s_i_o2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
+  lut40125 \ram2e_ufm/wb_dati_7_0_0_a3_13[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40126 nCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40126 \ram2e_ufm/wb_dati_7_0_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
@@ -3291,23 +3822,29 @@ module SLICE_78 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40126 ( input A, B, C, D, output Z );
+module lut40125 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hABBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_79 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
+module lut40126 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_77 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40127 nCS_6_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40128 nCS_0io_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
+  lut40127 \ram2e_ufm/SUM2_0_o2 ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
+  lut40128 \ram2e_ufm/N_314_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
@@ -3316,25 +3853,27 @@ endmodule
 
 module lut40127 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0122) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF3FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40128 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_80 ( input D1, B1, A1, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_78 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40129 nRAS_2_iv_0_a2_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
+  lut40129 \ram2e_ufm/S_r_i_0_o2[1] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40130 nRAS_2_iv_i( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40130 \ram2e_ufm/S_r_i_0_o2_RNIP4KI1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -3344,18 +3883,21 @@ endmodule
 
 module lut40129 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1144) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40130 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_79 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40131 un1_CS_0_sqmuxa_0_0_a2_1_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40132 un1_CS_0_sqmuxa_0_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40131 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40132 \ram2e_ufm/S_r_i_0_o2_RNIOGTF1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3372,18 +3914,21 @@ endmodule
 
 module lut40131 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8F88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40132 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40133 un1_CS_0_sqmuxa_0_0_a2_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40134 un1_CS_0_sqmuxa_0_0_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40133 \ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40134 \ram2e_ufm/CmdBitbangMXO2_RNINSM62 ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3400,18 +3945,21 @@ endmodule
 
 module lut40133 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h070F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40134 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40135 nCS_6_u_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40136 nCS_6_u_i_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40135 \ram2e_ufm/wb_dati_7_0_0_a3_14[7] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40136 \ram2e_ufm/wb_dati_7_0_0_a3_13_RNI81UL[7] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3428,18 +3976,21 @@ endmodule
 
 module lut40135 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40136 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40137 \wb_dati_7_0_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40138 \wb_dati_7_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40137 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40051 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3456,18 +4007,47 @@ endmodule
 
 module lut40137 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_83 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40138 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ( .A(GNDI), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40139 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40138 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40139 ( input A, B, C, D, output Z );
 
-  lut40139 \wb_adr_7_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40140 \wb_adr_7_0_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'hC040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40140 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40141 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3482,20 +4062,165 @@ module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40139 ( input A, B, C, D, output Z );
+module lut40140 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hCC08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40140 ( input A, B, C, D, output Z );
+module lut40141 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5510) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40142 \ram2e_ufm/wb_dati_7_0_0_a3_10[7] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40143 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40142 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40143 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_86 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40025 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_1 ( .A(A1), .B(GNDI), .C(C1), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40144 \ram2e_ufm/wb_adr_7_i_i_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40144 ( input A, B, C, D, output Z );
 
   ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40141 \wb_dati_7_0_a2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40142 \un1_LEDEN_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+  lut40145 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91 ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40146 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_m3 ( .A(A0), .B(B0), .C(C0), 
+    .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40145 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40146 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hB1B1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40147 \ram2e_ufm/wb_dati_7_0_0_a3_4_1_0[7] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40148 \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40147 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40148 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAA80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_89 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40149 \ram2e_ufm/wb_dati_7_0_0_a3_7[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40081 \ram2e_ufm/wb_dati_7_0_0_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40149 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40150 \ram2e_ufm/wb_dati_7_0_0_a3_1_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40151 \ram2e_ufm/wb_dati_7_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
 
   specify
@@ -3511,158 +4236,21 @@ module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40141 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40142 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40143 un1_CS_0_sqmuxa_0_0_a2_4_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40144 un1_CS_0_sqmuxa_0_0_a2_4( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40143 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40144 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_88 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40145 \FS_RNI9Q57[13] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40146 \wb_dati_7_0_o2_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40145 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFF55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40146 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_89 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40122 \wb_adr_7_0_o2[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40147 \wb_adr_7_0_a2_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40147 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40148 \wb_dati_7_0_o2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40149 \wb_dati_7_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40148 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40149 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_91 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40150 un1_CS_0_sqmuxa_0_0_a2_2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40151 un1_CS_0_sqmuxa_0_0_a2_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
 module lut40150 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0401) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40151 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40152 \wb_adr_7_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40153 \wb_adr_7_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40152 \ram2e_ufm/nRAS_s_i_0_a3_8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40153 \ram2e_ufm/nRAS_s_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3679,18 +4267,19 @@ endmodule
 
 module lut40152 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h4450) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40153 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40154 un1_CS_0_sqmuxa_0_0_a2_1_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40098 un1_CS_0_sqmuxa_0_0_a2_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40154 \ram2e_ufm/CKE_7s2_0_0_o3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40155 \ram2e_ufm/nCAS_s_i_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -3707,43 +4296,28 @@ endmodule
 
 module lut40154 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40155 un1_CS_0_sqmuxa_0_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40093 un1_CS_0_sqmuxa_0_0_a2_3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h4E0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40155 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_93 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40156 wb_we_RNO_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40157 wb_we_RNO_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40156 \ram2e_ufm/wb_dati_7_0_0_o2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40016 \ram2e_ufm/wb_dati_7_0_0_a3[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -3753,82 +4327,50 @@ endmodule
 
 module lut40156 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h6888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_94 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40157 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ( .A(GNDI), .B(GNDI), .C(C1), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40158 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ( .A(A0), .B(B0), .C(C0), 
+    .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40157 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_96 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40158 \RA_42_i_o2[8] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40159 \RA_0io_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'hF0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40158 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hEEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40159 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  ROM16X1A #(16'h0B08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_97 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40160 \wb_dati_7_0_a2_1[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40161 CKE_6_iv_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40160 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40161 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_98 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40162 un1_CS_0_sqmuxa_0_0_a2_16( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40163 un1_CS_0_sqmuxa_0_0_a2_4_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40159 \ram2e_ufm/RA_35_0_0_o2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40160 \ram2e_ufm/RA_35_0_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -3837,27 +4379,85 @@ module SLICE_98 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
+module lut40159 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40160 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40161 \ram2e_ufm/RA_35_0_0_o2_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40162 \ram2e_ufm/RA_35_0_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40161 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0326) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
 module lut40162 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_97 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40163 \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ( .A(A1), .B(GNDI), .C(C1), 
+    .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40151 \ram2e_ufm/wb_dati_7_0_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
 endmodule
 
 module lut40163 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_99 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_98 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40164 un1_CS_0_sqmuxa_0_0_a2_12( .A(GNDI), .B(B1), .C(GNDI), .D(D1), 
-    .Z(F1));
+  lut40164 \ram2e_ufm/wb_dati_7_0_0_a3_9[7] ( .A(GNDI), .B(GNDI), .C(C1), 
+    .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40143 un1_CS_0_sqmuxa_0_0_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40165 \ram2e_ufm/wb_dati_7_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -3868,48 +4468,88 @@ endmodule
 
 module lut40164 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h00F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_100 ( input C1, B1, A1, D0, C0, B0, output F0, F1 );
+module lut40165 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_99 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40165 un1_CS_0_sqmuxa_0_0_a2_17( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40166 \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ( .A(A1), .B(B1), .C(GNDI), 
+    .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40166 CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0( .A(GNDI), .B(B0), .C(C0), .D(D0), 
+  lut40167 \ram2e_ufm/wb_adr_7_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40166 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40167 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40168 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40169 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R ( .A(A0), .B(B0), 
+    .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40168 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40169 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF7B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_101 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40170 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3 ( .A(GNDI), .B(B1), 
+    .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40171 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40165 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40166 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40167 wb_reqc_1_RNIEO5C1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40168 \S_RNII9DO1_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -3918,102 +4558,28 @@ module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40167 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module lut40168 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'hD821) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40169 \S_s_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40170 \BA_0io_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module lut40169 ( input A, B, C, D, output Z );
-
-  ROM16X1A #(16'h8F0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
 module lut40170 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40156 \RA_0io_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40134 wb_req_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40171 \wb_dati_7_0_a2_3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40172 \wb_adr_7_0_a2_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40171 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h88B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40172 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_102 ( input D1, C1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  ROM16X1A #(16'hA0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40173 \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+  lut40172 \ram2e_ufm/CKE_7s2_0_0_a2_1 ( .A(A1), .B(GNDI), .C(C1), .D(D1), 
     .Z(F1));
-  lut40070 \wb_dati_7_0_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40173 \ram2e_ufm/CKE_7s2_0_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -4021,21 +4587,28 @@ module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
 
 endmodule
 
-module lut40173 ( input A, B, C, D, output Z );
+module lut40172 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_106 ( input C1, B1, C0, B0, A0, output F0, F1 );
+module lut40173 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_103 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40174 \S_RNINI6S[1] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40174 \ram2e_ufm/wb_dati_7_0_0_0_o2[7] ( .A(A1), .B(GNDI), .C(GNDI), 
+    .D(D1), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40175 CKE_6_iv_i_0_1_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40175 \ram2e_ufm/wb_adr_RNO_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
+    (D1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
@@ -4045,70 +4618,51 @@ endmodule
 
 module lut40174 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hAAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40175 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0C88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_107 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_104 ( input D1, C1, B1, A1, C0, B0, output F0, F1 );
   wire   GNDI;
 
-  lut40176 \S_r_i_o2[1] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  lut40176 \ram2e_ufm/wb_dati_7_0_0_o2_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40177 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ( .A(GNDI), .B(B0), .C(C0), 
+    .D(GNDI), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40023 \BA_0io_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40176 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_108 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-  wire   GNDI;
-
-  lut40177 \wb_adr_7_0_a2_5_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40178 \wb_dati_7_0_a2[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
-
-  specify
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (D0 => F0) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
+  ROM16X1A #(16'h28A4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40177 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module lut40178 ( input A, B, C, D, output Z );
+module ram2e_ufm_SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
 
-  ROM16X1A #(16'h8200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
-endmodule
-
-module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40179 \wb_dati_7_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40179 \wb_dati_7_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40178 \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40179 \ram2e_ufm/N_285_i ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
@@ -4118,25 +4672,31 @@ module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module lut40179 ( input A, B, C, D, output Z );
+module lut40178 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+module lut40179 ( input A, B, C, D, output Z );
 
-  lut40180 \RA_0io_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40181 CmdBitbangMXO2_RNI8CSO1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  ROM16X1A #(16'h00CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_106 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40180 \ram2e_ufm/S_r_i_0_o2[2] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40181 \ram2e_ufm/RA_35_2_0_a3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (D1 => F1) = (0:0:0,0:0:0);
     (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
@@ -4148,26 +4708,29 @@ endmodule
 
 module lut40180 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40181 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_111 ( input D1, B1, A1, D0, B0, A0, output F0, F1 );
-  wire   GNDI;
+module ram2e_ufm_SLICE_107 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
 
-  lut40182 \RA_42_3_0[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
-  gnd DRIVEGND( .PWR0(GNDI));
-  lut40183 \RA_0io_RNO[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+  lut40182 \ram2e_ufm/CKE_7_m1_0_0_o2_RNIGC501 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40183 \ram2e_ufm/RA_35_i_i_0_a3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
@@ -4176,19 +4739,21 @@ endmodule
 
 module lut40182 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAABB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40183 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAA88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hE040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_112 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_108 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
   wire   GNDI;
 
-  lut40184 nCS_6_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40185 \RA_0io_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40184 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3[0] ( .A(A1), .B(B1), 
+    .C(C1), .D(D1), .Z(F1));
+  lut40185 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ( .A(GNDI), 
+    .B(B0), .C(C0), .D(D0), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
@@ -4196,51 +4761,33 @@ module SLICE_112 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
     (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40184 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40185 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0F03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_109 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40025 \RA_0io_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  lut40186 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_6 ( .A(A1), .B(GNDI), .C(C1), 
+    .D(GNDI), .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40025 \RA_0io_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+  lut40187 \ram2e_ufm/wb_we_RNO_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
-    (A1 => F1) = (0:0:0,0:0:0);
-    (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
-
-  lut40186 \wb_dati_7_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40187 \un1_RWMask_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
-
-  specify
-    (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
-    (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
@@ -4252,51 +4799,56 @@ endmodule
 
 module lut40186 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40187 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_110 ( input D1, C1, B1, A1, D0, C0, output F0, F1 );
   wire   GNDI;
 
-  lut40188 nWE80_pad_RNI3ICD( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  lut40188 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_7 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40189 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ( .A(GNDI), .B(GNDI), 
+    .C(C0), .D(D0), .Z(F0));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40189 nRWE_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
-    (B0 => F0) = (0:0:0,0:0:0);
-    (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module lut40188 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40189 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h0F08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_116 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_111 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40190 \wb_adr_7_0_o2_2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
+  lut40190 \ram2e_ufm/wb_dati_7_0_0_a3_2[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40191 \wb_dati_7_0_a2_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+  lut40191 \ram2e_ufm/wb_dati_7_0_0_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
 
   specify
-    (B1 => F1) = (0:0:0,0:0:0);
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
@@ -4308,27 +4860,29 @@ endmodule
 
 module lut40190 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40191 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h4080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h8380) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_117 ( input D1, C1, B1, A1, C0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_112 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40192 \RWBank_5_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
-  lut40193 LED_pad_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
+  lut40192 \ram2e_ufm/nRAS_s_i_0_a3_6 ( .A(A1), .B(B1), .C(GNDI), .D(D1), 
+    .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
+  lut40193 \ram2e_ufm/nRAS_s_i_0_a3_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
     (B1 => F1) = (0:0:0,0:0:0);
     (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
 
@@ -4336,26 +4890,29 @@ endmodule
 
 module lut40192 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h1100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40193 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'hAFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_118 ( input D1, C1, B0, A0, output F0, F1 );
+module ram2e_ufm_SLICE_113 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
   wire   GNDI;
 
-  lut40194 un1_CS_0_sqmuxa_0_0_a2_11( .A(GNDI), .B(GNDI), .C(C1), .D(D1), 
+  lut40194 \ram2e_ufm/nRAS_s_i_0_a3_5 ( .A(A1), .B(B1), .C(GNDI), .D(D1), 
     .Z(F1));
   gnd DRIVEGND( .PWR0(GNDI));
-  lut40195 un1_CS_0_sqmuxa_0_0_a2_13( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
+  lut40195 \ram2e_ufm/RA_35_2_0_a3_3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
     .Z(F0));
 
   specify
     (D1 => F1) = (0:0:0,0:0:0);
-    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
     (A0 => F0) = (0:0:0,0:0:0);
   endspecify
@@ -4364,20 +4921,26 @@ endmodule
 
 module lut40194 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h0022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
 module lut40195 ( input A, B, C, D, output Z );
 
-  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
-module SLICE_119 ( input D0, C0, B0, A0, output F0 );
+module ram2e_ufm_SLICE_114 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
 
-  lut40196 Ready_0_sqmuxa_0_a2_6_a2_2_0( .A(A0), .B(B0), .C(C0), .D(D0), 
-    .Z(F0));
+  lut40196 \ram2e_ufm/wb_adr_RNO_2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40197 \ram2e_ufm/wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
 
   specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
     (D0 => F0) = (0:0:0,0:0:0);
     (C0 => F0) = (0:0:0,0:0:0);
     (B0 => F0) = (0:0:0,0:0:0);
@@ -4388,9 +4951,929 @@ endmodule
 
 module lut40196 ( input A, B, C, D, output Z );
 
+  ROM16X1A #(16'h8787) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40197 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_115 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40198 \ram2e_ufm/un2_S_2_i_0_0_o3 ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40199 \ram2e_ufm/CKE_7s2_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40198 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40199 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_116 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40200 \ram2e_ufm/CmdExecMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40201 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ( .A(A0), .B(B0), 
+    .C(C0), .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40200 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40201 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_117 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40202 \ram2e_ufm/S_s_0_0_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40203 \ram2e_ufm/N_225_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40202 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5554) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40203 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_118 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40204 \ram2e_ufm/CKE_7_m1_0_0_o2_RNI7FOA1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40205 \ram2e_ufm/N_201_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40204 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40205 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_119 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40206 \ram2e_ufm/S_r_i_0_o2_RNIBAU51[1] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40207 \ram2e_ufm/un1_CKE75_0_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40206 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40207 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hE36F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_120 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40208 \ram2e_ufm/DQMH_4_iv_0_0_i_i_a3_0_a3 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40209 \ram2e_ufm/N_507_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40208 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40209 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_121 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40210 \ram2e_ufm/Vout3_0_a3_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40211 \ram2e_ufm/RA_35_0_0_o2[11] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40210 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40211 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFFE0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_122 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40212 \ram2e_ufm/nRWE_s_i_0_63_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40213 \ram2e_ufm/nCAS_s_i_0_m2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40212 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h75FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40213 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5F6E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_123 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40214 \ram2e_ufm/wb_adr_RNO_3[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40215 \ram2e_ufm/wb_dati_7_0_0_a3_8[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40214 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h3FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40215 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_124 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40216 \ram2e_ufm/RA_35_0_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40217 \ram2e_ufm/RA_35_0_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40216 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h40CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40217 ( input A, B, C, D, output Z );
+
   ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
 endmodule
 
+module ram2e_ufm_SLICE_125 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40218 \ram2e_ufm/wb_adr_7_i_i_o2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40219 \ram2e_ufm/wb_dati_7_0_0_a3_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40218 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5CFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40219 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_126 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40220 \ram2e_ufm/wb_we_RNO_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40221 \ram2e_ufm/wb_adr_7_i_i_a3_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40220 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h2BAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40221 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_127 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40222 \ram2e_ufm/un9_VOEEN_0_a2_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40223 \ram2e_ufm/RA_35_2_30_a3_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40222 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40223 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_128 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40224 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40225 \ram2e_ufm/wb_adr_RNO_4[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40224 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40225 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40226 \ram2e_ufm/BA_4[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40227 \ram2e_ufm/RA_35_2_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40226 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hA0A2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40227 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_130 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40228 \ram2e_ufm/N_187_i ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40229 \ram2e_ufm/wb_we_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40228 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40229 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_131 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40230 \ram2e_ufm/Ready3_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40231 \ram2e_ufm/wb_dati_7_0_0_0_a3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40230 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40231 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_132 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40232 \ram2e_ufm/RA_35_0_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40233 \ram2e_ufm/RA_35_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40232 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40233 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_133 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40234 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ( .A(A1), .B(B1), .C(C1), 
+    .D(D1), .Z(F1));
+  lut40127 \ram2e_ufm/SUM0_i_o2_2 ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40234 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_134 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40184 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ( .A(A1), 
+    .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40235 \ram2e_ufm/RA_35_0_0_a3[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40235 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hA808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_135 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40236 \ram2e_ufm/S_r_i_0_o2_0[1] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40237 \ram2e_ufm/RA_35_2_0_a3_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40236 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40237 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_136 ( input D1, C1, B1, C0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40238 \ram2e_ufm/nRAS_s_i_0_o2 ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40239 \ram2e_ufm/un1_nDOE_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40238 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h0F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40239 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_137 ( input D1, C1, A1, D0, C0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40240 \ram2e_ufm/RDOE_i ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40241 \ram2e_ufm/LEDEN_RNI6G6M ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40240 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAAA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40241 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hF5FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_138 ( input C1, B1, A1, D0, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40242 VOEEN_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40243 DOEEN_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40242 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40243 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h003F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module SLICE_139 ( input C1, A1, D0, B0, A0, output F0, F1 );
+  wire   GNDI;
+
+  lut40244 nVOE_pad_RNO( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40245 S_1( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40244 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hAFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40245 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h2200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_140 ( input C1, A1, D0, C0, output F0, F1 );
+  wire   GNDI;
+
+  lut40025 \ram2e_ufm/RA_35_0_0_a3_0[2] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40189 \ram2e_ufm/RA_35_0_0_a3[5] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), 
+    .Z(F0));
+
+  specify
+    (C1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_141 ( input D1, C1, D0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40189 \ram2e_ufm/RDout_i_0_i_a3[0] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40246 \ram2e_ufm/N_263_i ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40246 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_142 ( input D1, C1, B1, D0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40247 \ram2e_ufm/CmdLEDGet_3_0_a3_1 ( .A(GNDI), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40248 \ram2e_ufm/RDout_i_i_a3[4] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40247 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40248 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_143 ( input D1, B1, D0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40248 \ram2e_ufm/RDout_i_0_i_a3[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40248 \ram2e_ufm/RDout_i_0_i_a3[7] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), 
+    .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_144 ( input B1, A1, D0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40073 \ram2e_ufm/RDout_i_0_i_a3[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
+    .Z(F1));
+  gnd DRIVEGND( .PWR0(GNDI));
+  lut40248 \ram2e_ufm/RDout_i_0_i_a3[6] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), 
+    .Z(F0));
+
+  specify
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module ram2e_ufm_SLICE_145 ( input D1, C1, B1, A1, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40249 \ram2e_ufm/wb_dati_7_0_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40250 \ram2e_ufm/wb_dati_7_0_0_o2_0[7] ( .A(GNDI), .B(B0), .C(C0), 
+    .D(GNDI), .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40249 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module lut40250 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hCFCF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_146 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, 
+    F1 );
+
+  lut40251 \ram2e_ufm/RA_35_0_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
+  lut40188 \ram2e_ufm/Ready3_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (D0 => F0) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+    (A0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40251 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hA0EC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
+module ram2e_ufm_SLICE_147 ( input D1, C1, B1, A1, C0, B0, output F0, F1 );
+  wire   GNDI;
+
+  lut40252 \ram2e_ufm/RWBank_3_0_0_o3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
+    .Z(F1));
+  lut40061 \ram2e_ufm/RDout_i_0_i_a3[5] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), 
+    .Z(F0));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (D1 => F1) = (0:0:0,0:0:0);
+    (C1 => F1) = (0:0:0,0:0:0);
+    (B1 => F1) = (0:0:0,0:0:0);
+    (A1 => F1) = (0:0:0,0:0:0);
+    (C0 => F0) = (0:0:0,0:0:0);
+    (B0 => F0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module lut40252 ( input A, B, C, D, output Z );
+
+  ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
+endmodule
+
 module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
 
   xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
@@ -4413,7 +5896,7 @@ endmodule
 
 module LED ( input PADDO, output LED );
 
-  xo2iobuf0197 LED_pad( .I(PADDO), .PAD(LED));
+  xo2iobuf0253 LED_pad( .I(PADDO), .PAD(LED));
 
   specify
     (PADDO => LED) = (0:0:0,0:0:0);
@@ -4421,14 +5904,14 @@ module LED ( input PADDO, output LED );
 
 endmodule
 
-module xo2iobuf0197 ( input I, output PAD );
+module xo2iobuf0253 ( input I, output PAD );
 
   OB INST5( .I(I), .O(PAD));
 endmodule
 
 module C14M ( output PADDI, input C14M );
 
-  xo2iobuf0198 C14M_pad( .Z(PADDI), .PAD(C14M));
+  xo2iobuf0254 C14M_pad( .Z(PADDI), .PAD(C14M));
 
   specify
     (C14M => PADDI) = (0:0:0,0:0:0);
@@ -4438,71 +5921,11 @@ module C14M ( output PADDI, input C14M );
 
 endmodule
 
-module xo2iobuf0198 ( output Z, input PAD );
+module xo2iobuf0254 ( output Z, input PAD );
 
   IB INST1( .I(PAD), .O(Z));
 endmodule
 
-module DQMH ( input IOLDO, output DQMH );
-
-  xo2iobuf0197 DQMH_pad( .I(IOLDO), .PAD(DQMH));
-
-  specify
-    (IOLDO => DQMH) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module DQMH_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre DQMH_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module mfflsre ( input D0, SP, CK, LSR, output Q );
-
-  FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
-  defparam INST01.GSR = "DISABLED";
-endmodule
-
-module DQML ( input IOLDO, output DQML );
-
-  xo2iobuf0197 DQML_pad( .I(IOLDO), .PAD(DQML));
-
-  specify
-    (IOLDO => DQML) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module DQML_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre DQML_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
 module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
 
   xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
@@ -4601,305 +6024,416 @@ module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
 
 endmodule
 
-module RA_11_ ( input IOLDO, output RA11 );
+module DQMH ( input IOLDO, output DQMH );
 
-  xo2iobuf0197 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));
+  xo2iobuf0253 DQMH_pad( .I(IOLDO), .PAD(DQMH));
 
   specify
-    (IOLDO => RA11) = (0:0:0,0:0:0);
+    (IOLDO => DQMH) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_11__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module DQMH_MGIOL ( output IOLDO, input OPOS, CE, CLK );
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0199 \RA_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre DQMH_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), 
     .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
   endspecify
 
 endmodule
 
-module mfflsre0199 ( input D0, SP, CK, LSR, output Q );
+module mfflsre ( input D0, SP, CK, LSR, output Q );
+
+  FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
+  defparam INST01.GSR = "DISABLED";
+endmodule
+
+module DQML ( input IOLDO, output DQML );
+
+  xo2iobuf0253 DQML_pad( .I(IOLDO), .PAD(DQML));
+
+  specify
+    (IOLDO => DQML) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module DQML_MGIOL ( output IOLDO, input OPOS, CE, CLK );
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+
+  mfflsre DQML_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), 
+    .Q(IOLDO));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_11_ ( input IOLDO, output RAout11 );
+
+  xo2iobuf0253 \RAout_pad[11] ( .I(IOLDO), .PAD(RAout11));
+
+  specify
+    (IOLDO => RAout11) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_11__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0255 \RAout_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+  endspecify
+
+endmodule
+
+module mfflsre0255 ( input D0, SP, CK, LSR, output Q );
 
   FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module RA_10_ ( input IOLDO, output RA10 );
+module inverter ( input I, output Z );
 
-  xo2iobuf0197 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));
+  INV INST1( .A(I), .Z(Z));
+endmodule
+
+module RAout_10_ ( input IOLDO, output RAout10 );
+
+  xo2iobuf0253 \RAout_pad[10] ( .I(IOLDO), .PAD(RAout10));
 
   specify
-    (IOLDO => RA10) = (0:0:0,0:0:0);
+    (IOLDO => RAout10) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_10__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_10__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0199 \RA_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0255 \RAout_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_9_ ( input IOLDO, output RA9 );
+module RAout_9_ ( input IOLDO, output RAout9 );
 
-  xo2iobuf0197 \RA_pad[9] ( .I(IOLDO), .PAD(RA9));
+  xo2iobuf0253 \RAout_pad[9] ( .I(IOLDO), .PAD(RAout9));
 
   specify
-    (IOLDO => RA9) = (0:0:0,0:0:0);
+    (IOLDO => RAout9) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_9__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_9__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0199 \RA_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0255 \RAout_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_8_ ( input IOLDO, output RA8 );
+module RAout_8_ ( input IOLDO, output RAout8 );
 
-  xo2iobuf0197 \RA_pad[8] ( .I(IOLDO), .PAD(RA8));
+  xo2iobuf0253 \RAout_pad[8] ( .I(IOLDO), .PAD(RAout8));
 
   specify
-    (IOLDO => RA8) = (0:0:0,0:0:0);
+    (IOLDO => RAout8) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_8__MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module RAout_8__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0199 \RA_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
+  mfflsre0255 \RAout_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_7_ ( input IOLDO, output RA7 );
+module RAout_7_ ( input IOLDO, output RAout7 );
 
-  xo2iobuf0197 \RA_pad[7] ( .I(IOLDO), .PAD(RA7));
+  xo2iobuf0253 \RAout_pad[7] ( .I(IOLDO), .PAD(RAout7));
 
   specify
-    (IOLDO => RA7) = (0:0:0,0:0:0);
+    (IOLDO => RAout7) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_7__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0199 \RA_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0255 \RAout_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_6_ ( input IOLDO, output RA6 );
+module RAout_6_ ( input IOLDO, output RAout6 );
 
-  xo2iobuf0197 \RA_pad[6] ( .I(IOLDO), .PAD(RA6));
+  xo2iobuf0253 \RAout_pad[6] ( .I(IOLDO), .PAD(RAout6));
 
   specify
-    (IOLDO => RA6) = (0:0:0,0:0:0);
+    (IOLDO => RAout6) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_6__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0199 \RA_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0255 \RAout_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_5_ ( input IOLDO, output RA5 );
+module RAout_5_ ( input IOLDO, output RAout5 );
 
-  xo2iobuf0197 \RA_pad[5] ( .I(IOLDO), .PAD(RA5));
+  xo2iobuf0253 \RAout_pad[5] ( .I(IOLDO), .PAD(RAout5));
 
   specify
-    (IOLDO => RA5) = (0:0:0,0:0:0);
+    (IOLDO => RAout5) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_5__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0199 \RA_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0255 \RAout_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_4_ ( input IOLDO, output RA4 );
+module RAout_4_ ( input IOLDO, output RAout4 );
 
-  xo2iobuf0197 \RA_pad[4] ( .I(IOLDO), .PAD(RA4));
+  xo2iobuf0253 \RAout_pad[4] ( .I(IOLDO), .PAD(RAout4));
 
   specify
-    (IOLDO => RA4) = (0:0:0,0:0:0);
+    (IOLDO => RAout4) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_4__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0199 \RA_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0255 \RAout_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_3_ ( input PADDO, output RA3 );
+module RAout_3_ ( input IOLDO, output RAout3 );
 
-  xo2iobuf0197 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
+  xo2iobuf0253 \RAout_pad[3] ( .I(IOLDO), .PAD(RAout3));
 
   specify
-    (PADDO => RA3) = (0:0:0,0:0:0);
+    (IOLDO => RAout3) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_2_ ( input IOLDO, output RA2 );
+module RAout_3__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  xo2iobuf0197 \RA_pad[2] ( .I(IOLDO), .PAD(RA2));
-
-  specify
-    (IOLDO => RA2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module RA_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0199 \RA_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0255 \RAout_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_1_ ( input IOLDO, output RA1 );
+module RAout_2_ ( input IOLDO, output RAout2 );
 
-  xo2iobuf0197 \RA_pad[1] ( .I(IOLDO), .PAD(RA1));
+  xo2iobuf0253 \RAout_pad[2] ( .I(IOLDO), .PAD(RAout2));
 
   specify
-    (IOLDO => RA1) = (0:0:0,0:0:0);
+    (IOLDO => RAout2) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module RA_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
+module RAout_2__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre0199 \RA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
+  mfflsre0255 \RAout_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
     .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module RA_0_ ( input PADDO, output RA0 );
+module RAout_1_ ( input IOLDO, output RAout1 );
 
-  xo2iobuf0197 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
+  xo2iobuf0253 \RAout_pad[1] ( .I(IOLDO), .PAD(RAout1));
 
   specify
-    (PADDO => RA0) = (0:0:0,0:0:0);
+    (IOLDO => RAout1) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_1__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0255 \RAout_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+  endspecify
+
+endmodule
+
+module RAout_0_ ( input IOLDO, output RAout0 );
+
+  xo2iobuf0253 \RAout_pad[0] ( .I(IOLDO), .PAD(RAout0));
+
+  specify
+    (IOLDO => RAout0) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module RAout_0__MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0255 \RAout_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), 
+    .LSR(GNDI), .Q(IOLDO));
+  vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
+  gnd DRIVEGND( .PWR0(GNDI));
+
+  specify
+    (CLK => IOLDO) = (0:0:0,0:0:0);
+    $width (posedge CLK, 0:0:0);
+    $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
 module BA_1_ ( input IOLDO, output BA1 );
 
-  xo2iobuf0197 \BA_pad[1] ( .I(IOLDO), .PAD(BA1));
+  xo2iobuf0253 \BA_pad[1] ( .I(IOLDO), .PAD(BA1));
 
   specify
     (IOLDO => BA1) = (0:0:0,0:0:0);
@@ -4907,16 +6441,16 @@ module BA_1_ ( input IOLDO, output BA1 );
 
 endmodule
 
-module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
-  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;
+module BA_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK );
+  wire   OPOS_dly, CLK_dly, CE_dly, LSR_dly;
 
-  mfflsre0200 \BA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), 
+  mfflsre0256 \BA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(LSR_dly), .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
@@ -4924,7 +6458,7 @@ module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
 
 endmodule
 
-module mfflsre0200 ( input D0, SP, CK, LSR, output Q );
+module mfflsre0256 ( input D0, SP, CK, LSR, output Q );
 
   FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
   defparam INST01.GSR = "DISABLED";
@@ -4932,7 +6466,7 @@ endmodule
 
 module BA_0_ ( input IOLDO, output BA0 );
 
-  xo2iobuf0197 \BA_pad[0] ( .I(IOLDO), .PAD(BA0));
+  xo2iobuf0253 \BA_pad[0] ( .I(IOLDO), .PAD(BA0));
 
   specify
     (IOLDO => BA0) = (0:0:0,0:0:0);
@@ -4940,16 +6474,16 @@ module BA_0_ ( input IOLDO, output BA0 );
 
 endmodule
 
-module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
-  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;
+module BA_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK );
+  wire   OPOS_dly, CLK_dly, CE_dly, LSR_dly;
 
-  mfflsre0200 \BA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), 
+  mfflsre0256 \BA_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(LSR_dly), .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
     $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
@@ -4957,144 +6491,131 @@ module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
 
 endmodule
 
-module nRWE ( input IOLDO, output nRWE );
+module nRWEout ( input IOLDO, output nRWEout );
 
-  xo2iobuf0197 nRWE_pad( .I(IOLDO), .PAD(nRWE));
+  xo2iobuf0253 nRWEout_pad( .I(IOLDO), .PAD(nRWEout));
 
   specify
-    (IOLDO => nRWE) = (0:0:0,0:0:0);
+    (IOLDO => nRWEout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nRWE_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nRWEout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nRWEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nCAS ( input IOLDO, output nCAS );
+module nCASout ( input IOLDO, output nCASout );
 
-  xo2iobuf0197 nCAS_pad( .I(IOLDO), .PAD(nCAS));
+  xo2iobuf0253 nCASout_pad( .I(IOLDO), .PAD(nCASout));
 
   specify
-    (IOLDO => nCAS) = (0:0:0,0:0:0);
+    (IOLDO => nCASout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nCAS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nCASout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nCASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nRAS ( input IOLDO, output nRAS );
+module nRASout ( input IOLDO, output nRASout );
 
-  xo2iobuf0197 nRAS_pad( .I(IOLDO), .PAD(nRAS));
+  xo2iobuf0253 nRASout_pad( .I(IOLDO), .PAD(nRASout));
 
   specify
-    (IOLDO => nRAS) = (0:0:0,0:0:0);
+    (IOLDO => nRASout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nRAS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module nRASout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
 
-  mfflsre nRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  mfflsre nRASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
-module nCS ( input IOLDO, output nCS );
+module nCSout ( input PADDO, output nCSout );
 
-  xo2iobuf0197 nCS_pad( .I(IOLDO), .PAD(nCS));
+  xo2iobuf0253 nCSout_pad( .I(PADDO), .PAD(nCSout));
 
   specify
-    (IOLDO => nCS) = (0:0:0,0:0:0);
+    (PADDO => nCSout) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module nCS_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
+module CKEout ( input IOLDO, output CKEout );
 
-  mfflsre nCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  xo2iobuf0253 CKEout_pad( .I(IOLDO), .PAD(CKEout));
+
+  specify
+    (IOLDO => CKEout) = (0:0:0,0:0:0);
+  endspecify
+
+endmodule
+
+module CKEout_MGIOL ( output IOLDO, input OPOS, CLK );
+  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
+
+  mfflsre0255 CKEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
     .Q(IOLDO));
   vcc DRIVEVCC( .PWR1(VCCI));
+  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-  endspecify
-
-endmodule
-
-module CKE ( input IOLDO, output CKE );
-
-  xo2iobuf0197 CKE_pad( .I(IOLDO), .PAD(CKE));
-
-  specify
-    (IOLDO => CKE) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module CKE_MGIOL ( output IOLDO, input OPOS, CLK );
-  wire   VCCI, GNDI, OPOS_dly, CLK_dly;
-
-  mfflsre0199 CKE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
-    .Q(IOLDO));
-  vcc DRIVEVCC( .PWR1(VCCI));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
+    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
   endspecify
 
 endmodule
 
 module nVOE ( input PADDO, output nVOE );
 
-  xo2iobuf0197 nVOE_pad( .I(PADDO), .PAD(nVOE));
+  xo2iobuf0253 nVOE_pad( .I(PADDO), .PAD(nVOE));
 
   specify
     (PADDO => nVOE) = (0:0:0,0:0:0);
@@ -5104,7 +6625,7 @@ endmodule
 
 module Vout_7_ ( input IOLDO, output Vout7 );
 
-  xo2iobuf0197 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7));
+  xo2iobuf0253 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7));
 
   specify
     (IOLDO => Vout7) = (0:0:0,0:0:0);
@@ -5113,31 +6634,25 @@ module Vout_7_ ( input IOLDO, output Vout7 );
 endmodule
 
 module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0199 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0255 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
-module inverter ( input I, output Z );
-
-  INV INST1( .A(I), .Z(Z));
-endmodule
-
 module Vout_6_ ( input IOLDO, output Vout6 );
 
-  xo2iobuf0197 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6));
+  xo2iobuf0253 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6));
 
   specify
     (IOLDO => Vout6) = (0:0:0,0:0:0);
@@ -5146,26 +6661,25 @@ module Vout_6_ ( input IOLDO, output Vout6 );
 endmodule
 
 module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0199 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0255 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_5_ ( input IOLDO, output Vout5 );
 
-  xo2iobuf0197 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5));
+  xo2iobuf0253 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5));
 
   specify
     (IOLDO => Vout5) = (0:0:0,0:0:0);
@@ -5174,26 +6688,25 @@ module Vout_5_ ( input IOLDO, output Vout5 );
 endmodule
 
 module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0199 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0255 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_4_ ( input IOLDO, output Vout4 );
 
-  xo2iobuf0197 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4));
+  xo2iobuf0253 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4));
 
   specify
     (IOLDO => Vout4) = (0:0:0,0:0:0);
@@ -5202,26 +6715,25 @@ module Vout_4_ ( input IOLDO, output Vout4 );
 endmodule
 
 module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0199 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0255 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_3_ ( input IOLDO, output Vout3 );
 
-  xo2iobuf0197 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3));
+  xo2iobuf0253 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3));
 
   specify
     (IOLDO => Vout3) = (0:0:0,0:0:0);
@@ -5230,26 +6742,25 @@ module Vout_3_ ( input IOLDO, output Vout3 );
 endmodule
 
 module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0199 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0255 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_2_ ( input IOLDO, output Vout2 );
 
-  xo2iobuf0197 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2));
+  xo2iobuf0253 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2));
 
   specify
     (IOLDO => Vout2) = (0:0:0,0:0:0);
@@ -5258,26 +6769,25 @@ module Vout_2_ ( input IOLDO, output Vout2 );
 endmodule
 
 module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0199 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0255 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_1_ ( input IOLDO, output Vout1 );
 
-  xo2iobuf0197 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1));
+  xo2iobuf0253 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1));
 
   specify
     (IOLDO => Vout1) = (0:0:0,0:0:0);
@@ -5286,26 +6796,25 @@ module Vout_1_ ( input IOLDO, output Vout1 );
 endmodule
 
 module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0199 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0255 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module Vout_0_ ( input IOLDO, output Vout0 );
 
-  xo2iobuf0197 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0));
+  xo2iobuf0253 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0));
 
   specify
     (IOLDO => Vout0) = (0:0:0,0:0:0);
@@ -5314,26 +6823,25 @@ module Vout_0_ ( input IOLDO, output Vout0 );
 endmodule
 
 module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;
 
-  mfflsre0199 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
+  mfflsre0255 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
     .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
   gnd DRIVEGND( .PWR0(GNDI));
 
   specify
     (CLK => IOLDO) = (0:0:0,0:0:0);
+    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
+    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
     $width (posedge CLK, 0:0:0);
     $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
   endspecify
 
 endmodule
 
 module nDOE ( input PADDO, output nDOE );
 
-  xo2iobuf0197 nDOE_pad( .I(PADDO), .PAD(nDOE));
+  xo2iobuf0253 nDOE_pad( .I(PADDO), .PAD(nDOE));
 
   specify
     (PADDO => nDOE) = (0:0:0,0:0:0);
@@ -5341,238 +6849,89 @@ module nDOE ( input PADDO, output nDOE );
 
 endmodule
 
-module Dout_7_ ( input IOLDO, output Dout7 );
+module Dout_7_ ( input PADDO, output Dout7 );
 
-  xo2iobuf0201 \Dout_pad[7] ( .I(IOLDO), .PAD(Dout7));
+  xo2iobuf0253 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
 
   specify
-    (IOLDO => Dout7) = (0:0:0,0:0:0);
+    (PADDO => Dout7) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module xo2iobuf0201 ( input I, output PAD );
+module Dout_6_ ( input PADDO, output Dout6 );
 
-  OB INST5( .I(I), .O(PAD));
-endmodule
-
-module Dout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0199 \Dout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0253 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout6) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_6_ ( input IOLDO, output Dout6 );
+module Dout_5_ ( input PADDO, output Dout5 );
 
-  xo2iobuf0201 \Dout_pad[6] ( .I(IOLDO), .PAD(Dout6));
+  xo2iobuf0253 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
 
   specify
-    (IOLDO => Dout6) = (0:0:0,0:0:0);
+    (PADDO => Dout5) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_4_ ( input PADDO, output Dout4 );
 
-  mfflsre0199 \Dout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0253 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout4) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_5_ ( input IOLDO, output Dout5 );
+module Dout_3_ ( input PADDO, output Dout3 );
 
-  xo2iobuf0201 \Dout_pad[5] ( .I(IOLDO), .PAD(Dout5));
+  xo2iobuf0253 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
 
   specify
-    (IOLDO => Dout5) = (0:0:0,0:0:0);
+    (PADDO => Dout3) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_2_ ( input PADDO, output Dout2 );
 
-  mfflsre0199 \Dout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0253 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout2) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_4_ ( input IOLDO, output Dout4 );
+module Dout_1_ ( input PADDO, output Dout1 );
 
-  xo2iobuf0201 \Dout_pad[4] ( .I(IOLDO), .PAD(Dout4));
+  xo2iobuf0253 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
 
   specify
-    (IOLDO => Dout4) = (0:0:0,0:0:0);
+    (PADDO => Dout1) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
-module Dout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
+module Dout_0_ ( input PADDO, output Dout0 );
 
-  mfflsre0199 \Dout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
+  xo2iobuf0253 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
 
   specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_3_ ( input IOLDO, output Dout3 );
-
-  xo2iobuf0201 \Dout_pad[3] ( .I(IOLDO), .PAD(Dout3));
-
-  specify
-    (IOLDO => Dout3) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0199 \Dout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_2_ ( input IOLDO, output Dout2 );
-
-  xo2iobuf0201 \Dout_pad[2] ( .I(IOLDO), .PAD(Dout2));
-
-  specify
-    (IOLDO => Dout2) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0199 \Dout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_1_ ( input IOLDO, output Dout1 );
-
-  xo2iobuf0201 \Dout_pad[1] ( .I(IOLDO), .PAD(Dout1));
-
-  specify
-    (IOLDO => Dout1) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0199 \Dout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
-  endspecify
-
-endmodule
-
-module Dout_0_ ( input IOLDO, output Dout0 );
-
-  xo2iobuf0201 \Dout_pad[0] ( .I(IOLDO), .PAD(Dout0));
-
-  specify
-    (IOLDO => Dout0) = (0:0:0,0:0:0);
-  endspecify
-
-endmodule
-
-module Dout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK );
-  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;
-
-  mfflsre0199 \Dout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
-    .LSR(GNDI), .Q(IOLDO));
-  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
-  gnd DRIVEGND( .PWR0(GNDI));
-
-  specify
-    (CLK => IOLDO) = (0:0:0,0:0:0);
-    $width (posedge CLK, 0:0:0);
-    $width (negedge CLK, 0:0:0);
-    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
-    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
+    (PADDO => Dout0) = (0:0:0,0:0:0);
   endspecify
 
 endmodule
 
 module Din_7_ ( output PADDI, input Din7 );
 
-  xo2iobuf0198 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
+  xo2iobuf0254 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
 
   specify
     (Din7 => PADDI) = (0:0:0,0:0:0);
@@ -5584,7 +6943,7 @@ endmodule
 
 module Din_6_ ( output PADDI, input Din6 );
 
-  xo2iobuf0198 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
+  xo2iobuf0254 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
 
   specify
     (Din6 => PADDI) = (0:0:0,0:0:0);
@@ -5596,7 +6955,7 @@ endmodule
 
 module Din_5_ ( output PADDI, input Din5 );
 
-  xo2iobuf0198 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
+  xo2iobuf0254 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
 
   specify
     (Din5 => PADDI) = (0:0:0,0:0:0);
@@ -5608,7 +6967,7 @@ endmodule
 
 module Din_4_ ( output PADDI, input Din4 );
 
-  xo2iobuf0198 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
+  xo2iobuf0254 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
 
   specify
     (Din4 => PADDI) = (0:0:0,0:0:0);
@@ -5620,7 +6979,7 @@ endmodule
 
 module Din_3_ ( output PADDI, input Din3 );
 
-  xo2iobuf0198 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
+  xo2iobuf0254 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
 
   specify
     (Din3 => PADDI) = (0:0:0,0:0:0);
@@ -5632,7 +6991,7 @@ endmodule
 
 module Din_2_ ( output PADDI, input Din2 );
 
-  xo2iobuf0198 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
+  xo2iobuf0254 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
 
   specify
     (Din2 => PADDI) = (0:0:0,0:0:0);
@@ -5644,7 +7003,7 @@ endmodule
 
 module Din_1_ ( output PADDI, input Din1 );
 
-  xo2iobuf0198 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
+  xo2iobuf0254 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
 
   specify
     (Din1 => PADDI) = (0:0:0,0:0:0);
@@ -5656,7 +7015,7 @@ endmodule
 
 module Din_0_ ( output PADDI, input Din0 );
 
-  xo2iobuf0198 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
+  xo2iobuf0254 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
 
   specify
     (Din0 => PADDI) = (0:0:0,0:0:0);
@@ -5668,7 +7027,7 @@ endmodule
 
 module Ain_7_ ( output PADDI, input Ain7 );
 
-  xo2iobuf0198 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7));
+  xo2iobuf0254 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7));
 
   specify
     (Ain7 => PADDI) = (0:0:0,0:0:0);
@@ -5680,7 +7039,7 @@ endmodule
 
 module Ain_6_ ( output PADDI, input Ain6 );
 
-  xo2iobuf0198 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6));
+  xo2iobuf0254 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6));
 
   specify
     (Ain6 => PADDI) = (0:0:0,0:0:0);
@@ -5692,7 +7051,7 @@ endmodule
 
 module Ain_5_ ( output PADDI, input Ain5 );
 
-  xo2iobuf0198 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5));
+  xo2iobuf0254 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5));
 
   specify
     (Ain5 => PADDI) = (0:0:0,0:0:0);
@@ -5704,7 +7063,7 @@ endmodule
 
 module Ain_4_ ( output PADDI, input Ain4 );
 
-  xo2iobuf0198 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4));
+  xo2iobuf0254 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4));
 
   specify
     (Ain4 => PADDI) = (0:0:0,0:0:0);
@@ -5716,7 +7075,7 @@ endmodule
 
 module Ain_3_ ( output PADDI, input Ain3 );
 
-  xo2iobuf0198 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3));
+  xo2iobuf0254 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3));
 
   specify
     (Ain3 => PADDI) = (0:0:0,0:0:0);
@@ -5728,7 +7087,7 @@ endmodule
 
 module Ain_2_ ( output PADDI, input Ain2 );
 
-  xo2iobuf0198 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2));
+  xo2iobuf0254 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2));
 
   specify
     (Ain2 => PADDI) = (0:0:0,0:0:0);
@@ -5740,7 +7099,7 @@ endmodule
 
 module Ain_1_ ( output PADDI, input Ain1 );
 
-  xo2iobuf0198 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1));
+  xo2iobuf0254 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1));
 
   specify
     (Ain1 => PADDI) = (0:0:0,0:0:0);
@@ -5752,7 +7111,7 @@ endmodule
 
 module Ain_0_ ( output PADDI, input Ain0 );
 
-  xo2iobuf0198 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0));
+  xo2iobuf0254 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0));
 
   specify
     (Ain0 => PADDI) = (0:0:0,0:0:0);
@@ -5764,7 +7123,7 @@ endmodule
 
 module nC07X ( output PADDI, input nC07X );
 
-  xo2iobuf0198 nC07X_pad( .Z(PADDI), .PAD(nC07X));
+  xo2iobuf0254 nC07X_pad( .Z(PADDI), .PAD(nC07X));
 
   specify
     (nC07X => PADDI) = (0:0:0,0:0:0);
@@ -5776,7 +7135,7 @@ endmodule
 
 module nEN80 ( output PADDI, input nEN80 );
 
-  xo2iobuf0198 nEN80_pad( .Z(PADDI), .PAD(nEN80));
+  xo2iobuf0254 nEN80_pad( .Z(PADDI), .PAD(nEN80));
 
   specify
     (nEN80 => PADDI) = (0:0:0,0:0:0);
@@ -5786,21 +7145,9 @@ module nEN80 ( output PADDI, input nEN80 );
 
 endmodule
 
-module nWE80 ( output PADDI, input nWE80 );
-
-  xo2iobuf0198 nWE80_pad( .Z(PADDI), .PAD(nWE80));
-
-  specify
-    (nWE80 => PADDI) = (0:0:0,0:0:0);
-    $width (posedge nWE80, 0:0:0);
-    $width (negedge nWE80, 0:0:0);
-  endspecify
-
-endmodule
-
 module nWE ( output PADDI, input nWE );
 
-  xo2iobuf0198 nWE_pad( .Z(PADDI), .PAD(nWE));
+  xo2iobuf0254 nWE_pad( .Z(PADDI), .PAD(nWE));
 
   specify
     (nWE => PADDI) = (0:0:0,0:0:0);
@@ -5812,7 +7159,7 @@ endmodule
 
 module PHI1 ( output PADDI, input PHI1 );
 
-  xo2iobuf0198 PHI1_pad( .Z(PADDI), .PAD(PHI1));
+  xo2iobuf0254 PHI1_pad( .Z(PADDI), .PAD(PHI1));
 
   specify
     (PHI1 => PADDI) = (0:0:0,0:0:0);
@@ -5825,7 +7172,7 @@ endmodule
 module PHI1_MGIOL ( input DI, CLK, output IN );
   wire   VCCI, GNDI, DI_dly, CLK_dly;
 
-  smuxlregsre PHI1reg_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
+  smuxlregsre PHI1r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
     .Q(IN));
   vcc DRIVEVCC( .PWR1(VCCI));
   gnd DRIVEGND( .PWR0(GNDI));
@@ -5845,14 +7192,14 @@ module smuxlregsre ( input D0, SP, CK, LSR, output Q );
   defparam INST01.GSR = "DISABLED";
 endmodule
 
-module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, 
-    WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, 
-    WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output 
-    WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, 
-    WBACKO );
+module ram2e_ufm_ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, 
+    WBWEI, WBADRI0, WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, 
+    WBADRI7, WBDATI0, WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, 
+    WBDATI7, output WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, 
+    WBDATO6, WBDATO7, WBACKO );
   wire   VCCI, GNDI;
 
-  EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), 
+  EFB_B \ram2e_ufm/ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), 
     .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), 
     .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), 
     .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), 
diff --git a/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
index 639e926..1142cd1 100644
--- a/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
+++ b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
@@ -1,11 +1,13 @@
-<HTML>         	<HEAD><TITLE></TITLE>                                   	<STYLE TYPE="text/css">                               	<!--                                                    	body,pre{                                              	font-family:'Courier New', monospace;             	color: #000000;                                     	font-size:88%;                                      	background-color: #ffffff;                          	}                                                       	h1 {                                                    	font-weight: bold;                                  	margin-top: 24px;                                   	margin-bottom: 10px;                                	border-bottom: 3px solid #000;    font-size: 1em;   	}                                                       	h2 {                                                    	font-weight: bold;                                  	margin-top: 18px;                                   	margin-bottom: 5px;                                 	font-size: 0.90em;                                  	}                                                       	h3 {                                                    	font-weight: bold;                                  	margin-top: 12px;                                   	margin-bottom: 5px;                                 	font-size: 0.80em;                                       	}                                                       	p {                                                     	font-size:78%;                                      	}                                                       	P.Table {                                               	margin-top: 4px;                                    	margin-bottom: 4px;                                 	margin-right: 4px;                                  	margin-left: 4px;                                   	}                                                       	table                                                   	{                                                       	border-width: 1px 1px 1px 1px;                      	border-style: solid solid solid solid;              	border-color: black black black black;              	border-collapse: collapse;                          	}                                                       	th {                                                    	font-weight:bold;                                   	padding: 4px;                                       	border-width: 1px 1px 1px 1px;                      	border-style: solid solid solid solid;              	border-color: black black black black;              	vertical-align:top;                                 	text-align:left;                                    	font-size:78%;                                           	}                                                       	td {                                                    	padding: 4px;                                       	border-width: 1px 1px 1px 1px;                      	border-style: solid solid solid solid;              	border-color: black black black black;              	vertical-align:top;                                 	font-size:78%;                                      	}                                                       	a {                                                     	color:#013C9A;                                      	text-decoration:none;                               	}                                                       		a:visited {                                             	color:#013C9A;                                      	}                                                       		a:hover, a:active {                                     	text-decoration:underline;                          	color:#5BAFD4;                                      	}                                                       	.pass                                                   	{                                                       	background-color: #00ff00;                              	}                                                                	.fail                                                   	{                                                       	background-color: #ff0000;                              	}                                                       	.comment                                                	{                                                       	font-size: 90%;                                     	font-style: italic;                                 	}                                                       		-->                                                     	</STYLE>                                                	</HEAD>                                                 	<BODY>                                                  	<PRE>Setting log file to '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
+<HTML>         	<HEAD><TITLE></TITLE>                                   	<STYLE TYPE="text/css">                               	<!--                                                    	body,pre{                                              	font-family:'Courier New', monospace;             	color: #000000;                                     	font-size:88%;                                      	background-color: #ffffff;                          	}                                                       	h1 {                                                    	font-weight: bold;                                  	margin-top: 24px;                                   	margin-bottom: 10px;                                	border-bottom: 3px solid #000;    font-size: 1em;   	}                                                       	h2 {                                                    	font-weight: bold;                                  	margin-top: 18px;                                   	margin-bottom: 5px;                                 	font-size: 0.90em;                                  	}                                                       	h3 {                                                    	font-weight: bold;                                  	margin-top: 12px;                                   	margin-bottom: 5px;                                 	font-size: 0.80em;                                       	}                                                       	p {                                                     	font-size:78%;                                      	}                                                       	P.Table {                                               	margin-top: 4px;                                    	margin-bottom: 4px;                                 	margin-right: 4px;                                  	margin-left: 4px;                                   	}                                                       	table                                                   	{                                                       	border-width: 1px 1px 1px 1px;                      	border-style: solid solid solid solid;              	border-color: black black black black;              	border-collapse: collapse;                          	}                                                       	th {                                                    	font-weight:bold;                                   	padding: 4px;                                       	border-width: 1px 1px 1px 1px;                      	border-style: solid solid solid solid;              	border-color: black black black black;              	vertical-align:top;                                 	text-align:left;                                    	font-size:78%;                                           	}                                                       	td {                                                    	padding: 4px;                                       	border-width: 1px 1px 1px 1px;                      	border-style: solid solid solid solid;              	border-color: black black black black;              	vertical-align:top;                                 	font-size:78%;                                      	}                                                       	a {                                                     	color:#013C9A;                                      	text-decoration:none;                               	}                                                       		a:visited {                                             	color:#013C9A;                                      	}                                                       		a:hover, a:active {                                     	text-decoration:underline;                          	color:#5BAFD4;                                      	}                                                       	.pass                                                   	{                                                       	background-color: #00ff00;                              	}                                                                	.fail                                                   	{                                                       	background-color: #ff0000;                              	}                                                       	.comment                                                	{                                                       	font-size: 90%;                                     	font-style: italic;                                 	}                                                       		-->                                                     	</STYLE>                                                	</HEAD>                                                 	<BODY>                                                  	<PRE>Setting log file to '//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
 Starting: parse design source files
 (VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
-(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v'
-(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/REFB.v'
-INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E'
-INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v(1,1-831,10) (VERI-9000) elaborating module 'RAM2E'
-INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
+(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/ram2e/CPLD/RAM2E.v'
+(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/ram2e/CPLD/UFM-LCMXO2.v'
+(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/REFB.v'
+INFO - //Mac/iCloud/Repos/ram2e/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E'
+INFO - //Mac/iCloud/Repos/ram2e/CPLD/RAM2E.v(1,1-473,10) (VERI-9000) elaborating module 'RAM2E'
+INFO - //Mac/iCloud/Repos/ram2e/CPLD/UFM-LCMXO2.v(1,1-334,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
+INFO - //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
 INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
 INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
 INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
diff --git a/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior
index 0656e13..0068b9c 100644
--- a/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior
+++ b/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior
@@ -29,9 +29,9 @@ Performance Hardware Data Status:   Final          Version 34.4.
 // Package: TQFP100
 // ncd File: ram2e_lcmxo2_640hc_impl1.ncd
 // Version: Diamond (64-bit) 3.12.1.454
-// Written on Thu Sep 21 05:35:10 2023
+// Written on Thu Dec 28 23:10:19 2023
 // M: Minimum Performance Grade
-// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
+// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml
 
 I/O Timing Report (All units are in ns)
 
@@ -41,78 +41,79 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
 
 Port   Clock Edge  Setup Performance_Grade  Hold Performance_Grade
 ----------------------------------------------------------------------
-Ain[0] C14M  R     0.502      4       0.868     4
-Ain[1] C14M  R     2.364      4      -0.126     M
-Ain[2] C14M  R     2.421      4      -0.129     M
-Ain[3] C14M  R     0.574      4       0.786     4
-Ain[4] C14M  R     1.452      4       0.140     M
-Ain[5] C14M  R     2.076      4      -0.039     M
-Ain[6] C14M  R     1.515      4       0.124     M
-Ain[7] C14M  R     2.270      4      -0.095     M
-Din[0] C14M  R     9.252      4       1.162     4
-Din[1] C14M  R     8.868      4       0.657     4
-Din[2] C14M  R     8.368      4       0.864     4
-Din[3] C14M  R     8.749      4       1.339     4
-Din[4] C14M  R     9.095      4       0.770     4
-Din[5] C14M  R     8.195      4       1.176     4
-Din[6] C14M  R     6.162      4       0.760     4
-Din[7] C14M  R     7.060      4       1.093     4
-PHI1   C14M  R     2.045      4       3.047     4
-RD[0]  C14M  F     0.267      4       0.866     4
-RD[1]  C14M  F     0.173      4       1.383     4
-RD[2]  C14M  F     0.924      4       1.018     4
-RD[3]  C14M  F     0.267      4       0.866     4
-RD[4]  C14M  F     0.173      4       0.937     4
-RD[5]  C14M  F     0.267      4       0.866     4
-RD[6]  C14M  F     0.766      4       0.866     4
-RD[7]  C14M  F     0.267      4       1.312     4
-nC07X  C14M  R     0.077      4       1.144     4
-nEN80  C14M  R     6.415      4      -0.286     M
-nWE    C14M  R     0.691      4       0.684     4
-nWE80  C14M  R     2.845      4      -0.260     M
+Ain[0] C14M  R     2.463      4      -0.066     M
+Ain[1] C14M  R     1.330      4       0.135     6
+Ain[2] C14M  R     1.221      4       0.223     4
+Ain[3] C14M  R     2.776      4      -0.165     M
+Ain[4] C14M  R     1.603      4       0.140     M
+Ain[5] C14M  R     0.021      6       1.287     4
+Ain[6] C14M  R     1.444      4       0.205     M
+Ain[7] C14M  R     1.816      4       0.114     M
+Din[0] C14M  R     8.919      4       0.723     4
+Din[1] C14M  R     8.410      4       1.156     4
+Din[2] C14M  R     8.503      4       1.181     4
+Din[3] C14M  R     8.783      4       0.110     M
+Din[4] C14M  R    10.420      4       1.022     4
+Din[5] C14M  R     8.001      4       0.566     4
+Din[6] C14M  R     9.731      4       1.050     4
+Din[7] C14M  R    10.052      4       0.862     4
+PHI1   C14M  R     2.579      4       3.047     4
+RD[0]  C14M  R     0.267      4       0.866     4
+RD[1]  C14M  R     0.173      4       0.937     4
+RD[2]  C14M  R     0.100      4       1.018     4
+RD[3]  C14M  R     0.267      4       0.866     4
+RD[4]  C14M  R     0.172      4       0.936     4
+RD[5]  C14M  R     0.267      4       0.866     4
+RD[6]  C14M  R     0.766      4       0.420     4
+RD[7]  C14M  R     0.267      4       0.866     4
+nC07X  C14M  R     0.998      4       0.405     6
+nEN80  C14M  R     6.107      4       0.114     M
+nWE    C14M  R     6.726      4       0.069     M
 
 
 // Clock to Output Delay
 
-Port    Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+Port      Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
 ------------------------------------------------------------------------
-BA[0]   C14M  R     8.629         4        2.885          M
-BA[1]   C14M  R     8.629         4        2.885          M
-CKE     C14M  R     8.629         4        2.885          M
-DQMH    C14M  R     8.609         4        2.892          M
-DQML    C14M  R     8.609         4        2.892          M
-Dout[0] C14M  F     8.955         4        3.164          M
-Dout[1] C14M  F     8.955         4        3.164          M
-Dout[2] C14M  F     8.944         4        3.158          M
-Dout[3] C14M  F     8.955         4        3.164          M
-Dout[4] C14M  F     8.944         4        3.158          M
-Dout[5] C14M  F     8.944         4        3.158          M
-Dout[6] C14M  F     8.955         4        3.164          M
-Dout[7] C14M  F     8.955         4        3.164          M
-LED     C14M  R    19.941         4        8.191          M
-RA[0]   C14M  R    10.013         4        3.186          M
-RA[10]  C14M  R     8.629         4        2.885          M
-RA[11]  C14M  R     8.629         4        2.885          M
-RA[1]   C14M  R     8.695         4        2.890          M
-RA[2]   C14M  R     8.695         4        2.890          M
-RA[3]   C14M  R    10.013         4        3.186          M
-RA[4]   C14M  R     8.695         4        2.890          M
-RA[5]   C14M  R     8.695         4        2.890          M
-RA[6]   C14M  R     8.695         4        2.890          M
-RA[7]   C14M  R     8.695         4        2.890          M
-RA[8]   C14M  R     8.629         4        2.885          M
-RA[9]   C14M  R     8.629         4        2.885          M
-Vout[0] C14M  F     9.553         4        3.402          M
-Vout[1] C14M  F     9.553         4        3.402          M
-Vout[2] C14M  F     9.553         4        3.402          M
-Vout[3] C14M  F     9.553         4        3.402          M
-Vout[4] C14M  F     9.553         4        3.402          M
-Vout[5] C14M  F     9.553         4        3.402          M
-Vout[6] C14M  F     9.553         4        3.402          M
-Vout[7] C14M  F     9.553         4        3.402          M
-nCAS    C14M  R     8.629         4        2.885          M
-nCS     C14M  R     8.629         4        2.885          M
-nDOE    C14M  R    11.976         4        3.776          M
-nRAS    C14M  R     8.629         4        2.885          M
-nRWE    C14M  R     8.629         4        2.885          M
+BA[0]     C14M  R     8.629         4        2.885          M
+BA[1]     C14M  R     8.629         4        2.885          M
+CKEout    C14M  F     8.629         4        2.885          M
+DQMH      C14M  R     8.609         4        2.892          M
+DQML      C14M  R     8.609         4        2.892          M
+LED       C14M  R    19.935         4        8.161          M
+RAout[0]  C14M  F     8.695         4        2.890          M
+RAout[10] C14M  F     8.629         4        2.885          M
+RAout[11] C14M  F     8.629         4        2.885          M
+RAout[1]  C14M  F     8.695         4        2.890          M
+RAout[2]  C14M  F     8.695         4        2.890          M
+RAout[3]  C14M  F     8.695         4        2.890          M
+RAout[4]  C14M  F     8.695         4        2.890          M
+RAout[5]  C14M  F     8.695         4        2.890          M
+RAout[6]  C14M  F     8.695         4        2.890          M
+RAout[7]  C14M  F     8.695         4        2.890          M
+RAout[8]  C14M  F     8.629         4        2.885          M
+RAout[9]  C14M  F     8.629         4        2.885          M
+RD[0]     C14M  R    11.414         4        3.265          M
+RD[1]     C14M  R    11.811         4        3.265          M
+RD[2]     C14M  R    11.925         4        3.265          M
+RD[3]     C14M  R    11.384         4        3.265          M
+RD[4]     C14M  R    12.301         4        3.371          M
+RD[5]     C14M  R    12.767         4        3.371          M
+RD[6]     C14M  R    12.010         4        3.371          M
+RD[7]     C14M  R    12.313         4        3.371          M
+Vout[0]   C14M  R     9.553         4        3.402          M
+Vout[1]   C14M  R     9.553         4        3.402          M
+Vout[2]   C14M  R     9.553         4        3.402          M
+Vout[3]   C14M  R     9.553         4        3.402          M
+Vout[4]   C14M  R     9.553         4        3.402          M
+Vout[5]   C14M  R     9.553         4        3.402          M
+Vout[6]   C14M  R     9.553         4        3.402          M
+Vout[7]   C14M  R     9.553         4        3.402          M
+nCASout   C14M  F     8.629         4        2.885          M
+nDOE      C14M  R    12.048         4        3.811          M
+nRASout   C14M  F     8.629         4        2.885          M
+nRWEout   C14M  F     8.629         4        2.885          M
+nVOE      C14M  R    12.164         4        3.783          M
 WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with setup speed: 6
+WARNING: you must also run trce with hold speed: 6
diff --git a/CPLD/LCMXO2-640HC/promote.xml b/CPLD/LCMXO2-640HC/promote.xml
index 2c3c713..3764576 100644
--- a/CPLD/LCMXO2-640HC/promote.xml
+++ b/CPLD/LCMXO2-640HC/promote.xml
@@ -1,3 +1,3 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Sep 21 05:35:47 2023" vendor="Lattice Semiconductor Corporation" >
+<userSetting name="//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:11:36 2023" vendor="Lattice Semiconductor Corporation" >
 </userSetting>
diff --git a/CPLD/LCMXO2-640HC/reportview.xml b/CPLD/LCMXO2-640HC/reportview.xml
index 146942a..ed7b29c 100644
--- a/CPLD/LCMXO2-640HC/reportview.xml
+++ b/CPLD/LCMXO2-640HC/reportview.xml
@@ -3,7 +3,7 @@
 <ReportView version="2.0">
     <Implement name="impl1">
         <ToolReport id="tooldec" path="" status="0"/>
-        <ToolReport id="toolhle_genhierarchy" path="Y:/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html" status="1"/>
+        <ToolReport id="toolhle_genhierarchy" path="//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html" status="1"/>
         <ToolReport id="toolpio" path="" status="2"/>
         <ToolReport id="toolsso" path="" status="2"/>
     </Implement>
diff --git a/CPLD/MAXII/RAM2E.qsf b/CPLD/MAXII/RAM2E.qsf
index 722f2da..f1854f5 100644
--- a/CPLD/MAXII/RAM2E.qsf
+++ b/CPLD/MAXII/RAM2E.qsf
@@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EPM240T100C5
 set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:26:23  AUGUST 20, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -75,7 +75,6 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80
 
 set_location_assignment PIN_33 -to nWE80
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80
 
 set_location_assignment PIN_52 -to nC07X
@@ -124,7 +123,6 @@ set_location_assignment PIN_85 -to Dout[7]
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout
 set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
 
 set_location_assignment PIN_50 -to nVOE
@@ -147,40 +145,39 @@ set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout
 
-set_location_assignment PIN_4 -to CKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE
-set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE
+set_location_assignment PIN_4 -to CKEout
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKEout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKEout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to CKEout
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKEout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKEout
 
-set_location_assignment PIN_8 -to nCS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS
+set_location_assignment PIN_8 -to nCSout
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCSout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCSout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nCSout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCSout
 
-set_location_assignment PIN_2 -to nRWE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE
+set_location_assignment PIN_2 -to nRWEout
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWEout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWEout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWEout
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWEout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWEout
 
-set_location_assignment PIN_5 -to nRAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
+set_location_assignment PIN_5 -to nRASout
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRASout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRASout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRASout
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRASout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRASout
 
-set_location_assignment PIN_3 -to nCAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
+set_location_assignment PIN_3 -to nCASout
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCASout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCASout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nCASout
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCASout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCASout
 
 set_location_assignment PIN_6 -to BA[0]
 set_location_assignment PIN_14 -to BA[1]
@@ -190,23 +187,23 @@ set_instance_assignment -name SLOW_SLEW_RATE ON -to BA
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA
 
-set_location_assignment PIN_18 -to RA[0]
-set_location_assignment PIN_20 -to RA[1]
-set_location_assignment PIN_30 -to RA[2]
-set_location_assignment PIN_27 -to RA[3]
-set_location_assignment PIN_26 -to RA[4]
-set_location_assignment PIN_29 -to RA[5]
-set_location_assignment PIN_21 -to RA[6]
-set_location_assignment PIN_19 -to RA[7]
-set_location_assignment PIN_17 -to RA[8]
-set_location_assignment PIN_15 -to RA[9]
-set_location_assignment PIN_16 -to RA[10]
-set_location_assignment PIN_7 -to RA[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA
-set_instance_assignment -name SLOW_SLEW_RATE ON -to RA
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
+set_location_assignment PIN_18 -to RAout[0]
+set_location_assignment PIN_20 -to RAout[1]
+set_location_assignment PIN_30 -to RAout[2]
+set_location_assignment PIN_27 -to RAout[3]
+set_location_assignment PIN_26 -to RAout[4]
+set_location_assignment PIN_29 -to RAout[5]
+set_location_assignment PIN_21 -to RAout[6]
+set_location_assignment PIN_19 -to RAout[7]
+set_location_assignment PIN_17 -to RAout[8]
+set_location_assignment PIN_15 -to RAout[9]
+set_location_assignment PIN_16 -to RAout[10]
+set_location_assignment PIN_7 -to RAout[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RAout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RAout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RAout
 
 set_location_assignment PIN_100 -to DQMH
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH
@@ -238,11 +235,12 @@ set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
 
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name VERILOG_FILE "../RAM2E-MAX.v"
+set_location_assignment PIN_88 -to LED
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
+set_global_assignment -name VERILOG_FILE ../RAM2E.v
+set_global_assignment -name VERILOG_FILE "../UFM-MAX.v"
 set_global_assignment -name QIP_FILE UFM.qip
 set_global_assignment -name MIF_FILE ../RAM2E.mif
 set_global_assignment -name SDC_FILE ../RAM2E.sdc
-set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc"
-set_location_assignment PIN_88 -to LED
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
-set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
\ No newline at end of file
+set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc"
\ No newline at end of file
diff --git a/CPLD/MAXII/output_files/RAM2E.asm.rpt b/CPLD/MAXII/output_files/RAM2E.asm.rpt
index c9fac51..6d4d777 100644
--- a/CPLD/MAXII/output_files/RAM2E.asm.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.asm.rpt
@@ -1,6 +1,6 @@
 Assembler report for RAM2E
-Thu Sep 21 05:34:41 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Thu Dec 28 23:09:46 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
 ---------------------
@@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
   2. Assembler Summary
   3. Assembler Settings
   4. Assembler Generated Files
-  5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof
+  5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof
   6. Assembler Messages
 
 
@@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Sep 21 05:34:41 2023 ;
+; Assembler Status      ; Successful - Thu Dec 28 23:09:46 2023 ;
 ; Revision Name         ; RAM2E                                 ;
 ; Top-level Entity Name ; RAM2E                                 ;
 ; Family                ; MAX II                                ;
@@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
 +--------+---------+---------------+
 
 
-+------------------------------------------------+
-; Assembler Generated Files                      ;
-+------------------------------------------------+
-; File Name                                      ;
-+------------------------------------------------+
-; /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
-+------------------------------------------------+
++--------------------------------------------------+
+; Assembler Generated Files                        ;
++--------------------------------------------------+
+; File Name                                        ;
++--------------------------------------------------+
+; Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
++--------------------------------------------------+
 
 
-+--------------------------------------------------------------------------+
-; Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
-+----------------+---------------------------------------------------------+
-; Option         ; Setting                                                 ;
-+----------------+---------------------------------------------------------+
-; JTAG usercode  ; 0x0016D33C                                              ;
-; Checksum       ; 0x0016D634                                              ;
-+----------------+---------------------------------------------------------+
++----------------------------------------------------------------------------+
+; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
++----------------+-----------------------------------------------------------+
+; Option         ; Setting                                                   ;
++----------------+-----------------------------------------------------------+
+; JTAG usercode  ; 0x00165DEE                                                ;
+; Checksum       ; 0x0016605E                                                ;
++----------------+-----------------------------------------------------------+
 
 
 +--------------------+
@@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
 +--------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Thu Sep 21 05:34:39 2023
+    Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
+    Info: Processing started: Thu Dec 28 23:09:46 2023
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 13092 megabytes
-    Info: Processing ended: Thu Sep 21 05:34:41 2023
-    Info: Elapsed time: 00:00:02
+    Info: Peak virtual memory: 13071 megabytes
+    Info: Processing ended: Thu Dec 28 23:09:47 2023
+    Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:01
 
 
diff --git a/CPLD/MAXII/output_files/RAM2E.done b/CPLD/MAXII/output_files/RAM2E.done
index 9e5945b..b88a509 100644
--- a/CPLD/MAXII/output_files/RAM2E.done
+++ b/CPLD/MAXII/output_files/RAM2E.done
@@ -1 +1 @@
-Thu Sep 21 05:34:46 2023
+Thu Dec 28 23:09:51 2023
diff --git a/CPLD/MAXII/output_files/RAM2E.fit.rpt b/CPLD/MAXII/output_files/RAM2E.fit.rpt
index 5adbd10..972e71e 100644
--- a/CPLD/MAXII/output_files/RAM2E.fit.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.fit.rpt
@@ -1,6 +1,6 @@
 Fitter report for RAM2E
-Thu Sep 21 05:34:37 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Thu Dec 28 23:09:44 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
 ---------------------
@@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula.
 
 
 
-+---------------------------------------------------------------------+
-; Fitter Summary                                                      ;
-+-----------------------+---------------------------------------------+
-; Fitter Status         ; Successful - Thu Sep 21 05:34:37 2023       ;
-; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name         ; RAM2E                                       ;
-; Top-level Entity Name ; RAM2E                                       ;
-; Family                ; MAX II                                      ;
-; Device                ; EPM240T100C5                                ;
-; Timing Models         ; Final                                       ;
-; Total logic elements  ; 197 / 240 ( 82 % )                          ;
-; Total pins            ; 70 / 80 ( 88 % )                            ;
-; Total virtual pins    ; 0                                           ;
-; UFM blocks            ; 1 / 1 ( 100 % )                             ;
-+-----------------------+---------------------------------------------+
++-------------------------------------------------------------------------------------+
+; Fitter Summary                                                                      ;
++-----------------------+-------------------------------------------------------------+
+; Fitter Status         ; Successful - Thu Dec 28 23:09:44 2023                       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
+; Revision Name         ; RAM2E                                                       ;
+; Top-level Entity Name ; RAM2E                                                       ;
+; Family                ; MAX II                                                      ;
+; Device                ; EPM240T100C5                                                ;
+; Timing Models         ; Final                                                       ;
+; Total logic elements  ; 238 / 240 ( 99 % )                                          ;
+; Total pins            ; 70 / 80 ( 88 % )                                            ;
+; Total virtual pins    ; 0                                                           ;
+; UFM blocks            ; 1 / 1 ( 100 % )                                             ;
++-----------------------+-------------------------------------------------------------+
 
 
 +--------------------------------------------------------------------------------------------------------------------------------------+
@@ -134,15 +134,15 @@ https://fpgasoftware.intel.com/eula.
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.2%      ;
-;     Processors 3-4         ;   1.1%      ;
+;     Processor 2            ;   1.1%      ;
+;     Processors 3-4         ;   1.0%      ;
 +----------------------------+-------------+
 
 
 +--------------+
 ; Pin-Out File ;
 +--------------+
-The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
+The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
 
 
 +---------------------------------------------------------------------+
@@ -150,27 +150,27 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
 +---------------------------------------------+-----------------------+
 ; Resource                                    ; Usage                 ;
 +---------------------------------------------+-----------------------+
-; Total logic elements                        ; 197 / 240 ( 82 % )    ;
-;     -- Combinational with no register       ; 85                    ;
-;     -- Register only                        ; 19                    ;
-;     -- Combinational with a register        ; 93                    ;
+; Total logic elements                        ; 238 / 240 ( 99 % )    ;
+;     -- Combinational with no register       ; 115                   ;
+;     -- Register only                        ; 26                    ;
+;     -- Combinational with a register        ; 97                    ;
 ;                                             ;                       ;
 ; Logic element usage by number of LUT inputs ;                       ;
-;     -- 4 input functions                    ; 103                   ;
-;     -- 3 input functions                    ; 29                    ;
-;     -- 2 input functions                    ; 42                    ;
-;     -- 1 input functions                    ; 3                     ;
+;     -- 4 input functions                    ; 118                   ;
+;     -- 3 input functions                    ; 41                    ;
+;     -- 2 input functions                    ; 48                    ;
+;     -- 1 input functions                    ; 4                     ;
 ;     -- 0 input functions                    ; 1                     ;
 ;                                             ;                       ;
 ; Logic elements by mode                      ;                       ;
-;     -- normal mode                          ; 183                   ;
+;     -- normal mode                          ; 224                   ;
 ;     -- arithmetic mode                      ; 14                    ;
-;     -- qfbk mode                            ; 8                     ;
+;     -- qfbk mode                            ; 6                     ;
 ;     -- register cascade mode                ; 0                     ;
-;     -- synchronous clear/load mode          ; 12                    ;
+;     -- synchronous clear/load mode          ; 24                    ;
 ;     -- asynchronous clear/load mode         ; 0                     ;
 ;                                             ;                       ;
-; Total registers                             ; 112 / 240 ( 47 % )    ;
+; Total registers                             ; 123 / 240 ( 51 % )    ;
 ; Total LABs                                  ; 24 / 24 ( 100 % )     ;
 ; Logic elements in carry chains              ; 15                    ;
 ; Virtual pins                                ; 0                     ;
@@ -185,11 +185,11 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
 ; Global signals                              ; 1                     ;
 ;     -- Global clocks                        ; 1 / 4 ( 25 % )        ;
 ; JTAGs                                       ; 0 / 1 ( 0 % )         ;
-; Average interconnect usage (total/H/V)      ; 22.5% / 24.3% / 20.7% ;
-; Peak interconnect usage (total/H/V)         ; 22.5% / 24.3% / 20.7% ;
-; Maximum fan-out                             ; 112                   ;
-; Highest non-global fan-out                  ; 31                    ;
-; Total fan-out                               ; 847                   ;
+; Average interconnect usage (total/H/V)      ; 26.0% / 25.7% / 26.3% ;
+; Peak interconnect usage (total/H/V)         ; 26.0% / 25.7% / 26.3% ;
+; Maximum fan-out                             ; 123                   ;
+; Highest non-global fan-out                  ; 35                    ;
+; Total fan-out                               ; 976                   ;
 ; Average fan-out                             ; 3.16                  ;
 +---------------------------------------------+-----------------------+
 
@@ -207,69 +207,69 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
 ; Ain[5] ; 34    ; 1        ; 3            ; 0            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; Ain[6] ; 39    ; 1        ; 5            ; 0            ; 3           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; Ain[7] ; 53    ; 2        ; 8            ; 1            ; 3           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; C14M   ; 12    ; 1        ; 1            ; 3            ; 3           ; 112                   ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[0] ; 38    ; 1        ; 4            ; 0            ; 0           ; 14                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[1] ; 40    ; 1        ; 5            ; 0            ; 2           ; 7                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; C14M   ; 12    ; 1        ; 1            ; 3            ; 3           ; 123                   ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[0] ; 38    ; 1        ; 4            ; 0            ; 0           ; 15                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[1] ; 40    ; 1        ; 5            ; 0            ; 2           ; 11                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; Din[2] ; 42    ; 1        ; 5            ; 0            ; 0           ; 13                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[3] ; 41    ; 1        ; 5            ; 0            ; 1           ; 12                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[4] ; 48    ; 1        ; 6            ; 0            ; 0           ; 9                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[5] ; 49    ; 1        ; 7            ; 0            ; 2           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[3] ; 41    ; 1        ; 5            ; 0            ; 1           ; 13                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[4] ; 48    ; 1        ; 6            ; 0            ; 0           ; 10                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[5] ; 49    ; 1        ; 7            ; 0            ; 2           ; 9                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; Din[6] ; 36    ; 1        ; 4            ; 0            ; 2           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[7] ; 35    ; 1        ; 3            ; 0            ; 0           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[7] ; 35    ; 1        ; 3            ; 0            ; 0           ; 9                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; PHI1   ; 37    ; 1        ; 4            ; 0            ; 1           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; nC07X  ; 52    ; 2        ; 8            ; 1            ; 4           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nEN80  ; 28    ; 1        ; 2            ; 0            ; 1           ; 5                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nWE    ; 51    ; 1        ; 7            ; 0            ; 0           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nWE80  ; 33    ; 1        ; 3            ; 0            ; 2           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nEN80  ; 28    ; 1        ; 2            ; 0            ; 1           ; 10                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nWE    ; 51    ; 1        ; 7            ; 0            ; 0           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nWE80  ; 33    ; 1        ; 3            ; 0            ; 2           ; 0                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 +--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                               ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; BA[0]   ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; BA[1]   ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; CKE     ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; DQMH    ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; DQML    ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[0] ; 77    ; 2        ; 7            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[1] ; 76    ; 2        ; 7            ; 5            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[2] ; 74    ; 2        ; 8            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[3] ; 75    ; 2        ; 7            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[4] ; 73    ; 2        ; 8            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[5] ; 72    ; 2        ; 8            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[6] ; 84    ; 2        ; 6            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[7] ; 85    ; 2        ; 5            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; LED     ; 88    ; 2        ; 5            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[0]   ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[10]  ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[11]  ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[1]   ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[2]   ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[3]   ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[4]   ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[5]   ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[6]   ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[7]   ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[8]   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[9]   ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[0] ; 70    ; 2        ; 8            ; 4            ; 4           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[1] ; 67    ; 2        ; 8            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[2] ; 69    ; 2        ; 8            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[3] ; 62    ; 2        ; 8            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[4] ; 71    ; 2        ; 8            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[5] ; 68    ; 2        ; 8            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[6] ; 58    ; 2        ; 8            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[7] ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nCAS    ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nCS     ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nDOE    ; 55    ; 2        ; 8            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRAS    ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nRWE    ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nVOE    ; 50    ; 1        ; 7            ; 0            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                 ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; BA[0]     ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; BA[1]     ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; CKEout    ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; DQMH      ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; DQML      ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[0]   ; 77    ; 2        ; 7            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[1]   ; 76    ; 2        ; 7            ; 5            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[2]   ; 74    ; 2        ; 8            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[3]   ; 75    ; 2        ; 7            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[4]   ; 73    ; 2        ; 8            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[5]   ; 72    ; 2        ; 8            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[6]   ; 84    ; 2        ; 6            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[7]   ; 85    ; 2        ; 5            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; LED       ; 88    ; 2        ; 5            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[0]  ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[10] ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[11] ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[1]  ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[2]  ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[3]  ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[4]  ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[5]  ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[6]  ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[7]  ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[8]  ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[9]  ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[0]   ; 70    ; 2        ; 8            ; 4            ; 4           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[1]   ; 67    ; 2        ; 8            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[2]   ; 69    ; 2        ; 8            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[3]   ; 62    ; 2        ; 8            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[4]   ; 71    ; 2        ; 8            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[5]   ; 68    ; 2        ; 8            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[6]   ; 58    ; 2        ; 8            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[7]   ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nCASout   ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nCSout    ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nDOE      ; 55    ; 2        ; 8            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nRASout   ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nRWEout   ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nVOE      ; 50    ; 1        ; 7            ; 0            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
 
 
 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -304,35 +304,35 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
 ; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage   ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
 +----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
 ; 1        ; 83         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 2        ; 0          ; 1        ; nRWE           ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 3        ; 1          ; 1        ; nCAS           ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 4        ; 2          ; 1        ; CKE            ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 5        ; 3          ; 1        ; nRAS           ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 2        ; 0          ; 1        ; nRWEout        ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 3        ; 1          ; 1        ; nCASout        ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 4        ; 2          ; 1        ; CKEout         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 5        ; 3          ; 1        ; nRASout        ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
 ; 6        ; 4          ; 1        ; BA[0]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 7        ; 5          ; 1        ; RA[11]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 8        ; 6          ; 1        ; nCS            ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 7        ; 5          ; 1        ; RAout[11]      ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 8        ; 6          ; 1        ; nCSout         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
 ; 9        ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
 ; 10       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
 ; 11       ;            ;          ; GNDINT         ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
 ; 12       ; 7          ; 1        ; C14M           ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
 ; 13       ;            ;          ; VCCINT         ; power  ;              ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
 ; 14       ; 8          ; 1        ; BA[1]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 15       ; 9          ; 1        ; RA[9]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 16       ; 10         ; 1        ; RA[10]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 17       ; 11         ; 1        ; RA[8]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 18       ; 12         ; 1        ; RA[0]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 19       ; 13         ; 1        ; RA[7]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 20       ; 14         ; 1        ; RA[1]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
-; 21       ; 15         ; 1        ; RA[6]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 15       ; 9          ; 1        ; RAout[9]       ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 16       ; 10         ; 1        ; RAout[10]      ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 17       ; 11         ; 1        ; RAout[8]       ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 18       ; 12         ; 1        ; RAout[0]       ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 19       ; 13         ; 1        ; RAout[7]       ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 20       ; 14         ; 1        ; RAout[1]       ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
+; 21       ; 15         ; 1        ; RAout[6]       ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; no       ; Off          ;
 ; 22       ; 16         ; 1        ; #TMS           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
 ; 23       ; 17         ; 1        ; #TDI           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
 ; 24       ; 18         ; 1        ; #TCK           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
 ; 25       ; 19         ; 1        ; #TDO           ; output ;              ;           ; --         ;                 ; --       ; --           ;
-; 26       ; 20         ; 1        ; RA[4]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 27       ; 21         ; 1        ; RA[3]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 26       ; 20         ; 1        ; RAout[4]       ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 27       ; 21         ; 1        ; RAout[3]       ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
 ; 28       ; 22         ; 1        ; nEN80          ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 29       ; 23         ; 1        ; RA[5]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
-; 30       ; 24         ; 1        ; RA[2]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 29       ; 23         ; 1        ; RAout[5]       ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
+; 30       ; 24         ; 1        ; RAout[2]       ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
 ; 31       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
 ; 32       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
 ; 33       ; 25         ; 1        ; nWE80          ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; no       ; Off          ;
@@ -423,112 +423,119 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
 Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
 
 
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                       ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                   ; Entity Name         ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
-; |RAM2E                                                    ; 197 (197)   ; 112          ; 1          ; 70   ; 0            ; 85 (85)      ; 19 (19)           ; 93 (93)          ; 15 (15)         ; 8 (8)      ; |RAM2E                                                                ; RAM2E               ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|UFM:UFM_inst                                                   ; UFM                 ; work         ;
-;       |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                              ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
+; Compilation Hierarchy Node                                   ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                                       ; Entity Name         ; Library Name ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
+; |RAM2E                                                       ; 238 (180)   ; 123          ; 1          ; 70   ; 0            ; 115 (90)     ; 26 (23)           ; 97 (67)          ; 15 (15)         ; 6 (1)      ; |RAM2E                                                                                    ; RAM2E               ; work         ;
+;    |RAM2E_UFM:ram2e_ufm|                                     ; 58 (58)     ; 33           ; 1          ; 0    ; 0            ; 25 (25)      ; 3 (3)             ; 30 (30)          ; 0 (0)           ; 5 (5)      ; |RAM2E|RAM2E_UFM:ram2e_ufm                                                                ; RAM2E_UFM           ; work         ;
+;       |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst                                                   ; UFM                 ; work         ;
+;          |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work         ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
-+------------------------------------+
-; Delay Chain Summary                ;
-+---------+----------+---------------+
-; Name    ; Pin Type ; Pad to Core 0 ;
-+---------+----------+---------------+
-; LED     ; Output   ; --            ;
-; Dout[0] ; Output   ; --            ;
-; Dout[1] ; Output   ; --            ;
-; Dout[2] ; Output   ; --            ;
-; Dout[3] ; Output   ; --            ;
-; Dout[4] ; Output   ; --            ;
-; Dout[5] ; Output   ; --            ;
-; Dout[6] ; Output   ; --            ;
-; Dout[7] ; Output   ; --            ;
-; nDOE    ; Output   ; --            ;
-; Vout[0] ; Output   ; --            ;
-; Vout[1] ; Output   ; --            ;
-; Vout[2] ; Output   ; --            ;
-; Vout[3] ; Output   ; --            ;
-; Vout[4] ; Output   ; --            ;
-; Vout[5] ; Output   ; --            ;
-; Vout[6] ; Output   ; --            ;
-; Vout[7] ; Output   ; --            ;
-; nVOE    ; Output   ; --            ;
-; CKE     ; Output   ; --            ;
-; nCS     ; Output   ; --            ;
-; nRAS    ; Output   ; --            ;
-; nCAS    ; Output   ; --            ;
-; nRWE    ; Output   ; --            ;
-; BA[0]   ; Output   ; --            ;
-; BA[1]   ; Output   ; --            ;
-; RA[0]   ; Output   ; --            ;
-; RA[1]   ; Output   ; --            ;
-; RA[2]   ; Output   ; --            ;
-; RA[3]   ; Output   ; --            ;
-; RA[4]   ; Output   ; --            ;
-; RA[5]   ; Output   ; --            ;
-; RA[6]   ; Output   ; --            ;
-; RA[7]   ; Output   ; --            ;
-; RA[8]   ; Output   ; --            ;
-; RA[9]   ; Output   ; --            ;
-; RA[10]  ; Output   ; --            ;
-; RA[11]  ; Output   ; --            ;
-; DQML    ; Output   ; --            ;
-; DQMH    ; Output   ; --            ;
-; RD[0]   ; Bidir    ; (0)           ;
-; RD[1]   ; Bidir    ; (0)           ;
-; RD[2]   ; Bidir    ; (0)           ;
-; RD[3]   ; Bidir    ; (0)           ;
-; RD[4]   ; Bidir    ; (0)           ;
-; RD[5]   ; Bidir    ; (0)           ;
-; RD[6]   ; Bidir    ; (0)           ;
-; RD[7]   ; Bidir    ; (0)           ;
-; nEN80   ; Input    ; (0)           ;
-; nWE     ; Input    ; (0)           ;
-; PHI1    ; Input    ; (1)           ;
-; Din[0]  ; Input    ; (0)           ;
-; C14M    ; Input    ; (0)           ;
-; nWE80   ; Input    ; (0)           ;
-; Ain[0]  ; Input    ; (0)           ;
-; Ain[1]  ; Input    ; (0)           ;
-; Ain[2]  ; Input    ; (0)           ;
-; Ain[3]  ; Input    ; (0)           ;
-; Ain[4]  ; Input    ; (0)           ;
-; Ain[5]  ; Input    ; (0)           ;
-; Ain[6]  ; Input    ; (0)           ;
-; Ain[7]  ; Input    ; (0)           ;
-; Din[6]  ; Input    ; (0)           ;
-; Din[2]  ; Input    ; (0)           ;
-; Din[1]  ; Input    ; (0)           ;
-; Din[5]  ; Input    ; (0)           ;
-; Din[7]  ; Input    ; (0)           ;
-; Din[4]  ; Input    ; (0)           ;
-; Din[3]  ; Input    ; (0)           ;
-; nC07X   ; Input    ; (0)           ;
-+---------+----------+---------------+
++--------------------------------------+
+; Delay Chain Summary                  ;
++-----------+----------+---------------+
+; Name      ; Pin Type ; Pad to Core 0 ;
++-----------+----------+---------------+
+; LED       ; Output   ; --            ;
+; nWE80     ; Input    ; (0)           ;
+; Dout[0]   ; Output   ; --            ;
+; Dout[1]   ; Output   ; --            ;
+; Dout[2]   ; Output   ; --            ;
+; Dout[3]   ; Output   ; --            ;
+; Dout[4]   ; Output   ; --            ;
+; Dout[5]   ; Output   ; --            ;
+; Dout[6]   ; Output   ; --            ;
+; Dout[7]   ; Output   ; --            ;
+; nDOE      ; Output   ; --            ;
+; Vout[0]   ; Output   ; --            ;
+; Vout[1]   ; Output   ; --            ;
+; Vout[2]   ; Output   ; --            ;
+; Vout[3]   ; Output   ; --            ;
+; Vout[4]   ; Output   ; --            ;
+; Vout[5]   ; Output   ; --            ;
+; Vout[6]   ; Output   ; --            ;
+; Vout[7]   ; Output   ; --            ;
+; nVOE      ; Output   ; --            ;
+; CKEout    ; Output   ; --            ;
+; nCSout    ; Output   ; --            ;
+; nRASout   ; Output   ; --            ;
+; nCASout   ; Output   ; --            ;
+; nRWEout   ; Output   ; --            ;
+; BA[0]     ; Output   ; --            ;
+; BA[1]     ; Output   ; --            ;
+; RAout[0]  ; Output   ; --            ;
+; RAout[1]  ; Output   ; --            ;
+; RAout[2]  ; Output   ; --            ;
+; RAout[3]  ; Output   ; --            ;
+; RAout[4]  ; Output   ; --            ;
+; RAout[5]  ; Output   ; --            ;
+; RAout[6]  ; Output   ; --            ;
+; RAout[7]  ; Output   ; --            ;
+; RAout[8]  ; Output   ; --            ;
+; RAout[9]  ; Output   ; --            ;
+; RAout[10] ; Output   ; --            ;
+; RAout[11] ; Output   ; --            ;
+; DQML      ; Output   ; --            ;
+; DQMH      ; Output   ; --            ;
+; RD[0]     ; Bidir    ; (0)           ;
+; RD[1]     ; Bidir    ; (0)           ;
+; RD[2]     ; Bidir    ; (0)           ;
+; RD[3]     ; Bidir    ; (0)           ;
+; RD[4]     ; Bidir    ; (0)           ;
+; RD[5]     ; Bidir    ; (0)           ;
+; RD[6]     ; Bidir    ; (0)           ;
+; RD[7]     ; Bidir    ; (0)           ;
+; nEN80     ; Input    ; (0)           ;
+; nWE       ; Input    ; (0)           ;
+; PHI1      ; Input    ; (1)           ;
+; C14M      ; Input    ; (0)           ;
+; Din[0]    ; Input    ; (0)           ;
+; Din[6]    ; Input    ; (0)           ;
+; Din[1]    ; Input    ; (0)           ;
+; Din[5]    ; Input    ; (0)           ;
+; Din[7]    ; Input    ; (0)           ;
+; Din[4]    ; Input    ; (0)           ;
+; Din[2]    ; Input    ; (0)           ;
+; Din[3]    ; Input    ; (0)           ;
+; nC07X     ; Input    ; (0)           ;
+; Ain[0]    ; Input    ; (0)           ;
+; Ain[1]    ; Input    ; (0)           ;
+; Ain[2]    ; Input    ; (0)           ;
+; Ain[3]    ; Input    ; (0)           ;
+; Ain[4]    ; Input    ; (0)           ;
+; Ain[5]    ; Input    ; (0)           ;
+; Ain[6]    ; Input    ; (0)           ;
+; Ain[7]    ; Input    ; (0)           ;
++-----------+----------+---------------+
 
 
-+-------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                       ;
-+------------+-------------+---------+---------------+--------+----------------------+------------------+
-; Name       ; Location    ; Fan-Out ; Usage         ; Global ; Global Resource Used ; Global Line Name ;
-+------------+-------------+---------+---------------+--------+----------------------+------------------+
-; C14M       ; PIN_12      ; 112     ; Clock         ; yes    ; Global Clock         ; GCLK0            ;
-; CS[0]~2    ; LC_X3_Y2_N8 ; 3       ; Clock enable  ; no     ; --                   ; --               ;
-; Equal9~1   ; LC_X3_Y3_N0 ; 16      ; Clock enable  ; no     ; --                   ; --               ;
-; Equal9~2   ; LC_X7_Y2_N5 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
-; RA[0]~15   ; LC_X2_Y2_N0 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
-; RDOE       ; LC_X3_Y3_N5 ; 8       ; Output enable ; no     ; --                   ; --               ;
-; RWMask~1   ; LC_X4_Y1_N4 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
-; S[2]       ; LC_X6_Y3_N6 ; 22      ; Sync. clear   ; no     ; --                   ; --               ;
-; UFMD[15]~0 ; LC_X6_Y1_N2 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
-; always2~8  ; LC_X3_Y3_N7 ; 16      ; Clock enable  ; no     ; --                   ; --               ;
-+------------+-------------+---------+---------------+--------+----------------------+------------------+
++---------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                           ;
++--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
+; Name                           ; Location    ; Fan-Out ; Usage         ; Global ; Global Resource Used ; Global Line Name ;
++--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
+; BA[1]~0                        ; LC_X2_Y2_N7 ; 2       ; Clock enable  ; no     ; --                   ; --               ;
+; C14M                           ; PIN_12      ; 123     ; Clock         ; yes    ; Global Clock         ; GCLK0            ;
+; CS[0]~2                        ; LC_X6_Y4_N2 ; 3       ; Clock enable  ; no     ; --                   ; --               ;
+; DQML~0                         ; LC_X2_Y4_N0 ; 2       ; Clock enable  ; no     ; --                   ; --               ;
+; Equal1~1                       ; LC_X7_Y4_N1 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
+; Equal1~2                       ; LC_X7_Y4_N2 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
+; Equal1~4                       ; LC_X5_Y4_N7 ; 4       ; Clock enable  ; no     ; --                   ; --               ;
+; Equal1~5                       ; LC_X4_Y4_N9 ; 3       ; Clock enable  ; no     ; --                   ; --               ;
+; Mux14~0                        ; LC_X2_Y2_N0 ; 2       ; Clock enable  ; no     ; --                   ; --               ;
+; RAM2E_UFM:ram2e_ufm|RWMask~1   ; LC_X6_Y1_N3 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
+; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X4_Y1_N1 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
+; RAM2E_UFM:ram2e_ufm|always2~8  ; LC_X7_Y4_N3 ; 16      ; Clock enable  ; no     ; --                   ; --               ;
+; RA[2]~0                        ; LC_X2_Y2_N5 ; 6       ; Clock enable  ; no     ; --                   ; --               ;
+; RDOE                           ; LC_X7_Y2_N7 ; 8       ; Output enable ; no     ; --                   ; --               ;
+; S[0]                           ; LC_X7_Y3_N8 ; 35      ; Sync. clear   ; no     ; --                   ; --               ;
+; S[3]                           ; LC_X5_Y4_N6 ; 32      ; Sync. clear   ; no     ; --                   ; --               ;
++--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
 
 
 +---------------------------------------------------------------------+
@@ -536,7 +543,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +------+----------+---------+----------------------+------------------+
 ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
 +------+----------+---------+----------------------+------------------+
-; C14M ; PIN_12   ; 112     ; Global Clock         ; GCLK0            ;
+; C14M ; PIN_12   ; 123     ; Global Clock         ; GCLK0            ;
 +------+----------+---------+----------------------+------------------+
 
 
@@ -545,120 +552,122 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-----------------------+--------------------+
 ; Routing Resource Type ; Usage              ;
 +-----------------------+--------------------+
-; C4s                   ; 139 / 784 ( 18 % ) ;
-; Direct links          ; 38 / 888 ( 4 % )   ;
+; C4s                   ; 163 / 784 ( 21 % ) ;
+; Direct links          ; 46 / 888 ( 5 % )   ;
 ; Global clocks         ; 1 / 4 ( 25 % )     ;
 ; LAB clocks            ; 6 / 32 ( 19 % )    ;
-; LUT chains            ; 4 / 216 ( 2 % )    ;
-; Local interconnects   ; 282 / 888 ( 32 % ) ;
-; R4s                   ; 134 / 704 ( 19 % ) ;
+; LUT chains            ; 9 / 216 ( 4 % )    ;
+; Local interconnects   ; 324 / 888 ( 36 % ) ;
+; R4s                   ; 142 / 704 ( 20 % ) ;
 +-----------------------+--------------------+
 
 
 +---------------------------------------------------------------------------+
 ; LAB Logic Elements                                                        ;
 +--------------------------------------------+------------------------------+
-; Number of Logic Elements  (Average = 8.21) ; Number of LABs  (Total = 24) ;
+; Number of Logic Elements  (Average = 9.92) ; Number of LABs  (Total = 24) ;
 +--------------------------------------------+------------------------------+
-; 1                                          ; 2                            ;
+; 1                                          ; 0                            ;
 ; 2                                          ; 0                            ;
-; 3                                          ; 1                            ;
+; 3                                          ; 0                            ;
 ; 4                                          ; 0                            ;
-; 5                                          ; 1                            ;
-; 6                                          ; 1                            ;
+; 5                                          ; 0                            ;
+; 6                                          ; 0                            ;
 ; 7                                          ; 0                            ;
-; 8                                          ; 3                            ;
-; 9                                          ; 3                            ;
-; 10                                         ; 13                           ;
+; 8                                          ; 1                            ;
+; 9                                          ; 0                            ;
+; 10                                         ; 23                           ;
 +--------------------------------------------+------------------------------+
 
 
 +-------------------------------------------------------------------+
 ; LAB-wide Signals                                                  ;
 +------------------------------------+------------------------------+
-; LAB-wide Signals  (Average = 1.38) ; Number of LABs  (Total = 24) ;
+; LAB-wide Signals  (Average = 1.54) ; Number of LABs  (Total = 24) ;
 +------------------------------------+------------------------------+
 ; 1 Clock                            ; 23                           ;
-; 1 Clock enable                     ; 9                            ;
-; 2 Clock enables                    ; 1                            ;
+; 1 Clock enable                     ; 10                           ;
+; 1 Sync. clear                      ; 2                            ;
+; 2 Clock enables                    ; 2                            ;
 +------------------------------------+------------------------------+
 
 
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced                                                        ;
-+---------------------------------------------+------------------------------+
-; Number of Signals Sourced  (Average = 8.54) ; Number of LABs  (Total = 24) ;
-+---------------------------------------------+------------------------------+
-; 0                                           ; 0                            ;
-; 1                                           ; 2                            ;
-; 2                                           ; 0                            ;
-; 3                                           ; 1                            ;
-; 4                                           ; 0                            ;
-; 5                                           ; 1                            ;
-; 6                                           ; 1                            ;
-; 7                                           ; 0                            ;
-; 8                                           ; 3                            ;
-; 9                                           ; 2                            ;
-; 10                                          ; 11                           ;
-; 11                                          ; 1                            ;
-; 12                                          ; 1                            ;
-; 13                                          ; 0                            ;
-; 14                                          ; 1                            ;
-+---------------------------------------------+------------------------------+
++-----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                         ;
++----------------------------------------------+------------------------------+
+; Number of Signals Sourced  (Average = 10.17) ; Number of LABs  (Total = 24) ;
++----------------------------------------------+------------------------------+
+; 0                                            ; 0                            ;
+; 1                                            ; 0                            ;
+; 2                                            ; 0                            ;
+; 3                                            ; 0                            ;
+; 4                                            ; 0                            ;
+; 5                                            ; 0                            ;
+; 6                                            ; 0                            ;
+; 7                                            ; 0                            ;
+; 8                                            ; 1                            ;
+; 9                                            ; 0                            ;
+; 10                                           ; 21                           ;
+; 11                                           ; 1                            ;
+; 12                                           ; 0                            ;
+; 13                                           ; 0                            ;
+; 14                                           ; 0                            ;
+; 15                                           ; 1                            ;
++----------------------------------------------+------------------------------+
 
 
 +--------------------------------------------------------------------------------+
 ; LAB Signals Sourced Out                                                        ;
 +-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out  (Average = 6.33) ; Number of LABs  (Total = 24) ;
+; Number of Signals Sourced Out  (Average = 7.08) ; Number of LABs  (Total = 24) ;
 +-------------------------------------------------+------------------------------+
 ; 0                                               ; 0                            ;
-; 1                                               ; 2                            ;
+; 1                                               ; 1                            ;
 ; 2                                               ; 0                            ;
 ; 3                                               ; 2                            ;
-; 4                                               ; 2                            ;
+; 4                                               ; 1                            ;
 ; 5                                               ; 3                            ;
-; 6                                               ; 4                            ;
+; 6                                               ; 2                            ;
 ; 7                                               ; 3                            ;
-; 8                                               ; 2                            ;
-; 9                                               ; 2                            ;
+; 8                                               ; 4                            ;
+; 9                                               ; 4                            ;
 ; 10                                              ; 3                            ;
 ; 11                                              ; 0                            ;
-; 12                                              ; 1                            ;
+; 12                                              ; 0                            ;
+; 13                                              ; 1                            ;
 +-------------------------------------------------+------------------------------+
 
 
 +-----------------------------------------------------------------------------+
 ; LAB Distinct Inputs                                                         ;
 +----------------------------------------------+------------------------------+
-; Number of Distinct Inputs  (Average = 10.42) ; Number of LABs  (Total = 24) ;
+; Number of Distinct Inputs  (Average = 12.17) ; Number of LABs  (Total = 24) ;
 +----------------------------------------------+------------------------------+
 ; 0                                            ; 0                            ;
 ; 1                                            ; 0                            ;
 ; 2                                            ; 0                            ;
-; 3                                            ; 3                            ;
-; 4                                            ; 0                            ;
-; 5                                            ; 2                            ;
-; 6                                            ; 2                            ;
-; 7                                            ; 1                            ;
-; 8                                            ; 3                            ;
+; 3                                            ; 0                            ;
+; 4                                            ; 1                            ;
+; 5                                            ; 0                            ;
+; 6                                            ; 1                            ;
+; 7                                            ; 2                            ;
+; 8                                            ; 2                            ;
 ; 9                                            ; 1                            ;
-; 10                                           ; 0                            ;
-; 11                                           ; 2                            ;
-; 12                                           ; 2                            ;
-; 13                                           ; 1                            ;
-; 14                                           ; 2                            ;
+; 10                                           ; 2                            ;
+; 11                                           ; 1                            ;
+; 12                                           ; 3                            ;
+; 13                                           ; 3                            ;
+; 14                                           ; 1                            ;
 ; 15                                           ; 1                            ;
-; 16                                           ; 1                            ;
-; 17                                           ; 1                            ;
-; 18                                           ; 0                            ;
-; 19                                           ; 1                            ;
+; 16                                           ; 2                            ;
+; 17                                           ; 2                            ;
+; 18                                           ; 1                            ;
+; 19                                           ; 0                            ;
 ; 20                                           ; 0                            ;
 ; 21                                           ; 0                            ;
 ; 22                                           ; 0                            ;
 ; 23                                           ; 0                            ;
-; 24                                           ; 0                            ;
-; 25                                           ; 1                            ;
+; 24                                           ; 1                            ;
 +----------------------------------------------+------------------------------+
 
 
@@ -697,17 +706,17 @@ Info (332129): Detected timing requirements -- optimizing circuit to achieve onl
 Info (332111): Found 3 clocks
     Info (332111):   Period   Clock Name
     Info (332111): ======== ============
-    Info (332111):  200.000        ARCLK
     Info (332111):   69.841         C14M
-    Info (332111):  200.000        DRCLK
+    Info (332111):  200.000 ram2e_ufm|ARCLK|regout
+    Info (332111):  200.000 ram2e_ufm|DRCLK|regout
 Info (186079): Completed User Assigned Global Signals Promotion Operation
-Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 8
+Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
 Info (186079): Completed Auto Global Promotion Operation
 Info (176234): Starting register packing
 Info (186468): Started processing fast register assignments
 Info (186469): Finished processing fast register assignments
 Info (176235): Finished register packing
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
 Info (170189): Fitter placement preparation operations beginning
 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
@@ -715,18 +724,17 @@ Info (170191): Fitter placement operations beginning
 Info (170137): Fitter placement was successful
 Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
 Info (170193): Fitter routing operations beginning
-Info (170089): 5e+01 ns of routing delay (approximately 3.1% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
-Info (170195): Router estimated average interconnect usage is 20% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170089): 5e+01 ns of routing delay (approximately 3.0% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
+Info (170195): Router estimated average interconnect usage is 24% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 24% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
+Info (170202): The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.83 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.84 seconds.
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
+Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 13770 megabytes
-    Info: Processing ended: Thu Sep 21 05:34:37 2023
+    Info: Peak virtual memory: 13747 megabytes
+    Info: Processing ended: Thu Dec 28 23:09:44 2023
     Info: Elapsed time: 00:00:04
     Info: Total CPU time (on all processors): 00:00:04
 
@@ -734,6 +742,6 @@ Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
 +----------------------------+
 ; Fitter Suppressed Messages ;
 +----------------------------+
-The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg.
+The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg.
 
 
diff --git a/CPLD/MAXII/output_files/RAM2E.fit.summary b/CPLD/MAXII/output_files/RAM2E.fit.summary
index f06b8fb..304f616 100644
--- a/CPLD/MAXII/output_files/RAM2E.fit.summary
+++ b/CPLD/MAXII/output_files/RAM2E.fit.summary
@@ -1,11 +1,11 @@
-Fitter Status : Successful - Thu Sep 21 05:34:37 2023
-Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Fitter Status : Successful - Thu Dec 28 23:09:44 2023
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
 Family : MAX II
 Device : EPM240T100C5
 Timing Models : Final
-Total logic elements : 197 / 240 ( 82 % )
+Total logic elements : 238 / 240 ( 99 % )
 Total pins : 70 / 80 ( 88 % )
 Total virtual pins : 0
 UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXII/output_files/RAM2E.flow.rpt b/CPLD/MAXII/output_files/RAM2E.flow.rpt
index ecb9121..3d4dbde 100644
--- a/CPLD/MAXII/output_files/RAM2E.flow.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.flow.rpt
@@ -1,6 +1,6 @@
 Flow report for RAM2E
-Thu Sep 21 05:34:45 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Thu Dec 28 23:09:50 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
 ---------------------
@@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
 
 
 
-+---------------------------------------------------------------------+
-; Flow Summary                                                        ;
-+-----------------------+---------------------------------------------+
-; Flow Status           ; Successful - Thu Sep 21 05:34:41 2023       ;
-; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name         ; RAM2E                                       ;
-; Top-level Entity Name ; RAM2E                                       ;
-; Family                ; MAX II                                      ;
-; Device                ; EPM240T100C5                                ;
-; Timing Models         ; Final                                       ;
-; Total logic elements  ; 197 / 240 ( 82 % )                          ;
-; Total pins            ; 70 / 80 ( 88 % )                            ;
-; Total virtual pins    ; 0                                           ;
-; UFM blocks            ; 1 / 1 ( 100 % )                             ;
-+-----------------------+---------------------------------------------+
++-------------------------------------------------------------------------------------+
+; Flow Summary                                                                        ;
++-----------------------+-------------------------------------------------------------+
+; Flow Status           ; Successful - Thu Dec 28 23:09:46 2023                       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
+; Revision Name         ; RAM2E                                                       ;
+; Top-level Entity Name ; RAM2E                                                       ;
+; Family                ; MAX II                                                      ;
+; Device                ; EPM240T100C5                                                ;
+; Timing Models         ; Final                                                       ;
+; Total logic elements  ; 238 / 240 ( 99 % )                                          ;
+; Total pins            ; 70 / 80 ( 88 % )                                            ;
+; Total virtual pins    ; 0                                                           ;
+; UFM blocks            ; 1 / 1 ( 100 % )                                             ;
++-----------------------+-------------------------------------------------------------+
 
 
 +-----------------------------------------+
@@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 09/21/2023 05:33:57 ;
+; Start date & time ; 12/28/2023 23:09:12 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; RAM2E               ;
 +-------------------+---------------------+
@@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------+------------------------------+---------------+-------------+------------+
 ; Assignment Name                       ; Value                        ; Default Value ; Entity Name ; Section Id ;
 +---------------------------------------+------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID                 ; 121381084694.169528883703908 ; --            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID                 ; 121381084694.170382295203604 ; --            ; --          ; --         ;
 ; MAX_CORE_JUNCTION_TEMP                ; 85                           ; --            ; --          ; --         ;
 ; MIN_CORE_JUNCTION_TEMP                ; 0                            ; --            ; --          ; --         ;
 ; NUM_PARALLEL_PROCESSORS               ; 4                            ; --            ; --          ; --         ;
@@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:35     ; 1.0                     ; 13144 MB            ; 00:00:49                           ;
-; Fitter               ; 00:00:04     ; 1.0                     ; 13770 MB            ; 00:00:04                           ;
-; Assembler            ; 00:00:02     ; 1.0                     ; 13091 MB            ; 00:00:01                           ;
-; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 13089 MB            ; 00:00:02                           ;
-; Total                ; 00:00:43     ; --                      ; --                  ; 00:00:56                           ;
+; Analysis & Synthesis ; 00:00:28     ; 1.0                     ; 13113 MB            ; 00:00:42                           ;
+; Fitter               ; 00:00:04     ; 1.0                     ; 13747 MB            ; 00:00:04                           ;
+; Assembler            ; 00:00:00     ; 1.0                     ; 13067 MB            ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 13064 MB            ; 00:00:02                           ;
+; Total                ; 00:00:34     ; --                      ; --                  ; 00:00:49                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
diff --git a/CPLD/MAXII/output_files/RAM2E.jdi b/CPLD/MAXII/output_files/RAM2E.jdi
index eb86129..dad2d4f 100644
--- a/CPLD/MAXII/output_files/RAM2E.jdi
+++ b/CPLD/MAXII/output_files/RAM2E.jdi
@@ -1,6 +1,6 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="c40857e37f967e83d8af"/>
+    <hash md5_digest_80b="f1177731eb35f907c990"/>
   </project>
   <file_info>
     <file device="EPM240T100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>
diff --git a/CPLD/MAXII/output_files/RAM2E.map.rpt b/CPLD/MAXII/output_files/RAM2E.map.rpt
index da29b55..d5d2070 100644
--- a/CPLD/MAXII/output_files/RAM2E.map.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.map.rpt
@@ -1,6 +1,6 @@
 Analysis & Synthesis report for RAM2E
-Thu Sep 21 05:34:32 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Thu Dec 28 23:09:39 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
 ---------------------
@@ -17,7 +17,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
   9. General Register Statistics
  10. Inverted Register Statistics
  11. Multiplexer Restructuring Statistics (Restructuring Performed)
- 12. Port Connectivity Checks: "UFM:UFM_inst"
+ 12. Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst"
  13. Analysis & Synthesis Messages
  14. Analysis & Synthesis Suppressed Messages
 
@@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
 
 
 
-+---------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                              ;
-+-----------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:34:32 2023       ;
-; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name               ; RAM2E                                       ;
-; Top-level Entity Name       ; RAM2E                                       ;
-; Family                      ; MAX II                                      ;
-; Total logic elements        ; 205                                         ;
-; Total pins                  ; 70                                          ;
-; Total virtual pins          ; 0                                           ;
-; UFM blocks                  ; 1 / 1 ( 100 % )                             ;
-+-----------------------------+---------------------------------------------+
++-------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                              ;
++-----------------------------+-------------------------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Thu Dec 28 23:09:39 2023                       ;
+; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
+; Revision Name               ; RAM2E                                                       ;
+; Top-level Entity Name       ; RAM2E                                                       ;
+; Family                      ; MAX II                                                      ;
+; Total logic elements        ; 244                                                         ;
+; Total pins                  ; 70                                                          ;
+; Total virtual pins          ; 0                                                           ;
+; UFM blocks                  ; 1 / 1 ( 100 % )                                             ;
++-----------------------------+-------------------------------------------------------------+
 
 
 +------------------------------------------------------------------------------------------------------------+
@@ -146,15 +146,16 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------+-------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                      ;
-+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type                        ; File Name with Absolute Path              ; Library ;
-+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
-; ../RAM2E-MAX.v                   ; yes             ; User Verilog HDL File            ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v ;         ;
-; UFM.v                            ; yes             ; User Wizard-Generated File       ; //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v ;         ;
-; ../RAM2E.mif                     ; yes             ; User Memory Initialization File  ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.mif   ;         ;
-+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                            ;
++----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                        ; File Name with Absolute Path    ; Library ;
++----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
+; ../RAM2E.v                       ; yes             ; User Verilog HDL File            ; Y:/Repos/RAM2E/CPLD/RAM2E.v     ;         ;
+; ../UFM-MAX.v                     ; yes             ; User Verilog HDL File            ; Y:/Repos/RAM2E/CPLD/UFM-MAX.v   ;         ;
+; UFM.v                            ; yes             ; User Wizard-Generated File       ; Y:/Repos/RAM2E/CPLD/MAXII/UFM.v ;         ;
+; ../RAM2E.mif                     ; yes             ; User Memory Initialization File  ; Y:/Repos/RAM2E/CPLD/RAM2E.mif   ;         ;
++----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
 
 
 +-----------------------------------------------------+
@@ -162,56 +163,57 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------+-------+
 ; Resource                                    ; Usage ;
 +---------------------------------------------+-------+
-; Total logic elements                        ; 205   ;
-;     -- Combinational with no register       ; 93    ;
-;     -- Register only                        ; 27    ;
-;     -- Combinational with a register        ; 85    ;
+; Total logic elements                        ; 244   ;
+;     -- Combinational with no register       ; 121   ;
+;     -- Register only                        ; 32    ;
+;     -- Combinational with a register        ; 91    ;
 ;                                             ;       ;
 ; Logic element usage by number of LUT inputs ;       ;
-;     -- 4 input functions                    ; 103   ;
-;     -- 3 input functions                    ; 29    ;
-;     -- 2 input functions                    ; 42    ;
-;     -- 1 input functions                    ; 3     ;
+;     -- 4 input functions                    ; 118   ;
+;     -- 3 input functions                    ; 41    ;
+;     -- 2 input functions                    ; 48    ;
+;     -- 1 input functions                    ; 4     ;
 ;     -- 0 input functions                    ; 1     ;
 ;                                             ;       ;
 ; Logic elements by mode                      ;       ;
-;     -- normal mode                          ; 191   ;
+;     -- normal mode                          ; 230   ;
 ;     -- arithmetic mode                      ; 14    ;
 ;     -- qfbk mode                            ; 0     ;
 ;     -- register cascade mode                ; 0     ;
-;     -- synchronous clear/load mode          ; 1     ;
+;     -- synchronous clear/load mode          ; 3     ;
 ;     -- asynchronous clear/load mode         ; 0     ;
 ;                                             ;       ;
-; Total registers                             ; 112   ;
+; Total registers                             ; 123   ;
 ; Total logic cells in carry chains           ; 15    ;
 ; I/O pins                                    ; 70    ;
 ; UFM blocks                                  ; 1     ;
 ; Maximum fan-out node                        ; C14M  ;
-; Maximum fan-out                             ; 112   ;
-; Total fan-out                               ; 850   ;
-; Average fan-out                             ; 3.08  ;
+; Maximum fan-out                             ; 123   ;
+; Total fan-out                               ; 977   ;
+; Average fan-out                             ; 3.10  ;
 +---------------------------------------------+-------+
 
 
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                   ; Entity Name         ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
-; |RAM2E                                                    ; 205 (205)   ; 112          ; 1          ; 70   ; 0            ; 93 (93)      ; 27 (27)           ; 85 (85)          ; 15 (15)         ; 0 (0)      ; |RAM2E                                                                ; RAM2E               ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|UFM:UFM_inst                                                   ; UFM                 ; work         ;
-;       |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
+; Compilation Hierarchy Node                                   ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                                       ; Entity Name         ; Library Name ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
+; |RAM2E                                                       ; 244 (181)   ; 123          ; 1          ; 70   ; 0            ; 121 (91)     ; 32 (24)           ; 91 (66)          ; 15 (15)         ; 0 (0)      ; |RAM2E                                                                                    ; RAM2E               ; work         ;
+;    |RAM2E_UFM:ram2e_ufm|                                     ; 63 (63)     ; 33           ; 1          ; 0    ; 0            ; 30 (30)      ; 8 (8)             ; 25 (25)          ; 0 (0)           ; 0 (0)      ; |RAM2E|RAM2E_UFM:ram2e_ufm                                                                ; RAM2E_UFM           ; work         ;
+;       |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst                                                   ; UFM                 ; work         ;
+;          |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work         ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
-+--------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis IP Cores Summary                                                                              ;
-+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
-; Vendor ; IP Core Name              ; Version ; Release Date ; License Type ; Entity Instance     ; IP Include File ;
-+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
-; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1    ; N/A          ; N/A          ; |RAM2E|UFM:UFM_inst ; UFM.v           ;
-+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                  ;
++--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
+; Vendor ; IP Core Name              ; Version ; Release Date ; License Type ; Entity Instance                         ; IP Include File ;
++--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
+; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1    ; N/A          ; N/A          ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM.v           ;
++--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
 
 
 +------------------------------------------------------+
@@ -219,12 +221,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------------------------------------------+-------+
 ; Statistic                                    ; Value ;
 +----------------------------------------------+-------+
-; Total registers                              ; 112   ;
-; Number of registers using Synchronous Clear  ; 1     ;
+; Total registers                              ; 123   ;
+; Number of registers using Synchronous Clear  ; 3     ;
 ; Number of registers using Synchronous Load   ; 0     ;
 ; Number of registers using Asynchronous Clear ; 0     ;
 ; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 60    ;
+; Number of registers using Clock Enable       ; 62    ;
 ; Number of registers using Preset             ; 0     ;
 +----------------------------------------------+-------+
 
@@ -234,30 +236,36 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------------------------------------+---------+
 ; Inverted Register                      ; Fan out ;
 +----------------------------------------+---------+
-; nCS~reg0                               ; 1       ;
-; nRAS~reg0                              ; 1       ;
-; nCAS~reg0                              ; 1       ;
-; nRWE~reg0                              ; 1       ;
+; nRASout~reg0                           ; 1       ;
+; nCASout~reg0                           ; 1       ;
+; nRWEout~reg0                           ; 1       ;
 ; DQML~reg0                              ; 1       ;
 ; DQMH~reg0                              ; 1       ;
-; Total number of inverted registers = 6 ;         ;
+; CKE                                    ; 1       ;
+; nRAS                                   ; 1       ;
+; nCAS                                   ; 1       ;
+; nRWE                                   ; 1       ;
+; Total number of inverted registers = 9 ;         ;
 +----------------------------------------+---------+
 
 
-+------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |RAM2E|RA[0]~reg0          ;
-; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |RAM2E|S[2]                ;
-; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |RAM2E|CS[0]               ;
-; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |RAM2E|RWMask[4]           ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                     ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output           ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |RAM2E|S[0]                          ;
+; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |RAM2E|CS[0]                         ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[5] ;
+; 16:1               ; 2 bits    ; 20 LEs        ; 2 LEs                ; 18 LEs                 ; Yes        ; |RAM2E|BA[1]~reg0                    ;
+; 17:1               ; 4 bits    ; 44 LEs        ; 8 LEs                ; 36 LEs                 ; Yes        ; |RAM2E|RA[4]                         ;
+; 19:1               ; 2 bits    ; 24 LEs        ; 4 LEs                ; 20 LEs                 ; Yes        ; |RAM2E|RA[2]                         ;
+; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |RAM2E|DQML~reg0                     ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
 
 
 +------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "UFM:UFM_inst"                                                                         ;
+; Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst"                                                     ;
 +--------+--------+----------+-------------------------------------------------------------------------------------+
 ; Port   ; Type   ; Severity ; Details                                                                             ;
 +--------+--------+----------+-------------------------------------------------------------------------------------+
@@ -272,35 +280,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-------------------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Thu Sep 21 05:33:57 2023
+    Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
+    Info: Processing started: Thu Dec 28 23:09:11 2023
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
-Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2e/cpld/ram2e-max.v
-    Info (12023): Found entity 1: RAM2E File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
+    Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ufm-max.v
+    Info (12023): Found entity 1: RAM2E_UFM File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
-    Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47
-    Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
+    Info (12023): Found entity 1: UFM_altufm_none_lbr File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47
+    Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
 Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
-Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 93
-Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
-Info (21057): Implemented 276 device resources after synthesis - the final resource count might be different
+Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 112
+Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 79
+Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "nCSout" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 78
+Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (21074): Design contains 1 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "nWE80" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 11
+Info (21057): Implemented 315 device resources after synthesis - the final resource count might be different
     Info (21058): Implemented 22 input pins
     Info (21059): Implemented 40 output pins
     Info (21060): Implemented 8 bidirectional pins
-    Info (21061): Implemented 205 logic cells
+    Info (21061): Implemented 244 logic cells
     Info (21070): Implemented 1 User Flash Memory blocks
-Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 13144 megabytes
-    Info: Processing ended: Thu Sep 21 05:34:32 2023
-    Info: Elapsed time: 00:00:35
-    Info: Total CPU time (on all processors): 00:00:49
+Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
+    Info: Peak virtual memory: 13113 megabytes
+    Info: Processing ended: Thu Dec 28 23:09:39 2023
+    Info: Elapsed time: 00:00:28
+    Info: Total CPU time (on all processors): 00:00:42
 
 
 +------------------------------------------+
 ; Analysis & Synthesis Suppressed Messages ;
 +------------------------------------------+
-The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg.
+The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg.
 
 
diff --git a/CPLD/MAXII/output_files/RAM2E.map.smsg b/CPLD/MAXII/output_files/RAM2E.map.smsg
index 06be456..b2004b0 100644
--- a/CPLD/MAXII/output_files/RAM2E.map.smsg
+++ b/CPLD/MAXII/output_files/RAM2E.map.smsg
@@ -1,3 +1,3 @@
-Warning (10273): Verilog HDL warning at RAM2E-MAX.v(46): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 46
-Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73
-Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189
+Warning (10273): Verilog HDL warning at RAM2E.v(74): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 74
+Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73
+Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189
diff --git a/CPLD/MAXII/output_files/RAM2E.map.summary b/CPLD/MAXII/output_files/RAM2E.map.summary
index 8b68ed4..0d1b334 100644
--- a/CPLD/MAXII/output_files/RAM2E.map.summary
+++ b/CPLD/MAXII/output_files/RAM2E.map.summary
@@ -1,9 +1,9 @@
-Analysis & Synthesis Status : Successful - Thu Sep 21 05:34:32 2023
-Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Analysis & Synthesis Status : Successful - Thu Dec 28 23:09:39 2023
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
 Family : MAX II
-Total logic elements : 205
+Total logic elements : 244
 Total pins : 70
 Total virtual pins : 0
 UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXII/output_files/RAM2E.pin b/CPLD/MAXII/output_files/RAM2E.pin
index f8fa7ef..3f032f5 100644
--- a/CPLD/MAXII/output_files/RAM2E.pin
+++ b/CPLD/MAXII/output_files/RAM2E.pin
@@ -58,41 +58,41 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 CHIP  "RAM2E"  ASSIGNED TO AN: EPM240T100C5
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
 -------------------------------------------------------------------------------------------------------------
 GND*                         : 1         :        :                   :         : 2         :                
-nRWE                         : 2         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nCAS                         : 3         : output : 3.3-V LVCMOS      :         : 1         : Y              
-CKE                          : 4         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRAS                         : 5         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nRWEout                      : 2         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nCASout                      : 3         : output : 3.3-V LVCMOS      :         : 1         : Y              
+CKEout                       : 4         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nRASout                      : 5         : output : 3.3-V LVCMOS      :         : 1         : Y              
 BA[0]                        : 6         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[11]                       : 7         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nCS                          : 8         : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[11]                    : 7         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nCSout                       : 8         : output : 3.3-V LVCMOS      :         : 1         : Y              
 VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
 GNDIO                        : 10        : gnd    :                   :         :           :                
 GNDINT                       : 11        : gnd    :                   :         :           :                
 C14M                         : 12        : input  : 3.3-V LVCMOS      :         : 1         : Y              
 VCCINT                       : 13        : power  :                   : 2.5V/3.3V :           :                
 BA[1]                        : 14        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[9]                        : 15        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[10]                       : 16        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[8]                        : 17        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[0]                        : 18        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[7]                        : 19        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[1]                        : 20        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[6]                        : 21        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[9]                     : 15        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[10]                    : 16        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[8]                     : 17        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[0]                     : 18        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[7]                     : 19        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[1]                     : 20        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[6]                     : 21        : output : 3.3-V LVCMOS      :         : 1         : Y              
 TMS                          : 22        : input  :                   :         : 1         :                
 TDI                          : 23        : input  :                   :         : 1         :                
 TCK                          : 24        : input  :                   :         : 1         :                
 TDO                          : 25        : output :                   :         : 1         :                
-RA[4]                        : 26        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[3]                        : 27        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[4]                     : 26        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[3]                     : 27        : output : 3.3-V LVCMOS      :         : 1         : Y              
 nEN80                        : 28        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-RA[5]                        : 29        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[2]                        : 30        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[5]                     : 29        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[2]                     : 30        : output : 3.3-V LVCMOS      :         : 1         : Y              
 VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
 GNDIO                        : 32        : gnd    :                   :         :           :                
 nWE80                        : 33        : input  : 3.3-V LVCMOS      :         : 1         : Y              
diff --git a/CPLD/MAXII/output_files/RAM2E.pof b/CPLD/MAXII/output_files/RAM2E.pof
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diff --git a/CPLD/MAXII/output_files/RAM2E.sta.rpt b/CPLD/MAXII/output_files/RAM2E.sta.rpt
index 1a2c492..c4c394c 100644
--- a/CPLD/MAXII/output_files/RAM2E.sta.rpt
+++ b/CPLD/MAXII/output_files/RAM2E.sta.rpt
@@ -1,6 +1,6 @@
 Timing Analyzer report for RAM2E
-Thu Sep 21 05:34:45 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Thu Dec 28 23:09:50 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
 ---------------------
@@ -17,11 +17,11 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
   9. Recovery Summary
  10. Removal Summary
  11. Minimum Pulse Width Summary
- 12. Setup: 'DRCLK'
- 13. Setup: 'ARCLK'
+ 12. Setup: 'ram2e_ufm|DRCLK|regout'
+ 13. Setup: 'ram2e_ufm|ARCLK|regout'
  14. Setup: 'C14M'
- 15. Hold: 'ARCLK'
- 16. Hold: 'DRCLK'
+ 15. Hold: 'ram2e_ufm|DRCLK|regout'
+ 16. Hold: 'ram2e_ufm|ARCLK|regout'
  17. Hold: 'C14M'
  18. Setup Transfers
  19. Hold Transfers
@@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.
 
 
 
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary                                                     ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Timing Analyzer       ; Legacy Timing Analyzer                              ;
-; Revision Name         ; RAM2E                                               ;
-; Device Family         ; MAX II                                              ;
-; Device Name           ; EPM240T100C5                                        ;
-; Timing Models         ; Final                                               ;
-; Delay Model           ; Slow Model                                          ;
-; Rise/Fall Delays      ; Unavailable                                         ;
-+-----------------------+-----------------------------------------------------+
++---------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                                     ;
++-----------------------+---------------------------------------------------------------------+
+; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
+; Timing Analyzer       ; Legacy Timing Analyzer                                              ;
+; Revision Name         ; RAM2E                                                               ;
+; Device Family         ; MAX II                                                              ;
+; Device Name           ; EPM240T100C5                                                        ;
+; Timing Models         ; Final                                                               ;
+; Delay Model           ; Slow Model                                                          ;
+; Rise/Fall Delays      ; Unavailable                                                         ;
++-----------------------+---------------------------------------------------------------------+
 
 
 +------------------------------------------+
@@ -80,11 +80,10 @@ https://fpgasoftware.intel.com/eula.
 ; Maximum allowed            ; 4           ;
 ;                            ;             ;
 ; Average used               ; 1.00        ;
-; Maximum used               ; 2           ;
+; Maximum used               ; 1           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.2%      ;
 +----------------------------+-------------+
 
 
@@ -93,54 +92,54 @@ https://fpgasoftware.intel.com/eula.
 +------------------+--------+--------------------------+
 ; SDC File Path    ; Status ; Read at                  ;
 +------------------+--------+--------------------------+
-; ../RAM2E.sdc     ; OK     ; Thu Sep 21 05:34:44 2023 ;
-; ../RAM2E-MAX.sdc ; OK     ; Thu Sep 21 05:34:44 2023 ;
+; ../RAM2E.sdc     ; OK     ; Thu Dec 28 23:09:50 2023 ;
+; ../RAM2E-MAX.sdc ; OK     ; Thu Dec 28 23:09:50 2023 ;
 +------------------+--------+--------------------------+
 
 
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                              ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; Clock Name ; Type ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets   ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; ARCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ARCLK } ;
-; C14M       ; Base ; 69.841  ; 14.32 MHz ; 0.000 ; 34.920  ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { C14M }  ;
-; DRCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DRCLK } ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                           ;
++------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
+; Clock Name             ; Type ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                    ;
++------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
+; C14M                   ; Base ; 69.841  ; 14.32 MHz ; 0.000 ; 34.920  ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { C14M }                   ;
+; ram2e_ufm|ARCLK|regout ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ram2e_ufm|ARCLK|regout } ;
+; ram2e_ufm|DRCLK|regout ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ram2e_ufm|DRCLK|regout } ;
++------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
 
 
-+-------------------------------------------------+
-; Fmax Summary                                    ;
-+-----------+-----------------+------------+------+
-; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
-+-----------+-----------------+------------+------+
-; 10.0 MHz  ; 10.0 MHz        ; ARCLK      ;      ;
-; 10.0 MHz  ; 10.0 MHz        ; DRCLK      ;      ;
-; 61.13 MHz ; 61.13 MHz       ; C14M       ;      ;
-+-----------+-----------------+------------+------+
++-------------------------------------------------------------+
+; Fmax Summary                                                ;
++-----------+-----------------+------------------------+------+
+; Fmax      ; Restricted Fmax ; Clock Name             ; Note ;
++-----------+-----------------+------------------------+------+
+; 10.0 MHz  ; 10.0 MHz        ; ram2e_ufm|ARCLK|regout ;      ;
+; 10.0 MHz  ; 10.0 MHz        ; ram2e_ufm|DRCLK|regout ;      ;
+; 70.81 MHz ; 70.81 MHz       ; C14M                   ;      ;
++-----------+-----------------+------------------------+------+
 This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
 
 
-+---------------------------------+
-; Setup Summary                   ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; DRCLK ; -23.265 ; -23.265       ;
-; ARCLK ; -23.125 ; -23.125       ;
-; C14M  ; -8.026  ; -92.836       ;
-+-------+---------+---------------+
++--------------------------------------------------+
+; Setup Summary                                    ;
++------------------------+---------+---------------+
+; Clock                  ; Slack   ; End Point TNS ;
++------------------------+---------+---------------+
+; ram2e_ufm|DRCLK|regout ; -23.738 ; -23.738       ;
+; ram2e_ufm|ARCLK|regout ; -23.720 ; -23.720       ;
+; C14M                   ; -9.644  ; -106.641      ;
++------------------------+---------+---------------+
 
 
-+---------------------------------+
-; Hold Summary                    ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; ARCLK ; -16.874 ; -16.874       ;
-; DRCLK ; -16.746 ; -16.746       ;
-; C14M  ; 1.415   ; 0.000         ;
-+-------+---------+---------------+
++--------------------------------------------------+
+; Hold Summary                                     ;
++------------------------+---------+---------------+
+; Clock                  ; Slack   ; End Point TNS ;
++------------------------+---------+---------------+
+; ram2e_ufm|DRCLK|regout ; -16.287 ; -16.287       ;
+; ram2e_ufm|ARCLK|regout ; -16.279 ; -16.279       ;
+; C14M                   ; 1.421   ; 0.000         ;
++------------------------+---------+---------------+
 
 
 --------------------
@@ -155,302 +154,302 @@ No paths to report.
 No paths to report.
 
 
-+--------------------------------+
-; Minimum Pulse Width Summary    ;
-+-------+--------+---------------+
-; Clock ; Slack  ; End Point TNS ;
-+-------+--------+---------------+
-; C14M  ; 34.654 ; 0.000         ;
-; ARCLK ; 70.000 ; 0.000         ;
-; DRCLK ; 70.000 ; 0.000         ;
-+-------+--------+---------------+
++-------------------------------------------------+
+; Minimum Pulse Width Summary                     ;
++------------------------+--------+---------------+
+; Clock                  ; Slack  ; End Point TNS ;
++------------------------+--------+---------------+
+; C14M                   ; 34.654 ; 0.000         ;
+; ram2e_ufm|ARCLK|regout ; 70.000 ; 0.000         ;
+; ram2e_ufm|DRCLK|regout ; 70.000 ; 0.000         ;
++------------------------+--------+---------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'DRCLK'                                                                                                                                                                                                                                                            ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -23.265 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M         ; DRCLK       ; 0.001        ; -1.725     ; 1.541      ;
-; -23.253 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M         ; DRCLK       ; 0.001        ; -1.725     ; 1.529      ;
-; 100.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 200.000      ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'ram2e_ufm|DRCLK|regout'                                                                                                                                                                                                                                                                                                        ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                                       ; To Node                                                                                                         ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; -23.738 ; RAM2E_UFM:ram2e_ufm|DRDIn                                                                                       ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M                   ; ram2e_ufm|DRCLK|regout ; 0.001        ; -1.671     ; 2.068      ;
+; -23.712 ; RAM2E_UFM:ram2e_ufm|DRShift                                                                                     ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M                   ; ram2e_ufm|DRCLK|regout ; 0.001        ; -1.671     ; 2.042      ;
+; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000      ; 0.000      ; 80.000     ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'ARCLK'                                                                                                                                                                                                                                                                                    ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -23.125 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M         ; ARCLK       ; 0.001        ; -1.597     ; 1.529      ;
-; 100.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 200.000      ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'ram2e_ufm|ARCLK|regout'                                                                                                                                                                                                                                                                                                                                ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                                                   ; To Node                                                                                                                     ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; -23.720 ; RAM2E_UFM:ram2e_ufm|ARShift                                                                                                 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M                   ; ram2e_ufm|ARCLK|regout ; 0.001        ; -1.663     ; 2.058      ;
+; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000      ; 0.000      ; 80.000     ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
 
 
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'C14M'                                                                                                                                                                             ;
-+--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node                                                                                   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
-; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[4]    ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 9.419      ;
-; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[5]    ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 9.419      ;
-; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[7]    ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 9.419      ;
-; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[0]    ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 9.419      ;
-; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[1]    ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 9.419      ;
-; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[2]    ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 9.419      ;
-; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[3]    ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 9.419      ;
-; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[6]    ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 9.419      ;
-; -7.612 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; LEDEN        ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 9.005      ;
-; -7.370 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMInitDone  ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 8.763      ;
-; -7.319 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMReqErase  ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 8.712      ;
-; -6.327 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMD[8]      ; DRCLK        ; C14M        ; 0.001        ; 1.725      ; 7.720      ;
-; 27.280 ; S[1]                                                                                        ; Vout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.307      ;
-; 27.280 ; S[1]                                                                                        ; Vout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.307      ;
-; 27.332 ; S[1]                                                                                        ; Vout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.255      ;
-; 27.332 ; S[1]                                                                                        ; Vout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.255      ;
-; 27.332 ; S[1]                                                                                        ; Vout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.255      ;
-; 27.583 ; S[2]                                                                                        ; Dout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.004      ;
-; 27.583 ; S[2]                                                                                        ; Dout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.004      ;
-; 27.583 ; S[2]                                                                                        ; Dout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.004      ;
-; 27.583 ; S[2]                                                                                        ; Dout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.004      ;
-; 27.583 ; S[2]                                                                                        ; Dout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.004      ;
-; 27.583 ; S[2]                                                                                        ; Dout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.004      ;
-; 27.585 ; S[2]                                                                                        ; Dout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.002      ;
-; 27.590 ; S[2]                                                                                        ; Dout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.997      ;
-; 27.761 ; S[1]                                                                                        ; Dout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.826      ;
-; 27.761 ; S[1]                                                                                        ; Dout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.826      ;
-; 27.761 ; S[1]                                                                                        ; Dout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.826      ;
-; 27.761 ; S[1]                                                                                        ; Dout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.826      ;
-; 27.761 ; S[1]                                                                                        ; Dout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.826      ;
-; 27.761 ; S[1]                                                                                        ; Dout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.826      ;
-; 27.763 ; S[1]                                                                                        ; Dout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.824      ;
-; 27.768 ; S[1]                                                                                        ; Dout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.819      ;
-; 27.779 ; S[0]                                                                                        ; Dout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.808      ;
-; 27.779 ; S[0]                                                                                        ; Dout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.808      ;
-; 27.779 ; S[0]                                                                                        ; Dout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.808      ;
-; 27.779 ; S[0]                                                                                        ; Dout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.808      ;
-; 27.779 ; S[0]                                                                                        ; Dout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.808      ;
-; 27.779 ; S[0]                                                                                        ; Dout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.808      ;
-; 27.781 ; S[0]                                                                                        ; Dout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.806      ;
-; 27.786 ; S[0]                                                                                        ; Dout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.801      ;
-; 27.878 ; S[2]                                                                                        ; Vout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.709      ;
-; 27.878 ; S[2]                                                                                        ; Vout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.709      ;
-; 27.930 ; S[2]                                                                                        ; Vout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.657      ;
-; 27.930 ; S[2]                                                                                        ; Vout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.657      ;
-; 27.930 ; S[2]                                                                                        ; Vout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.657      ;
-; 28.203 ; S[3]                                                                                        ; Dout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.384      ;
-; 28.203 ; S[3]                                                                                        ; Dout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.384      ;
-; 28.203 ; S[3]                                                                                        ; Dout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.384      ;
-; 28.203 ; S[3]                                                                                        ; Dout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.384      ;
-; 28.203 ; S[3]                                                                                        ; Dout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.384      ;
-; 28.203 ; S[3]                                                                                        ; Dout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.384      ;
-; 28.205 ; S[3]                                                                                        ; Dout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.382      ;
-; 28.210 ; S[3]                                                                                        ; Dout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.377      ;
-; 28.368 ; S[1]                                                                                        ; Vout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.219      ;
-; 28.368 ; S[1]                                                                                        ; Vout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.219      ;
-; 28.368 ; S[1]                                                                                        ; Vout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.219      ;
-; 28.431 ; S[3]                                                                                        ; Vout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.156      ;
-; 28.431 ; S[3]                                                                                        ; Vout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.156      ;
-; 28.483 ; S[3]                                                                                        ; Vout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.104      ;
-; 28.483 ; S[3]                                                                                        ; Vout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.104      ;
-; 28.483 ; S[3]                                                                                        ; Vout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.104      ;
-; 28.546 ; S[0]                                                                                        ; Vout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.041      ;
-; 28.546 ; S[0]                                                                                        ; Vout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 6.041      ;
-; 28.598 ; S[0]                                                                                        ; Vout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 5.989      ;
-; 28.598 ; S[0]                                                                                        ; Vout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 5.989      ;
-; 28.598 ; S[0]                                                                                        ; Vout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 5.989      ;
-; 28.966 ; S[2]                                                                                        ; Vout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 5.621      ;
-; 28.966 ; S[2]                                                                                        ; Vout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 5.621      ;
-; 28.966 ; S[2]                                                                                        ; Vout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 5.621      ;
-; 29.519 ; S[3]                                                                                        ; Vout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 5.068      ;
-; 29.519 ; S[3]                                                                                        ; Vout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 5.068      ;
-; 29.519 ; S[3]                                                                                        ; Vout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 5.068      ;
-; 29.634 ; S[0]                                                                                        ; Vout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 4.953      ;
-; 29.634 ; S[0]                                                                                        ; Vout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 4.953      ;
-; 29.634 ; S[0]                                                                                        ; Vout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 4.953      ;
-; 53.482 ; FS[15]                                                                                      ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 16.026     ;
-; 53.855 ; FS[14]                                                                                      ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 15.653     ;
-; 54.606 ; FS[15]                                                                                      ; nCS~reg0     ; C14M         ; C14M        ; 69.841       ; 0.000      ; 14.902     ;
-; 54.773 ; FS[15]                                                                                      ; RA[10]~reg0  ; C14M         ; C14M        ; 69.841       ; 0.000      ; 14.735     ;
-; 54.979 ; FS[14]                                                                                      ; nCS~reg0     ; C14M         ; C14M        ; 69.841       ; 0.000      ; 14.529     ;
-; 55.110 ; FS[15]                                                                                      ; nCAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 14.398     ;
-; 55.146 ; FS[14]                                                                                      ; RA[10]~reg0  ; C14M         ; C14M        ; 69.841       ; 0.000      ; 14.362     ;
-; 55.483 ; FS[14]                                                                                      ; nCAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 14.025     ;
-; 55.674 ; FS[11]                                                                                      ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 13.834     ;
-; 55.804 ; FS[10]                                                                                      ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 13.704     ;
-; 56.000 ; FS[8]                                                                                       ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 13.508     ;
-; 56.341 ; FS[9]                                                                                       ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 13.167     ;
-; 56.591 ; FS[12]                                                                                      ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.917     ;
-; 56.798 ; FS[11]                                                                                      ; nCS~reg0     ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.710     ;
-; 56.928 ; FS[10]                                                                                      ; nCS~reg0     ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.580     ;
-; 56.931 ; FS[13]                                                                                      ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.577     ;
-; 56.965 ; FS[11]                                                                                      ; RA[10]~reg0  ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.543     ;
-; 56.994 ; S[2]                                                                                        ; RWMask[4]    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.514     ;
-; 56.994 ; S[2]                                                                                        ; RWMask[5]    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.514     ;
-; 56.994 ; S[2]                                                                                        ; RWMask[7]    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.514     ;
-; 56.994 ; S[2]                                                                                        ; RWMask[0]    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.514     ;
-; 56.994 ; S[2]                                                                                        ; RWMask[1]    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.514     ;
-; 56.994 ; S[2]                                                                                        ; RWMask[2]    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.514     ;
-; 56.994 ; S[2]                                                                                        ; RWMask[3]    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 12.514     ;
-+--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'C14M'                                                                                                                                                                                                                              ;
++--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                                       ; To Node                         ; Launch Clock           ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
+; -9.644 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6]   ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 10.983     ;
+; -9.644 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4]   ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 10.983     ;
+; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5]   ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 10.496     ;
+; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0]   ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 10.496     ;
+; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1]   ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 10.496     ;
+; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7]   ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 10.496     ;
+; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2]   ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 10.496     ;
+; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3]   ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 10.496     ;
+; -8.710 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 10.049     ;
+; -8.708 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 10.047     ;
+; -8.612 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN       ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 9.951      ;
+; -6.381 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8]     ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 1.671      ; 7.720      ;
+; 31.279 ; RA[8]                                                                                                           ; RAout[8]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 3.308      ;
+; 31.326 ; RA[11]                                                                                                          ; RAout[11]~reg0                  ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 3.261      ;
+; 31.442 ; RA[9]                                                                                                           ; RAout[9]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 3.145      ;
+; 31.464 ; RA[0]                                                                                                           ; RAout[0]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 3.123      ;
+; 31.631 ; RA[10]                                                                                                          ; RAout[10]~reg0                  ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 2.956      ;
+; 31.767 ; CKE                                                                                                             ; CKEout~reg0                     ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 2.820      ;
+; 31.783 ; RA[5]                                                                                                           ; RAout[5]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 2.804      ;
+; 31.887 ; RA[3]                                                                                                           ; RAout[3]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 2.700      ;
+; 32.525 ; nCAS                                                                                                            ; nCASout~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 2.062      ;
+; 32.582 ; nRWE                                                                                                            ; nRWEout~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 2.005      ;
+; 32.583 ; RA[1]                                                                                                           ; RAout[1]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 2.004      ;
+; 32.593 ; nRAS                                                                                                            ; nRASout~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 1.994      ;
+; 32.721 ; RA[4]                                                                                                           ; RAout[4]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 1.866      ;
+; 32.969 ; RA[2]                                                                                                           ; RAout[2]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 1.618      ;
+; 32.978 ; RA[7]                                                                                                           ; RAout[7]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 1.609      ;
+; 32.989 ; RA[6]                                                                                                           ; RAout[6]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 1.598      ;
+; 55.719 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[6]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 13.789     ;
+; 55.719 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[4]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 13.789     ;
+; 56.206 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[5]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 13.302     ;
+; 56.206 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[0]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 13.302     ;
+; 56.206 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[1]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 13.302     ;
+; 56.206 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[7]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 13.302     ;
+; 56.206 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[2]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 13.302     ;
+; 56.206 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[3]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 13.302     ;
+; 56.603 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.905     ;
+; 56.844 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[11]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.664     ;
+; 56.844 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[10]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.664     ;
+; 56.844 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[9]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.664     ;
+; 56.844 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[8]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.664     ;
+; 56.844 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[13]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.664     ;
+; 56.844 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[14]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.664     ;
+; 56.844 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[15]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.664     ;
+; 56.844 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[12]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.664     ;
+; 56.915 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.593     ;
+; 57.079 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[6]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.429     ;
+; 57.079 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[4]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.429     ;
+; 57.323 ; FS[4]                                                                                                           ; RAM2E_UFM:ram2e_ufm|LEDEN       ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.185     ;
+; 57.476 ; S[0]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[6]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.032     ;
+; 57.476 ; S[0]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[4]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 12.032     ;
+; 57.566 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[5]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.942     ;
+; 57.566 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[0]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.942     ;
+; 57.566 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[1]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.942     ;
+; 57.566 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[7]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.942     ;
+; 57.566 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[2]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.942     ;
+; 57.566 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[3]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.942     ;
+; 57.651 ; S[0]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.857     ;
+; 57.772 ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[6]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.736     ;
+; 57.772 ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[4]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.736     ;
+; 57.960 ; FS[4]                                                                                                           ; nCAS                            ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.548     ;
+; 57.963 ; S[0]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[5]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.545     ;
+; 57.963 ; S[0]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[0]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.545     ;
+; 57.963 ; S[0]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[1]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.545     ;
+; 57.963 ; S[0]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[7]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.545     ;
+; 57.963 ; S[0]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[2]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.545     ;
+; 57.963 ; S[0]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[3]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.545     ;
+; 57.963 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.545     ;
+; 57.963 ; S[0]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.545     ;
+; 58.006 ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[11]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.502     ;
+; 58.006 ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[10]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.502     ;
+; 58.006 ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[9]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.502     ;
+; 58.006 ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[8]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.502     ;
+; 58.006 ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[13]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.502     ;
+; 58.006 ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[14]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.502     ;
+; 58.006 ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[15]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.502     ;
+; 58.006 ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[12]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.502     ;
+; 58.030 ; FS[3]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[6]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.478     ;
+; 58.030 ; FS[3]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[4]   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.478     ;
+; 58.039 ; CS[1]                                                                                                           ; CS[0]                           ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.469     ;
+; 58.040 ; CS[1]                                                                                                           ; CS[1]                           ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.468     ;
+; 58.040 ; CS[1]                                                                                                           ; CS[2]                           ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.468     ;
+; 58.068 ; FS[4]                                                                                                           ; nRWE                            ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.440     ;
+; 58.143 ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[11]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.365     ;
+; 58.143 ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[10]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.365     ;
+; 58.143 ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[9]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.365     ;
+; 58.143 ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[8]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.365     ;
+; 58.143 ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[13]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.365     ;
+; 58.143 ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[14]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.365     ;
+; 58.143 ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[15]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.365     ;
+; 58.143 ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[12]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.365     ;
+; 58.204 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[11]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.304     ;
+; 58.204 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[10]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.304     ;
+; 58.204 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[9]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.304     ;
+; 58.204 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[8]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.304     ;
+; 58.204 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[13]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.304     ;
+; 58.204 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[14]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.304     ;
+; 58.204 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[15]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.304     ;
+; 58.204 ; FS[1]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[12]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.304     ;
+; 58.230 ; S[0]                                                                                                            ; S[1]                            ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 11.278     ;
++--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'ARCLK'                                                                                                                                                                                                                                                                                     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.874 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M         ; ARCLK       ; 0.000        ; -1.597     ; 1.529      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'ram2e_ufm|DRCLK|regout'                                                                                                                                                                                                                                                                                                         ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                                       ; To Node                                                                                                         ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; -16.287 ; RAM2E_UFM:ram2e_ufm|DRShift                                                                                     ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M                   ; ram2e_ufm|DRCLK|regout ; 0.000        ; -1.671     ; 2.042      ;
+; -16.261 ; RAM2E_UFM:ram2e_ufm|DRDIn                                                                                       ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M                   ; ram2e_ufm|DRCLK|regout ; 0.000        ; -1.671     ; 2.068      ;
+; 60.000  ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000        ; 0.000      ; 80.000     ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'DRCLK'                                                                                                                                                                                                                                                             ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.746 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M         ; DRCLK       ; 0.000        ; -1.725     ; 1.529      ;
-; -16.734 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M         ; DRCLK       ; 0.000        ; -1.725     ; 1.541      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'ram2e_ufm|ARCLK|regout'                                                                                                                                                                                                                                                                                                                                 ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                                                   ; To Node                                                                                                                     ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; -16.279 ; RAM2E_UFM:ram2e_ufm|ARShift                                                                                                 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M                   ; ram2e_ufm|ARCLK|regout ; 0.000        ; -1.663     ; 2.058      ;
+; 60.000  ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000        ; 0.000      ; 80.000     ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
 
 
-+---------------------------------------------------------------------------------------------------------------+
-; Hold: 'C14M'                                                                                                  ;
-+-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node         ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+
-; 1.415 ; UFMD[12]          ; UFMD[13]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.636      ;
-; 1.421 ; UFMD[11]          ; UFMD[12]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.642      ;
-; 1.639 ; DRDIn             ; DRDIn       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.860      ;
-; 1.639 ; FS[0]             ; FS[0]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.860      ;
-; 1.660 ; CmdTout[2]        ; CmdTout[2]  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.881      ;
-; 1.669 ; UFMD[10]          ; UFMD[11]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.890      ;
-; 1.701 ; S[3]              ; S[3]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.922      ;
-; 1.701 ; CS[2]             ; CS[2]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.922      ;
-; 1.730 ; S[0]              ; S[0]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.951      ;
-; 1.732 ; S[0]              ; S[1]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.953      ;
-; 1.822 ; UFMD[8]           ; UFMD[9]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.043      ;
-; 1.844 ; UFMD[9]           ; UFMD[10]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.065      ;
-; 1.953 ; UFMInitDone       ; UFMInitDone ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.174      ;
-; 1.981 ; CmdTout[1]        ; CmdTout[2]  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.202      ;
-; 1.991 ; CmdTout[0]        ; CmdTout[1]  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.212      ;
-; 2.107 ; LEDEN             ; LEDEN       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.328      ;
-; 2.107 ; FS[7]             ; FS[7]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.328      ;
-; 2.107 ; CmdBitbangMAX     ; DRCLKPulse  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.328      ;
-; 2.118 ; Ready             ; Ready       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.339      ;
-; 2.126 ; FS[15]            ; FS[15]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.347      ;
-; 2.126 ; FS[5]             ; FS[5]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.347      ;
-; 2.134 ; FS[8]             ; FS[8]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.355      ;
-; 2.138 ; CmdPrgmMAX        ; CmdPrgmMAX  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.359      ;
-; 2.143 ; CmdPrgmMAX        ; UFMProgram  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.364      ;
-; 2.144 ; UFMErase          ; UFMErase    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.365      ;
-; 2.146 ; UFMProgram        ; UFMProgram  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.367      ;
-; 2.152 ; FS[9]             ; FS[9]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.373      ;
-; 2.152 ; FS[10]            ; FS[10]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.373      ;
-; 2.162 ; S[2]              ; S[2]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.383      ;
-; 2.165 ; CmdEraseMAX       ; CmdEraseMAX ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.386      ;
-; 2.199 ; CS[0]             ; CS[0]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.420      ;
-; 2.207 ; CS[0]             ; CS[2]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.428      ;
-; 2.218 ; CS[0]             ; CS[1]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.439      ;
-; 2.233 ; FS[11]            ; FS[11]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.454      ;
-; 2.247 ; FS[6]             ; FS[6]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.468      ;
-; 2.249 ; FS[14]            ; FS[14]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.470      ;
-; 2.260 ; FS[13]            ; FS[13]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.481      ;
-; 2.262 ; FS[12]            ; FS[12]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.483      ;
-; 2.268 ; FS[4]             ; FS[4]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.489      ;
-; 2.273 ; FS[1]             ; FS[1]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.494      ;
-; 2.290 ; FS[3]             ; FS[3]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.511      ;
-; 2.291 ; CmdTout[1]        ; CmdTout[1]  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.512      ;
-; 2.295 ; FS[2]             ; FS[2]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.516      ;
-; 2.308 ; CmdTout[0]        ; CmdTout[0]  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.529      ;
-; 2.309 ; CmdTout[0]        ; CmdTout[2]  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.530      ;
-; 2.382 ; UFMReqErase       ; UFMReqErase ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.603      ;
-; 2.390 ; S[1]              ; S[1]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.611      ;
-; 2.448 ; UFMD[14]          ; UFMD[15]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.669      ;
-; 2.455 ; CS[1]             ; CS[1]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.676      ;
-; 2.461 ; CS[1]             ; CS[2]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.682      ;
-; 2.622 ; RTPBusyReg        ; UFMProgram  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.843      ;
-; 2.624 ; UFMBusyReg        ; UFMErase    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.845      ;
-; 2.626 ; RWBank[3]         ; RA[11]~reg0 ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.847      ;
-; 2.645 ; UFMD[13]          ; UFMD[14]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.866      ;
-; 2.655 ; PHI1reg           ; S[0]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.876      ;
-; 2.720 ; RWSel             ; RWSel       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.941      ;
-; 2.732 ; UFMD[15]          ; RWMask[7]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.953      ;
-; 2.766 ; RWSel             ; CmdTout[1]  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.987      ;
-; 2.823 ; RWMask[3]         ; RWBank[3]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.044      ;
-; 2.844 ; UFMD[9]           ; RWMask[1]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.065      ;
-; 2.851 ; RWBank[5]         ; BA[1]~reg0  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.072      ;
-; 2.911 ; S[3]              ; nCS~reg0    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.132      ;
-; 2.913 ; S[3]              ; BA[0]~reg0  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.134      ;
-; 2.952 ; RTPBusyReg        ; UFMErase    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.173      ;
-; 2.958 ; FS[5]             ; FS[6]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.179      ;
-; 2.966 ; FS[8]             ; FS[9]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.187      ;
-; 2.984 ; FS[9]             ; FS[10]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.205      ;
-; 2.984 ; FS[10]            ; FS[11]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.205      ;
-; 2.992 ; RWMask[2]         ; RWBank[2]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.213      ;
-; 3.041 ; RWBank[0]         ; RA[8]~reg0  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.262      ;
-; 3.063 ; RWMask[0]         ; RWBank[0]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.284      ;
-; 3.069 ; FS[5]             ; FS[7]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.290      ;
-; 3.077 ; FS[8]             ; FS[10]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.298      ;
-; 3.095 ; FS[10]            ; FS[12]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.316      ;
-; 3.095 ; FS[9]             ; FS[11]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.316      ;
-; 3.096 ; RWSel             ; DRCLKPulse  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.317      ;
-; 3.098 ; RWSel             ; CmdTout[0]  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.319      ;
-; 3.118 ; S[0]              ; DOEEN       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.339      ;
-; 3.134 ; RWBank[1]         ; RA[9]~reg0  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.355      ;
-; 3.163 ; UFMD[11]          ; RWMask[3]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.384      ;
-; 3.168 ; DRCLKPulse        ; DRCLK       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.389      ;
-; 3.170 ; RWBank[7]         ; RA[8]~reg0  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.391      ;
-; 3.173 ; FS[11]            ; FS[12]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.394      ;
-; 3.187 ; FS[6]             ; FS[7]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.408      ;
-; 3.188 ; FS[8]             ; FS[11]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.409      ;
-; 3.189 ; FS[14]            ; FS[15]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.410      ;
-; 3.189 ; RWMask[4]         ; RWBank[4]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.410      ;
-; 3.200 ; FS[13]            ; FS[14]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.421      ;
-; 3.203 ; RWMask[1]         ; RWBank[1]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.424      ;
-; 3.206 ; FS[9]             ; FS[12]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.427      ;
-; 3.208 ; FS[4]             ; FS[5]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.429      ;
-; 3.213 ; FS[1]             ; FS[2]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.434      ;
-; 3.218 ; CmdSetRWBankFFLED ; RWBank[4]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.439      ;
-; 3.222 ; CmdSetRWBankFFLED ; RWBank[3]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.443      ;
-; 3.230 ; FS[3]             ; FS[4]       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.451      ;
-; 3.230 ; RWSel             ; CmdTout[2]  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.451      ;
-; 3.236 ; S[0]              ; nCS~reg0    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.457      ;
-; 3.241 ; UFMD[12]          ; RWMask[4]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.462      ;
-; 3.274 ; UFMD[14]          ; RWMask[6]   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.495      ;
-; 3.299 ; FS[8]             ; FS[12]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.520      ;
-+-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'C14M'                                                                                                                                      ;
++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                        ; To Node                          ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.421 ; RAM2E_UFM:ram2e_ufm|UFMD[8]      ; RAM2E_UFM:ram2e_ufm|UFMD[9]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.642      ;
+; 1.421 ; RAM2E_UFM:ram2e_ufm|UFMD[12]     ; RAM2E_UFM:ram2e_ufm|UFMD[13]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.642      ;
+; 1.445 ; RAM2E_UFM:ram2e_ufm|UFMD[10]     ; RAM2E_UFM:ram2e_ufm|UFMD[11]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.666      ;
+; 1.451 ; RAM2E_UFM:ram2e_ufm|UFMD[11]     ; RAM2E_UFM:ram2e_ufm|UFMD[12]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.672      ;
+; 1.461 ; RAM2E_UFM:ram2e_ufm|UFMD[14]     ; RAM2E_UFM:ram2e_ufm|UFMD[15]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.682      ;
+; 1.639 ; RWSel                            ; RWSel                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.860      ;
+; 1.684 ; FS[0]                            ; FS[0]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.905      ;
+; 1.687 ; CS[1]                            ; CS[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.908      ;
+; 1.688 ; CS[1]                            ; CS[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.909      ;
+; 1.696 ; CmdTout[0]                       ; CmdTout[0]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.917      ;
+; 1.702 ; CmdTout[0]                       ; CmdTout[1]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.923      ;
+; 1.706 ; CmdTout[0]                       ; CmdTout[2]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.927      ;
+; 1.716 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M         ; C14M        ; 0.000        ; 0.000      ; 1.937      ;
+; 1.818 ; RAM2E_UFM:ram2e_ufm|UFMD[9]      ; RAM2E_UFM:ram2e_ufm|UFMD[10]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.039      ;
+; 1.905 ; RAM2E_UFM:ram2e_ufm|RWMask[4]    ; RWBank[4]                        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.126      ;
+; 1.928 ; RWBank[1]                        ; RA[8]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.149      ;
+; 1.935 ; CS[2]                            ; CS[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.156      ;
+; 1.954 ; RC[0]                            ; RC[0]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.175      ;
+; 1.961 ; RC[0]                            ; RC[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.182      ;
+; 1.968 ; RC[0]                            ; RC[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.189      ;
+; 1.971 ; S[3]                             ; S[3]                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.192      ;
+; 1.972 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX  ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.193      ;
+; 1.984 ; CS[0]                            ; CS[0]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.205      ;
+; 1.993 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX  ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.214      ;
+; 1.995 ; CS[0]                            ; CS[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.216      ;
+; 2.107 ; RAM2E_UFM:ram2e_ufm|LEDEN        ; RAM2E_UFM:ram2e_ufm|LEDEN        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.328      ;
+; 2.109 ; RAM2E_UFM:ram2e_ufm|RWMask[6]    ; RWBank[6]                        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.330      ;
+; 2.116 ; FS[8]                            ; FS[8]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.337      ;
+; 2.117 ; FS[15]                           ; FS[15]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; FS[5]                            ; FS[5]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.125 ; FS[9]                            ; FS[9]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.346      ;
+; 2.126 ; RAM2E_UFM:ram2e_ufm|DRDIn        ; RAM2E_UFM:ram2e_ufm|DRDIn        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.347      ;
+; 2.126 ; FS[7]                            ; FS[7]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.347      ;
+; 2.128 ; RWBank[7]                        ; RA[8]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.349      ;
+; 2.133 ; RAM2E_UFM:ram2e_ufm|UFMD[13]     ; RAM2E_UFM:ram2e_ufm|UFMD[14]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.354      ;
+; 2.136 ; RAM2E_UFM:ram2e_ufm|UFMInitDone  ; RAM2E_UFM:ram2e_ufm|UFMInitDone  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.357      ;
+; 2.143 ; CmdTout[2]                       ; CmdTout[2]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.364      ;
+; 2.150 ; Ready                            ; Ready                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.371      ;
+; 2.163 ; RC[1]                            ; RC[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.384      ;
+; 2.181 ; RC[1]                            ; RC[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.402      ;
+; 2.182 ; S[1]                             ; S[1]                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.403      ;
+; 2.184 ; RC[1]                            ; RC[0]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.405      ;
+; 2.212 ; RA[10]                           ; RA[10]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.433      ;
+; 2.230 ; FS[6]                            ; FS[6]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.451      ;
+; 2.232 ; FS[11]                           ; FS[11]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.453      ;
+; 2.239 ; FS[13]                           ; FS[13]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.460      ;
+; 2.239 ; FS[14]                           ; FS[14]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.460      ;
+; 2.241 ; FS[1]                            ; FS[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.462      ;
+; 2.249 ; FS[2]                            ; FS[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.470      ;
+; 2.250 ; FS[12]                           ; FS[12]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.471      ;
+; 2.259 ; FS[3]                            ; FS[3]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.480      ;
+; 2.261 ; FS[4]                            ; FS[4]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.482      ;
+; 2.272 ; RAM2E_UFM:ram2e_ufm|UFMProgram   ; RAM2E_UFM:ram2e_ufm|UFMProgram   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.493      ;
+; 2.277 ; RC[2]                            ; RC[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.498      ;
+; 2.279 ; RC[2]                            ; RC[0]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.500      ;
+; 2.282 ; RC[2]                            ; RC[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.503      ;
+; 2.302 ; CmdTout[1]                       ; CmdTout[1]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.523      ;
+; 2.305 ; S[3]                             ; RA[11]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.526      ;
+; 2.310 ; CmdTout[1]                       ; CmdTout[2]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.531      ;
+; 2.313 ; RAM2E_UFM:ram2e_ufm|RWMask[2]    ; RWBank[2]                        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.534      ;
+; 2.316 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.537      ;
+; 2.319 ; CS[0]                            ; CS[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.540      ;
+; 2.323 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.544      ;
+; 2.332 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.553      ;
+; 2.347 ; PHI1r                            ; S[0]                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.568      ;
+; 2.372 ; RAM2E_UFM:ram2e_ufm|UFMReqErase  ; RAM2E_UFM:ram2e_ufm|UFMReqErase  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.593      ;
+; 2.446 ; RWSel                            ; CmdTout[0]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.667      ;
+; 2.455 ; RWSel                            ; CmdTout[1]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.676      ;
+; 2.457 ; S[3]                             ; CKE                              ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.678      ;
+; 2.459 ; RWSel                            ; CmdTout[2]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.680      ;
+; 2.531 ; RAM2E_UFM:ram2e_ufm|UFMD[10]     ; RAM2E_UFM:ram2e_ufm|RWMask[2]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.752      ;
+; 2.542 ; S[2]                             ; S[2]                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.763      ;
+; 2.544 ; S[2]                             ; DOEEN                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.765      ;
+; 2.563 ; RAM2E_UFM:ram2e_ufm|UFMD[15]     ; RAM2E_UFM:ram2e_ufm|RWMask[7]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.784      ;
+; 2.606 ; RAM2E_UFM:ram2e_ufm|UFMErase     ; RAM2E_UFM:ram2e_ufm|UFMProgram   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.827      ;
+; 2.610 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; RAM2E_UFM:ram2e_ufm|UFMErase     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.831      ;
+; 2.653 ; RAM2E_UFM:ram2e_ufm|UFMD[9]      ; RAM2E_UFM:ram2e_ufm|RWMask[1]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.874      ;
+; 2.655 ; S[0]                             ; S[0]                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.876      ;
+; 2.656 ; FS[10]                           ; FS[10]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.877      ;
+; 2.657 ; S[0]                             ; VOEEN                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.878      ;
+; 2.660 ; RAM2E_UFM:ram2e_ufm|UFMD[13]     ; RAM2E_UFM:ram2e_ufm|RWMask[5]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.881      ;
+; 2.678 ; S[1]                             ; DOEEN                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.899      ;
+; 2.719 ; RAM2E_UFM:ram2e_ufm|UFMD[11]     ; RAM2E_UFM:ram2e_ufm|RWMask[3]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.940      ;
+; 2.750 ; S[0]                             ; RA[10]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.971      ;
+; 2.764 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX  ; RAM2E_UFM:ram2e_ufm|UFMErase     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.985      ;
+; 2.773 ; S[1]                             ; S[3]                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.994      ;
+; 2.785 ; RAM2E_UFM:ram2e_ufm|RWMask[3]    ; RWBank[3]                        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.006      ;
+; 2.794 ; S[0]                             ; RA[8]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.015      ;
+; 2.815 ; FS[4]                            ; RA[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.036      ;
+; 2.830 ; S[3]                             ; RA[9]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.051      ;
+; 2.850 ; FS[1]                            ; RA[0]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.071      ;
+; 2.851 ; RWBank[5]                        ; BA[0]~reg0                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.072      ;
+; 2.902 ; S[2]                             ; nRWE                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.123      ;
+; 2.911 ; S[2]                             ; nCAS                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.132      ;
+; 2.929 ; RAM2E_UFM:ram2e_ufm|RWMask[0]    ; RWBank[0]                        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.150      ;
+; 2.933 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMErase     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.154      ;
+; 2.935 ; RAM2E_UFM:ram2e_ufm|RWMask[5]    ; RWBank[5]                        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.156      ;
+; 2.948 ; FS[8]                            ; FS[9]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.169      ;
+; 2.949 ; FS[5]                            ; FS[6]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.170      ;
+; 2.957 ; FS[9]                            ; FS[10]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.178      ;
++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
 
 
-+-------------------------------------------------------------------+
-; Setup Transfers                                                   ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; C14M       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; C14M       ; C14M     ; 1607     ; 0        ; 64       ; 0        ;
-; DRCLK      ; C14M     ; 13       ; 0        ; 0        ; 0        ;
-; C14M       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
++---------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                             ;
++------------------------+------------------------+----------+----------+----------+----------+
+; From Clock             ; To Clock               ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------------------+------------------------+----------+----------+----------+----------+
+; C14M                   ; C14M                   ; 1625     ; 0        ; 16       ; 0        ;
+; ram2e_ufm|DRCLK|regout ; C14M                   ; 13       ; 0        ; 0        ; 0        ;
+; C14M                   ; ram2e_ufm|ARCLK|regout ; 1        ; 0        ; 0        ; 0        ;
+; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1        ; 0        ; 0        ; 0        ;
+; C14M                   ; ram2e_ufm|DRCLK|regout ; 2        ; 0        ; 0        ; 0        ;
+; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1        ; 0        ; 0        ; 0        ;
++------------------------+------------------------+----------+----------+----------+----------+
 Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
 
 
-+-------------------------------------------------------------------+
-; Hold Transfers                                                    ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; C14M       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; C14M       ; C14M     ; 1607     ; 0        ; 64       ; 0        ;
-; DRCLK      ; C14M     ; 13       ; 0        ; 0        ; 0        ;
-; C14M       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
++---------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                              ;
++------------------------+------------------------+----------+----------+----------+----------+
+; From Clock             ; To Clock               ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------------------+------------------------+----------+----------+----------+----------+
+; C14M                   ; C14M                   ; 1625     ; 0        ; 16       ; 0        ;
+; ram2e_ufm|DRCLK|regout ; C14M                   ; 13       ; 0        ; 0        ; 0        ;
+; C14M                   ; ram2e_ufm|ARCLK|regout ; 1        ; 0        ; 0        ; 0        ;
+; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1        ; 0        ; 0        ; 0        ;
+; C14M                   ; ram2e_ufm|DRCLK|regout ; 2        ; 0        ; 0        ; 0        ;
+; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1        ; 0        ; 0        ; 0        ;
++------------------------+------------------------+----------+----------+----------+----------+
 Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
 
 
@@ -473,22 +472,22 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +---------------------------------+-------+------+
 ; Illegal Clocks                  ; 0     ; 0    ;
 ; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 29    ; 29   ;
-; Unconstrained Input Port Paths  ; 169   ; 169  ;
-; Unconstrained Output Ports      ; 48    ; 48   ;
-; Unconstrained Output Port Paths ; 67    ; 67   ;
+; Unconstrained Input Ports       ; 28    ; 28   ;
+; Unconstrained Input Port Paths  ; 176   ; 176  ;
+; Unconstrained Output Ports      ; 47    ; 47   ;
+; Unconstrained Output Port Paths ; 76    ; 76   ;
 +---------------------------------+-------+------+
 
 
-+-------------------------------------+
-; Clock Status Summary                ;
-+--------+-------+------+-------------+
-; Target ; Clock ; Type ; Status      ;
-+--------+-------+------+-------------+
-; ARCLK  ; ARCLK ; Base ; Constrained ;
-; C14M   ; C14M  ; Base ; Constrained ;
-; DRCLK  ; DRCLK ; Base ; Constrained ;
-+--------+-------+------+-------------+
++----------------------------------------------------------------------+
+; Clock Status Summary                                                 ;
++------------------------+------------------------+------+-------------+
+; Target                 ; Clock                  ; Type ; Status      ;
++------------------------+------------------------+------+-------------+
+; C14M                   ; C14M                   ; Base ; Constrained ;
+; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; Base ; Constrained ;
+; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; Base ; Constrained ;
++------------------------+------------------------+------+-------------+
 
 
 +---------------------------------------------------------------------------------------------------+
@@ -524,7 +523,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; nC07X      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nEN80      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nWE        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nWE80      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +------------+--------------------------------------------------------------------------------------+
 
 
@@ -535,7 +533,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +-------------+---------------------------------------------------------------------------------------+
 ; BA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; BA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; CKE         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; CKEout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; DQMH        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; DQML        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -547,18 +545,18 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[0]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[1]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[2]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[3]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[4]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[5]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[6]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[7]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[8]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[9]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[10]   ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[11]   ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -575,11 +573,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; Vout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Vout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Vout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCS         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCASout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nDOE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRASout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRWEout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nVOE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +-------------+---------------------------------------------------------------------------------------+
 
@@ -617,7 +614,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; nC07X      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nEN80      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nWE        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nWE80      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +------------+--------------------------------------------------------------------------------------+
 
 
@@ -628,7 +624,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +-------------+---------------------------------------------------------------------------------------+
 ; BA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; BA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; CKE         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; CKEout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; DQMH        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; DQML        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -640,18 +636,18 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[0]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[1]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[2]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[3]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[4]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[5]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[6]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[7]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[8]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[9]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[10]   ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[11]   ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -668,11 +664,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; Vout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Vout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Vout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCS         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCASout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nDOE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRASout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRWEout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nVOE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +-------------+---------------------------------------------------------------------------------------+
 
@@ -682,8 +677,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +--------------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Thu Sep 21 05:34:43 2023
+    Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
+    Info: Processing started: Thu Dec 28 23:09:48 2023
 Info: Command: quartus_sta RAM2E-MAXII -c RAM2E
 Info: qsta_default_script.tcl version: #1
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
@@ -695,37 +690,37 @@ Info (332104): Reading SDC File: '../RAM2E.sdc'
 Info (332104): Reading SDC File: '../RAM2E-MAX.sdc'
 Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
 Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
-Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
-Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
+Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
+Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
 Critical Warning (332148): Timing requirements not met
-Info (332146): Worst-case setup slack is -23.265
+Info (332146): Worst-case setup slack is -23.738
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):   -23.265             -23.265 DRCLK 
-    Info (332119):   -23.125             -23.125 ARCLK 
-    Info (332119):    -8.026             -92.836 C14M 
-Info (332146): Worst-case hold slack is -16.874
+    Info (332119):   -23.738             -23.738 ram2e_ufm|DRCLK|regout 
+    Info (332119):   -23.720             -23.720 ram2e_ufm|ARCLK|regout 
+    Info (332119):    -9.644            -106.641 C14M 
+Info (332146): Worst-case hold slack is -16.287
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):   -16.874             -16.874 ARCLK 
-    Info (332119):   -16.746             -16.746 DRCLK 
-    Info (332119):     1.415               0.000 C14M 
+    Info (332119):   -16.287             -16.287 ram2e_ufm|DRCLK|regout 
+    Info (332119):   -16.279             -16.279 ram2e_ufm|ARCLK|regout 
+    Info (332119):     1.421               0.000 C14M 
 Info (332140): No Recovery paths to report
 Info (332140): No Removal paths to report
 Info (332146): Worst-case minimum pulse width slack is 34.654
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
     Info (332119):    34.654               0.000 C14M 
-    Info (332119):    70.000               0.000 ARCLK 
-    Info (332119):    70.000               0.000 DRCLK 
+    Info (332119):    70.000               0.000 ram2e_ufm|ARCLK|regout 
+    Info (332119):    70.000               0.000 ram2e_ufm|DRCLK|regout 
 Info (332001): The selected device family is not supported by the report_metastability command.
-Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
-Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
+Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
+Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 13089 megabytes
-    Info: Processing ended: Thu Sep 21 05:34:45 2023
+    Info: Peak virtual memory: 13064 megabytes
+    Info: Processing ended: Thu Dec 28 23:09:50 2023
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02
 
diff --git a/CPLD/MAXII/output_files/RAM2E.sta.summary b/CPLD/MAXII/output_files/RAM2E.sta.summary
index 8103b71..9e7e945 100644
--- a/CPLD/MAXII/output_files/RAM2E.sta.summary
+++ b/CPLD/MAXII/output_files/RAM2E.sta.summary
@@ -2,39 +2,39 @@
 Timing Analyzer Summary
 ------------------------------------------------------------
 
-Type  : Setup 'DRCLK'
-Slack : -23.265
-TNS   : -23.265
+Type  : Setup 'ram2e_ufm|DRCLK|regout'
+Slack : -23.738
+TNS   : -23.738
 
-Type  : Setup 'ARCLK'
-Slack : -23.125
-TNS   : -23.125
+Type  : Setup 'ram2e_ufm|ARCLK|regout'
+Slack : -23.720
+TNS   : -23.720
 
 Type  : Setup 'C14M'
-Slack : -8.026
-TNS   : -92.836
+Slack : -9.644
+TNS   : -106.641
 
-Type  : Hold 'ARCLK'
-Slack : -16.874
-TNS   : -16.874
+Type  : Hold 'ram2e_ufm|DRCLK|regout'
+Slack : -16.287
+TNS   : -16.287
 
-Type  : Hold 'DRCLK'
-Slack : -16.746
-TNS   : -16.746
+Type  : Hold 'ram2e_ufm|ARCLK|regout'
+Slack : -16.279
+TNS   : -16.279
 
 Type  : Hold 'C14M'
-Slack : 1.415
+Slack : 1.421
 TNS   : 0.000
 
 Type  : Minimum Pulse Width 'C14M'
 Slack : 34.654
 TNS   : 0.000
 
-Type  : Minimum Pulse Width 'ARCLK'
+Type  : Minimum Pulse Width 'ram2e_ufm|ARCLK|regout'
 Slack : 70.000
 TNS   : 0.000
 
-Type  : Minimum Pulse Width 'DRCLK'
+Type  : Minimum Pulse Width 'ram2e_ufm|DRCLK|regout'
 Slack : 70.000
 TNS   : 0.000
 
diff --git a/CPLD/MAXV/RAM2E.qsf b/CPLD/MAXV/RAM2E.qsf
index d4f161d..19727c5 100644
--- a/CPLD/MAXV/RAM2E.qsf
+++ b/CPLD/MAXV/RAM2E.qsf
@@ -42,7 +42,7 @@ set_global_assignment -name DEVICE 5M240ZT100C5
 set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:27:32  AUGUST 20, 2023"
-set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -74,7 +74,6 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80
 
 set_location_assignment PIN_33 -to nWE80
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80
 
 set_location_assignment PIN_52 -to nC07X
@@ -123,7 +122,6 @@ set_location_assignment PIN_85 -to Dout[7]
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout
 set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
 
 set_location_assignment PIN_50 -to nVOE
@@ -146,40 +144,39 @@ set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout
 
-set_location_assignment PIN_4 -to CKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE
-set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE
+set_location_assignment PIN_4 -to CKEout
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKEout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKEout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to CKEout
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKEout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKEout
 
-set_location_assignment PIN_8 -to nCS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS
+set_location_assignment PIN_8 -to nCSout
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCSout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCSout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nCSout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCSout
 
-set_location_assignment PIN_2 -to nRWE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE
+set_location_assignment PIN_2 -to nRWEout
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWEout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWEout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWEout
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWEout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWEout
 
-set_location_assignment PIN_5 -to nRAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
+set_location_assignment PIN_5 -to nRASout
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRASout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRASout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRASout
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRASout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRASout
 
-set_location_assignment PIN_3 -to nCAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
+set_location_assignment PIN_3 -to nCASout
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCASout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCASout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nCASout
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCASout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCASout
 
 set_location_assignment PIN_6 -to BA[0]
 set_location_assignment PIN_14 -to BA[1]
@@ -189,23 +186,23 @@ set_instance_assignment -name SLOW_SLEW_RATE ON -to BA
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA
 
-set_location_assignment PIN_18 -to RA[0]
-set_location_assignment PIN_20 -to RA[1]
-set_location_assignment PIN_30 -to RA[2]
-set_location_assignment PIN_27 -to RA[3]
-set_location_assignment PIN_26 -to RA[4]
-set_location_assignment PIN_29 -to RA[5]
-set_location_assignment PIN_21 -to RA[6]
-set_location_assignment PIN_19 -to RA[7]
-set_location_assignment PIN_17 -to RA[8]
-set_location_assignment PIN_15 -to RA[9]
-set_location_assignment PIN_16 -to RA[10]
-set_location_assignment PIN_7 -to RA[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA
-set_instance_assignment -name SLOW_SLEW_RATE ON -to RA
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
+set_location_assignment PIN_18 -to RAout[0]
+set_location_assignment PIN_20 -to RAout[1]
+set_location_assignment PIN_30 -to RAout[2]
+set_location_assignment PIN_27 -to RAout[3]
+set_location_assignment PIN_26 -to RAout[4]
+set_location_assignment PIN_29 -to RAout[5]
+set_location_assignment PIN_21 -to RAout[6]
+set_location_assignment PIN_19 -to RAout[7]
+set_location_assignment PIN_17 -to RAout[8]
+set_location_assignment PIN_15 -to RAout[9]
+set_location_assignment PIN_16 -to RAout[10]
+set_location_assignment PIN_7 -to RAout[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RAout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RAout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RAout
 
 set_location_assignment PIN_100 -to DQMH
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH
@@ -237,11 +234,12 @@ set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
 
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name VERILOG_FILE "../RAM2E-MAX.v"
+set_location_assignment PIN_88 -to LED
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
+set_global_assignment -name VERILOG_FILE ../RAM2E.v
+set_global_assignment -name VERILOG_FILE "../UFM-MAX.v"
 set_global_assignment -name QIP_FILE UFM.qip
 set_global_assignment -name MIF_FILE ../RAM2E.mif
 set_global_assignment -name SDC_FILE ../RAM2E.sdc
-set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc"
-set_location_assignment PIN_88 -to LED
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
-set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
\ No newline at end of file
+set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc"
\ No newline at end of file
diff --git a/CPLD/MAXV/RAM2E.qws b/CPLD/MAXV/RAM2E.qws
index 8de3d3ecec64b3ff743c66893051e3ad1a1fae78..f6f69ce180188e29d6210913345135901ddd90b8 100644
GIT binary patch
delta 67
zcmaFO@|tDBTsDRi3=B-%6Bk<xax*Y6BryE{|DS<@kqIQY@qGfL4C7fKlM5&X20+<=
KAPnL#F#rIIFcZ!I

delta 67
zcmaFO@|tDBTsB4q1_maciHofTd4Q}0hX4QnGcYht0|{<?pTH=?G!w|=21<beQ1%}P
IgE&kK0B(*GYybcN

diff --git a/CPLD/MAXV/output_files/RAM2E.asm.rpt b/CPLD/MAXV/output_files/RAM2E.asm.rpt
index 2fca0e6..ecac003 100644
--- a/CPLD/MAXV/output_files/RAM2E.asm.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.asm.rpt
@@ -1,6 +1,6 @@
 Assembler report for RAM2E
-Thu Sep 21 05:34:42 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Thu Dec 28 23:09:48 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
 ---------------------
@@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
   2. Assembler Summary
   3. Assembler Settings
   4. Assembler Generated Files
-  5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof
+  5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof
   6. Assembler Messages
 
 
@@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Sep 21 05:34:42 2023 ;
+; Assembler Status      ; Successful - Thu Dec 28 23:09:48 2023 ;
 ; Revision Name         ; RAM2E                                 ;
 ; Top-level Entity Name ; RAM2E                                 ;
 ; Family                ; MAX V                                 ;
@@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
 +--------+---------+---------------+
 
 
-+-----------------------------------------------+
-; Assembler Generated Files                     ;
-+-----------------------------------------------+
-; File Name                                     ;
-+-----------------------------------------------+
-; /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
-+-----------------------------------------------+
++-------------------------------------------------+
+; Assembler Generated Files                       ;
++-------------------------------------------------+
+; File Name                                       ;
++-------------------------------------------------+
+; Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
++-------------------------------------------------+
 
 
-+-------------------------------------------------------------------------+
-; Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
-+----------------+--------------------------------------------------------+
-; Option         ; Setting                                                ;
-+----------------+--------------------------------------------------------+
-; JTAG usercode  ; 0x0016B5DB                                             ;
-; Checksum       ; 0x0016B84B                                             ;
-+----------------+--------------------------------------------------------+
++---------------------------------------------------------------------------+
+; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
++----------------+----------------------------------------------------------+
+; Option         ; Setting                                                  ;
++----------------+----------------------------------------------------------+
+; JTAG usercode  ; 0x001658EB                                               ;
+; Checksum       ; 0x00165BE3                                               ;
++----------------+----------------------------------------------------------+
 
 
 +--------------------+
@@ -77,14 +77,14 @@ https://fpgasoftware.intel.com/eula.
 +--------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Thu Sep 21 05:34:41 2023
+    Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
+    Info: Processing started: Thu Dec 28 23:09:47 2023
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 13092 megabytes
-    Info: Processing ended: Thu Sep 21 05:34:42 2023
+    Info: Peak virtual memory: 13070 megabytes
+    Info: Processing ended: Thu Dec 28 23:09:48 2023
     Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:01
 
diff --git a/CPLD/MAXV/output_files/RAM2E.done b/CPLD/MAXV/output_files/RAM2E.done
index af92b7d..aacbb63 100644
--- a/CPLD/MAXV/output_files/RAM2E.done
+++ b/CPLD/MAXV/output_files/RAM2E.done
@@ -1 +1 @@
-Thu Sep 21 05:34:47 2023
+Thu Dec 28 23:09:52 2023
diff --git a/CPLD/MAXV/output_files/RAM2E.fit.rpt b/CPLD/MAXV/output_files/RAM2E.fit.rpt
index 2b2fd74..4ec5759 100644
--- a/CPLD/MAXV/output_files/RAM2E.fit.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.fit.rpt
@@ -1,6 +1,6 @@
 Fitter report for RAM2E
-Thu Sep 21 05:34:38 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Thu Dec 28 23:09:45 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
 ---------------------
@@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula.
 
 
 
-+---------------------------------------------------------------------+
-; Fitter Summary                                                      ;
-+-----------------------+---------------------------------------------+
-; Fitter Status         ; Successful - Thu Sep 21 05:34:38 2023       ;
-; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name         ; RAM2E                                       ;
-; Top-level Entity Name ; RAM2E                                       ;
-; Family                ; MAX V                                       ;
-; Device                ; 5M240ZT100C5                                ;
-; Timing Models         ; Final                                       ;
-; Total logic elements  ; 197 / 240 ( 82 % )                          ;
-; Total pins            ; 70 / 79 ( 89 % )                            ;
-; Total virtual pins    ; 0                                           ;
-; UFM blocks            ; 1 / 1 ( 100 % )                             ;
-+-----------------------+---------------------------------------------+
++-------------------------------------------------------------------------------------+
+; Fitter Summary                                                                      ;
++-----------------------+-------------------------------------------------------------+
+; Fitter Status         ; Successful - Thu Dec 28 23:09:45 2023                       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
+; Revision Name         ; RAM2E                                                       ;
+; Top-level Entity Name ; RAM2E                                                       ;
+; Family                ; MAX V                                                       ;
+; Device                ; 5M240ZT100C5                                                ;
+; Timing Models         ; Final                                                       ;
+; Total logic elements  ; 238 / 240 ( 99 % )                                          ;
+; Total pins            ; 70 / 79 ( 89 % )                                            ;
+; Total virtual pins    ; 0                                                           ;
+; UFM blocks            ; 1 / 1 ( 100 % )                                             ;
++-----------------------+-------------------------------------------------------------+
 
 
 +--------------------------------------------------------------------------------------------------------------------------------------+
@@ -134,15 +134,15 @@ https://fpgasoftware.intel.com/eula.
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.2%      ;
-;     Processors 3-4         ;   1.1%      ;
+;     Processor 2            ;   1.0%      ;
+;     Processors 3-4         ;   0.9%      ;
 +----------------------------+-------------+
 
 
 +--------------+
 ; Pin-Out File ;
 +--------------+
-The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
+The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
 
 
 +---------------------------------------------------------------------+
@@ -150,27 +150,27 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
 +---------------------------------------------+-----------------------+
 ; Resource                                    ; Usage                 ;
 +---------------------------------------------+-----------------------+
-; Total logic elements                        ; 197 / 240 ( 82 % )    ;
-;     -- Combinational with no register       ; 85                    ;
-;     -- Register only                        ; 19                    ;
-;     -- Combinational with a register        ; 93                    ;
+; Total logic elements                        ; 238 / 240 ( 99 % )    ;
+;     -- Combinational with no register       ; 115                   ;
+;     -- Register only                        ; 26                    ;
+;     -- Combinational with a register        ; 97                    ;
 ;                                             ;                       ;
 ; Logic element usage by number of LUT inputs ;                       ;
-;     -- 4 input functions                    ; 103                   ;
-;     -- 3 input functions                    ; 29                    ;
-;     -- 2 input functions                    ; 42                    ;
-;     -- 1 input functions                    ; 3                     ;
+;     -- 4 input functions                    ; 118                   ;
+;     -- 3 input functions                    ; 41                    ;
+;     -- 2 input functions                    ; 48                    ;
+;     -- 1 input functions                    ; 4                     ;
 ;     -- 0 input functions                    ; 1                     ;
 ;                                             ;                       ;
 ; Logic elements by mode                      ;                       ;
-;     -- normal mode                          ; 183                   ;
+;     -- normal mode                          ; 224                   ;
 ;     -- arithmetic mode                      ; 14                    ;
-;     -- qfbk mode                            ; 8                     ;
+;     -- qfbk mode                            ; 6                     ;
 ;     -- register cascade mode                ; 0                     ;
-;     -- synchronous clear/load mode          ; 16                    ;
+;     -- synchronous clear/load mode          ; 20                    ;
 ;     -- asynchronous clear/load mode         ; 0                     ;
 ;                                             ;                       ;
-; Total registers                             ; 112 / 240 ( 47 % )    ;
+; Total registers                             ; 123 / 240 ( 51 % )    ;
 ; Total LABs                                  ; 24 / 24 ( 100 % )     ;
 ; Logic elements in carry chains              ; 15                    ;
 ; Virtual pins                                ; 0                     ;
@@ -185,11 +185,11 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
 ; Global signals                              ; 1                     ;
 ;     -- Global clocks                        ; 1 / 4 ( 25 % )        ;
 ; JTAGs                                       ; 0 / 1 ( 0 % )         ;
-; Average interconnect usage (total/H/V)      ; 24.3% / 25.4% / 23.2% ;
-; Peak interconnect usage (total/H/V)         ; 24.3% / 25.4% / 23.2% ;
-; Maximum fan-out                             ; 112                   ;
-; Highest non-global fan-out                  ; 31                    ;
-; Total fan-out                               ; 847                   ;
+; Average interconnect usage (total/H/V)      ; 26.9% / 27.0% / 26.7% ;
+; Peak interconnect usage (total/H/V)         ; 26.9% / 27.0% / 26.7% ;
+; Maximum fan-out                             ; 123                   ;
+; Highest non-global fan-out                  ; 35                    ;
+; Total fan-out                               ; 976                   ;
 ; Average fan-out                             ; 3.16                  ;
 +---------------------------------------------+-----------------------+
 
@@ -207,69 +207,69 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
 ; Ain[5] ; 34    ; 1        ; 3            ; 0            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; Ain[6] ; 39    ; 1        ; 5            ; 0            ; 3           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; Ain[7] ; 53    ; 2        ; 8            ; 1            ; 3           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; C14M   ; 12    ; 1        ; 1            ; 3            ; 3           ; 112                   ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[0] ; 38    ; 1        ; 4            ; 0            ; 0           ; 14                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[1] ; 40    ; 1        ; 5            ; 0            ; 2           ; 7                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; C14M   ; 12    ; 1        ; 1            ; 3            ; 3           ; 123                   ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[0] ; 38    ; 1        ; 4            ; 0            ; 0           ; 15                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[1] ; 40    ; 1        ; 5            ; 0            ; 2           ; 11                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; Din[2] ; 42    ; 1        ; 5            ; 0            ; 0           ; 13                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[3] ; 41    ; 1        ; 5            ; 0            ; 1           ; 12                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[4] ; 48    ; 1        ; 6            ; 0            ; 0           ; 9                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[5] ; 49    ; 1        ; 7            ; 0            ; 2           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[3] ; 41    ; 1        ; 5            ; 0            ; 1           ; 13                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[4] ; 48    ; 1        ; 6            ; 0            ; 0           ; 10                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[5] ; 49    ; 1        ; 7            ; 0            ; 2           ; 9                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; Din[6] ; 36    ; 1        ; 4            ; 0            ; 2           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; Din[7] ; 35    ; 1        ; 3            ; 0            ; 0           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; Din[7] ; 35    ; 1        ; 3            ; 0            ; 0           ; 9                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; PHI1   ; 37    ; 1        ; 4            ; 0            ; 1           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 ; nC07X  ; 52    ; 2        ; 8            ; 1            ; 4           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nEN80  ; 28    ; 1        ; 2            ; 0            ; 1           ; 5                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nWE    ; 51    ; 1        ; 7            ; 0            ; 0           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
-; nWE80  ; 33    ; 1        ; 3            ; 0            ; 2           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nEN80  ; 28    ; 1        ; 2            ; 0            ; 1           ; 10                    ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nWE    ; 51    ; 1        ; 7            ; 0            ; 0           ; 8                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
+; nWE80  ; 33    ; 1        ; 3            ; 0            ; 2           ; 0                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVCMOS ; User                 ; no             ;
 +--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                               ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; BA[0]   ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; BA[1]   ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; CKE     ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; DQMH    ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; DQML    ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[0] ; 77    ; 2        ; 7            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[1] ; 76    ; 2        ; 7            ; 5            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[2] ; 74    ; 2        ; 8            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[3] ; 75    ; 2        ; 7            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[4] ; 73    ; 2        ; 8            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[5] ; 72    ; 2        ; 8            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[6] ; 84    ; 2        ; 6            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[7] ; 85    ; 2        ; 5            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; LED     ; 88    ; 2        ; 5            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[0]   ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[10]  ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[11]  ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[1]   ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[2]   ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[3]   ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[4]   ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[5]   ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[6]   ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[7]   ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[8]   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[9]   ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[0] ; 70    ; 2        ; 8            ; 4            ; 4           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[1] ; 67    ; 2        ; 8            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[2] ; 69    ; 2        ; 8            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[3] ; 62    ; 2        ; 8            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[4] ; 71    ; 2        ; 8            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[5] ; 68    ; 2        ; 8            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[6] ; 58    ; 2        ; 8            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; Vout[7] ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nCAS    ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nCS     ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nDOE    ; 55    ; 2        ; 8            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRAS    ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nRWE    ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nVOE    ; 50    ; 1        ; 7            ; 0            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                 ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; BA[0]     ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; BA[1]     ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; CKEout    ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; DQMH      ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; DQML      ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[0]   ; 77    ; 2        ; 7            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[1]   ; 76    ; 2        ; 7            ; 5            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[2]   ; 74    ; 2        ; 8            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[3]   ; 75    ; 2        ; 7            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[4]   ; 73    ; 2        ; 8            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[5]   ; 72    ; 2        ; 8            ; 4            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[6]   ; 84    ; 2        ; 6            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Dout[7]   ; 85    ; 2        ; 5            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; LED       ; 88    ; 2        ; 5            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[0]  ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[10] ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[11] ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[1]  ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[2]  ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[3]  ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[4]  ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[5]  ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[6]  ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[7]  ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[8]  ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; RAout[9]  ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[0]   ; 70    ; 2        ; 8            ; 4            ; 4           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[1]   ; 67    ; 2        ; 8            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[2]   ; 69    ; 2        ; 8            ; 3            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[3]   ; 62    ; 2        ; 8            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[4]   ; 71    ; 2        ; 8            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[5]   ; 68    ; 2        ; 8            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[6]   ; 58    ; 2        ; 8            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; Vout[7]   ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nCASout   ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nCSout    ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nDOE      ; 55    ; 2        ; 8            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRASout   ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nRWEout   ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; nVOE      ; 50    ; 1        ; 7            ; 0            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
++-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
 
 
 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -283,7 +283,7 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
 ; RD[3] ; 89    ; 2        ; 4            ; 5            ; 0           ; 2                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
 ; RD[4] ; 91    ; 2        ; 4            ; 5            ; 2           ; 2                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
 ; RD[5] ; 92    ; 2        ; 3            ; 5            ; 0           ; 2                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
-; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 2                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
+; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 2                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; RDOE                 ; -                   ;
 ; RD[7] ; 96    ; 2        ; 3            ; 5            ; 2           ; 2                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; RDOE                 ; -                   ;
 +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
 
@@ -304,35 +304,35 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
 ; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
 +----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
 ; 1        ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 2        ; 0          ; 1        ; nRWE           ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 3        ; 1          ; 1        ; nCAS           ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 4        ; 2          ; 1        ; CKE            ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 5        ; 3          ; 1        ; nRAS           ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 2        ; 0          ; 1        ; nRWEout        ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 3        ; 1          ; 1        ; nCASout        ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 4        ; 2          ; 1        ; CKEout         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 5        ; 3          ; 1        ; nRASout        ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
 ; 6        ; 4          ; 1        ; BA[0]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 7        ; 5          ; 1        ; RA[11]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 8        ; 6          ; 1        ; nCS            ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 7        ; 5          ; 1        ; RAout[11]      ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 8        ; 6          ; 1        ; nCSout         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
 ; 9        ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
 ; 10       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
 ; 11       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
 ; 12       ; 7          ; 1        ; C14M           ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
 ; 13       ;            ;          ; VCCINT         ; power  ;              ; 1.8V    ; --         ;                 ; --       ; --           ;
 ; 14       ; 8          ; 1        ; BA[1]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 15       ; 9          ; 1        ; RA[9]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 16       ; 10         ; 1        ; RA[10]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 17       ; 11         ; 1        ; RA[8]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 18       ; 12         ; 1        ; RA[0]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 19       ; 13         ; 1        ; RA[7]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 20       ; 14         ; 1        ; RA[1]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; 21       ; 15         ; 1        ; RA[6]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 15       ; 9          ; 1        ; RAout[9]       ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 16       ; 10         ; 1        ; RAout[10]      ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 17       ; 11         ; 1        ; RAout[8]       ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 18       ; 12         ; 1        ; RAout[0]       ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 19       ; 13         ; 1        ; RAout[7]       ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 20       ; 14         ; 1        ; RAout[1]       ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 21       ; 15         ; 1        ; RAout[6]       ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
 ; 22       ; 16         ; 1        ; #TMS           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
 ; 23       ; 17         ; 1        ; #TDI           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
 ; 24       ; 18         ; 1        ; #TCK           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
 ; 25       ; 19         ; 1        ; #TDO           ; output ;              ;         ; --         ;                 ; --       ; --           ;
-; 26       ; 20         ; 1        ; RA[4]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 27       ; 21         ; 1        ; RA[3]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 26       ; 20         ; 1        ; RAout[4]       ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 27       ; 21         ; 1        ; RAout[3]       ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
 ; 28       ; 22         ; 1        ; nEN80          ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 29       ; 23         ; 1        ; RA[5]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
-; 30       ; 24         ; 1        ; RA[2]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 29       ; 23         ; 1        ; RAout[5]       ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 30       ; 24         ; 1        ; RAout[2]       ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
 ; 31       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
 ; 32       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
 ; 33       ; 25         ; 1        ; nWE80          ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; no       ; Off          ;
@@ -426,112 +426,119 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
 Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
 
 
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                       ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                   ; Entity Name         ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
-; |RAM2E                                                    ; 197 (197)   ; 112          ; 1          ; 70   ; 0            ; 85 (85)      ; 19 (19)           ; 93 (93)          ; 15 (15)         ; 8 (8)      ; |RAM2E                                                                ; RAM2E               ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|UFM:UFM_inst                                                   ; UFM                 ; work         ;
-;       |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                              ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
+; Compilation Hierarchy Node                                   ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                                       ; Entity Name         ; Library Name ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
+; |RAM2E                                                       ; 238 (180)   ; 123          ; 1          ; 70   ; 0            ; 115 (90)     ; 26 (23)           ; 97 (67)          ; 15 (15)         ; 6 (1)      ; |RAM2E                                                                                    ; RAM2E               ; work         ;
+;    |RAM2E_UFM:ram2e_ufm|                                     ; 58 (58)     ; 33           ; 1          ; 0    ; 0            ; 25 (25)      ; 3 (3)             ; 30 (30)          ; 0 (0)           ; 5 (5)      ; |RAM2E|RAM2E_UFM:ram2e_ufm                                                                ; RAM2E_UFM           ; work         ;
+;       |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst                                                   ; UFM                 ; work         ;
+;          |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work         ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
-+------------------------------------+
-; Delay Chain Summary                ;
-+---------+----------+---------------+
-; Name    ; Pin Type ; Pad to Core 0 ;
-+---------+----------+---------------+
-; LED     ; Output   ; --            ;
-; Dout[0] ; Output   ; --            ;
-; Dout[1] ; Output   ; --            ;
-; Dout[2] ; Output   ; --            ;
-; Dout[3] ; Output   ; --            ;
-; Dout[4] ; Output   ; --            ;
-; Dout[5] ; Output   ; --            ;
-; Dout[6] ; Output   ; --            ;
-; Dout[7] ; Output   ; --            ;
-; nDOE    ; Output   ; --            ;
-; Vout[0] ; Output   ; --            ;
-; Vout[1] ; Output   ; --            ;
-; Vout[2] ; Output   ; --            ;
-; Vout[3] ; Output   ; --            ;
-; Vout[4] ; Output   ; --            ;
-; Vout[5] ; Output   ; --            ;
-; Vout[6] ; Output   ; --            ;
-; Vout[7] ; Output   ; --            ;
-; nVOE    ; Output   ; --            ;
-; CKE     ; Output   ; --            ;
-; nCS     ; Output   ; --            ;
-; nRAS    ; Output   ; --            ;
-; nCAS    ; Output   ; --            ;
-; nRWE    ; Output   ; --            ;
-; BA[0]   ; Output   ; --            ;
-; BA[1]   ; Output   ; --            ;
-; RA[0]   ; Output   ; --            ;
-; RA[1]   ; Output   ; --            ;
-; RA[2]   ; Output   ; --            ;
-; RA[3]   ; Output   ; --            ;
-; RA[4]   ; Output   ; --            ;
-; RA[5]   ; Output   ; --            ;
-; RA[6]   ; Output   ; --            ;
-; RA[7]   ; Output   ; --            ;
-; RA[8]   ; Output   ; --            ;
-; RA[9]   ; Output   ; --            ;
-; RA[10]  ; Output   ; --            ;
-; RA[11]  ; Output   ; --            ;
-; DQML    ; Output   ; --            ;
-; DQMH    ; Output   ; --            ;
-; RD[0]   ; Bidir    ; (0)           ;
-; RD[1]   ; Bidir    ; (0)           ;
-; RD[2]   ; Bidir    ; (0)           ;
-; RD[3]   ; Bidir    ; (0)           ;
-; RD[4]   ; Bidir    ; (0)           ;
-; RD[5]   ; Bidir    ; (0)           ;
-; RD[6]   ; Bidir    ; (0)           ;
-; RD[7]   ; Bidir    ; (0)           ;
-; nEN80   ; Input    ; (0)           ;
-; nWE     ; Input    ; (0)           ;
-; PHI1    ; Input    ; (1)           ;
-; Din[0]  ; Input    ; (0)           ;
-; C14M    ; Input    ; (0)           ;
-; nWE80   ; Input    ; (0)           ;
-; Ain[0]  ; Input    ; (0)           ;
-; Ain[1]  ; Input    ; (0)           ;
-; Ain[2]  ; Input    ; (0)           ;
-; Ain[3]  ; Input    ; (0)           ;
-; Ain[4]  ; Input    ; (0)           ;
-; Ain[5]  ; Input    ; (0)           ;
-; Ain[6]  ; Input    ; (0)           ;
-; Ain[7]  ; Input    ; (0)           ;
-; Din[6]  ; Input    ; (0)           ;
-; Din[2]  ; Input    ; (0)           ;
-; Din[1]  ; Input    ; (0)           ;
-; Din[5]  ; Input    ; (0)           ;
-; Din[7]  ; Input    ; (0)           ;
-; Din[4]  ; Input    ; (0)           ;
-; Din[3]  ; Input    ; (0)           ;
-; nC07X   ; Input    ; (0)           ;
-+---------+----------+---------------+
++--------------------------------------+
+; Delay Chain Summary                  ;
++-----------+----------+---------------+
+; Name      ; Pin Type ; Pad to Core 0 ;
++-----------+----------+---------------+
+; LED       ; Output   ; --            ;
+; nWE80     ; Input    ; (0)           ;
+; Dout[0]   ; Output   ; --            ;
+; Dout[1]   ; Output   ; --            ;
+; Dout[2]   ; Output   ; --            ;
+; Dout[3]   ; Output   ; --            ;
+; Dout[4]   ; Output   ; --            ;
+; Dout[5]   ; Output   ; --            ;
+; Dout[6]   ; Output   ; --            ;
+; Dout[7]   ; Output   ; --            ;
+; nDOE      ; Output   ; --            ;
+; Vout[0]   ; Output   ; --            ;
+; Vout[1]   ; Output   ; --            ;
+; Vout[2]   ; Output   ; --            ;
+; Vout[3]   ; Output   ; --            ;
+; Vout[4]   ; Output   ; --            ;
+; Vout[5]   ; Output   ; --            ;
+; Vout[6]   ; Output   ; --            ;
+; Vout[7]   ; Output   ; --            ;
+; nVOE      ; Output   ; --            ;
+; CKEout    ; Output   ; --            ;
+; nCSout    ; Output   ; --            ;
+; nRASout   ; Output   ; --            ;
+; nCASout   ; Output   ; --            ;
+; nRWEout   ; Output   ; --            ;
+; BA[0]     ; Output   ; --            ;
+; BA[1]     ; Output   ; --            ;
+; RAout[0]  ; Output   ; --            ;
+; RAout[1]  ; Output   ; --            ;
+; RAout[2]  ; Output   ; --            ;
+; RAout[3]  ; Output   ; --            ;
+; RAout[4]  ; Output   ; --            ;
+; RAout[5]  ; Output   ; --            ;
+; RAout[6]  ; Output   ; --            ;
+; RAout[7]  ; Output   ; --            ;
+; RAout[8]  ; Output   ; --            ;
+; RAout[9]  ; Output   ; --            ;
+; RAout[10] ; Output   ; --            ;
+; RAout[11] ; Output   ; --            ;
+; DQML      ; Output   ; --            ;
+; DQMH      ; Output   ; --            ;
+; RD[0]     ; Bidir    ; (0)           ;
+; RD[1]     ; Bidir    ; (0)           ;
+; RD[2]     ; Bidir    ; (0)           ;
+; RD[3]     ; Bidir    ; (0)           ;
+; RD[4]     ; Bidir    ; (0)           ;
+; RD[5]     ; Bidir    ; (0)           ;
+; RD[6]     ; Bidir    ; (0)           ;
+; RD[7]     ; Bidir    ; (0)           ;
+; nEN80     ; Input    ; (0)           ;
+; nWE       ; Input    ; (0)           ;
+; PHI1      ; Input    ; (1)           ;
+; C14M      ; Input    ; (0)           ;
+; Din[0]    ; Input    ; (0)           ;
+; Din[6]    ; Input    ; (0)           ;
+; Din[1]    ; Input    ; (0)           ;
+; Din[5]    ; Input    ; (0)           ;
+; Din[7]    ; Input    ; (0)           ;
+; Din[4]    ; Input    ; (0)           ;
+; Din[2]    ; Input    ; (0)           ;
+; Din[3]    ; Input    ; (0)           ;
+; nC07X     ; Input    ; (0)           ;
+; Ain[0]    ; Input    ; (0)           ;
+; Ain[1]    ; Input    ; (0)           ;
+; Ain[2]    ; Input    ; (0)           ;
+; Ain[3]    ; Input    ; (0)           ;
+; Ain[4]    ; Input    ; (0)           ;
+; Ain[5]    ; Input    ; (0)           ;
+; Ain[6]    ; Input    ; (0)           ;
+; Ain[7]    ; Input    ; (0)           ;
++-----------+----------+---------------+
 
 
-+-------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                       ;
-+------------+-------------+---------+---------------+--------+----------------------+------------------+
-; Name       ; Location    ; Fan-Out ; Usage         ; Global ; Global Resource Used ; Global Line Name ;
-+------------+-------------+---------+---------------+--------+----------------------+------------------+
-; C14M       ; PIN_12      ; 112     ; Clock         ; yes    ; Global Clock         ; GCLK0            ;
-; CS[0]~2    ; LC_X6_Y1_N1 ; 3       ; Clock enable  ; no     ; --                   ; --               ;
-; Equal9~1   ; LC_X5_Y3_N0 ; 16      ; Clock enable  ; no     ; --                   ; --               ;
-; Equal9~2   ; LC_X7_Y2_N5 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
-; RA[0]~15   ; LC_X2_Y2_N0 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
-; RDOE       ; LC_X2_Y4_N6 ; 8       ; Output enable ; no     ; --                   ; --               ;
-; RWMask~1   ; LC_X4_Y1_N7 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
-; S[2]       ; LC_X7_Y2_N1 ; 22      ; Sync. clear   ; no     ; --                   ; --               ;
-; UFMD[15]~0 ; LC_X5_Y1_N1 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
-; always2~8  ; LC_X6_Y1_N2 ; 16      ; Clock enable  ; no     ; --                   ; --               ;
-+------------+-------------+---------+---------------+--------+----------------------+------------------+
++---------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                           ;
++--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
+; Name                           ; Location    ; Fan-Out ; Usage         ; Global ; Global Resource Used ; Global Line Name ;
++--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
+; BA[1]~0                        ; LC_X2_Y2_N7 ; 2       ; Clock enable  ; no     ; --                   ; --               ;
+; C14M                           ; PIN_12      ; 123     ; Clock         ; yes    ; Global Clock         ; GCLK0            ;
+; CS[0]~2                        ; LC_X4_Y3_N0 ; 3       ; Clock enable  ; no     ; --                   ; --               ;
+; DQML~0                         ; LC_X2_Y4_N5 ; 2       ; Clock enable  ; no     ; --                   ; --               ;
+; Equal1~1                       ; LC_X6_Y3_N2 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
+; Equal1~2                       ; LC_X6_Y4_N0 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
+; Equal1~4                       ; LC_X6_Y3_N1 ; 4       ; Clock enable  ; no     ; --                   ; --               ;
+; Equal1~5                       ; LC_X5_Y4_N8 ; 3       ; Clock enable  ; no     ; --                   ; --               ;
+; Mux14~0                        ; LC_X5_Y4_N3 ; 2       ; Clock enable  ; no     ; --                   ; --               ;
+; RAM2E_UFM:ram2e_ufm|RWMask~1   ; LC_X6_Y1_N9 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
+; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X4_Y1_N6 ; 8       ; Clock enable  ; no     ; --                   ; --               ;
+; RAM2E_UFM:ram2e_ufm|always2~8  ; LC_X6_Y3_N9 ; 16      ; Clock enable  ; no     ; --                   ; --               ;
+; RA[2]~0                        ; LC_X2_Y2_N5 ; 6       ; Clock enable  ; no     ; --                   ; --               ;
+; RDOE                           ; LC_X3_Y4_N0 ; 8       ; Output enable ; no     ; --                   ; --               ;
+; S[0]                           ; LC_X7_Y3_N2 ; 35      ; Sync. clear   ; no     ; --                   ; --               ;
+; S[3]                           ; LC_X6_Y4_N9 ; 32      ; Sync. clear   ; no     ; --                   ; --               ;
++--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
 
 
 +---------------------------------------------------------------------+
@@ -539,7 +546,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +------+----------+---------+----------------------+------------------+
 ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
 +------+----------+---------+----------------------+------------------+
-; C14M ; PIN_12   ; 112     ; Global Clock         ; GCLK0            ;
+; C14M ; PIN_12   ; 123     ; Global Clock         ; GCLK0            ;
 +------+----------+---------+----------------------+------------------+
 
 
@@ -548,118 +555,121 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-----------------------+--------------------+
 ; Routing Resource Type ; Usage              ;
 +-----------------------+--------------------+
-; C4s                   ; 146 / 784 ( 19 % ) ;
-; Direct links          ; 31 / 888 ( 3 % )   ;
+; C4s                   ; 171 / 784 ( 22 % ) ;
+; Direct links          ; 55 / 888 ( 6 % )   ;
 ; Global clocks         ; 1 / 4 ( 25 % )     ;
 ; LAB clocks            ; 6 / 32 ( 19 % )    ;
-; LUT chains            ; 4 / 216 ( 2 % )    ;
-; Local interconnects   ; 279 / 888 ( 31 % ) ;
-; R4s                   ; 144 / 704 ( 20 % ) ;
+; LUT chains            ; 6 / 216 ( 3 % )    ;
+; Local interconnects   ; 343 / 888 ( 39 % ) ;
+; R4s                   ; 150 / 704 ( 21 % ) ;
 +-----------------------+--------------------+
 
 
 +---------------------------------------------------------------------------+
 ; LAB Logic Elements                                                        ;
 +--------------------------------------------+------------------------------+
-; Number of Logic Elements  (Average = 8.21) ; Number of LABs  (Total = 24) ;
+; Number of Logic Elements  (Average = 9.92) ; Number of LABs  (Total = 24) ;
 +--------------------------------------------+------------------------------+
-; 1                                          ; 2                            ;
+; 1                                          ; 0                            ;
 ; 2                                          ; 0                            ;
-; 3                                          ; 1                            ;
+; 3                                          ; 0                            ;
 ; 4                                          ; 0                            ;
-; 5                                          ; 1                            ;
-; 6                                          ; 1                            ;
-; 7                                          ; 1                            ;
-; 8                                          ; 2                            ;
-; 9                                          ; 2                            ;
-; 10                                         ; 14                           ;
+; 5                                          ; 0                            ;
+; 6                                          ; 0                            ;
+; 7                                          ; 0                            ;
+; 8                                          ; 1                            ;
+; 9                                          ; 0                            ;
+; 10                                         ; 23                           ;
 +--------------------------------------------+------------------------------+
 
 
 +-------------------------------------------------------------------+
 ; LAB-wide Signals                                                  ;
 +------------------------------------+------------------------------+
-; LAB-wide Signals  (Average = 1.38) ; Number of LABs  (Total = 24) ;
+; LAB-wide Signals  (Average = 1.58) ; Number of LABs  (Total = 24) ;
 +------------------------------------+------------------------------+
-; 1 Clock                            ; 22                           ;
-; 1 Clock enable                     ; 10                           ;
-; 2 Clock enables                    ; 1                            ;
+; 1 Clock                            ; 24                           ;
+; 1 Clock enable                     ; 9                            ;
+; 1 Sync. clear                      ; 2                            ;
+; 2 Clock enables                    ; 3                            ;
 +------------------------------------+------------------------------+
 
 
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced                                                        ;
-+---------------------------------------------+------------------------------+
-; Number of Signals Sourced  (Average = 8.54) ; Number of LABs  (Total = 24) ;
-+---------------------------------------------+------------------------------+
-; 0                                           ; 0                            ;
-; 1                                           ; 2                            ;
-; 2                                           ; 0                            ;
-; 3                                           ; 1                            ;
-; 4                                           ; 0                            ;
-; 5                                           ; 1                            ;
-; 6                                           ; 1                            ;
-; 7                                           ; 0                            ;
-; 8                                           ; 2                            ;
-; 9                                           ; 2                            ;
-; 10                                          ; 13                           ;
-; 11                                          ; 0                            ;
-; 12                                          ; 1                            ;
-; 13                                          ; 1                            ;
-+---------------------------------------------+------------------------------+
++-----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                         ;
++----------------------------------------------+------------------------------+
+; Number of Signals Sourced  (Average = 10.17) ; Number of LABs  (Total = 24) ;
++----------------------------------------------+------------------------------+
+; 0                                            ; 0                            ;
+; 1                                            ; 0                            ;
+; 2                                            ; 0                            ;
+; 3                                            ; 0                            ;
+; 4                                            ; 0                            ;
+; 5                                            ; 0                            ;
+; 6                                            ; 0                            ;
+; 7                                            ; 0                            ;
+; 8                                            ; 1                            ;
+; 9                                            ; 0                            ;
+; 10                                           ; 21                           ;
+; 11                                           ; 1                            ;
+; 12                                           ; 0                            ;
+; 13                                           ; 0                            ;
+; 14                                           ; 0                            ;
+; 15                                           ; 1                            ;
++----------------------------------------------+------------------------------+
 
 
 +--------------------------------------------------------------------------------+
 ; LAB Signals Sourced Out                                                        ;
 +-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out  (Average = 6.25) ; Number of LABs  (Total = 24) ;
+; Number of Signals Sourced Out  (Average = 7.50) ; Number of LABs  (Total = 24) ;
 +-------------------------------------------------+------------------------------+
 ; 0                                               ; 0                            ;
-; 1                                               ; 2                            ;
+; 1                                               ; 0                            ;
 ; 2                                               ; 0                            ;
 ; 3                                               ; 1                            ;
 ; 4                                               ; 2                            ;
-; 5                                               ; 5                            ;
+; 5                                               ; 3                            ;
 ; 6                                               ; 2                            ;
-; 7                                               ; 3                            ;
-; 8                                               ; 5                            ;
-; 9                                               ; 2                            ;
-; 10                                              ; 1                            ;
-; 11                                              ; 1                            ;
+; 7                                               ; 2                            ;
+; 8                                               ; 4                            ;
+; 9                                               ; 6                            ;
+; 10                                              ; 3                            ;
+; 11                                              ; 0                            ;
+; 12                                              ; 1                            ;
 +-------------------------------------------------+------------------------------+
 
 
 +-----------------------------------------------------------------------------+
 ; LAB Distinct Inputs                                                         ;
 +----------------------------------------------+------------------------------+
-; Number of Distinct Inputs  (Average = 10.46) ; Number of LABs  (Total = 24) ;
+; Number of Distinct Inputs  (Average = 12.88) ; Number of LABs  (Total = 24) ;
 +----------------------------------------------+------------------------------+
 ; 0                                            ; 0                            ;
 ; 1                                            ; 0                            ;
 ; 2                                            ; 0                            ;
-; 3                                            ; 4                            ;
-; 4                                            ; 0                            ;
-; 5                                            ; 2                            ;
+; 3                                            ; 0                            ;
+; 4                                            ; 2                            ;
+; 5                                            ; 1                            ;
 ; 6                                            ; 0                            ;
-; 7                                            ; 1                            ;
-; 8                                            ; 2                            ;
-; 9                                            ; 2                            ;
-; 10                                           ; 3                            ;
-; 11                                           ; 3                            ;
-; 12                                           ; 0                            ;
-; 13                                           ; 1                            ;
-; 14                                           ; 1                            ;
-; 15                                           ; 1                            ;
-; 16                                           ; 1                            ;
-; 17                                           ; 0                            ;
-; 18                                           ; 0                            ;
-; 19                                           ; 0                            ;
+; 7                                            ; 2                            ;
+; 8                                            ; 0                            ;
+; 9                                            ; 0                            ;
+; 10                                           ; 2                            ;
+; 11                                           ; 1                            ;
+; 12                                           ; 1                            ;
+; 13                                           ; 3                            ;
+; 14                                           ; 3                            ;
+; 15                                           ; 2                            ;
+; 16                                           ; 2                            ;
+; 17                                           ; 1                            ;
+; 18                                           ; 2                            ;
+; 19                                           ; 1                            ;
 ; 20                                           ; 0                            ;
-; 21                                           ; 2                            ;
+; 21                                           ; 0                            ;
 ; 22                                           ; 0                            ;
 ; 23                                           ; 0                            ;
-; 24                                           ; 0                            ;
-; 25                                           ; 1                            ;
+; 24                                           ; 1                            ;
 +----------------------------------------------+------------------------------+
 
 
@@ -700,11 +710,11 @@ Info (332129): Detected timing requirements -- optimizing circuit to achieve onl
 Info (332111): Found 3 clocks
     Info (332111):   Period   Clock Name
     Info (332111): ======== ============
-    Info (332111):  200.000        ARCLK
     Info (332111):   69.841         C14M
-    Info (332111):  200.000        DRCLK
+    Info (332111):  200.000 ram2e_ufm|ARCLK|regout
+    Info (332111):  200.000 ram2e_ufm|DRCLK|regout
 Info (186079): Completed User Assigned Global Signals Promotion Operation
-Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 8
+Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
 Info (186079): Completed Auto Global Promotion Operation
 Info (176234): Starting register packing
 Info (186468): Started processing fast register assignments
@@ -718,25 +728,23 @@ Info (170191): Fitter placement operations beginning
 Info (170137): Fitter placement was successful
 Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
 Info (170193): Fitter routing operations beginning
-Info (170089): 2e+01 ns of routing delay (approximately 1.0% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
-Info (170195): Router estimated average interconnect usage is 21% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170195): Router estimated average interconnect usage is 23% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 23% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
+Info (170202): The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
 Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.58 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.67 seconds.
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
+Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 13770 megabytes
-    Info: Processing ended: Thu Sep 21 05:34:39 2023
-    Info: Elapsed time: 00:00:05
-    Info: Total CPU time (on all processors): 00:00:03
+    Info: Peak virtual memory: 13748 megabytes
+    Info: Processing ended: Thu Dec 28 23:09:45 2023
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:04
 
 
 +----------------------------+
 ; Fitter Suppressed Messages ;
 +----------------------------+
-The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg.
+The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg.
 
 
diff --git a/CPLD/MAXV/output_files/RAM2E.fit.summary b/CPLD/MAXV/output_files/RAM2E.fit.summary
index 375255d..0ef0041 100644
--- a/CPLD/MAXV/output_files/RAM2E.fit.summary
+++ b/CPLD/MAXV/output_files/RAM2E.fit.summary
@@ -1,11 +1,11 @@
-Fitter Status : Successful - Thu Sep 21 05:34:38 2023
-Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Fitter Status : Successful - Thu Dec 28 23:09:45 2023
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
 Family : MAX V
 Device : 5M240ZT100C5
 Timing Models : Final
-Total logic elements : 197 / 240 ( 82 % )
+Total logic elements : 238 / 240 ( 99 % )
 Total pins : 70 / 79 ( 89 % )
 Total virtual pins : 0
 UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXV/output_files/RAM2E.flow.rpt b/CPLD/MAXV/output_files/RAM2E.flow.rpt
index e4e5269..13640c2 100644
--- a/CPLD/MAXV/output_files/RAM2E.flow.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.flow.rpt
@@ -1,6 +1,6 @@
 Flow report for RAM2E
-Thu Sep 21 05:34:46 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Thu Dec 28 23:09:52 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
 ---------------------
@@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
 
 
 
-+---------------------------------------------------------------------+
-; Flow Summary                                                        ;
-+-----------------------+---------------------------------------------+
-; Flow Status           ; Successful - Thu Sep 21 05:34:42 2023       ;
-; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name         ; RAM2E                                       ;
-; Top-level Entity Name ; RAM2E                                       ;
-; Family                ; MAX V                                       ;
-; Device                ; 5M240ZT100C5                                ;
-; Timing Models         ; Final                                       ;
-; Total logic elements  ; 197 / 240 ( 82 % )                          ;
-; Total pins            ; 70 / 79 ( 89 % )                            ;
-; Total virtual pins    ; 0                                           ;
-; UFM blocks            ; 1 / 1 ( 100 % )                             ;
-+-----------------------+---------------------------------------------+
++-------------------------------------------------------------------------------------+
+; Flow Summary                                                                        ;
++-----------------------+-------------------------------------------------------------+
+; Flow Status           ; Successful - Thu Dec 28 23:09:48 2023                       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
+; Revision Name         ; RAM2E                                                       ;
+; Top-level Entity Name ; RAM2E                                                       ;
+; Family                ; MAX V                                                       ;
+; Device                ; 5M240ZT100C5                                                ;
+; Timing Models         ; Final                                                       ;
+; Total logic elements  ; 238 / 240 ( 99 % )                                          ;
+; Total pins            ; 70 / 79 ( 89 % )                                            ;
+; Total virtual pins    ; 0                                                           ;
+; UFM blocks            ; 1 / 1 ( 100 % )                                             ;
++-----------------------+-------------------------------------------------------------+
 
 
 +-----------------------------------------+
@@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 09/21/2023 05:34:00 ;
+; Start date & time ; 12/28/2023 23:09:13 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; RAM2E               ;
 +-------------------+---------------------+
@@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------+------------------------------+---------------+-------------+------------+
 ; Assignment Name               ; Value                        ; Default Value ; Entity Name ; Section Id ;
 +-------------------------------+------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID         ; 121381084694.169528883915840 ; --            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID         ; 121381084694.170382295304664 ; --            ; --          ; --         ;
 ; MAX_CORE_JUNCTION_TEMP        ; 85                           ; --            ; --          ; --         ;
 ; MIN_CORE_JUNCTION_TEMP        ; 0                            ; --            ; --          ; --         ;
 ; NUM_PARALLEL_PROCESSORS       ; 4                            ; --            ; --          ; --         ;
@@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:35     ; 1.0                     ; 13144 MB            ; 00:00:50                           ;
-; Fitter               ; 00:00:04     ; 1.0                     ; 13770 MB            ; 00:00:03                           ;
-; Assembler            ; 00:00:01     ; 1.0                     ; 13091 MB            ; 00:00:01                           ;
-; Timing Analyzer      ; 00:00:03     ; 1.0                     ; 13092 MB            ; 00:00:02                           ;
-; Total                ; 00:00:43     ; --                      ; --                  ; 00:00:56                           ;
+; Analysis & Synthesis ; 00:00:28     ; 1.0                     ; 13113 MB            ; 00:00:41                           ;
+; Fitter               ; 00:00:04     ; 1.0                     ; 13748 MB            ; 00:00:04                           ;
+; Assembler            ; 00:00:01     ; 1.0                     ; 13069 MB            ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:03     ; 1.0                     ; 13067 MB            ; 00:00:02                           ;
+; Total                ; 00:00:36     ; --                      ; --                  ; 00:00:48                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
diff --git a/CPLD/MAXV/output_files/RAM2E.jdi b/CPLD/MAXV/output_files/RAM2E.jdi
index bec8212..60ebd55 100644
--- a/CPLD/MAXV/output_files/RAM2E.jdi
+++ b/CPLD/MAXV/output_files/RAM2E.jdi
@@ -1,6 +1,6 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="ec04ae5d795b1a9f31d1"/>
+    <hash md5_digest_80b="a200c32949da45b33c7d"/>
   </project>
   <file_info>
     <file device="5M240ZT100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>
diff --git a/CPLD/MAXV/output_files/RAM2E.map.rpt b/CPLD/MAXV/output_files/RAM2E.map.rpt
index 6f3badf..51a17f5 100644
--- a/CPLD/MAXV/output_files/RAM2E.map.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.map.rpt
@@ -1,6 +1,6 @@
 Analysis & Synthesis report for RAM2E
-Thu Sep 21 05:34:33 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Thu Dec 28 23:09:40 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
 ---------------------
@@ -17,7 +17,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
   9. General Register Statistics
  10. Inverted Register Statistics
  11. Multiplexer Restructuring Statistics (Restructuring Performed)
- 12. Port Connectivity Checks: "UFM:UFM_inst"
+ 12. Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst"
  13. Analysis & Synthesis Messages
  14. Analysis & Synthesis Suppressed Messages
 
@@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
 
 
 
-+---------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                              ;
-+-----------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:34:33 2023       ;
-; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Revision Name               ; RAM2E                                       ;
-; Top-level Entity Name       ; RAM2E                                       ;
-; Family                      ; MAX V                                       ;
-; Total logic elements        ; 205                                         ;
-; Total pins                  ; 70                                          ;
-; Total virtual pins          ; 0                                           ;
-; UFM blocks                  ; 1 / 1 ( 100 % )                             ;
-+-----------------------------+---------------------------------------------+
++-------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                              ;
++-----------------------------+-------------------------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Thu Dec 28 23:09:40 2023                       ;
+; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
+; Revision Name               ; RAM2E                                                       ;
+; Top-level Entity Name       ; RAM2E                                                       ;
+; Family                      ; MAX V                                                       ;
+; Total logic elements        ; 244                                                         ;
+; Total pins                  ; 70                                                          ;
+; Total virtual pins          ; 0                                                           ;
+; UFM blocks                  ; 1 / 1 ( 100 % )                                             ;
++-----------------------------+-------------------------------------------------------------+
 
 
 +------------------------------------------------------------------------------------------------------------+
@@ -146,15 +146,16 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------+-------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                      ;
-+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type                        ; File Name with Absolute Path              ; Library ;
-+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
-; ../RAM2E-MAX.v                   ; yes             ; User Verilog HDL File            ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v ;         ;
-; UFM.v                            ; yes             ; User Wizard-Generated File       ; //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v  ;         ;
-; ../RAM2E.mif                     ; yes             ; User Memory Initialization File  ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.mif   ;         ;
-+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                           ;
++----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                        ; File Name with Absolute Path   ; Library ;
++----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
+; ../RAM2E.v                       ; yes             ; User Verilog HDL File            ; Y:/Repos/RAM2E/CPLD/RAM2E.v    ;         ;
+; ../UFM-MAX.v                     ; yes             ; User Verilog HDL File            ; Y:/Repos/RAM2E/CPLD/UFM-MAX.v  ;         ;
+; UFM.v                            ; yes             ; User Wizard-Generated File       ; Y:/Repos/RAM2E/CPLD/MAXV/UFM.v ;         ;
+; ../RAM2E.mif                     ; yes             ; User Memory Initialization File  ; Y:/Repos/RAM2E/CPLD/RAM2E.mif  ;         ;
++----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
 
 
 +-----------------------------------------------------+
@@ -162,56 +163,57 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------+-------+
 ; Resource                                    ; Usage ;
 +---------------------------------------------+-------+
-; Total logic elements                        ; 205   ;
-;     -- Combinational with no register       ; 93    ;
-;     -- Register only                        ; 27    ;
-;     -- Combinational with a register        ; 85    ;
+; Total logic elements                        ; 244   ;
+;     -- Combinational with no register       ; 121   ;
+;     -- Register only                        ; 32    ;
+;     -- Combinational with a register        ; 91    ;
 ;                                             ;       ;
 ; Logic element usage by number of LUT inputs ;       ;
-;     -- 4 input functions                    ; 103   ;
-;     -- 3 input functions                    ; 29    ;
-;     -- 2 input functions                    ; 42    ;
-;     -- 1 input functions                    ; 3     ;
+;     -- 4 input functions                    ; 118   ;
+;     -- 3 input functions                    ; 41    ;
+;     -- 2 input functions                    ; 48    ;
+;     -- 1 input functions                    ; 4     ;
 ;     -- 0 input functions                    ; 1     ;
 ;                                             ;       ;
 ; Logic elements by mode                      ;       ;
-;     -- normal mode                          ; 191   ;
+;     -- normal mode                          ; 230   ;
 ;     -- arithmetic mode                      ; 14    ;
 ;     -- qfbk mode                            ; 0     ;
 ;     -- register cascade mode                ; 0     ;
-;     -- synchronous clear/load mode          ; 1     ;
+;     -- synchronous clear/load mode          ; 3     ;
 ;     -- asynchronous clear/load mode         ; 0     ;
 ;                                             ;       ;
-; Total registers                             ; 112   ;
+; Total registers                             ; 123   ;
 ; Total logic cells in carry chains           ; 15    ;
 ; I/O pins                                    ; 70    ;
 ; UFM blocks                                  ; 1     ;
 ; Maximum fan-out node                        ; C14M  ;
-; Maximum fan-out                             ; 112   ;
-; Total fan-out                               ; 850   ;
-; Average fan-out                             ; 3.08  ;
+; Maximum fan-out                             ; 123   ;
+; Total fan-out                               ; 977   ;
+; Average fan-out                             ; 3.10  ;
 +---------------------------------------------+-------+
 
 
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                   ; Entity Name         ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
-; |RAM2E                                                    ; 205 (205)   ; 112          ; 1          ; 70   ; 0            ; 93 (93)      ; 27 (27)           ; 85 (85)          ; 15 (15)         ; 0 (0)      ; |RAM2E                                                                ; RAM2E               ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|UFM:UFM_inst                                                   ; UFM                 ; work         ;
-;       |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
+; Compilation Hierarchy Node                                   ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                                       ; Entity Name         ; Library Name ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
+; |RAM2E                                                       ; 244 (181)   ; 123          ; 1          ; 70   ; 0            ; 121 (91)     ; 32 (24)           ; 91 (66)          ; 15 (15)         ; 0 (0)      ; |RAM2E                                                                                    ; RAM2E               ; work         ;
+;    |RAM2E_UFM:ram2e_ufm|                                     ; 63 (63)     ; 33           ; 1          ; 0    ; 0            ; 30 (30)      ; 8 (8)             ; 25 (25)          ; 0 (0)           ; 0 (0)      ; |RAM2E|RAM2E_UFM:ram2e_ufm                                                                ; RAM2E_UFM           ; work         ;
+;       |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst                                                   ; UFM                 ; work         ;
+;          |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work         ;
++--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
-+--------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis IP Cores Summary                                                                              ;
-+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
-; Vendor ; IP Core Name              ; Version ; Release Date ; License Type ; Entity Instance     ; IP Include File ;
-+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
-; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1    ; N/A          ; N/A          ; |RAM2E|UFM:UFM_inst ; UFM.v           ;
-+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                  ;
++--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
+; Vendor ; IP Core Name              ; Version ; Release Date ; License Type ; Entity Instance                         ; IP Include File ;
++--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
+; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1    ; N/A          ; N/A          ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM.v           ;
++--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
 
 
 +------------------------------------------------------+
@@ -219,12 +221,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------------------------------------------+-------+
 ; Statistic                                    ; Value ;
 +----------------------------------------------+-------+
-; Total registers                              ; 112   ;
-; Number of registers using Synchronous Clear  ; 1     ;
+; Total registers                              ; 123   ;
+; Number of registers using Synchronous Clear  ; 3     ;
 ; Number of registers using Synchronous Load   ; 0     ;
 ; Number of registers using Asynchronous Clear ; 0     ;
 ; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 60    ;
+; Number of registers using Clock Enable       ; 62    ;
 ; Number of registers using Preset             ; 0     ;
 +----------------------------------------------+-------+
 
@@ -234,30 +236,36 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------------------------------------+---------+
 ; Inverted Register                      ; Fan out ;
 +----------------------------------------+---------+
-; nCS~reg0                               ; 1       ;
-; nRAS~reg0                              ; 1       ;
-; nCAS~reg0                              ; 1       ;
-; nRWE~reg0                              ; 1       ;
+; nRASout~reg0                           ; 1       ;
+; nCASout~reg0                           ; 1       ;
+; nRWEout~reg0                           ; 1       ;
 ; DQML~reg0                              ; 1       ;
 ; DQMH~reg0                              ; 1       ;
-; Total number of inverted registers = 6 ;         ;
+; CKE                                    ; 1       ;
+; nRAS                                   ; 1       ;
+; nCAS                                   ; 1       ;
+; nRWE                                   ; 1       ;
+; Total number of inverted registers = 9 ;         ;
 +----------------------------------------+---------+
 
 
-+------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |RAM2E|RA[0]~reg0          ;
-; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |RAM2E|S[2]                ;
-; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |RAM2E|CS[0]               ;
-; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |RAM2E|RWMask[4]           ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                     ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output           ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |RAM2E|S[0]                          ;
+; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |RAM2E|CS[0]                         ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[5] ;
+; 16:1               ; 2 bits    ; 20 LEs        ; 2 LEs                ; 18 LEs                 ; Yes        ; |RAM2E|BA[1]~reg0                    ;
+; 17:1               ; 4 bits    ; 44 LEs        ; 8 LEs                ; 36 LEs                 ; Yes        ; |RAM2E|RA[4]                         ;
+; 19:1               ; 2 bits    ; 24 LEs        ; 4 LEs                ; 20 LEs                 ; Yes        ; |RAM2E|RA[2]                         ;
+; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |RAM2E|DQML~reg0                     ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
 
 
 +------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "UFM:UFM_inst"                                                                         ;
+; Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst"                                                     ;
 +--------+--------+----------+-------------------------------------------------------------------------------------+
 ; Port   ; Type   ; Severity ; Details                                                                             ;
 +--------+--------+----------+-------------------------------------------------------------------------------------+
@@ -272,35 +280,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-------------------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Thu Sep 21 05:33:58 2023
+    Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
+    Info: Processing started: Thu Dec 28 23:09:12 2023
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
-Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2e/cpld/ram2e-max.v
-    Info (12023): Found entity 1: RAM2E File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
+    Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ufm-max.v
+    Info (12023): Found entity 1: RAM2E_UFM File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
-    Info (12023): Found entity 1: UFM_altufm_none_p8r File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47
-    Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166
+    Info (12023): Found entity 1: UFM_altufm_none_p8r File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47
+    Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166
 Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
-Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 93
-Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217
-Info (21057): Implemented 276 device resources after synthesis - the final resource count might be different
+Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 112
+Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 79
+Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "nCSout" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 78
+Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
+Warning (21074): Design contains 1 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "nWE80" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 11
+Info (21057): Implemented 315 device resources after synthesis - the final resource count might be different
     Info (21058): Implemented 22 input pins
     Info (21059): Implemented 40 output pins
     Info (21060): Implemented 8 bidirectional pins
-    Info (21061): Implemented 205 logic cells
+    Info (21061): Implemented 244 logic cells
     Info (21070): Implemented 1 User Flash Memory blocks
-Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 13144 megabytes
-    Info: Processing ended: Thu Sep 21 05:34:33 2023
-    Info: Elapsed time: 00:00:35
-    Info: Total CPU time (on all processors): 00:00:50
+Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
+    Info: Peak virtual memory: 13113 megabytes
+    Info: Processing ended: Thu Dec 28 23:09:40 2023
+    Info: Elapsed time: 00:00:28
+    Info: Total CPU time (on all processors): 00:00:41
 
 
 +------------------------------------------+
 ; Analysis & Synthesis Suppressed Messages ;
 +------------------------------------------+
-The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg.
+The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg.
 
 
diff --git a/CPLD/MAXV/output_files/RAM2E.map.smsg b/CPLD/MAXV/output_files/RAM2E.map.smsg
index 0b3ca79..37d8d09 100644
--- a/CPLD/MAXV/output_files/RAM2E.map.smsg
+++ b/CPLD/MAXV/output_files/RAM2E.map.smsg
@@ -1,3 +1,3 @@
-Warning (10273): Verilog HDL warning at RAM2E-MAX.v(46): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 46
-Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73
-Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189
+Warning (10273): Verilog HDL warning at RAM2E.v(74): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 74
+Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73
+Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189
diff --git a/CPLD/MAXV/output_files/RAM2E.map.summary b/CPLD/MAXV/output_files/RAM2E.map.summary
index e2665d6..83dcb8d 100644
--- a/CPLD/MAXV/output_files/RAM2E.map.summary
+++ b/CPLD/MAXV/output_files/RAM2E.map.summary
@@ -1,9 +1,9 @@
-Analysis & Synthesis Status : Successful - Thu Sep 21 05:34:33 2023
-Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Analysis & Synthesis Status : Successful - Thu Dec 28 23:09:40 2023
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 Revision Name : RAM2E
 Top-level Entity Name : RAM2E
 Family : MAX V
-Total logic elements : 205
+Total logic elements : 244
 Total pins : 70
 Total virtual pins : 0
 UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD/MAXV/output_files/RAM2E.pin b/CPLD/MAXV/output_files/RAM2E.pin
index e88a551..2236865 100644
--- a/CPLD/MAXV/output_files/RAM2E.pin
+++ b/CPLD/MAXV/output_files/RAM2E.pin
@@ -58,41 +58,41 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 CHIP  "RAM2E"  ASSIGNED TO AN: 5M240ZT100C5
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
 -------------------------------------------------------------------------------------------------------------
 GND                          : 1         : gnd    :                   :         :           :                
-nRWE                         : 2         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nCAS                         : 3         : output : 3.3-V LVCMOS      :         : 1         : Y              
-CKE                          : 4         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRAS                         : 5         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nRWEout                      : 2         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nCASout                      : 3         : output : 3.3-V LVCMOS      :         : 1         : Y              
+CKEout                       : 4         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nRASout                      : 5         : output : 3.3-V LVCMOS      :         : 1         : Y              
 BA[0]                        : 6         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[11]                       : 7         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nCS                          : 8         : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[11]                    : 7         : output : 3.3-V LVCMOS      :         : 1         : Y              
+nCSout                       : 8         : output : 3.3-V LVCMOS      :         : 1         : Y              
 VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
 GND                          : 10        : gnd    :                   :         :           :                
 GND                          : 11        : gnd    :                   :         :           :                
 C14M                         : 12        : input  : 3.3-V LVCMOS      :         : 1         : Y              
 VCCINT                       : 13        : power  :                   : 1.8V    :           :                
 BA[1]                        : 14        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[9]                        : 15        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[10]                       : 16        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[8]                        : 17        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[0]                        : 18        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[7]                        : 19        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[1]                        : 20        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[6]                        : 21        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[9]                     : 15        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[10]                    : 16        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[8]                     : 17        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[0]                     : 18        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[7]                     : 19        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[1]                     : 20        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[6]                     : 21        : output : 3.3-V LVCMOS      :         : 1         : Y              
 TMS                          : 22        : input  :                   :         : 1         :                
 TDI                          : 23        : input  :                   :         : 1         :                
 TCK                          : 24        : input  :                   :         : 1         :                
 TDO                          : 25        : output :                   :         : 1         :                
-RA[4]                        : 26        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[3]                        : 27        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[4]                     : 26        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[3]                     : 27        : output : 3.3-V LVCMOS      :         : 1         : Y              
 nEN80                        : 28        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-RA[5]                        : 29        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[2]                        : 30        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[5]                     : 29        : output : 3.3-V LVCMOS      :         : 1         : Y              
+RAout[2]                     : 30        : output : 3.3-V LVCMOS      :         : 1         : Y              
 VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
 GND                          : 32        : gnd    :                   :         :           :                
 nWE80                        : 33        : input  : 3.3-V LVCMOS      :         : 1         : Y              
diff --git a/CPLD/MAXV/output_files/RAM2E.pof b/CPLD/MAXV/output_files/RAM2E.pof
index 18142e9d8dd91f0f9c92103fb47779487b7028f2..bebf2bcd3462d040b0297a0171971d41474f1f18 100644
GIT binary patch
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diff --git a/CPLD/MAXV/output_files/RAM2E.sta.rpt b/CPLD/MAXV/output_files/RAM2E.sta.rpt
index c0e33ea..d19a1c7 100644
--- a/CPLD/MAXV/output_files/RAM2E.sta.rpt
+++ b/CPLD/MAXV/output_files/RAM2E.sta.rpt
@@ -1,6 +1,6 @@
 Timing Analyzer report for RAM2E
-Thu Sep 21 05:34:46 2023
-Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Thu Dec 28 23:09:52 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
 
 
 ---------------------
@@ -17,11 +17,11 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
   9. Recovery Summary
  10. Removal Summary
  11. Minimum Pulse Width Summary
- 12. Setup: 'DRCLK'
- 13. Setup: 'ARCLK'
+ 12. Setup: 'ram2e_ufm|DRCLK|regout'
+ 13. Setup: 'ram2e_ufm|ARCLK|regout'
  14. Setup: 'C14M'
- 15. Hold: 'ARCLK'
- 16. Hold: 'DRCLK'
+ 15. Hold: 'ram2e_ufm|DRCLK|regout'
+ 16. Hold: 'ram2e_ufm|ARCLK|regout'
  17. Hold: 'C14M'
  18. Setup Transfers
  19. Hold Transfers
@@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.
 
 
 
-+-----------------------------------------------------------------------------+
-; Timing Analyzer Summary                                                     ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
-; Timing Analyzer       ; Legacy Timing Analyzer                              ;
-; Revision Name         ; RAM2E                                               ;
-; Device Family         ; MAX V                                               ;
-; Device Name           ; 5M240ZT100C5                                        ;
-; Timing Models         ; Final                                               ;
-; Delay Model           ; Slow Model                                          ;
-; Rise/Fall Delays      ; Unavailable                                         ;
-+-----------------------+-----------------------------------------------------+
++---------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                                     ;
++-----------------------+---------------------------------------------------------------------+
+; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
+; Timing Analyzer       ; Legacy Timing Analyzer                                              ;
+; Revision Name         ; RAM2E                                                               ;
+; Device Family         ; MAX V                                                               ;
+; Device Name           ; 5M240ZT100C5                                                        ;
+; Timing Models         ; Final                                                               ;
+; Delay Model           ; Slow Model                                                          ;
+; Rise/Fall Delays      ; Unavailable                                                         ;
++-----------------------+---------------------------------------------------------------------+
 
 
 +------------------------------------------+
@@ -93,54 +93,54 @@ https://fpgasoftware.intel.com/eula.
 +------------------+--------+--------------------------+
 ; SDC File Path    ; Status ; Read at                  ;
 +------------------+--------+--------------------------+
-; ../RAM2E.sdc     ; OK     ; Thu Sep 21 05:34:45 2023 ;
-; ../RAM2E-MAX.sdc ; OK     ; Thu Sep 21 05:34:45 2023 ;
+; ../RAM2E.sdc     ; OK     ; Thu Dec 28 23:09:51 2023 ;
+; ../RAM2E-MAX.sdc ; OK     ; Thu Dec 28 23:09:51 2023 ;
 +------------------+--------+--------------------------+
 
 
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                              ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; Clock Name ; Type ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets   ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; ARCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ARCLK } ;
-; C14M       ; Base ; 69.841  ; 14.32 MHz ; 0.000 ; 34.920  ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { C14M }  ;
-; DRCLK      ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DRCLK } ;
-+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                           ;
++------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
+; Clock Name             ; Type ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                    ;
++------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
+; C14M                   ; Base ; 69.841  ; 14.32 MHz ; 0.000 ; 34.920  ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { C14M }                   ;
+; ram2e_ufm|ARCLK|regout ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ram2e_ufm|ARCLK|regout } ;
+; ram2e_ufm|DRCLK|regout ; Base ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ram2e_ufm|DRCLK|regout } ;
++------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
 
 
-+-------------------------------------------------+
-; Fmax Summary                                    ;
-+-----------+-----------------+------------+------+
-; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
-+-----------+-----------------+------------+------+
-; 10.0 MHz  ; 10.0 MHz        ; ARCLK      ;      ;
-; 10.0 MHz  ; 10.0 MHz        ; DRCLK      ;      ;
-; 25.52 MHz ; 25.52 MHz       ; C14M       ;      ;
-+-----------+-----------------+------------+------+
++-------------------------------------------------------------+
+; Fmax Summary                                                ;
++-----------+-----------------+------------------------+------+
+; Fmax      ; Restricted Fmax ; Clock Name             ; Note ;
++-----------+-----------------+------------------------+------+
+; 10.0 MHz  ; 10.0 MHz        ; ram2e_ufm|ARCLK|regout ;      ;
+; 10.0 MHz  ; 10.0 MHz        ; ram2e_ufm|DRCLK|regout ;      ;
+; 27.71 MHz ; 27.71 MHz       ; C14M                   ;      ;
++-----------+-----------------+------------------------+------+
 This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
 
 
-+---------------------------------+
-; Setup Summary                   ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; DRCLK ; -24.019 ; -24.019       ;
-; ARCLK ; -23.863 ; -23.863       ;
-; C14M  ; -15.767 ; -176.992      ;
-+-------+---------+---------------+
++--------------------------------------------------+
+; Setup Summary                                    ;
++------------------------+---------+---------------+
+; Clock                  ; Slack   ; End Point TNS ;
++------------------------+---------+---------------+
+; ram2e_ufm|DRCLK|regout ; -25.451 ; -25.451       ;
+; ram2e_ufm|ARCLK|regout ; -25.441 ; -25.441       ;
+; C14M                   ; -20.081 ; -208.886      ;
++------------------------+---------+---------------+
 
 
-+---------------------------------+
-; Hold Summary                    ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; ARCLK ; -16.136 ; -16.136       ;
-; DRCLK ; -15.980 ; -15.980       ;
-; C14M  ; 2.440   ; 0.000         ;
-+-------+---------+---------------+
++--------------------------------------------------+
+; Hold Summary                                     ;
++------------------------+---------+---------------+
+; Clock                  ; Slack   ; End Point TNS ;
++------------------------+---------+---------------+
+; ram2e_ufm|DRCLK|regout ; -14.567 ; -14.567       ;
+; ram2e_ufm|ARCLK|regout ; -14.558 ; -14.558       ;
+; C14M                   ; 3.133   ; 0.000         ;
++------------------------+---------+---------------+
 
 
 --------------------
@@ -155,302 +155,302 @@ No paths to report.
 No paths to report.
 
 
-+--------------------------------+
-; Minimum Pulse Width Summary    ;
-+-------+--------+---------------+
-; Clock ; Slack  ; End Point TNS ;
-+-------+--------+---------------+
-; C14M  ; 34.581 ; 0.000         ;
-; ARCLK ; 70.000 ; 0.000         ;
-; DRCLK ; 70.000 ; 0.000         ;
-+-------+--------+---------------+
++-------------------------------------------------+
+; Minimum Pulse Width Summary                     ;
++------------------------+--------+---------------+
+; Clock                  ; Slack  ; End Point TNS ;
++------------------------+--------+---------------+
+; C14M                   ; 34.581 ; 0.000         ;
+; ram2e_ufm|ARCLK|regout ; 70.000 ; 0.000         ;
+; ram2e_ufm|DRCLK|regout ; 70.000 ; 0.000         ;
++------------------------+--------+---------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'DRCLK'                                                                                                                                                                                                                                                            ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -24.019 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M         ; DRCLK       ; 0.001        ; -1.057     ; 2.963      ;
-; -24.019 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M         ; DRCLK       ; 0.001        ; -1.057     ; 2.963      ;
-; 100.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 200.000      ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'ram2e_ufm|DRCLK|regout'                                                                                                                                                                                                                                                                                                        ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                                       ; To Node                                                                                                         ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; -25.451 ; RAM2E_UFM:ram2e_ufm|DRShift                                                                                     ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M                   ; ram2e_ufm|DRCLK|regout ; 0.001        ; -0.970     ; 4.482      ;
+; -25.432 ; RAM2E_UFM:ram2e_ufm|DRDIn                                                                                       ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M                   ; ram2e_ufm|DRCLK|regout ; 0.001        ; -0.970     ; 4.463      ;
+; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000      ; 0.000      ; 80.000     ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'ARCLK'                                                                                                                                                                                                                                                                                    ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -23.863 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M         ; ARCLK       ; 0.001        ; -0.901     ; 2.963      ;
-; 100.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 200.000      ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'ram2e_ufm|ARCLK|regout'                                                                                                                                                                                                                                                                                                                                ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                                                   ; To Node                                                                                                                     ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; -25.441 ; RAM2E_UFM:ram2e_ufm|ARShift                                                                                                 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M                   ; ram2e_ufm|ARCLK|regout ; 0.001        ; -0.977     ; 4.465      ;
+; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000      ; 0.000      ; 80.000     ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
 
 
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'C14M'                                                                                                                                                                              ;
-+---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
-; -15.767 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMReqErase  ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 16.504     ;
-; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[4]    ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 15.952     ;
-; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[5]    ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 15.952     ;
-; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[7]    ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 15.952     ;
-; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[0]    ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 15.952     ;
-; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[1]    ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 15.952     ;
-; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[2]    ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 15.952     ;
-; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[3]    ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 15.952     ;
-; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[6]    ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 15.952     ;
-; -14.411 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; LEDEN        ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 15.148     ;
-; -13.177 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMInitDone  ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 13.914     ;
-; -11.917 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMD[8]      ; DRCLK        ; C14M        ; 0.001        ; 1.057      ; 12.654     ;
-; 16.803  ; S[1]                                                                                        ; Dout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 17.796     ;
-; 16.803  ; S[1]                                                                                        ; Dout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 17.796     ;
-; 16.803  ; S[1]                                                                                        ; Dout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 17.796     ;
-; 16.803  ; S[1]                                                                                        ; Dout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 17.796     ;
-; 16.803  ; S[1]                                                                                        ; Dout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 17.796     ;
-; 16.803  ; S[1]                                                                                        ; Dout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 17.796     ;
-; 16.806  ; S[1]                                                                                        ; Dout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 17.793     ;
-; 16.809  ; S[1]                                                                                        ; Dout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 17.790     ;
-; 18.727  ; S[2]                                                                                        ; Dout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.872     ;
-; 18.727  ; S[2]                                                                                        ; Dout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.872     ;
-; 18.727  ; S[2]                                                                                        ; Dout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.872     ;
-; 18.727  ; S[2]                                                                                        ; Dout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.872     ;
-; 18.727  ; S[2]                                                                                        ; Dout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.872     ;
-; 18.727  ; S[2]                                                                                        ; Dout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.872     ;
-; 18.730  ; S[2]                                                                                        ; Dout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.869     ;
-; 18.733  ; S[2]                                                                                        ; Dout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.866     ;
-; 19.149  ; S[3]                                                                                        ; Vout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.450     ;
-; 19.149  ; S[3]                                                                                        ; Vout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.450     ;
-; 19.196  ; S[3]                                                                                        ; Vout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.403     ;
-; 19.196  ; S[3]                                                                                        ; Vout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.403     ;
-; 19.196  ; S[3]                                                                                        ; Vout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.403     ;
-; 19.260  ; S[0]                                                                                        ; Vout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.339     ;
-; 19.260  ; S[0]                                                                                        ; Vout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.339     ;
-; 19.307  ; S[0]                                                                                        ; Vout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.292     ;
-; 19.307  ; S[0]                                                                                        ; Vout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.292     ;
-; 19.307  ; S[0]                                                                                        ; Vout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 15.292     ;
-; 20.893  ; S[0]                                                                                        ; Dout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 13.706     ;
-; 20.893  ; S[0]                                                                                        ; Dout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 13.706     ;
-; 20.893  ; S[0]                                                                                        ; Dout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 13.706     ;
-; 20.893  ; S[0]                                                                                        ; Dout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 13.706     ;
-; 20.893  ; S[0]                                                                                        ; Dout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 13.706     ;
-; 20.893  ; S[0]                                                                                        ; Dout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 13.706     ;
-; 20.896  ; S[0]                                                                                        ; Dout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 13.703     ;
-; 20.899  ; S[0]                                                                                        ; Dout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 13.700     ;
-; 22.101  ; S[3]                                                                                        ; Vout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 12.498     ;
-; 22.101  ; S[3]                                                                                        ; Vout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 12.498     ;
-; 22.101  ; S[3]                                                                                        ; Vout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 12.498     ;
-; 22.212  ; S[0]                                                                                        ; Vout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 12.387     ;
-; 22.212  ; S[0]                                                                                        ; Vout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 12.387     ;
-; 22.212  ; S[0]                                                                                        ; Vout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 12.387     ;
-; 23.092  ; S[3]                                                                                        ; Dout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 11.507     ;
-; 23.092  ; S[3]                                                                                        ; Dout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 11.507     ;
-; 23.092  ; S[3]                                                                                        ; Dout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 11.507     ;
-; 23.092  ; S[3]                                                                                        ; Dout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 11.507     ;
-; 23.092  ; S[3]                                                                                        ; Dout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 11.507     ;
-; 23.092  ; S[3]                                                                                        ; Dout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 11.507     ;
-; 23.095  ; S[3]                                                                                        ; Dout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 11.504     ;
-; 23.098  ; S[3]                                                                                        ; Dout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 11.501     ;
-; 23.710  ; S[1]                                                                                        ; Vout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 10.889     ;
-; 23.710  ; S[1]                                                                                        ; Vout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 10.889     ;
-; 23.757  ; S[1]                                                                                        ; Vout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 10.842     ;
-; 23.757  ; S[1]                                                                                        ; Vout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 10.842     ;
-; 23.757  ; S[1]                                                                                        ; Vout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 10.842     ;
-; 24.349  ; S[2]                                                                                        ; Vout[0]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 10.250     ;
-; 24.349  ; S[2]                                                                                        ; Vout[4]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 10.250     ;
-; 24.396  ; S[2]                                                                                        ; Vout[1]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 10.203     ;
-; 24.396  ; S[2]                                                                                        ; Vout[2]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 10.203     ;
-; 24.396  ; S[2]                                                                                        ; Vout[5]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 10.203     ;
-; 26.662  ; S[1]                                                                                        ; Vout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.937      ;
-; 26.662  ; S[1]                                                                                        ; Vout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.937      ;
-; 26.662  ; S[1]                                                                                        ; Vout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.937      ;
-; 27.301  ; S[2]                                                                                        ; Vout[3]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.298      ;
-; 27.301  ; S[2]                                                                                        ; Vout[6]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.298      ;
-; 27.301  ; S[2]                                                                                        ; Vout[7]~reg0 ; C14M         ; C14M        ; 34.920       ; 0.000      ; 7.298      ;
-; 30.659  ; FS[15]                                                                                      ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 38.861     ;
-; 31.593  ; FS[14]                                                                                      ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 37.927     ;
-; 32.392  ; FS[15]                                                                                      ; nCS~reg0     ; C14M         ; C14M        ; 69.841       ; 0.000      ; 37.128     ;
-; 32.513  ; FS[2]                                                                                       ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 37.007     ;
-; 33.326  ; FS[14]                                                                                      ; nCS~reg0     ; C14M         ; C14M        ; 69.841       ; 0.000      ; 36.194     ;
-; 33.452  ; FS[15]                                                                                      ; nCAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 36.068     ;
-; 33.715  ; S[1]                                                                                        ; CmdEraseMAX  ; C14M         ; C14M        ; 69.841       ; 0.000      ; 35.805     ;
-; 34.111  ; FS[1]                                                                                       ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 35.409     ;
-; 34.246  ; FS[2]                                                                                       ; nCS~reg0     ; C14M         ; C14M        ; 69.841       ; 0.000      ; 35.274     ;
-; 34.386  ; FS[14]                                                                                      ; nCAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 35.134     ;
-; 35.112  ; FS[11]                                                                                      ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 34.408     ;
-; 35.288  ; FS[10]                                                                                      ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 34.232     ;
-; 35.392  ; S[1]                                                                                        ; CmdPrgmMAX   ; C14M         ; C14M        ; 69.841       ; 0.000      ; 34.128     ;
-; 35.639  ; S[2]                                                                                        ; CmdEraseMAX  ; C14M         ; C14M        ; 69.841       ; 0.000      ; 33.881     ;
-; 35.844  ; FS[1]                                                                                       ; nCS~reg0     ; C14M         ; C14M        ; 69.841       ; 0.000      ; 33.676     ;
-; 36.147  ; FS[8]                                                                                       ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 33.373     ;
-; 36.765  ; FS[9]                                                                                       ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 32.755     ;
-; 36.845  ; FS[11]                                                                                      ; nCS~reg0     ; C14M         ; C14M        ; 69.841       ; 0.000      ; 32.675     ;
-; 37.021  ; FS[10]                                                                                      ; nCS~reg0     ; C14M         ; C14M        ; 69.841       ; 0.000      ; 32.499     ;
-; 37.152  ; FS[4]                                                                                       ; nRAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 32.368     ;
-; 37.316  ; S[2]                                                                                        ; CmdPrgmMAX   ; C14M         ; C14M        ; 69.841       ; 0.000      ; 32.204     ;
-; 37.805  ; S[0]                                                                                        ; CmdEraseMAX  ; C14M         ; C14M        ; 69.841       ; 0.000      ; 31.715     ;
-; 37.880  ; FS[8]                                                                                       ; nCS~reg0     ; C14M         ; C14M        ; 69.841       ; 0.000      ; 31.640     ;
-; 37.905  ; FS[11]                                                                                      ; nCAS~reg0    ; C14M         ; C14M        ; 69.841       ; 0.000      ; 31.615     ;
-+---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'C14M'                                                                                                                                                                                                                                ;
++---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                                       ; To Node                          ; Launch Clock           ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
+; -20.081 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase  ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 20.731     ;
+; -18.769 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0]    ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 19.419     ;
+; -18.109 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone  ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 18.759     ;
+; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5]    ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 18.234     ;
+; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6]    ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 18.234     ;
+; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1]    ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 18.234     ;
+; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7]    ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 18.234     ;
+; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2]    ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 18.234     ;
+; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3]    ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 18.234     ;
+; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4]    ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 18.234     ;
+; -16.915 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN        ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 17.565     ;
+; -11.924 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8]      ; ram2e_ufm|DRCLK|regout ; C14M        ; 0.001        ; 0.970      ; 12.574     ;
+; 25.780  ; RA[5]                                                                                                           ; RAout[5]~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 8.819      ;
+; 26.401  ; RA[0]                                                                                                           ; RAout[0]~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 8.198      ;
+; 27.872  ; RA[10]                                                                                                          ; RAout[10]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 6.727      ;
+; 28.323  ; CKE                                                                                                             ; CKEout~reg0                      ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 6.276      ;
+; 28.531  ; RA[8]                                                                                                           ; RAout[8]~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 6.068      ;
+; 28.539  ; RA[11]                                                                                                          ; RAout[11]~reg0                   ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 6.060      ;
+; 28.589  ; RA[9]                                                                                                           ; RAout[9]~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 6.010      ;
+; 30.107  ; RA[7]                                                                                                           ; RAout[7]~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 4.492      ;
+; 30.133  ; nRWE                                                                                                            ; nRWEout~reg0                     ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 4.466      ;
+; 30.360  ; nRAS                                                                                                            ; nRASout~reg0                     ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 4.239      ;
+; 30.365  ; nCAS                                                                                                            ; nCASout~reg0                     ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 4.234      ;
+; 30.369  ; RA[1]                                                                                                           ; RAout[1]~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 4.230      ;
+; 30.392  ; RA[6]                                                                                                           ; RAout[6]~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 4.207      ;
+; 31.173  ; RA[3]                                                                                                           ; RAout[3]~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 3.426      ;
+; 31.207  ; RA[2]                                                                                                           ; RAout[2]~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 3.392      ;
+; 31.456  ; RA[4]                                                                                                           ; RAout[4]~reg0                    ; C14M                   ; C14M        ; 34.920       ; 0.000      ; 3.143      ;
+; 33.754  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[11]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.766     ;
+; 33.754  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[9]      ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.766     ;
+; 33.754  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[10]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.766     ;
+; 33.754  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[8]      ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.766     ;
+; 33.754  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[13]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.766     ;
+; 33.754  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[14]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.766     ;
+; 33.754  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[15]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.766     ;
+; 33.754  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[12]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.766     ;
+; 34.170  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[11]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.350     ;
+; 34.170  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[9]      ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.350     ;
+; 34.170  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[10]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.350     ;
+; 34.170  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[8]      ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.350     ;
+; 34.170  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[13]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.350     ;
+; 34.170  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[14]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.350     ;
+; 34.170  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[15]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.350     ;
+; 34.170  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[12]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 35.350     ;
+; 35.281  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[11]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 34.239     ;
+; 35.281  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[9]      ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 34.239     ;
+; 35.281  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[10]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 34.239     ;
+; 35.281  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[8]      ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 34.239     ;
+; 35.281  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[13]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 34.239     ;
+; 35.281  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[14]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 34.239     ;
+; 35.281  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[15]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 34.239     ;
+; 35.281  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMD[12]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 34.239     ;
+; 37.521  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMErase     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 31.999     ;
+; 37.937  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMErase     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 31.583     ;
+; 39.048  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMErase     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 30.472     ;
+; 40.235  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMProgram   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 29.285     ;
+; 40.239  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 29.281     ;
+; 40.355  ; S[1]                                                                                                            ; RAM2E_UFM:ram2e_ufm|DRCLK        ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 29.165     ;
+; 40.651  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMProgram   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 28.869     ;
+; 40.655  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 28.865     ;
+; 40.771  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|DRCLK        ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 28.749     ;
+; 41.239  ; FS[15]                                                                                                          ; nCAS                             ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 28.281     ;
+; 41.532  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[0]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 27.988     ;
+; 41.557  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[0]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 27.963     ;
+; 41.762  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMProgram   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 27.758     ;
+; 41.766  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 27.754     ;
+; 41.808  ; FS[15]                                                                                                          ; RAM2E_UFM:ram2e_ufm|RWMask[0]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 27.712     ;
+; 41.882  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|DRCLK        ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 27.638     ;
+; 41.904  ; FS[13]                                                                                                          ; RAM2E_UFM:ram2e_ufm|RWMask[0]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 27.616     ;
+; 42.244  ; CS[0]                                                                                                           ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 27.276     ;
+; 42.246  ; CS[0]                                                                                                           ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX  ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 27.274     ;
+; 42.482  ; FS[15]                                                                                                          ; nRAS                             ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 27.038     ;
+; 42.717  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[5]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.803     ;
+; 42.717  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[6]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.803     ;
+; 42.717  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[1]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.803     ;
+; 42.717  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[7]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.803     ;
+; 42.717  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[2]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.803     ;
+; 42.717  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[3]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.803     ;
+; 42.717  ; S[3]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[4]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.803     ;
+; 42.742  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[5]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.778     ;
+; 42.742  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[6]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.778     ;
+; 42.742  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[1]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.778     ;
+; 42.742  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[7]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.778     ;
+; 42.742  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[2]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.778     ;
+; 42.742  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[3]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.778     ;
+; 42.742  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|RWMask[4]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.778     ;
+; 42.780  ; RAM2E_UFM:ram2e_ufm|UFMInitDone                                                                                 ; RAM2E_UFM:ram2e_ufm|RWMask[0]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.740     ;
+; 42.842  ; S[2]                                                                                                            ; RAM2E_UFM:ram2e_ufm|RWMask[0]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.678     ;
+; 42.988  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[11]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.532     ;
+; 42.988  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[9]      ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.532     ;
+; 42.988  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[10]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.532     ;
+; 42.988  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[8]      ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.532     ;
+; 42.988  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[13]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.532     ;
+; 42.988  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[14]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.532     ;
+; 42.988  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[15]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.532     ;
+; 42.988  ; FS[2]                                                                                                           ; RAM2E_UFM:ram2e_ufm|UFMD[12]     ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.532     ;
+; 42.991  ; FS[0]                                                                                                           ; nCAS                             ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.529     ;
+; 42.993  ; FS[15]                                                                                                          ; RAM2E_UFM:ram2e_ufm|RWMask[5]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.527     ;
+; 42.993  ; FS[15]                                                                                                          ; RAM2E_UFM:ram2e_ufm|RWMask[6]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.527     ;
+; 42.993  ; FS[15]                                                                                                          ; RAM2E_UFM:ram2e_ufm|RWMask[1]    ; C14M                   ; C14M        ; 69.841       ; 0.000      ; 26.527     ;
++---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'ARCLK'                                                                                                                                                                                                                                                                                     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.136 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M         ; ARCLK       ; 0.000        ; -0.901     ; 2.963      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'ram2e_ufm|DRCLK|regout'                                                                                                                                                                                                                                                                                                         ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                                       ; To Node                                                                                                         ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; -14.567 ; RAM2E_UFM:ram2e_ufm|DRDIn                                                                                       ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M                   ; ram2e_ufm|DRCLK|regout ; 0.000        ; -0.970     ; 4.463      ;
+; -14.548 ; RAM2E_UFM:ram2e_ufm|DRShift                                                                                     ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M                   ; ram2e_ufm|DRCLK|regout ; 0.000        ; -0.970     ; 4.482      ;
+; 60.000  ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000        ; 0.000      ; 80.000     ;
++---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'DRCLK'                                                                                                                                                                                                                                                             ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -15.980 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M         ; DRCLK       ; 0.000        ; -1.057     ; 2.963      ;
-; -15.980 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M         ; DRCLK       ; 0.000        ; -1.057     ; 2.963      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'ram2e_ufm|ARCLK|regout'                                                                                                                                                                                                                                                                                                                                 ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack   ; From Node                                                                                                                   ; To Node                                                                                                                     ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+; -14.558 ; RAM2E_UFM:ram2e_ufm|ARShift                                                                                                 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M                   ; ram2e_ufm|ARCLK|regout ; 0.000        ; -0.977     ; 4.465      ;
+; 60.000  ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000        ; 0.000      ; 80.000     ;
++---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
 
 
-+-----------------------------------------------------------------------------------------------------------------+
-; Hold: 'C14M'                                                                                                    ;
-+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node     ; To Node           ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
-; 2.440 ; UFMBusyReg    ; UFMErase          ; C14M         ; C14M        ; 0.000        ; 0.000      ; 2.479      ;
-; 3.130 ; UFMD[12]      ; UFMD[13]          ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.169      ;
-; 3.153 ; UFMD[9]       ; UFMD[10]          ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.192      ;
-; 3.166 ; UFMD[14]      ; UFMD[15]          ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.205      ;
-; 3.170 ; UFMD[13]      ; UFMD[14]          ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.209      ;
-; 3.385 ; UFMD[10]      ; UFMD[11]          ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.424      ;
-; 3.414 ; FS[0]         ; FS[0]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.453      ;
-; 3.442 ; CmdEraseMAX   ; CmdEraseMAX       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.481      ;
-; 3.443 ; S[2]          ; S[2]              ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.482      ;
-; 3.451 ; S[2]          ; DOEEN             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.490      ;
-; 3.451 ; CmdTout[0]    ; CmdTout[0]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.490      ;
-; 3.453 ; CmdTout[0]    ; CmdTout[1]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.492      ;
-; 3.454 ; CmdTout[0]    ; CmdTout[2]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.493      ;
-; 3.528 ; CS[0]         ; CS[0]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.567      ;
-; 3.538 ; CS[0]         ; CS[1]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.577      ;
-; 3.740 ; S[0]          ; S[0]              ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.779      ;
-; 3.740 ; DRDIn         ; DRDIn             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.779      ;
-; 3.741 ; RTPBusyReg    ; UFMErase          ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.780      ;
-; 3.779 ; RWSel         ; RWSel             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.818      ;
-; 3.810 ; S[1]          ; S[1]              ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.849      ;
-; 3.827 ; CmdPrgmMAX    ; UFMProgram        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.866      ;
-; 3.831 ; S[1]          ; DOEEN             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.870      ;
-; 3.833 ; CmdTout[1]    ; CmdTout[1]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.872      ;
-; 3.839 ; CmdTout[1]    ; CmdTout[2]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.878      ;
-; 3.843 ; CS[2]         ; CS[2]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.882      ;
-; 4.011 ; PHI1reg       ; S[0]              ; C14M         ; C14M        ; 0.000        ; 0.000      ; 4.050      ;
-; 4.210 ; UFMD[8]       ; UFMD[9]           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 4.249      ;
-; 4.278 ; CmdEraseMAX   ; UFMErase          ; C14M         ; C14M        ; 0.000        ; 0.000      ; 4.317      ;
-; 4.279 ; UFMD[11]      ; UFMD[12]          ; C14M         ; C14M        ; 0.000        ; 0.000      ; 4.318      ;
-; 5.056 ; RTPBusyReg    ; UFMProgram        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.095      ;
-; 5.228 ; LEDEN         ; LEDEN             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.267      ;
-; 5.241 ; FS[15]        ; FS[15]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.280      ;
-; 5.243 ; FS[5]         ; FS[5]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.282      ;
-; 5.252 ; FS[8]         ; FS[8]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.291      ;
-; 5.268 ; Ready         ; Ready             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.307      ;
-; 5.272 ; FS[7]         ; FS[7]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.311      ;
-; 5.278 ; FS[10]        ; FS[10]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.317      ;
-; 5.281 ; FS[9]         ; FS[9]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.320      ;
-; 5.286 ; CmdPrgmMAX    ; CmdPrgmMAX        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.325      ;
-; 5.360 ; CS[1]         ; CS[1]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.399      ;
-; 5.361 ; CS[1]         ; CS[2]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.400      ;
-; 5.440 ; FS[3]         ; FS[3]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.479      ;
-; 5.441 ; FS[4]         ; FS[4]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.480      ;
-; 5.441 ; FS[2]         ; FS[2]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.480      ;
-; 5.442 ; FS[11]        ; FS[11]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.481      ;
-; 5.452 ; FS[1]         ; FS[1]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.491      ;
-; 5.464 ; FS[14]        ; FS[14]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.503      ;
-; 5.473 ; UFMErase      ; UFMErase          ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.512      ;
-; 5.474 ; UFMProgram    ; UFMProgram        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.513      ;
-; 5.475 ; FS[13]        ; FS[13]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.514      ;
-; 5.476 ; FS[12]        ; FS[12]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.515      ;
-; 5.476 ; FS[6]         ; FS[6]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.515      ;
-; 5.478 ; UFMInitDone   ; UFMInitDone       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.517      ;
-; 5.486 ; CmdTout[2]    ; CmdTout[2]        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.525      ;
-; 5.541 ; S[3]          ; S[3]              ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.580      ;
-; 5.613 ; CS[0]         ; CS[2]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.652      ;
-; 5.664 ; RWBank[2]     ; RA[10]~reg0       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.703      ;
-; 5.753 ; CmdPrgmMAX    ; UFMErase          ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.792      ;
-; 5.978 ; FS[5]         ; FS[6]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.017      ;
-; 5.987 ; FS[8]         ; FS[9]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.026      ;
-; 6.013 ; FS[10]        ; FS[11]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.052      ;
-; 6.016 ; FS[9]         ; FS[10]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.055      ;
-; 6.122 ; FS[5]         ; FS[7]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.161      ;
-; 6.131 ; FS[8]         ; FS[10]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.170      ;
-; 6.157 ; FS[10]        ; FS[12]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.196      ;
-; 6.160 ; FS[9]         ; FS[11]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.199      ;
-; 6.229 ; DRCLKPulse    ; DRCLK             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.268      ;
-; 6.275 ; FS[8]         ; FS[11]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.314      ;
-; 6.304 ; FS[9]         ; FS[12]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.343      ;
-; 6.419 ; FS[8]         ; FS[12]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.458      ;
-; 6.442 ; FS[3]         ; FS[4]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.481      ;
-; 6.443 ; FS[4]         ; FS[5]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.482      ;
-; 6.444 ; FS[11]        ; FS[12]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.483      ;
-; 6.454 ; FS[1]         ; FS[2]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.493      ;
-; 6.466 ; FS[14]        ; FS[15]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.505      ;
-; 6.477 ; FS[13]        ; FS[14]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.516      ;
-; 6.478 ; FS[6]         ; FS[7]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.517      ;
-; 6.507 ; RWBank[5]     ; BA[1]~reg0        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.546      ;
-; 6.533 ; CmdBitbangMAX ; DRCLKPulse        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.572      ;
-; 6.586 ; FS[3]         ; FS[5]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.625      ;
-; 6.587 ; FS[4]         ; FS[6]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.626      ;
-; 6.621 ; FS[13]        ; FS[15]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.660      ;
-; 6.651 ; UFMD[11]      ; RWMask[3]         ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.690      ;
-; 6.724 ; RWMask[4]     ; RWBank[4]         ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.763      ;
-; 6.730 ; FS[3]         ; FS[6]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.769      ;
-; 6.731 ; FS[4]         ; FS[7]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.770      ;
-; 6.774 ; RWMask[3]     ; RWBank[3]         ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.813      ;
-; 6.793 ; FS[10]        ; FS[13]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.832      ;
-; 6.793 ; FS[10]        ; FS[14]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.832      ;
-; 6.793 ; FS[10]        ; FS[15]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.832      ;
-; 6.816 ; UFMD[15]      ; RWMask[7]         ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.855      ;
-; 6.836 ; CS[0]         ; CmdRWMaskSet      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.875      ;
-; 6.843 ; CS[0]         ; CmdSetRWBankFFLED ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.882      ;
-; 6.874 ; FS[3]         ; FS[7]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.913      ;
-; 6.895 ; CmdEraseMAX   ; UFMProgram        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.934      ;
-; 6.940 ; FS[9]         ; FS[13]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.979      ;
-; 6.940 ; FS[9]         ; FS[14]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.979      ;
-; 6.940 ; FS[9]         ; FS[15]            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.979      ;
-; 6.998 ; FS[2]         ; FS[4]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 7.037      ;
-; 6.998 ; FS[2]         ; FS[3]             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 7.037      ;
-+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'C14M'                                                                                                                                      ;
++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                        ; To Node                          ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
+; 3.133 ; RAM2E_UFM:ram2e_ufm|UFMD[12]     ; RAM2E_UFM:ram2e_ufm|UFMD[13]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.172      ;
+; 3.136 ; RAM2E_UFM:ram2e_ufm|UFMD[8]      ; RAM2E_UFM:ram2e_ufm|UFMD[9]      ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.175      ;
+; 3.429 ; RAM2E_UFM:ram2e_ufm|UFMD[13]     ; RAM2E_UFM:ram2e_ufm|UFMD[14]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.468      ;
+; 3.436 ; RAM2E_UFM:ram2e_ufm|UFMD[10]     ; RAM2E_UFM:ram2e_ufm|UFMD[11]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.475      ;
+; 3.453 ; CmdTout[0]                       ; CmdTout[2]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.492      ;
+; 3.483 ; CS[0]                            ; CS[0]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.522      ;
+; 3.527 ; CS[1]                            ; CS[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.566      ;
+; 3.753 ; RWBank[7]                        ; RA[8]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.792      ;
+; 3.765 ; Ready                            ; Ready                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.804      ;
+; 3.767 ; FS[0]                            ; FS[0]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.806      ;
+; 3.803 ; CmdTout[1]                       ; CmdTout[1]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.842      ;
+; 3.833 ; CS[2]                            ; CS[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.872      ;
+; 3.879 ; RC[2]                            ; RC[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.918      ;
+; 3.883 ; RC[2]                            ; RC[0]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.922      ;
+; 3.885 ; RC[2]                            ; RC[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 3.924      ;
+; 4.002 ; PHI1r                            ; S[0]                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 4.041      ;
+; 4.318 ; RAM2E_UFM:ram2e_ufm|UFMD[11]     ; RAM2E_UFM:ram2e_ufm|UFMD[12]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 4.357      ;
+; 4.629 ; RWSel                            ; RWSel                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 4.668      ;
+; 4.854 ; S[0]                             ; S[0]                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 4.893      ;
+; 4.855 ; S[1]                             ; S[1]                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 4.894      ;
+; 4.859 ; RAM2E_UFM:ram2e_ufm|UFMD[13]     ; RAM2E_UFM:ram2e_ufm|RWMask[5]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 4.898      ;
+; 4.879 ; RAM2E_UFM:ram2e_ufm|UFMD[15]     ; RAM2E_UFM:ram2e_ufm|RWMask[7]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 4.918      ;
+; 5.050 ; RWSel                            ; CmdTout[0]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.089      ;
+; 5.054 ; RWSel                            ; CmdTout[2]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.093      ;
+; 5.156 ; S[2]                             ; DOEEN                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.195      ;
+; 5.163 ; S[2]                             ; VOEEN                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.202      ;
+; 5.217 ; FS[15]                           ; FS[15]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.256      ;
+; 5.217 ; FS[7]                            ; FS[7]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.256      ;
+; 5.228 ; RAM2E_UFM:ram2e_ufm|UFMInitDone  ; RAM2E_UFM:ram2e_ufm|UFMInitDone  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.267      ;
+; 5.229 ; RAM2E_UFM:ram2e_ufm|DRDIn        ; RAM2E_UFM:ram2e_ufm|DRDIn        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.268      ;
+; 5.233 ; RAM2E_UFM:ram2e_ufm|RWMask[0]    ; RWBank[0]                        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.272      ;
+; 5.253 ; FS[9]                            ; FS[9]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.292      ;
+; 5.266 ; FS[5]                            ; FS[5]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.305      ;
+; 5.272 ; RWBank[1]                        ; RA[8]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.311      ;
+; 5.281 ; CmdTout[1]                       ; CmdTout[2]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.320      ;
+; 5.290 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX  ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.329      ;
+; 5.301 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX  ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.340      ;
+; 5.312 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.351      ;
+; 5.313 ; RC[0]                            ; RC[0]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.352      ;
+; 5.315 ; RC[0]                            ; RC[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.354      ;
+; 5.316 ; RC[0]                            ; RC[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.355      ;
+; 5.320 ; CmdTout[0]                       ; CmdTout[0]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.359      ;
+; 5.329 ; CmdTout[0]                       ; CmdTout[1]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.368      ;
+; 5.351 ; S[3]                             ; S[3]                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.390      ;
+; 5.354 ; S[3]                             ; VOEEN                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.393      ;
+; 5.355 ; S[3]                             ; DOEEN                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.394      ;
+; 5.429 ; RAM2E_UFM:ram2e_ufm|UFMProgram   ; RAM2E_UFM:ram2e_ufm|UFMProgram   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.468      ;
+; 5.429 ; RAM2E_UFM:ram2e_ufm|UFMReqErase  ; RAM2E_UFM:ram2e_ufm|UFMReqErase  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.468      ;
+; 5.443 ; FS[1]                            ; FS[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.482      ;
+; 5.443 ; CmdTout[2]                       ; CmdTout[2]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.482      ;
+; 5.449 ; FS[11]                           ; FS[11]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.488      ;
+; 5.452 ; FS[4]                            ; FS[4]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.491      ;
+; 5.452 ; FS[13]                           ; FS[13]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.491      ;
+; 5.453 ; FS[2]                            ; FS[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.492      ;
+; 5.453 ; FS[14]                           ; FS[14]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.492      ;
+; 5.460 ; FS[6]                            ; FS[6]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.499      ;
+; 5.464 ; FS[3]                            ; FS[3]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.503      ;
+; 5.466 ; FS[12]                           ; FS[12]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.505      ;
+; 5.552 ; RC[1]                            ; RC[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.591      ;
+; 5.559 ; RC[1]                            ; RC[0]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.598      ;
+; 5.561 ; CS[0]                            ; CS[1]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.600      ;
+; 5.563 ; RC[1]                            ; RC[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.602      ;
+; 5.564 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.603      ;
+; 5.565 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.604      ;
+; 5.565 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX   ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX  ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.604      ;
+; 5.570 ; S[1]                             ; DOEEN                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.609      ;
+; 5.579 ; S[1]                             ; VOEEN                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.618      ;
+; 5.613 ; CS[1]                            ; CS[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.652      ;
+; 5.884 ; RAM2E_UFM:ram2e_ufm|UFMD[9]      ; RAM2E_UFM:ram2e_ufm|UFMD[10]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 5.923      ;
+; 5.988 ; FS[9]                            ; FS[10]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.027      ;
+; 6.001 ; FS[5]                            ; FS[6]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.040      ;
+; 6.016 ; S[0]                             ; RA[11]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.055      ;
+; 6.132 ; FS[9]                            ; FS[11]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.171      ;
+; 6.145 ; FS[5]                            ; FS[7]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.184      ;
+; 6.276 ; FS[9]                            ; FS[12]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.315      ;
+; 6.315 ; RAM2E_UFM:ram2e_ufm|UFMD[11]     ; RAM2E_UFM:ram2e_ufm|RWMask[3]    ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.354      ;
+; 6.319 ; RAM2E_UFM:ram2e_ufm|RWMask[2]    ; RWBank[2]                        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.358      ;
+; 6.338 ; CS[0]                            ; CS[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.377      ;
+; 6.365 ; FS[8]                            ; FS[8]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.404      ;
+; 6.445 ; FS[1]                            ; FS[2]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.484      ;
+; 6.451 ; FS[11]                           ; FS[12]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.490      ;
+; 6.454 ; FS[4]                            ; FS[5]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.493      ;
+; 6.454 ; FS[13]                           ; FS[14]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.493      ;
+; 6.455 ; FS[14]                           ; FS[15]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.494      ;
+; 6.462 ; FS[6]                            ; FS[7]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.501      ;
+; 6.466 ; FS[3]                            ; FS[4]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.505      ;
+; 6.516 ; RAM2E_UFM:ram2e_ufm|RWMask[6]    ; RWBank[6]                        ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.555      ;
+; 6.536 ; FS[10]                           ; FS[10]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.575      ;
+; 6.567 ; S[3]                             ; CKE                              ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.606      ;
+; 6.598 ; FS[4]                            ; FS[6]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.637      ;
+; 6.598 ; FS[13]                           ; FS[15]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.637      ;
+; 6.610 ; FS[3]                            ; FS[5]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.649      ;
+; 6.627 ; S[2]                             ; S[2]                             ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.666      ;
+; 6.628 ; RA[10]                           ; RA[10]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.667      ;
+; 6.710 ; RAM2E_UFM:ram2e_ufm|UFMD[14]     ; RAM2E_UFM:ram2e_ufm|UFMD[15]     ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.749      ;
+; 6.735 ; RWSel                            ; CmdTout[1]                       ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.774      ;
+; 6.742 ; FS[4]                            ; FS[7]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.781      ;
+; 6.754 ; FS[3]                            ; FS[6]                            ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.793      ;
+; 6.771 ; RWBank[4]                        ; RA[11]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.810      ;
+; 6.787 ; S[0]                             ; RA[10]                           ; C14M         ; C14M        ; 0.000        ; 0.000      ; 6.826      ;
++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
 
 
-+-------------------------------------------------------------------+
-; Setup Transfers                                                   ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; C14M       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; C14M       ; C14M     ; 1607     ; 0        ; 64       ; 0        ;
-; DRCLK      ; C14M     ; 13       ; 0        ; 0        ; 0        ;
-; C14M       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
++---------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                             ;
++------------------------+------------------------+----------+----------+----------+----------+
+; From Clock             ; To Clock               ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------------------+------------------------+----------+----------+----------+----------+
+; C14M                   ; C14M                   ; 1625     ; 0        ; 16       ; 0        ;
+; ram2e_ufm|DRCLK|regout ; C14M                   ; 13       ; 0        ; 0        ; 0        ;
+; C14M                   ; ram2e_ufm|ARCLK|regout ; 1        ; 0        ; 0        ; 0        ;
+; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1        ; 0        ; 0        ; 0        ;
+; C14M                   ; ram2e_ufm|DRCLK|regout ; 2        ; 0        ; 0        ; 0        ;
+; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1        ; 0        ; 0        ; 0        ;
++------------------------+------------------------+----------+----------+----------+----------+
 Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
 
 
-+-------------------------------------------------------------------+
-; Hold Transfers                                                    ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; C14M       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; C14M       ; C14M     ; 1607     ; 0        ; 64       ; 0        ;
-; DRCLK      ; C14M     ; 13       ; 0        ; 0        ; 0        ;
-; C14M       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
++---------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                              ;
++------------------------+------------------------+----------+----------+----------+----------+
+; From Clock             ; To Clock               ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------------------+------------------------+----------+----------+----------+----------+
+; C14M                   ; C14M                   ; 1625     ; 0        ; 16       ; 0        ;
+; ram2e_ufm|DRCLK|regout ; C14M                   ; 13       ; 0        ; 0        ; 0        ;
+; C14M                   ; ram2e_ufm|ARCLK|regout ; 1        ; 0        ; 0        ; 0        ;
+; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1        ; 0        ; 0        ; 0        ;
+; C14M                   ; ram2e_ufm|DRCLK|regout ; 2        ; 0        ; 0        ; 0        ;
+; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1        ; 0        ; 0        ; 0        ;
++------------------------+------------------------+----------+----------+----------+----------+
 Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
 
 
@@ -473,22 +473,22 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +---------------------------------+-------+------+
 ; Illegal Clocks                  ; 0     ; 0    ;
 ; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 29    ; 29   ;
-; Unconstrained Input Port Paths  ; 169   ; 169  ;
-; Unconstrained Output Ports      ; 48    ; 48   ;
-; Unconstrained Output Port Paths ; 67    ; 67   ;
+; Unconstrained Input Ports       ; 28    ; 28   ;
+; Unconstrained Input Port Paths  ; 176   ; 176  ;
+; Unconstrained Output Ports      ; 47    ; 47   ;
+; Unconstrained Output Port Paths ; 76    ; 76   ;
 +---------------------------------+-------+------+
 
 
-+-------------------------------------+
-; Clock Status Summary                ;
-+--------+-------+------+-------------+
-; Target ; Clock ; Type ; Status      ;
-+--------+-------+------+-------------+
-; ARCLK  ; ARCLK ; Base ; Constrained ;
-; C14M   ; C14M  ; Base ; Constrained ;
-; DRCLK  ; DRCLK ; Base ; Constrained ;
-+--------+-------+------+-------------+
++----------------------------------------------------------------------+
+; Clock Status Summary                                                 ;
++------------------------+------------------------+------+-------------+
+; Target                 ; Clock                  ; Type ; Status      ;
++------------------------+------------------------+------+-------------+
+; C14M                   ; C14M                   ; Base ; Constrained ;
+; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; Base ; Constrained ;
+; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; Base ; Constrained ;
++------------------------+------------------------+------+-------------+
 
 
 +---------------------------------------------------------------------------------------------------+
@@ -524,7 +524,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; nC07X      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nEN80      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nWE        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nWE80      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +------------+--------------------------------------------------------------------------------------+
 
 
@@ -535,7 +534,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +-------------+---------------------------------------------------------------------------------------+
 ; BA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; BA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; CKE         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; CKEout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; DQMH        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; DQML        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -547,18 +546,18 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[0]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[1]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[2]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[3]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[4]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[5]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[6]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[7]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[8]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[9]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[10]   ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[11]   ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -575,11 +574,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; Vout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Vout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Vout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCS         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCASout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nDOE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRASout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRWEout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nVOE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +-------------+---------------------------------------------------------------------------------------+
 
@@ -617,7 +615,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; nC07X      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nEN80      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nWE        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nWE80      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +------------+--------------------------------------------------------------------------------------+
 
 
@@ -628,7 +625,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +-------------+---------------------------------------------------------------------------------------+
 ; BA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; BA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; CKE         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; CKEout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; DQMH        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; DQML        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Dout[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -640,18 +637,18 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; Dout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Dout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; LED         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; RA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[0]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[1]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[2]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[3]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[4]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[5]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[6]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[7]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[8]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[9]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[10]   ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RAout[11]   ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -668,11 +665,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; Vout[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Vout[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; Vout[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nCS         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCASout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nDOE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; nRWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRASout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRWEout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; nVOE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +-------------+---------------------------------------------------------------------------------------+
 
@@ -682,8 +678,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +--------------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
-    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
-    Info: Processing started: Thu Sep 21 05:34:43 2023
+    Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
+    Info: Processing started: Thu Dec 28 23:09:49 2023
 Info: Command: quartus_sta RAM2E-MAXV -c RAM2E
 Info: qsta_default_script.tcl version: #1
 Info (20032): Parallel compilation is enabled and will use up to 4 processors
@@ -695,37 +691,37 @@ Info (332104): Reading SDC File: '../RAM2E.sdc'
 Info (332104): Reading SDC File: '../RAM2E-MAX.sdc'
 Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
 Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
-Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
-Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
+Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
+Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
 Critical Warning (332148): Timing requirements not met
-Info (332146): Worst-case setup slack is -24.019
+Info (332146): Worst-case setup slack is -25.451
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):   -24.019             -24.019 DRCLK 
-    Info (332119):   -23.863             -23.863 ARCLK 
-    Info (332119):   -15.767            -176.992 C14M 
-Info (332146): Worst-case hold slack is -16.136
+    Info (332119):   -25.451             -25.451 ram2e_ufm|DRCLK|regout 
+    Info (332119):   -25.441             -25.441 ram2e_ufm|ARCLK|regout 
+    Info (332119):   -20.081            -208.886 C14M 
+Info (332146): Worst-case hold slack is -14.567
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):   -16.136             -16.136 ARCLK 
-    Info (332119):   -15.980             -15.980 DRCLK 
-    Info (332119):     2.440               0.000 C14M 
+    Info (332119):   -14.567             -14.567 ram2e_ufm|DRCLK|regout 
+    Info (332119):   -14.558             -14.558 ram2e_ufm|ARCLK|regout 
+    Info (332119):     3.133               0.000 C14M 
 Info (332140): No Recovery paths to report
 Info (332140): No Removal paths to report
 Info (332146): Worst-case minimum pulse width slack is 34.581
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
     Info (332119):    34.581               0.000 C14M 
-    Info (332119):    70.000               0.000 ARCLK 
-    Info (332119):    70.000               0.000 DRCLK 
+    Info (332119):    70.000               0.000 ram2e_ufm|ARCLK|regout 
+    Info (332119):    70.000               0.000 ram2e_ufm|DRCLK|regout 
 Info (332001): The selected device family is not supported by the report_metastability command.
-Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
-Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
+Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
+Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 13092 megabytes
-    Info: Processing ended: Thu Sep 21 05:34:46 2023
+    Info: Peak virtual memory: 13067 megabytes
+    Info: Processing ended: Thu Dec 28 23:09:52 2023
     Info: Elapsed time: 00:00:03
     Info: Total CPU time (on all processors): 00:00:02
 
diff --git a/CPLD/MAXV/output_files/RAM2E.sta.summary b/CPLD/MAXV/output_files/RAM2E.sta.summary
index 3d31fdf..c1760b6 100644
--- a/CPLD/MAXV/output_files/RAM2E.sta.summary
+++ b/CPLD/MAXV/output_files/RAM2E.sta.summary
@@ -2,39 +2,39 @@
 Timing Analyzer Summary
 ------------------------------------------------------------
 
-Type  : Setup 'DRCLK'
-Slack : -24.019
-TNS   : -24.019
+Type  : Setup 'ram2e_ufm|DRCLK|regout'
+Slack : -25.451
+TNS   : -25.451
 
-Type  : Setup 'ARCLK'
-Slack : -23.863
-TNS   : -23.863
+Type  : Setup 'ram2e_ufm|ARCLK|regout'
+Slack : -25.441
+TNS   : -25.441
 
 Type  : Setup 'C14M'
-Slack : -15.767
-TNS   : -176.992
+Slack : -20.081
+TNS   : -208.886
 
-Type  : Hold 'ARCLK'
-Slack : -16.136
-TNS   : -16.136
+Type  : Hold 'ram2e_ufm|DRCLK|regout'
+Slack : -14.567
+TNS   : -14.567
 
-Type  : Hold 'DRCLK'
-Slack : -15.980
-TNS   : -15.980
+Type  : Hold 'ram2e_ufm|ARCLK|regout'
+Slack : -14.558
+TNS   : -14.558
 
 Type  : Hold 'C14M'
-Slack : 2.440
+Slack : 3.133
 TNS   : 0.000
 
 Type  : Minimum Pulse Width 'C14M'
 Slack : 34.581
 TNS   : 0.000
 
-Type  : Minimum Pulse Width 'ARCLK'
+Type  : Minimum Pulse Width 'ram2e_ufm|ARCLK|regout'
 Slack : 70.000
 TNS   : 0.000
 
-Type  : Minimum Pulse Width 'DRCLK'
+Type  : Minimum Pulse Width 'ram2e_ufm|DRCLK|regout'
 Slack : 70.000
 TNS   : 0.000
 
diff --git a/CPLD/RAM2E-LCMXO2.lpf b/CPLD/RAM2E-LCMXO2.lpf
index ef9437f..635fe6d 100644
--- a/CPLD/RAM2E-LCMXO2.lpf
+++ b/CPLD/RAM2E-LCMXO2.lpf
@@ -23,7 +23,7 @@ LOCATE COMP "nWE" SITE "29" ;
 LOCATE COMP "nWE80" SITE "83" ;
 LOCATE COMP "BA[0]" SITE "58" ;
 LOCATE COMP "BA[1]" SITE "60" ;
-LOCATE COMP "CKE" SITE "53" ;
+LOCATE COMP "CKEout" SITE "53" ;
 LOCATE COMP "DQMH" SITE "49" ;
 LOCATE COMP "DQML" SITE "48" ;
 LOCATE COMP "Dout[0]" SITE "30" ;
@@ -35,18 +35,18 @@ LOCATE COMP "Dout[5]" SITE "21" ;
 LOCATE COMP "Dout[6]" SITE "31" ;
 LOCATE COMP "Dout[7]" SITE "32" ;
 LOCATE COMP "LED" SITE "35" ;
-LOCATE COMP "RA[0]" SITE "66" ;
-LOCATE COMP "RA[1]" SITE "68" ;
-LOCATE COMP "RA[2]" SITE "70" ;
-LOCATE COMP "RA[3]" SITE "74" ;
-LOCATE COMP "RA[4]" SITE "75" ;
-LOCATE COMP "RA[5]" SITE "71" ;
-LOCATE COMP "RA[7]" SITE "67" ;
-LOCATE COMP "RA[6]" SITE "69" ;
-LOCATE COMP "RA[8]" SITE "65" ;
-LOCATE COMP "RA[9]" SITE "63" ;
-LOCATE COMP "RA[10]" SITE "64" ;
-LOCATE COMP "RA[11]" SITE "59" ;
+LOCATE COMP "RAout[0]" SITE "66" ;
+LOCATE COMP "RAout[1]" SITE "68" ;
+LOCATE COMP "RAout[2]" SITE "70" ;
+LOCATE COMP "RAout[3]" SITE "74" ;
+LOCATE COMP "RAout[4]" SITE "75" ;
+LOCATE COMP "RAout[5]" SITE "71" ;
+LOCATE COMP "RAout[7]" SITE "67" ;
+LOCATE COMP "RAout[6]" SITE "69" ;
+LOCATE COMP "RAout[8]" SITE "65" ;
+LOCATE COMP "RAout[9]" SITE "63" ;
+LOCATE COMP "RAout[10]" SITE "64" ;
+LOCATE COMP "RAout[11]" SITE "59" ;
 LOCATE COMP "Vout[0]" SITE "18" ;
 LOCATE COMP "Vout[1]" SITE "15" ;
 LOCATE COMP "Vout[2]" SITE "17" ;
@@ -55,11 +55,11 @@ LOCATE COMP "Vout[4]" SITE "19" ;
 LOCATE COMP "Vout[5]" SITE "16" ;
 LOCATE COMP "Vout[6]" SITE "14" ;
 LOCATE COMP "Vout[7]" SITE "12" ;
-LOCATE COMP "nCAS" SITE "52" ;
-LOCATE COMP "nCS" SITE "57" ;
+LOCATE COMP "nCASout" SITE "52" ;
+LOCATE COMP "nCSout" SITE "57" ;
 LOCATE COMP "nDOE" SITE "20" ;
-LOCATE COMP "nRAS" SITE "54" ;
-LOCATE COMP "nRWE" SITE "51" ;
+LOCATE COMP "nRASout" SITE "54" ;
+LOCATE COMP "nRWEout" SITE "51" ;
 LOCATE COMP "nVOE" SITE "10" ;
 LOCATE COMP "RD[0]" SITE "36" ;
 LOCATE COMP "RD[1]" SITE "37" ;
@@ -93,30 +93,30 @@ IOBUF PORT "nWE" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
 IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
 IOBUF PORT "BA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "BA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "CKE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "CKEout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "DQMH" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "DQML" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
-IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
-IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
-IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
-IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
-IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
-IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
-IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
+IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
+IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
 IOBUF PORT "LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "RA[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RAout[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "Vout[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "Vout[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "Vout[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
@@ -125,11 +125,11 @@ IOBUF PORT "Vout[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "Vout[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "Vout[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "Vout[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "nCAS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "nCS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "nCASout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "nCSout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "nDOE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "nRAS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
-IOBUF PORT "nRWE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "nRASout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "nRWEout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "nVOE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
 IOBUF PORT "RD[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ;
 IOBUF PORT "RD[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ;
@@ -142,7 +142,7 @@ IOBUF PORT "RD[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ;
 OUTPUT PORT "LED" LOAD 100.000000 pF ;
 OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
 OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
-OUTPUT PORT "CKE" LOAD 5.000000 pF ;
+OUTPUT PORT "CKEout" LOAD 5.000000 pF ;
 OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
 OUTPUT PORT "DQML" LOAD 5.000000 pF ;
 OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
@@ -153,18 +153,18 @@ OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
 OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
 OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
 OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
-OUTPUT PORT "RA[0]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[1]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[2]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[3]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[4]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[5]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[6]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[7]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[8]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[9]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[10]" LOAD 5.000000 pF ;
-OUTPUT PORT "RA[11]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ;
+OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ;
 OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
@@ -173,11 +173,11 @@ OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
 OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
-OUTPUT PORT "nCAS" LOAD 5.000000 pF ;
-OUTPUT PORT "nCS" LOAD 5.000000 pF ;
+OUTPUT PORT "nCASout" LOAD 5.000000 pF ;
+OUTPUT PORT "nCSout" LOAD 5.000000 pF ;
 OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
-OUTPUT PORT "nRAS" LOAD 5.000000 pF ;
-OUTPUT PORT "nRWE" LOAD 5.000000 pF ;
+OUTPUT PORT "nRASout" LOAD 5.000000 pF ;
+OUTPUT PORT "nRWEout" LOAD 5.000000 pF ;
 OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
 OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
 OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
diff --git a/CPLD/RAM2E-MAX.sdc b/CPLD/RAM2E-MAX.sdc
index e0b0052..411ded0 100644
--- a/CPLD/RAM2E-MAX.sdc
+++ b/CPLD/RAM2E-MAX.sdc
@@ -1,2 +1,2 @@
-create_clock ARCLK -period 200ns
-create_clock DRCLK -period 200ns
+create_clock [get_nets RAM2E_UFM:ram2e_ufm\|ARCLK] -period 200ns
+create_clock [get_nets RAM2E_UFM:ram2e_ufm\|DRCLK] -period 200ns
diff --git a/CPLD/RAM2E.mif b/CPLD/RAM2E.mif
index 80fa213..cef0e8a 100644
--- a/CPLD/RAM2E.mif
+++ b/CPLD/RAM2E.mif
@@ -1,25 +1,26 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- Quartus II generated Memory Initialization File (.mif)
-
-WIDTH=16;
-DEPTH=512;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-	[000..1FF]  :   FFFF;
-END;
+-- Copyright (C) 2019  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and any partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details, at
+-- https://fpgasoftware.intel.com/eula.
+
+-- Quartus Prime generated Memory Initialization File (.mif)
+
+WIDTH=16;
+DEPTH=512;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+	[000..1FF]  :   FFFF;
+END;
diff --git a/CPLD/RAM2E.qsf b/CPLD/RAM2E.qsf
deleted file mode 100644
index c9ec12d..0000000
--- a/CPLD/RAM2E.qsf
+++ /dev/null
@@ -1,259 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-# Date created = 22:58:44  May 05, 2020
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		RAM2E_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "MAX II"
-set_global_assignment -name DEVICE EPM240T100C5
-set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:58:44  MAY 05, 2020"
-set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
-set_global_assignment -name VERILOG_FILE RAM2E.v
-set_global_assignment -name SDC_FILE constraints.sdc
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
-set_global_assignment -name SAFE_STATE_MACHINE ON
-set_global_assignment -name PARALLEL_SYNTHESIS OFF
-set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name MIF_FILE RAM2E.mif
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
-
-set_location_assignment PIN_12 -to C14M
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C14M
-
-set_location_assignment PIN_37 -to PHI1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI1
-set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to PHI1
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI1
-
-set_location_assignment PIN_51 -to nWE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE
-
-set_location_assignment PIN_28 -to nEN80
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nEN80
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nEN80
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80
-
-set_location_assignment PIN_33 -to nWE80
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80
-
-set_location_assignment PIN_52 -to nC07X
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nC07X
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nC07X
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nC07X
-
-set_location_assignment PIN_56 -to Ain[0]
-set_location_assignment PIN_54 -to Ain[1]
-set_location_assignment PIN_43 -to Ain[2]
-set_location_assignment PIN_47 -to Ain[3]
-set_location_assignment PIN_44 -to Ain[4]
-set_location_assignment PIN_34 -to Ain[5]
-set_location_assignment PIN_39 -to Ain[6]
-set_location_assignment PIN_53 -to Ain[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Ain
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Ain
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Ain
-
-set_location_assignment PIN_38 -to Din[0]
-set_location_assignment PIN_40 -to Din[1]
-set_location_assignment PIN_42 -to Din[2]
-set_location_assignment PIN_41 -to Din[3]
-set_location_assignment PIN_48 -to Din[4]
-set_location_assignment PIN_49 -to Din[5]
-set_location_assignment PIN_36 -to Din[6]
-set_location_assignment PIN_35 -to Din[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Din
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Din
-
-set_location_assignment PIN_55 -to nDOE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE
-
-set_location_assignment PIN_77 -to Dout[0]
-set_location_assignment PIN_76 -to Dout[1]
-set_location_assignment PIN_74 -to Dout[2]
-set_location_assignment PIN_75 -to Dout[3]
-set_location_assignment PIN_73 -to Dout[4]
-set_location_assignment PIN_72 -to Dout[5]
-set_location_assignment PIN_84 -to Dout[6]
-set_location_assignment PIN_85 -to Dout[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout
-set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
-
-set_location_assignment PIN_50 -to nVOE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE
-
-set_location_assignment PIN_70 -to Vout[0]
-set_location_assignment PIN_67 -to Vout[1]
-set_location_assignment PIN_69 -to Vout[2]
-set_location_assignment PIN_62 -to Vout[3]
-set_location_assignment PIN_71 -to Vout[4]
-set_location_assignment PIN_68 -to Vout[5]
-set_location_assignment PIN_58 -to Vout[6]
-set_location_assignment PIN_57 -to Vout[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Vout
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Vout
-set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout
-
-set_location_assignment PIN_4 -to CKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE
-set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE
-
-set_location_assignment PIN_8 -to nCS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS
-
-set_location_assignment PIN_2 -to nRWE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE
-
-set_location_assignment PIN_5 -to nRAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
-
-set_location_assignment PIN_3 -to nCAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
-set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
-
-set_location_assignment PIN_6 -to BA[0]
-set_location_assignment PIN_14 -to BA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BA
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to BA
-set_instance_assignment -name SLOW_SLEW_RATE ON -to BA
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA
-
-set_location_assignment PIN_18 -to RA[0]
-set_location_assignment PIN_20 -to RA[1]
-set_location_assignment PIN_30 -to RA[2]
-set_location_assignment PIN_27 -to RA[3]
-set_location_assignment PIN_26 -to RA[4]
-set_location_assignment PIN_29 -to RA[5]
-set_location_assignment PIN_21 -to RA[6]
-set_location_assignment PIN_19 -to RA[7]
-set_location_assignment PIN_17 -to RA[8]
-set_location_assignment PIN_15 -to RA[9]
-set_location_assignment PIN_16 -to RA[10]
-set_location_assignment PIN_7 -to RA[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA
-set_instance_assignment -name SLOW_SLEW_RATE ON -to RA
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
-
-set_location_assignment PIN_100 -to DQMH
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH
-set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQMH
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH
-
-set_location_assignment PIN_98 -to DQML
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQML
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML
-set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQML
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML
-
-set_location_assignment PIN_97 -to RD[0]
-set_location_assignment PIN_90 -to RD[1]
-set_location_assignment PIN_99 -to RD[2]
-set_location_assignment PIN_89 -to RD[3]
-set_location_assignment PIN_91 -to RD[4]
-set_location_assignment PIN_92 -to RD[5]
-set_location_assignment PIN_95 -to RD[6]
-set_location_assignment PIN_96 -to RD[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD
-set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
-set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
-
-set_global_assignment -name QIP_FILE UFM.qip
\ No newline at end of file
diff --git a/CPLD/RAM2E.v b/CPLD/RAM2E.v
index 1849e7c..54b0303 100644
--- a/CPLD/RAM2E.v
+++ b/CPLD/RAM2E.v
@@ -14,7 +14,6 @@ module RAM2E(C14M, PHI1, LED,
     reg [15:0] FS = 0; always @(posedge C14M) FS <= FS+16'h0001;
     reg Ready = 0;
     always @(posedge C14M) if (FS[15:0]==16'hFFFF) Ready <= 1'b1;
-    wire RefReq = FS[5:4]==0; // Refresh request based on fast state counter
 
     /* IIe state counter */
     reg [3:0] S = 0;
@@ -25,6 +24,16 @@ module RAM2E(C14M, PHI1, LED,
              (S==4'hF) ? 4'hF : S+4'h1;
     end
 
+    /* Refresh counter */
+    reg [2:0] RC;
+    wire RefReq = RC==0;
+    always @(posedge C14M) begin
+        if (S==4'h1) begin
+            if (RC[2] && RC[1]) RC <= 0; // RC==6 || RC==7
+            else RC <= RC+3'h1;
+        end
+    end
+
     /* Activity LED */
     wire LEDEN;
     output LED; assign LED = !(!nEN80 && LEDEN && Ready);
@@ -53,15 +62,16 @@ module RAM2E(C14M, PHI1, LED,
     output reg [7:0] Vout; // Video data bus
     always @(posedge C14M) if (S==4'h6) Vout[7:0] <= RD[7:0];
 
-    /* SDRAM */
+    /* SDRAM bus */
     reg CKE = 1;
-	//reg nCS = 1;
     reg nRAS = 1, nCAS = 1, nRWE = 1;
     output reg [1:0] BA;
     reg [11:0] RA;
     output reg DQML = 1, DQMH = 1;
     inout [7:0] RD;
-    assign RD[7:0] = Ready ? (!nWE80 ? Din[7:0] : 8'bZ) : 8'h00;
+    wire [7:0] RDout = Ready ? Din[7:0] : 8'h00;
+    wire RDOE = (!Ready) || (!nEN80 && !nWE);
+    assign RD[7:0] = RDOE ? RDout[7:0] : 8'bZ;
 
     /* SDRAM falling edge outputs */
 	output reg CKEout;
@@ -84,7 +94,6 @@ module RAM2E(C14M, PHI1, LED,
         if (S==4'h9) RWSel <= RA[0] && !RA[3] && !nWE && !nC07X;
     end
     reg CmdRWMaskSet = 0; // RAMWorks Mask register set flag
-    // Causes RWBank to be zeroed next RWSel access
     wire CmdSetRWBankFFChip;
     reg CmdSetRWBankFFLED = 0;
     reg CmdLEDSet = 0;
@@ -96,7 +105,7 @@ module RAM2E(C14M, PHI1, LED,
 
     /* Chip-specific UFM interface */
     RAM2E_UFM ram2e_ufm (
-        .C14M(C14M), .S(S), .FS(FS), .CS(CS), 
+        .C14M(C14M), .S(S), .FS(FS), .CS(CS), .Ready(Ready),
         .RWSel(RWSel), .D(Din),
         .RWMask(RWMask), .LEDEN(LEDEN),
         .CmdRWMaskSet(CmdRWMaskSet), .CmdLEDSet(CmdLEDSet),
@@ -259,24 +268,32 @@ module RAM2E(C14M, PHI1, LED,
             RA[7:0] <= Ain[7:0];
             // Hold DQMs
         end 4'h4: begin
-            // PC all CKE
-            CKE <= 1'b1;
-            nRAS <= 1'b0;
-            nCAS <= 1'b1;
-            nRWE <= 1'b0;
+            if (RefReq) begin // Refresh request
+                // PC all CKE
+                CKE <= 1'b1;
+                nRAS <= 1'b0;
+                nCAS <= 1'b1;
+                nRWE <= 1'b0;
+            end else begin // No refresh request
+                // PC all CKD
+                CKE <= 1'b0;
+                nRAS <= 1'b0;
+                nCAS <= 1'b1;
+                nRWE <= 1'b0;
+            end
             // Hold BA
             // Hold RA[11]
             RA[10] <= 1'b1; // "all"
             // Hold RA[9:0]
             // Hold DQMs
         end 4'h5: begin
-            if (RefReq) begin
+            if (RefReq) begin // Refresh request
                 // AREF CKE
                 CKE <= 1'b1;
                 nRAS <= 1'b0;
                 nCAS <= 1'b0;
                 nRWE <= 1'b1;
-            end else begin
+            end else begin // No refresh request
                 // NOP CKD
                 CKE <= 1'b0;
                 nRAS <= 1'b1;
@@ -297,21 +314,13 @@ module RAM2E(C14M, PHI1, LED,
             // Hold DQMs
         end 4'h7: begin
             // Can't check EN80 at this time
-            if (nWE) begin // Read / idle
-                // NOP CKE
-                CKE <= 1'b1;
-                nRAS <= 1'b1;
-                nCAS <= 1'b1;
-                nRWE <= 1'b1;
-            end else begin // Write / idle
-                // NOP CKD
-                CKE <= 1'b0;
-                nRAS <= 1'b1;
-                nCAS <= 1'b1;
-                nRWE <= 1'b1;
-            end
-            BA[1:0] <= RWBank[6:5];
-            RA[11:8] <= RWBank[4:1];
+            // NOP CKE
+            CKE <= 1'b1;
+            nRAS <= 1'b1;
+            nCAS <= 1'b1;
+            nRWE <= 1'b1;
+            // Hold BA
+            // Hold RA[11:8]
             RA[7:0] <= Ain[7:0];
             // Hold DQMs
         end 4'h8: begin
@@ -328,14 +337,15 @@ module RAM2E(C14M, PHI1, LED,
                 nCAS <= 1'b1;
                 nRWE <= 1'b1;
             end else begin // Write
-                // NOP CKE
-                CKE <= 1'b1;
-                nRAS <= 1'b1;
+                // ACT CKD
+                CKE <= 1'b0;
+                nRAS <= 1'b0;
                 nCAS <= 1'b1;
                 nRWE <= 1'b1;
             end
-            // Hold BA
-            // Hold RA
+            BA[1:0] <= RWBank[6:5];
+            RA[11:8] <= RWBank[4:1];
+            // Hold RA[7:0]
             // Hold DQMs
         end 4'h9: begin
             if (nEN80) begin // Idle
@@ -351,9 +361,9 @@ module RAM2E(C14M, PHI1, LED,
                 nCAS <= 1'b0;
                 nRWE <= 1'b1;
             end else begin // Write
-                // ACT CKE
+                // NOP CKE
                 CKE <= 1'b1;
-                nRAS <= 1'b0;
+                nRAS <= 1'b1;
                 nCAS <= 1'b1;
                 nRWE <= 1'b1;
             end
@@ -361,8 +371,8 @@ module RAM2E(C14M, PHI1, LED,
             RA[11:9] <= 3'b000; // no auto-precharge
             RA[8] <= RWBank[7];
             RA[7:0] <= Ain[7:0];
+            DQML <=  RWBank[0];
             DQMH <= !RWBank[0];
-            DQMH <=  RWBank[0];
         end 4'hA: begin
             if (nEN80) begin // Idle
                 // NOP CKD
@@ -370,21 +380,21 @@ module RAM2E(C14M, PHI1, LED,
                 nRAS <= 1'b1;
                 nCAS <= 1'b1;
                 nRWE <= 1'b1;
-                // Hold RA[10]
+                RA[10] <= 1'b0;
             end else if (nWE) begin // Read
                 // PC all CKD
                 CKE <= 1'b0;
                 nRAS <= 1'b0;
                 nCAS <= 1'b1;
                 nRWE <= 1'b0;
-                RA[10] <= 1'b1;
+                RA[10] <= 1'b1; // "all"
             end else begin // Write
                 // WR CKE
                 CKE <= 1'b1;
                 nRAS <= 1'b1;
                 nCAS <= 1'b0;
                 nRWE <= 1'b0;
-                RA[10] <= 1'b0;
+                RA[10] <= 1'b0; // no auto-precharge
             end
             // Hold BA
             // Hold RA[11,9:0]
@@ -419,14 +429,14 @@ module RAM2E(C14M, PHI1, LED,
                 nRAS <= 1'b1;
                 nCAS <= 1'b1;
                 nRWE <= 1'b1;
-                // Hold RA[10]
+                RA[10] <= 1'b0;
             end else if (nWE) begin // Read
                 // NOP CKD
                 CKE <= 1'b0;
                 nRAS <= 1'b1;
                 nCAS <= 1'b1;
                 nRWE <= 1'b1;
-                // Hold RA[10]
+                RA[10] <= 1'b1;
             end else begin // Write
                 // PC all CKD
                 CKE <= 1'b0;
diff --git a/CPLD/UFM-LCMXO2.v b/CPLD/UFM-LCMXO2.v
index faf1ae0..1a8fbf1 100644
--- a/CPLD/UFM-LCMXO2.v
+++ b/CPLD/UFM-LCMXO2.v
@@ -1,4 +1,4 @@
-module RAM2E_UFM(C14M, S, FS, CS,
+module RAM2E_UFM(C14M, S, FS, CS, Ready,
                  RWSel, D,
                  RWMask, LEDEN,
                  CmdRWMaskSet, CmdLEDSet,
@@ -6,7 +6,8 @@ module RAM2E_UFM(C14M, S, FS, CS,
     input C14M;
     input [3:0] S;
     input [15:0] FS;
-    input [2:0] CS;
+    input [2:0] CS;
+	input Ready;
     input RWSel;
     input [7:0] D;
     output reg [7:0] RWMask;
diff --git a/CPLD/UFM-MAX.v b/CPLD/UFM-MAX.v
index d144db7..e0b94a9 100644
--- a/CPLD/UFM-MAX.v
+++ b/CPLD/UFM-MAX.v
@@ -1,4 +1,4 @@
-module RAM2E_UFM(C14M, S, FS, CS,
+module RAM2E_UFM(C14M, S, FS, CS, Ready,
                  RWSel, D,
                  RWMask, LEDEN,
 				 CmdRWMaskSet, CmdLEDSet,
@@ -7,6 +7,7 @@ module RAM2E_UFM(C14M, S, FS, CS,
 	input [3:0] S;
     input [15:0] FS;
     input [2:0] CS;
+    input Ready;
 	input RWSel;
 	input [7:0] D;
     output reg [7:0] RWMask;
diff --git a/Documentation/GW4203BDevNote.pdf b/Documentation/GW4203BDevNote.pdf
index 89f2dc61020b097c61871a28063e40e67fafcda1..41975b6b5b934a2b2f86122aa509f402d75a8e9f 100644
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