mirror of
https://github.com/garrettsworkshop/RAM2E.git
synced 2024-12-13 01:30:10 +00:00
Merge branch 'dev-GW4203B-2.0' into dev-GW4203B
This commit is contained in:
Zane Kaminski
commit
eaeba53cda
47
.gitignore
vendored
47
.gitignore
vendored
@ -14,18 +14,41 @@ _autosave-*
|
||||
*-save.pro
|
||||
*-save.kicad_pcb
|
||||
fp-info-cache
|
||||
Hardware/*/*-backups
|
||||
|
||||
# Netlist files (exported from Eeschema)
|
||||
*.net
|
||||
|
||||
# Autorouter files (exported from Pcbnew)
|
||||
*.dsn
|
||||
*.ses
|
||||
|
||||
# Exported BOM files
|
||||
*.xml
|
||||
|
||||
# Mac
|
||||
*.DS_Store
|
||||
Documentation/~$4203BManual.docx
|
||||
*.cdf
|
||||
Documentation/~$4203BDevNote.docx
|
||||
|
||||
|
||||
# Altera MAX II/V
|
||||
CPLD/MAX*/db
|
||||
CPLD/MAX*/incremental_db
|
||||
CPLD/MAX*/greybox_tmp
|
||||
|
||||
|
||||
# Lattice Diamond
|
||||
CPLD/LCMXO*/*.dir
|
||||
CPLD/LCMXO*/.build_status
|
||||
CPLD/LCMXO*/.run_manager.ini
|
||||
CPLD/LCMXO*/.recovery
|
||||
CPLD/LCMXO*/.spread_sheet.ini
|
||||
CPLD/LCMXO*/.spreadsheet_view.ini
|
||||
CPLD/LCMXO*/impl1/*
|
||||
!CPLD/LCMXO*/impl1/*.jed
|
||||
!CPLD/LCMXO*/impl1/*.bit
|
||||
!CPLD/LCMXO*/impl1/*.html
|
||||
!CPLD/LCMXO*/impl1/*.rpt
|
||||
!CPLD/LCMXO*/impl1/*.sdf
|
||||
!CPLD/LCMXO*/impl1/*.vo
|
||||
!CPLD/LCMXO*/impl1/*.alt
|
||||
!CPLD/LCMXO*/impl1/*.areasrr
|
||||
!CPLD/LCMXO*/impl1/*.bgn
|
||||
!CPLD/LCMXO*/impl1/*.edi
|
||||
!CPLD/LCMXO*/impl1/*.ior
|
||||
!CPLD/LCMXO*/impl1/*.mrp
|
||||
!CPLD/LCMXO*/impl1/*.pad
|
||||
!CPLD/LCMXO*/impl1/*.prf
|
||||
!CPLD/LCMXO*/impl1/*.srr
|
||||
!CPLD/LCMXO*/impl1/*.twr
|
||||
!CPLD/LCMXO*/impl1/*.tw1
|
||||
|
||||
4
CPLD/LCMXO2-1200HC/.setting.ini
Normal file
4
CPLD/LCMXO2-1200HC/.setting.ini
Normal file
@ -0,0 +1,4 @@
|
||||
[General]
|
||||
Map.auto_tasks=MapTrace, MapVerilogSimFile
|
||||
PAR.auto_tasks=PARTrace, IOTiming
|
||||
Export.auto_tasks=IBIS, TimingSimFileVlg, Bitgen, Jedecgen
|
||||
20
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf
Normal file
20
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf
Normal file
@ -0,0 +1,20 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BaliProject version="3.2" title="RAM2E_LCMXO2_1200HC" device="LCMXO2-1200HC-4TG100C" default_implementation="impl1">
|
||||
<Options/>
|
||||
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
|
||||
<Options def_top="RAM2E" top="RAM2E"/>
|
||||
<Source name="../RAM2E-LCMXO2.v" type="Verilog" type_short="Verilog">
|
||||
<Options top_module="RAM2E"/>
|
||||
</Source>
|
||||
<Source name="REFB.v" type="Verilog" type_short="Verilog">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="../RAM2E-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="../RAM2E.sdc" type="Synplify Design Constraints File" type_short="SDC">
|
||||
<Options/>
|
||||
</Source>
|
||||
</Implementation>
|
||||
<Strategy name="Strategy1" file="RAM2E_LCMXO2_1200HC1.sty"/>
|
||||
</BaliProject>
|
||||
205
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC1.sty
Normal file
205
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC1.sty
Normal file
@ -0,0 +1,205 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE strategy>
|
||||
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
|
||||
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
|
||||
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
|
||||
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
|
||||
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
|
||||
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
|
||||
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
|
||||
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
|
||||
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
|
||||
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
|
||||
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
|
||||
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
|
||||
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
|
||||
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
|
||||
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
|
||||
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
|
||||
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
|
||||
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
|
||||
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
|
||||
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
|
||||
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
|
||||
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
|
||||
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
|
||||
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
|
||||
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
|
||||
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
|
||||
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
|
||||
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
|
||||
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
|
||||
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
|
||||
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
|
||||
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
|
||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
|
||||
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
|
||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
|
||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
|
||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
|
||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
|
||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
|
||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
|
||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
|
||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
||||
</Strategy>
|
||||
71
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html
Normal file
71
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html
Normal file
@ -0,0 +1,71 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn230921045934"></A><B><U><big>pn230921045934</big></U></B>
|
||||
#Start recording tcl command: 9/21/2023 04:58:28
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
|
||||
prj_run PAR -impl impl1 -task IOTiming
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 9/21/2023 04:59:34
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
550
CPLD/LCMXO2-1200HC/REFB.edn
Normal file
550
CPLD/LCMXO2-1200HC/REFB.edn
Normal file
@ -0,0 +1,550 @@
|
||||
(edif REFB
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2023 9 20 4 45 58)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.12.1.454"))))
|
||||
(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell EFB
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port WBCLKI
|
||||
(direction INPUT))
|
||||
(port WBRSTI
|
||||
(direction INPUT))
|
||||
(port WBCYCI
|
||||
(direction INPUT))
|
||||
(port WBSTBI
|
||||
(direction INPUT))
|
||||
(port WBWEI
|
||||
(direction INPUT))
|
||||
(port WBADRI7
|
||||
(direction INPUT))
|
||||
(port WBADRI6
|
||||
(direction INPUT))
|
||||
(port WBADRI5
|
||||
(direction INPUT))
|
||||
(port WBADRI4
|
||||
(direction INPUT))
|
||||
(port WBADRI3
|
||||
(direction INPUT))
|
||||
(port WBADRI2
|
||||
(direction INPUT))
|
||||
(port WBADRI1
|
||||
(direction INPUT))
|
||||
(port WBADRI0
|
||||
(direction INPUT))
|
||||
(port WBDATI7
|
||||
(direction INPUT))
|
||||
(port WBDATI6
|
||||
(direction INPUT))
|
||||
(port WBDATI5
|
||||
(direction INPUT))
|
||||
(port WBDATI4
|
||||
(direction INPUT))
|
||||
(port WBDATI3
|
||||
(direction INPUT))
|
||||
(port WBDATI2
|
||||
(direction INPUT))
|
||||
(port WBDATI1
|
||||
(direction INPUT))
|
||||
(port WBDATI0
|
||||
(direction INPUT))
|
||||
(port PLL0DATI7
|
||||
(direction INPUT))
|
||||
(port PLL0DATI6
|
||||
(direction INPUT))
|
||||
(port PLL0DATI5
|
||||
(direction INPUT))
|
||||
(port PLL0DATI4
|
||||
(direction INPUT))
|
||||
(port PLL0DATI3
|
||||
(direction INPUT))
|
||||
(port PLL0DATI2
|
||||
(direction INPUT))
|
||||
(port PLL0DATI1
|
||||
(direction INPUT))
|
||||
(port PLL0DATI0
|
||||
(direction INPUT))
|
||||
(port PLL0ACKI
|
||||
(direction INPUT))
|
||||
(port PLL1DATI7
|
||||
(direction INPUT))
|
||||
(port PLL1DATI6
|
||||
(direction INPUT))
|
||||
(port PLL1DATI5
|
||||
(direction INPUT))
|
||||
(port PLL1DATI4
|
||||
(direction INPUT))
|
||||
(port PLL1DATI3
|
||||
(direction INPUT))
|
||||
(port PLL1DATI2
|
||||
(direction INPUT))
|
||||
(port PLL1DATI1
|
||||
(direction INPUT))
|
||||
(port PLL1DATI0
|
||||
(direction INPUT))
|
||||
(port PLL1ACKI
|
||||
(direction INPUT))
|
||||
(port I2C1SCLI
|
||||
(direction INPUT))
|
||||
(port I2C1SDAI
|
||||
(direction INPUT))
|
||||
(port I2C2SCLI
|
||||
(direction INPUT))
|
||||
(port I2C2SDAI
|
||||
(direction INPUT))
|
||||
(port SPISCKI
|
||||
(direction INPUT))
|
||||
(port SPIMISOI
|
||||
(direction INPUT))
|
||||
(port SPIMOSII
|
||||
(direction INPUT))
|
||||
(port SPISCSN
|
||||
(direction INPUT))
|
||||
(port TCCLKI
|
||||
(direction INPUT))
|
||||
(port TCRSTN
|
||||
(direction INPUT))
|
||||
(port TCIC
|
||||
(direction INPUT))
|
||||
(port UFMSN
|
||||
(direction INPUT))
|
||||
(port WBDATO7
|
||||
(direction OUTPUT))
|
||||
(port WBDATO6
|
||||
(direction OUTPUT))
|
||||
(port WBDATO5
|
||||
(direction OUTPUT))
|
||||
(port WBDATO4
|
||||
(direction OUTPUT))
|
||||
(port WBDATO3
|
||||
(direction OUTPUT))
|
||||
(port WBDATO2
|
||||
(direction OUTPUT))
|
||||
(port WBDATO1
|
||||
(direction OUTPUT))
|
||||
(port WBDATO0
|
||||
(direction OUTPUT))
|
||||
(port WBACKO
|
||||
(direction OUTPUT))
|
||||
(port PLLCLKO
|
||||
(direction OUTPUT))
|
||||
(port PLLRSTO
|
||||
(direction OUTPUT))
|
||||
(port PLL0STBO
|
||||
(direction OUTPUT))
|
||||
(port PLL1STBO
|
||||
(direction OUTPUT))
|
||||
(port PLLWEO
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO4
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO3
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO2
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO1
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO0
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO7
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO6
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO5
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO4
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO3
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO2
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO1
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO0
|
||||
(direction OUTPUT))
|
||||
(port I2C1SCLO
|
||||
(direction OUTPUT))
|
||||
(port I2C1SCLOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C1SDAO
|
||||
(direction OUTPUT))
|
||||
(port I2C1SDAOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C2SCLO
|
||||
(direction OUTPUT))
|
||||
(port I2C2SCLOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C2SDAO
|
||||
(direction OUTPUT))
|
||||
(port I2C2SDAOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C1IRQO
|
||||
(direction OUTPUT))
|
||||
(port I2C2IRQO
|
||||
(direction OUTPUT))
|
||||
(port SPISCKO
|
||||
(direction OUTPUT))
|
||||
(port SPISCKEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMISOO
|
||||
(direction OUTPUT))
|
||||
(port SPIMISOEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMOSIO
|
||||
(direction OUTPUT))
|
||||
(port SPIMOSIEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN7
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN6
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN5
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN4
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN3
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN2
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN1
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN0
|
||||
(direction OUTPUT))
|
||||
(port SPICSNEN
|
||||
(direction OUTPUT))
|
||||
(port SPIIRQO
|
||||
(direction OUTPUT))
|
||||
(port TCINT
|
||||
(direction OUTPUT))
|
||||
(port TCOC
|
||||
(direction OUTPUT))
|
||||
(port WBCUFMIRQ
|
||||
(direction OUTPUT))
|
||||
(port CFGWAKE
|
||||
(direction OUTPUT))
|
||||
(port CFGSTDBY
|
||||
(direction OUTPUT)))))
|
||||
(cell REFB
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port wb_clk_i
|
||||
(direction INPUT))
|
||||
(port wb_rst_i
|
||||
(direction INPUT))
|
||||
(port wb_cyc_i
|
||||
(direction INPUT))
|
||||
(port wb_stb_i
|
||||
(direction INPUT))
|
||||
(port wb_we_i
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_adr_i "wb_adr_i(7:0)") 8)
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_dat_i "wb_dat_i(7:0)") 8)
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_dat_o "wb_dat_o(7:0)") 8)
|
||||
(direction OUTPUT))
|
||||
(port wb_ack_o
|
||||
(direction OUTPUT))
|
||||
(port wbc_ufm_irq
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance EFBInst_0
|
||||
(viewRef view1
|
||||
(cellRef EFB))
|
||||
(property UFM_INIT_FILE_FORMAT
|
||||
(string "HEX"))
|
||||
(property UFM_INIT_FILE_NAME
|
||||
(string "../RAM2E-LCMXO2.mem"))
|
||||
(property UFM_INIT_ALL_ZEROS
|
||||
(string "DISABLED"))
|
||||
(property UFM_INIT_START_PAGE
|
||||
(string "190"))
|
||||
(property UFM_INIT_PAGES
|
||||
(string "321"))
|
||||
(property DEV_DENSITY
|
||||
(string "1200L"))
|
||||
(property EFB_UFM
|
||||
(string "ENABLED"))
|
||||
(property TC_ICAPTURE
|
||||
(string "DISABLED"))
|
||||
(property TC_OVERFLOW
|
||||
(string "DISABLED"))
|
||||
(property TC_ICR_INT
|
||||
(string "OFF"))
|
||||
(property TC_OCR_INT
|
||||
(string "OFF"))
|
||||
(property TC_OV_INT
|
||||
(string "OFF"))
|
||||
(property TC_TOP_SEL
|
||||
(string "OFF"))
|
||||
(property TC_RESETN
|
||||
(string "ENABLED"))
|
||||
(property TC_OC_MODE
|
||||
(string "TOGGLE"))
|
||||
(property TC_OCR_SET
|
||||
(string "32767"))
|
||||
(property TC_TOP_SET
|
||||
(string "65535"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property TC_CCLK_SEL
|
||||
(string "1"))
|
||||
(property TC_MODE
|
||||
(string "CTCM"))
|
||||
(property TC_SCLK_SEL
|
||||
(string "PCLOCK"))
|
||||
(property EFB_TC_PORTMODE
|
||||
(string "WB"))
|
||||
(property EFB_TC
|
||||
(string "DISABLED"))
|
||||
(property SPI_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_RXOVR
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_TXOVR
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_RXRDY
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_TXRDY
|
||||
(string "DISABLED"))
|
||||
(property SPI_SLAVE_HANDSHAKE
|
||||
(string "DISABLED"))
|
||||
(property SPI_PHASE_ADJ
|
||||
(string "DISABLED"))
|
||||
(property SPI_CLK_INV
|
||||
(string "DISABLED"))
|
||||
(property SPI_LSB_FIRST
|
||||
(string "DISABLED"))
|
||||
(property SPI_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property SPI_MODE
|
||||
(string "MASTER"))
|
||||
(property EFB_SPI
|
||||
(string "DISABLED"))
|
||||
(property I2C2_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property I2C2_GEN_CALL
|
||||
(string "DISABLED"))
|
||||
(property I2C2_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property I2C2_BUS_PERF
|
||||
(string "100kHz"))
|
||||
(property I2C2_SLAVE_ADDR
|
||||
(string "0b1000010"))
|
||||
(property I2C2_ADDRESSING
|
||||
(string "7BIT"))
|
||||
(property EFB_I2C2
|
||||
(string "DISABLED"))
|
||||
(property I2C1_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property I2C1_GEN_CALL
|
||||
(string "DISABLED"))
|
||||
(property I2C1_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property I2C1_BUS_PERF
|
||||
(string "100kHz"))
|
||||
(property I2C1_SLAVE_ADDR
|
||||
(string "0b1000001"))
|
||||
(property I2C1_ADDRESSING
|
||||
(string "7BIT"))
|
||||
(property EFB_I2C1
|
||||
(string "DISABLED"))
|
||||
(property EFB_WB_CLK_FREQ
|
||||
(string "14.4")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef UFMSN (instanceRef EFBInst_0))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef PLL1DATI7 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI6 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI5 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI4 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI3 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI2 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI1 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI0 (instanceRef EFBInst_0))
|
||||
(portRef PLL1ACKI (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI7 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI6 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI5 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI4 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI3 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI2 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI1 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI0 (instanceRef EFBInst_0))
|
||||
(portRef PLL0ACKI (instanceRef EFBInst_0))
|
||||
(portRef TCIC (instanceRef EFBInst_0))
|
||||
(portRef TCRSTN (instanceRef EFBInst_0))
|
||||
(portRef TCCLKI (instanceRef EFBInst_0))
|
||||
(portRef SPISCSN (instanceRef EFBInst_0))
|
||||
(portRef SPIMOSII (instanceRef EFBInst_0))
|
||||
(portRef SPIMISOI (instanceRef EFBInst_0))
|
||||
(portRef SPISCKI (instanceRef EFBInst_0))
|
||||
(portRef I2C2SDAI (instanceRef EFBInst_0))
|
||||
(portRef I2C2SCLI (instanceRef EFBInst_0))
|
||||
(portRef I2C1SDAI (instanceRef EFBInst_0))
|
||||
(portRef I2C1SCLI (instanceRef EFBInst_0))))
|
||||
(net wbc_ufm_irq
|
||||
(joined
|
||||
(portRef wbc_ufm_irq)
|
||||
(portRef WBCUFMIRQ (instanceRef EFBInst_0))))
|
||||
(net wb_ack_o
|
||||
(joined
|
||||
(portRef wb_ack_o)
|
||||
(portRef WBACKO (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o7
|
||||
(joined
|
||||
(portRef (member wb_dat_o 0))
|
||||
(portRef WBDATO7 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o6
|
||||
(joined
|
||||
(portRef (member wb_dat_o 1))
|
||||
(portRef WBDATO6 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o5
|
||||
(joined
|
||||
(portRef (member wb_dat_o 2))
|
||||
(portRef WBDATO5 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o4
|
||||
(joined
|
||||
(portRef (member wb_dat_o 3))
|
||||
(portRef WBDATO4 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o3
|
||||
(joined
|
||||
(portRef (member wb_dat_o 4))
|
||||
(portRef WBDATO3 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o2
|
||||
(joined
|
||||
(portRef (member wb_dat_o 5))
|
||||
(portRef WBDATO2 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o1
|
||||
(joined
|
||||
(portRef (member wb_dat_o 6))
|
||||
(portRef WBDATO1 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o0
|
||||
(joined
|
||||
(portRef (member wb_dat_o 7))
|
||||
(portRef WBDATO0 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i7
|
||||
(joined
|
||||
(portRef (member wb_dat_i 0))
|
||||
(portRef WBDATI7 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i6
|
||||
(joined
|
||||
(portRef (member wb_dat_i 1))
|
||||
(portRef WBDATI6 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i5
|
||||
(joined
|
||||
(portRef (member wb_dat_i 2))
|
||||
(portRef WBDATI5 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i4
|
||||
(joined
|
||||
(portRef (member wb_dat_i 3))
|
||||
(portRef WBDATI4 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i3
|
||||
(joined
|
||||
(portRef (member wb_dat_i 4))
|
||||
(portRef WBDATI3 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i2
|
||||
(joined
|
||||
(portRef (member wb_dat_i 5))
|
||||
(portRef WBDATI2 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i1
|
||||
(joined
|
||||
(portRef (member wb_dat_i 6))
|
||||
(portRef WBDATI1 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i0
|
||||
(joined
|
||||
(portRef (member wb_dat_i 7))
|
||||
(portRef WBDATI0 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i7
|
||||
(joined
|
||||
(portRef (member wb_adr_i 0))
|
||||
(portRef WBADRI7 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i6
|
||||
(joined
|
||||
(portRef (member wb_adr_i 1))
|
||||
(portRef WBADRI6 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i5
|
||||
(joined
|
||||
(portRef (member wb_adr_i 2))
|
||||
(portRef WBADRI5 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i4
|
||||
(joined
|
||||
(portRef (member wb_adr_i 3))
|
||||
(portRef WBADRI4 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i3
|
||||
(joined
|
||||
(portRef (member wb_adr_i 4))
|
||||
(portRef WBADRI3 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i2
|
||||
(joined
|
||||
(portRef (member wb_adr_i 5))
|
||||
(portRef WBADRI2 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i1
|
||||
(joined
|
||||
(portRef (member wb_adr_i 6))
|
||||
(portRef WBADRI1 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i0
|
||||
(joined
|
||||
(portRef (member wb_adr_i 7))
|
||||
(portRef WBADRI0 (instanceRef EFBInst_0))))
|
||||
(net wb_we_i
|
||||
(joined
|
||||
(portRef wb_we_i)
|
||||
(portRef WBWEI (instanceRef EFBInst_0))))
|
||||
(net wb_stb_i
|
||||
(joined
|
||||
(portRef wb_stb_i)
|
||||
(portRef WBSTBI (instanceRef EFBInst_0))))
|
||||
(net wb_cyc_i
|
||||
(joined
|
||||
(portRef wb_cyc_i)
|
||||
(portRef WBCYCI (instanceRef EFBInst_0))))
|
||||
(net wb_rst_i
|
||||
(joined
|
||||
(portRef wb_rst_i)
|
||||
(portRef WBRSTI (instanceRef EFBInst_0))))
|
||||
(net wb_clk_i
|
||||
(joined
|
||||
(portRef wb_clk_i)
|
||||
(portRef WBCLKI (instanceRef EFBInst_0))))))))
|
||||
(design REFB
|
||||
(cellRef REFB
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
8
CPLD/LCMXO2-1200HC/REFB.ipx
Normal file
8
CPLD/LCMXO2-1200HC/REFB.ipx
Normal file
@ -0,0 +1,8 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 09 20 04:46:00.352" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
|
||||
<Package>
|
||||
<File name="REFB.lpc" type="lpc" modified="2023 09 20 04:45:58.427"/>
|
||||
<File name="REFB.v" type="top_level_verilog" modified="2023 09 20 04:45:58.515"/>
|
||||
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 09 20 04:45:58.515"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
||||
141
CPLD/LCMXO2-1200HC/REFB.lpc
Normal file
141
CPLD/LCMXO2-1200HC/REFB.lpc
Normal file
@ -0,0 +1,141 @@
|
||||
[Device]
|
||||
Family=machxo2
|
||||
PartType=LCMXO2-1200HC
|
||||
PartName=LCMXO2-1200HC-4TG100C
|
||||
SpeedGrade=4
|
||||
Package=TQFP100
|
||||
OperatingCondition=COM
|
||||
Status=S
|
||||
|
||||
[IP]
|
||||
VendorName=Lattice Semiconductor Corporation
|
||||
CoreType=LPM
|
||||
CoreStatus=Demo
|
||||
CoreName=EFB
|
||||
CoreRevision=1.2
|
||||
ModuleName=REFB
|
||||
SourceFormat=Verilog HDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=09/20/2023
|
||||
Time=04:45:58
|
||||
|
||||
[Parameters]
|
||||
Verilog=1
|
||||
VHDL=0
|
||||
EDIF=1
|
||||
Destination=Synplicity
|
||||
Expression=BusA(0 to 7)
|
||||
Order=Big Endian [MSB:LSB]
|
||||
IO=0
|
||||
freq=
|
||||
i2c1=0
|
||||
i2c1config=0
|
||||
i2c1_addr=7-Bit Addressing
|
||||
i2c1_ce=0
|
||||
i2c1_freq=100
|
||||
i2c1_sa=10000
|
||||
i2c1_we=0
|
||||
i2c2=0
|
||||
i2c2_addr=7-Bit Addressing
|
||||
i2c2_ce=0
|
||||
i2c2_freq=100
|
||||
i2c2_sa=10000
|
||||
i2c2_we=0
|
||||
ufm_addr=7-Bit Addressing
|
||||
ufm_sa=10000
|
||||
pll=0
|
||||
pll_cnt=1
|
||||
spi=0
|
||||
spi_clkinv=0
|
||||
spi_cs=1
|
||||
spi_en=0
|
||||
spi_freq=1
|
||||
spi_lsb=0
|
||||
spi_mode=Slave
|
||||
spi_ib=0
|
||||
spi_ph=0
|
||||
spi_hs=0
|
||||
spi_rxo=0
|
||||
spi_rxr=0
|
||||
spi_txo=0
|
||||
spi_txr=0
|
||||
spi_we=0
|
||||
static_tc=Static
|
||||
tc=0
|
||||
tc_clkinv=Positive
|
||||
tc_ctr=1
|
||||
tc_div=1
|
||||
tc_ipcap=0
|
||||
tc_mode=CTCM
|
||||
tc_ocr=32767
|
||||
tc_oflow=1
|
||||
tc_o=TOGGLE
|
||||
tc_opcomp=0
|
||||
tc_osc=0
|
||||
tc_sa_oflow=0
|
||||
tc_top=65535
|
||||
ufm=1
|
||||
ufm0=0
|
||||
ufm1=0
|
||||
ufm2=0
|
||||
ufm3=0
|
||||
ufm_cfg0=0
|
||||
ufm_cfg1=0
|
||||
wb_clk_freq=14.4
|
||||
ufm_usage=SHARED_EBR_TAG
|
||||
ufm_ebr=190
|
||||
ufm_remain=
|
||||
mem_size=321
|
||||
ufm_start=
|
||||
ufm_init=mem
|
||||
memfile=../RAM2E-LCMXO2.mem
|
||||
ufm_dt=hex
|
||||
ufm0_ebr=
|
||||
mem_size0=1
|
||||
ufm0_init=0
|
||||
memfile0=
|
||||
ufm0_dt=hex
|
||||
ufm1_ebr=
|
||||
mem_size1=1
|
||||
ufm1_init=0
|
||||
memfile1=
|
||||
ufm1_dt=hex
|
||||
ufm2_ebr=
|
||||
mem_size2=1
|
||||
ufm2_init=0
|
||||
memfile2=
|
||||
ufm2_dt=hex
|
||||
ufm3_ebr=
|
||||
mem_size3=1
|
||||
ufm3_init=0
|
||||
memfile3=
|
||||
ufm3_dt=hex
|
||||
ufm_cfg0_ebr=
|
||||
mem_size_cfg0=1
|
||||
ufm_cfg0_init=0
|
||||
memfile_cfg0=
|
||||
ufm_cfg0_dt=hex
|
||||
ufm_cfg1_ebr=
|
||||
mem_size_cfg1=1
|
||||
ufm_cfg1_init=0
|
||||
memfile_cfg1=
|
||||
ufm_cfg1_dt=hex
|
||||
wb=1
|
||||
boot_option=Internal
|
||||
efb_ufm=0
|
||||
boot_option_internal=Single Boot
|
||||
internal_ufm0=0
|
||||
internal_ufm1=0
|
||||
efb_ufm_boot=
|
||||
tamperdr=0
|
||||
t_pwd=0
|
||||
t_lockflash=0
|
||||
t_manmode=0
|
||||
t_jtagport=0
|
||||
t_sspiport=0
|
||||
t_sic2port=0
|
||||
t_wbport=0
|
||||
t_portlock=0
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
31
CPLD/LCMXO2-1200HC/REFB.naf
Normal file
31
CPLD/LCMXO2-1200HC/REFB.naf
Normal file
@ -0,0 +1,31 @@
|
||||
wb_clk_i i
|
||||
wb_rst_i i
|
||||
wb_cyc_i i
|
||||
wb_stb_i i
|
||||
wb_we_i i
|
||||
wb_adr_i[7] i
|
||||
wb_adr_i[6] i
|
||||
wb_adr_i[5] i
|
||||
wb_adr_i[4] i
|
||||
wb_adr_i[3] i
|
||||
wb_adr_i[2] i
|
||||
wb_adr_i[1] i
|
||||
wb_adr_i[0] i
|
||||
wb_dat_i[7] i
|
||||
wb_dat_i[6] i
|
||||
wb_dat_i[5] i
|
||||
wb_dat_i[4] i
|
||||
wb_dat_i[3] i
|
||||
wb_dat_i[2] i
|
||||
wb_dat_i[1] i
|
||||
wb_dat_i[0] i
|
||||
wb_dat_o[7] o
|
||||
wb_dat_o[6] o
|
||||
wb_dat_o[5] o
|
||||
wb_dat_o[4] o
|
||||
wb_dat_o[3] o
|
||||
wb_dat_o[2] o
|
||||
wb_dat_o[1] o
|
||||
wb_dat_o[0] o
|
||||
wb_ack_o o
|
||||
wbc_ufm_irq o
|
||||
1
CPLD/LCMXO2-1200HC/REFB.sort
Normal file
1
CPLD/LCMXO2-1200HC/REFB.sort
Normal file
@ -0,0 +1 @@
|
||||
REFB.v
|
||||
26
CPLD/LCMXO2-1200HC/REFB.srp
Normal file
26
CPLD/LCMXO2-1200HC/REFB.srp
Normal file
@ -0,0 +1,26 @@
|
||||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Sep 20 04:45:58 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Element Usage :
|
||||
EFB : 1
|
||||
Estimated Resource Usage:
|
||||
BIN
CPLD/LCMXO2-1200HC/REFB.sym
Normal file
BIN
CPLD/LCMXO2-1200HC/REFB.sym
Normal file
Binary file not shown.
113
CPLD/LCMXO2-1200HC/REFB.v
Normal file
113
CPLD/LCMXO2-1200HC/REFB.v
Normal file
@ -0,0 +1,113 @@
|
||||
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 */
|
||||
/* Wed Sep 20 04:45:58 2023 */
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
|
||||
wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
|
||||
input wire wb_clk_i;
|
||||
input wire wb_rst_i;
|
||||
input wire wb_cyc_i;
|
||||
input wire wb_stb_i;
|
||||
input wire wb_we_i;
|
||||
input wire [7:0] wb_adr_i;
|
||||
input wire [7:0] wb_dat_i;
|
||||
output wire [7:0] wb_dat_o;
|
||||
output wire wb_ack_o;
|
||||
output wire wbc_ufm_irq;
|
||||
|
||||
wire scuba_vhi;
|
||||
wire scuba_vlo;
|
||||
|
||||
VHI scuba_vhi_inst (.Z(scuba_vhi));
|
||||
|
||||
VLO scuba_vlo_inst (.Z(scuba_vlo));
|
||||
|
||||
defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
|
||||
defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem" ;
|
||||
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ;
|
||||
defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ;
|
||||
defparam EFBInst_0.UFM_INIT_PAGES = 321 ;
|
||||
defparam EFBInst_0.DEV_DENSITY = "1200L" ;
|
||||
defparam EFBInst_0.EFB_UFM = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
|
||||
defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
|
||||
defparam EFBInst_0.TC_ICR_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_OCR_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_OV_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
|
||||
defparam EFBInst_0.TC_RESETN = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
|
||||
defparam EFBInst_0.TC_OCR_SET = 32767 ;
|
||||
defparam EFBInst_0.TC_TOP_SET = 65535 ;
|
||||
defparam EFBInst_0.GSR = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_CCLK_SEL = 1 ;
|
||||
defparam EFBInst_0.TC_MODE = "CTCM" ;
|
||||
defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
|
||||
defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
|
||||
defparam EFBInst_0.EFB_TC = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.SPI_MODE = "MASTER" ;
|
||||
defparam EFBInst_0.EFB_SPI = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
|
||||
defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
|
||||
defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
|
||||
defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
|
||||
defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
|
||||
defparam EFBInst_0.EFB_WB_CLK_FREQ = "14.4" ;
|
||||
EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
|
||||
.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
|
||||
.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
|
||||
.WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]),
|
||||
.WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]),
|
||||
.WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]),
|
||||
.WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo),
|
||||
.PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo),
|
||||
.PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo),
|
||||
.PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo),
|
||||
.PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
|
||||
.PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
|
||||
.PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo),
|
||||
.I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo),
|
||||
.SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo),
|
||||
.SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo),
|
||||
.UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]),
|
||||
.WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]),
|
||||
.WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]),
|
||||
.WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(),
|
||||
.PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(),
|
||||
.PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
|
||||
.PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(),
|
||||
.I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(),
|
||||
.I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(),
|
||||
.SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(),
|
||||
.SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(),
|
||||
.SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(),
|
||||
.WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY());
|
||||
|
||||
|
||||
|
||||
// exemplar begin
|
||||
// exemplar end
|
||||
|
||||
endmodule
|
||||
44
CPLD/LCMXO2-1200HC/REFB_generate.log
Normal file
44
CPLD/LCMXO2-1200HC/REFB_generate.log
Normal file
@ -0,0 +1,44 @@
|
||||
Starting process: Module
|
||||
|
||||
Starting process:
|
||||
|
||||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Sep 20 04:45:58 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
File: REFB.lpc created.
|
||||
|
||||
|
||||
End process: completed successfully.
|
||||
|
||||
|
||||
Total Warnings: 0
|
||||
|
||||
Total Errors: 0
|
||||
|
||||
|
||||
8
CPLD/LCMXO2-1200HC/REFB_tmpl.v
Normal file
8
CPLD/LCMXO2-1200HC/REFB_tmpl.v
Normal file
@ -0,0 +1,8 @@
|
||||
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* Wed Sep 20 04:45:58 2023 */
|
||||
|
||||
/* parameterized module instance */
|
||||
REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),
|
||||
.wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ),
|
||||
.wbc_ufm_irq( ));
|
||||
2574
CPLD/LCMXO2-1200HC/_math_real.vhd
Normal file
2574
CPLD/LCMXO2-1200HC/_math_real.vhd
Normal file
File diff suppressed because it is too large
Load Diff
100
CPLD/LCMXO2-1200HC/generate_core.tcl
Normal file
100
CPLD/LCMXO2-1200HC/generate_core.tcl
Normal file
@ -0,0 +1,100 @@
|
||||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
proc GetCmdLine {lpcfile} {
|
||||
global Para
|
||||
|
||||
if [catch {open $lpcfile r} fileid] {
|
||||
puts "Cannot open $para_file file!"
|
||||
exit -1
|
||||
}
|
||||
|
||||
seek $fileid 0 start
|
||||
set default_match 0
|
||||
while {[gets $fileid line] >= 0} {
|
||||
if {[string first "\[Command\]" $line] == 0} {
|
||||
set default_match 1
|
||||
continue
|
||||
}
|
||||
if {[string first "\[" $line] == 0} {
|
||||
set default_match 0
|
||||
}
|
||||
if {$default_match == 1} {
|
||||
if [regexp {([^=]*)=(.*)} $line match parameter value] {
|
||||
if [regexp {([ |\t]*;)} $parameter match] {continue}
|
||||
if [regexp {(.*)[ |\t]*;} $value match temp] {
|
||||
set Para($parameter) $temp
|
||||
} else {
|
||||
set Para($parameter) $value
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
set default_match 0
|
||||
close $fileid
|
||||
|
||||
return $Para(cmd_line)
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
|
||||
set scuba "$Para(FPGAPath)/scuba"
|
||||
set modulename "REFB"
|
||||
set lang "verilog"
|
||||
set lpcfile "$Para(sbp_path)/$modulename.lpc"
|
||||
set arch "xo2c00"
|
||||
set cmd_line [GetCmdLine $lpcfile]
|
||||
set fdcfile "$Para(sbp_path)/$modulename.fdc"
|
||||
if {[file exists $fdcfile] == 0} {
|
||||
append scuba " " $cmd_line
|
||||
} else {
|
||||
append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
|
||||
}
|
||||
set Para(result) [catch {eval exec "$scuba"} msg]
|
||||
#puts $msg
|
||||
74
CPLD/LCMXO2-1200HC/generate_ngd.tcl
Normal file
74
CPLD/LCMXO2-1200HC/generate_ngd.tcl
Normal file
@ -0,0 +1,74 @@
|
||||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
|
||||
|
||||
set Para(ModuleName) "REFB"
|
||||
set Para(Module) "EFB"
|
||||
set Para(libname) machxo2
|
||||
set Para(arch_name) xo2c00
|
||||
set Para(PartType) "LCMXO2-1200HC"
|
||||
|
||||
set Para(tech_syn) machxo2
|
||||
set Para(tech_cae) machxo2
|
||||
set Para(Package) "TQFP100"
|
||||
set Para(SpeedGrade) "4"
|
||||
set Para(FMax) "100"
|
||||
set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
|
||||
|
||||
#edif2ngd
|
||||
set edif2ngd "$Para(FPGAPath)/edif2ngd"
|
||||
set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
|
||||
#puts $msg
|
||||
|
||||
#ngdbuild
|
||||
set ngdbuild "$Para(FPGAPath)/ngdbuild"
|
||||
set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
|
||||
#puts $msg
|
||||
78
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt
Normal file
78
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt
Normal file
@ -0,0 +1,78 @@
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Thu Sep 21 05:35:26 2023 *
|
||||
NOTE DESIGN NAME: RAM2E *
|
||||
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS LED : 35 : out *
|
||||
NOTE PINS C14M : 62 : in *
|
||||
NOTE PINS DQMH : 49 : out *
|
||||
NOTE PINS DQML : 48 : out *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||