Apple-2-HW
/
RAM2E
mirror of https://github.com/garrettsworkshop/RAM2E.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Compare commits

base: Apple-2-HW:4abb0873bf2d12c7aff326d42343f6de60f46c05
Branches Tags
Apple-2-HW:release-GW4203B
Apple-2-HW:dev-GW4203B
Apple-2-HW:RC-GW4203B
Apple-2-HW:release-GW4203A
Apple-2-HW:B.1.3
Apple-2-HW:B.1.2
Apple-2-HW:B.1.1
Apple-2-HW:B.1.0
Apple-2-HW:A.1.0
...
compare: Apple-2-HW:2adbbb15175b999bc912526badbb990817a38574
Branches Tags
Apple-2-HW:dev-GW4203B
Apple-2-HW:release-GW4203B
Apple-2-HW:RC-GW4203B
Apple-2-HW:release-GW4203A
Apple-2-HW:B.1.3
Apple-2-HW:B.1.2
Apple-2-HW:B.1.1
Apple-2-HW:B.1.0
Apple-2-HW:A.1.0

15 Commits
4abb0873bf ... 2adbbb1517

Author SHA1 Message Date
Zane Kaminski 2adbbb1517 Just formatting changes, MAX II/V POF files identical 2024-02-15 13:46:36 -05:00
Zane Kaminski 48d821e7b4 Create Timing.png 2024-02-15 13:46:08 -05:00
Zane Kaminski 73d958c1f8 RC 2024-02-12 17:13:24 -05:00
Zane Kaminski 1937ad85e2 Firmware RC 2024-02-07 21:12:43 -05:00
Zane Kaminski 21a04dedb5 Small board revision, still v2.0 2024-02-07 20:48:53 -05:00
Zane Kaminski 5e32b9cbe9 change nVOE to be solely falling-edge register output 2024-01-31 09:44:04 -05:00
Zane Kaminski 4450161b76 Update Makefile 2024-01-31 09:40:11 -05:00
Zane Kaminski 82c12e351f Change BOM to separate U4 from U3 and U5 2024-01-30 21:02:30 -05:00
Zane Kaminski 1ec43a5a39 Delete duplicate files 2024-01-30 21:02:16 -05:00
Zane Kaminski ab6dd7bbb1 Update Makefile 2024-01-30 21:01:53 -05:00
Zane Kaminski 0bc28d5c8a nVOE change 2024-01-27 17:27:22 -05:00
Zane Kaminski 4d22a0dae6 Create Timing.json 2024-01-27 17:27:15 -05:00
Zane Kaminski 9faa06b94f Add back qws files 2024-01-19 09:33:20 -05:00
Zane Kaminski f021148c5d Fix comments 2024-01-19 09:33:12 -05:00
Zane Kaminski 5335a6ed3c fix comment 2024-01-19 06:30:04 -05:00
84 changed files with 192209 additions and 111464 deletions
Show Stats Expand all files Collapse all files

13
CPLD/MAXII/RAM2E.qsf
View File

@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:26:23 AUGUST 20, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@ -50,9 +50,10 @@ set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_location_assignment PIN_12 -to C14M
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M
@ -110,7 +111,7 @@ set_location_assignment PIN_55 -to nDOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDOE
set_location_assignment PIN_77 -to Dout[0]
set_location_assignment PIN_76 -to Dout[1]
@ -128,8 +129,8 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
set_location_assignment PIN_50 -to nVOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nVOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nVOE
set_location_assignment PIN_70 -to Vout[0]
set_location_assignment PIN_67 -to Vout[1]
@ -234,10 +235,10 @@ set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_location_assignment PIN_88 -to LED
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
set_global_assignment -name VERILOG_FILE ../RAM2E.v
set_global_assignment -name VERILOG_FILE "../UFM-MAX.v"
set_global_assignment -name QIP_FILE UFM.qip

BIN
CPLD/MAXII/RAM2E.qws Normal file
View File

Binary file not shown.

48
CPLD/MAXII/output_files/RAM2E.asm.rpt
View File

@ -1,6 +1,6 @@
Assembler report for RAM2E
Tue Jan 16 14:28:02 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:27 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof
5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof
6. Assembler Messages
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Jan 16 14:28:02 2024 ;
; Assembler Status ; Successful - Thu Feb 15 04:16:27 2024 ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
+--------+---------+---------------+
+--------------------------------------------------+
; Assembler Generated Files ;
+--------------------------------------------------+
; File Name ;
+--------------------------------------------------+
; Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
+--------------------------------------------------+
+------------------------------------------------+
; Assembler Generated Files ;
+------------------------------------------------+
; File Name ;
+------------------------------------------------+
; /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
+------------------------------------------------+
+----------------------------------------------------------------------------+
; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
+----------------+-----------------------------------------------------------+
; Option ; Setting ;
+----------------+-----------------------------------------------------------+
; JTAG usercode ; 0x00164FC2 ;
; Checksum ; 0x0016533A ;
+----------------+-----------------------------------------------------------+
+--------------------------------------------------------------------------+
; Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
+----------------+---------------------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------------------+
; JTAG usercode ; 0x00164C21 ;
; Checksum ; 0x00165119 ;
+----------------+---------------------------------------------------------+
+--------------------+
@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Tue Jan 16 14:28:01 2024
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:16:25 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 13074 megabytes
Info: Processing ended: Tue Jan 16 14:28:02 2024
Info: Elapsed time: 00:00:01
Info: Peak virtual memory: 13103 megabytes
Info: Processing ended: Thu Feb 15 04:16:27 2024
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01

2
CPLD/MAXII/output_files/RAM2E.done
View File

@ -1 +1 @@
Tue Jan 16 14:28:05 2024
Thu Feb 15 04:16:32 2024

257
CPLD/MAXII/output_files/RAM2E.fit.rpt
View File

@ -1,6 +1,6 @@
Fitter report for RAM2E
Tue Jan 16 14:28:00 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:23 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-------------------------------------------------------------+
; Fitter Status ; Successful - Tue Jan 16 14:28:00 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 80 ( 88 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Thu Feb 15 04:16:23 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 80 ( 88 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
@ -129,20 +129,20 @@ https://fpgasoftware.intel.com/eula.
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.04 ;
; Average used ; 1.03 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 1.7% ;
; Processors 3-4 ; 1.2% ;
; Processor 2 ; 1.2% ;
; Processors 3-4 ; 1.0% ;
+----------------------------+-------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
+---------------------------------------------------------------------+
@ -156,9 +156,9 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; -- Combinational with a register ; 107 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 115 ;
; -- 3 input functions ; 55 ;
; -- 2 input functions ; 45 ;
; -- 4 input functions ; 116 ;
; -- 3 input functions ; 53 ;
; -- 2 input functions ; 46 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
@ -167,7 +167,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 14 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 24 ;
; -- synchronous clear/load mode ; 26 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 126 / 240 ( 53 % ) ;
@ -185,10 +185,10 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; Global signals ; 2 ;
; -- Global clocks ; 2 / 4 ( 50 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 28.6% / 30.2% / 27.0% ;
; Peak interconnect usage (total/H/V) ; 28.6% / 30.2% / 27.0% ;
; Average interconnect usage (total/H/V) ; 29.9% / 32.0% / 27.7% ;
; Peak interconnect usage (total/H/V) ; 29.9% / 32.0% / 27.7% ;
; Maximum fan-out ; 122 ;
; Highest non-global fan-out ; 35 ;
; Highest non-global fan-out ; 34 ;
; Total fan-out ; 992 ;
; Average fan-out ; 3.21 ;
+---------------------------------------------+-----------------------+
@ -208,18 +208,18 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 122 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 14 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 15 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 7 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
@ -242,7 +242,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
@ -255,20 +255,20 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRWEout ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRWEout ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -279,7 +279,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; RD[0] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[2] ; 99 ; 2 ; 2 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; RDOE ; - ;
; RD[2] ; 99 ; 2 ; 2 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[4] ; 91 ; 2 ; 4 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[5] ; 92 ; 2 ; 3 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
@ -352,12 +352,12 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; On ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; On ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
@ -428,8 +428,8 @@ Note: User assignments will override these defaults. The user specified values a
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; |RAM2E ; 238 (183) ; 126 ; 1 ; 70 ; 0 ; 112 (89) ; 19 (16) ; 107 (78) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 55 (55) ; 32 ; 1 ; 0 ; 0 ; 23 (23) ; 3 (3) ; 29 (29) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |RAM2E ; 238 (182) ; 126 ; 1 ; 70 ; 0 ; 112 (88) ; 19 (16) ; 107 (78) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 56 (56) ; 32 ; 1 ; 0 ; 0 ; 24 (24) ; 3 (3) ; 29 (29) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
@ -492,7 +492,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RD[7] ; Bidir ; (0) ;
; nEN80 ; Input ; (0) ;
; nWE ; Input ; (0) ;
; PHI1 ; Input ; (1) ;
; Ain[0] ; Input ; (0) ;
; Ain[1] ; Input ; (0) ;
; Ain[2] ; Input ; (0) ;
@ -504,6 +503,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; C14M ; Input ; (0) ;
; Din[0] ; Input ; (0) ;
; Din[6] ; Input ; (0) ;
; PHI1 ; Input ; (1) ;
; Din[1] ; Input ; (0) ;
; Din[5] ; Input ; (0) ;
; Din[7] ; Input ; (0) ;
@ -519,22 +519,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
; BA[0]~0 ; LC_X2_Y2_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
; BA[0]~1 ; LC_X5_Y2_N0 ; 3 ; Clock enable ; no ; -- ; -- ;
; BA[0]~0 ; LC_X2_Y3_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
; BA[0]~1 ; LC_X4_Y3_N9 ; 3 ; Clock enable ; no ; -- ; -- ;
; C14M ; PIN_12 ; 122 ; Clock ; yes ; Global Clock ; GCLK0 ;
; CS[0]~2 ; LC_X6_Y2_N2 ; 3 ; Clock enable ; no ; -- ; -- ;
; DQML~0 ; LC_X2_Y4_N0 ; 2 ; Clock enable ; no ; -- ; -- ;
; Equal1~1 ; LC_X7_Y4_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal1~2 ; LC_X7_Y4_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
; Mux14~0 ; LC_X5_Y2_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI1 ; PIN_37 ; 7 ; Clock ; yes ; Global Clock ; GCLK3 ;
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X2_Y1_N4 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X4_Y1_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X6_Y2_N6 ; 16 ; Clock enable ; no ; -- ; -- ;
; RA[1]~2 ; LC_X2_Y2_N8 ; 6 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X6_Y4_N2 ; 8 ; Output enable ; no ; -- ; -- ;
; S[0] ; LC_X7_Y2_N3 ; 32 ; Sync. clear ; no ; -- ; -- ;
; S[3] ; LC_X7_Y3_N8 ; 35 ; Sync. clear ; no ; -- ; -- ;
; CS[0]~2 ; LC_X4_Y2_N7 ; 3 ; Clock enable ; no ; -- ; -- ;
; DQML~0 ; LC_X2_Y4_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
; Equal1~1 ; LC_X4_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal1~2 ; LC_X6_Y3_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
; Mux14~0 ; LC_X2_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI1 ; PIN_37 ; 5 ; Clock ; yes ; Global Clock ; GCLK3 ;
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X6_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X3_Y1_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X4_Y2_N0 ; 16 ; Clock enable ; no ; -- ; -- ;
; RA[1]~2 ; LC_X2_Y3_N1 ; 6 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X5_Y4_N7 ; 8 ; Output enable ; no ; -- ; -- ;
; S[0] ; LC_X6_Y4_N8 ; 32 ; Sync. clear ; no ; -- ; -- ;
; S[3] ; LC_X6_Y4_N1 ; 34 ; Sync. clear ; no ; -- ; -- ;
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
@ -544,7 +544,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; C14M ; PIN_12 ; 122 ; Global Clock ; GCLK0 ;
; PHI1 ; PIN_37 ; 7 ; Global Clock ; GCLK3 ;
; PHI1 ; PIN_37 ; 5 ; Global Clock ; GCLK3 ;
+------+----------+---------+----------------------+------------------+
@ -553,13 +553,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
; C4s ; 169 / 784 ( 22 % ) ;
; Direct links ; 52 / 888 ( 6 % ) ;
; C4s ; 173 / 784 ( 22 % ) ;
; Direct links ; 43 / 888 ( 5 % ) ;
; Global clocks ; 2 / 4 ( 50 % ) ;
; LAB clocks ; 7 / 32 ( 22 % ) ;
; LUT chains ; 3 / 216 ( 1 % ) ;
; Local interconnects ; 351 / 888 ( 40 % ) ;
; R4s ; 168 / 704 ( 24 % ) ;
; LUT chains ; 7 / 216 ( 3 % ) ;
; Local interconnects ; 340 / 888 ( 38 % ) ;
; R4s ; 174 / 704 ( 25 % ) ;
+-----------------------+--------------------+
@ -575,29 +575,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 2 ;
; 10 ; 22 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 23 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.58) ; Number of LABs (Total = 24) ;
; LAB-wide Signals (Average = 1.50) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+
; 1 Clock ; 22 ;
; 1 Clock enable ; 11 ;
; 1 Clock enable ; 9 ;
; 1 Sync. clear ; 2 ;
; 2 Clock enables ; 2 ;
; 2 Clocks ; 1 ;
; 2 Clock enables ; 3 ;
+------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 10.17) ; Number of LABs (Total = 24) ;
; Number of Signals Sourced (Average = 10.13) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
@ -607,10 +606,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 2 ;
; 10 ; 20 ;
; 11 ; 1 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 22 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
@ -621,18 +620,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 7.50) ; Number of LABs (Total = 24) ;
; Number of Signals Sourced Out (Average = 7.08) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 6 ;
; 7 ; 2 ;
; 8 ; 4 ;
; 9 ; 6 ;
; 5 ; 3 ;
; 6 ; 3 ;
; 7 ; 4 ;
; 8 ; 5 ;
; 9 ; 3 ;
; 10 ; 2 ;
; 11 ; 0 ;
; 12 ; 1 ;
@ -642,33 +641,31 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 12.88) ; Number of LABs (Total = 24) ;
; Number of Distinct Inputs (Average = 12.50) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 2 ;
; 11 ; 5 ;
; 12 ; 2 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 2 ;
; 10 ; 1 ;
; 11 ; 4 ;
; 12 ; 3 ;
; 13 ; 1 ;
; 14 ; 2 ;
; 15 ; 1 ;
; 16 ; 1 ;
; 17 ; 1 ;
; 18 ; 3 ;
; 15 ; 0 ;
; 16 ; 2 ;
; 17 ; 0 ;
; 18 ; 1 ;
; 19 ; 1 ;
; 20 ; 0 ;
; 21 ; 0 ;
; 22 ; 0 ;
; 23 ; 0 ;
; 24 ; 1 ;
; 21 ; 2 ;
; 22 ; 1 ;
+----------------------------------------------+------------------------------+
@ -713,53 +710,51 @@ Info (332111): Found 3 clocks
Info (332111): 200.000 ram2e_ufm|ARCLK|regout
Info (332111): 200.000 ram2e_ufm|DRCLK|regout
Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186217): Destination "nVOE~0" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 59
Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 20
Info (186217): Destination "S~2" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 19
Info (186217): Destination "S[2]~9" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 21
Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 20
Info (186217): Destination "S~0" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 19
Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes
Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
Info (170193): Fitter routing operations beginning
Info (170089): 5e+01 ns of routing delay (approximately 3.1% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
Info (170089): 5e+01 ns of routing delay (approximately 3.3% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
Info (170195): Router estimated average interconnect usage is 26% of the available device resources
Info (170196): Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.52 seconds.
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.97 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings
Info: Peak virtual memory: 13751 megabytes
Info: Processing ended: Tue Jan 16 14:28:00 2024
Info: Elapsed time: 00:00:04
Info: Peak virtual memory: 13770 megabytes
Info: Processing ended: Thu Feb 15 04:16:23 2024
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:04
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg.
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg.

4
CPLD/MAXII/output_files/RAM2E.fit.summary
View File

@ -1,5 +1,5 @@
Fitter Status : Successful - Tue Jan 16 14:28:00 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Fitter Status : Successful - Thu Feb 15 04:16:23 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX II

48
CPLD/MAXII/output_files/RAM2E.flow.rpt
View File

@ -1,6 +1,6 @@
Flow report for RAM2E
Tue Jan 16 14:28:05 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:31 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+-------------------------------------------------------------+
; Flow Status ; Successful - Tue Jan 16 14:28:02 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 80 ( 88 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Feb 15 04:16:27 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 80 ( 88 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+-----------------------------------------+
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 01/16/2024 14:27:30 ;
; Start date & time ; 02/15/2024 04:15:27 ;
; Main task ; Compilation ;
; Revision Name ; RAM2E ;
+-------------------+---------------------+
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------+------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 121381084694.170543325000956 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 121380219419.170798852707820 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:25 ; 1.0 ; 13117 MB ; 00:00:42 ;
; Fitter ; 00:00:04 ; 1.0 ; 13751 MB ; 00:00:04 ;
; Assembler ; 00:00:01 ; 1.0 ; 13070 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13069 MB ; 00:00:01 ;
; Total ; 00:00:32 ; -- ; -- ; 00:00:48 ;
; Analysis & Synthesis ; 00:00:47 ; 1.0 ; 13146 MB ; 00:00:47 ;
; Fitter ; 00:00:08 ; 1.0 ; 13770 MB ; 00:00:04 ;
; Assembler ; 00:00:02 ; 1.0 ; 13099 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13089 MB ; 00:00:02 ;
; Total ; 00:00:59 ; -- ; -- ; 00:00:54 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+

2
CPLD/MAXII/output_files/RAM2E.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="f1177731eb35f907c990"/>
<hash md5_digest_80b="c40857e37f967e83d8af"/>
</project>
<file_info>
<file device="EPM240T100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>

114
CPLD/MAXII/output_files/RAM2E.map.rpt
View File

@ -1,6 +1,6 @@
Analysis & Synthesis report for RAM2E
Tue Jan 16 14:27:55 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:13 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Jan 16 14:27:55 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Total logic elements ; 252 ;
; Total pins ; 70 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Feb 15 04:16:13 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Total logic elements ; 252 ;
; Total pins ; 70 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
@ -146,16 +146,16 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
; ../RAM2E.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/RAM2E.v ; ;
; ../UFM-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/UFM-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2E/CPLD/MAXII/UFM.v ; ;
; ../RAM2E.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2E/CPLD/RAM2E.mif ; ;
+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+
; ../RAM2E.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v ; ;
; ../UFM-MAX.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v ; ;
; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.mif ; ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+
+-----------------------------------------------------+
@ -169,9 +169,9 @@ https://fpgasoftware.intel.com/eula.
; -- Combinational with a register ; 93 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 115 ;
; -- 3 input functions ; 55 ;
; -- 2 input functions ; 45 ;
; -- 4 input functions ; 116 ;
; -- 3 input functions ; 53 ;
; -- 2 input functions ; 46 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
@ -199,8 +199,8 @@ https://fpgasoftware.intel.com/eula.
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; |RAM2E ; 252 (192) ; 126 ; 1 ; 70 ; 0 ; 126 (98) ; 33 (25) ; 93 (69) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 60 (60) ; 32 ; 1 ; 0 ; 0 ; 28 (28) ; 8 (8) ; 24 (24) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |RAM2E ; 252 (191) ; 126 ; 1 ; 70 ; 0 ; 126 (97) ; 33 (25) ; 93 (69) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 61 (61) ; 32 ; 1 ; 0 ; 0 ; 29 (29) ; 8 (8) ; 24 (24) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
@ -281,50 +281,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Tue Jan 16 14:27:30 2024
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:15:26 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ufm-max.v
Info (12023): Found entity 1: RAM2E_UFM File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v
Info (12023): Found entity 1: RAM2E File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ufm-max.v
Info (12023): Found entity 1: RAM2E_UFM File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Info (12023): Found entity 1: UFM_altufm_none_lbr File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 138
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 78
Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 136
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 77
Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "nCSout" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 77
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 75
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "nWE80" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 11
Warning (15610): No output dependent on input pin "nWE80" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 11
Info (21057): Implemented 323 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 22 input pins
Info (21059): Implemented 40 output pins
Info (21060): Implemented 8 bidirectional pins
Info (21061): Implemented 252 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Peak virtual memory: 13117 megabytes
Info: Processing ended: Tue Jan 16 14:27:55 2024
Info: Elapsed time: 00:00:25
Info: Total CPU time (on all processors): 00:00:42
Info: Peak virtual memory: 13146 megabytes
Info: Processing ended: Thu Feb 15 04:16:13 2024
Info: Elapsed time: 00:00:47
Info: Total CPU time (on all processors): 00:00:47
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg.
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg.

6
CPLD/MAXII/output_files/RAM2E.map.smsg
View File

@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at RAM2E.v(74): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 74
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189
Warning (10273): Verilog HDL warning at RAM2E.v(72): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 72
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189

4
CPLD/MAXII/output_files/RAM2E.map.summary
View File

@ -1,5 +1,5 @@
Analysis & Synthesis Status : Successful - Tue Jan 16 14:27:55 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Analysis & Synthesis Status : Successful - Thu Feb 15 04:16:13 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX II

2
CPLD/MAXII/output_files/RAM2E.pin
View File

@ -58,7 +58,7 @@
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
CHIP "RAM2E" ASSIGNED TO AN: EPM240T100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment

BIN
CPLD/MAXII/output_files/RAM2E.pof
View File

Binary file not shown.

520
CPLD/MAXII/output_files/RAM2E.sta.rpt
View File

@ -1,6 +1,6 @@
Timing Analyzer report for RAM2E
Tue Jan 16 14:28:05 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:31 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+---------------------------------------------------------------------+
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; RAM2E ;
; Device Family ; MAX II ;
; Device Name ; EPM240T100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+---------------------------------------------------------------------+
+-----------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; RAM2E ;
; Device Family ; MAX II ;
; Device Name ; EPM240T100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
+------------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+------------------+--------+--------------------------+
; ../RAM2E.sdc ; OK ; Tue Jan 16 14:28:04 2024 ;
; ../RAM2E-MAX.sdc ; OK ; Tue Jan 16 14:28:04 2024 ;
; ../RAM2E.sdc ; OK ; Thu Feb 15 04:16:31 2024 ;
; ../RAM2E-MAX.sdc ; OK ; Thu Feb 15 04:16:31 2024 ;
+------------------+--------+--------------------------+
@ -116,7 +116,7 @@ https://fpgasoftware.intel.com/eula.
+-----------+-----------------+------------------------+------+
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|ARCLK|regout ; ;
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|DRCLK|regout ; ;
; 68.96 MHz ; 68.96 MHz ; C14M ; ;
; 68.17 MHz ; 68.17 MHz ; C14M ; ;
+-----------+-----------------+------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@ -126,9 +126,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------+---------+---------------+
; ram2e_ufm|ARCLK|regout ; -23.682 ; -23.682 ;
; ram2e_ufm|DRCLK|regout ; -23.562 ; -23.562 ;
; C14M ; -8.731 ; -96.469 ;
; ram2e_ufm|ARCLK|regout ; -23.723 ; -23.723 ;
; ram2e_ufm|DRCLK|regout ; -23.713 ; -23.713 ;
; C14M ; -10.120 ; -109.885 ;
+------------------------+---------+---------------+
@ -137,9 +137,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------+---------+---------------+
; ram2e_ufm|DRCLK|regout ; -16.461 ; -16.461 ;
; ram2e_ufm|ARCLK|regout ; -16.317 ; -16.317 ;
; C14M ; 1.433 ; 0.000 ;
; ram2e_ufm|DRCLK|regout ; -16.306 ; -16.306 ;
; ram2e_ufm|ARCLK|regout ; -16.276 ; -16.276 ;
; C14M ; 1.415 ; 0.000 ;
+------------------------+---------+---------------+
@ -171,7 +171,7 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -23.682 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -1.630 ; 2.053 ;
; -23.723 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -2.195 ; 1.529 ;
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
@ -181,118 +181,118 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -23.562 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -1.497 ; 2.066 ;
; -23.538 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -1.497 ; 2.042 ;
; -23.713 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.165 ; 1.549 ;
; -23.693 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.165 ; 1.529 ;
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'C14M' ;
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; -8.731 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 9.896 ;
; -8.317 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 9.482 ;
; -8.260 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 9.425 ;
; -8.260 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 9.425 ;
; -8.260 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 9.425 ;
; -8.260 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 9.425 ;
; -8.260 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 9.425 ;
; -8.260 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 9.425 ;
; -8.260 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 9.425 ;
; -7.816 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 8.981 ;
; -7.814 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 8.979 ;
; -5.971 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.497 ; 7.136 ;
; 27.670 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.917 ;
; 27.670 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.917 ;
; 27.670 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.917 ;
; 27.813 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.774 ;
; 27.813 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.774 ;
; 27.813 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.774 ;
; 28.259 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.328 ;
; 28.259 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.328 ;
; 28.259 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.328 ;
; 28.266 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.321 ;
; 28.266 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.321 ;
; 28.266 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.321 ;
; 28.402 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.185 ;
; 28.402 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.185 ;
; 28.402 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.185 ;
; 28.409 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.178 ;
; 28.409 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.178 ;
; 28.409 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.178 ;
; 28.823 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.764 ;
; 28.823 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.764 ;
; 28.933 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.654 ;
; 28.933 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.654 ;
; 28.933 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.654 ;
; 28.943 ; S[1] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 5.644 ;
; 29.076 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.511 ;
; 29.076 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.511 ;
; 29.076 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.511 ;
; 29.412 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.175 ;
; 29.412 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.175 ;
; 29.419 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.168 ;
; 29.419 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.168 ;
; 30.003 ; S[3] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.584 ;
; 30.086 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.501 ;
; 30.086 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.501 ;
; 30.847 ; RA[11] ; RAr[11] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.740 ;
; 31.031 ; RA[9] ; RAr[9] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.556 ;
; 31.053 ; S[0] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 3.534 ;
; 31.540 ; S[2] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 3.047 ;
; 31.845 ; RA[10] ; RAr[10] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.742 ;
; 31.915 ; RA[8] ; RAr[8] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.672 ;
; 31.941 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.646 ;
; 32.280 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.307 ;
; 32.515 ; RA[4] ; RAr[4] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.072 ;
; 32.546 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.041 ;
; 32.578 ; RA[3] ; RAr[3] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.009 ;
; 32.601 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.986 ;
; 32.954 ; RA[0] ; RAr[0] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.633 ;
; 32.975 ; RA[6] ; RAr[6] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.612 ;
; 32.976 ; RA[5] ; RAr[5] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.611 ;
; 32.977 ; RA[7] ; RAr[7] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.610 ;
; 32.987 ; RA[1] ; RAr[1] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.600 ;
; 32.992 ; RA[2] ; RAr[2] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.595 ;
; 56.663 ; FS[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.845 ;
; 56.914 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.594 ;
; 57.077 ; FS[13] ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 69.841 ; 0.000 ; 12.431 ;
; 57.134 ; FS[13] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.374 ;
; 57.134 ; FS[13] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.374 ;
; 57.134 ; FS[13] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.374 ;
; 57.134 ; FS[13] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.374 ;
; 57.134 ; FS[13] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.374 ;
; 57.134 ; FS[13] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.374 ;
; 57.134 ; FS[13] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.374 ;
; 57.137 ; FS[13] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 12.371 ;
; 57.140 ; FS[13] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 12.368 ;
; 57.277 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.231 ;
; 57.328 ; FS[2] ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 69.841 ; 0.000 ; 12.180 ;
; 57.385 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.123 ;
; 57.385 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.123 ;
; 57.385 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.123 ;
; 57.385 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.123 ;
; 57.385 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.123 ;
; 57.385 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.123 ;
; 57.385 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.123 ;
; 57.388 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 12.120 ;
; 57.391 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 12.117 ;
; 57.670 ; S[1] ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 11.838 ;
; 57.671 ; S[1] ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 11.837 ;
; 57.748 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.760 ;
; 57.748 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.760 ;
; 57.748 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.760 ;
; 57.748 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.760 ;
; 57.748 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.760 ;
; 57.748 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.760 ;
; 57.748 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.760 ;
; 57.871 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.637 ;
; 57.875 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.633 ;
; 57.938 ; FS[14] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.570 ;
; 58.030 ; S[1] ; CmdLEDSet ; C14M ; C14M ; 69.841 ; 0.000 ; 11.478 ;
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'C14M' ;
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; -10.120 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.953 ;
; -10.120 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.953 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.027 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 10.860 ;
; -7.930 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.763 ;
; -7.925 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.758 ;
; -6.497 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 8.330 ;
; 27.586 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.001 ;
; 27.586 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.001 ;
; 27.729 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.858 ;
; 27.729 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.858 ;
; 27.800 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.787 ;
; 27.800 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.787 ;
; 28.220 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.367 ;
; 28.220 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.367 ;
; 28.226 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.361 ;
; 28.226 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.361 ;
; 28.226 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.361 ;
; 28.369 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.218 ;
; 28.369 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.218 ;
; 28.369 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.218 ;
; 28.440 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.147 ;
; 28.440 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.147 ;
; 28.440 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.147 ;
; 28.860 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.727 ;
; 28.860 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.727 ;
; 28.860 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.727 ;
; 28.910 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.677 ;
; 28.910 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.677 ;
; 28.910 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.677 ;
; 29.053 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.534 ;
; 29.053 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.534 ;
; 29.053 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.534 ;
; 29.124 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.463 ;
; 29.124 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.463 ;
; 29.124 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.463 ;
; 29.544 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.043 ;
; 29.544 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.043 ;
; 29.544 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.043 ;
; 29.726 ; S[1] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.861 ;
; 30.004 ; S[3] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.583 ;
; 30.351 ; S[2] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.236 ;
; 30.681 ; S[0] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 3.906 ;
; 31.064 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.523 ;
; 31.134 ; RA[10] ; RAr[10] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.453 ;
; 31.373 ; RA[9] ; RAr[9] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.214 ;
; 31.459 ; RA[8] ; RAr[8] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.128 ;
; 31.701 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.886 ;
; 31.732 ; S[3] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 2.855 ;
; 31.854 ; RA[11] ; RAr[11] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.733 ;
; 31.909 ; S[2] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 2.678 ;
; 31.932 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.655 ;
; 31.945 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.642 ;
; 32.013 ; S[0] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 2.574 ;
; 32.533 ; RA[3] ; RAr[3] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.054 ;
; 32.562 ; RA[6] ; RAr[6] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.025 ;
; 32.597 ; S[1] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 1.990 ;
; 32.955 ; RA[0] ; RAr[0] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.632 ;
; 32.974 ; RA[4] ; RAr[4] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.613 ;
; 32.977 ; RA[7] ; RAr[7] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.610 ;
; 32.979 ; RA[5] ; RAr[5] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.608 ;
; 32.980 ; RA[1] ; RAr[1] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.607 ;
; 32.981 ; RA[2] ; RAr[2] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.606 ;
; 55.823 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.685 ;
; 55.823 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.685 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.355 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 13.153 ;
; 56.360 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 13.148 ;
; 56.403 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.105 ;
; 56.403 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.105 ;
; 56.476 ; FS[15] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 13.032 ;
; 56.481 ; FS[15] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 13.027 ;
; 56.524 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.984 ;
; 56.524 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.984 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.916 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 69.841 ; 0.000 ; 12.592 ;
; 56.933 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.575 ;
; 56.933 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.575 ;
; 56.933 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.575 ;
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@ -300,8 +300,8 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -16.461 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -1.497 ; 2.042 ;
; -16.437 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -1.497 ; 2.066 ;
; -16.306 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.165 ; 1.529 ;
; -16.286 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.165 ; 1.549 ;
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
@ -311,117 +311,117 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -16.317 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -1.630 ; 2.053 ;
; -16.276 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -2.195 ; 1.529 ;
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'C14M' ;
+-------+-----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
; 1.433 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.654 ;
; 1.650 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 1.871 ;
; 1.668 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 1.889 ;
; 1.683 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.904 ;
; 1.685 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 1.906 ;
; 1.695 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.916 ;
; 1.696 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.917 ;
; 1.714 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.935 ;
; 1.808 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.029 ;
; 1.878 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.099 ;
; 1.912 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.133 ;
; 1.932 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 2.153 ;
; 1.935 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.156 ;
; 1.939 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.160 ;
; 1.962 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.183 ;
; 1.967 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.188 ;
; 1.974 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.195 ;
; 2.085 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.306 ;
; 2.107 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
; 2.108 ; RWBank[2] ; RA[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.329 ;
; 2.113 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.334 ;
; 2.116 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.337 ;
; 2.117 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.338 ;
; 2.126 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ;
; 2.139 ; RWSel ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 2.360 ;
; 2.144 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.365 ;
; 2.153 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.374 ;
; 2.159 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.380 ;
; 2.166 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.387 ;
; 2.177 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.398 ;
; 2.177 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.398 ;
; 2.180 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.401 ;
; 2.182 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.403 ;
; 2.231 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.452 ;
; 2.239 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
; 2.239 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
; 2.240 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ;
; 2.240 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ;
; 2.240 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ;
; 2.242 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.463 ;
; 2.248 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.469 ;
; 2.250 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.471 ;
; 2.252 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.473 ;
; 2.262 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.483 ;
; 2.263 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.484 ;
; 2.268 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.489 ;
; 2.274 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.495 ;
; 2.275 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.496 ;
; 2.276 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.497 ;
; 2.288 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.509 ;
; 2.334 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.555 ;
; 2.344 ; S[0] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.565 ;
; 2.398 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.619 ;
; 2.400 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.621 ;
; 2.491 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.712 ;
; 2.516 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.737 ;
; 2.521 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.742 ;
; 2.537 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.758 ;
; 2.545 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.766 ;
; 2.633 ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.854 ;
; 2.657 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.878 ;
; 2.661 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.882 ;
; 2.684 ; PHI1r ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.905 ;
; 2.751 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.972 ;
; 2.766 ; S[3] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.987 ;
; 2.767 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.988 ;
; 2.768 ; S[3] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.989 ;
; 2.834 ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.055 ;
; 2.859 ; S[0] ; RA[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.080 ;
; 2.868 ; S[1] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.089 ;
; 2.873 ; RWBank[0] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.094 ;
; 2.874 ; RWBank[0] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.095 ;
; 2.918 ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.139 ;
; 2.945 ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.166 ;
; 2.945 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.166 ;
; 2.948 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.169 ;
; 2.949 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.170 ;
; 2.950 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.171 ;
; 2.950 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.171 ;
; 2.976 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.197 ;
; 2.985 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.206 ;
; 2.991 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.212 ;
; 3.020 ; FS[11] ; RA[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.241 ;
; 3.038 ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.259 ;
; 3.039 ; RAM2E_UFM:ram2e_ufm|CmdBitbangMAX ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 3.260 ;
; 3.048 ; FS[10] ; RA[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.269 ;
; 3.059 ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.280 ;
; 3.059 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.280 ;
; 3.087 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.308 ;
; 3.096 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.317 ;
; 3.101 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.322 ;
; 3.102 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.323 ;
; 3.143 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.364 ;
; 3.143 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.364 ;
; 3.167 ; FS[15] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.388 ;
; 3.169 ; FS[15] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.390 ;
; 3.170 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.391 ;
; 3.171 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.392 ;
; 3.179 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ;
+-------+-----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'C14M' ;
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
; 1.415 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.636 ;
; 1.644 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.865 ;
; 1.650 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.871 ;
; 1.665 ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.886 ;
; 1.684 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 1.905 ;
; 1.701 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.922 ;
; 1.715 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.936 ;
; 1.914 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.135 ;
; 1.916 ; RWBank[2] ; RA[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.137 ;
; 1.968 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.189 ;
; 1.971 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.192 ;
; 1.973 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.194 ;
; 1.973 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.194 ;
; 1.979 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.200 ;
; 2.026 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.247 ;
; 2.107 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
; 2.107 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
; 2.125 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.346 ;
; 2.127 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.348 ;
; 2.134 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.355 ;
; 2.144 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.365 ;
; 2.151 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.372 ;
; 2.153 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.374 ;
; 2.170 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.391 ;
; 2.174 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.395 ;
; 2.175 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.396 ;
; 2.189 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.410 ;
; 2.190 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.411 ;
; 2.207 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.428 ;
; 2.214 ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.435 ;
; 2.222 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.443 ;
; 2.222 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 2.443 ;
; 2.228 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.449 ;
; 2.233 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.454 ;
; 2.239 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
; 2.239 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
; 2.240 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ;
; 2.240 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ;
; 2.248 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.469 ;
; 2.249 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.470 ;
; 2.250 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.471 ;
; 2.255 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.476 ;
; 2.259 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.480 ;
; 2.262 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.483 ;
; 2.271 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.492 ;
; 2.273 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.494 ;
; 2.286 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.507 ;
; 2.345 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.566 ;
; 2.346 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.567 ;
; 2.362 ; S[1] ; RDOE ; C14M ; C14M ; 0.000 ; 0.000 ; 2.583 ;
; 2.417 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.638 ;
; 2.455 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.676 ;
; 2.486 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.707 ;
; 2.528 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.749 ;
; 2.544 ; RWSel ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 2.765 ;
; 2.551 ; PHI1r ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.772 ;
; 2.552 ; PHI1r ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.773 ;
; 2.553 ; PHI1r ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.774 ;
; 2.555 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.776 ;
; 2.621 ; RAM2E_UFM:ram2e_ufm|UFMErase ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.842 ;
; 2.633 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.854 ;
; 2.722 ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.943 ;
; 2.838 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 3.059 ;
; 2.839 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.060 ;
; 2.842 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.063 ;
; 2.843 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.064 ;
; 2.855 ; RWBank[6] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.076 ;
; 2.860 ; RWBank[5] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.081 ;
; 2.921 ; RAM2E_UFM:ram2e_ufm|UFMErase ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.142 ;
; 2.938 ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.159 ;
; 2.957 ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.178 ;
; 2.966 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.187 ;
; 2.976 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.197 ;
; 2.983 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.204 ;
; 2.985 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.206 ;
; 2.994 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.215 ;
; 3.005 ; S[1] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.226 ;
; 3.014 ; S[1] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.235 ;
; 3.015 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.236 ;
; 3.016 ; S[1] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.237 ;
; 3.077 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.298 ;
; 3.087 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.308 ;
; 3.094 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.315 ;
; 3.096 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.317 ;
; 3.096 ; FS[11] ; RA[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.317 ;
; 3.128 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.349 ;
; 3.129 ; S[3] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.350 ;
; 3.132 ; FS[0] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.353 ;
; 3.134 ; S[3] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.355 ;
; 3.155 ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.376 ;
; 3.172 ; RWBank[0] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.393 ;
; 3.173 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.394 ;
; 3.174 ; RWBank[0] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.395 ;
; 3.179 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ;
; 3.179 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ;
; 3.180 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.401 ;
; 3.188 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ;
; 3.188 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ;
; 3.202 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.423 ;
; 3.205 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.426 ;
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------+
@ -429,7 +429,7 @@ No paths to report.
+------------------------+------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------+------------------------+----------+----------+----------+----------+
; C14M ; C14M ; 1550 ; 0 ; 52 ; 0 ;
; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ;
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
@ -444,7 +444,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------------------+------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------+------------------------+----------+----------+----------+----------+
; C14M ; C14M ; 1550 ; 0 ; 52 ; 0 ;
; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ;
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
@ -474,9 +474,9 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 1 ; 1 ;
; Unconstrained Input Ports ; 28 ; 28 ;
; Unconstrained Input Port Paths ; 170 ; 170 ;
; Unconstrained Input Port Paths ; 169 ; 169 ;
; Unconstrained Output Ports ; 47 ; 47 ;
; Unconstrained Output Port Paths ; 84 ; 84 ;
; Unconstrained Output Port Paths ; 83 ; 83 ;
+---------------------------------+-------+------+
@ -679,8 +679,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Tue Jan 16 14:28:03 2024
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:16:29 2024
Info: Command: quartus_sta RAM2E-MAXII -c RAM2E
Info: qsta_default_script.tcl version: #1
Info (20032): Parallel compilation is enabled and will use up to 4 processors
@ -697,18 +697,18 @@ Info: Can't run Report Timing Closure Recommendations. The current device family
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -23.682
Info (332146): Worst-case setup slack is -23.723
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -23.682 -23.682 ram2e_ufm|ARCLK|regout
Info (332119): -23.562 -23.562 ram2e_ufm|DRCLK|regout
Info (332119): -8.731 -96.469 C14M
Info (332146): Worst-case hold slack is -16.461
Info (332119): -23.723 -23.723 ram2e_ufm|ARCLK|regout
Info (332119): -23.713 -23.713 ram2e_ufm|DRCLK|regout
Info (332119): -10.120 -109.885 C14M
Info (332146): Worst-case hold slack is -16.306
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -16.461 -16.461 ram2e_ufm|DRCLK|regout
Info (332119): -16.317 -16.317 ram2e_ufm|ARCLK|regout
Info (332119): 1.433 0.000 C14M
Info (332119): -16.306 -16.306 ram2e_ufm|DRCLK|regout
Info (332119): -16.276 -16.276 ram2e_ufm|ARCLK|regout
Info (332119): 1.415 0.000 C14M
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 34.654
@ -718,14 +718,12 @@ Info (332146): Worst-case minimum pulse width slack is 34.654
Info (332119): 70.000 0.000 ram2e_ufm|ARCLK|regout
Info (332119): 70.000 0.000 ram2e_ufm|DRCLK|regout
Info (332001): The selected device family is not supported by the report_metastability command.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 13069 megabytes
Info: Processing ended: Tue Jan 16 14:28:05 2024
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 13089 megabytes
Info: Processing ended: Thu Feb 15 04:16:31 2024
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
Info: Total CPU time (on all processors): 00:00:02

22
CPLD/MAXII/output_files/RAM2E.sta.summary
View File

@ -3,27 +3,27 @@ Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'ram2e_ufm|ARCLK|regout'
Slack : -23.682
TNS : -23.682
Slack : -23.723
TNS : -23.723
Type : Setup 'ram2e_ufm|DRCLK|regout'
Slack : -23.562
TNS : -23.562
Slack : -23.713
TNS : -23.713
Type : Setup 'C14M'
Slack : -8.731
TNS : -96.469
Slack : -10.120
TNS : -109.885
Type : Hold 'ram2e_ufm|DRCLK|regout'
Slack : -16.461
TNS : -16.461
Slack : -16.306
TNS : -16.306
Type : Hold 'ram2e_ufm|ARCLK|regout'
Slack : -16.317
TNS : -16.317
Slack : -16.276
TNS : -16.276
Type : Hold 'C14M'
Slack : 1.433
Slack : 1.415
TNS : 0.000
Type : Minimum Pulse Width 'C14M'

25
CPLD/MAXV/RAM2E.qsf
View File

@ -42,7 +42,7 @@ set_global_assignment -name DEVICE 5M240ZT100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:27:32 AUGUST 20, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@ -52,6 +52,8 @@ set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_location_assignment PIN_12 -to C14M
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M
@ -109,7 +111,7 @@ set_location_assignment PIN_55 -to nDOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDOE
set_location_assignment PIN_77 -to Dout[0]
set_location_assignment PIN_76 -to Dout[1]
@ -127,8 +129,8 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
set_location_assignment PIN_50 -to nVOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nVOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nVOE
set_location_assignment PIN_70 -to Vout[0]
set_location_assignment PIN_67 -to Vout[1]
@ -200,7 +202,18 @@ set_location_assignment PIN_16 -to RAout[10]
set_location_assignment PIN_7 -to RAout[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RAout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAout
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[0]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[1]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[2]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[3]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[4]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[5]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[6]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[7]
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout[8]
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout[9]
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout[10]
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RAout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RAout
@ -233,10 +246,10 @@ set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_location_assignment PIN_88 -to LED
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
set_global_assignment -name VERILOG_FILE ../RAM2E.v
set_global_assignment -name VERILOG_FILE "../UFM-MAX.v"
set_global_assignment -name QIP_FILE UFM.qip

BIN
CPLD/MAXV/RAM2E.qws Normal file
View File

Binary file not shown.

48
CPLD/MAXV/output_files/RAM2E.asm.rpt
View File

@ -1,6 +1,6 @@
Assembler report for RAM2E
Tue Jan 16 14:28:02 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:27 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof
5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof
6. Assembler Messages
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Jan 16 14:28:02 2024 ;
; Assembler Status ; Successful - Thu Feb 15 04:16:27 2024 ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
+--------+---------+---------------+
+-------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------+
; File Name ;
+-------------------------------------------------+
; Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
+-------------------------------------------------+
+-----------------------------------------------+
; Assembler Generated Files ;
+-----------------------------------------------+
; File Name ;
+-----------------------------------------------+
; /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
+-----------------------------------------------+
+---------------------------------------------------------------------------+
; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
+----------------+----------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------+
; JTAG usercode ; 0x00164C9F ;
; Checksum ; 0x00164F97 ;
+----------------+----------------------------------------------------------+
+-------------------------------------------------------------------------+
; Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
+----------------+--------------------------------------------------------+
; Option ; Setting ;
+----------------+--------------------------------------------------------+
; JTAG usercode ; 0x001651A7 ;
; Checksum ; 0x001654A7 ;
+----------------+--------------------------------------------------------+
+--------------------+
@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Tue Jan 16 14:28:02 2024
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:16:25 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 13072 megabytes
Info: Processing ended: Tue Jan 16 14:28:02 2024
Info: Elapsed time: 00:00:00
Info: Peak virtual memory: 13095 megabytes
Info: Processing ended: Thu Feb 15 04:16:27 2024
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01

2
CPLD/MAXV/output_files/RAM2E.done
View File

@ -1 +1 @@
Tue Jan 16 14:28:06 2024
Thu Feb 15 04:16:33 2024

263
CPLD/MAXV/output_files/RAM2E.fit.rpt
View File

@ -1,6 +1,6 @@
Fitter report for RAM2E
Tue Jan 16 14:28:00 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:23 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-------------------------------------------------------------+
; Fitter Status ; Successful - Tue Jan 16 14:28:00 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 79 ( 89 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Thu Feb 15 04:16:23 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 79 ( 89 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
@ -134,7 +134,7 @@ https://fpgasoftware.intel.com/eula.
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 1.2% ;
; Processor 2 ; 1.1% ;
; Processors 3-4 ; 0.9% ;
+----------------------------+-------------+
@ -142,7 +142,7 @@ https://fpgasoftware.intel.com/eula.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
+---------------------------------------------------------------------+
@ -156,9 +156,9 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; -- Combinational with a register ; 107 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 115 ;
; -- 3 input functions ; 55 ;
; -- 2 input functions ; 45 ;
; -- 4 input functions ; 116 ;
; -- 3 input functions ; 53 ;
; -- 2 input functions ; 46 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
@ -167,7 +167,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 14 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 25 ;
; -- synchronous clear/load mode ; 24 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 126 / 240 ( 53 % ) ;
@ -185,10 +185,10 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; Global signals ; 2 ;
; -- Global clocks ; 2 / 4 ( 50 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 28.7% / 30.1% / 27.2% ;
; Peak interconnect usage (total/H/V) ; 28.7% / 30.1% / 27.2% ;
; Average interconnect usage (total/H/V) ; 26.9% / 26.8% / 27.1% ;
; Peak interconnect usage (total/H/V) ; 26.9% / 26.8% / 27.1% ;
; Maximum fan-out ; 122 ;
; Highest non-global fan-out ; 35 ;
; Highest non-global fan-out ; 34 ;
; Total fan-out ; 992 ;
; Average fan-out ; 3.21 ;
+---------------------------------------------+-----------------------+
@ -208,18 +208,18 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 122 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 14 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 15 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 7 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
@ -243,32 +243,32 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RAout[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRWEout ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -352,12 +352,12 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; On ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; On ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
@ -431,8 +431,8 @@ Note: User assignments will override these defaults. The user specified values a
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; |RAM2E ; 238 (183) ; 126 ; 1 ; 70 ; 0 ; 112 (89) ; 19 (16) ; 107 (78) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 55 (55) ; 32 ; 1 ; 0 ; 0 ; 23 (23) ; 3 (3) ; 29 (29) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |RAM2E ; 238 (182) ; 126 ; 1 ; 70 ; 0 ; 112 (88) ; 19 (16) ; 107 (78) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 56 (56) ; 32 ; 1 ; 0 ; 0 ; 24 (24) ; 3 (3) ; 29 (29) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
@ -495,7 +495,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RD[7] ; Bidir ; (0) ;
; nEN80 ; Input ; (0) ;
; nWE ; Input ; (0) ;
; PHI1 ; Input ; (1) ;
; Ain[0] ; Input ; (0) ;
; Ain[1] ; Input ; (0) ;
; Ain[2] ; Input ; (0) ;
@ -507,6 +506,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; C14M ; Input ; (0) ;
; Din[0] ; Input ; (0) ;
; Din[6] ; Input ; (0) ;
; PHI1 ; Input ; (1) ;
; Din[1] ; Input ; (0) ;
; Din[5] ; Input ; (0) ;
; Din[7] ; Input ; (0) ;
@ -522,22 +522,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
; BA[0]~0 ; LC_X2_Y2_N0 ; 2 ; Clock enable ; no ; -- ; -- ;
; BA[0]~1 ; LC_X3_Y3_N0 ; 3 ; Clock enable ; no ; -- ; -- ;
; BA[0]~0 ; LC_X2_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
; BA[0]~1 ; LC_X5_Y2_N3 ; 3 ; Clock enable ; no ; -- ; -- ;
; C14M ; PIN_12 ; 122 ; Clock ; yes ; Global Clock ; GCLK0 ;
; CS[0]~2 ; LC_X5_Y1_N7 ; 3 ; Clock enable ; no ; -- ; -- ;
; CS[0]~2 ; LC_X3_Y1_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
; DQML~0 ; LC_X2_Y4_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
; Equal1~1 ; LC_X3_Y3_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal1~2 ; LC_X7_Y4_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
; Mux14~0 ; LC_X4_Y2_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI1 ; PIN_37 ; 7 ; Clock ; yes ; Global Clock ; GCLK3 ;
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X2_Y1_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X4_Y1_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X5_Y3_N1 ; 16 ; Clock enable ; no ; -- ; -- ;
; RA[1]~2 ; LC_X3_Y3_N5 ; 6 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X3_Y3_N1 ; 8 ; Output enable ; no ; -- ; -- ;
; S[0] ; LC_X7_Y2_N5 ; 32 ; Sync. clear ; no ; -- ; -- ;
; S[3] ; LC_X7_Y2_N3 ; 35 ; Sync. clear ; no ; -- ; -- ;
; Equal1~1 ; LC_X2_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal1~2 ; LC_X7_Y4_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
; Mux14~0 ; LC_X2_Y3_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI1 ; PIN_37 ; 5 ; Clock ; yes ; Global Clock ; GCLK3 ;
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X7_Y1_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X3_Y1_N3 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X4_Y2_N1 ; 16 ; Clock enable ; no ; -- ; -- ;
; RA[1]~2 ; LC_X2_Y3_N9 ; 6 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X3_Y3_N4 ; 8 ; Output enable ; no ; -- ; -- ;
; S[0] ; LC_X3_Y3_N3 ; 32 ; Sync. clear ; no ; -- ; -- ;
; S[3] ; LC_X3_Y3_N6 ; 34 ; Sync. clear ; no ; -- ; -- ;
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
@ -547,7 +547,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; C14M ; PIN_12 ; 122 ; Global Clock ; GCLK0 ;
; PHI1 ; PIN_37 ; 7 ; Global Clock ; GCLK3 ;
; PHI1 ; PIN_37 ; 5 ; Global Clock ; GCLK3 ;
+------+----------+---------+----------------------+------------------+
@ -556,13 +556,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
; C4s ; 168 / 784 ( 21 % ) ;
; Direct links ; 51 / 888 ( 6 % ) ;
; C4s ; 163 / 784 ( 21 % ) ;
; Direct links ; 57 / 888 ( 6 % ) ;
; Global clocks ; 2 / 4 ( 50 % ) ;
; LAB clocks ; 7 / 32 ( 22 % ) ;
; LUT chains ; 6 / 216 ( 3 % ) ;
; Local interconnects ; 347 / 888 ( 39 % ) ;
; R4s ; 164 / 704 ( 23 % ) ;
; LUT chains ; 5 / 216 ( 2 % ) ;
; Local interconnects ; 340 / 888 ( 38 % ) ;
; R4s ; 150 / 704 ( 21 % ) ;
+-----------------------+--------------------+
@ -578,21 +578,21 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 2 ;
; 10 ; 22 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 23 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.25) ; Number of LABs (Total = 24) ;
; LAB-wide Signals (Average = 1.42) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+
; 1 Clock ; 21 ;
; 1 Clock enable ; 5 ;
; 1 Sync. clear ; 1 ;
; 2 Clock enables ; 2 ;
; 1 Clock enable ; 9 ;
; 1 Sync. clear ; 2 ;
; 2 Clock enables ; 1 ;
; 2 Clocks ; 1 ;
+------------------------------------+------------------------------+
@ -600,7 +600,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 10.17) ; Number of LABs (Total = 24) ;
; Number of Signals Sourced (Average = 10.13) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
@ -610,10 +610,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 2 ;
; 10 ; 20 ;
; 11 ; 1 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 22 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
@ -624,18 +624,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 7.38) ; Number of LABs (Total = 24) ;
; Number of Signals Sourced Out (Average = 7.21) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 2 ;
; 5 ; 2 ;
; 6 ; 1 ;
; 7 ; 4 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 3 ;
; 7 ; 6 ;
; 8 ; 4 ;
; 9 ; 5 ;
; 9 ; 3 ;
; 10 ; 3 ;
; 11 ; 0 ;
; 12 ; 1 ;
@ -645,7 +645,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 12.21) ; Number of LABs (Total = 24) ;
; Number of Distinct Inputs (Average = 12.54) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
@ -653,24 +653,24 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 3 ; 0 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 1 ;
; 9 ; 2 ;
; 10 ; 1 ;
; 11 ; 3 ;
; 12 ; 1 ;
; 13 ; 5 ;
; 14 ; 4 ;
; 12 ; 2 ;
; 13 ; 1 ;
; 14 ; 2 ;
; 15 ; 1 ;
; 16 ; 0 ;
; 17 ; 0 ;
; 16 ; 2 ;
; 17 ; 1 ;
; 18 ; 1 ;
; 19 ; 0 ;
; 20 ; 0 ;
; 19 ; 1 ;
; 20 ; 1 ;
; 21 ; 0 ;
; 22 ; 0 ;
; 23 ; 1 ;
; 23 ; 0 ;
; 24 ; 1 ;
+----------------------------------------------+------------------------------+
@ -718,52 +718,51 @@ Info (332111): Found 3 clocks
Info (332111): 200.000 ram2e_ufm|ARCLK|regout
Info (332111): 200.000 ram2e_ufm|DRCLK|regout
Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186217): Destination "nVOE~0" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 59
Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 20
Info (186217): Destination "S~2" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 19
Info (186217): Destination "S[2]~9" may be non-global or may not use global clock File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 21
Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 20
Info (186217): Destination "S~0" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 19
Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes
Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 87
Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
Info (170193): Fitter routing operations beginning
Info (170089): 2e+01 ns of routing delay (approximately 1.1% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
Info (170195): Router estimated average interconnect usage is 25% of the available device resources
Info (170196): Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.35 seconds.
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.84 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings
Info: Peak virtual memory: 13751 megabytes
Info: Processing ended: Tue Jan 16 14:28:00 2024
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:04
Info: Peak virtual memory: 13771 megabytes
Info: Processing ended: Thu Feb 15 04:16:23 2024
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:05
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg.
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg.

4
CPLD/MAXV/output_files/RAM2E.fit.summary
View File

@ -1,5 +1,5 @@
Fitter Status : Successful - Tue Jan 16 14:28:00 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Fitter Status : Successful - Thu Feb 15 04:16:23 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX V

48
CPLD/MAXV/output_files/RAM2E.flow.rpt
View File

@ -1,6 +1,6 @@
Flow report for RAM2E
Tue Jan 16 14:28:05 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:32 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+-------------------------------------------------------------+
; Flow Status ; Successful - Tue Jan 16 14:28:02 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 79 ( 89 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Feb 15 04:16:27 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 79 ( 89 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+-----------------------------------------+
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 01/16/2024 14:27:31 ;
; Start date & time ; 02/15/2024 04:15:29 ;
; Main task ; Compilation ;
; Revision Name ; RAM2E ;
+-------------------+---------------------+
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------+------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------+------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 121381084694.170543325107988 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 121380219419.170798852904876 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:25 ; 1.0 ; 13116 MB ; 00:00:42 ;
; Fitter ; 00:00:03 ; 1.0 ; 13751 MB ; 00:00:04 ;
; Assembler ; 00:00:00 ; 1.0 ; 13071 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:01 ; 1.0 ; 13072 MB ; 00:00:01 ;
; Total ; 00:00:29 ; -- ; -- ; 00:00:48 ;
; Analysis & Synthesis ; 00:00:45 ; 1.0 ; 13146 MB ; 00:00:47 ;
; Fitter ; 00:00:08 ; 1.0 ; 13771 MB ; 00:00:05 ;
; Assembler ; 00:00:02 ; 1.0 ; 13091 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:03 ; 1.0 ; 13093 MB ; 00:00:02 ;
; Total ; 00:00:58 ; -- ; -- ; 00:00:55 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+

2
CPLD/MAXV/output_files/RAM2E.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="a200c32949da45b33c7d"/>
<hash md5_digest_80b="ec04ae5d795b1a9f31d1"/>
</project>
<file_info>
<file device="5M240ZT100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>

114
CPLD/MAXV/output_files/RAM2E.map.rpt
View File

@ -1,6 +1,6 @@
Analysis & Synthesis report for RAM2E
Tue Jan 16 14:27:56 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:13 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Jan 16 14:27:56 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Total logic elements ; 252 ;
; Total pins ; 70 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Feb 15 04:16:13 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Total logic elements ; 252 ;
; Total pins ; 70 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
@ -146,16 +146,16 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
+----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
; ../RAM2E.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/RAM2E.v ; ;
; ../UFM-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/UFM-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2E/CPLD/MAXV/UFM.v ; ;
; ../RAM2E.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2E/CPLD/RAM2E.mif ; ;
+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+
; ../RAM2E.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v ; ;
; ../UFM-MAX.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v ; ;
; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.mif ; ;
+----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+
+-----------------------------------------------------+
@ -169,9 +169,9 @@ https://fpgasoftware.intel.com/eula.
; -- Combinational with a register ; 93 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 115 ;
; -- 3 input functions ; 55 ;
; -- 2 input functions ; 45 ;
; -- 4 input functions ; 116 ;
; -- 3 input functions ; 53 ;
; -- 2 input functions ; 46 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
@ -199,8 +199,8 @@ https://fpgasoftware.intel.com/eula.
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; |RAM2E ; 252 (192) ; 126 ; 1 ; 70 ; 0 ; 126 (98) ; 33 (25) ; 93 (69) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 60 (60) ; 32 ; 1 ; 0 ; 0 ; 28 (28) ; 8 (8) ; 24 (24) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |RAM2E ; 252 (191) ; 126 ; 1 ; 70 ; 0 ; 126 (97) ; 33 (25) ; 93 (69) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 61 (61) ; 32 ; 1 ; 0 ; 0 ; 29 (29) ; 8 (8) ; 24 (24) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
@ -281,50 +281,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Tue Jan 16 14:27:31 2024
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:15:28 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ufm-max.v
Info (12023): Found entity 1: RAM2E_UFM File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v
Info (12023): Found entity 1: RAM2E File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ufm-max.v
Info (12023): Found entity 1: RAM2E_UFM File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Info (12023): Found entity 1: UFM_altufm_none_p8r File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166
Info (12023): Found entity 1: UFM_altufm_none_p8r File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 138
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 78
Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 136
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 77
Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "nCSout" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 77
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 75
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "nWE80" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 11
Warning (15610): No output dependent on input pin "nWE80" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 11
Info (21057): Implemented 323 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 22 input pins
Info (21059): Implemented 40 output pins
Info (21060): Implemented 8 bidirectional pins
Info (21061): Implemented 252 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Peak virtual memory: 13116 megabytes
Info: Processing ended: Tue Jan 16 14:27:56 2024
Info: Elapsed time: 00:00:25
Info: Total CPU time (on all processors): 00:00:42
Info: Peak virtual memory: 13146 megabytes
Info: Processing ended: Thu Feb 15 04:16:13 2024
Info: Elapsed time: 00:00:45
Info: Total CPU time (on all processors): 00:00:47
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg.
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg.

6
CPLD/MAXV/output_files/RAM2E.map.smsg
View File

@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at RAM2E.v(74): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 74
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189
Warning (10273): Verilog HDL warning at RAM2E.v(72): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 72
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189

4
CPLD/MAXV/output_files/RAM2E.map.summary
View File

@ -1,5 +1,5 @@
Analysis & Synthesis Status : Successful - Tue Jan 16 14:27:56 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Analysis & Synthesis Status : Successful - Thu Feb 15 04:16:13 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX V

2
CPLD/MAXV/output_files/RAM2E.pin
View File

@ -58,7 +58,7 @@
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
CHIP "RAM2E" ASSIGNED TO AN: 5M240ZT100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment

BIN
CPLD/MAXV/output_files/RAM2E.pof
View File

Binary file not shown.

442
CPLD/MAXV/output_files/RAM2E.sta.rpt
View File

@ -1,6 +1,6 @@
Timing Analyzer report for RAM2E
Tue Jan 16 14:28:05 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:32 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -20,8 +20,8 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio
12. Setup: 'ram2e_ufm|DRCLK|regout'
13. Setup: 'ram2e_ufm|ARCLK|regout'
14. Setup: 'C14M'
15. Hold: 'ram2e_ufm|DRCLK|regout'
16. Hold: 'ram2e_ufm|ARCLK|regout'
15. Hold: 'ram2e_ufm|ARCLK|regout'
16. Hold: 'ram2e_ufm|DRCLK|regout'
17. Hold: 'C14M'
18. Setup Transfers
19. Hold Transfers
@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+---------------------------------------------------------------------+
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; RAM2E ;
; Device Family ; MAX V ;
; Device Name ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+---------------------------------------------------------------------+
+-----------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; RAM2E ;
; Device Family ; MAX V ;
; Device Name ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
+------------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+------------------+--------+--------------------------+
; ../RAM2E.sdc ; OK ; Tue Jan 16 14:28:05 2024 ;
; ../RAM2E-MAX.sdc ; OK ; Tue Jan 16 14:28:05 2024 ;
; ../RAM2E.sdc ; OK ; Thu Feb 15 04:16:31 2024 ;
; ../RAM2E-MAX.sdc ; OK ; Thu Feb 15 04:16:31 2024 ;
+------------------+--------+--------------------------+
@ -116,7 +116,7 @@ https://fpgasoftware.intel.com/eula.
+-----------+-----------------+------------------------+------+
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|ARCLK|regout ; ;
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|DRCLK|regout ; ;
; 27.62 MHz ; 27.62 MHz ; C14M ; ;
; 27.75 MHz ; 27.75 MHz ; C14M ; ;
+-----------+-----------------+------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@ -126,9 +126,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------+---------+---------------+
; ram2e_ufm|DRCLK|regout ; -25.457 ; -25.457 ;
; ram2e_ufm|DRCLK|regout ; -25.469 ; -25.469 ;
; ram2e_ufm|ARCLK|regout ; -25.439 ; -25.439 ;
; C14M ; -17.639 ; -171.643 ;
; C14M ; -18.223 ; -201.658 ;
+------------------------+---------+---------------+
@ -137,9 +137,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------+---------+---------------+
; ram2e_ufm|DRCLK|regout ; -14.583 ; -14.583 ;
; ram2e_ufm|ARCLK|regout ; -14.560 ; -14.560 ;
; C14M ; 2.730 ; 0.000 ;
; ram2e_ufm|DRCLK|regout ; -14.560 ; -14.560 ;
; C14M ; 3.156 ; 0.000 ;
+------------------------+---------+---------------+
@ -171,8 +171,8 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -25.457 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -0.912 ; 4.546 ;
; -25.416 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -0.912 ; 4.505 ;
; -25.469 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.477 ; 2.993 ;
; -25.439 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.477 ; 2.963 ;
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
@ -182,7 +182,7 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -25.439 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -0.958 ; 4.482 ;
; -25.439 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -2.477 ; 2.963 ;
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
@ -192,235 +192,235 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; -17.639 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 18.231 ;
; -17.637 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 18.229 ;
; -15.030 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 15.622 ;
; -14.952 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 15.544 ;
; -13.751 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 14.343 ;
; -13.751 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 14.343 ;
; -13.751 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 14.343 ;
; -13.751 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 14.343 ;
; -13.751 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 14.343 ;
; -13.751 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 14.343 ;
; -13.751 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 14.343 ;
; -10.128 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.912 ; 10.720 ;
; 16.820 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.779 ;
; 16.820 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.779 ;
; 16.820 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.779 ;
; 16.844 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.755 ;
; 16.844 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.755 ;
; 16.844 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.755 ;
; 17.014 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.585 ;
; 17.014 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.585 ;
; 17.014 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.585 ;
; 17.038 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.561 ;
; 17.038 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.561 ;
; 17.038 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.561 ;
; 18.060 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.539 ;
; 18.060 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.539 ;
; 18.060 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.539 ;
; 18.084 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.515 ;
; 18.084 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.515 ;
; 18.084 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.515 ;
; 18.321 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.278 ;
; 18.321 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.278 ;
; 18.321 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.278 ;
; 18.345 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.254 ;
; 18.345 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.254 ;
; 18.345 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.254 ;
; 20.092 ; S[0] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 14.507 ;
; 20.492 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.107 ;
; 20.492 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.107 ;
; 20.686 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.913 ;
; 20.686 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.913 ;
; 21.317 ; S[1] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 13.282 ;
; 21.732 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.867 ;
; 21.732 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.867 ;
; 21.993 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.606 ;
; 21.993 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.606 ;
; 26.069 ; S[3] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 8.530 ;
; 26.118 ; S[2] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 8.481 ;
; 28.496 ; RA[4] ; RAr[4] ; C14M ; C14M ; 34.920 ; 0.000 ; 6.103 ;
; 28.497 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.102 ;
; 28.552 ; RA[10] ; RAr[10] ; C14M ; C14M ; 34.920 ; 0.000 ; 6.047 ;
; 28.590 ; RA[9] ; RAr[9] ; C14M ; C14M ; 34.920 ; 0.000 ; 6.009 ;
; 30.057 ; RA[11] ; RAr[11] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.542 ;
; 30.106 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.493 ;
; 30.124 ; RA[8] ; RAr[8] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.475 ;
; 30.337 ; RA[0] ; RAr[0] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.262 ;
; 30.381 ; RA[6] ; RAr[6] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.218 ;
; 30.386 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.213 ;
; 30.391 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.208 ;
; 31.414 ; RA[1] ; RAr[1] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.185 ;
; 31.415 ; RA[7] ; RAr[7] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.184 ;
; 31.443 ; RA[2] ; RAr[2] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.156 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -17.497 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 19.654 ;
; -14.015 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 16.172 ;
; -14.004 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 16.161 ;
; -10.358 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 12.515 ;
; 16.903 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.696 ;
; 16.903 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.696 ;
; 16.903 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.696 ;
; 16.993 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.606 ;
; 16.993 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.606 ;
; 16.993 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.606 ;
; 17.034 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.565 ;
; 17.034 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.565 ;
; 17.034 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.565 ;
; 17.124 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.475 ;
; 17.124 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.475 ;
; 17.124 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.475 ;
; 17.625 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.974 ;
; 17.625 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.974 ;
; 17.625 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.974 ;
; 17.715 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.884 ;
; 17.715 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.884 ;
; 17.715 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.884 ;
; 17.828 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.771 ;
; 17.828 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.771 ;
; 17.828 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.771 ;
; 17.918 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.681 ;
; 17.918 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.681 ;
; 17.918 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.681 ;
; 20.070 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.529 ;
; 20.070 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.529 ;
; 20.201 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.398 ;
; 20.201 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.398 ;
; 20.792 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.807 ;
; 20.792 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.807 ;
; 20.995 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.604 ;
; 20.995 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.604 ;
; 22.233 ; S[2] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 12.366 ;
; 23.933 ; S[3] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 10.666 ;
; 24.168 ; S[0] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 10.431 ;
; 25.342 ; S[1] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 9.257 ;
; 25.631 ; S[2] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 8.968 ;
; 27.763 ; S[3] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 6.836 ;
; 28.027 ; RA[8] ; RAr[8] ; C14M ; C14M ; 34.920 ; 0.000 ; 6.572 ;
; 28.362 ; RA[11] ; RAr[11] ; C14M ; C14M ; 34.920 ; 0.000 ; 6.237 ;
; 28.707 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.892 ;
; 29.373 ; S[0] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 5.226 ;
; 29.587 ; S[1] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 5.012 ;
; 30.153 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.446 ;
; 30.163 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.436 ;
; 30.336 ; RA[6] ; RAr[6] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.263 ;
; 30.364 ; RA[2] ; RAr[2] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.235 ;
; 30.410 ; RA[9] ; RAr[9] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.189 ;
; 30.411 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.188 ;
; 30.417 ; RA[10] ; RAr[10] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.182 ;
; 31.443 ; RA[0] ; RAr[0] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.156 ;
; 31.443 ; RA[3] ; RAr[3] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.156 ;
; 31.453 ; RA[5] ; RAr[5] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.146 ;
; 34.230 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.290 ;
; 34.657 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 34.863 ;
; 35.260 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 34.260 ;
; 35.431 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.089 ;
; 35.431 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.089 ;
; 35.431 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.089 ;
; 35.431 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.089 ;
; 35.431 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.089 ;
; 35.431 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.089 ;
; 35.431 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.089 ;
; 36.333 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 33.187 ;
; 36.936 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 32.584 ;
; 37.042 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.478 ;
; 37.390 ; S[0] ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 32.130 ;
; 37.395 ; S[0] ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 32.125 ;
; 37.408 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 32.112 ;
; 37.689 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.831 ;
; 37.689 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.831 ;
; 37.689 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.831 ;
; 37.689 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.831 ;
; 37.689 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.831 ;
; 37.689 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.831 ;
; 37.689 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.831 ;
; 37.689 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.831 ;
; 37.794 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.726 ;
; 38.141 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 31.379 ;
; 38.243 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.277 ;
; 38.243 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.277 ;
; 38.243 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.277 ;
; 38.243 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.277 ;
; 38.243 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.277 ;
; 38.243 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.277 ;
; 38.243 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.277 ;
; 38.292 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.228 ;
; 38.292 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.228 ;
; 38.292 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 31.228 ;
; 31.443 ; RA[4] ; RAr[4] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.156 ;
; 31.444 ; RA[1] ; RAr[1] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.155 ;
; 31.444 ; RA[7] ; RAr[7] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.155 ;
; 31.452 ; RA[5] ; RAr[5] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.147 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.851 ; S[2] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 32.669 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'ram2e_ufm|DRCLK|regout' ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -14.583 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -0.912 ; 4.505 ;
; -14.542 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -0.912 ; 4.546 ;
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'ram2e_ufm|ARCLK|regout' ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -14.560 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -0.958 ; 4.482 ;
; -14.560 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -2.477 ; 2.963 ;
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'ram2e_ufm|DRCLK|regout' ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -14.560 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.477 ; 2.963 ;
; -14.530 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.477 ; 2.993 ;
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'C14M' ;
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
; 2.730 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.769 ;
; 3.117 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.156 ;
; 3.171 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.210 ;
; 3.193 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.232 ;
; 3.363 ; RWBank[7] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.402 ;
; 3.367 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.406 ;
; 3.385 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.424 ;
; 3.403 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.442 ;
; 3.441 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.480 ;
; 3.448 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.487 ;
; 3.458 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.497 ;
; 3.464 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 3.503 ;
; 3.740 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.779 ;
; 3.740 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.779 ;
; 3.766 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 3.805 ;
; 3.832 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.871 ;
; 3.846 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 3.885 ;
; 3.854 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.893 ;
; 3.858 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.897 ;
; 3.862 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.901 ;
; 4.411 ; PHI1r ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.450 ;
; 4.806 ; RWBank[6] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 4.845 ;
; 4.857 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.896 ;
; 3.156 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.195 ;
; 3.164 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.203 ;
; 3.170 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.209 ;
; 3.364 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.403 ;
; 3.394 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 3.433 ;
; 3.418 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.457 ;
; 3.450 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.489 ;
; 3.543 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.582 ;
; 3.547 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.586 ;
; 3.741 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 3.780 ;
; 3.752 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.791 ;
; 3.752 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 3.791 ;
; 3.776 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 3.815 ;
; 3.814 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.853 ;
; 3.817 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.856 ;
; 3.829 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.868 ;
; 3.865 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 3.904 ;
; 3.935 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.974 ;
; 3.938 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.977 ;
; 3.951 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.990 ;
; 4.101 ; PHI1r ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.140 ;
; 4.102 ; PHI1r ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.141 ;
; 4.106 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.145 ;
; 4.224 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.263 ;
; 4.479 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.518 ;
; 4.839 ; CmdSetRWBankFFChip ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.878 ;
; 4.849 ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 4.888 ;
; 5.135 ; S[3] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.174 ;
; 5.217 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
; 5.217 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
; 5.217 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
; 5.227 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.266 ;
; 5.247 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.286 ;
; 5.257 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.296 ;
; 5.218 ; RWBank[7] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.257 ;
; 5.231 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.270 ;
; 5.266 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.305 ;
; 5.267 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.306 ;
; 5.271 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.310 ;
; 5.286 ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 5.325 ;
; 5.320 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.359 ;
; 5.323 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.362 ;
; 5.429 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ;
; 5.429 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ;
; 5.284 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.323 ;
; 5.287 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.326 ;
; 5.420 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 5.459 ;
; 5.443 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.482 ;
; 5.443 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.482 ;
; 5.452 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
; 5.452 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
; 5.453 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ;
; 5.455 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.494 ;
; 5.457 ; S[1] ; RDOE ; C14M ; C14M ; 0.000 ; 0.000 ; 5.496 ;
; 5.464 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.503 ;
; 5.465 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.504 ;
; 5.465 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.504 ;
; 5.466 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.505 ;
; 5.467 ; S[0] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.506 ;
; 5.482 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.521 ;
; 5.486 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.525 ;
; 5.508 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.547 ;
; 5.522 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 5.561 ;
; 5.533 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.572 ;
; 5.538 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.577 ;
; 5.546 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.585 ;
; 5.563 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.602 ;
; 5.580 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.619 ;
; 5.581 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.620 ;
; 5.514 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.553 ;
; 5.515 ; S[0] ; nCAS ; C14M ; C14M ; 0.000 ; 0.000 ; 5.554 ;
; 5.530 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.569 ;
; 5.534 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.573 ;
; 5.564 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.603 ;
; 5.574 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.613 ;
; 5.704 ; CmdLEDGet ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.743 ;
; 5.895 ; CmdSetRWBankFFLED ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.934 ;
; 6.001 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.040 ;
; 6.002 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.041 ;
; 6.006 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.045 ;
; 6.037 ; RAM2E_UFM:ram2e_ufm|UFMErase ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 6.076 ;
; 6.064 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.103 ;
; 6.145 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.184 ;
; 6.146 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.185 ;
; 6.150 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.189 ;
; 6.289 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.328 ;
; 6.174 ; PHI1r ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.213 ;
; 6.290 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.329 ;
; 6.298 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.337 ;
; 6.294 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.333 ;
; 6.298 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.337 ;
; 6.310 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.349 ;
; 6.318 ; RWBank[6] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.357 ;
; 6.321 ; FS[15] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.360 ;
; 6.323 ; FS[15] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.362 ;
; 6.348 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 6.387 ;
; 6.351 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.390 ;
; 6.371 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.410 ;
; 6.430 ; FS[13] ; RA[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.469 ;
; 6.454 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
; 6.389 ; Ready ; RDOE ; C14M ; C14M ; 0.000 ; 0.000 ; 6.428 ;
; 6.393 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 6.432 ;
; 6.425 ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.464 ;
; 6.452 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.491 ;
; 6.454 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
; 6.455 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.494 ;
; 6.457 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.496 ;
; 6.466 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.505 ;
; 6.484 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.523 ;
; 6.488 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.527 ;
; 6.503 ; RAM2E_UFM:ram2e_ufm|UFMErase ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 6.542 ;
; 6.527 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.566 ;
; 6.509 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.548 ;
; 6.537 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.576 ;
; 6.557 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.596 ;
; 6.562 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.601 ;
; 6.576 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.615 ;
; 6.542 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.581 ;
; 6.549 ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.588 ;
; 6.598 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ;
; 6.610 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.649 ;
; 6.617 ; S[3] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.656 ;
; 6.618 ; RWBank[5] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.657 ;
; 6.613 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.652 ;
; 6.632 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.671 ;
; 6.644 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.683 ;
; 6.647 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.686 ;
; 6.675 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.714 ;
; 6.705 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.744 ;
; 6.705 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.744 ;
; 6.712 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.751 ;
; 6.715 ; RWSel ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 6.754 ;
; 6.742 ; FS[11] ; RA[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.781 ;
; 6.692 ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.731 ;
; 6.754 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.793 ;
; 6.774 ; FS[10] ; RA[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.813 ;
; 6.776 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.815 ;
; 6.786 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ;
; 6.786 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ;
; 6.786 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ;
; 6.803 ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.842 ;
; 6.836 ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.875 ;
; 6.838 ; RWBank[2] ; RA[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.877 ;
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
@ -429,7 +429,7 @@ No paths to report.
+------------------------+------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------+------------------------+----------+----------+----------+----------+
; C14M ; C14M ; 1550 ; 0 ; 52 ; 0 ;
; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ;
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
@ -444,7 +444,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------------------+------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------+------------------------+----------+----------+----------+----------+
; C14M ; C14M ; 1550 ; 0 ; 52 ; 0 ;
; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ;
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
@ -474,9 +474,9 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 1 ; 1 ;
; Unconstrained Input Ports ; 28 ; 28 ;
; Unconstrained Input Port Paths ; 170 ; 170 ;
; Unconstrained Input Port Paths ; 169 ; 169 ;
; Unconstrained Output Ports ; 47 ; 47 ;
; Unconstrained Output Port Paths ; 84 ; 84 ;
; Unconstrained Output Port Paths ; 83 ; 83 ;
+---------------------------------+-------+------+
@ -679,8 +679,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Tue Jan 16 14:28:04 2024
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:16:29 2024
Info: Command: quartus_sta RAM2E-MAXV -c RAM2E
Info: qsta_default_script.tcl version: #1
Info (20032): Parallel compilation is enabled and will use up to 4 processors
@ -697,18 +697,18 @@ Info: Can't run Report Timing Closure Recommendations. The current device family
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -25.457
Info (332146): Worst-case setup slack is -25.469
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -25.457 -25.457 ram2e_ufm|DRCLK|regout
Info (332119): -25.469 -25.469 ram2e_ufm|DRCLK|regout
Info (332119): -25.439 -25.439 ram2e_ufm|ARCLK|regout
Info (332119): -17.639 -171.643 C14M
Info (332146): Worst-case hold slack is -14.583
Info (332119): -18.223 -201.658 C14M
Info (332146): Worst-case hold slack is -14.560
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -14.583 -14.583 ram2e_ufm|DRCLK|regout
Info (332119): -14.560 -14.560 ram2e_ufm|ARCLK|regout
Info (332119): 2.730 0.000 C14M
Info (332119): -14.560 -14.560 ram2e_ufm|DRCLK|regout
Info (332119): 3.156 0.000 C14M
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 34.581
@ -718,14 +718,12 @@ Info (332146): Worst-case minimum pulse width slack is 34.581
Info (332119): 70.000 0.000 ram2e_ufm|ARCLK|regout
Info (332119): 70.000 0.000 ram2e_ufm|DRCLK|regout
Info (332001): The selected device family is not supported by the report_metastability command.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 13072 megabytes
Info: Processing ended: Tue Jan 16 14:28:05 2024
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 13093 megabytes
Info: Processing ended: Thu Feb 15 04:16:32 2024
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02

18
CPLD/MAXV/output_files/RAM2E.sta.summary
View File

@ -3,27 +3,27 @@ Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'ram2e_ufm|DRCLK|regout'
Slack : -25.457
TNS : -25.457
Slack : -25.469
TNS : -25.469
Type : Setup 'ram2e_ufm|ARCLK|regout'
Slack : -25.439
TNS : -25.439
Type : Setup 'C14M'
Slack : -17.639
TNS : -171.643
Type : Hold 'ram2e_ufm|DRCLK|regout'
Slack : -14.583
TNS : -14.583
Slack : -18.223
TNS : -201.658
Type : Hold 'ram2e_ufm|ARCLK|regout'
Slack : -14.560
TNS : -14.560
Type : Hold 'ram2e_ufm|DRCLK|regout'
Slack : -14.560
TNS : -14.560
Type : Hold 'C14M'
Slack : 2.730
Slack : 3.156
TNS : 0.000
Type : Minimum Pulse Width 'C14M'

32
CPLD/RAM2E.v
View File

@ -44,19 +44,17 @@ module RAM2E(C14M, PHI1, LED,
input [7:0] Din;
reg DOEEN;
always @(posedge C14M) begin
DOEEN <= S==4'hB || S==4'hC || S==4'hD || S==4'hE || S==4'hF ;
DOEEN <= S==4'hB || S==4'hC || S==4'hD || S==4'hE || S==4'hF;
end
output nDOE; assign nDOE = !(!nEN80 && nWE && DOEEN);
output [7:0] Dout; assign Dout[7:0] = RD[7:0];
/* Video Data Bus */
reg VOEEN;
always @(posedge C14M) begin
VOEEN <= S==4'h7 ||
S==4'h8 || S==4'h9 || S==4'hA || S==4'hB ||
S==4'hC || S==4'hD || S==4'hE || S==4'hF;
reg VOE;
always @(negedge C14M) begin
VOE <= S==4'h7 || S==4'h8 || S==4'h9 || S==4'hA || S==4'hB || S==4'hC;
end
output nVOE; assign nVOE = !(!PHI1 && VOEEN);
output nVOE; assign nVOE = !VOE;
output reg [7:0] Vout; // Video data bus
always @(negedge C14M) if (S==4'h6) Vout[7:0] <= RD[7:0];
@ -68,7 +66,7 @@ module RAM2E(C14M, PHI1, LED,
inout [7:0] RD;
wire [7:0] RDout = Ready ? Din[7:0] : 8'h00;
reg RDOE;
always @(posedge C14M) begin
always @(posedge C14M) begin
RDOE <= (!Ready) || (!nEN80 && !nWE && (S==4'hA || S==4'hB));
end
assign RD[7:0] = RDOE ? RDout[7:0] : 8'bZ;
@ -131,7 +129,7 @@ module RAM2E(C14M, PHI1, LED,
/* Chip-specific UFM interface */
wire [7:0] ChipCmdNum;
RAM2E_UFM ram2e_ufm (
.C14M(C14M), .S(S), .FS(FS), .CS(CS), .Ready(Ready),
.C14M(C14M), .S(S), .FS(FS), .CS(CS),
.RWSel(RWSel), .D(Din),
.RWMask(RWMask), .LEDEN(LEDEN),
.CmdRWMaskSet(CmdRWMaskSet), .CmdLEDSet(CmdLEDSet),
@ -150,11 +148,11 @@ module RAM2E(C14M, PHI1, LED,
// Chip detection command
CmdSetRWBankFFChip <= Din[7:0]==ChipCmdNum[7:0];
// LED exists detect command
CmdSetRWBankFFLED <= Din[7:0]==8'hF0;
CmdSetRWBankFFLED <= Din[7:0]==8'hF0;
// Volatile settings commands
CmdRWMaskSet <= Din[7:0]==8'hE0;
CmdLEDSet <= Din[7:0]==8'hE2;
CmdLEDGet <= Din[7:0]==8'hE3;
CmdRWMaskSet <= Din[7:0]==8'hE0;
CmdLEDSet <= Din[7:0]==8'hE2;
CmdLEDGet <= Din[7:0]==8'hE3;
end else begin // Reset command triggers
CmdSetRWBankFFChip <= 0;
CmdSetRWBankFFLED <= 0;
@ -218,10 +216,10 @@ module RAM2E(C14M, PHI1, LED,
nRWE <= 1'b0;
end
endcase
BA[1:0] <= 2'b00;
case (FS[4:3])
2'b00, 2'b01: begin
// Mode register contents
BA[1:0] <= 2'b00; // Reserved
RA[11] <= 1'b0; // Reserved
RA[10] <= !FS[1]; // reserved / "all"
RA[9] <= 1'b1; // "1" for single write mode
@ -231,11 +229,9 @@ module RAM2E(C14M, PHI1, LED,
RA[3] <= 1'b0; // "0" for sequential burst (not used)
RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
end 2'b10: begin
BA[1:0] <= 2'b00;
RA[11:8] <= 4'h0;
RA[7:0] <= FS[14:7];
end 2'b11: begin
BA[1:0] <= 2'b00;
RA[11:3] <= 9'h000;
RA[2:1] <= FS[6:5];
RA[0] <= FS[1];
@ -402,7 +398,7 @@ module RAM2E(C14M, PHI1, LED,
RA[10] <= 1'b0; // no auto-precharge
end
// Hold BA
// Hold RA[11,9:8]x
// Hold RA[11,9:8]
RA[7:0] <= Ain[7:0];
// Hold DQMs
end 4'hB: begin
@ -435,12 +431,14 @@ module RAM2E(C14M, PHI1, LED,
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Hold RA[10]
end else if (nWE) begin // Read
// NOP CKD
CKE <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Hold RA[10]
end else begin // Write
// PC all CKD
CKE <= 1'b0;

3
CPLD/UFM-LCMXO2.v
View File

@ -1,4 +1,4 @@
module RAM2E_UFM(C14M, S, FS, CS, Ready,
module RAM2E_UFM(C14M, S, FS, CS,
RWSel, D,
RWMask, LEDEN,
CmdRWMaskSet, CmdLEDSet,
@ -7,7 +7,6 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
input [3:0] S;
input [15:0] FS;
input [2:0] CS;
input Ready;
input RWSel;
input [7:0] D;
output reg [7:0] RWMask;

3
CPLD/UFM-MAX.v
View File

@ -1,4 +1,4 @@
module RAM2E_UFM(C14M, S, FS, CS, Ready,
module RAM2E_UFM(C14M, S, FS, CS,
RWSel, D,
RWMask, LEDEN,
CmdRWMaskSet, CmdLEDSet,
@ -7,7 +7,6 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
input [3:0] S;
input [15:0] FS;
input [2:0] CS;
input Ready;
input RWSel;
input [7:0] D;
output reg [7:0] RWMask;

38
Documentation/Timing.json Normal file
View File

@ -0,0 +1,38 @@
{signal: [
{name: 'C14M', wave: 'p................', phase: 0.00, period: 1},
{name: 'State', wave: '22222222222222222', phase: 0.00, period: 1,
data:['D/F','E/F','1','2','3','4','5','6','7','8','9','A','B','C','D','E','1']},
{name: 'PHI0', wave: '10......1......0.', phase: 0.00, period: 1},
{name: '/RAS', wave: '1.0....1.0....1.0', phase: 0.00, period: 1},
{name: '/CAS', wave: '1...0...1..0...1.', phase: 0.00, period: 1},
{name: '/Q3', wave: '1....0..1...0..1.', phase: 0.00, period: 1},
{name: 'RA[7:0]', wave: '2.x2.xx2...xx2..x2.xx2...xx2..x2.x', phase: 0.00, period: 0.5,
data:['crow','vrow','vcol','vrow','crow','ccol','crow','vrow']},
{},
{name: 'CKE (idle)', wave: '0..1..0..10......', phase: 0.00, period: 1},
{name: 'Cmd (idle)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP']},
{name: 'CKE (idle)', wave: '0..1....010......', phase: 0.00, period: 1},
{name: 'Cmd (idle)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','REF','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP']},
{},
{name: 'CKE (read)', wave: '0..1..0..1..0....', phase: 0.00, period: 1},
{name: 'Cmd (read)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','NOP','NOP','NOP','ACT','RD','PCa','NOP','NOP','NOP','NOP']},
{name: 'CKE (read)', wave: '0..1....01..0....', phase: 0.00, period: 1},
{name: 'Cmd (read)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','REF','NOP','NOP','ACT','RD','PCa','NOP','NOP','NOP','NOP']},
{},
{name: 'CKE (write)', wave: '0..1..0..101..0..', phase: 0.00, period: 1},
{name: 'Cmd (write)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','NOP','NOP','NOP','ACT','NOP','WR','NOP','PCa','NOP','NOP']},
{name: 'CKE (write)', wave: '0..1....0101..0..', phase: 0.00, period: 1},
{name: 'Cmd (write)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','REF','NOP','NOP','ACT','NOP','WR','NOP','PCa','NOP','NOP']},
]}

BIN
Documentation/Timing.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 198 KiB

5
Hardware/LCMXO2/BOM/RAM2E-BOM.LCMXO2HC.csv
View File

@ -17,7 +17,8 @@ R7 ,1,DNP,stdpads:R_0805,,,,
R5 R8 R9 R11 ,4,10k,stdpads:R_0603,,C25804,Uniroyal 0603WAF1002T5E,Any manufacturer's part is acceptable.
U1 ,1,LCMXO2-TG100,stdpads:TQFP-100_14x14mm_P0.5mm,,C1519051,"Lattice LCMXO2-640HC-4TG100C, Lattice LCMXO2-640HC-5TG100C, Lattice LCMXO2-640HC-6TG100C, Lattice LCMXO2-640HC-4TG100I, Lattice LCMXO2-640HC-5TG100I, Lattice LCMXO2-640HC-6TG100I, Lattice LCMXO2-1200HC-4TG100C, Lattice LCMXO2-1200HC-5TG100C, Lattice LCMXO2-1200HC-6TG100C, Lattice LCMXO2-1200HC-4TG100I, Lattice LCMXO2-1200HC-5TG100I, Lattice LCMXO2-1200HC-6TG100I",
U2 ,1,W9812G6KH-6,stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm,,C62379,"Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G",Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
U3 U4 U5 ,3,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U4 ,1,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U3 U5 ,2,74AHC245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U6 U7 ,2,74AHCT245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C173388,"NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW",Most 74AHCT245 in TSSOP-20 package is acceptable.
U8 ,1,XC6206P332MR,stdpads:SOT-23,,C5446,Torex XC6206P332MR,Most 3.3V regulator in SOT-23 package is acceptable.
U9 ,1,DNP,stdpads:SOT-23-5,,,,
U9 ,1,DNP,stdpads:SOT-23-5,,,,

1 Reference Quantity Value Footprint Datasheet LCSC Part Mfg. Part Numbers Notes
17 R5 R8 R9 R11 4 10k stdpads:R_0603 C25804 Uniroyal 0603WAF1002T5E Any manufacturer's part is acceptable.
18 U1 1 LCMXO2-TG100 stdpads:TQFP-100_14x14mm_P0.5mm C1519051 Lattice LCMXO2-640HC-4TG100C, Lattice LCMXO2-640HC-5TG100C, Lattice LCMXO2-640HC-6TG100C, Lattice LCMXO2-640HC-4TG100I, Lattice LCMXO2-640HC-5TG100I, Lattice LCMXO2-640HC-6TG100I, Lattice LCMXO2-1200HC-4TG100C, Lattice LCMXO2-1200HC-5TG100C, Lattice LCMXO2-1200HC-6TG100C, Lattice LCMXO2-1200HC-4TG100I, Lattice LCMXO2-1200HC-5TG100I, Lattice LCMXO2-1200HC-6TG100I
19 U2 1 W9812G6KH-6 stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm C62379 Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
20 U3 U4 U5 U4 3 1 74LVC245APW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
21 U3 U5 2 74AHC245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
22 U6 U7 2 74AHCT245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C173388 NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW Most 74AHCT245 in TSSOP-20 package is acceptable.
23 U8 1 XC6206P332MR stdpads:SOT-23 C5446 Torex XC6206P332MR Most 3.3V regulator in SOT-23 package is acceptable.
24 U9 1 DNP stdpads:SOT-23-5

5
Hardware/LCMXO2/BOM/RAM2E-BOM.LCMXO2HE.csv
View File

@ -17,7 +17,8 @@ R7 ,1,DNP,stdpads:R_0805,,,,
R5 R8 R9 R11 ,4,10k,stdpads:R_0603,,C25804,Uniroyal 0603WAF1002T5E,Any manufacturer's part is acceptable.
U1 ,1,LCMXO2-TG100,stdpads:TQFP-100_14x14mm_P0.5mm,,C1519051,"Lattice LCMXO2-640HE-4TG100C, Lattice LCMXO2-640HE-5TG100C, Lattice LCMXO2-640HE-6TG100C, Lattice LCMXO2-640HE-4TG100I, Lattice LCMXO2-640HE-5TG100I, Lattice LCMXO2-640HE-6TG100I, Lattice LCMXO2-1200HE-4TG100C, Lattice LCMXO2-1200HE-5TG100C, Lattice LCMXO2-1200HE-6TG100C, Lattice LCMXO2-1200HE-4TG100I, Lattice LCMXO2-1200HE-5TG100I, Lattice LCMXO2-1200HE-6TG100I",
U2 ,1,W9812G6KH-6,stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm,,C62379,"Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G",Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
U3 U4 U5 ,3,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U4 ,1,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U3 U5 ,2,74AHC245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U6 U7 ,2,74AHCT245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C173388,"NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW",Most 74AHCT245 in TSSOP-20 package is acceptable.
U8 ,1,XC6206P332MR,stdpads:SOT-23,,C5446,Torex XC6206P332MR,Most 3.3V regulator in SOT-23 package is acceptable.
U9 ,1,AP2127K-1.2TRG1,stdpads:SOT-23-5,,C151376,"Diodes AP2127K-1.2TRG1, Torex XC6228D122VR",Most 1.2V regulator in SOT-23-5 package is acceptable.
U9 ,1,AP2127K-1.2TRG1,stdpads:SOT-23-5,,C151376,"Diodes AP2127K-1.2TRG1, Torex XC6228D122VR",Most 1.2V regulator in SOT-23-5 package is acceptable.

1 Reference Quantity Value Footprint Datasheet LCSC Part Mfg. Part Numbers Notes
17 R5 R8 R9 R11 4 10k stdpads:R_0603 C25804 Uniroyal 0603WAF1002T5E Any manufacturer's part is acceptable.
18 U1 1 LCMXO2-TG100 stdpads:TQFP-100_14x14mm_P0.5mm C1519051 Lattice LCMXO2-640HE-4TG100C, Lattice LCMXO2-640HE-5TG100C, Lattice LCMXO2-640HE-6TG100C, Lattice LCMXO2-640HE-4TG100I, Lattice LCMXO2-640HE-5TG100I, Lattice LCMXO2-640HE-6TG100I, Lattice LCMXO2-1200HE-4TG100C, Lattice LCMXO2-1200HE-5TG100C, Lattice LCMXO2-1200HE-6TG100C, Lattice LCMXO2-1200HE-4TG100I, Lattice LCMXO2-1200HE-5TG100I, Lattice LCMXO2-1200HE-6TG100I
19 U2 1 W9812G6KH-6 stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm C62379 Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
20 U3 U4 U5 U4 3 1 74LVC245APW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
21 U3 U5 2 74AHC245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
22 U6 U7 2 74AHCT245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C173388 NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW Most 74AHCT245 in TSSOP-20 package is acceptable.
23 U8 1 XC6206P332MR stdpads:SOT-23 C5446 Torex XC6206P332MR Most 3.3V regulator in SOT-23 package is acceptable.
24 U9 1 AP2127K-1.2TRG1 stdpads:SOT-23-5 C151376 Diodes AP2127K-1.2TRG1, Torex XC6228D122VR Most 1.2V regulator in SOT-23-5 package is acceptable.

BIN
Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Placement 2.pdf
View File

Binary file not shown.

BIN
Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Placement.pdf
View File

Binary file not shown.

BIN
Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Schematic 2.pdf
View File

Binary file not shown.

BIN
Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Schematic.pdf
View File

Binary file not shown.

75602
Hardware/LCMXO2/RAM2E.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

8
Hardware/LCMXO2/RAM2E.kicad_sch
View File

@ -5034,7 +5034,7 @@
(property "Reference" "U3" (at 76.2 22.86 0)
(effects (font (size 1.27 1.27)))
)
(property "Value" "74LVC245APW" (at 76.2 53.34 0)
(property "Value" "74AHC245PW" (at 76.2 53.34 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 76.2 54.61 0)
@ -5043,7 +5043,7 @@
(property "Datasheet" "" (at 76.2 35.56 0)
(effects (font (size 1.524 1.524)) hide)
)
(property "LCSC Part" "C6082" (at 76.2 38.1 0)
(property "LCSC Part" "C5516" (at 76.2 38.1 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Mfg. Part Numbers" "NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW" (at 76.2 38.1 0)
@ -5087,7 +5087,7 @@
(property "Reference" "U5" (at 76.2 88.9 0)
(effects (font (size 1.27 1.27)))
)
(property "Value" "74LVC245APW" (at 76.2 119.38 0)
(property "Value" "74AHC245PW" (at 76.2 119.38 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 76.2 120.65 0)
@ -5096,7 +5096,7 @@
(property "Datasheet" "" (at 76.2 101.6 0)
(effects (font (size 1.524 1.524)) hide)
)
(property "LCSC Part" "C6082" (at 76.2 104.14 0)
(property "LCSC Part" "C5516" (at 76.2 104.14 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Mfg. Part Numbers" "NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW" (at 76.2 104.14 0)

13558
Hardware/LCMXO2/gerber/RAM2E-B_Cu.gbl
View File

File diff suppressed because it is too large Load Diff

2158
Hardware/LCMXO2/gerber/RAM2E-B_Mask.gbs
View File

File diff suppressed because it is too large Load Diff

1369
Hardware/LCMXO2/gerber/RAM2E-B_Silkscreen.gbo
View File

File diff suppressed because it is too large Load Diff

6
Hardware/LCMXO2/gerber/RAM2E-Edge_Cuts.gm1
View File

@ -1,11 +1,11 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.1-0*
G04 #@! TF.CreationDate,2023-10-30T17:31:41-04:00*
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.10*
G04 #@! TF.CreationDate,2024-02-07T20:48:26-05:00*
G04 #@! TF.ProjectId,RAM2E,52414d32-452e-46b6-9963-61645f706362,2.1*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 7.0.1-0) date 2023-10-30 17:31:41*
G04 Created by KiCad (PCBNEW 7.0.10) date 2024-02-07 20:48:26*
%MOMM*%
%LPD*%
G01*

26083
Hardware/LCMXO2/gerber/RAM2E-F_Cu.gtl
View File

File diff suppressed because it is too large Load Diff

16277
Hardware/LCMXO2/gerber/RAM2E-F_Mask.gts
View File

File diff suppressed because it is too large Load Diff

46
Hardware/LCMXO2/gerber/RAM2E-F_Paste.gtp
View File

@ -1,12 +1,12 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.1-0*
G04 #@! TF.CreationDate,2023-10-30T17:31:41-04:00*
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.10*
G04 #@! TF.CreationDate,2024-02-07T20:48:26-05:00*
G04 #@! TF.ProjectId,RAM2E,52414d32-452e-46b6-9963-61645f706362,2.1*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Paste,Top*
G04 #@! TF.FilePolarity,Positive*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 7.0.1-0) date 2023-10-30 17:31:41*
G04 Created by KiCad (PCBNEW 7.0.10) date 2024-02-07 20:48:26*
%MOMM*%
%LPD*%
G01*
@ -29,26 +29,26 @@ G04 Aperture macros list*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10RoundRect,0.072500X0.112500X-0.612500X0.112500X0.612500X-0.112500X0.612500X-0.112500X-0.612500X0*%
%ADD11RoundRect,0.172500X-0.262500X0.212500X-0.262500X-0.212500X0.262500X-0.212500X0.262500X0.212500X0*%
%ADD12RoundRect,0.172500X0.262500X-0.212500X0.262500X0.212500X-0.262500X0.212500X-0.262500X-0.212500X0*%
%ADD13RoundRect,0.084500X-0.640500X-0.114500X0.640500X-0.114500X0.640500X0.114500X-0.640500X0.114500X0*%
%ADD14RoundRect,0.237500X0.262500X0.437500X-0.262500X0.437500X-0.262500X-0.437500X0.262500X-0.437500X0*%
%ADD15RoundRect,0.237500X-0.437500X0.262500X-0.437500X-0.262500X0.437500X-0.262500X0.437500X0.262500X0*%
%ADD16RoundRect,0.172500X-0.212500X-0.262500X0.212500X-0.262500X0.212500X0.262500X-0.212500X0.262500X0*%
%ADD17RoundRect,0.187500X-0.212500X-0.487500X0.212500X-0.487500X0.212500X0.487500X-0.212500X0.487500X0*%
%ADD18RoundRect,0.237500X0.437500X-0.262500X0.437500X0.262500X-0.437500X0.262500X-0.437500X-0.262500X0*%
%ADD19RoundRect,0.150000X-0.475000X-0.200000X0.475000X-0.200000X0.475000X0.200000X-0.475000X0.200000X0*%
%ADD20RoundRect,0.187500X0.487500X-0.212500X0.487500X0.212500X-0.487500X0.212500X-0.487500X-0.212500X0*%
%ADD21RoundRect,0.125000X-0.175000X-0.300000X0.175000X-0.300000X0.175000X0.300000X-0.175000X0.300000X0*%
%ADD22RoundRect,0.172500X0.212500X0.262500X-0.212500X0.262500X-0.212500X-0.262500X0.212500X-0.262500X0*%
%ADD23RoundRect,0.205650X0.243750X0.456250X-0.243750X0.456250X-0.243750X-0.456250X0.243750X-0.456250X0*%
%ADD24RoundRect,0.125000X-0.300000X0.175000X-0.300000X-0.175000X0.300000X-0.175000X0.300000X0.175000X0*%
%ADD25RoundRect,0.040000X0.662500X0.075000X-0.662500X0.075000X-0.662500X-0.075000X0.662500X-0.075000X0*%
%ADD26RoundRect,0.040000X0.075000X0.662500X-0.075000X0.662500X-0.075000X-0.662500X0.075000X-0.662500X0*%
%ADD27RoundRect,0.125000X0.175000X0.300000X-0.175000X0.300000X-0.175000X-0.300000X0.175000X-0.300000X0*%
%ADD28RoundRect,0.125000X0.300000X-0.175000X0.300000X0.175000X-0.300000X0.175000X-0.300000X-0.175000X0*%
%ADD29RoundRect,0.112500X0.512500X0.162500X-0.512500X0.162500X-0.512500X-0.162500X0.512500X-0.162500X0*%
%ADD10RoundRect,0.092500X0.092500X-0.592500X0.092500X0.592500X-0.092500X0.592500X-0.092500X-0.592500X0*%
%ADD11RoundRect,0.192500X-0.242500X0.192500X-0.242500X-0.192500X0.242500X-0.192500X0.242500X0.192500X0*%
%ADD12RoundRect,0.192500X0.242500X-0.192500X0.242500X0.192500X-0.242500X0.192500X-0.242500X-0.192500X0*%
%ADD13RoundRect,0.099500X-0.625500X-0.099500X0.625500X-0.099500X0.625500X0.099500X-0.625500X0.099500X0*%
%ADD14RoundRect,0.250000X0.250000X0.425000X-0.250000X0.425000X-0.250000X-0.425000X0.250000X-0.425000X0*%
%ADD15RoundRect,0.250000X-0.425000X0.250000X-0.425000X-0.250000X0.425000X-0.250000X0.425000X0.250000X0*%
%ADD16RoundRect,0.192500X-0.192500X-0.242500X0.192500X-0.242500X0.192500X0.242500X-0.192500X0.242500X0*%
%ADD17RoundRect,0.200000X-0.200000X-0.475000X0.200000X-0.475000X0.200000X0.475000X-0.200000X0.475000X0*%
%ADD18RoundRect,0.250000X0.425000X-0.250000X0.425000X0.250000X-0.425000X0.250000X-0.425000X-0.250000X0*%
%ADD19RoundRect,0.175000X-0.450000X-0.175000X0.450000X-0.175000X0.450000X0.175000X-0.450000X0.175000X0*%
%ADD20RoundRect,0.200000X0.475000X-0.200000X0.475000X0.200000X-0.475000X0.200000X-0.475000X-0.200000X0*%
%ADD21RoundRect,0.150000X-0.150000X-0.275000X0.150000X-0.275000X0.150000X0.275000X-0.150000X0.275000X0*%
%ADD22RoundRect,0.192500X0.192500X0.242500X-0.192500X0.242500X-0.192500X-0.242500X0.192500X-0.242500X0*%
%ADD23RoundRect,0.224700X0.224700X0.437200X-0.224700X0.437200X-0.224700X-0.437200X0.224700X-0.437200X0*%
%ADD24RoundRect,0.150000X-0.275000X0.150000X-0.275000X-0.150000X0.275000X-0.150000X0.275000X0.150000X0*%
%ADD25RoundRect,0.057500X0.645000X0.057500X-0.645000X0.057500X-0.645000X-0.057500X0.645000X-0.057500X0*%
%ADD26RoundRect,0.057500X0.057500X0.645000X-0.057500X0.645000X-0.057500X-0.645000X0.057500X-0.645000X0*%
%ADD27RoundRect,0.150000X0.150000X0.275000X-0.150000X0.275000X-0.150000X-0.275000X0.150000X-0.275000X0*%
%ADD28RoundRect,0.150000X0.275000X-0.150000X0.275000X0.150000X-0.275000X0.150000X-0.275000X-0.150000X0*%
%ADD29RoundRect,0.137500X0.487500X0.137500X-0.487500X0.137500X-0.487500X-0.137500X0.487500X-0.137500X0*%
G04 APERTURE END LIST*
D10*
X236250000Y-127550000D03*

2850
Hardware/LCMXO2/gerber/RAM2E-F_Silkscreen.gto
View File

File diff suppressed because it is too large Load Diff

13347
Hardware/LCMXO2/gerber/RAM2E-In1_Cu.g2
View File

File diff suppressed because it is too large Load Diff

22596
Hardware/LCMXO2/gerber/RAM2E-In2_Cu.g3
View File

File diff suppressed because it is too large Load Diff

4
Hardware/LCMXO2/gerber/RAM2E-job.gbrjob
View File

@ -3,9 +3,9 @@
"GenerationSoftware": {
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "7.0.1-0"
"Version": "7.0.10"
},
"CreationDate": "2023-10-30T17:31:41-04:00"
"CreationDate": "2024-02-07T20:48:26-05:00"
},
"GeneralSpecs": {
"ProjectId": {

4
Hardware/LCMXO2/gerber/RAM2E-top-pos.JUMPER.csv
View File

@ -49,9 +49,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R13","47","R_0603",228.000000,-118.550000,-90.000000,top
"U1","LCMXO2-TG100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
49 R13 47 R_0603 228.000000 -118.550000 -90.000000 top
50 U1 LCMXO2-TG100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 90.000000 top
51 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
52 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
53 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
54 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
55 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
56 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
57 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

4
Hardware/LCMXO2/gerber/RAM2E-top-pos.VCORE.csv
View File

@ -48,9 +48,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R13","47","R_0603",228.000000,-118.550000,-90.000000,top
"U1","LCMXO2-TG100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
48 R13 47 R_0603 228.000000 -118.550000 -90.000000 top
49 U1 LCMXO2-TG100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 90.000000 top
50 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
51 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
52 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
53 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
54 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
55 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
56 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

4
Hardware/LCMXO2/gerber/RAM2E-top-pos.csv
View File

@ -49,9 +49,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R13","47","R_0603",228.000000,-118.550000,-90.000000,top
"U1","LCMXO2-TG100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
49 R13 47 R_0603 228.000000 -118.550000 -90.000000 top
50 U1 LCMXO2-TG100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 90.000000 top
51 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
52 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
53 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
54 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
55 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
56 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
57 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

BIN
Hardware/LCMXO2/gerber/RAM2E.4203B.LCMXO2-gerber 2.zip
View File

Binary file not shown.

BIN
Hardware/LCMXO2/gerber/RAM2E.4203B.LCMXO2-gerber.zip
View File

Binary file not shown.

1033
Hardware/LCMXO2/gerber/RAM2E.drl
View File

File diff suppressed because it is too large Load Diff

5
Hardware/MAX/BOM/RAM2E-BOM.MAXII.csv
View File

@ -16,7 +16,8 @@ R8 ,1,220,stdpads:R_0805,,C17557,Uniroyal 0805W8F2200T5E,Any manufacturer's part
R9 R10 ,2,22k,stdpads:R_0805,,C17560,Uniroyal 0805W8F2202T5E,Any manufacturer's part is acceptable.
U1 ,1,EPM240T100,stdpads:TQFP-100_14x14mm_P0.5mm,,C10041,"Altera EPM240T100C5N, Altera EPM240T100C4N, Altera EPM240T100C3N, Altera EPM240T100I5N, Altera EPM240T100I4N, Altera EPM240T100A5N, Altera EPM240T100A4N",
U2 ,1,W9812G6KH-6,stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm,,C62379,"Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G",Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
U3 U4 U5 ,3,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U4 ,1,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U3 U5 ,2,74AHC245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C5516,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U6 U7 ,2,74AHCT245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C173388,"NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW",Most 74AHCT245 in TSSOP-20 package is acceptable.
U8 ,1,XC6206P332MR,stdpads:SOT-23,,C5446,Torex XC6206P332MR,Most 3.3V regulator in SOT-23 package is acceptable.
U9 ,1,AP2127K-1.8TRG1,stdpads:SOT-23-5,,C151375,"Diodes AP2127K-1.8TRG1, Torex XC6228D182VR",Most 1.8V regulator in SOT-23-5 package is acceptable.
U9 ,1,DNP,stdpads:SOT-23-5,,,,

1 Reference Quantity Value Footprint Datasheet LCSC Part Mfg. Part Numbers Notes
16 R9 R10 2 22k stdpads:R_0805 C17560 Uniroyal 0805W8F2202T5E Any manufacturer's part is acceptable.
17 U1 1 EPM240T100 stdpads:TQFP-100_14x14mm_P0.5mm C10041 Altera EPM240T100C5N, Altera EPM240T100C4N, Altera EPM240T100C3N, Altera EPM240T100I5N, Altera EPM240T100I4N, Altera EPM240T100A5N, Altera EPM240T100A4N
18 U2 1 W9812G6KH-6 stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm C62379 Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
19 U3 U4 U5 U4 3 1 74LVC245APW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
20 U3 U5 2 74AHC245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C5516 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
21 U6 U7 2 74AHCT245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C173388 NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW Most 74AHCT245 in TSSOP-20 package is acceptable.
22 U8 1 XC6206P332MR stdpads:SOT-23 C5446 Torex XC6206P332MR Most 3.3V regulator in SOT-23 package is acceptable.
23 U9 1 AP2127K-1.8TRG1 DNP stdpads:SOT-23-5 C151375 Diodes AP2127K-1.8TRG1, Torex XC6228D182VR Most 1.8V regulator in SOT-23-5 package is acceptable.

5
Hardware/MAX/BOM/RAM2E-BOM.MAXV.csv
View File

@ -16,7 +16,8 @@ R8 ,1,220,stdpads:R_0805,,C17557,Uniroyal 0805W8F2200T5E,Any manufacturer's part
R9 R10 ,2,22k,stdpads:R_0805,,C17560,Uniroyal 0805W8F2202T5E,Any manufacturer's part is acceptable.
U1 ,1,5M240ZT100,stdpads:TQFP-100_14x14mm_P0.5mm,,C10041,"Altera 5M240ZT100C5N, Altera 5M240ZT100C4N, Altera 5M240ZT100C3N, Altera 5M240ZT100I5N, Altera 5M240ZT100I4N, Altera 5M240ZT100A5N, Altera 5M240ZT100A4N",
U2 ,1,W9812G6KH-6,stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm,,C62379,"Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G",Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
U3 U4 U5 ,3,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U4 ,1,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U3 U5 ,2,74AHC245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C5516,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U6 U7 ,2,74AHCT245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C173388,"NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW",Most 74AHCT245 in TSSOP-20 package is acceptable.
U8 ,1,XC6206P332MR,stdpads:SOT-23,,C5446,Torex XC6206P332MR,Most 3.3V regulator in SOT-23 package is acceptable.
U9 ,1,AP2127K-1.8TRG1,stdpads:SOT-23-5,,C151375,"Diodes AP2127K-1.8TRG1, Torex XC6228D182VR",Most 1.8V regulator in SOT-23-5 package is acceptable.
U9 ,1,AP2127K-1.8TRG1,stdpads:SOT-23-5,,C151375,"Diodes AP2127K-1.8TRG1, Torex XC6228D182VR",Most 1.8V regulator in SOT-23-5 package is acceptable.

1 Reference Quantity Value Footprint Datasheet LCSC Part Mfg. Part Numbers Notes
16 R9 R10 2 22k stdpads:R_0805 C17560 Uniroyal 0805W8F2202T5E Any manufacturer's part is acceptable.
17 U1 1 5M240ZT100 stdpads:TQFP-100_14x14mm_P0.5mm C10041 Altera 5M240ZT100C5N, Altera 5M240ZT100C4N, Altera 5M240ZT100C3N, Altera 5M240ZT100I5N, Altera 5M240ZT100I4N, Altera 5M240ZT100A5N, Altera 5M240ZT100A4N
18 U2 1 W9812G6KH-6 stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm C62379 Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
19 U3 U4 U5 U4 3 1 74LVC245APW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
20 U3 U5 2 74AHC245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C5516 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
21 U6 U7 2 74AHCT245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C173388 NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW Most 74AHCT245 in TSSOP-20 package is acceptable.
22 U8 1 XC6206P332MR stdpads:SOT-23 C5446 Torex XC6206P332MR Most 3.3V regulator in SOT-23 package is acceptable.
23 U9 1 AP2127K-1.8TRG1 stdpads:SOT-23-5 C151375 Diodes AP2127K-1.8TRG1, Torex XC6228D182VR Most 1.8V regulator in SOT-23-5 package is acceptable.

BIN
Hardware/MAX/Documentation/RAM2E.4203B.MAX-Placement.pdf
View File

Binary file not shown.

BIN
Hardware/MAX/Documentation/RAM2E.4203B.MAX-Schematic.pdf
View File

Binary file not shown.

51752
Hardware/MAX/RAM2E.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

6
Hardware/MAX/RAM2E.kicad_pro
View File

@ -517,12 +517,8 @@
},
"sheets": [
[
"0dd11af3-0465-4c84-bbb0-f3ae16a77316",
"ca91ccfe-7a99-4124-b7c6-e1f3ffab8bf1",
""
],
[
"00000000-0000-0000-0000-00005e93a857",
"Docs"
]
],
"text_variables": {}

8
Hardware/MAX/RAM2E.kicad_sch
View File

@ -4969,7 +4969,7 @@
(property "Reference" "U3" (at 76.2 22.86 0)
(effects (font (size 1.27 1.27)))
)
(property "Value" "74LVC245APW" (at 76.2 53.34 0)
(property "Value" "74AHC245PW" (at 76.2 53.34 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 76.2 54.61 0)
@ -4978,7 +4978,7 @@
(property "Datasheet" "" (at 76.2 35.56 0)
(effects (font (size 1.524 1.524)) hide)
)
(property "LCSC Part" "C6082" (at 76.2 38.1 0)
(property "LCSC Part" "C5516" (at 76.2 38.1 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Mfg. Part Numbers" "NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW" (at 76.2 38.1 0)
@ -5022,7 +5022,7 @@
(property "Reference" "U5" (at 76.2 88.9 0)
(effects (font (size 1.27 1.27)))
)
(property "Value" "74LVC245APW" (at 76.2 119.38 0)
(property "Value" "74AHC245PW" (at 76.2 119.38 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 76.2 120.65 0)
@ -5031,7 +5031,7 @@
(property "Datasheet" "" (at 76.2 101.6 0)
(effects (font (size 1.524 1.524)) hide)
)
(property "LCSC Part" "C6082" (at 76.2 104.14 0)
(property "LCSC Part" "C5516" (at 76.2 104.14 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Mfg. Part Numbers" "NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW" (at 76.2 104.14 0)

10596
Hardware/MAX/gerber/RAM2E-B_Cu.gbl
View File

File diff suppressed because it is too large Load Diff

2158
Hardware/MAX/gerber/RAM2E-B_Mask.gbs
View File

File diff suppressed because it is too large Load Diff

1321
Hardware/MAX/gerber/RAM2E-B_Silkscreen.gbo
View File

File diff suppressed because it is too large Load Diff

6
Hardware/MAX/gerber/RAM2E-Edge_Cuts.gm1
View File

@ -1,11 +1,11 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.1-0*
G04 #@! TF.CreationDate,2023-10-30T17:31:38-04:00*
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.10*
G04 #@! TF.CreationDate,2024-02-07T20:48:24-05:00*
G04 #@! TF.ProjectId,RAM2E,52414d32-452e-46b6-9963-61645f706362,2.1*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 7.0.1-0) date 2023-10-30 17:31:38*
G04 Created by KiCad (PCBNEW 7.0.10) date 2024-02-07 20:48:24*
%MOMM*%
%LPD*%
G01*

22950
Hardware/MAX/gerber/RAM2E-F_Cu.gtl
View File

File diff suppressed because it is too large Load Diff

15541
Hardware/MAX/gerber/RAM2E-F_Mask.gts
View File

File diff suppressed because it is too large Load Diff

44
Hardware/MAX/gerber/RAM2E-F_Paste.gtp
View File

@ -1,12 +1,12 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.1-0*
G04 #@! TF.CreationDate,2023-10-30T17:31:38-04:00*
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.10*
G04 #@! TF.CreationDate,2024-02-07T20:48:24-05:00*
G04 #@! TF.ProjectId,RAM2E,52414d32-452e-46b6-9963-61645f706362,2.1*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Paste,Top*
G04 #@! TF.FilePolarity,Positive*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 7.0.1-0) date 2023-10-30 17:31:38*
G04 Created by KiCad (PCBNEW 7.0.10) date 2024-02-07 20:48:24*
%MOMM*%
%LPD*%
G01*
@ -29,25 +29,25 @@ G04 Aperture macros list*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10RoundRect,0.072500X0.112500X-0.612500X0.112500X0.612500X-0.112500X0.612500X-0.112500X-0.612500X0*%
%ADD11RoundRect,0.172500X-0.262500X0.212500X-0.262500X-0.212500X0.262500X-0.212500X0.262500X0.212500X0*%
%ADD12RoundRect,0.172500X0.262500X-0.212500X0.262500X0.212500X-0.262500X0.212500X-0.262500X-0.212500X0*%
%ADD13RoundRect,0.172500X-0.212500X-0.262500X0.212500X-0.262500X0.212500X0.262500X-0.212500X0.262500X0*%
%ADD14RoundRect,0.084500X-0.640500X-0.114500X0.640500X-0.114500X0.640500X0.114500X-0.640500X0.114500X0*%
%ADD15RoundRect,0.172500X0.212500X0.262500X-0.212500X0.262500X-0.212500X-0.262500X0.212500X-0.262500X0*%
%ADD16RoundRect,0.040000X-0.662500X-0.075000X0.662500X-0.075000X0.662500X0.075000X-0.662500X0.075000X0*%
%ADD17RoundRect,0.040000X-0.075000X-0.662500X0.075000X-0.662500X0.075000X0.662500X-0.075000X0.662500X0*%
%ADD18RoundRect,0.237500X0.262500X0.437500X-0.262500X0.437500X-0.262500X-0.437500X0.262500X-0.437500X0*%
%ADD19RoundRect,0.237500X-0.437500X0.262500X-0.437500X-0.262500X0.437500X-0.262500X0.437500X0.262500X0*%
%ADD20RoundRect,0.187500X-0.212500X-0.487500X0.212500X-0.487500X0.212500X0.487500X-0.212500X0.487500X0*%
%ADD21RoundRect,0.187500X0.212500X0.487500X-0.212500X0.487500X-0.212500X-0.487500X0.212500X-0.487500X0*%
%ADD22RoundRect,0.237500X0.437500X-0.262500X0.437500X0.262500X-0.437500X0.262500X-0.437500X-0.262500X0*%
%ADD23RoundRect,0.150000X-0.475000X-0.200000X0.475000X-0.200000X0.475000X0.200000X-0.475000X0.200000X0*%
%ADD24RoundRect,0.112500X0.512500X0.162500X-0.512500X0.162500X-0.512500X-0.162500X0.512500X-0.162500X0*%
%ADD25RoundRect,0.187500X0.487500X-0.212500X0.487500X0.212500X-0.487500X0.212500X-0.487500X-0.212500X0*%
%ADD26RoundRect,0.125000X-0.300000X0.175000X-0.300000X-0.175000X0.300000X-0.175000X0.300000X0.175000X0*%
%ADD27RoundRect,0.125000X-0.175000X-0.300000X0.175000X-0.300000X0.175000X0.300000X-0.175000X0.300000X0*%
%ADD28RoundRect,0.205650X0.243750X0.456250X-0.243750X0.456250X-0.243750X-0.456250X0.243750X-0.456250X0*%
%ADD10RoundRect,0.092500X0.092500X-0.592500X0.092500X0.592500X-0.092500X0.592500X-0.092500X-0.592500X0*%
%ADD11RoundRect,0.192500X-0.242500X0.192500X-0.242500X-0.192500X0.242500X-0.192500X0.242500X0.192500X0*%
%ADD12RoundRect,0.192500X0.242500X-0.192500X0.242500X0.192500X-0.242500X0.192500X-0.242500X-0.192500X0*%
%ADD13RoundRect,0.192500X-0.192500X-0.242500X0.192500X-0.242500X0.192500X0.242500X-0.192500X0.242500X0*%
%ADD14RoundRect,0.099500X-0.625500X-0.099500X0.625500X-0.099500X0.625500X0.099500X-0.625500X0.099500X0*%
%ADD15RoundRect,0.192500X0.192500X0.242500X-0.192500X0.242500X-0.192500X-0.242500X0.192500X-0.242500X0*%
%ADD16RoundRect,0.057500X-0.645000X-0.057500X0.645000X-0.057500X0.645000X0.057500X-0.645000X0.057500X0*%
%ADD17RoundRect,0.057500X-0.057500X-0.645000X0.057500X-0.645000X0.057500X0.645000X-0.057500X0.645000X0*%
%ADD18RoundRect,0.250000X0.250000X0.425000X-0.250000X0.425000X-0.250000X-0.425000X0.250000X-0.425000X0*%
%ADD19RoundRect,0.250000X-0.425000X0.250000X-0.425000X-0.250000X0.425000X-0.250000X0.425000X0.250000X0*%
%ADD20RoundRect,0.200000X-0.200000X-0.475000X0.200000X-0.475000X0.200000X0.475000X-0.200000X0.475000X0*%
%ADD21RoundRect,0.200000X0.200000X0.475000X-0.200000X0.475000X-0.200000X-0.475000X0.200000X-0.475000X0*%
%ADD22RoundRect,0.250000X0.425000X-0.250000X0.425000X0.250000X-0.425000X0.250000X-0.425000X-0.250000X0*%
%ADD23RoundRect,0.175000X-0.450000X-0.175000X0.450000X-0.175000X0.450000X0.175000X-0.450000X0.175000X0*%
%ADD24RoundRect,0.137500X0.487500X0.137500X-0.487500X0.137500X-0.487500X-0.137500X0.487500X-0.137500X0*%
%ADD25RoundRect,0.200000X0.475000X-0.200000X0.475000X0.200000X-0.475000X0.200000X-0.475000X-0.200000X0*%
%ADD26RoundRect,0.150000X-0.275000X0.150000X-0.275000X-0.150000X0.275000X-0.150000X0.275000X0.150000X0*%
%ADD27RoundRect,0.150000X-0.150000X-0.275000X0.150000X-0.275000X0.150000X0.275000X-0.150000X0.275000X0*%
%ADD28RoundRect,0.224700X0.224700X0.437200X-0.224700X0.437200X-0.224700X-0.437200X0.224700X-0.437200X0*%
G04 APERTURE END LIST*
D10*
X236250000Y-127550000D03*

2848
Hardware/MAX/gerber/RAM2E-F_Silkscreen.gto
View File

File diff suppressed because it is too large Load Diff

6322
Hardware/MAX/gerber/RAM2E-In1_Cu.g2
View File

File diff suppressed because it is too large Load Diff

11930
Hardware/MAX/gerber/RAM2E-In2_Cu.g3
View File

File diff suppressed because it is too large Load Diff

4
Hardware/MAX/gerber/RAM2E-job.gbrjob
View File

@ -3,9 +3,9 @@
"GenerationSoftware": {
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "7.0.1-0"
"Version": "7.0.10"
},
"CreationDate": "2023-10-30T17:31:38-04:00"
"CreationDate": "2024-02-07T20:48:24-05:00"
},
"GeneralSpecs": {
"ProjectId": {

4
Hardware/MAX/gerber/RAM2E-top-pos.JUMPER.csv
View File

@ -44,9 +44,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R10","22k","R_0805",207.264000,-108.077000,180.000000,top
"U1","EPM240T100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,-90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
44 R10 22k R_0805 207.264000 -108.077000 180.000000 top
45 U1 EPM240T100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 -90.000000 top
46 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
47 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
48 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
49 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
50 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
51 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
52 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

4
Hardware/MAX/gerber/RAM2E-top-pos.VCORE.csv
View File

@ -43,9 +43,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R10","22k","R_0805",207.264000,-108.077000,180.000000,top
"U1","EPM240T100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,-90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
43 R10 22k R_0805 207.264000 -108.077000 180.000000 top
44 U1 EPM240T100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 -90.000000 top
45 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
46 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
47 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
48 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
49 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
50 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
51 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

4
Hardware/MAX/gerber/RAM2E-top-pos.csv
View File

@ -44,9 +44,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R10","22k","R_0805",207.264000,-108.077000,180.000000,top
"U1","EPM240T100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,-90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
44 R10 22k R_0805 207.264000 -108.077000 180.000000 top
45 U1 EPM240T100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 -90.000000 top
46 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
47 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
48 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
49 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
50 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
51 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
52 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

BIN
Hardware/MAX/gerber/RAM2E.4203B.MAX-gerber.zip
View File

Binary file not shown.

1109
Hardware/MAX/gerber/RAM2E.drl
View File

File diff suppressed because it is too large Load Diff

1
Makefile
View File

@ -51,6 +51,7 @@ Hardware/MAX/gerber Hardware/LCMXO2/gerber:
cp $(F_POS) $(F_POS_JUMPER)
sed -i '' '/"R1"/d' $(F_POS_VCORE)
sed -i '' '/"U9"/d' $(F_POS_JUMPER)
rm -f $(F_ZIP)
zip -r $(F_ZIP) $@/
Hardware/MAX/Documentation Hardware/LCMXO2/Documentation:
mkdir -p $@