Compare commits
2 Commits
c72df9e5e0
...
520e7edbdf
| Author | SHA1 | Date |
|---|---|---|
Zane Kaminski
|
520e7edbdf | |
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Zane Kaminski
|
1c1dcf9ba0 |
Binary file not shown.
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@ -1,5 +1,5 @@
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Assembler report for RAM2E
|
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Thu Dec 28 23:09:46 2023
|
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Thu Jan 11 09:29:25 2024
|
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
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@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
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+---------------------------------------------------------------+
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; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Thu Dec 28 23:09:46 2023 ;
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; Assembler Status ; Successful - Thu Jan 11 09:29:25 2024 ;
|
||||
; Revision Name ; RAM2E ;
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; Top-level Entity Name ; RAM2E ;
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; Family ; MAX II ;
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@ -78,13 +78,13 @@ https://fpgasoftware.intel.com/eula.
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Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:46 2023
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Info: Processing started: Thu Jan 11 09:29:24 2024
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Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E
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Info (115031): Writing out detailed assembly data for power analysis
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Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13071 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:47 2023
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||||
Info: Peak virtual memory: 13074 megabytes
|
||||
Info: Processing ended: Thu Jan 11 09:29:25 2024
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||||
Info: Elapsed time: 00:00:01
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||||
Info: Total CPU time (on all processors): 00:00:01
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@ -1 +1 @@
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Thu Dec 28 23:09:51 2023
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Thu Jan 11 09:29:29 2024
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@ -1,5 +1,5 @@
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Fitter report for RAM2E
|
||||
Thu Dec 28 23:09:44 2023
|
||||
Thu Jan 11 09:29:23 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
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@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula.
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|||
+-------------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
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||||
+-----------------------+-------------------------------------------------------------+
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||||
; Fitter Status ; Successful - Thu Dec 28 23:09:44 2023 ;
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; Fitter Status ; Successful - Thu Jan 11 09:29:23 2024 ;
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||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
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||||
; Top-level Entity Name ; RAM2E ;
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||||
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@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula.
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; Number detected on machine ; 4 ;
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||||
; Maximum allowed ; 4 ;
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||||
; ; ;
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||||
; Average used ; 1.03 ;
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||||
; Average used ; 1.04 ;
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||||
; Maximum used ; 4 ;
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||||
; ; ;
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||||
; Usage by Processor ; % Time Used ;
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||||
; Processor 1 ; 100.0% ;
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||||
; Processor 2 ; 1.1% ;
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||||
; Processors 3-4 ; 1.0% ;
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||||
; Processor 2 ; 1.8% ;
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||||
; Processors 3-4 ; 1.3% ;
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||||
+----------------------------+-------------+
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||||
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@ -728,14 +728,14 @@ Info (170089): 5e+01 ns of routing delay (approximately 3.0% of available device
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Info (170195): Router estimated average interconnect usage is 24% of the available device resources
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||||
Info (170196): Router estimated peak interconnect usage is 24% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
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||||
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
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Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
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||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.84 seconds.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.44 seconds.
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 13747 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:44 2023
|
||||
Info: Elapsed time: 00:00:04
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||||
Info: Peak virtual memory: 13748 megabytes
|
||||
Info: Processing ended: Thu Jan 11 09:29:23 2024
|
||||
Info: Elapsed time: 00:00:03
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||||
Info: Total CPU time (on all processors): 00:00:04
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||||
|
||||
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||||
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@ -1,4 +1,4 @@
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|||
Fitter Status : Successful - Thu Dec 28 23:09:44 2023
|
||||
Fitter Status : Successful - Thu Jan 11 09:29:23 2024
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2E
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||||
Top-level Entity Name : RAM2E
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||||
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@ -1,5 +1,5 @@
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Flow report for RAM2E
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||||
Thu Dec 28 23:09:50 2023
|
||||
Thu Jan 11 09:29:28 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
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@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
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|||
+-------------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Dec 28 23:09:46 2023 ;
|
||||
; Flow Status ; Successful - Thu Jan 11 09:29:25 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
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||||
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@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
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+-------------------+---------------------+
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||||
; Option ; Setting ;
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||||
+-------------------+---------------------+
|
||||
; Start date & time ; 12/28/2023 23:09:12 ;
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||||
; Start date & time ; 01/11/2024 09:28:55 ;
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; Main task ; Compilation ;
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||||
; Revision Name ; RAM2E ;
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||||
+-------------------+---------------------+
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@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
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|||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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||||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.170382295203604 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.170498333501484 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
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||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
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||||
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
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||||
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@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
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|||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:28 ; 1.0 ; 13113 MB ; 00:00:42 ;
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||||
; Fitter ; 00:00:04 ; 1.0 ; 13747 MB ; 00:00:04 ;
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||||
; Assembler ; 00:00:00 ; 1.0 ; 13067 MB ; 00:00:01 ;
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||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13064 MB ; 00:00:02 ;
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||||
; Total ; 00:00:34 ; -- ; -- ; 00:00:49 ;
|
||||
; Analysis & Synthesis ; 00:00:25 ; 1.0 ; 13116 MB ; 00:00:41 ;
|
||||
; Fitter ; 00:00:03 ; 1.0 ; 13748 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13070 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13066 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:31 ; -- ; -- ; 00:00:47 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
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||||
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||||
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@ -1,5 +1,5 @@
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|||
Analysis & Synthesis report for RAM2E
|
||||
Thu Dec 28 23:09:39 2023
|
||||
Thu Jan 11 09:29:19 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
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@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula.
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|||
+-------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Dec 28 23:09:39 2023 ;
|
||||
; Analysis & Synthesis Status ; Successful - Thu Jan 11 09:29:19 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
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@ -281,7 +281,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:11 2023
|
||||
Info: Processing started: Thu Jan 11 09:28:54 2024
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
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||||
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@ -315,10 +315,10 @@ Info (21057): Implemented 315 device resources after synthesis - the final resou
|
|||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
|
||||
Info: Peak virtual memory: 13113 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:39 2023
|
||||
Info: Elapsed time: 00:00:28
|
||||
Info: Total CPU time (on all processors): 00:00:42
|
||||
Info: Peak virtual memory: 13116 megabytes
|
||||
Info: Processing ended: Thu Jan 11 09:29:19 2024
|
||||
Info: Elapsed time: 00:00:25
|
||||
Info: Total CPU time (on all processors): 00:00:41
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
|
|
|
|||
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@ -1,4 +1,4 @@
|
|||
Analysis & Synthesis Status : Successful - Thu Dec 28 23:09:39 2023
|
||||
Analysis & Synthesis Status : Successful - Thu Jan 11 09:29:19 2024
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
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|
|||
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@ -1,5 +1,5 @@
|
|||
Timing Analyzer report for RAM2E
|
||||
Thu Dec 28 23:09:50 2023
|
||||
Thu Jan 11 09:29:28 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
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@ -80,10 +80,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
; Maximum used ; 1 ;
|
||||
; Maximum used ; 2 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.1% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
|
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@ -92,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
|
|||
+------------------+--------+--------------------------+
|
||||
; SDC File Path ; Status ; Read at ;
|
||||
+------------------+--------+--------------------------+
|
||||
; ../RAM2E.sdc ; OK ; Thu Dec 28 23:09:50 2023 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Thu Dec 28 23:09:50 2023 ;
|
||||
; ../RAM2E.sdc ; OK ; Thu Jan 11 09:29:28 2024 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Thu Jan 11 09:29:28 2024 ;
|
||||
+------------------+--------+--------------------------+
|
||||
|
||||
|
||||
|
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@ -678,7 +679,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:48 2023
|
||||
Info: Processing started: Thu Jan 11 09:29:26 2024
|
||||
Info: Command: quartus_sta RAM2E-MAXII -c RAM2E
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
|
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@ -719,9 +720,9 @@ Warning (332009): The launch and latch times for the relationship between source
|
|||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
|
||||
Info: Peak virtual memory: 13064 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:50 2023
|
||||
Info: Peak virtual memory: 13066 megabytes
|
||||
Info: Processing ended: Thu Jan 11 09:29:28 2024
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
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|
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Binary file not shown.
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@ -1,5 +1,5 @@
|
|||
Assembler report for RAM2E
|
||||
Thu Dec 28 23:09:48 2023
|
||||
Thu Jan 11 09:29:26 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Thu Dec 28 23:09:48 2023 ;
|
||||
; Assembler Status ; Successful - Thu Jan 11 09:29:26 2024 ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
|
|
@ -78,13 +78,13 @@ https://fpgasoftware.intel.com/eula.
|
|||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:47 2023
|
||||
Info: Processing started: Thu Jan 11 09:29:25 2024
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13070 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:48 2023
|
||||
Info: Peak virtual memory: 13073 megabytes
|
||||
Info: Processing ended: Thu Jan 11 09:29:26 2024
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Thu Dec 28 23:09:52 2023
|
||||
Thu Jan 11 09:29:29 2024
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Fitter report for RAM2E
|
||||
Thu Dec 28 23:09:45 2023
|
||||
Thu Jan 11 09:29:24 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Fitter Status ; Successful - Thu Dec 28 23:09:45 2023 ;
|
||||
; Fitter Status ; Successful - Thu Jan 11 09:29:24 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
|
|
@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula.
|
|||
; Number detected on machine ; 4 ;
|
||||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.03 ;
|
||||
; Average used ; 1.04 ;
|
||||
; Maximum used ; 4 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 1.0% ;
|
||||
; Processors 3-4 ; 0.9% ;
|
||||
; Processor 2 ; 1.6% ;
|
||||
; Processors 3-4 ; 1.2% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
|
|
@ -720,7 +720,7 @@ Info (176234): Starting register packing
|
|||
Info (186468): Started processing fast register assignments
|
||||
Info (186469): Finished processing fast register assignments
|
||||
Info (176235): Finished register packing
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
|
||||
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
|
|
@ -732,13 +732,13 @@ Info (170195): Router estimated average interconnect usage is 23% of the availab
|
|||
Info (170196): Router estimated peak interconnect usage is 23% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.67 seconds.
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.40 seconds.
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 13748 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:45 2023
|
||||
Info: Elapsed time: 00:00:04
|
||||
Info: Peak virtual memory: 13751 megabytes
|
||||
Info: Processing ended: Thu Jan 11 09:29:24 2024
|
||||
Info: Elapsed time: 00:00:03
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Fitter Status : Successful - Thu Dec 28 23:09:45 2023
|
||||
Fitter Status : Successful - Thu Jan 11 09:29:24 2024
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Flow report for RAM2E
|
||||
Thu Dec 28 23:09:52 2023
|
||||
Thu Jan 11 09:29:29 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Dec 28 23:09:48 2023 ;
|
||||
; Flow Status ; Successful - Thu Jan 11 09:29:26 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
|
|
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 12/28/2023 23:09:13 ;
|
||||
; Start date & time ; 01/11/2024 09:28:56 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; RAM2E ;
|
||||
+-------------------+---------------------+
|
||||
|
|
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.170382295304664 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.170498333604684 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
|
||||
|
|
@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:28 ; 1.0 ; 13113 MB ; 00:00:41 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 13748 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13069 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:03 ; 1.0 ; 13067 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:36 ; -- ; -- ; 00:00:48 ;
|
||||
; Analysis & Synthesis ; 00:00:23 ; 1.0 ; 13116 MB ; 00:00:40 ;
|
||||
; Fitter ; 00:00:03 ; 1.0 ; 13751 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13072 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13069 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:29 ; -- ; -- ; 00:00:46 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Analysis & Synthesis report for RAM2E
|
||||
Thu Dec 28 23:09:40 2023
|
||||
Thu Jan 11 09:29:19 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Dec 28 23:09:40 2023 ;
|
||||
; Analysis & Synthesis Status ; Successful - Thu Jan 11 09:29:19 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
|
|
@ -281,7 +281,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:12 2023
|
||||
Info: Processing started: Thu Jan 11 09:28:56 2024
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
|
||||
|
|
@ -315,10 +315,10 @@ Info (21057): Implemented 315 device resources after synthesis - the final resou
|
|||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
|
||||
Info: Peak virtual memory: 13113 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:40 2023
|
||||
Info: Elapsed time: 00:00:28
|
||||
Info: Total CPU time (on all processors): 00:00:41
|
||||
Info: Peak virtual memory: 13116 megabytes
|
||||
Info: Processing ended: Thu Jan 11 09:29:19 2024
|
||||
Info: Elapsed time: 00:00:23
|
||||
Info: Total CPU time (on all processors): 00:00:40
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Analysis & Synthesis Status : Successful - Thu Dec 28 23:09:40 2023
|
||||
Analysis & Synthesis Status : Successful - Thu Jan 11 09:29:19 2024
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Timing Analyzer report for RAM2E
|
||||
Thu Dec 28 23:09:52 2023
|
||||
Thu Jan 11 09:29:29 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
|
|||
+------------------+--------+--------------------------+
|
||||
; SDC File Path ; Status ; Read at ;
|
||||
+------------------+--------+--------------------------+
|
||||
; ../RAM2E.sdc ; OK ; Thu Dec 28 23:09:51 2023 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Thu Dec 28 23:09:51 2023 ;
|
||||
; ../RAM2E.sdc ; OK ; Thu Jan 11 09:29:28 2024 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Thu Jan 11 09:29:28 2024 ;
|
||||
+------------------+--------+--------------------------+
|
||||
|
||||
|
||||
|
|
@ -679,7 +679,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:49 2023
|
||||
Info: Processing started: Thu Jan 11 09:29:27 2024
|
||||
Info: Command: quartus_sta RAM2E-MAXV -c RAM2E
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
|
|
@ -720,9 +720,9 @@ Warning (332009): The launch and latch times for the relationship between source
|
|||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
|
||||
Info: Peak virtual memory: 13067 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:52 2023
|
||||
Info: Elapsed time: 00:00:03
|
||||
Info: Peak virtual memory: 13069 megabytes
|
||||
Info: Processing ended: Thu Jan 11 09:29:29 2024
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,636 @@
|
|||
module RAM2E(C14M, PHI1,
|
||||
nWE, nWE80, nEN80, nC07X,
|
||||
Ain, Din, Dout, nDOE, Vout, nVOE,
|
||||
CKE, nCS, nRAS, nCAS, nRWE,
|
||||
BA, RA, RD, DQML, DQMH);
|
||||
|
||||
/* Clocks */
|
||||
input C14M, PHI1;
|
||||
|
||||
/* Control inputs */
|
||||
input nWE, nWE80, nEN80, nC07X;
|
||||
|
||||
/* Delay for EN80 signal */
|
||||
//output DelayOut = 1'b0;
|
||||
//input DelayIn;
|
||||
wire EN80 = ~nEN80;
|
||||
|
||||
/* Address Bus */
|
||||
input [7:0] Ain; // Multiplexed DRAM address input
|
||||
|
||||
/* 6502 Data Bus */
|
||||
input [7:0] Din; // 6502 data bus inputs
|
||||
reg DOEEN = 0; // 6502 data bus output enable from state machine
|
||||
output nDOE = ~(EN80 & nWE & DOEEN); // 6502 data bus output enable
|
||||
output reg [7:0] Dout; // 6502 data Bus output
|
||||
|
||||
/* Video Data Bus */
|
||||
output nVOE = ~(~PHI1); /// Video data bus output enable
|
||||
output reg [7:0] Vout; // Video data bus
|
||||
|
||||
/* SDRAM */
|
||||
output reg CKE = 0;
|
||||
output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1;
|
||||
output reg [1:0] BA;
|
||||
output reg [11:0] RA;
|
||||
output reg DQML = 1, DQMH = 1;
|
||||
wire RDOE = EN80 & ~nWE80;
|
||||
inout [7:0] RD = RDOE ? Din[7:0] : 8'bZ;
|
||||
|
||||
/* RAMWorks Bank Register and Capacity Mask */
|
||||
reg [7:0] RWBank = 0; // RAMWorks bank register
|
||||
reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask
|
||||
reg RWSel = 0; // RAMWorks bank register select
|
||||
reg RWMaskSet = 0; // RAMWorks Mask register set flag
|
||||
reg SetRWBankFF = 0; // Causes RWBank to be zeroed next RWSel access
|
||||
|
||||
/* Command Sequence Detector */
|
||||
reg [2:0] CS = 0; // Command sequence state
|
||||
reg [2:0] CmdTout = 0; // Command sequence timeout
|
||||
|
||||
/* UFM Interface */
|
||||
reg [15:8] UFMD = 0; // *Parallel* UFM data register
|
||||
reg ARCLK = 0; // UFM address register clock
|
||||
// UFM address register data input tied to 0
|
||||
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
|
||||
reg DRCLK = 0; // UFM data register clock
|
||||
reg DRDIn = 0; // UFM data register input
|
||||
reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
|
||||
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
|
||||
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
|
||||
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
|
||||
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
|
||||
wire DRDOut; // UFM data output
|
||||
// UFM oscillator always enabled
|
||||
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
|
||||
UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
|
||||
.arclk (ARCLK),
|
||||
.ardin (1'b0),
|
||||
.arshft (ARShift),
|
||||
.drclk (DRCLK),
|
||||
.drdin (DRDIn),
|
||||
.drshft (DRShift),
|
||||
.erase (UFMErase),
|
||||
.oscena (1'b1),
|
||||
.program (UFMProgram),
|
||||
.busy (UFMBusy),
|
||||
.drdout (DRDOut),
|
||||
.osc (UFMOsc),
|
||||
.rtpbusy (RTPBusy));
|
||||
reg UFMBusyReg = 0; // UFMBusy registered to sync with C14M
|
||||
reg RTPBusyReg = 0; // RTPBusy registered to sync with C14M
|
||||
|
||||
/* UFM State & User Command Triggers */
|
||||
reg UFMInitDone = 0; // 1 if UFM initialization finished
|
||||
reg UFMReqErase = 0; // 1 if UFM requires erase
|
||||
reg UFMBitbang = 0; // Set by user command. Loads UFM outputs next RWSel
|
||||
reg UFMPrgmEN = 0; // Set by user command. Programs UFM
|
||||
reg UFMEraseEN = 0; // Set by user command. Erases UFM
|
||||
reg DRCLKPulse = 0; // Set by user command. Causes DRCLK pulse next C14M
|
||||
|
||||
/* State Counters */
|
||||
reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
|
||||
reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15
|
||||
reg [15:0] FS = 0; // Fast state counter
|
||||
reg [3:0] S = 0; // IIe State counter
|
||||
|
||||
/* State Counters */
|
||||
always @(posedge C14M) begin
|
||||
// Increment fast state counter
|
||||
FS <= FS+1;
|
||||
// Synchronize Apple state counter to S1 when just entering PHI1
|
||||
PHI1reg <= PHI1; // Save old PHI1
|
||||
S <= (PHI1 & ~PHI1reg & Ready) ? 4'h1 :
|
||||
S==4'h0 ? 4'h0 :
|
||||
S==4'hF ? 4'hF : S+1;
|
||||
end
|
||||
|
||||
/* UFM Control */
|
||||
always @(posedge C14M) begin
|
||||
// Synchronize asynchronous UFM signals
|
||||
UFMBusyReg <= UFMBusy;
|
||||
RTPBusyReg <= RTPBusy;
|
||||
|
||||
if (S==4'h0) begin
|
||||
if ((FS[15:13]==3'b101) | (FS[15:13]==3'b111 & UFMReqErase)) begin
|
||||
// In states AXXX-BXXX and also EXXX-FXXX if erase/wrap req'd
|
||||
// shift in 0's to address register
|
||||
ARCLK <= FS[0]; // Clock address register
|
||||
DRCLK <= 1'b0; // Don't clock data register
|
||||
ARShift <= 1'b1; // Shift address registers
|
||||
DRDIn <= 1'b0; // Don't care DRDIn
|
||||
DRShift <= 1'b0; // Don't care DRDShift
|
||||
end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4:1]==4'h4) begin
|
||||
// In states CXXX-DXXX (substep 4)
|
||||
// Xfer to data reg (repeat 256x 1x)
|
||||
ARCLK <= 1'b0; // Don't clock address register
|
||||
DRCLK <= FS[0]; // Clock data register
|
||||
ARShift <= 1'b0; // Don't care ARShift
|
||||
DRDIn <= 1'b0; // Don't care DRDIn
|
||||
DRShift <= 1'b0; // Don't care DRShift
|
||||
end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4]==1'b1) begin
|
||||
// In states CXXX-DXXX (substeps 8-F)
|
||||
// Save UFM D15-8, shift out D14-7 (repeat 256x 8x)
|
||||
DRCLK <= FS[0]; // Clock data register
|
||||
ARShift <= 1'b0; // ARShift is 0 because we want to increment
|
||||
DRDIn <= 1'b0; // Don't care what to shift into data register
|
||||
DRShift <= 1'b1; // Shift data register
|
||||
// Shift into UFMD
|
||||
if (FS[0]) UFMD[15:8] <= {UFMD[14:8], DRDOut};
|
||||
|
||||
// Compare and store mask
|
||||
if (FS[4:1]==4'hF) begin
|
||||
ARCLK <= FS[0]; // Clock address register to increment
|
||||
// If byte is erased (0xFF, i.e. all 1's, is erased)...
|
||||
if (UFMD[14:8]==7'b1111111 & DRDOut==1'b1) begin
|
||||
// Current UFM address is where we want to store
|
||||
UFMInitDone <= 1'b1; // Quit iterating
|
||||
// Otherwise byte is valid setting (i.e. some bit is 0)...
|
||||
end else begin
|
||||
// Set RWMask, but if saved mask is 0x80, store ~0xFF
|
||||
if (UFMD[14:8]==7'b1000000 & DRDOut==1'b0) begin
|
||||
RWMask[7:0] <= {1'b1, ~7'h7F};
|
||||
end else RWMask[7:0] <= {UFMD[14], ~UFMD[13:8], ~DRDOut};
|
||||
// If last byte in sector...
|
||||
if (FS[12:5]==8'hFF) begin
|
||||
UFMReqErase <= 1'b1; // Mark need to erase
|
||||
end
|
||||
end
|
||||
end else ARCLK <= 1'b0; // Don't clock address register
|
||||
end else begin
|
||||
ARCLK <= 1'b0;
|
||||
DRCLK <= 1'b0;
|
||||
ARShift <= 1'b0;
|
||||
DRDIn <= 1'b0;
|
||||
DRShift <= 1'b0;
|
||||
end
|
||||
|
||||
// Don't erase or program UFM during initialization
|
||||
UFMErase <= 1'b0;
|
||||
UFMProgram <= 1'b0;
|
||||
// Keep DRCLK pulse control disabled during init
|
||||
DRCLKPulse <= 1'b0;
|
||||
end else begin
|
||||
// Can only shift UFM data register now
|
||||
ARCLK <= 1'b0;
|
||||
ARShift <= 1'b0;
|
||||
DRShift <= 1'b1;
|
||||
|
||||
// UFM bitbang control
|
||||
if (UFMBitbang & CS==3'h7 & RWSel & S==4'hC) begin
|
||||
DRDIn <= Din[6];
|
||||
DRCLKPulse <= Din[7];
|
||||
DRCLK <= 1'b0;
|
||||
end else begin
|
||||
DRCLKPulse <= 1'b0;
|
||||
DRCLK <= DRCLKPulse;
|
||||
end
|
||||
|
||||
// Set capacity mask
|
||||
if (RWMaskSet & RWSel & S==4'hC) RWMask[7:0] <= {Din[7], ~Din[6:0]};
|
||||
|
||||
// UFM programming sequence
|
||||
if (UFMPrgmEN | UFMEraseEN) begin
|
||||
if (~UFMBusyReg & ~RTPBusyReg) begin
|
||||
if (UFMReqErase | UFMEraseEN) UFMErase <= 1'b1;
|
||||
else if (UFMPrgmEN) UFMProgram <= 1'b1;
|
||||
end else if (UFMBusyReg) UFMReqErase <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/* SDRAM Control */
|
||||
always @(posedge C14M) begin
|
||||
if (S==4'h0) begin
|
||||
// SDRAM initialization
|
||||
if (FS[15:0]==16'hFFC0) begin
|
||||
// Precharge All
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b0;
|
||||
RA[10] <= 1'b1; // "all"
|
||||
end else if (FS[15:4]==16'hFFD & FS[0]==1'b0) begin // Repeat 8x
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end else if (FS[15:0]==16'hFFE8) begin
|
||||
// Set Mode Register
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b0;
|
||||
RA[10] <= 1'b0; // Reserved in mode register
|
||||
end else if (FS[15:4]==12'hFFF & FS[0]==1'b0) begin // Repeat 8x
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end else begin // Otherwise send no-op
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end
|
||||
// Enable SDRAM clock after 65,280 cycles (~4.56ms)
|
||||
CKE <= FS[15:8] == 8'hFF;
|
||||
|
||||
// Mode register contents
|
||||
BA[1:0] <= 2'b00; // Reserved
|
||||
RA[11] <= 1'b0; // Reserved
|
||||
// RA[10] set above ^
|
||||
RA[9] <= 1'b1; // "1" for single write mode
|
||||
RA[8] <= 1'b0; // Reserved
|
||||
RA[7] <= 1'b0; // "0" for not test mode
|
||||
RA[6:4] <= 3'b010; // "2" for CAS latency 2
|
||||
RA[3] <= 1'b0; // "0" for sequential burst (not used)
|
||||
RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
|
||||
// Begin normal operation after 128k init cycles (~9.15ms)
|
||||
if (FS == 16'hFFFF) Ready <= 1'b1;
|
||||
end else if (S==4'h1) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h2) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// Activate
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank 0, high-order row address is 0
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Row address is as previously latched
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h3) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// Read
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank 0, RA[11,9:8] don't care
|
||||
BA <= 2'b00;
|
||||
RA[11] <= 1'b0;
|
||||
RA[10] <= 1'b1; // (A10 set to auto-precharge)
|
||||
RA[9] <= 1'b0;
|
||||
RA[8] <= 1'b0;
|
||||
// Latch column address for read command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Read low byte (high byte is +4MB in ramworks)
|
||||
DQML <= 1'b0;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h4) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h5) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h6) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
if (FS[5:4]==0) begin
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
end else begin
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
end
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h7) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Latch row address for activate command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h8) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// Activate if '245 output enabled
|
||||
nCS <= nEN80;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank, RA[11:8] determine by RamWorks bank
|
||||
BA <= RWBank[5:4];
|
||||
RA[11:8] <= RWBank[3:0];
|
||||
// Row address is as previously latched
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h9) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// Read/Write if '245 output enabled
|
||||
nCS <= nEN80;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= nWE80;
|
||||
|
||||
// SDRAM bank still determined by RamWorks, RA[11,9:8] don't care
|
||||
BA <= RWBank[5:4];
|
||||
RA[11] <= 1'b0;
|
||||
RA[10] <= 1'b1; // (A10 set to auto-precharge)
|
||||
RA[9] <= 1'b0;
|
||||
RA[8] <= RWBank[7];
|
||||
// Latch column address for R/W command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Latch RAMWorks low nybble write select using old row address
|
||||
RWSel <= RA[0] & ~RA[3] & ~nWE & ~nC07X;
|
||||
|
||||
// Mask according to RAMWorks bank (high byte is +4MB)
|
||||
DQML <= RWBank[6];
|
||||
DQMH <= ~RWBank[6];
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'hA) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'hB) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end else if (S==4'hC) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
|
||||
// RAMWorks Bank Register Select
|
||||
if (RWSel) begin
|
||||
// Latch RAMWorks bank if accessed
|
||||
if (SetRWBankFF) RWBank <= 8'hFF;
|
||||
else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]};
|
||||
|
||||
// Recognize command sequence and advance CS state
|
||||
if ((CS==3'h0 & Din[7:0]==8'hFF) |
|
||||
(CS==3'h1 & Din[7:0]==8'h00) |
|
||||
(CS==3'h2 & Din[7:0]==8'h55) |
|
||||
(CS==3'h3 & Din[7:0]==8'hAA) |
|
||||
(CS==3'h4 & Din[7:0]==8'hC1) |
|
||||
(CS==3'h5 & Din[7:0]==8'hAD) |
|
||||
CS==3'h6 | CS==3'h7) CS <= CS+1;
|
||||
else CS <= 0; // Back to beginning if it's not right
|
||||
|
||||
if (CS==3'h6) begin // Recognize and submit command in CS6
|
||||
SetRWBankFF <= Din[7:0]==8'hFF;
|
||||
if (Din[7:0]==8'hEF) UFMPrgmEN <= 1'b1;
|
||||
if (Din[7:0]==8'hEE) UFMEraseEN <= 1'b1;
|
||||
UFMBitbang <= Din[7:0]==8'hEA;
|
||||
RWMaskSet <= Din[7:0]==8'hE0;
|
||||
end else begin // Reset command triggers
|
||||
SetRWBankFF <= 1'b0;
|
||||
UFMBitbang <= 1'b0;
|
||||
RWMaskSet <= 1'b0;
|
||||
end
|
||||
|
||||
CmdTout <= 0; // Reset command timeout if RWSel accessed
|
||||
end else begin
|
||||
CmdTout <= CmdTout+1; // Increment command timeout
|
||||
// If command sequence times out, reset sequence state
|
||||
if (CmdTout==3'h7) CS <= 0;
|
||||
end
|
||||
end else if (S==4'hD) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end else if (S==4'hE) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Latch row address for next video read
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end else if (S==4'hF) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Latch row address for next video read
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end
|
||||
end
|
||||
always @(negedge C14M) begin
|
||||
// Latch video and read data outputs
|
||||
if (S==4'h6) Vout[7:0] <= RD[7:0];
|
||||
if (S==4'hC) Dout[7:0] <= RD[7:0];
|
||||
end
|
||||
endmodule
|
||||
Loading…
Reference in New Issue