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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2

Hostname: ZANEMACWIN11

Implementation : impl1

# Written on Fri Jun  7 20:49:58 2024

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start          Requested     Requested     Clock        Clock                   Clock
Level     Clock          Frequency     Period        Type         Group                   Load 
-----------------------------------------------------------------------------------------------
0 -       C14M           14.3 MHz      69.841        declared     default_clkgroup        121  
                                                                                               
0 -       System         100.0 MHz     10.000        system       system_clkgroup         0    
                                                                                               
0 -       RAM2E|PHI1     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     9    
===============================================================================================


Clock Load Summary
******************

               Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin     
Clock          Load      Pin            Seq Example     Seq Example       Comb Example      
--------------------------------------------------------------------------------------------
C14M           121       C14M(port)     RAT.C           -                 un1_C14M.I[0](inv)
                                                                                            
System         0         -              -               -                 -                 
                                                                                            
RAM2E|PHI1     9         PHI1(port)     RefReq.C        S[0].D[0]         un1_PHI1.I[0](inv)
============================================================================================