Place & Route TRACE Report

Loading design for application trce from file ram2e_lcmxo2_1200hc_impl1.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:23:45 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
Design file:     ram2e_lcmxo2_1200hc_impl1.ncd
Preference file: ram2e_lcmxo2_1200hc_impl1.prf
Device,speed:    LCMXO2-1200HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
  • 1611 items scored, 0 timing errors detected. Report: 84.310MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; 1611 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 58.069ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[2] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 11.695ns (29.3% logic, 70.7% route), 7 logic levels. Constraint Details: 11.695ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.069ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q0 SLICE_34 (from C14M_c) ROUTE 50 1.472 R5C13B.Q0 to R5C11D.A0 S[2] CTOF_DEL --- 0.495 R5C11D.A0 to R5C11D.F0 SLICE_35 ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 ROUTE 5 1.755 R3C6C.F1 to R2C7D.A0 ram2e_ufm/N_781 CTOF_DEL --- 0.495 R2C7D.A0 to R2C7D.F0 ram2e_ufm/SLICE_99 ROUTE 1 1.023 R2C7D.F0 to R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0] CTOF_DEL --- 0.495 R3C7A.B0 to R3C7A.F0 ram2e_ufm/SLICE_86 ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 11.695 (29.3% logic, 70.7% route), 7 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.138ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[2] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 11.626ns (29.4% logic, 70.6% route), 7 logic levels. Constraint Details: 11.626ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.138ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q0 SLICE_34 (from C14M_c) ROUTE 50 1.472 R5C13B.Q0 to R5C11D.A0 S[2] CTOF_DEL --- 0.495 R5C11D.A0 to R5C11D.F0 SLICE_35 ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 ROUTE 5 1.962 R3C6C.F1 to R3C7C.C0 ram2e_ufm/N_781 CTOF_DEL --- 0.495 R3C7C.C0 to R3C7C.F0 ram2e_ufm/SLICE_126 ROUTE 1 0.747 R3C7C.F0 to R3C7A.C0 ram2e_ufm/N_753 CTOF_DEL --- 0.495 R3C7A.C0 to R3C7A.F0 ram2e_ufm/SLICE_86 ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 11.626 (29.4% logic, 70.6% route), 7 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.247ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[2] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_dati[7] (to C14M_c +) Delay: 11.517ns (25.4% logic, 74.6% route), 6 logic levels. Constraint Details: 11.517ns physical path delay SLICE_34 to ram2e_ufm/SLICE_55 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.247ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_55: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q0 SLICE_34 (from C14M_c) ROUTE 50 1.472 R5C13B.Q0 to R5C11D.A0 S[2] CTOF_DEL --- 0.495 R5C11D.A0 to R5C11D.F0 SLICE_35 ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.631 R5C10B.F1 to R3C6A.A1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C6A.A1 to R3C6A.F1 ram2e_ufm/SLICE_81 ROUTE 4 1.963 R3C6A.F1 to R3C10A.C0 ram2e_ufm/N_856 CTOF_DEL --- 0.495 R3C10A.C0 to R3C10A.F0 ram2e_ufm/SLICE_131 ROUTE 1 1.535 R3C10A.F0 to R3C6B.B1 ram2e_ufm/N_602 CTOF_DEL --- 0.495 R3C6B.B1 to R3C6B.F1 ram2e_ufm/SLICE_55 ROUTE 1 0.000 R3C6B.F1 to R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c) -------- 11.517 (25.4% logic, 74.6% route), 6 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_55: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R3C6B.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.444ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[3] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 11.320ns (30.2% logic, 69.8% route), 7 logic levels. Constraint Details: 11.320ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.444ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q1 SLICE_34 (from C14M_c) ROUTE 45 1.097 R5C13B.Q1 to R5C11D.B0 S[3] CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_35 ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 ROUTE 5 1.755 R3C6C.F1 to R2C7D.A0 ram2e_ufm/N_781 CTOF_DEL --- 0.495 R2C7D.A0 to R2C7D.F0 ram2e_ufm/SLICE_99 ROUTE 1 1.023 R2C7D.F0 to R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0] CTOF_DEL --- 0.495 R3C7A.B0 to R3C7A.F0 ram2e_ufm/SLICE_86 ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 11.320 (30.2% logic, 69.8% route), 7 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.513ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[3] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 11.251ns (30.4% logic, 69.6% route), 7 logic levels. Constraint Details: 11.251ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.513ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q1 SLICE_34 (from C14M_c) ROUTE 45 1.097 R5C13B.Q1 to R5C11D.B0 S[3] CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_35 ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 ROUTE 5 1.962 R3C6C.F1 to R3C7C.C0 ram2e_ufm/N_781 CTOF_DEL --- 0.495 R3C7C.C0 to R3C7C.F0 ram2e_ufm/SLICE_126 ROUTE 1 0.747 R3C7C.F0 to R3C7A.C0 ram2e_ufm/N_753 CTOF_DEL --- 0.495 R3C7A.C0 to R3C7A.F0 ram2e_ufm/SLICE_86 ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 11.251 (30.4% logic, 69.6% route), 7 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.525ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[0] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 11.239ns (26.0% logic, 74.0% route), 6 logic levels. Constraint Details: 11.239ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.525ns Physical Path Details: Data path SLICE_33 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C13D.CLK to R5C13D.Q0 SLICE_33 (from C14M_c) ROUTE 37 2.500 R5C13D.Q0 to R5C10B.C1 S[0] CTOF_DEL --- 0.495 R5C10B.C1 to R5C10B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 ROUTE 5 1.755 R3C6C.F1 to R2C7D.A0 ram2e_ufm/N_781 CTOF_DEL --- 0.495 R2C7D.A0 to R2C7D.F0 ram2e_ufm/SLICE_99 ROUTE 1 1.023 R2C7D.F0 to R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0] CTOF_DEL --- 0.495 R3C7A.B0 to R3C7A.F0 ram2e_ufm/SLICE_86 ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 11.239 (26.0% logic, 74.0% route), 6 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R5C13D.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.594ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[0] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 11.170ns (26.2% logic, 73.8% route), 6 logic levels. Constraint Details: 11.170ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.594ns Physical Path Details: Data path SLICE_33 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C13D.CLK to R5C13D.Q0 SLICE_33 (from C14M_c) ROUTE 37 2.500 R5C13D.Q0 to R5C10B.C1 S[0] CTOF_DEL --- 0.495 R5C10B.C1 to R5C10B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 ROUTE 5 1.962 R3C6C.F1 to R3C7C.C0 ram2e_ufm/N_781 CTOF_DEL --- 0.495 R3C7C.C0 to R3C7C.F0 ram2e_ufm/SLICE_126 ROUTE 1 0.747 R3C7C.F0 to R3C7A.C0 ram2e_ufm/N_753 CTOF_DEL --- 0.495 R3C7A.C0 to R3C7A.F0 ram2e_ufm/SLICE_86 ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 11.170 (26.2% logic, 73.8% route), 6 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R5C13D.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.622ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[3] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_dati[7] (to C14M_c +) Delay: 11.142ns (26.3% logic, 73.7% route), 6 logic levels. Constraint Details: 11.142ns physical path delay SLICE_34 to ram2e_ufm/SLICE_55 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.622ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_55: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q1 SLICE_34 (from C14M_c) ROUTE 45 1.097 R5C13B.Q1 to R5C11D.B0 S[3] CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_35 ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.631 R5C10B.F1 to R3C6A.A1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C6A.A1 to R3C6A.F1 ram2e_ufm/SLICE_81 ROUTE 4 1.963 R3C6A.F1 to R3C10A.C0 ram2e_ufm/N_856 CTOF_DEL --- 0.495 R3C10A.C0 to R3C10A.F0 ram2e_ufm/SLICE_131 ROUTE 1 1.535 R3C10A.F0 to R3C6B.B1 ram2e_ufm/N_602 CTOF_DEL --- 0.495 R3C6B.B1 to R3C6B.F1 ram2e_ufm/SLICE_55 ROUTE 1 0.000 R3C6B.F1 to R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c) -------- 11.142 (26.3% logic, 73.7% route), 6 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_55: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R3C6B.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.703ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[0] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_dati[7] (to C14M_c +) Delay: 11.061ns (22.0% logic, 78.0% route), 5 logic levels. Constraint Details: 11.061ns physical path delay SLICE_33 to ram2e_ufm/SLICE_55 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.703ns Physical Path Details: Data path SLICE_33 to ram2e_ufm/SLICE_55: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C13D.CLK to R5C13D.Q0 SLICE_33 (from C14M_c) ROUTE 37 2.500 R5C13D.Q0 to R5C10B.C1 S[0] CTOF_DEL --- 0.495 R5C10B.C1 to R5C10B.F1 ram2e_ufm/SLICE_80 ROUTE 8 2.631 R5C10B.F1 to R3C6A.A1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C6A.A1 to R3C6A.F1 ram2e_ufm/SLICE_81 ROUTE 4 1.963 R3C6A.F1 to R3C10A.C0 ram2e_ufm/N_856 CTOF_DEL --- 0.495 R3C10A.C0 to R3C10A.F0 ram2e_ufm/SLICE_131 ROUTE 1 1.535 R3C10A.F0 to R3C6B.B1 ram2e_ufm/N_602 CTOF_DEL --- 0.495 R3C6B.B1 to R3C6B.F1 ram2e_ufm/SLICE_55 ROUTE 1 0.000 R3C6B.F1 to R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c) -------- 11.061 (22.0% logic, 78.0% route), 5 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R5C13D.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_55: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R3C6B.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.866ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q S[2] (from C14M_c +) Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) Delay: 10.898ns (31.4% logic, 68.6% route), 7 logic levels. Constraint Details: 10.898ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets 69.930ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.866ns Physical Path Details: Data path SLICE_34 to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q0 SLICE_34 (from C14M_c) ROUTE 50 1.472 R5C13B.Q0 to R5C11D.A0 S[2] CTOF_DEL --- 0.495 R5C11D.A0 to R5C11D.F0 SLICE_35 ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 ROUTE 8 3.058 R5C10B.F1 to R3C5D.A1 ram2e_ufm/N_777 CTOF_DEL --- 0.495 R3C5D.A1 to R3C5D.F1 ram2e_ufm/SLICE_89 ROUTE 6 0.348 R3C5D.F1 to R3C5C.D1 ram2e_ufm/N_783 CTOF_DEL --- 0.495 R3C5C.D1 to R3C5C.F1 ram2e_ufm/SLICE_68 ROUTE 1 0.986 R3C5C.F1 to R3C7A.A0 ram2e_ufm/wb_adr_7_i_i_3[0] CTOF_DEL --- 0.495 R3C7A.A0 to R3C7A.F0 ram2e_ufm/SLICE_86 ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) -------- 10.898 (31.4% logic, 68.6% route), 7 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c -------- 4.865 (0.0% logic, 100.0% route), 0 logic levels. Report: 84.310MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 84.310 MHz| 7 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: C14M_c Source: C14M.PAD Loads: 89 Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Thu Dec 28 23:23:45 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf Design file: ram2e_lcmxo2_1200hc_impl1.ncd Preference file: ram2e_lcmxo2_1200hc_impl1.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
  • 1611 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; 1611 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.342ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ram2e_ufm/wb_dati[6] (from C14M_c +) Destination: EFB Port ram2e_ufm/ufmefb/EFBInst_0(ASIC) (to C14M_c +) Delay: 0.305ns (43.6% logic, 56.4% route), 1 logic levels. Constraint Details: 0.305ns physical path delay ram2e_ufm/SLICE_55 to ram2e_ufm/ufmefb/EFBInst_0 meets -0.091ns WBDATI_HLD and 0.000ns delay constraint less -0.054ns skew requirement (totaling -0.037ns) by 0.342ns Physical Path Details: Data path ram2e_ufm/SLICE_55 to ram2e_ufm/ufmefb/EFBInst_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R3C6B.CLK to R3C6B.Q0 ram2e_ufm/SLICE_55 (from C14M_c) ROUTE 1 0.172 R3C6B.Q0 to EFB.WBDATI6 ram2e_ufm/wb_dati[6] (to C14M_c) -------- 0.305 (43.6% logic, 56.4% route), 1 logic levels. Clock Skew Details: Source Clock Path C14M to ram2e_ufm/SLICE_55: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R3C6B.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to ram2e_ufm/ufmefb/EFBInst_0: Name Fanout Delay (ns) Site Resource ROUTE 89 1.722 62.PADDI to EFB.WBCLKI C14M_c -------- 1.722 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[15] (from C14M_c +) Destination: FF Data in FS[15] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_1 to SLICE_1 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C12A.CLK to R2C12A.Q0 SLICE_1 (from C14M_c) ROUTE 9 0.132 R2C12A.Q0 to R2C12A.A0 FS[15] CTOF_DEL --- 0.101 R2C12A.A0 to R2C12A.F0 SLICE_1 ROUTE 1 0.000 R2C12A.F0 to R2C12A.DI0 FS_s[15] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R2C12A.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R2C12A.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdTout[2] (from C14M_c +) Destination: FF Data in CmdTout[2] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_18 to SLICE_18 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_18 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C11A.CLK to R8C11A.Q1 SLICE_18 (from C14M_c) ROUTE 2 0.132 R8C11A.Q1 to R8C11A.A1 CmdTout[2] CTOF_DEL --- 0.101 R8C11A.A1 to R8C11A.F1 SLICE_18 ROUTE 1 0.000 R8C11A.F1 to R8C11A.DI1 N_369_i (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R8C11A.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R8C11A.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdTout[1] (from C14M_c +) Destination: FF Data in CmdTout[1] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_18 to SLICE_18 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_18 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C11A.CLK to R8C11A.Q0 SLICE_18 (from C14M_c) ROUTE 3 0.132 R8C11A.Q0 to R8C11A.A0 CmdTout[1] CTOF_DEL --- 0.101 R8C11A.A0 to R8C11A.F0 SLICE_18 ROUTE 1 0.000 R8C11A.F0 to R8C11A.DI0 N_368_i (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R8C11A.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R8C11A.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[13] (from C14M_c +) Destination: FF Data in FS[13] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_2 to SLICE_2 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C11D.CLK to R2C11D.Q0 SLICE_2 (from C14M_c) ROUTE 19 0.132 R2C11D.Q0 to R2C11D.A0 FS[13] CTOF_DEL --- 0.101 R2C11D.A0 to R2C11D.F0 SLICE_2 ROUTE 1 0.000 R2C11D.F0 to R2C11D.DI0 FS_s[13] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R2C11D.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R2C11D.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RA[9] (from C14M_c +) Destination: FF Data in RA[9] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_24 to SLICE_24 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_24 to SLICE_24: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C11C.CLK to R5C11C.Q1 SLICE_24 (from C14M_c) ROUTE 2 0.132 R5C11C.Q1 to R5C11C.A1 RA[9] CTOF_DEL --- 0.101 R5C11C.A1 to R5C11C.F1 SLICE_24 ROUTE 1 0.000 R5C11C.F1 to R5C11C.DI1 RA_35[9] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R5C11C.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R5C11C.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RA[8] (from C14M_c +) Destination: FF Data in RA[8] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_24 to SLICE_24 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_24 to SLICE_24: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C11C.CLK to R5C11C.Q0 SLICE_24 (from C14M_c) ROUTE 2 0.132 R5C11C.Q0 to R5C11C.A0 RA[8] CTOF_DEL --- 0.101 R5C11C.A0 to R5C11C.F0 SLICE_24 ROUTE 1 0.000 R5C11C.F0 to R5C11C.DI0 un2_S_2_i_0_0_o3_RNIHFHN3 (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R5C11C.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R5C11C.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RA[11] (from C14M_c +) Destination: FF Data in RA[11] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_25 to SLICE_25 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_25 to SLICE_25: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C12D.CLK to R5C12D.Q1 SLICE_25 (from C14M_c) ROUTE 2 0.132 R5C12D.Q1 to R5C12D.A1 RA[11] CTOF_DEL --- 0.101 R5C12D.A1 to R5C12D.F1 SLICE_25 ROUTE 1 0.000 R5C12D.F1 to R5C12D.DI1 RA_35[11] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R5C12D.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R5C12D.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RC[2] (from C14M_c +) Destination: FF Data in RC[2] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_26 to SLICE_26 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_26 to SLICE_26: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C15C.CLK to R4C15C.Q1 SLICE_26 (from C14M_c) ROUTE 5 0.132 R4C15C.Q1 to R4C15C.A1 RC[2] CTOF_DEL --- 0.101 R4C15C.A1 to R4C15C.F1 SLICE_26 ROUTE 1 0.000 R4C15C.F1 to R4C15C.DI1 RC_3[2] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R4C15C.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R4C15C.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[12] (from C14M_c +) Destination: FF Data in FS[12] (to C14M_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_3 to SLICE_3 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C11C.CLK to R2C11C.Q1 SLICE_3 (from C14M_c) ROUTE 24 0.132 R2C11C.Q1 to R2C11C.A1 FS[12] CTOF_DEL --- 0.101 R2C11C.A1 to R2C11C.F1 SLICE_3 ROUTE 1 0.000 R2C11C.F1 to R2C11C.DI1 FS_s[12] (to C14M_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path C14M to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R2C11C.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path C14M to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 89 1.668 62.PADDI to R2C11C.CLK C14M_c -------- 1.668 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: C14M_c Source: C14M.PAD Loads: 89 Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------