PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
Thu Dec 28 23:23:31 2023

C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset
//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml


Preference file: RAM2E_LCMXO2_640HC_impl1.prf.

Cost Table Summary
Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            57.938       0            0.379        0            13           Completed
* : Design saved.

Total (real) run time for 1-seed: 13 secs 

par done!

Note: user must run 'Trace' for timing closure signoff.

Lattice Place and Route Report for Design "RAM2E_LCMXO2_640HC_impl1_map.ncd"
Thu Dec 28 23:23:31 2023


Best Par Run
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file RAM2E_LCMXO2_640HC_impl1_map.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-640HC
Package:     TQFP100
Performance: 4
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.39.
Performance Hardware Data Status:   Final          Version 34.4.
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)   69+4(JTAG)/80      91% used
                  69+4(JTAG)/79      92% bonded
   IOLOGIC           29/80           36% used

   SLICE            148/320          46% used

   EFB                1/1           100% used


Number of Signals: 459
Number of Connections: 1330

Pin Constraint Summary:
   69 out of 69 pins locked (100% locked).

The following 1 signal is selected to use the primary clock routing resources:
    C14M_c (driver: C14M, clk load #: 89)

WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.

The following 1 signal is selected to use the secondary clock routing resources:
    N_187_i (driver: ram2e_ufm/SLICE_130, clk load #: 0, sr load #: 0, ce load #: 11)

No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
Finished Placer Phase 0.  REAL time: 0 secs 

Starting Placer Phase 1.
....................
Placer score = 69810.
Finished Placer Phase 1.  REAL time: 7 secs 

Starting Placer Phase 2.
.
Placer score =  69262
Finished Placer Phase 2.  REAL time: 7 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  General PIO: 1 out of 80 (1%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Global Clocks:
  PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 89
  SECONDARY "N_187_i" from F1 on comp "ram2e_ufm/SLICE_130" on site "R6C8B", clk load = 0, ce load = 11, sr load = 0

  PRIMARY  : 1 out of 8 (12%)
  SECONDARY: 1 out of 8 (12%)




I/O Usage Summary (final):
   69 + 4(JTAG) out of 80 (91.3%) PIO sites used.
   69 + 4(JTAG) out of 79 (92.4%) bonded PIO sites used.
   Number of PIO comps: 69; differential: 0.
   Number of Vref pins used: 0.

I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0        | 11 / 19 ( 57%) | 3.3V       | -         |
| 1        | 20 / 20 (100%) | 3.3V       | -         |
| 2        | 18 / 20 ( 90%) | 3.3V       | -         |
| 3        | 20 / 20 (100%) | 3.3V       | -         |
+----------+----------------+------------+-----------+

Total placer CPU time: 6 secs 

Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.

0 connections routed; 1330 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.

Completed router resource preassignment. Real time: 11 secs 

Start NBR router at 23:23:42 12/28/23

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in TRCE report. You should always run TRCE to verify  
      your design.                                               
*****************************************************************

Start NBR special constraint process at 23:23:42 12/28/23

Start NBR section for initial routing at 23:23:42 12/28/23
Level 4, iteration 1
19(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 58.137ns/0.000ns; real time: 11 secs 

Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area  at 75% usage is 0 (0.00%)

Start NBR section for normal routing at 23:23:42 12/28/23
Level 4, iteration 1
8(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 11 secs 
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 11 secs 
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 12 secs 

Start NBR section for setup/hold timing optimization with effort level 3 at 23:23:43 12/28/23

Start NBR section for re-routing at 23:23:43 12/28/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 12 secs 

Start NBR section for post-routing at 23:23:43 12/28/23

End NBR router with 0 unrouted connection

NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 0 (0.00%)
  Estimated worst slack<setup> : 57.938ns
  Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.



Total CPU time 12 secs 
Total REAL time: 12 secs 
Completely routed.
End of route.  1330 routed (100.00%); 0 unrouted.

Hold time timing score: 0, hold timing errors: 0

Timing score: 0 

Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack<setup/<ns>> = 57.938
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.379
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0

Total CPU  time to completion: 12 secs 
Total REAL time to completion: 13 secs 

par done!

Note: user must run 'Trace' for timing closure signoff.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.