// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454

// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd 
// Netlist created on Thu Sep 21 05:34:46 2023
// Netlist written on Thu Sep 21 05:35:15 2023
// Design is for device LCMXO2-640HC
// Design is for package TQFP100
// Design is for performance grade 4

`timescale 1 ns / 1 ps

module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, 
               Vout, nVOE, CKE, nCS, nRAS, nCAS, nRWE, BA, RA, RD, DQML, DQMH );
  input  C14M, PHI1, nWE, nWE80, nEN80, nC07X;
  input  [7:0] Ain;
  input  [7:0] Din;
  output LED;
  output [7:0] Dout;
  output nDOE;
  output [7:0] Vout;
  output nVOE, CKE, nCS, nRAS, nCAS, nRWE;
  output [1:0] BA;
  output [11:0] RA;
  output DQML, DQMH;
  inout  [7:0] RD;
  wire   \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , 
         \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , 
         \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , 
         \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , 
         \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , 
         \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , 
         \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , 
         PHI1_c, PHI1reg, Ready, RWSel, CO0_1, \CmdTout_3[0] , N_576_i, S_1, 
         \S_RNII9DO1_0[1] , N_461, \CS[0] , \CS[1] , N_511_i, N_504_i, 
         un1_CS_0_sqmuxa_i, N_637, \CS[2] , N_510_i, \Din_c[0] , \Din_c[2] , 
         \Din_c[3] , CmdBitbangMXO2_4_u_0_0_a2_0_1, N_643, CmdBitbangMXO2, 
         CmdBitbangMXO2_4, \Din_c[7] , \Din_c[5] , N_629, CmdExecMXO2, 
         CmdExecMXO2_4, N_466, \Din_c[1] , \Din_c[4] , N_478, 
         CmdLEDGet_4_u_0_0_a2_0_2, N_476, CmdLEDGet, CmdLEDGet_4, N_626, N_605, 
         CmdLEDSet, CmdLEDSet_4, CmdRWMaskSet, CmdRWMaskSet_4, N_401, 
         CmdSetRWBankFFLED, CmdSetRWBankFFLED_4, N_474, 
         CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0, CmdSetRWBankFFMXO2, 
         CmdSetRWBankFFMXO2_4, \CmdTout[1] , \CmdTout[2] , N_556_i, N_555_i, 
         \S[2] , \S[1] , \S[3] , \S[0] , N_6_i, DOEEN, \Ain_c[1] , 
         \wb_dato[0] , LEDEN_RNO, \un1_LEDEN_0_sqmuxa_1_i_0[0] , LEDEN, 
         N_558_i, \Ain_c[3] , \Ain_c[0] , N_552_i, N_127_i, \S_RNII9DO1_1[1] , 
         \RA_c[0] , \RA_c[3] , N_591, \RWMask[1] , \RWMask[0] , \RWBank_5[1] , 
         \RWBank_5[0] , LEDEN13, \RWBank[0] , \RWBank[1] , \RWMask[3] , 
         \RWMask[2] , \RWBank_5[3] , \RWBank_5[2] , \RWBank[2] , \RWBank[3] , 
         \RWMask[5] , \RWMask[4] , \RWBank_5[5] , \RWBank_5[4] , \RWBank[4] , 
         \RWBank[5] , \RWMask[7] , \Din_c[6] , \RWMask[6] , \RWBank_5[7] , 
         \RWBank_5[6] , \RWBank[6] , \RWBank[7] , \wb_dato[1] , N_291_i, 
         N_292_i, N_88, \wb_dato[3] , \wb_dato[2] , N_289_i, N_290_i, 
         \wb_dato[5] , \wb_dato[4] , N_287_i, N_288_i, \wb_dato[7] , 
         \wb_dato[6] , N_285, N_286_i, nEN80_c, nWE_c, nC07X_c, RWSel_2, nCS61, 
         nDOE_c, N_489, Ready_0_sqmuxa_0_a2_6_a2_4, Ready_0_sqmuxa, N_876_0, 
         N_572, N_575, wb_reqc_1, \S_s_0_1[0] , N_133_i, \S_s_0[0] , N_129_i, 
         N_131_i, N_388, wb_adr_7_5_214_0_1, \wb_adr_7_0_4[0] , N_376, N_642, 
         \wb_adr_RNO[1] , \wb_adr_7[0] , \un1_wb_adr_0_sqmuxa_2_i[0] , 
         \wb_adr[0] , \wb_adr[1] , N_41_i, N_43_i, \wb_adr[2] , \wb_adr[3] , 
         N_295, N_294, \wb_adr[4] , \wb_adr[5] , N_39_i, N_296, \wb_adr[6] , 
         \wb_adr[7] , wb_ack, N_300, N_395, wb_cyc_stb_RNO, N_104, wb_cyc_stb, 
         N_336, N_627, N_621, \wb_dati_7_0_0[1] , \wb_dati_7_0_a2_1[0] , N_484, 
         \wb_dati_7[1] , \wb_dati_7[0] , \wb_dati[0] , \wb_dati[1] , 
         \wb_dati_7_0_2[3] , \wb_dati_7_0_0[3] , \wb_dati_7_0_o2_0[2] , N_345, 
         \wb_dati_7[3] , \wb_dati_7[2] , \wb_dati[2] , \wb_dati[3] , N_346, 
         N_349, \wb_dati_7_0_0[4] , \wb_dati_7[5] , \wb_dati_7[4] , 
         \wb_dati[4] , \wb_dati[5] , \wb_dati_7_0_RNO[7] , N_424, 
         \wb_dati_7_0_0[7] , N_422, \wb_dati_7_0_1[6] , \wb_dati_7[7] , 
         \wb_dati_7[6] , \wb_dati[6] , \wb_dati[7] , N_397, wb_reqc_i, 
         wb_adr_0_sqmuxa_i, wb_req, wb_rst8, \S_RNII9DO1[1] , wb_rst, N_586, 
         N_584, N_475, wb_we_7_iv_0_0_0_1, wb_we_RNO, 
         \un1_wb_cyc_stb_0_sqmuxa_1_i[0] , wb_we, N_255, N_358_i, N_254, Vout3, 
         N_635, nCAS_s_i_tz_0, un1_CS_0_sqmuxa_0_0_a2_1_4, N_327, 
         un1_CS_0_sqmuxa_0_0_0, \wb_dati_7_0_a2_0_1[7] , N_579, 
         CKE_6_iv_i_a2_0, CKE_6_iv_i_0_1, CKE_6_iv_i_0, N_449, N_365, N_364, 
         \un1_wb_adr_0_sqmuxa_2_1[0] , N_623, N_616, N_279, N_633, N_264, 
         N_570, N_452, \wb_dati_7_0_a2_2_1[3] , N_455, N_644, DQML_s_i_a2_0, 
         N_28_i, wb_adr_7_5_214_a2_2_0, N_569, N_577, N_634, 
         \wb_dati_7_0_a2_2_0[1] , N_265_i, \un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] , 
         \wb_dati_7_0_a2_0[6] , \wb_dati_7_0_a2_4_0[7] , N_393, nCAS_0_sqmuxa, 
         N_639, \RA_42[10] , N_640, un1_nCS61_1_i, Ready_0_sqmuxa_0_a2_6_a2_2, 
         N_562, N_377, N_628, un1_CS_0_sqmuxa_0_0_3, un1_CS_0_sqmuxa_0_0_2, 
         un1_CS_0_sqmuxa_0_0_a2_3_2, N_567, N_561_i, nCS_6_u_i_0, N_559_1, 
         N_559_i, nRAS_2_iv_i, un1_CS_0_sqmuxa_0_0_a2_1, N_328, N_330, 
         nCS_6_u_i_a2_1, N_429, N_351, \wb_adr_7_0_a2_5_0[0] , N_378, 
         \wb_adr_7_0_1[0] , \wb_adr_7_0_0[0] , 
         \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] , un1_CS_0_sqmuxa_0_0_a2_4_2, 
         un1_CS_0_sqmuxa_0_0_a2_4_4, N_565, un1_CS_0_sqmuxa_0_0_a2_2_2, 
         un1_CS_0_sqmuxa_0_0_a2_2_4, \wb_adr_7_0_a2_0[0] , 
         un1_CS_0_sqmuxa_0_0_a2_1_2, un1_CS_0_sqmuxa_0_0_a2_3_0, N_394, N_49_i, 
         N_456, N_477, N_566_i, \BA_4[0] , \RA_42[11] , \BA_4[1] , N_59_i, 
         \Ain_c[5] , \Ain_c[4] , N_551_i, \RA_42_3_0[5] , \Ain_c[6] , N_550_i, 
         \Ain_c[2] , \Ain_c[7] , N_549_i, N_553_i, nWE80_c, nRWE_r_0, RDOE_i, 
         LED_c, \RD_in[0] , DQMH_c, DQML_c, \RD_in[7] , \RD_in[6] , \RD_in[5] , 
         \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , \RA_c[11] , 
         \RA_c[10] , \RA_c[9] , \RA_c[8] , \RA_c[7] , \RA_c[6] , \RA_c[5] , 
         \RA_c[4] , \RA_c[2] , \RA_c[1] , \BA_c[1] , \BA_c[0] , nRWE_c, nCAS_c, 
         nRAS_c, nCS_c, CKE_c, \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , 
         \Vout_c[4] , \Vout_c[3] , \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , 
         \Dout_c[7] , \Dout_c[6] , \Dout_c[5] , \Dout_c[4] , \Dout_c[3] , 
         \Dout_c[2] , \Dout_c[1] , \Dout_c[0] , VCCI;

  SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), 
    .Q1(\FS[0] ), .FCO(\FS_cry[0] ));
  SLICE_1 SLICE_1( .A0(\FS[15] ), .DI0(\FS_s[15] ), .CLK(C14M_c), 
    .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), .Q0(\FS[15] ));
  SLICE_2 SLICE_2( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), 
    .DI0(\FS_s[13] ), .CLK(C14M_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), 
    .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] ));
  SLICE_3 SLICE_3( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), 
    .DI0(\FS_s[11] ), .CLK(C14M_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), 
    .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] ));
  SLICE_4 SLICE_4( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), 
    .DI0(\FS_s[9] ), .CLK(C14M_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), 
    .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] ));
  SLICE_5 SLICE_5( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), 
    .DI0(\FS_s[7] ), .CLK(C14M_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), 
    .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] ));
  SLICE_6 SLICE_6( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), 
    .DI0(\FS_s[5] ), .CLK(C14M_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), 
    .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] ));
  SLICE_7 SLICE_7( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), 
    .DI0(\FS_s[3] ), .CLK(C14M_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), 
    .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] ));
  SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), 
    .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), 
    .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
  SLICE_9 SLICE_9( .C1(PHI1_c), .B1(PHI1reg), .A1(Ready), .D0(RWSel), 
    .A0(CO0_1), .DI0(\CmdTout_3[0] ), .CE(N_576_i), .CLK(C14M_c), 
    .F0(\CmdTout_3[0] ), .Q0(CO0_1), .F1(S_1));
  SLICE_10 SLICE_10( .D1(\S_RNII9DO1_0[1] ), .C1(N_461), .B1(\CS[0] ), 
    .A1(\CS[1] ), .D0(\S_RNII9DO1_0[1] ), .C0(N_461), .A0(\CS[0] ), 
    .DI1(N_511_i), .DI0(N_504_i), .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), 
    .F0(N_504_i), .Q0(\CS[0] ), .F1(N_511_i), .Q1(\CS[1] ));
  SLICE_11 SLICE_11( .D1(\CS[0] ), .C1(N_461), .B1(\S_RNII9DO1_0[1] ), 
    .C0(N_637), .B0(\CS[1] ), .A0(\CS[2] ), .DI0(N_510_i), 
    .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_510_i), .Q0(\CS[2] ), 
    .F1(N_637));
  SLICE_12 SLICE_12( .D1(\Din_c[0] ), .B1(\Din_c[2] ), .A1(\Din_c[3] ), 
    .D0(RWSel), .C0(CmdBitbangMXO2_4_u_0_0_a2_0_1), .B0(N_643), 
    .A0(CmdBitbangMXO2), .DI0(CmdBitbangMXO2_4), .CE(N_576_i), .CLK(C14M_c), 
    .F0(CmdBitbangMXO2_4), .Q0(CmdBitbangMXO2), 
    .F1(CmdBitbangMXO2_4_u_0_0_a2_0_1));
  SLICE_13 SLICE_13( .D1(RWSel), .C1(\Din_c[7] ), .A1(\Din_c[5] ), .D0(N_643), 
    .C0(RWSel), .B0(N_629), .A0(CmdExecMXO2), .DI0(CmdExecMXO2_4), 
    .CE(N_576_i), .CLK(C14M_c), .F0(CmdExecMXO2_4), .Q0(CmdExecMXO2), 
    .F1(N_466));
  SLICE_14 SLICE_14( .D1(\Din_c[0] ), .C1(\Din_c[1] ), .B1(\Din_c[4] ), 
    .A1(N_478), .D0(CmdLEDGet_4_u_0_0_a2_0_2), .C0(N_476), .B0(CmdLEDGet), 
    .A0(RWSel), .DI0(CmdLEDGet_4), .CE(N_576_i), .CLK(C14M_c), 
    .F0(CmdLEDGet_4), .Q0(CmdLEDGet), .F1(CmdLEDGet_4_u_0_0_a2_0_2));
  SLICE_15 SLICE_15( .D1(\Din_c[4] ), .C1(N_626), .B1(N_476), .A1(\Din_c[1] ), 
    .D0(RWSel), .C0(N_605), .A0(CmdLEDSet), .DI0(CmdLEDSet_4), .CE(N_576_i), 
    .CLK(C14M_c), .F0(CmdLEDSet_4), .Q0(CmdLEDSet), .F1(N_605));
  SLICE_16 SLICE_16( .D1(\Din_c[4] ), .B1(\Din_c[1] ), .A1(N_476), .D0(RWSel), 
    .C0(N_643), .B0(N_626), .A0(CmdRWMaskSet), .DI0(CmdRWMaskSet_4), 
    .CE(N_576_i), .CLK(C14M_c), .F0(CmdRWMaskSet_4), .Q0(CmdRWMaskSet), 
    .F1(N_643));
  SLICE_17 SLICE_17( .D1(\Din_c[4] ), .C1(N_476), .B1(\Din_c[1] ), .A1(N_626), 
    .D0(RWSel), .C0(N_401), .A0(CmdSetRWBankFFLED), .DI0(CmdSetRWBankFFLED_4), 
    .CE(N_576_i), .CLK(C14M_c), .F0(CmdSetRWBankFFLED_4), 
    .Q0(CmdSetRWBankFFLED), .F1(N_401));
  SLICE_18 SLICE_18( .D1(N_474), .C1(\CS[1] ), .A1(\CS[2] ), .D0(RWSel), 
    .C0(N_476), .B0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), 
    .A0(CmdSetRWBankFFMXO2), .DI0(CmdSetRWBankFFMXO2_4), .CE(N_576_i), 
    .CLK(C14M_c), .F0(CmdSetRWBankFFMXO2_4), .Q0(CmdSetRWBankFFMXO2), 
    .F1(N_476));
  SLICE_19 SLICE_19( .D1(\CmdTout[1] ), .C1(\CmdTout[2] ), .B1(CO0_1), 
    .A1(RWSel), .D0(\CmdTout[1] ), .B0(CO0_1), .A0(RWSel), .DI1(N_556_i), 
    .DI0(N_555_i), .CE(N_576_i), .CLK(C14M_c), .F0(N_555_i), .Q0(\CmdTout[1] ), 
    .F1(N_556_i), .Q1(\CmdTout[2] ));
  SLICE_20 SLICE_20( .D1(\S[2] ), .C1(\S[1] ), .B1(\S[3] ), .A1(\S[0] ), 
    .D0(\S[2] ), .C0(\S[1] ), .B0(\S[3] ), .A0(\S[0] ), .DI0(N_6_i), 
    .CLK(C14M_c), .F0(N_6_i), .Q0(DOEEN), .F1(N_576_i));
  SLICE_21 SLICE_21( .C1(\S[0] ), .B1(\Ain_c[1] ), .A1(\S[3] ), 
    .D0(\Din_c[0] ), .B0(\wb_dato[0] ), .A0(\S[3] ), .DI0(LEDEN_RNO), 
    .CE(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .CLK(C14M_c), .F0(LEDEN_RNO), 
    .Q0(LEDEN), .F1(N_558_i));
  SLICE_22 SLICE_22( .D1(\S[0] ), .C1(\Ain_c[3] ), .A1(\S[3] ), .D0(\S[0] ), 
    .C0(\Ain_c[0] ), .A0(\S[3] ), .DI1(N_552_i), .DI0(N_127_i), 
    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c), .F0(N_127_i), .Q0(\RA_c[0] ), 
    .F1(N_552_i), .Q1(\RA_c[3] ));
  SLICE_23 SLICE_23( .D1(N_591), .C1(\RWMask[1] ), .A1(\Din_c[1] ), .D0(N_591), 
    .C0(\RWMask[0] ), .A0(\Din_c[0] ), .DI1(\RWBank_5[1] ), 
    .DI0(\RWBank_5[0] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[0] ), 
    .Q0(\RWBank[0] ), .F1(\RWBank_5[1] ), .Q1(\RWBank[1] ));
  SLICE_24 SLICE_24( .C1(\RWMask[3] ), .B1(\Din_c[3] ), .A1(N_591), 
    .D0(\Din_c[2] ), .B0(\RWMask[2] ), .A0(N_591), .DI1(\RWBank_5[3] ), 
    .DI0(\RWBank_5[2] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[2] ), 
    .Q0(\RWBank[2] ), .F1(\RWBank_5[3] ), .Q1(\RWBank[3] ));
  SLICE_25 SLICE_25( .C1(\RWMask[5] ), .B1(\Din_c[5] ), .A1(N_591), 
    .D0(\RWMask[4] ), .C0(\Din_c[4] ), .A0(N_591), .DI1(\RWBank_5[5] ), 
    .DI0(\RWBank_5[4] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[4] ), 
    .Q0(\RWBank[4] ), .F1(\RWBank_5[5] ), .Q1(\RWBank[5] ));
  SLICE_26 SLICE_26( .D1(\Din_c[7] ), .C1(\RWMask[7] ), .A1(N_591), 
    .C0(\Din_c[6] ), .B0(\RWMask[6] ), .A0(N_591), .DI1(\RWBank_5[7] ), 
    .DI0(\RWBank_5[6] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[6] ), 
    .Q0(\RWBank[6] ), .F1(\RWBank_5[7] ), .Q1(\RWBank[7] ));
  SLICE_27 SLICE_27( .D1(\Din_c[1] ), .C1(\wb_dato[1] ), .A1(\S[3] ), 
    .C0(\wb_dato[0] ), .B0(\Din_c[0] ), .A0(\S[3] ), .DI1(N_291_i), 
    .DI0(N_292_i), .CE(N_88), .CLK(C14M_c), .F0(N_292_i), .Q0(\RWMask[0] ), 
    .F1(N_291_i), .Q1(\RWMask[1] ));
  SLICE_28 SLICE_28( .D1(\wb_dato[3] ), .B1(\Din_c[3] ), .A1(\S[3] ), 
    .C0(\wb_dato[2] ), .B0(\Din_c[2] ), .A0(\S[3] ), .DI1(N_289_i), 
    .DI0(N_290_i), .CE(N_88), .CLK(C14M_c), .F0(N_290_i), .Q0(\RWMask[2] ), 
    .F1(N_289_i), .Q1(\RWMask[3] ));
  SLICE_29 SLICE_29( .D1(\wb_dato[5] ), .C1(\Din_c[5] ), .A1(\S[3] ), 
    .C0(\wb_dato[4] ), .B0(\Din_c[4] ), .A0(\S[3] ), .DI1(N_287_i), 
    .DI0(N_288_i), .CE(N_88), .CLK(C14M_c), .F0(N_288_i), .Q0(\RWMask[4] ), 
    .F1(N_287_i), .Q1(\RWMask[5] ));
  SLICE_30 SLICE_30( .D1(\wb_dato[7] ), .C1(\Din_c[7] ), .A1(\S[3] ), 
    .C0(\wb_dato[6] ), .B0(\Din_c[6] ), .A0(\S[3] ), .DI1(N_285), 
    .DI0(N_286_i), .CE(N_88), .CLK(C14M_c), .F0(N_286_i), .Q0(\RWMask[6] ), 
    .F1(N_285), .Q1(\RWMask[7] ));
  SLICE_31 SLICE_31( .C1(nEN80_c), .B1(nWE_c), .A1(DOEEN), .D0(nC07X_c), 
    .C0(\RA_c[0] ), .B0(nWE_c), .A0(\RA_c[3] ), .DI0(RWSel_2), .CE(nCS61), 
    .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(nDOE_c));
  SLICE_32 SLICE_32( .D1(\FS[6] ), .C1(\FS[7] ), .B1(N_489), 
    .A1(Ready_0_sqmuxa_0_a2_6_a2_4), .C0(Ready_0_sqmuxa), .A0(Ready), 
    .DI0(N_876_0), .CLK(C14M_c), .F0(N_876_0), .Q0(Ready), .F1(Ready_0_sqmuxa));
  SLICE_33 SLICE_33( .D1(N_572), .C1(N_575), .B1(S_1), .A1(wb_reqc_1), 
    .D0(\S_s_0_1[0] ), .C0(\S[1] ), .B0(S_1), .A0(\S[0] ), .DI1(N_133_i), 
    .DI0(\S_s_0[0] ), .CLK(C14M_c), .F0(\S_s_0[0] ), .Q0(\S[0] ), .F1(N_133_i), 
    .Q1(\S[1] ));
  SLICE_34 SLICE_34( .D1(N_575), .C1(\S[2] ), .B1(S_1), .A1(\S[3] ), 
    .D0(N_575), .C0(\S[3] ), .B0(S_1), .A0(\S[2] ), .DI1(N_129_i), 
    .DI0(N_131_i), .CLK(C14M_c), .F0(N_131_i), .Q0(\S[2] ), .F1(N_129_i), 
    .Q1(\S[3] ));
  SLICE_35 SLICE_35( .D1(N_388), .C1(\Din_c[1] ), .B1(\S[2] ), 
    .A1(wb_adr_7_5_214_0_1), .D0(\wb_adr_7_0_4[0] ), .C0(N_376), .B0(N_642), 
    .A0(\FS[13] ), .DI1(\wb_adr_RNO[1] ), .DI0(\wb_adr_7[0] ), 
    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_adr_7[0] ), 
    .Q0(\wb_adr[0] ), .F1(\wb_adr_RNO[1] ), .Q1(\wb_adr[1] ));
  SLICE_36 SLICE_36( .C1(\Din_c[3] ), .B1(\S[2] ), .C0(\Din_c[2] ), 
    .B0(\S[2] ), .DI1(N_41_i), .DI0(N_43_i), .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), 
    .CLK(C14M_c), .F0(N_43_i), .Q0(\wb_adr[2] ), .F1(N_41_i), .Q1(\wb_adr[3] ));
  SLICE_37 SLICE_37( .C1(\S[2] ), .B1(\FS[14] ), .A1(\Din_c[5] ), 
    .D0(\Din_c[4] ), .C0(\S[2] ), .B0(\FS[14] ), .DI1(N_295), .DI0(N_294), 
    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_294), 
    .Q0(\wb_adr[4] ), .F1(N_295), .Q1(\wb_adr[5] ));
  SLICE_38 SLICE_38( .C1(\Din_c[7] ), .B1(\S[2] ), .D0(\Din_c[6] ), 
    .C0(\FS[14] ), .B0(\S[2] ), .DI1(N_39_i), .DI0(N_296), 
    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_296), 
    .Q0(\wb_adr[6] ), .F1(N_39_i), .Q1(\wb_adr[7] ));
  SLICE_39 SLICE_39( .D1(\FS[0] ), .C1(\FS[14] ), .B1(wb_ack), .A1(N_300), 
    .C0(N_395), .B0(\S[3] ), .A0(CmdExecMXO2), .DI0(wb_cyc_stb_RNO), 
    .CE(N_104), .CLK(C14M_c), .F0(wb_cyc_stb_RNO), .Q0(wb_cyc_stb), .F1(N_395));
  SLICE_40 SLICE_40( .D1(N_336), .C1(N_627), .B1(N_621), 
    .A1(\wb_dati_7_0_0[1] ), .D0(\wb_dati_7_0_a2_1[0] ), .C0(\S[2] ), 
    .B0(\wb_adr[0] ), .A0(N_484), .DI1(\wb_dati_7[1] ), .DI0(\wb_dati_7[0] ), 
    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[0] ), 
    .Q0(\wb_dati[0] ), .F1(\wb_dati_7[1] ), .Q1(\wb_dati[1] ));
  SLICE_41 SLICE_41( .D1(\wb_dati_7_0_2[3] ), .B1(\wb_dati_7_0_0[3] ), 
    .A1(N_336), .D0(\wb_dati_7_0_o2_0[2] ), .C0(N_345), .B0(\S[2] ), 
    .A0(\wb_adr[2] ), .DI1(\wb_dati_7[3] ), .DI0(\wb_dati_7[2] ), 
    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[2] ), 
    .Q0(\wb_dati[2] ), .F1(\wb_dati_7[3] ), .Q1(\wb_dati[3] ));
  SLICE_42 SLICE_42( .D1(\wb_dati_7_0_o2_0[2] ), .C1(N_345), .B1(\S[2] ), 
    .A1(\wb_adr[5] ), .D0(N_346), .C0(N_349), .B0(N_345), 
    .A0(\wb_dati_7_0_0[4] ), .DI1(\wb_dati_7[5] ), .DI0(\wb_dati_7[4] ), 
    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[4] ), 
    .Q0(\wb_dati[4] ), .F1(\wb_dati_7[5] ), .Q1(\wb_dati[5] ));
  SLICE_43 SLICE_43( .D1(\wb_dati_7_0_RNO[7] ), .C1(N_424), 
    .B1(\wb_dati_7_0_0[7] ), .A1(N_422), .D0(\wb_dati_7_0_1[6] ), .C0(N_621), 
    .A0(N_627), .DI1(\wb_dati_7[7] ), .DI0(\wb_dati_7[6] ), 
    .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[6] ), 
    .Q0(\wb_dati[6] ), .F1(\wb_dati_7[7] ), .Q1(\wb_dati[7] ));
  SLICE_44 SLICE_44( .D1(\FS[11] ), .C1(\FS[12] ), .A1(\FS[13] ), 
    .D0(\FS[14] ), .C0(wb_reqc_1), .B0(\S[3] ), .A0(N_397), .DI0(wb_reqc_i), 
    .CE(wb_adr_0_sqmuxa_i), .LSR(\S[2] ), .CLK(C14M_c), .F0(wb_reqc_i), 
    .Q0(wb_req), .F1(N_397));
  SLICE_45 SLICE_45( .C1(\FS[14] ), .B1(wb_ack), .C0(\FS[14] ), .B0(\FS[15] ), 
    .DI0(wb_rst8), .LSR(\S_RNII9DO1[1] ), .CLK(C14M_c), .F0(wb_rst8), 
    .Q0(wb_rst), .F1(N_586));
  SLICE_46 SLICE_46( .D1(\FS[8] ), .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[12] ), 
    .D0(\FS[13] ), .C0(N_584), .B0(N_475), .A0(wb_we_7_iv_0_0_0_1), 
    .DI0(wb_we_RNO), .CE(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), .CLK(C14M_c), 
    .F0(wb_we_RNO), .Q0(wb_we), .F1(N_584));
  SLICE_47 SLICE_47( .D1(N_255), .C1(\S_RNII9DO1[1] ), .B1(\RWBank[6] ), 
    .A1(\S[0] ), .D0(\S[3] ), .C0(\S[0] ), .B0(\S[2] ), .A0(\S[1] ), 
    .F0(\S_RNII9DO1[1] ), .F1(N_358_i));
  SLICE_48 SLICE_48( .D1(\S[2] ), .C1(\S[1] ), .B1(\S[0] ), .A1(\S[3] ), 
    .D0(N_254), .C0(Vout3), .B0(N_635), .A0(\S[0] ), .F0(nCAS_s_i_tz_0), 
    .F1(Vout3));
  SLICE_49 SLICE_49( .D1(un1_CS_0_sqmuxa_0_0_a2_1_4), .C1(\CS[0] ), 
    .B1(\Din_c[6] ), .A1(RWSel), .D0(\CS[1] ), .C0(N_327), .B0(\CS[2] ), 
    .A0(RWSel), .F0(un1_CS_0_sqmuxa_0_0_0), .F1(N_327));
  SLICE_50 SLICE_50( .D1(\FS[8] ), .C1(\FS[10] ), .B1(\FS[9] ), .A1(\FS[11] ), 
    .D0(\wb_dati_7_0_a2_0_1[7] ), .C0(N_579), .B0(\FS[9] ), .A0(N_621), 
    .F0(\wb_dati_7_0_RNO[7] ), .F1(\wb_dati_7_0_a2_0_1[7] ));
  SLICE_51 SLICE_51( .D1(\S[2] ), .C1(\S[3] ), .B1(wb_reqc_1), 
    .A1(CKE_6_iv_i_a2_0), .D0(N_489), .C0(\S[3] ), .B0(CKE_6_iv_i_0_1), 
    .A0(\FS[15] ), .F0(CKE_6_iv_i_0), .F1(CKE_6_iv_i_0_1));
  SLICE_52 SLICE_52( .D1(N_449), .C1(\FS[0] ), .B1(N_300), .A1(wb_req), 
    .D0(N_449), .C0(N_586), .B0(N_365), .A0(N_364), .F0(N_104), .F1(N_365));
  SLICE_53 SLICE_53( .D1(RWSel), .C1(\FS[15] ), .B1(\S[2] ), .A1(\S[3] ), 
    .D0(CmdExecMXO2), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .B0(\S[2] ), 
    .A0(wb_reqc_1), .F0(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), 
    .F1(\un1_wb_adr_0_sqmuxa_2_1[0] ));
  SLICE_54 SLICE_54( .D1(\Din_c[1] ), .C1(\Din_c[0] ), .B1(\Din_c[2] ), 
    .A1(\CS[1] ), .D0(\Din_c[1] ), .C0(N_623), .B0(N_616), .A0(\CS[2] ), 
    .F0(N_279), .F1(N_623));
  SLICE_55 SLICE_55( .D1(N_633), .C1(N_264), .B1(\FS[5] ), .A1(\FS[4] ), 
    .D0(\FS[2] ), .C0(\FS[1] ), .B0(\FS[5] ), .A0(\FS[3] ), .F0(N_633), 
    .F1(N_570));
  SLICE_56 SLICE_56( .D1(\FS[14] ), .C1(\S_RNII9DO1[1] ), .A1(\FS[15] ), 
    .C0(\FS[12] ), .B0(N_452), .A0(\FS[13] ), .F0(N_621), .F1(N_452));
  SLICE_57 SLICE_57( .D1(\S_RNII9DO1_0[1] ), .C1(RWSel), .B1(wb_ack), 
    .A1(CmdExecMXO2), .D0(\S[2] ), .C0(\S[3] ), .B0(\S[0] ), .A0(\S[1] ), 
    .F0(\S_RNII9DO1_0[1] ), .F1(N_364));
  SLICE_58 SLICE_58( .D1(\FS[12] ), .C1(\wb_dati_7_0_a2_2_1[3] ), .B1(N_455), 
    .A1(N_644), .D0(\FS[10] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[11] ), 
    .F0(\wb_dati_7_0_a2_2_1[3] ), .F1(\wb_dati_7_0_2[3] ));
  SLICE_59 SLICE_59( .D1(\RWBank[6] ), .C1(nCS61), .B1(\S_RNII9DO1[1] ), 
    .A1(DQML_s_i_a2_0), .D0(\S[3] ), .C0(\S[0] ), .B0(\S[1] ), .A0(\S[2] ), 
    .F0(DQML_s_i_a2_0), .F1(N_28_i));
  SLICE_60 SLICE_60( .D1(wb_adr_7_5_214_a2_2_0), .C1(N_569), .B1(N_577), 
    .A1(N_475), .D0(\FS[10] ), .C0(\FS[12] ), .A0(\FS[13] ), 
    .F0(wb_adr_7_5_214_a2_2_0), .F1(wb_adr_7_5_214_0_1));
  SLICE_61 SLICE_61( .D1(\FS[13] ), .C1(N_634), .B1(\FS[12] ), .D0(\FS[11] ), 
    .C0(\FS[8] ), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_634), 
    .F1(\wb_dati_7_0_a2_2_0[1] ));
  SLICE_62 SLICE_62( .D1(N_265_i), .C1(\FS[12] ), .B1(N_475), .A1(\FS[11] ), 
    .D0(\FS[10] ), .B0(\FS[9] ), .A0(\FS[8] ), .F0(N_265_i), .F1(N_388));
  SLICE_63 SLICE_63( .D1(\FS[6] ), .C1(N_264), .B1(\FS[7] ), .A1(N_254), 
    .C0(\FS[1] ), .B0(\FS[3] ), .A0(\FS[2] ), .F0(N_264), .F1(N_300));
  SLICE_64 SLICE_64( .C1(\FS[8] ), .B1(\FS[9] ), .A1(\FS[11] ), .D0(N_577), 
    .C0(wb_ack), .B0(\FS[10] ), .A0(\FS[12] ), 
    .F0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .F1(N_577));
  SLICE_65 SLICE_65( .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[10] ), 
    .C0(\FS[12] ), .B0(\wb_dati_7_0_a2_0[6] ), .A0(\FS[13] ), 
    .F0(\wb_dati_7_0_a2_4_0[7] ), .F1(\wb_dati_7_0_a2_0[6] ));
  SLICE_66 SLICE_66( .B1(\FS[14] ), .A1(\S[2] ), .D0(\FS[13] ), .C0(\FS[11] ), 
    .B0(N_475), .A0(\FS[12] ), .F0(N_393), .F1(N_475));
  SLICE_67 SLICE_67( .D1(\S[1] ), .C1(\S[0] ), .D0(\S[3] ), .C0(wb_reqc_1), 
    .B0(RWSel), .A0(\S[2] ), .F0(LEDEN13), .F1(wb_reqc_1));
  SLICE_68 SLICE_68( .D1(\wb_adr[3] ), .C1(N_627), .B1(N_455), .A1(\S[2] ), 
    .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ), .A0(\FS[8] ), .F0(N_627), 
    .F1(\wb_dati_7_0_0[3] ));
  SLICE_69 SLICE_69( .D1(nCAS_0_sqmuxa), .C1(N_639), .B1(\RWBank[2] ), 
    .A1(N_255), .D0(\S[0] ), .C0(\S[3] ), .B0(\S[2] ), .A0(\S[1] ), .F0(N_639), 
    .F1(\RA_42[10] ));
  SLICE_70 SLICE_70( .D1(\FS[12] ), .C1(N_627), .B1(N_455), .A1(N_644), 
    .D0(\FS[10] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[11] ), .F0(N_644), 
    .F1(N_345));
  SLICE_71 SLICE_71( .D1(nCS61), .C1(N_633), .B1(\FS[4] ), .A1(N_640), 
    .D0(\S[1] ), .C0(\S[0] ), .B0(\S[3] ), .A0(\S[2] ), .F0(nCS61), 
    .F1(un1_nCS61_1_i));
  SLICE_72 SLICE_72( .D1(\FS[5] ), .C1(N_449), .B1(Ready_0_sqmuxa_0_a2_6_a2_2), 
    .A1(\FS[3] ), .D0(\S[3] ), .C0(wb_reqc_1), .B0(\FS[15] ), .A0(\S[2] ), 
    .F0(N_449), .F1(Ready_0_sqmuxa_0_a2_6_a2_4));
  SLICE_73 SLICE_73( .D1(N_562), .C1(N_455), .B1(\FS[12] ), .A1(\FS[11] ), 
    .D0(\FS[13] ), .C0(\FS[14] ), .B0(\S_RNII9DO1[1] ), .A0(\FS[15] ), 
    .F0(N_455), .F1(N_377));
  SLICE_74 SLICE_74( .D1(N_484), .C1(\FS[11] ), .B1(\FS[9] ), .D0(\FS[10] ), 
    .C0(\FS[12] ), .B0(N_642), .A0(\FS[13] ), .F0(N_346), .F1(N_642));
  SLICE_75 SLICE_75( .D1(\FS[7] ), .C1(\FS[0] ), .B1(N_489), .A1(\FS[6] ), 
    .C0(N_628), .B0(\S_RNII9DO1[1] ), .A0(\FS[15] ), .F0(N_640), .F1(N_628));
  SLICE_76 SLICE_76( .D1(\FS[4] ), .A1(\FS[5] ), .D0(N_254), .C0(N_449), 
    .B0(N_628), .A0(N_264), .F0(nCAS_0_sqmuxa), .F1(N_254));
  SLICE_77 SLICE_77( .D1(\CS[0] ), .C1(N_466), .A1(\Din_c[6] ), 
    .D0(un1_CS_0_sqmuxa_0_0_3), .C0(un1_CS_0_sqmuxa_0_0_2), .B0(N_474), 
    .A0(un1_CS_0_sqmuxa_0_0_a2_3_2), .F0(un1_CS_0_sqmuxa_i), .F1(N_474));
  SLICE_78 SLICE_78( .D1(\FS[4] ), .A1(N_633), .D0(N_567), .C0(N_640), 
    .B0(nCAS_s_i_tz_0), .A0(nCAS_0_sqmuxa), .F0(N_561_i), .F1(N_567));
  SLICE_79 SLICE_79( .D1(\S[3] ), .C1(nEN80_c), .B1(\S[2] ), .A1(\S[1] ), 
    .B0(nCS_6_u_i_0), .A0(N_559_1), .F0(N_559_i), .F1(nCS_6_u_i_0));
  SLICE_80 SLICE_80( .D1(\S[3] ), .B1(\S[1] ), .A1(\S[2] ), .C0(\S[0] ), 
    .B0(N_635), .A0(N_559_1), .F0(nRAS_2_iv_i), .F1(N_635));
  SLICE_81 SLICE_81( .D1(\CS[0] ), .C1(\Din_c[6] ), .B1(\Din_c[4] ), 
    .A1(\Din_c[3] ), .D0(un1_CS_0_sqmuxa_0_0_0), .C0(un1_CS_0_sqmuxa_0_0_a2_1), 
    .B0(N_279), .A0(N_466), .F0(un1_CS_0_sqmuxa_0_0_2), 
    .F1(un1_CS_0_sqmuxa_0_0_a2_1));
  SLICE_82 SLICE_82( .D1(CO0_1), .C1(RWSel), .B1(\CmdTout[1] ), 
    .A1(\CmdTout[2] ), .D0(N_461), .C0(N_328), .B0(N_330), 
    .A0(\S_RNII9DO1_0[1] ), .F0(un1_CS_0_sqmuxa_0_0_3), .F1(N_461));
  SLICE_83 SLICE_83( .D1(\FS[15] ), .C1(\S[0] ), .B1(\S[2] ), .A1(\S[3] ), 
    .D0(N_570), .C0(nCS_6_u_i_a2_1), .B0(N_429), .A0(N_628), .F0(N_559_1), 
    .F1(nCS_6_u_i_a2_1));
  SLICE_84 SLICE_84( .D1(\FS[10] ), .C1(\FS[12] ), .B1(N_455), 
    .A1(\wb_dati_7_0_a2_0[6] ), .D0(\wb_adr[6] ), .C0(N_346), .B0(\S[2] ), 
    .A0(N_351), .F0(\wb_dati_7_0_1[6] ), .F1(N_351));
  SLICE_85 SLICE_85( .D1(\wb_adr_7_0_a2_5_0[0] ), .C1(N_579), .B1(N_452), 
    .A1(\FS[8] ), .D0(N_378), .C0(N_377), .B0(\wb_adr_7_0_1[0] ), 
    .A0(\wb_adr_7_0_0[0] ), .F0(\wb_adr_7_0_4[0] ), .F1(\wb_adr_7_0_1[0] ));
  SLICE_86 SLICE_86( .D1(\FS[15] ), .C1(\S_RNII9DO1[1] ), .B1(\FS[14] ), 
    .A1(\FS[8] ), .D0(CmdLEDSet), .C0(N_484), .B0(LEDEN13), 
    .A0(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ), 
    .F0(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .F1(N_484));
  SLICE_87 SLICE_87( .D1(RWSel), .C1(un1_CS_0_sqmuxa_0_0_a2_4_2), 
    .B1(\Din_c[6] ), .A1(\CS[0] ), .C0(un1_CS_0_sqmuxa_0_0_a2_4_4), 
    .B0(\CS[2] ), .A0(\CS[1] ), .F0(N_330), .F1(un1_CS_0_sqmuxa_0_0_a2_4_4));
  SLICE_88 SLICE_88( .D1(\FS[12] ), .A1(\FS[13] ), .D0(N_336), .C0(N_452), 
    .B0(N_634), .A0(N_569), .F0(\wb_dati_7_0_o2_0[2] ), .F1(N_569));
  SLICE_89 SLICE_89( .D1(\FS[10] ), .A1(\FS[11] ), .D0(N_455), .C0(\FS[8] ), 
    .B0(\FS[9] ), .A0(N_579), .F0(N_378), .F1(N_579));
  SLICE_90 SLICE_90( .D1(\FS[10] ), .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[13] ), 
    .C0(N_565), .B0(N_484), .A0(\FS[12] ), .F0(N_336), .F1(N_565));
  SLICE_91 SLICE_91( .D1(\CS[0] ), .C1(\Din_c[6] ), .B1(\CS[2] ), 
    .A1(un1_CS_0_sqmuxa_0_0_a2_2_2), .C0(RWSel), 
    .B0(un1_CS_0_sqmuxa_0_0_a2_2_4), .A0(\Din_c[7] ), .F0(N_328), 
    .F1(un1_CS_0_sqmuxa_0_0_a2_2_4));
  SLICE_92 SLICE_92( .D1(\FS[11] ), .C1(\FS[13] ), .B1(N_562), .A1(\FS[12] ), 
    .D0(N_452), .C0(\wb_adr_7_0_a2_0[0] ), .B0(\S[2] ), .A0(\Din_c[0] ), 
    .F0(\wb_adr_7_0_0[0] ), .F1(\wb_adr_7_0_a2_0[0] ));
  SLICE_93 SLICE_93( .D1(N_616), .C1(\Din_c[5] ), .B1(\Din_c[4] ), 
    .A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[3] ), 
    .B0(un1_CS_0_sqmuxa_0_0_a2_1_2), .A0(\CS[1] ), 
    .F0(un1_CS_0_sqmuxa_0_0_a2_1_4), .F1(un1_CS_0_sqmuxa_0_0_a2_1_2));
  SLICE_94 SLICE_94( .D1(\Din_c[3] ), .C1(\Din_c[0] ), .B1(\Din_c[2] ), 
    .A1(\Din_c[1] ), .D0(\CS[1] ), .C0(un1_CS_0_sqmuxa_0_0_a2_3_0), 
    .B0(\Din_c[4] ), .A0(\CS[2] ), .F0(un1_CS_0_sqmuxa_0_0_a2_3_2), 
    .F1(un1_CS_0_sqmuxa_0_0_a2_3_0));
  SLICE_95 SLICE_95( .D1(N_475), .C1(N_577), .B1(\FS[10] ), .A1(\FS[12] ), 
    .D0(N_393), .C0(N_394), .B0(\S[2] ), .A0(\Din_c[0] ), 
    .F0(wb_we_7_iv_0_0_0_1), .F1(N_394));
  SLICE_96 SLICE_96( .D1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), .D0(\RWBank[0] ), 
    .C0(N_255), .B0(\S[0] ), .A0(\RWBank[7] ), .F0(N_49_i), .F1(N_255));
  SLICE_97 SLICE_97( .D1(\FS[10] ), .A1(\FS[12] ), .D0(\FS[14] ), .C0(N_577), 
    .B0(N_456), .A0(\FS[13] ), .F0(N_489), .F1(N_456));
  SLICE_98 SLICE_98( .D1(\Din_c[0] ), .C1(\Din_c[3] ), .B1(\Din_c[2] ), 
    .D0(N_477), .C0(\Din_c[7] ), .B0(N_626), .A0(\Din_c[5] ), 
    .F0(un1_CS_0_sqmuxa_0_0_a2_4_2), .F1(N_626));
  SLICE_99 SLICE_99( .D1(\Din_c[3] ), .B1(\Din_c[2] ), .D0(N_477), .C0(N_478), 
    .B0(\Din_c[5] ), .A0(\Din_c[0] ), .F0(un1_CS_0_sqmuxa_0_0_a2_2_2), 
    .F1(N_478));
  SLICE_100 SLICE_100( .C1(\Din_c[3] ), .B1(\Din_c[0] ), .A1(\Din_c[2] ), 
    .D0(\Din_c[1] ), .C0(\Din_c[4] ), .B0(N_629), 
    .F0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), .F1(N_629));
  SLICE_101 SLICE_101( .D1(\S[1] ), .C1(\S[0] ), .B1(\S[2] ), .A1(\S[3] ), 
    .D0(\S[1] ), .C0(\S[0] ), .B0(\S[2] ), .A0(\S[3] ), .F0(\S_RNII9DO1_1[1] ), 
    .F1(N_566_i));
  SLICE_102 SLICE_102( .D1(\S[2] ), .C1(\S[0] ), .B1(\S[1] ), .A1(\S[3] ), 
    .D0(\S[2] ), .C0(\RWBank[4] ), .B0(\S[1] ), .A0(\S[3] ), .F0(\BA_4[0] ), 
    .F1(\S_s_0_1[0] ));
  SLICE_103 SLICE_103( .D1(\S[3] ), .C1(wb_reqc_1), .B1(\RWBank[3] ), 
    .A1(\S[2] ), .D0(\S[3] ), .C0(\FS[15] ), .B0(wb_reqc_1), .A0(\S[2] ), 
    .F0(wb_adr_0_sqmuxa_i), .F1(\RA_42[11] ));
  SLICE_104 SLICE_104( .D1(\FS[11] ), .C1(N_621), .B1(\FS[9] ), .A1(\FS[8] ), 
    .D0(\FS[11] ), .C0(N_621), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_376), 
    .F1(N_349));
  SLICE_105 SLICE_105( .D1(N_569), .C1(wb_ack), .B1(\FS[9] ), .A1(N_579), 
    .D0(N_569), .C0(N_484), .B0(\FS[9] ), .A0(N_579), .F0(N_424), 
    .F1(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ));
  SLICE_106 SLICE_106( .C1(\S[1] ), .B1(\S[0] ), .C0(\S[1] ), .B0(\S[0] ), 
    .A0(nEN80_c), .F0(CKE_6_iv_i_a2_0), .F1(N_575));
  SLICE_107 SLICE_107( .D1(\S[3] ), .C1(\S[2] ), .D0(\S[3] ), .C0(\S[2] ), 
    .B0(\RWBank[5] ), .A0(\S[1] ), .F0(\BA_4[1] ), .F1(N_572));
  SLICE_108 SLICE_108( .C1(\FS[9] ), .B1(\FS[12] ), .A1(\FS[10] ), .D0(N_642), 
    .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ), .F0(N_422), 
    .F1(\wb_adr_7_0_a2_5_0[0] ));
  SLICE_109 SLICE_109( .D1(\S[2] ), .C1(\wb_adr[7] ), .B1(N_452), 
    .A1(\wb_dati_7_0_a2_4_0[7] ), .D0(\S[2] ), .C0(\wb_adr[1] ), .B0(N_452), 
    .A0(\wb_dati_7_0_a2_2_0[1] ), .F0(\wb_dati_7_0_0[1] ), 
    .F1(\wb_dati_7_0_0[7] ));
  SLICE_110 SLICE_110( .D1(\S[3] ), .C1(wb_reqc_1), .B1(\S[2] ), 
    .A1(\RWBank[1] ), .D0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .C0(wb_reqc_1), 
    .B0(\S[2] ), .A0(CmdBitbangMXO2), .F0(\un1_wb_adr_0_sqmuxa_2_i[0] ), 
    .F1(N_59_i));
  SLICE_111 SLICE_111( .D1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[5] ), .D0(\S[3] ), 
    .B0(\S[0] ), .A0(\Ain_c[4] ), .F0(N_551_i), .F1(\RA_42_3_0[5] ));
  SLICE_112 SLICE_112( .D1(\S[0] ), .C1(N_254), .B1(\S[1] ), .A1(\S[3] ), 
    .C0(\Ain_c[6] ), .B0(\S[0] ), .A0(\S[3] ), .F0(N_550_i), .F1(N_429));
  SLICE_113 SLICE_113( .C1(\S[0] ), .B1(\Ain_c[2] ), .A1(\S[3] ), .C0(\S[0] ), 
    .B0(\Ain_c[7] ), .A0(\S[3] ), .F0(N_549_i), .F1(N_553_i));
  SLICE_114 SLICE_114( .D1(\S[2] ), .C1(N_634), .B1(N_455), .A1(\wb_adr[4] ), 
    .D0(N_455), .C0(CmdRWMaskSet), .B0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), 
    .A0(LEDEN13), .F0(N_88), .F1(\wb_dati_7_0_0[4] ));
  SLICE_115 SLICE_115( .B1(nEN80_c), .A1(nWE80_c), .D0(un1_nCS61_1_i), 
    .C0(nCAS_0_sqmuxa), .B0(\S[0] ), .A0(nWE80_c), .F0(nRWE_r_0), .F1(RDOE_i));
  SLICE_116 SLICE_116( .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[11] ), .C0(N_456), 
    .B0(\FS[9] ), .A0(\FS[13] ), .F0(\wb_dati_7_0_a2_1[0] ), .F1(N_562));
  SLICE_117 SLICE_117( .D1(CmdSetRWBankFFMXO2), .C1(LEDEN), 
    .B1(CmdSetRWBankFFLED), .A1(CmdLEDGet), .C0(LEDEN), .A0(nEN80_c), 
    .F0(LED_c), .F1(N_591));
  SLICE_118 SLICE_118( .D1(\Din_c[4] ), .C1(\Din_c[1] ), .B0(\Din_c[2] ), 
    .A0(\Din_c[0] ), .F0(N_616), .F1(N_477));
  SLICE_119 SLICE_119( .D0(\FS[1] ), .C0(\FS[0] ), .B0(\FS[2] ), .A0(\FS[4] ), 
    .F0(Ready_0_sqmuxa_0_a2_6_a2_2));
  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(\Din_c[0] ), 
    .RD0(RD[0]));
  LED LED_I( .PADDO(LED_c), .LED(LED));
  C14M C14M_I( .PADDI(C14M_c), .C14M(C14M));
  DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH));
  DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_358_i), .CLK(C14M_c));
  DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML));
  DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_28_i), .CLK(C14M_c));
  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(\Din_c[7] ), 
    .RD7(RD[7]));
  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(\Din_c[6] ), 
    .RD6(RD[6]));
  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(\Din_c[5] ), 
    .RD5(RD[5]));
  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(\Din_c[4] ), 
    .RD4(RD[4]));
  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(\Din_c[3] ), 
    .RD3(RD[3]));
  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(\Din_c[2] ), 
    .RD2(RD[2]));
  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(\Din_c[1] ), 
    .RD1(RD[1]));
  RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11]));
  RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(\RA_42[11] ), 
    .CLK(C14M_c));
  RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10]));
  RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(\RA_42[10] ), 
    .CLK(C14M_c));
  RA_9_ \RA[9]_I ( .IOLDO(\RA_c[9] ), .RA9(RA[9]));
  RA_9__MGIOL \RA[9]_MGIOL ( .IOLDO(\RA_c[9] ), .OPOS(N_59_i), .CLK(C14M_c));
  RA_8_ \RA[8]_I ( .IOLDO(\RA_c[8] ), .RA8(RA[8]));
  RA_8__MGIOL \RA[8]_MGIOL ( .IOLDO(\RA_c[8] ), .OPOS(N_49_i), .CLK(C14M_c));
  RA_7_ \RA[7]_I ( .IOLDO(\RA_c[7] ), .RA7(RA[7]));
  RA_7__MGIOL \RA[7]_MGIOL ( .IOLDO(\RA_c[7] ), .OPOS(N_549_i), 
    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
  RA_6_ \RA[6]_I ( .IOLDO(\RA_c[6] ), .RA6(RA[6]));
  RA_6__MGIOL \RA[6]_MGIOL ( .IOLDO(\RA_c[6] ), .OPOS(N_550_i), 
    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
  RA_5_ \RA[5]_I ( .IOLDO(\RA_c[5] ), .RA5(RA[5]));
  RA_5__MGIOL \RA[5]_MGIOL ( .IOLDO(\RA_c[5] ), .OPOS(\RA_42_3_0[5] ), 
    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
  RA_4_ \RA[4]_I ( .IOLDO(\RA_c[4] ), .RA4(RA[4]));
  RA_4__MGIOL \RA[4]_MGIOL ( .IOLDO(\RA_c[4] ), .OPOS(N_551_i), 
    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
  RA_2_ \RA[2]_I ( .IOLDO(\RA_c[2] ), .RA2(RA[2]));
  RA_2__MGIOL \RA[2]_MGIOL ( .IOLDO(\RA_c[2] ), .OPOS(N_553_i), 
    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
  RA_1_ \RA[1]_I ( .IOLDO(\RA_c[1] ), .RA1(RA[1]));
  RA_1__MGIOL \RA[1]_MGIOL ( .IOLDO(\RA_c[1] ), .OPOS(N_558_i), 
    .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c));
  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
  BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1]));
  BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), 
    .LSR(N_566_i), .CLK(C14M_c));
  BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0]));
  BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), 
    .LSR(N_566_i), .CLK(C14M_c));
  nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE));
  nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(nRWE_r_0), .CLK(C14M_c));
  nCAS nCAS_I( .IOLDO(nCAS_c), .nCAS(nCAS));
  nCAS_MGIOL nCAS_MGIOL( .IOLDO(nCAS_c), .OPOS(N_561_i), .CLK(C14M_c));
  nRAS nRAS_I( .IOLDO(nRAS_c), .nRAS(nRAS));
  nRAS_MGIOL nRAS_MGIOL( .IOLDO(nRAS_c), .OPOS(nRAS_2_iv_i), .CLK(C14M_c));
  nCS nCS_I( .IOLDO(nCS_c), .nCS(nCS));
  nCS_MGIOL nCS_MGIOL( .IOLDO(nCS_c), .OPOS(N_559_i), .CLK(C14M_c));
  CKE CKE_I( .IOLDO(CKE_c), .CKE(CKE));
  CKE_MGIOL CKE_MGIOL( .IOLDO(CKE_c), .OPOS(CKE_6_iv_i_0), .CLK(C14M_c));
  nVOE nVOE_I( .PADDO(PHI1_c), .nVOE(nVOE));
  Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7]));
  Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), 
    .CE(Vout3), .CLK(C14M_c));
  Vout_6_ \Vout[6]_I ( .IOLDO(\Vout_c[6] ), .Vout6(Vout[6]));
  Vout_6__MGIOL \Vout[6]_MGIOL ( .IOLDO(\Vout_c[6] ), .OPOS(\RD_in[6] ), 
    .CE(Vout3), .CLK(C14M_c));
  Vout_5_ \Vout[5]_I ( .IOLDO(\Vout_c[5] ), .Vout5(Vout[5]));
  Vout_5__MGIOL \Vout[5]_MGIOL ( .IOLDO(\Vout_c[5] ), .OPOS(\RD_in[5] ), 
    .CE(Vout3), .CLK(C14M_c));
  Vout_4_ \Vout[4]_I ( .IOLDO(\Vout_c[4] ), .Vout4(Vout[4]));
  Vout_4__MGIOL \Vout[4]_MGIOL ( .IOLDO(\Vout_c[4] ), .OPOS(\RD_in[4] ), 
    .CE(Vout3), .CLK(C14M_c));
  Vout_3_ \Vout[3]_I ( .IOLDO(\Vout_c[3] ), .Vout3(Vout[3]));
  Vout_3__MGIOL \Vout[3]_MGIOL ( .IOLDO(\Vout_c[3] ), .OPOS(\RD_in[3] ), 
    .CE(Vout3), .CLK(C14M_c));
  Vout_2_ \Vout[2]_I ( .IOLDO(\Vout_c[2] ), .Vout2(Vout[2]));
  Vout_2__MGIOL \Vout[2]_MGIOL ( .IOLDO(\Vout_c[2] ), .OPOS(\RD_in[2] ), 
    .CE(Vout3), .CLK(C14M_c));
  Vout_1_ \Vout[1]_I ( .IOLDO(\Vout_c[1] ), .Vout1(Vout[1]));
  Vout_1__MGIOL \Vout[1]_MGIOL ( .IOLDO(\Vout_c[1] ), .OPOS(\RD_in[1] ), 
    .CE(Vout3), .CLK(C14M_c));
  Vout_0_ \Vout[0]_I ( .IOLDO(\Vout_c[0] ), .Vout0(Vout[0]));
  Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), 
    .CE(Vout3), .CLK(C14M_c));
  nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE));
  Dout_7_ \Dout[7]_I ( .IOLDO(\Dout_c[7] ), .Dout7(Dout[7]));
  Dout_7__MGIOL \Dout[7]_MGIOL ( .IOLDO(\Dout_c[7] ), .OPOS(\RD_in[7] ), 
    .CE(N_576_i), .CLK(C14M_c));
  Dout_6_ \Dout[6]_I ( .IOLDO(\Dout_c[6] ), .Dout6(Dout[6]));
  Dout_6__MGIOL \Dout[6]_MGIOL ( .IOLDO(\Dout_c[6] ), .OPOS(\RD_in[6] ), 
    .CE(N_576_i), .CLK(C14M_c));
  Dout_5_ \Dout[5]_I ( .IOLDO(\Dout_c[5] ), .Dout5(Dout[5]));
  Dout_5__MGIOL \Dout[5]_MGIOL ( .IOLDO(\Dout_c[5] ), .OPOS(\RD_in[5] ), 
    .CE(N_576_i), .CLK(C14M_c));
  Dout_4_ \Dout[4]_I ( .IOLDO(\Dout_c[4] ), .Dout4(Dout[4]));
  Dout_4__MGIOL \Dout[4]_MGIOL ( .IOLDO(\Dout_c[4] ), .OPOS(\RD_in[4] ), 
    .CE(N_576_i), .CLK(C14M_c));
  Dout_3_ \Dout[3]_I ( .IOLDO(\Dout_c[3] ), .Dout3(Dout[3]));
  Dout_3__MGIOL \Dout[3]_MGIOL ( .IOLDO(\Dout_c[3] ), .OPOS(\RD_in[3] ), 
    .CE(N_576_i), .CLK(C14M_c));
  Dout_2_ \Dout[2]_I ( .IOLDO(\Dout_c[2] ), .Dout2(Dout[2]));
  Dout_2__MGIOL \Dout[2]_MGIOL ( .IOLDO(\Dout_c[2] ), .OPOS(\RD_in[2] ), 
    .CE(N_576_i), .CLK(C14M_c));
  Dout_1_ \Dout[1]_I ( .IOLDO(\Dout_c[1] ), .Dout1(Dout[1]));
  Dout_1__MGIOL \Dout[1]_MGIOL ( .IOLDO(\Dout_c[1] ), .OPOS(\RD_in[1] ), 
    .CE(N_576_i), .CLK(C14M_c));
  Dout_0_ \Dout[0]_I ( .IOLDO(\Dout_c[0] ), .Dout0(Dout[0]));
  Dout_0__MGIOL \Dout[0]_MGIOL ( .IOLDO(\Dout_c[0] ), .OPOS(\RD_in[0] ), 
    .CE(N_576_i), .CLK(C14M_c));
  Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
  Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
  Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
  Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
  Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
  Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
  Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
  Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
  Ain_7_ \Ain[7]_I ( .PADDI(\Ain_c[7] ), .Ain7(Ain[7]));
  Ain_6_ \Ain[6]_I ( .PADDI(\Ain_c[6] ), .Ain6(Ain[6]));
  Ain_5_ \Ain[5]_I ( .PADDI(\Ain_c[5] ), .Ain5(Ain[5]));
  Ain_4_ \Ain[4]_I ( .PADDI(\Ain_c[4] ), .Ain4(Ain[4]));
  Ain_3_ \Ain[3]_I ( .PADDI(\Ain_c[3] ), .Ain3(Ain[3]));
  Ain_2_ \Ain[2]_I ( .PADDI(\Ain_c[2] ), .Ain2(Ain[2]));
  Ain_1_ \Ain[1]_I ( .PADDI(\Ain_c[1] ), .Ain1(Ain[1]));
  Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0]));
  nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X));
  nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80));
  nWE80 nWE80_I( .PADDI(nWE80_c), .nWE80(nWE80));
  nWE nWE_I( .PADDI(nWE_c), .nWE(nWE));
  PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1));
  PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1reg));
  ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), .WBRSTI(wb_rst), 
    .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), 
    .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), 
    .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), 
    .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), 
    .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), 
    .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), 
    .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), 
    .WBDATO2(\wb_dato[2] ), .WBDATO3(\wb_dato[3] ), .WBDATO4(\wb_dato[4] ), 
    .WBDATO5(\wb_dato[5] ), .WBDATO6(\wb_dato[6] ), .WBDATO7(\wb_dato[7] ), 
    .WBACKO(wb_ack));
  VHI VHI_INST( .Z(VCCI));
  PUR PUR_INST( .PUR(VCCI));
  GSR GSR_INST( .GSR(VCCI));
endmodule

module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly;

  vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );

  FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module vcc ( output PWR1 );

  VHI INST1( .Z(PWR1));
endmodule

module gnd ( output PWR0 );

  VLO INST1( .Z(PWR0));
endmodule

module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );

  CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
  defparam inst1.INIT0 = 16'h000A;
  defparam inst1.INIT1 = 16'h300A;
  defparam inst1.INJECT1_0 = "NO";
  defparam inst1.INJECT1_1 = "NO";
endmodule

module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 );
  wire   VCCI, GNDI, DI0_dly, CLK_dly;

  vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  ccu20001 \FS_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1());

  specify
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );

  CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
  defparam inst1.INIT0 = 16'h5002;
  defparam inst1.INIT1 = 16'h300A;
  defparam inst1.INJECT1_0 = "NO";
  defparam inst1.INJECT1_1 = "NO";
endmodule

module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );

  CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
  defparam inst1.INIT0 = 16'h300A;
  defparam inst1.INIT1 = 16'h300A;
  defparam inst1.INJECT1_0 = "NO";
  defparam inst1.INJECT1_1 = "NO";
endmodule

module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_9 ( input C1, B1, A1, D0, A0, DI0, CE, CLK, output F0, Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut4 S_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40003 \CmdTout_3_0_a2[0] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
  vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut4 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40003 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_10 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, LSR, CLK, 
    output F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly;

  lut40004 \CS_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40005 \CS_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre0006 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre0006 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge LSR, 0:0:0);
    $width (negedge LSR, 0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40004 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAAA6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40005 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAAA5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q );

  FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module SLICE_11 ( input D1, C1, B1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;

  lut40007 \CS_RNO_0[2] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40008 \CS_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre0006 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge LSR, 0:0:0);
    $width (negedge LSR, 0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40007 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40008 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h6A6A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_12 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40009 CmdBitbangMXO2_4_u_0_0_a2_0_1( .A(A1), .B(B1), .C(GNDI), .D(D1), 
    .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40010 CmdBitbangMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre CmdBitbangMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40009 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40010 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_13 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40011 un1_CS_0_sqmuxa_0_0_a2_7( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40012 CmdExecMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre CmdExecMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40011 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40012 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
    F0, Q0, F1 );
  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;

  lut40013 CmdLEDGet_4_u_0_0_a2_0_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40014 CmdLEDGet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40013 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40014 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_15 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40015 CmdLEDSet_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40016 CmdLEDSet_4_u_0_0_0( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40015 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40016 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF0FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_16 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40017 CmdBitbangMXO2_4_u_0_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(D1), 
    .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40018 CmdRWMaskSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40017 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40018 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_17 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40019 CmdSetRWBankFFLED_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), 
    .Z(F1));
  lut40016 CmdSetRWBankFFLED_4_u_0_0_0( .A(A0), .B(GNDI), .C(C0), .D(D0), 
    .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40019 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_18 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40020 CmdSetRWBankFFLED_4_u_0_0_a2_1( .A(A1), .B(GNDI), .C(C1), .D(D1), 
    .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40018 CmdSetRWBankFFMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), 
    .Z(F0));
  vmuxregsre CmdSetRWBankFFMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), 
    .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40020 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_19 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output 
    F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40021 \CmdTout_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40022 \CmdTout_RNO[1] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \CmdTout[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40021 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1450) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40022 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1144) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
    Q0, F1 );
  wire   VCCI, GNDI, DI0_dly, CLK_dly;

  lut40023 \S_RNII9DO1_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40024 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre DOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40023 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40024 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hCC80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_21 ( input C1, B1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40025 \RA_0io_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40026 LEDEN_RNO( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40025 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hC8C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40026 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEE44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_22 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40027 \RA_RNO[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40027 \RA_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40027 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_23 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40028 \RWBank_5_0[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40028 \RWBank_5_0[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40028 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFF0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_24 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40029 \RWBank_5_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40030 \RWBank_5_0[2] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
  vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40029 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40030 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hBBAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_25 ( input C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40029 \RWBank_5_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40031 \RWBank_5_0[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40031 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_26 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40032 \RWBank_5_0_0[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40033 \RWBank_5_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40032 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40033 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_27 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40034 \RWMask_RNO[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40035 \RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre \RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40034 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h50FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40035 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h7272) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_28 ( input D1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40036 \RWMask_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40035 \RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre \RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40036 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h7722) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_29 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40037 \RWMask_RNO[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40035 \RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre \RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40037 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h5F0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_30 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40038 \RWMask_RNO[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40035 \RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre \RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40038 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF5A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40039 nDOE_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40040 RWSel_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40039 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40040 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_32 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly;

  lut40041 Ready_0_sqmuxa_0_a2_6_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40042 Ready_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40041 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40042 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output 
    F0, Q0, F1, Q1 );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  lut40043 \S_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40044 \S_s_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40043 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40044 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output 
    F0, Q0, F1, Q1 );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  lut40045 \S_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40046 \S_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \S[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40045 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40046 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2231) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
    output F0, Q0, F1, Q1 );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40047 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40048 \wb_adr_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40047 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40048 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_36 ( input C1, B1, C0, B0, DI1, DI0, CE, CLK, output F0, Q0, F1, 
    Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40049 \wb_adr_RNO[3] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40049 \wb_adr_RNO[2] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40049 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_37 ( input C1, B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40050 \wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40051 \wb_adr_RNO[4] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40050 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40051 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_38 ( input C1, B1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, Q0, 
    F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40049 \wb_adr_RNO[7] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40052 \wb_adr_RNO[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40052 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hCF03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_39 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40053 wb_cyc_stb_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40054 wb_cyc_stb_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40053 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40054 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
    output F0, Q0, F1, Q1 );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40055 \wb_dati_7_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40056 \wb_dati_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40055 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40056 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_41 ( input D1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output 
    F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40057 \wb_dati_7_0[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40058 \wb_dati_7_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40057 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40058 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
    output F0, Q0, F1, Q1 );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40058 \wb_dati_7_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40059 \wb_dati_7_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40059 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_43 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output 
    F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40060 \wb_dati_7_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40061 \wb_dati_7_0[6] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40060 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40061 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_44 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output 
    F0, Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;

  lut40062 wb_req_RNO_1( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40063 wb_req_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre0006 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge LSR, 0:0:0);
    $width (negedge LSR, 0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40062 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40063 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_45 ( input C1, B1, C0, B0, DI0, LSR, CLK, output F0, Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;

  lut40064 \un1_LEDEN13_2_i_o2[0] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40065 wb_rst8_0_a2( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre0006 wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge LSR, 0:0:0);
    $width (negedge LSR, 0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40064 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFCFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40065 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output 
    F0, Q0, F1 );
  wire   VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;

  lut40066 wb_we_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40067 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40066 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40067 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40068 DQMH_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40069 \S_RNII9DO1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40068 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40069 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40070 Vout3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40071 nCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40070 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40071 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h88F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40072 un1_CS_0_sqmuxa_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40073 un1_CS_0_sqmuxa_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40072 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40073 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40074 \wb_dati_7_0_a2_0_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40075 \wb_dati_7_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40074 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h080A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40075 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAA02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40076 CKE_6_iv_i_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40077 CKE_6_iv_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40076 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0FAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40077 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40078 \un1_LEDEN13_2_i_a2_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40079 \un1_LEDEN13_2_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40078 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40079 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40080 \un1_wb_adr_0_sqmuxa_2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
    .Z(F1));
  lut40081 wb_we_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40080 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h67EF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40081 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0501) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40082 un1_CS_0_sqmuxa_0_0_a2_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40083 un1_CS_0_sqmuxa_0_0_o2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40082 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40083 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF0F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40084 nCS_6_u_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40085 un1_nCS61_1_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40084 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40085 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_56 ( input D1, C1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40086 \wb_dati_7_0_a2_5[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40087 \wb_dati_7_0_a2_6[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40086 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h000A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40087 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40088 \un1_LEDEN13_2_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40089 \S_RNII9DO1_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40088 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h00E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40089 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40090 \wb_dati_7_0_2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40091 \wb_dati_7_0_2_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40090 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h00C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40091 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40092 DQML_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40093 DQML_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40092 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h7737) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40093 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_60 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
  wire   GNDI;

  lut40094 \wb_adr_RNO_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40095 \wb_adr_RNO_3[1] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40094 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40095 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h5000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_61 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40096 \wb_dati_7_0_a2_2_0[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40097 \FS_RNIOD6E_1[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40096 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40097 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_62 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40098 \wb_adr_RNO_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40099 \wb_adr_RNO_2[1] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40098 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40099 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8877) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40069 \un1_LEDEN13_2_i_o2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40100 \FS_RNI9FGA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40100 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40101 \FS_RNI6JJA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40102 \un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
    .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40101 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40102 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_65 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40103 \wb_dati_7_0_a2_0_0[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40104 \wb_dati_7_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40103 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40104 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_66 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40105 \FS_RNIJ9MH[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40106 wb_we_RNO_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40105 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40106 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h080C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_67 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40107 wb_reqc_1( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40108 wb_reqc_1_RNIRU4M1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40107 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40108 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40109 \wb_dati_7_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40110 \FS_RNIOD6E_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40109 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40110 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40111 \RA_42_0[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40112 \RA_42_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40111 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40112 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40113 \wb_dati_7_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40114 \FS_RNIOD6E[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40113 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h00C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40114 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h6A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40115 nRWE_r_0_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40116 \S_RNII9DO1_3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40115 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h00DF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40116 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40117 Ready_0_sqmuxa_0_a2_6_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40118 \FS_RNI5OOF1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40117 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40118 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40119 \wb_adr_7_0_a2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40120 \FS_RNIK5632[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40119 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h00D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40120 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_74 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40121 \wb_dati_7_0_a2_5[4] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40104 \wb_dati_7_0_a2_5_RNIC22J[4] ( .A(A0), .B(B0), .C(C0), .D(D0), 
    .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40121 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_75 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40110 nCS_6_u_i_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut4 nCS_6_u_i_a2_4_RNI3A062( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_76 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40122 nCS_6_u_i_o2_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40123 nCS_6_u_i_a2_4_RNICJKD2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40122 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40123 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_77 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40124 un1_CS_0_sqmuxa_0_0_a2_10( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40125 un1_CS_0_sqmuxa_0_0_2_RNIQS7F( .A(A0), .B(B0), .C(C0), .D(D0), 
    .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40124 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40125 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_78 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40122 nCAS_s_i_o2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40126 nCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40126 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hABBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_79 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40127 nCS_6_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40128 nCS_0io_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40127 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0122) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40128 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_80 ( input D1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40129 nRAS_2_iv_0_a2_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40130 nRAS_2_iv_i( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40129 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1144) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40130 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40131 un1_CS_0_sqmuxa_0_0_a2_1_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40132 un1_CS_0_sqmuxa_0_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40131 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40132 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40133 un1_CS_0_sqmuxa_0_0_a2_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40134 un1_CS_0_sqmuxa_0_0_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40133 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h070F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40134 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40135 nCS_6_u_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40136 nCS_6_u_i_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40135 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40136 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40137 \wb_dati_7_0_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40138 \wb_dati_7_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40137 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40138 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40139 \wb_adr_7_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40140 \wb_adr_7_0_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40139 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hCC08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40140 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40141 \wb_dati_7_0_a2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40142 \un1_LEDEN_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
    .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40141 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40142 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40143 un1_CS_0_sqmuxa_0_0_a2_4_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40144 un1_CS_0_sqmuxa_0_0_a2_4( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40143 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40144 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_88 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40145 \FS_RNI9Q57[13] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40146 \wb_dati_7_0_o2_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40145 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFF55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40146 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_89 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40122 \wb_adr_7_0_o2[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40147 \wb_adr_7_0_a2_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40147 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40148 \wb_dati_7_0_o2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40149 \wb_dati_7_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40148 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40149 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_91 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40150 un1_CS_0_sqmuxa_0_0_a2_2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40151 un1_CS_0_sqmuxa_0_0_a2_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40150 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40151 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40152 \wb_adr_7_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40153 \wb_adr_7_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40152 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h4450) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40153 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40154 un1_CS_0_sqmuxa_0_0_a2_1_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40098 un1_CS_0_sqmuxa_0_0_a2_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40154 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40155 un1_CS_0_sqmuxa_0_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40093 un1_CS_0_sqmuxa_0_0_a2_3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40155 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40156 wb_we_RNO_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40157 wb_we_RNO_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40156 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40157 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_96 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40158 \RA_42_i_o2[8] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40159 \RA_0io_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40158 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40159 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0B08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_97 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40160 \wb_dati_7_0_a2_1[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40161 CKE_6_iv_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40160 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40161 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_98 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40162 un1_CS_0_sqmuxa_0_0_a2_16( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40163 un1_CS_0_sqmuxa_0_0_a2_4_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40162 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40163 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_99 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40164 un1_CS_0_sqmuxa_0_0_a2_12( .A(GNDI), .B(B1), .C(GNDI), .D(D1), 
    .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40143 un1_CS_0_sqmuxa_0_0_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40164 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_100 ( input C1, B1, A1, D0, C0, B0, output F0, F1 );
  wire   GNDI;

  lut40165 un1_CS_0_sqmuxa_0_0_a2_17( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40166 CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0( .A(GNDI), .B(B0), .C(C0), .D(D0), 
    .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40165 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40166 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40167 wb_reqc_1_RNIEO5C1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40168 \S_RNII9DO1_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40167 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40168 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hD821) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40169 \S_s_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40170 \BA_0io_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40169 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8F0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40170 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40156 \RA_0io_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40134 wb_req_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40171 \wb_dati_7_0_a2_3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40172 \wb_adr_7_0_a2_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40171 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40172 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hA0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40173 \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), 
    .Z(F1));
  lut40070 \wb_dati_7_0_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40173 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_106 ( input C1, B1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40174 \S_RNINI6S[1] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40175 CKE_6_iv_i_0_1_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40174 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40175 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_107 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40176 \S_r_i_o2[1] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40023 \BA_0io_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40176 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_108 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40177 \wb_adr_7_0_a2_5_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40178 \wb_dati_7_0_a2[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40177 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40178 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40179 \wb_dati_7_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40179 \wb_dati_7_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40179 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40180 \RA_0io_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40181 CmdBitbangMXO2_RNI8CSO1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40180 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40181 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_111 ( input D1, B1, A1, D0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40182 \RA_42_3_0[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40183 \RA_0io_RNO[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40182 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAABB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40183 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAA88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_112 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40184 nCS_6_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40185 \RA_0io_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40184 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40185 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40025 \RA_0io_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40025 \RA_0io_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40186 \wb_dati_7_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40187 \un1_RWMask_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), 
    .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40186 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40187 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40188 nWE80_pad_RNI3ICD( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40189 nRWE_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40188 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40189 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0F08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_116 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40190 \wb_adr_7_0_o2_2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40191 \wb_dati_7_0_a2_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40190 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40191 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h4080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_117 ( input D1, C1, B1, A1, C0, A0, output F0, F1 );
  wire   GNDI;

  lut40192 \RWBank_5_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40193 LED_pad_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40192 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40193 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_118 ( input D1, C1, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40194 un1_CS_0_sqmuxa_0_0_a2_11( .A(GNDI), .B(GNDI), .C(C1), .D(D1), 
    .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40195 un1_CS_0_sqmuxa_0_0_a2_13( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
    .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40194 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40195 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_119 ( input D0, C0, B0, A0, output F0 );

  lut40196 Ready_0_sqmuxa_0_a2_6_a2_2_0( .A(A0), .B(B0), .C(C0), .D(D0), 
    .Z(F0));

  specify
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40196 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );

  xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));

  specify
    (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (PADDO => RD0) = (0:0:0,0:0:0);
    (RD0 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD0, 0:0:0);
    $width (negedge RD0, 0:0:0);
  endspecify

endmodule

module xo2iobuf ( input I, T, output Z, PAD, input PADI );

  IB INST1( .I(PADI), .O(Z));
  OBW INST2( .I(I), .T(T), .O(PAD));
endmodule

module LED ( input PADDO, output LED );

  xo2iobuf0197 LED_pad( .I(PADDO), .PAD(LED));

  specify
    (PADDO => LED) = (0:0:0,0:0:0);
  endspecify

endmodule

module xo2iobuf0197 ( input I, output PAD );

  OB INST5( .I(I), .O(PAD));
endmodule

module C14M ( output PADDI, input C14M );

  xo2iobuf0198 C14M_pad( .Z(PADDI), .PAD(C14M));

  specify
    (C14M => PADDI) = (0:0:0,0:0:0);
    $width (posedge C14M, 0:0:0);
    $width (negedge C14M, 0:0:0);
  endspecify

endmodule

module xo2iobuf0198 ( output Z, input PAD );

  IB INST1( .I(PAD), .O(Z));
endmodule

module DQMH ( input IOLDO, output DQMH );

  xo2iobuf0197 DQMH_pad( .I(IOLDO), .PAD(DQMH));

  specify
    (IOLDO => DQMH) = (0:0:0,0:0:0);
  endspecify

endmodule

module DQMH_MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre DQMH_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module mfflsre ( input D0, SP, CK, LSR, output Q );

  FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module DQML ( input IOLDO, output DQML );

  xo2iobuf0197 DQML_pad( .I(IOLDO), .PAD(DQML));

  specify
    (IOLDO => DQML) = (0:0:0,0:0:0);
  endspecify

endmodule

module DQML_MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre DQML_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );

  xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));

  specify
    (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (PADDO => RD7) = (0:0:0,0:0:0);
    (RD7 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD7, 0:0:0);
    $width (negedge RD7, 0:0:0);
  endspecify

endmodule

module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );

  xo2iobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));

  specify
    (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (PADDO => RD6) = (0:0:0,0:0:0);
    (RD6 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD6, 0:0:0);
    $width (negedge RD6, 0:0:0);
  endspecify

endmodule

module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );

  xo2iobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));

  specify
    (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (PADDO => RD5) = (0:0:0,0:0:0);
    (RD5 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD5, 0:0:0);
    $width (negedge RD5, 0:0:0);
  endspecify

endmodule

module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );

  xo2iobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));

  specify
    (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (PADDO => RD4) = (0:0:0,0:0:0);
    (RD4 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD4, 0:0:0);
    $width (negedge RD4, 0:0:0);
  endspecify

endmodule

module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );

  xo2iobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));

  specify
    (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (PADDO => RD3) = (0:0:0,0:0:0);
    (RD3 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD3, 0:0:0);
    $width (negedge RD3, 0:0:0);
  endspecify

endmodule

module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );

  xo2iobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));

  specify
    (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (PADDO => RD2) = (0:0:0,0:0:0);
    (RD2 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD2, 0:0:0);
    $width (negedge RD2, 0:0:0);
  endspecify

endmodule

module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );

  xo2iobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));

  specify
    (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (PADDO => RD1) = (0:0:0,0:0:0);
    (RD1 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD1, 0:0:0);
    $width (negedge RD1, 0:0:0);
  endspecify

endmodule

module RA_11_ ( input IOLDO, output RA11 );

  xo2iobuf0197 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));

  specify
    (IOLDO => RA11) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_11__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre0199 \RA_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module mfflsre0199 ( input D0, SP, CK, LSR, output Q );

  FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module RA_10_ ( input IOLDO, output RA10 );

  xo2iobuf0197 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));

  specify
    (IOLDO => RA10) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_10__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre0199 \RA_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RA_9_ ( input IOLDO, output RA9 );

  xo2iobuf0197 \RA_pad[9] ( .I(IOLDO), .PAD(RA9));

  specify
    (IOLDO => RA9) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_9__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre0199 \RA_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RA_8_ ( input IOLDO, output RA8 );

  xo2iobuf0197 \RA_pad[8] ( .I(IOLDO), .PAD(RA8));

  specify
    (IOLDO => RA8) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_8__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre0199 \RA_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RA_7_ ( input IOLDO, output RA7 );

  xo2iobuf0197 \RA_pad[7] ( .I(IOLDO), .PAD(RA7));

  specify
    (IOLDO => RA7) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \RA_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
    .LSR(GNDI), .Q(IOLDO));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RA_6_ ( input IOLDO, output RA6 );

  xo2iobuf0197 \RA_pad[6] ( .I(IOLDO), .PAD(RA6));

  specify
    (IOLDO => RA6) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \RA_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
    .LSR(GNDI), .Q(IOLDO));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RA_5_ ( input IOLDO, output RA5 );

  xo2iobuf0197 \RA_pad[5] ( .I(IOLDO), .PAD(RA5));

  specify
    (IOLDO => RA5) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \RA_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
    .LSR(GNDI), .Q(IOLDO));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RA_4_ ( input IOLDO, output RA4 );

  xo2iobuf0197 \RA_pad[4] ( .I(IOLDO), .PAD(RA4));

  specify
    (IOLDO => RA4) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \RA_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
    .LSR(GNDI), .Q(IOLDO));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RA_3_ ( input PADDO, output RA3 );

  xo2iobuf0197 \RA_pad[3] ( .I(PADDO), .PAD(RA3));

  specify
    (PADDO => RA3) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_2_ ( input IOLDO, output RA2 );

  xo2iobuf0197 \RA_pad[2] ( .I(IOLDO), .PAD(RA2));

  specify
    (IOLDO => RA2) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \RA_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
    .LSR(GNDI), .Q(IOLDO));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RA_1_ ( input IOLDO, output RA1 );

  xo2iobuf0197 \RA_pad[1] ( .I(IOLDO), .PAD(RA1));

  specify
    (IOLDO => RA1) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \RA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), 
    .LSR(GNDI), .Q(IOLDO));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RA_0_ ( input PADDO, output RA0 );

  xo2iobuf0197 \RA_pad[0] ( .I(PADDO), .PAD(RA0));

  specify
    (PADDO => RA0) = (0:0:0,0:0:0);
  endspecify

endmodule

module BA_1_ ( input IOLDO, output BA1 );

  xo2iobuf0197 \BA_pad[1] ( .I(IOLDO), .PAD(BA1));

  specify
    (IOLDO => BA1) = (0:0:0,0:0:0);
  endspecify

endmodule

module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;

  mfflsre0200 \BA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), 
    .LSR(LSR_dly), .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module mfflsre0200 ( input D0, SP, CK, LSR, output Q );

  FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module BA_0_ ( input IOLDO, output BA0 );

  xo2iobuf0197 \BA_pad[0] ( .I(IOLDO), .PAD(BA0));

  specify
    (IOLDO => BA0) = (0:0:0,0:0:0);
  endspecify

endmodule

module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;

  mfflsre0200 \BA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), 
    .LSR(LSR_dly), .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module nRWE ( input IOLDO, output nRWE );

  xo2iobuf0197 nRWE_pad( .I(IOLDO), .PAD(nRWE));

  specify
    (IOLDO => nRWE) = (0:0:0,0:0:0);
  endspecify

endmodule

module nRWE_MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module nCAS ( input IOLDO, output nCAS );

  xo2iobuf0197 nCAS_pad( .I(IOLDO), .PAD(nCAS));

  specify
    (IOLDO => nCAS) = (0:0:0,0:0:0);
  endspecify

endmodule

module nCAS_MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre nCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module nRAS ( input IOLDO, output nRAS );

  xo2iobuf0197 nRAS_pad( .I(IOLDO), .PAD(nRAS));

  specify
    (IOLDO => nRAS) = (0:0:0,0:0:0);
  endspecify

endmodule

module nRAS_MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre nRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module nCS ( input IOLDO, output nCS );

  xo2iobuf0197 nCS_pad( .I(IOLDO), .PAD(nCS));

  specify
    (IOLDO => nCS) = (0:0:0,0:0:0);
  endspecify

endmodule

module nCS_MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre nCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module CKE ( input IOLDO, output CKE );

  xo2iobuf0197 CKE_pad( .I(IOLDO), .PAD(CKE));

  specify
    (IOLDO => CKE) = (0:0:0,0:0:0);
  endspecify

endmodule

module CKE_MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre0199 CKE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module nVOE ( input PADDO, output nVOE );

  xo2iobuf0197 nVOE_pad( .I(PADDO), .PAD(nVOE));

  specify
    (PADDO => nVOE) = (0:0:0,0:0:0);
  endspecify

endmodule

module Vout_7_ ( input IOLDO, output Vout7 );

  xo2iobuf0197 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7));

  specify
    (IOLDO => Vout7) = (0:0:0,0:0:0);
  endspecify

endmodule

module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module inverter ( input I, output Z );

  INV INST1( .A(I), .Z(Z));
endmodule

module Vout_6_ ( input IOLDO, output Vout6 );

  xo2iobuf0197 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6));

  specify
    (IOLDO => Vout6) = (0:0:0,0:0:0);
  endspecify

endmodule

module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Vout_5_ ( input IOLDO, output Vout5 );

  xo2iobuf0197 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5));

  specify
    (IOLDO => Vout5) = (0:0:0,0:0:0);
  endspecify

endmodule

module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Vout_4_ ( input IOLDO, output Vout4 );

  xo2iobuf0197 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4));

  specify
    (IOLDO => Vout4) = (0:0:0,0:0:0);
  endspecify

endmodule

module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Vout_3_ ( input IOLDO, output Vout3 );

  xo2iobuf0197 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3));

  specify
    (IOLDO => Vout3) = (0:0:0,0:0:0);
  endspecify

endmodule

module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Vout_2_ ( input IOLDO, output Vout2 );

  xo2iobuf0197 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2));

  specify
    (IOLDO => Vout2) = (0:0:0,0:0:0);
  endspecify

endmodule

module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Vout_1_ ( input IOLDO, output Vout1 );

  xo2iobuf0197 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1));

  specify
    (IOLDO => Vout1) = (0:0:0,0:0:0);
  endspecify

endmodule

module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Vout_0_ ( input IOLDO, output Vout0 );

  xo2iobuf0197 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0));

  specify
    (IOLDO => Vout0) = (0:0:0,0:0:0);
  endspecify

endmodule

module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module nDOE ( input PADDO, output nDOE );

  xo2iobuf0197 nDOE_pad( .I(PADDO), .PAD(nDOE));

  specify
    (PADDO => nDOE) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_7_ ( input IOLDO, output Dout7 );

  xo2iobuf0201 \Dout_pad[7] ( .I(IOLDO), .PAD(Dout7));

  specify
    (IOLDO => Dout7) = (0:0:0,0:0:0);
  endspecify

endmodule

module xo2iobuf0201 ( input I, output PAD );

  OB INST5( .I(I), .O(PAD));
endmodule

module Dout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Dout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Dout_6_ ( input IOLDO, output Dout6 );

  xo2iobuf0201 \Dout_pad[6] ( .I(IOLDO), .PAD(Dout6));

  specify
    (IOLDO => Dout6) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Dout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Dout_5_ ( input IOLDO, output Dout5 );

  xo2iobuf0201 \Dout_pad[5] ( .I(IOLDO), .PAD(Dout5));

  specify
    (IOLDO => Dout5) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Dout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Dout_4_ ( input IOLDO, output Dout4 );

  xo2iobuf0201 \Dout_pad[4] ( .I(IOLDO), .PAD(Dout4));

  specify
    (IOLDO => Dout4) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Dout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Dout_3_ ( input IOLDO, output Dout3 );

  xo2iobuf0201 \Dout_pad[3] ( .I(IOLDO), .PAD(Dout3));

  specify
    (IOLDO => Dout3) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Dout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Dout_2_ ( input IOLDO, output Dout2 );

  xo2iobuf0201 \Dout_pad[2] ( .I(IOLDO), .PAD(Dout2));

  specify
    (IOLDO => Dout2) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Dout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Dout_1_ ( input IOLDO, output Dout1 );

  xo2iobuf0201 \Dout_pad[1] ( .I(IOLDO), .PAD(Dout1));

  specify
    (IOLDO => Dout1) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Dout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Dout_0_ ( input IOLDO, output Dout0 );

  xo2iobuf0201 \Dout_pad[0] ( .I(IOLDO), .PAD(Dout0));

  specify
    (IOLDO => Dout0) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK );
  wire   CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly;

  mfflsre0199 \Dout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(IOLDO));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module Din_7_ ( output PADDI, input Din7 );

  xo2iobuf0198 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));

  specify
    (Din7 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din7, 0:0:0);
    $width (negedge Din7, 0:0:0);
  endspecify

endmodule

module Din_6_ ( output PADDI, input Din6 );

  xo2iobuf0198 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));

  specify
    (Din6 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din6, 0:0:0);
    $width (negedge Din6, 0:0:0);
  endspecify

endmodule

module Din_5_ ( output PADDI, input Din5 );

  xo2iobuf0198 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));

  specify
    (Din5 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din5, 0:0:0);
    $width (negedge Din5, 0:0:0);
  endspecify

endmodule

module Din_4_ ( output PADDI, input Din4 );

  xo2iobuf0198 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));

  specify
    (Din4 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din4, 0:0:0);
    $width (negedge Din4, 0:0:0);
  endspecify

endmodule

module Din_3_ ( output PADDI, input Din3 );

  xo2iobuf0198 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));

  specify
    (Din3 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din3, 0:0:0);
    $width (negedge Din3, 0:0:0);
  endspecify

endmodule

module Din_2_ ( output PADDI, input Din2 );

  xo2iobuf0198 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));

  specify
    (Din2 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din2, 0:0:0);
    $width (negedge Din2, 0:0:0);
  endspecify

endmodule

module Din_1_ ( output PADDI, input Din1 );

  xo2iobuf0198 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));

  specify
    (Din1 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din1, 0:0:0);
    $width (negedge Din1, 0:0:0);
  endspecify

endmodule

module Din_0_ ( output PADDI, input Din0 );

  xo2iobuf0198 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));

  specify
    (Din0 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din0, 0:0:0);
    $width (negedge Din0, 0:0:0);
  endspecify

endmodule

module Ain_7_ ( output PADDI, input Ain7 );

  xo2iobuf0198 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7));

  specify
    (Ain7 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Ain7, 0:0:0);
    $width (negedge Ain7, 0:0:0);
  endspecify

endmodule

module Ain_6_ ( output PADDI, input Ain6 );

  xo2iobuf0198 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6));

  specify
    (Ain6 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Ain6, 0:0:0);
    $width (negedge Ain6, 0:0:0);
  endspecify

endmodule

module Ain_5_ ( output PADDI, input Ain5 );

  xo2iobuf0198 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5));

  specify
    (Ain5 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Ain5, 0:0:0);
    $width (negedge Ain5, 0:0:0);
  endspecify

endmodule

module Ain_4_ ( output PADDI, input Ain4 );

  xo2iobuf0198 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4));

  specify
    (Ain4 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Ain4, 0:0:0);
    $width (negedge Ain4, 0:0:0);
  endspecify

endmodule

module Ain_3_ ( output PADDI, input Ain3 );

  xo2iobuf0198 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3));

  specify
    (Ain3 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Ain3, 0:0:0);
    $width (negedge Ain3, 0:0:0);
  endspecify

endmodule

module Ain_2_ ( output PADDI, input Ain2 );

  xo2iobuf0198 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2));

  specify
    (Ain2 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Ain2, 0:0:0);
    $width (negedge Ain2, 0:0:0);
  endspecify

endmodule

module Ain_1_ ( output PADDI, input Ain1 );

  xo2iobuf0198 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1));

  specify
    (Ain1 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Ain1, 0:0:0);
    $width (negedge Ain1, 0:0:0);
  endspecify

endmodule

module Ain_0_ ( output PADDI, input Ain0 );

  xo2iobuf0198 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0));

  specify
    (Ain0 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Ain0, 0:0:0);
    $width (negedge Ain0, 0:0:0);
  endspecify

endmodule

module nC07X ( output PADDI, input nC07X );

  xo2iobuf0198 nC07X_pad( .Z(PADDI), .PAD(nC07X));

  specify
    (nC07X => PADDI) = (0:0:0,0:0:0);
    $width (posedge nC07X, 0:0:0);
    $width (negedge nC07X, 0:0:0);
  endspecify

endmodule

module nEN80 ( output PADDI, input nEN80 );

  xo2iobuf0198 nEN80_pad( .Z(PADDI), .PAD(nEN80));

  specify
    (nEN80 => PADDI) = (0:0:0,0:0:0);
    $width (posedge nEN80, 0:0:0);
    $width (negedge nEN80, 0:0:0);
  endspecify

endmodule

module nWE80 ( output PADDI, input nWE80 );

  xo2iobuf0198 nWE80_pad( .Z(PADDI), .PAD(nWE80));

  specify
    (nWE80 => PADDI) = (0:0:0,0:0:0);
    $width (posedge nWE80, 0:0:0);
    $width (negedge nWE80, 0:0:0);
  endspecify

endmodule

module nWE ( output PADDI, input nWE );

  xo2iobuf0198 nWE_pad( .Z(PADDI), .PAD(nWE));

  specify
    (nWE => PADDI) = (0:0:0,0:0:0);
    $width (posedge nWE, 0:0:0);
    $width (negedge nWE, 0:0:0);
  endspecify

endmodule

module PHI1 ( output PADDI, input PHI1 );

  xo2iobuf0198 PHI1_pad( .Z(PADDI), .PAD(PHI1));

  specify
    (PHI1 => PADDI) = (0:0:0,0:0:0);
    $width (posedge PHI1, 0:0:0);
    $width (negedge PHI1, 0:0:0);
  endspecify

endmodule

module PHI1_MGIOL ( input DI, CLK, output IN );
  wire   VCCI, GNDI, DI_dly, CLK_dly;

  smuxlregsre PHI1reg_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IN));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IN) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module smuxlregsre ( input D0, SP, CK, LSR, output Q );

  IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, 
    WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, 
    WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output 
    WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, 
    WBACKO );
  wire   VCCI, GNDI;

  EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), 
    .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), 
    .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), 
    .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), 
    .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), 
    .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), 
    .WBDATO1(WBDATO1), .WBDATO2(WBDATO2), .WBDATO3(WBDATO3), .WBDATO4(WBDATO4), 
    .WBDATO5(WBDATO5), .WBDATO6(WBDATO6), .WBDATO7(WBDATO7), .WBACKO(WBACKO), 
    .WBCUFMIRQ(), .UFMSN(VCCI), .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), 
    .I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), 
    .I2C2SCLI(GNDI), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), 
    .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), 
    .SPISCKEN(), .SPIMISOI(GNDI), .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), 
    .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), 
    .SPIMCSN3(), .SPIMCSN4(), .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), 
    .SPICSNEN(), .SPISCSN(GNDI), .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), 
    .TCIC(GNDI), .TCINT(), .TCOC(), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), 
    .PLL1STBO(), .PLLWEO(), .PLLADRO0(), .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), 
    .PLLADRO4(), .PLLDATO0(), .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), 
    .PLLDATO4(), .PLLDATO5(), .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), 
    .PLL0DATI1(GNDI), .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), 
    .PLL0DATI5(GNDI), .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), 
    .PLL1DATI0(GNDI), .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), 
    .PLL1DATI4(GNDI), .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), 
    .PLL1ACKI(GNDI));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
endmodule

module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, 
    WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, 
    WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, 
    WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, 
    WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output 
    I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input 
    I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, 
    I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, 
    input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output 
    SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, 
    SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, 
    input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, 
    PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, 
    PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, 
    PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, 
    PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, 
    PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI );
  wire   WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, 
         WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, 
         WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, 
         WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, 
         WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, 
         PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, 
         PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, 
         PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, 
         PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, 
         I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, 
         SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, 
         UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, 
         WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, 
         PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, 
         PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, 
         PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, 
         PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, 
         I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, 
         I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, 
         I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, 
         SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, 
         SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, 
         SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, 
         CFGWAKE_buf, CFGSTDBY_buf;

  EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), 
    .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), 
    .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), 
    .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), 
    .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), 
    .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), 
    .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), 
    .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), 
    .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), 
    .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), 
    .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), 
    .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), 
    .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), 
    .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), 
    .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), 
    .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), 
    .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), 
    .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), 
    .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), 
    .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), 
    .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), 
    .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), 
    .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), 
    .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), 
    .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), 
    .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), 
    .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), 
    .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), 
    .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), 
    .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), 
    .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), 
    .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), 
    .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), 
    .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), 
    .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), 
    .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), 
    .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), 
    .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), 
    .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), 
    .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), 
    .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), 
    .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf));
  defparam INST10.DEV_DENSITY = "640L";
  defparam INST10.EFB_I2C1 = "DISABLED";
  defparam INST10.EFB_I2C2 = "DISABLED";
  defparam INST10.EFB_SPI = "DISABLED";
  defparam INST10.EFB_TC = "DISABLED";
  defparam INST10.EFB_TC_PORTMODE = "WB";
  defparam INST10.EFB_UFM = "ENABLED";
  defparam INST10.EFB_WB_CLK_FREQ = "14.4";
  defparam INST10.GSR = "ENABLED";
  defparam INST10.I2C1_ADDRESSING = "7BIT";
  defparam INST10.I2C1_BUS_PERF = "100kHz";
  defparam INST10.I2C1_CLK_DIVIDER = 1;
  defparam INST10.I2C1_GEN_CALL = "DISABLED";
  defparam INST10.I2C1_SLAVE_ADDR = "0b1000001";
  defparam INST10.I2C1_WAKEUP = "DISABLED";
  defparam INST10.I2C2_ADDRESSING = "7BIT";
  defparam INST10.I2C2_BUS_PERF = "100kHz";
  defparam INST10.I2C2_CLK_DIVIDER = 1;
  defparam INST10.I2C2_GEN_CALL = "DISABLED";
  defparam INST10.I2C2_SLAVE_ADDR = "0b1000010";
  defparam INST10.I2C2_WAKEUP = "DISABLED";
  defparam INST10.SPI_CLK_DIVIDER = 1;
  defparam INST10.SPI_CLK_INV = "DISABLED";
  defparam INST10.SPI_INTR_RXOVR = "DISABLED";
  defparam INST10.SPI_INTR_RXRDY = "DISABLED";
  defparam INST10.SPI_INTR_TXOVR = "DISABLED";
  defparam INST10.SPI_INTR_TXRDY = "DISABLED";
  defparam INST10.SPI_LSB_FIRST = "DISABLED";
  defparam INST10.SPI_MODE = "MASTER";
  defparam INST10.SPI_PHASE_ADJ = "DISABLED";
  defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED";
  defparam INST10.SPI_WAKEUP = "DISABLED";
  defparam INST10.TC_CCLK_SEL = 1;
  defparam INST10.TC_ICAPTURE = "DISABLED";
  defparam INST10.TC_ICR_INT = "OFF";
  defparam INST10.TC_MODE = "CTCM";
  defparam INST10.TC_OCR_INT = "OFF";
  defparam INST10.TC_OCR_SET = 32767;
  defparam INST10.TC_OC_MODE = "TOGGLE";
  defparam INST10.TC_OVERFLOW = "DISABLED";
  defparam INST10.TC_OV_INT = "OFF";
  defparam INST10.TC_RESETN = "ENABLED";
  defparam INST10.TC_SCLK_SEL = "PCLOCK";
  defparam INST10.TC_TOP_SEL = "OFF";
  defparam INST10.TC_TOP_SET = 65535;
  defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED";
  defparam INST10.UFM_INIT_FILE_FORMAT = "HEX";
  defparam INST10.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem";
  defparam INST10.UFM_INIT_PAGES = 1;
  defparam INST10.UFM_INIT_START_PAGE = 190;
  EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), 
    .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), 
    .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), 
    .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), 
    .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), 
    .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), 
    .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), 
    .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), 
    .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), 
    .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), 
    .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), 
    .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), 
    .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), 
    .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), 
    .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), 
    .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), 
    .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), 
    .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), 
    .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), 
    .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), 
    .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), 
    .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), 
    .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), 
    .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), 
    .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), 
    .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), 
    .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), 
    .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), 
    .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), 
    .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), 
    .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), 
    .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), 
    .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), 
    .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), 
    .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), 
    .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), 
    .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), 
    .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), 
    .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), 
    .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), 
    .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), 
    .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), 
    .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), 
    .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), 
    .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), 
    .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), 
    .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), 
    .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), 
    .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), 
    .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), 
    .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), 
    .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), 
    .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), 
    .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), 
    .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), 
    .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), 
    .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), 
    .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), 
    .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), 
    .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), 
    .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), 
    .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), 
    .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), 
    .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), 
    .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), 
    .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), 
    .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), 
    .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), 
    .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), 
    .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), 
    .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), 
    .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), 
    .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), 
    .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), 
    .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), 
    .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), 
    .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), 
    .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), 
    .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), 
    .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), 
    .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), 
    .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), 
    .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), 
    .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), 
    .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), 
    .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), 
    .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), 
    .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), 
    .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), 
    .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), 
    .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), 
    .CFGSTDBYin(CFGSTDBY_buf));
endmodule

module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, 
    output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, 
    output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output 
    WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output 
    WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output 
    WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output 
    WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output 
    WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output 
    WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output 
    WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output 
    WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output 
    PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, 
    output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input 
    PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, 
    input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output 
    PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, 
    output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input 
    PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, 
    input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output 
    PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, 
    output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input 
    I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, 
    input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, 
    input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, 
    input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, 
    input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input 
    TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input 
    WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input 
    WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input 
    WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input 
    WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input 
    WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input 
    PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, 
    input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, 
    input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, 
    input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, 
    input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, 
    input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, 
    input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, 
    input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, 
    input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output 
    I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, 
    output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input 
    I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, 
    input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output 
    I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, 
    output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, 
    output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input 
    SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, 
    input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output 
    SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, 
    output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, 
    output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, 
    output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, 
    output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, 
    output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, 
    output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin );
  wire   WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, 
         WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, 
         WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, 
         WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, 
         WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly;

  BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout));
  BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout));
  BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout));
  BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout));
  BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout));
  BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out));
  BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out));
  BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out));
  BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out));
  BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out));
  BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out));
  BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out));
  BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out));
  BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out));
  BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out));
  BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out));
  BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out));
  BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out));
  BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out));
  BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out));
  BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out));
  BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out));
  BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out));
  BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out));
  BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out));
  BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out));
  BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out));
  BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out));
  BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out));
  BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout));
  BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out));
  BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out));
  BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out));
  BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out));
  BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out));
  BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out));
  BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out));
  BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out));
  BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout));
  BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout));
  BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout));
  BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout));
  BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout));
  BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout));
  BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout));
  BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout));
  BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout));
  BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout));
  BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout));
  BUFBA TCIC_buf( .A(TCICin), .Z(TCICout));
  BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout));
  BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out));
  BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out));
  BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out));
  BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out));
  BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out));
  BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out));
  BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out));
  BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out));
  BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout));
  BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout));
  BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout));
  BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout));
  BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout));
  BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout));
  BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out));
  BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out));
  BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out));
  BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out));
  BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out));
  BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out));
  BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out));
  BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out));
  BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out));
  BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out));
  BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out));
  BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out));
  BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out));
  BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout));
  BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout));
  BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout));
  BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout));
  BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout));
  BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout));
  BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout));
  BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout));
  BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout));
  BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout));
  BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout));
  BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout));
  BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout));
  BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout));
  BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout));
  BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout));
  BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out));
  BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out));
  BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out));
  BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out));
  BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out));
  BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out));
  BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out));
  BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out));
  BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout));
  BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout));
  BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout));
  BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout));
  BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout));
  BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout));
  BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout));

  specify
    (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0);
    (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0);
    (WBCLKIin => WBDATO2out) = (0:0:0,0:0:0);
    (WBCLKIin => WBDATO3out) = (0:0:0,0:0:0);
    (WBCLKIin => WBDATO4out) = (0:0:0,0:0:0);
    (WBCLKIin => WBDATO5out) = (0:0:0,0:0:0);
    (WBCLKIin => WBDATO6out) = (0:0:0,0:0:0);
    (WBCLKIin => WBDATO7out) = (0:0:0,0:0:0);
    (WBCLKIin => WBACKOout) = (0:0:0,0:0:0);
    $setuphold 
      (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly);
    $setuphold 
      (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly);
    $setuphold 
      (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly);
    $setuphold 
      (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly);
    $width (posedge WBCLKIin, 0:0:0);
    $width (negedge WBCLKIin, 0:0:0);
  endspecify

endmodule