PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jul 12 16:08:03 2024
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/promote.xml
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
Cost Table Summary
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 56.179 0 0.319 0 38 Completed
* : Design saved.
Total (real) run time for 1-seed: 40 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Lattice Place and Route Report for Design "RAM2E_LCMXO2_1200HC_impl1_map.ncd"
Fri Jul 12 16:08:04 2024
Best Par Run
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file RAM2E_LCMXO2_1200HC_impl1_map.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 70+4(JTAG)/108 69% used
70+4(JTAG)/80 93% bonded
IOLOGIC 22/108 20% used
SLICE 145/640 22% used
EFB 1/1 100% used
Number of Signals: 447
Number of Connections: 1292
Pin Constraint Summary:
70 out of 70 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
C14M_c (driver: C14M, clk load #: 84)
WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
RWBank14 (driver: ram2e_ufm/SLICE_89, clk load #: 0, sr load #: 0, ce load #: 10)
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
........
Finished Placer Phase 0. REAL time: 4 secs
Starting Placer Phase 1.
....................
Placer score = 83226.
Finished Placer Phase 1. REAL time: 15 secs
Starting Placer Phase 2.
.
Placer score = 83139
Finished Placer Phase 2. REAL time: 15 secs
Clock Report
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
General PIO: 1 out of 108 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 84
SECONDARY "RWBank14" from F0 on comp "ram2e_ufm/SLICE_89" on site "R7C12C", clk load = 0, ce load = 10, sr load = 0
PRIMARY : 1 out of 8 (12%)
SECONDARY: 1 out of 8 (12%)
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
70 + 4(JTAG) out of 108 (68.5%) PIO sites used.
70 + 4(JTAG) out of 80 (92.5%) bonded PIO sites used.
Number of PIO comps: 70; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 11 / 19 ( 57%) | 3.3V | - |
| 1 | 20 / 21 ( 95%) | 3.3V | - |
| 2 | 19 / 20 ( 95%) | 3.3V | - |
| 3 | 20 / 20 (100%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 8 secs
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
0 connections routed; 1292 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=PHI1_c loads=5 clock_loads=3
Completed router resource preassignment. Real time: 29 secs
Start NBR router at 16:08:33 07/12/24
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 16:08:33 07/12/24
Start NBR section for initial routing at 16:08:33 07/12/24
Level 4, iteration 1
14(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 56.179ns/0.000ns; real time: 37 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 16:08:41 07/12/24
Level 4, iteration 1
6(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 56.179ns/0.000ns; real time: 37 secs
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 56.179ns/0.000ns; real time: 37 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 56.179ns/0.000ns; real time: 37 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 16:08:41 07/12/24
Start NBR section for re-routing at 16:08:41 07/12/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 56.179ns/0.000ns; real time: 37 secs
Start NBR section for post-routing at 16:08:41 07/12/24
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 56.179ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=PHI1_c loads=5 clock_loads=3
Total CPU time 14 secs
Total REAL time: 38 secs
Completely routed.
End of route. 1292 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 56.179
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.319
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 14 secs
Total REAL time to completion: 39 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.