Flow report for RAM2E Sun Feb 16 22:32:27 2020 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Flow Summary 3. Flow Settings 4. Flow Non-Default Global Settings 5. Flow Elapsed Time 6. Flow OS Summary 7. Flow Log 8. Flow Messages 9. Flow Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ ; Flow Status ; Successful - Sun Feb 16 22:32:27 2020 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; ; Family ; MAX7000S ; ; Device ; EPM7128SLC84-15 ; ; Timing Models ; Final ; ; Total macrocells ; 55 / 128 ( 43 % ) ; ; Total pins ; 68 / 68 ( 100 % ) ; +---------------------------+-------------------------------------------------+ +-----------------------------------------+ ; Flow Settings ; +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ ; Start date & time ; 02/16/2020 22:32:22 ; ; Main task ; Compilation ; ; Revision Name ; RAM2E ; +-------------------+---------------------+ +-----------------------------------------------------------------------------------------------------------------------------+ ; Flow Non-Default Global Settings ; +--------------------------------------------+---------------------------------+---------------+-------------+----------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +--------------------------------------------+---------------------------------+---------------+-------------+----------------+ ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ; ; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ; ; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 207120313862967.158191034233144 ; -- ; -- ; -- ; ; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ; ; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; On ; -- ; -- ; eda_simulation ; ; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; ; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ; ; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; ; POWER_USE_PVA ; Off ; On ; -- ; -- ; ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ; ; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ; ; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; +--------------------------------------------+---------------------------------+---------------+-------------+----------------+ +-------------------------------------------------------------------------------------------------------------------------------+ ; Flow Elapsed Time ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4586 MB ; 00:00:01 ; ; Fitter ; 00:00:00 ; 1.0 ; 4697 MB ; 00:00:00 ; ; Assembler ; 00:00:00 ; 1.0 ; 4522 MB ; 00:00:00 ; ; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4525 MB ; 00:00:00 ; ; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4493 MB ; 00:00:00 ; ; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------------------------------------------------------------------------+ ; Flow OS Summary ; +---------------------------+------------------+-----------+------------+----------------+ ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; +---------------------------+------------------+-----------+------------+----------------+ ; Analysis & Synthesis ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; ; Fitter ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; ; Assembler ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; ; TimeQuest Timing Analyzer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; ; EDA Netlist Writer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; +---------------------------+------------------+-----------+------------+----------------+ ------------ ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E quartus_sta RAM2E -c RAM2E quartus_eda --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E