Analysis & Synthesis report for RAM2E Sun Feb 16 22:32:22 2020 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation 5. Analysis & Synthesis Source Files Read 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity 8. Registers Removed During Synthesis 9. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 10. Analysis & Synthesis Messages 11. Analysis & Synthesis Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Sun Feb 16 22:32:22 2020 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; ; Family ; MAX7000S ; ; Total macrocells ; 55 ; ; Total pins ; 64 ; +-----------------------------+-------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +----------------------------------------------------------------------------+-----------------+---------------+ ; Option ; Setting ; Default Value ; +----------------------------------------------------------------------------+-----------------+---------------+ ; Device ; EPM7128SLC84-15 ; ; ; Top-level entity name ; RAM2E ; RAM2E ; ; Family name ; MAX7000S ; Cyclone IV GX ; ; Ignore LCELL Buffers ; Off ; Auto ; ; Auto Logic Cell Insertion ; Off ; On ; ; Auto Parallel Expanders ; Off ; On ; ; Analysis & Synthesis Message Level ; High ; Medium ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; Parallel Synthesis ; On ; On ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; Off ; Off ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Speed ; Speed ; ; Allow XOR Gate Usage ; On ; On ; ; Parallel Expander Chain Length ; 4 ; 4 ; ; Auto Open-Drain Pins ; On ; On ; ; Auto Resource Sharing ; Off ; Off ; ; Maximum Fan-in Per Macrocell ; 100 ; 100 ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Report Connectivity Checks ; On ; On ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Block Design Naming ; Auto ; Auto ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Synthesis Seed ; 1 ; 1 ; +----------------------------------------------------------------------------+-----------------+---------------+ Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. +-------------------------------------+ ; Parallel Compilation ; +----------------------------+--------+ ; Processors ; Number ; +----------------------------+--------+ ; Number detected on machine ; 8 ; ; Maximum allowed ; 1 ; +----------------------------+--------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ ; RAM2E.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v ; ; ; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ; ; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ; ; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ; ; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; ; cmpconst.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/cmpconst.inc ; ; ; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_compare.inc ; ; ; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.inc ; ; ; dffeea.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dffeea.inc ; ; ; alt_counter_stratix.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_counter_stratix.inc ; ; ; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc ; ; +----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ +---------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +----------------------+----------------------+ ; Resource ; Usage ; +----------------------+----------------------+ ; Logic cells ; 55 ; ; Total registers ; 39 ; ; I/O pins ; 64 ; ; Shareable expanders ; 4 ; ; Maximum fan-out node ; S[3] ; ; Maximum fan-out ; 39 ; ; Total fan-out ; 350 ; ; Average fan-out ; 2.85 ; +----------------------+----------------------+ +----------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +----------------------------+------------+------+------------------------------+--------------+ ; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ; +----------------------------+------------+------+------------------------------+--------------+ ; |RAM2E ; 55 ; 64 ; |RAM2E ; work ; ; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |RAM2E|lpm_counter:Ref_rtl_0 ; work ; +----------------------------+------------+------+------------------------------+--------------+ +--------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +---------------------------------------+----------------------------------------+ ; Register name ; Reason for Removal ; +---------------------------------------+----------------------------------------+ ; RA[11]~reg0 ; Stuck at GND due to stuck port data_in ; ; Total Number of Removed Registers = 1 ; ; +---------------------------------------+----------------------------------------+ +------------------------------------------------------------------------+ ; Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 ; +------------------------+-------------------+---------------------------+ ; Parameter Name ; Value ; Type ; +------------------------+-------------------+---------------------------+ ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; LPM_WIDTH ; 4 ; Untyped ; ; LPM_DIRECTION ; UP ; Untyped ; ; LPM_MODULUS ; 0 ; Untyped ; ; LPM_AVALUE ; UNUSED ; Untyped ; ; LPM_SVALUE ; UNUSED ; Untyped ; ; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ; ; DEVICE_FAMILY ; MAX7000S ; Untyped ; ; CARRY_CHAIN ; MANUAL ; Untyped ; ; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; ; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; ; CARRY_CNT_EN ; SMART ; Untyped ; ; LABWIDE_SCLR ; ON ; Untyped ; ; USE_NEW_VERSION ; TRUE ; Untyped ; ; CBXI_PARAMETER ; NOTHING ; Untyped ; +------------------------+-------------------+---------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Processing started: Sun Feb 16 22:32:21 2020 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file ram2e.v Info (12023): Found entity 1: RAM2E Info (12127): Elaborating entity "RAM2E" for the top level hierarchy Warning (10230): Verilog HDL assignment warning at RAM2E.v(60): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at RAM2E.v(65): truncated value with size 32 to match size of target (4) Warning (14130): Reduced register "RA[11]~reg0" with stuck data_in port to stuck value GND Info (19000): Inferred 1 megafunctions from design logic Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0" Info (12130): Elaborated megafunction instantiation "lpm_counter:Ref_rtl_0" Info (12133): Instantiated megafunction "lpm_counter:Ref_rtl_0" with the following parameter: Info (12134): Parameter "LPM_WIDTH" = "4" Info (12134): Parameter "LPM_DIRECTION" = "UP" Info (12134): Parameter "LPM_TYPE" = "LPM_COUNTER" Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "RA[11]" is stuck at GND Warning (13410): Pin "DelayOut[0]" is stuck at GND Warning (13410): Pin "DelayOut[3]" is stuck at GND Info (280013): Promoted pin-driven signal(s) to global signal Info (280014): Promoted clock signal driven by pin "C14M" to global clock signal Warning (21074): Design contains 18 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "C14M_2" Warning (15610): No output dependent on input pin "C7M" Warning (15610): No output dependent on input pin "Q3" Warning (15610): No output dependent on input pin "PHI0" Warning (15610): No output dependent on input pin "nPRAS" Warning (15610): No output dependent on input pin "nPCAS" Warning (15610): No output dependent on input pin "MA[1]" Warning (15610): No output dependent on input pin "MA[2]" Warning (15610): No output dependent on input pin "MA[4]" Warning (15610): No output dependent on input pin "MA[5]" Warning (15610): No output dependent on input pin "MA[6]" Warning (15610): No output dependent on input pin "MA[7]" Warning (15610): No output dependent on input pin "Q3_2" Warning (15610): No output dependent on input pin "C3M58" Warning (15610): No output dependent on input pin "AN3" Warning (15610): No output dependent on input pin "nCASEN" Warning (15610): No output dependent on input pin "DelayIn[0]" Warning (15610): No output dependent on input pin "DelayIn[3]" Info (21057): Implemented 123 device resources after synthesis - the final resource count might be different Info (21058): Implemented 28 input pins Info (21059): Implemented 12 output pins Info (21060): Implemented 24 bidirectional pins Info (21063): Implemented 55 macrocells Info (21073): Implemented 4 shareable expanders Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 27 warnings Info: Peak virtual memory: 4586 megabytes Info: Processing ended: Sun Feb 16 22:32:22 2020 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg.