Setting log file to '//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/ram2e/CPLD/RAM2E.v'
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/ram2e/CPLD/UFM-LCMXO2.v'
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/REFB.v'
INFO - //Mac/iCloud/Repos/ram2e/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E'
INFO - //Mac/iCloud/Repos/ram2e/CPLD/RAM2E.v(1,1-473,10) (VERI-9000) elaborating module 'RAM2E'
INFO - //Mac/iCloud/Repos/ram2e/CPLD/UFM-LCMXO2.v(1,1-334,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
INFO - //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
Done: design load finished with (0) errors, and (0) warnings