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RAM2E/CPLD/DHGR-OFF.v
Zane Kaminski e23b3a29a2 RC1
2024-06-09 01:17:38 -04:00

2 lines
68 B
Verilog

module DHGR(nDHGROE); output nDHGROE; assign nDHGROE = 1; endmodule