mirror of
https://github.com/garrettsworkshop/RAM2E.git
synced 2024-11-30 23:49:40 +00:00
308 lines
11 KiB
HTML
308 lines
11 KiB
HTML
<HTML>
|
|
<HEAD><TITLE>Place & Route Report</TITLE>
|
|
<STYLE TYPE="text/css">
|
|
<!--
|
|
body,pre{
|
|
font-family:'Courier New', monospace;
|
|
color: #000000;
|
|
font-size:88%;
|
|
background-color: #ffffff;
|
|
}
|
|
h1 {
|
|
font-weight: bold;
|
|
margin-top: 24px;
|
|
margin-bottom: 10px;
|
|
border-bottom: 3px solid #000; font-size: 1em;
|
|
}
|
|
h2 {
|
|
font-weight: bold;
|
|
margin-top: 18px;
|
|
margin-bottom: 5px;
|
|
font-size: 0.90em;
|
|
}
|
|
h3 {
|
|
font-weight: bold;
|
|
margin-top: 12px;
|
|
margin-bottom: 5px;
|
|
font-size: 0.80em;
|
|
}
|
|
p {
|
|
font-size:78%;
|
|
}
|
|
P.Table {
|
|
margin-top: 4px;
|
|
margin-bottom: 4px;
|
|
margin-right: 4px;
|
|
margin-left: 4px;
|
|
}
|
|
table
|
|
{
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
border-collapse: collapse;
|
|
}
|
|
th {
|
|
font-weight:bold;
|
|
padding: 4px;
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
vertical-align:top;
|
|
text-align:left;
|
|
font-size:78%;
|
|
}
|
|
td {
|
|
padding: 4px;
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
vertical-align:top;
|
|
font-size:78%;
|
|
}
|
|
a {
|
|
color:#013C9A;
|
|
text-decoration:none;
|
|
}
|
|
|
|
a:visited {
|
|
color:#013C9A;
|
|
}
|
|
|
|
a:hover, a:active {
|
|
text-decoration:underline;
|
|
color:#5BAFD4;
|
|
}
|
|
.pass
|
|
{
|
|
background-color: #00ff00;
|
|
}
|
|
.fail
|
|
{
|
|
background-color: #ff0000;
|
|
}
|
|
.comment
|
|
{
|
|
font-size: 90%;
|
|
font-style: italic;
|
|
}
|
|
|
|
-->
|
|
</STYLE>
|
|
</HEAD>
|
|
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|
Fri Jun 07 20:50:07 2024
|
|
|
|
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
|
|
RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
|
|
RAM2E_LCMXO2_1200HC_impl1.prf -gui
|
|
|
|
|
|
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
|
|
|
|
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
|
|
Level/ Number Worst Timing Worst Timing Run NCD
|
|
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
|
---------- -------- ----- ------ ----------- ----------- ---- ------
|
|
5_1 * 0 56.210 0 0.326 0 17 Completed
|
|
* : Design saved.
|
|
|
|
Total (real) run time for 1-seed: 17 secs
|
|
|
|
par done!
|
|
|
|
Note: user must run 'Trace' for timing closure signoff.
|
|
|
|
Lattice Place and Route Report for Design "RAM2E_LCMXO2_1200HC_impl1_map.ncd"
|
|
Fri Jun 07 20:50:07 2024
|
|
|
|
|
|
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
|
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
|
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
|
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
|
|
Placement level-cost: 5-1.
|
|
Routing Iterations: 6
|
|
|
|
Loading design for application par from file RAM2E_LCMXO2_1200HC_impl1_map.ncd.
|
|
Design name: RAM2E
|
|
NCD version: 3.3
|
|
Vendor: LATTICE
|
|
Device: LCMXO2-1200HC
|
|
Package: TQFP100
|
|
Performance: 4
|
|
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
|
|
Package Status: Final Version 1.42.
|
|
Performance Hardware Data Status: Final Version 34.4.
|
|
License checked out.
|
|
|
|
|
|
Ignore Preference Error(s): True
|
|
|
|
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
|
|
|
PIO (prelim) 70+4(JTAG)/108 69% used
|
|
70+4(JTAG)/80 93% bonded
|
|
IOLOGIC 22/108 20% used
|
|
|
|
SLICE 148/640 23% used
|
|
|
|
EFB 1/1 100% used
|
|
|
|
|
|
Number of Signals: 465
|
|
Number of Connections: 1330
|
|
|
|
Pin Constraint Summary:
|
|
70 out of 70 pins locked (100% locked).
|
|
|
|
The following 1 signal is selected to use the primary clock routing resources:
|
|
C14M_c (driver: C14M, clk load #: 85)
|
|
|
|
WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
|
|
|
The following 1 signal is selected to use the secondary clock routing resources:
|
|
RWBank14 (driver: ram2e_ufm/SLICE_82, clk load #: 0, sr load #: 0, ce load #: 11)
|
|
|
|
No signal is selected as Global Set/Reset.
|
|
Starting Placer Phase 0.
|
|
.......
|
|
Finished Placer Phase 0. REAL time: 2 secs
|
|
|
|
Starting Placer Phase 1.
|
|
....................
|
|
Placer score = 84481.
|
|
Finished Placer Phase 1. REAL time: 8 secs
|
|
|
|
Starting Placer Phase 2.
|
|
.
|
|
Placer score = 83723
|
|
Finished Placer Phase 2. REAL time: 8 secs
|
|
|
|
|
|
|
|
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
|
|
|
|
Global Clock Resources:
|
|
CLK_PIN : 0 out of 8 (0%)
|
|
General PIO: 1 out of 108 (0%)
|
|
PLL : 0 out of 1 (0%)
|
|
DCM : 0 out of 2 (0%)
|
|
DCC : 0 out of 8 (0%)
|
|
|
|
Global Clocks:
|
|
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 85
|
|
SECONDARY "RWBank14" from F0 on comp "ram2e_ufm/SLICE_82" on site "R7C12A", clk load = 0, ce load = 11, sr load = 0
|
|
|
|
PRIMARY : 1 out of 8 (12%)
|
|
SECONDARY: 1 out of 8 (12%)
|
|
|
|
Edge Clocks:
|
|
No edge clock selected.
|
|
|
|
|
|
|
|
|
|
I/O Usage Summary (final):
|
|
70 + 4(JTAG) out of 108 (68.5%) PIO sites used.
|
|
70 + 4(JTAG) out of 80 (92.5%) bonded PIO sites used.
|
|
Number of PIO comps: 70; differential: 0.
|
|
Number of Vref pins used: 0.
|
|
|
|
I/O Bank Usage Summary:
|
|
+----------+----------------+------------+-----------+
|
|
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
|
+----------+----------------+------------+-----------+
|
|
| 0 | 11 / 19 ( 57%) | 3.3V | - |
|
|
| 1 | 20 / 21 ( 95%) | 3.3V | - |
|
|
| 2 | 19 / 20 ( 95%) | 3.3V | - |
|
|
| 3 | 20 / 20 (100%) | 3.3V | - |
|
|
+----------+----------------+------------+-----------+
|
|
|
|
Total placer CPU time: 7 secs
|
|
|
|
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
|
|
|
0 connections routed; 1330 unrouted.
|
|
Starting router resource preassignment
|
|
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
|
|
|
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
|
Signal=PHI1_c loads=5 clock_loads=3
|
|
|
|
Completed router resource preassignment. Real time: 14 secs
|
|
|
|
Start NBR router at 20:50:21 06/07/24
|
|
|
|
*****************************************************************
|
|
Info: NBR allows conflicts(one node used by more than one signal)
|
|
in the earlier iterations. In each iteration, it tries to
|
|
solve the conflicts while keeping the critical connections
|
|
routed as short as possible. The routing process is said to
|
|
be completed when no conflicts exist and all connections
|
|
are routed.
|
|
Note: NBR uses a different method to calculate timing slacks. The
|
|
worst slack and total negative slack may not be the same as
|
|
that in TRCE report. You should always run TRCE to verify
|
|
your design.
|
|
*****************************************************************
|
|
|
|
Start NBR special constraint process at 20:50:21 06/07/24
|
|
|
|
Start NBR section for initial routing at 20:50:21 06/07/24
|
|
Level 4, iteration 1
|
|
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 56.222ns/0.000ns; real time: 15 secs
|
|
|
|
Info: Initial congestion level at 75% usage is 0
|
|
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
|
|
|
Start NBR section for normal routing at 20:50:22 06/07/24
|
|
Level 4, iteration 1
|
|
6(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 56.222ns/0.000ns; real time: 15 secs
|
|
Level 4, iteration 2
|
|
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 56.210ns/0.000ns; real time: 15 secs
|
|
Level 4, iteration 3
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 56.210ns/0.000ns; real time: 15 secs
|
|
|
|
Start NBR section for setup/hold timing optimization with effort level 3 at 20:50:22 06/07/24
|
|
|
|
Start NBR section for re-routing at 20:50:23 06/07/24
|
|
Level 4, iteration 1
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 56.210ns/0.000ns; real time: 16 secs
|
|
|
|
Start NBR section for post-routing at 20:50:23 06/07/24
|
|
|
|
End NBR router with 0 unrouted connection
|
|
|
|
NBR Summary
|
|
-----------
|
|
Number of unrouted connections : 0 (0.00%)
|
|
Number of connections with timing violations : 0 (0.00%)
|
|
Estimated worst slack<setup> : 56.210ns
|
|
Timing score<setup> : 0
|
|
-----------
|
|
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
|
|
|
|
|
|
|
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
|
Signal=PHI1_c loads=5 clock_loads=3
|
|
|
|
Total CPU time 14 secs
|
|
Total REAL time: 16 secs
|
|
Completely routed.
|
|
End of route. 1330 routed (100.00%); 0 unrouted.
|
|
|
|
Hold time timing score: 0, hold timing errors: 0
|
|
|
|
Timing score: 0
|
|
|
|
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
|
|
|
|
|
All signals are completely routed.
|
|
|
|
|
|
PAR_SUMMARY::Run status = Completed
|
|
PAR_SUMMARY::Number of unrouted conns = 0
|
|
PAR_SUMMARY::Worst slack<setup/<ns>> = 56.210
|
|
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
|
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.326
|
|
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
|
PAR_SUMMARY::Number of errors = 0
|
|
|
|
Total CPU time to completion: 14 secs
|
|
Total REAL time to completion: 17 secs
|
|
|
|
par done!
|
|
|
|
Note: user must run 'Trace' for timing closure signoff.
|
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|
|
|
|
|
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
</PRE></FONT>
|
|
</BODY>
|
|
</HTML>
|