786 lines
27 KiB
Verilog
786 lines
27 KiB
Verilog
module RAM2E(C14M, PHI1, LED,
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nWE, nWE80, nEN80, nC07X,
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Ain, Din, Dout, nDOE, Vout, nVOE,
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CKEout, nCSout, nRASout, nCASout, nRWEout,
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BA, RAout, DQML, DQMH, RD);
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/* Clocks */
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input C14M, PHI1;
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/* Control inputs */
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input nWE, nWE80, nEN80, nC07X;
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/* Activity LED */
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reg LEDEN = 0;
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output LED; assign LED = !(!nEN80 && LEDEN && Ready);
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/* Address Bus */
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input [7:0] Ain; // Multiplexed DRAM address input
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/* 6502 Data Bus */
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input [7:0] Din; // 6502 data bus inputs
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reg DOEEN;
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always @(posedge C14M) begin
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DOEEN <= /*(S==4'h8) || (S==4'h9) || (S==4'hA) ||*/ (S==4'hB) ||
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(S==4'hC) || (S==4'hD) || (S==4'hE) || (S==4'hF);
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end
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output nDOE; assign nDOE = !(!nEN80 && nWE && DOEEN);
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output [7:0] Dout; assign Dout[7:0] = RD[7:0];
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/* Video Data Bus */
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reg VOEEN;
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always @(posedge C14M) begin
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VOEEN <= (S==4'h7) ||
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(S==4'h8) || (S==4'h9) || (S==4'hA) || (S==4'hB) ||
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(S==4'hC) || (S==4'hD) || (S==4'hE) || (S==4'hF);
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end
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output nVOE; assign nVOE = !(!PHI1 && VOEEN);
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output reg [7:0] Vout; // Video data bus
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always @(posedge C14M) if (S==4'h6) Vout[7:0] <= RD[7:0];
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/* SDRAM */
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reg CKE = 1;
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//reg nCS = 1;
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reg nRAS = 1, nCAS = 1, nRWE = 1;
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output reg [1:0] BA;
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reg [11:0] RA;
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output reg DQML = 1, DQMH = 1;
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inout [7:0] RD;
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assign RD[7:0] = Ready ? (!nWE80 ? Din[7:0] : 8'bZ) : 8'h00;
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/* SDRAM falling edge outputs */
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output reg CKEout;
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output nCSout; assign nCSout = 0;
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output reg nRASout = 1, nCASout = 1, nRWEout = 1;
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output reg [11:0] RAout;
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always @(negedge C14M) begin
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CKEout <= CKE;
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nRASout <= nRAS;
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nCASout <= nCAS;
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nRWEout <= nRWE;
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RAout <= RA;
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end
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/* RAMWorks Bank Register and Capacity Mask */
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reg [7:0] RWBank = 0; // RAMWorks bank register
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reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask
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reg RWSel = 0; // RAMWorks bank register select
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always @(posedge C14M) begin
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if (S==4'h9) RWSel <= RA[0] && !RA[3] && !nWE && !nC07X;
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end
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reg CmdRWMaskSet = 0; // RAMWorks Mask register set flag
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// Causes RWBank to be zeroed next RWSel access
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reg CmdSetRWBankFFChip = 0;
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reg CmdSetRWBankFFLED = 0;
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reg CmdLEDSet = 0;
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reg CmdLEDGet = 0;
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/* Command Sequence Detector */
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reg [2:0] CS = 0; // Command sequence state
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reg [2:0] CmdTout = 0; // Command sequence timeout
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/* UFM Interface */
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reg wb_rst;
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reg wb_cyc_stb;
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reg wb_req;
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reg wb_we;
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reg [7:0] wb_adr;
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reg [7:0] wb_dati;
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wire wb_ack;
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wire [7:0] wb_dato;
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wire ufm_irq;
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REFB ufmefb(
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.wb_clk_i(C14M),
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.wb_rst_i(wb_rst),
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.wb_cyc_i(wb_cyc_stb),
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.wb_stb_i(wb_cyc_stb),
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.wb_we_i(wb_we),
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.wb_adr_i(wb_adr),
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.wb_dat_i(wb_dati),
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.wb_dat_o(wb_dato),
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.wb_ack_o(wb_ack),
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.wbc_ufm_irq(ufm_irq));
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/* User Command Triggers */
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//reg CmdBitbangMAX = 0; // Set by user command. Loads UFM outputs next RWSel
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//reg CmdBitbangSPI = 0;
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reg CmdBitbangMXO2 = 0;
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reg CmdExecMXO2 = 0;
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//reg CmdPrgmMAX = 0; // Set by user command. Programs UFM
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//reg CmdEraseMAX = 0; // Set by user command. Erases UFM
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/* State Counters */
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reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
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reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15
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reg [15:0] FS = 0; // Fast state counter
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wire RefReq = FS[5:4]==0; // Refresh request based on fast state counter
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reg [3:0] S = 0; // IIe State counter
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/* State Counters */
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always @(posedge C14M) begin
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// Increment fast state counter
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FS <= FS+16'h0001;
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// Synchronize Apple state counter to S1 when just entering PHI1
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PHI1reg <= PHI1; // Save old PHI1
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S <= (PHI1 && !PHI1reg && Ready) ? 4'h1 :
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(S==4'h0) ? 4'h0 :
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(S==4'hF) ? 4'hF : S+4'h1;
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// Begin normal operation after 64k init cycles (~4.59ms)
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if (FS[15:0]==16'hFFFF) Ready <= 1'b1;
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end
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/* Command sequence control */
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always @(posedge C14M) begin
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if (S==4'hC) begin
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if (RWSel) begin
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CmdTout <= 0; // Reset command timeout if RWSel accessed
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// Recognize command sequence and advance CS state
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if ((CS==3'h0 && Din[7:0]==8'hFF) ||
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(CS==3'h1 && Din[7:0]==8'h00) ||
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(CS==3'h2 && Din[7:0]==8'h55) ||
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(CS==3'h3 && Din[7:0]==8'hAA) ||
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(CS==3'h4 && Din[7:0]==8'hC1) ||
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(CS==3'h5 && Din[7:0]==8'hAD) ||
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CS==3'h6 || CS==3'h7) CS <= CS+3'h1;
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else CS <= 0; // Back to beginning if it's not right
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end else begin
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CmdTout <= CmdTout+3'h1; // Increment command timeout
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// If command sequence times out, reset sequence state
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if (CmdTout==3'h7) CS <= 0;
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end
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end
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end
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/* UFM Control */
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always @(posedge C14M) begin
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if (S==4'h0) begin
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if (FS[15:14]==2'b00) wb_rst <= 1'b1;
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else if (FS[15:14]==2'b01) wb_rst <= 1'b0;
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else if (FS[15:14]==2'b10) begin
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wb_rst <= 1'b0;
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if (wb_ack || (FS[7:0]==0)) wb_cyc_stb <= 0;
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else if ((FS[7:0]==1) && wb_req) wb_cyc_stb <= 1;
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case (FS[13:8])
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0: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 1: begin // Enable configuration interface - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h74;
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wb_req <= 1;
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end 2: begin // Enable configuration interface - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h08;
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wb_req <= 1;
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end 3: begin // Enable configuration interface - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 4: begin // Enable configuration interface - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 5: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 6: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 7: begin // Poll status register - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h3C;
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wb_req <= 1;
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end 8: begin // Poll status register - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 9: begin // Poll status register - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 10: begin // Poll status register - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 11, 12, 13, 14: begin // Read status register 1-4
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h3C;
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wb_req <= 1;
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end 15: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 16: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 17: begin // Set UFM address - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'hB4;
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wb_req <= 1;
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end 18: begin // Set UFM address - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 19: begin // Set UFM address - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 20: begin // Set UFM address - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 21: begin // Set UFM address - data 1/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h40;
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wb_req <= 1;
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end 22: begin // Set UFM address - data 2/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 23: begin // Set UFM address - data 3/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 24: begin // Set UFM address - data 4/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 190;
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wb_req <= 1;
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end 25: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 26: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 27: begin // Read UFM page - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'hCA;
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wb_req <= 1;
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end 28: begin // Read UFM page - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h10;
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wb_req <= 1;
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end 29: begin // Read UFM page - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 30: begin // Read UFM page - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h01;
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wb_req <= 1;
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end 31: begin // Read UFM page - data 0
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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if (wb_ack) RWMask[7:0] <= wb_dato[7:0];
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end 32: begin // Read UFM page - data 1
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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if (wb_ack) LEDEN <= wb_dato[0];
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end 33, 34,
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35, 36, 37, 38,
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39, 40, 41, 42,
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43, 44, 45, 46: begin // Read UFM page - data 2-15
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 47: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 48: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 49: begin // Disable configuration interface - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h26;
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wb_req <= 1;
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end 50: begin // Disable configuration interface - operand 1/2
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 51: begin // Disable configuration interface - operand 2/2
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 52: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 53: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 54: begin // Bypass - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'hFF;
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wb_req <= 1;
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end 55: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end default: begin
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 0;
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end
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endcase
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end else begin
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wb_rst <= 1'b0;
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wb_cyc_stb <= 1'b0;
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wb_req <= 1'b0;
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h00;
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wb_dati[7:0] <= 8'h00;
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end
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end else begin
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// UFM bitbang control
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wb_rst <= 1'b0;
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wb_req <= 1'b0;
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if (RWSel && S==4'hC) begin
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// LED control
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if (CmdLEDSet) LEDEN <= Din[0];
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// Set capacity mask
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if (CmdRWMaskSet) RWMask[7:0] <= {Din[7], ~Din[6:0]};
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// Set EFB address
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if (CmdBitbangMXO2) begin
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wb_adr[7:0] <= Din[7:0];
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wb_dati[7:0] <= wb_adr[7:0];
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end
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// Excecute EFB R/W cycle
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if (CmdExecMXO2) begin
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wb_we <= Din[0];
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wb_cyc_stb <= 1;
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end else if (wb_ack) wb_cyc_stb <= 0;
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end
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end
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end
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/* RAMWorks register control - bank, LED, etc. */
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always @(posedge C14M) begin
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if (S==4'hC && RWSel) begin
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// Latch RAMWorks bank if accessed
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if ((CmdSetRWBankFFLED) ||
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(CmdSetRWBankFFChip) ||
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(CmdLEDGet && LEDEN)) RWBank <= 8'hFF;
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else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]};
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if (CS==3'h6) begin // Recognize and submit command in CS6
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// Board has LED detect command
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CmdSetRWBankFFLED <= Din[7:0]==8'hF0;
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// Volatile commands
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CmdRWMaskSet <= Din[7:0]==8'hE0;
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CmdLEDSet <= Din[7:0]==8'hE2;
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CmdLEDGet <= Din[7:0]==8'hE3;
|
|
end else begin // Reset command triggers
|
|
CmdSetRWBankFFLED <= 0;
|
|
CmdRWMaskSet <= 0;
|
|
CmdLEDSet <= 0;
|
|
CmdLEDGet <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
|
/* RAMWorks register control - Lattice MachXO2 */
|
|
always @(posedge C14M) begin
|
|
if (S==4'hC && RWSel) begin
|
|
if (CS==3'h6) begin // Recognize and submit command in CS6
|
|
// Chip detection commands
|
|
//CmdSetRWBankFFChip <= Din[7:0]==8'hFF; // MAX
|
|
//CmdSetRWBankFFChip <= Din[7:0]==8'hFE; // SPI
|
|
CmdSetRWBankFFChip <= Din[7:0]==8'hFD; // MachXO2
|
|
|
|
// Altera MAX II/V commands
|
|
//CmdBitbangMAX <= Din[7:0]==8'hEA;
|
|
//if (!CmdEraseMAX && !CmdPrgmMAX) begin
|
|
// if (Din[7:0]==8'hEE) CmdEraseMAX <= 1;
|
|
// if (Din[7:0]==8'hEF) CmdPrgmMAX <= 1;
|
|
//end
|
|
|
|
// SPI commands
|
|
//CmdBitbangSPI <= Din[7:0]==8'hEB;
|
|
|
|
// MachXO2 commands
|
|
CmdBitbangMXO2 <= Din[7:0]==8'hEC;
|
|
CmdExecMXO2 <= Din[7:0]==8'hED;
|
|
end else begin // Reset command triggers
|
|
CmdSetRWBankFFChip <= 0;
|
|
//CmdBitbangMAX <= 0;
|
|
//CmdBitbangSPI <= 0;
|
|
CmdBitbangMXO2 <= 0;
|
|
CmdExecMXO2 <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
/* SDRAM Control */
|
|
always @(posedge C14M) case (S)
|
|
4'h0: begin
|
|
CKE <= 1'b1;
|
|
if (!FS[15] || FS[0]) begin
|
|
// NOP
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end else case (FS[4:1])
|
|
4'h0: begin
|
|
// PC all
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b0;
|
|
end 4'h1: begin
|
|
// LDM
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b0;
|
|
nRWE <= 1'b0;
|
|
end 4'h2: begin
|
|
// NOP
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end 4'h3, 4'h4, 4'h5, 4'h6,
|
|
4'h7, 4'h8, 4'h9, 4'hA: begin
|
|
// AREF
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b0;
|
|
nRWE <= 1'b1;
|
|
end 4'hB: begin
|
|
// ACT
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end 4'hC, 4'hD: begin
|
|
// WR
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b0;
|
|
nRWE <= 1'b0;
|
|
end 4'hE: begin
|
|
// NOP
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end 4'hF: begin
|
|
// PC all
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b0;
|
|
end
|
|
endcase
|
|
case (FS[4:3])
|
|
2'b00, 2'b01: begin
|
|
// Mode register contents
|
|
BA[1:0] <= 2'b00; // Reserved
|
|
RA[11] <= 1'b0; // Reserved
|
|
RA[10] <= !FS[1]; // reserved / "all"
|
|
RA[9] <= 1'b1; // "1" for single write mode
|
|
RA[8] <= 1'b0; // Reserved
|
|
RA[7] <= 1'b0; // "0" for not test mode
|
|
RA[6:4] <= 3'b010; // "2" for CAS latency 2
|
|
RA[3] <= 1'b0; // "0" for sequential burst (not used)
|
|
RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
|
|
end 2'b10: begin
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'h0;
|
|
RA[7:0] <= FS[14:7];
|
|
end 2'b11: begin
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:3] <= 9'h000;
|
|
RA[2:1] <= FS[6:5];
|
|
RA[0] <= FS[1];
|
|
end
|
|
endcase
|
|
DQML <= !FS[15];
|
|
DQMH <= !FS[15];
|
|
end 4'h1: begin
|
|
// NOP CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
// Hold RA[7:0]
|
|
DQML <= 1'b0;
|
|
DQMH <= 1'b1;
|
|
end 4'h2: begin
|
|
// ACT CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
// Hold BA
|
|
// Hold RA
|
|
// Hold DQMs
|
|
end 4'h3: begin
|
|
// RD CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b0;
|
|
nRWE <= 1'b1;
|
|
// Hold BA
|
|
// Hold RA[11:8]
|
|
RA[7:0] <= Ain[7:0];
|
|
// Hold DQMs
|
|
end 4'h4: begin
|
|
// PC all CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b0;
|
|
// Hold BA
|
|
// Hold RA[11]
|
|
RA[10] <= 1'b1; // "all"
|
|
// Hold RA[9:0]
|
|
// Hold DQMs
|
|
end 4'h5: begin
|
|
if (RefReq) begin
|
|
// AREF CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b0;
|
|
nRWE <= 1'b1;
|
|
end else begin
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end
|
|
// Hold BA
|
|
// Hold RA
|
|
// Hold DQMs
|
|
end 4'h6: begin
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
// Hold BA
|
|
// Hold RA
|
|
// Hold DQMs
|
|
end 4'h7: begin
|
|
// Can't check EN80 at this time
|
|
if (nWE) begin // Read / idle
|
|
// NOP CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end else begin // Write / idle
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end
|
|
BA[1:0] <= RWBank[6:5];
|
|
RA[11:8] <= RWBank[4:1];
|
|
RA[7:0] <= Ain[7:0];
|
|
// Hold DQMs
|
|
end 4'h8: begin
|
|
if (nEN80) begin // Idle
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end else if (nWE) begin // Read
|
|
// ACT CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end else begin // Write
|
|
// NOP CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end
|
|
// Hold BA
|
|
// Hold RA
|
|
// Hold DQMs
|
|
end 4'h9: begin
|
|
if (nEN80) begin // Idle
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end else if (nWE) begin // Read
|
|
// RD CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b0;
|
|
nRWE <= 1'b1;
|
|
end else begin // Write
|
|
// ACT CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end
|
|
// Hold BA
|
|
RA[11:9] <= 3'b000; // no auto-precharge
|
|
RA[8] <= RWBank[7];
|
|
RA[7:0] <= Ain[7:0];
|
|
DQMH <= !RWBank[0];
|
|
DQMH <= RWBank[0];
|
|
end 4'hA: begin
|
|
if (nEN80) begin // Idle
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
// Hold RA[10]
|
|
end else if (nWE) begin // Read
|
|
// PC all CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b0;
|
|
RA[10] <= 1'b1;
|
|
end else begin // Write
|
|
// WR CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b0;
|
|
nRWE <= 1'b0;
|
|
RA[10] <= 1'b0;
|
|
end
|
|
// Hold BA
|
|
// Hold RA[11,9:0]
|
|
// Hold DQMs
|
|
end 4'hB: begin
|
|
if (nEN80) begin // Idle
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end else if (nWE) begin // Read
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end else begin // Write
|
|
// NOP CKE
|
|
CKE <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end
|
|
// Hold BA
|
|
// Hold RA[11:0]
|
|
// Hold DQMs
|
|
end 4'hC: begin
|
|
if (nEN80) begin // Idle
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
// Hold RA[10]
|
|
end else if (nWE) begin // Read
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
// Hold RA[10]
|
|
end else begin // Write
|
|
// PC all CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b0;
|
|
RA[10] <= 1'b1; // "all"
|
|
end
|
|
// Hold BA
|
|
// Hold RA[11,9:0]
|
|
// Hold RA[7:0]
|
|
// Hold DQMs
|
|
end 4'hD: begin
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
// Hold BA
|
|
// Hold RA[11:0]
|
|
// Hold DQMs
|
|
end 4'hE, 4'hF: begin
|
|
// NOP CKD
|
|
CKE <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
// Hold BA
|
|
// Hold RA[11:8]
|
|
RA[7:0] <= Ain[7:0]; // Latch row address for next video read
|
|
// Hold DQMs
|
|
end
|
|
endcase
|
|
endmodule
|