Apple-2-HW/RAM2E
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RAM2E/cpld_maxv/db/RAM2E.hier_info
Zane Kaminski 3fcf6a1bb2 Added MAX V CPLD firmware
2021-03-10 21:14:12 -05:00

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|RAM2E
C14M => CmdTout[0].CLK
C14M => CmdTout[1].CLK
C14M => CmdTout[2].CLK
C14M => RWMaskSet.CLK
C14M => UFMBitbang.CLK
C14M => UFMEraseEN.CLK
C14M => UFMPrgmEN.CLK
C14M => SetRWBankFF.CLK
C14M => CS[0].CLK
C14M => CS[1].CLK
C14M => CS[2].CLK
C14M => RWBank[0].CLK
C14M => RWBank[1].CLK
C14M => RWBank[2].CLK
C14M => RWBank[3].CLK
C14M => RWBank[4].CLK
C14M => RWBank[5].CLK
C14M => RWBank[6].CLK
C14M => RWBank[7].CLK
C14M => RWSel.CLK
C14M => Ready.CLK
C14M => DOEEN.CLK
C14M => DQMH~reg0.CLK
C14M => DQML~reg0.CLK
C14M => BA[0]~reg0.CLK
C14M => BA[1]~reg0.CLK
C14M => CKE~reg0.CLK
C14M => RA[0]~reg0.CLK
C14M => RA[1]~reg0.CLK
C14M => RA[2]~reg0.CLK
C14M => RA[3]~reg0.CLK
C14M => RA[4]~reg0.CLK
C14M => RA[5]~reg0.CLK
C14M => RA[6]~reg0.CLK
C14M => RA[7]~reg0.CLK
C14M => RA[8]~reg0.CLK
C14M => RA[9]~reg0.CLK
C14M => RA[10]~reg0.CLK
C14M => RA[11]~reg0.CLK
C14M => nRWE~reg0.CLK
C14M => nCAS~reg0.CLK
C14M => nRAS~reg0.CLK
C14M => nCS~reg0.CLK
C14M => DRCLKPulse.CLK
C14M => UFMProgram.CLK
C14M => UFMErase.CLK
C14M => UFMReqErase.CLK
C14M => RWMask[0].CLK
C14M => RWMask[1].CLK
C14M => RWMask[2].CLK
C14M => RWMask[3].CLK
C14M => RWMask[4].CLK
C14M => RWMask[5].CLK
C14M => RWMask[6].CLK
C14M => RWMask[7].CLK
C14M => UFMInitDone.CLK
C14M => UFMD[8].CLK
C14M => UFMD[9].CLK
C14M => UFMD[10].CLK
C14M => UFMD[11].CLK
C14M => UFMD[12].CLK
C14M => UFMD[13].CLK
C14M => UFMD[14].CLK
C14M => DRShift.CLK
C14M => DRDIn.CLK
C14M => ARShift.CLK
C14M => DRCLK.CLK
C14M => ARCLK.CLK
C14M => RTPBusyReg.CLK
C14M => UFMBusyReg.CLK
C14M => S[0].CLK
C14M => S[1].CLK
C14M => S[2].CLK
C14M => S[3].CLK
C14M => PHI1reg.CLK
C14M => FS[0].CLK
C14M => FS[1].CLK
C14M => FS[2].CLK
C14M => FS[3].CLK
C14M => FS[4].CLK
C14M => FS[5].CLK
C14M => FS[6].CLK
C14M => FS[7].CLK
C14M => FS[8].CLK
C14M => FS[9].CLK
C14M => FS[10].CLK
C14M => FS[11].CLK
C14M => FS[12].CLK
C14M => FS[13].CLK
C14M => FS[14].CLK
C14M => FS[15].CLK
C14M => Dout[0]~reg0.CLK
C14M => Dout[1]~reg0.CLK
C14M => Dout[2]~reg0.CLK
C14M => Dout[3]~reg0.CLK
C14M => Dout[4]~reg0.CLK
C14M => Dout[5]~reg0.CLK
C14M => Dout[6]~reg0.CLK
C14M => Dout[7]~reg0.CLK
C14M => Vout[0]~reg0.CLK
C14M => Vout[1]~reg0.CLK
C14M => Vout[2]~reg0.CLK
C14M => Vout[3]~reg0.CLK
C14M => Vout[4]~reg0.CLK
C14M => Vout[5]~reg0.CLK
C14M => Vout[6]~reg0.CLK
C14M => Vout[7]~reg0.CLK
PHI1 => S.IN1
PHI1 => PHI1reg.DATAIN
PHI1 => nVOE.DATAIN
nWE => comb.IN0
nWE => RWSel.IN1
nWE80 => nRWE.DATAB
nWE80 => RDOE.IN0
nEN80 => nCS.DATAB
nEN80 => nCS.DATAB
nEN80 => comb.IN1
nEN80 => RDOE.IN1
nEN80 => CKE.DATAB
nEN80 => CKE.DATAB
nEN80 => CKE.DATAB
nC07X => RWSel.IN1
Ain[0] => RA.DATAB
Ain[0] => RA.DATAB
Ain[0] => RA.DATAB
Ain[0] => RA.DATAB
Ain[0] => RA.DATAB
Ain[1] => RA.DATAB
Ain[1] => RA.DATAB
Ain[1] => RA.DATAB
Ain[1] => RA.DATAB
Ain[1] => RA.DATAB
Ain[2] => RA.DATAB
Ain[2] => RA.DATAB
Ain[2] => RA.DATAB
Ain[2] => RA.DATAB
Ain[2] => RA.DATAB
Ain[3] => RA.DATAB
Ain[3] => RA.DATAB
Ain[3] => RA.DATAB
Ain[3] => RA.DATAB
Ain[3] => RA.DATAB
Ain[4] => RA.DATAB
Ain[4] => RA.DATAB
Ain[4] => RA.DATAB
Ain[4] => RA.DATAB
Ain[4] => RA.DATAB
Ain[5] => RA.DATAB
Ain[5] => RA.DATAB
Ain[5] => RA.DATAB
Ain[5] => RA.DATAB
Ain[5] => RA.DATAB
Ain[6] => RA.DATAB
Ain[6] => RA.DATAB
Ain[6] => RA.DATAB
Ain[6] => RA.DATAB
Ain[6] => RA.DATAB
Ain[7] => RA.DATAB
Ain[7] => RA.DATAB
Ain[7] => RA.DATAB
Ain[7] => RA.DATAB
Ain[7] => RA.DATAB
Din[0] => RWBank.IN1
Din[0] => RD[0].DATAIN
Din[0] => RWMask.DATAB
Din[0] => Equal29.IN7
Din[0] => Equal31.IN3
Din[0] => Equal33.IN7
Din[0] => Equal35.IN2
Din[0] => Equal37.IN4
Din[0] => Equal39.IN7
Din[0] => Equal40.IN6
Din[0] => Equal41.IN7
Din[0] => Equal42.IN7
Din[0] => Equal43.IN7
Din[1] => RWBank.IN1
Din[1] => RD[1].DATAIN
Din[1] => RWMask.DATAB
Din[1] => Equal29.IN6
Din[1] => Equal31.IN7
Din[1] => Equal33.IN3
Din[1] => Equal35.IN7
Din[1] => Equal37.IN7
Din[1] => Equal39.IN6
Din[1] => Equal40.IN5
Din[1] => Equal41.IN5
Din[1] => Equal42.IN4
Din[1] => Equal43.IN6
Din[2] => RWBank.IN1
Din[2] => RD[2].DATAIN
Din[2] => RWMask.DATAB
Din[2] => Equal29.IN5
Din[2] => Equal31.IN2
Din[2] => Equal33.IN6
Din[2] => Equal35.IN6
Din[2] => Equal37.IN3
Din[2] => Equal39.IN5
Din[2] => Equal40.IN4
Din[2] => Equal41.IN4
Din[2] => Equal42.IN6
Din[2] => Equal43.IN5
Din[3] => RWBank.IN1
Din[3] => RD[3].DATAIN
Din[3] => RWMask.DATAB
Din[3] => Equal29.IN4
Din[3] => Equal31.IN6
Din[3] => Equal33.IN2
Din[3] => Equal35.IN5
Din[3] => Equal37.IN2
Din[3] => Equal39.IN4
Din[3] => Equal40.IN3
Din[3] => Equal41.IN3
Din[3] => Equal42.IN3
Din[3] => Equal43.IN4
Din[4] => RWBank.IN1
Din[4] => RD[4].DATAIN
Din[4] => RWMask.DATAB
Din[4] => Equal29.IN3
Din[4] => Equal31.IN1
Din[4] => Equal33.IN5
Din[4] => Equal35.IN4
Din[4] => Equal37.IN6
Din[4] => Equal39.IN3
Din[4] => Equal40.IN7
Din[4] => Equal41.IN6
Din[4] => Equal42.IN5
Din[4] => Equal43.IN3
Din[5] => RWBank.IN1
Din[5] => RD[5].DATAIN
Din[5] => RWMask.DATAB
Din[5] => Equal29.IN2
Din[5] => Equal31.IN5
Din[5] => Equal33.IN1
Din[5] => Equal35.IN3
Din[5] => Equal37.IN1
Din[5] => Equal39.IN2
Din[5] => Equal40.IN2
Din[5] => Equal41.IN2
Din[5] => Equal42.IN2
Din[5] => Equal43.IN2
Din[6] => DRDIn.DATAB
Din[6] => RWBank.IN1
Din[6] => RD[6].DATAIN
Din[6] => RWMask.DATAB
Din[6] => Equal29.IN1
Din[6] => Equal31.IN0
Din[6] => Equal33.IN4
Din[6] => Equal35.IN1
Din[6] => Equal37.IN5
Din[6] => Equal39.IN1
Din[6] => Equal40.IN1
Din[6] => Equal41.IN1
Din[6] => Equal42.IN1
Din[6] => Equal43.IN1
Din[7] => DRCLKPulse.DATAB
Din[7] => RWMask.DATAB
Din[7] => RWBank.IN1
Din[7] => RD[7].DATAIN
Din[7] => Equal29.IN0
Din[7] => Equal31.IN4
Din[7] => Equal33.IN0
Din[7] => Equal35.IN0
Din[7] => Equal37.IN0
Din[7] => Equal39.IN0
Din[7] => Equal40.IN0
Din[7] => Equal41.IN0
Din[7] => Equal42.IN0
Din[7] => Equal43.IN0
Dout[0] <= Dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[1] <= Dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[2] <= Dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[3] <= Dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[4] <= Dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[5] <= Dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[6] <= Dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[7] <= Dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
nDOE <= comb.DB_MAX_OUTPUT_PORT_TYPE
Vout[0] <= Vout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Vout[1] <= Vout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Vout[2] <= Vout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Vout[3] <= Vout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Vout[4] <= Vout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Vout[5] <= Vout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Vout[6] <= Vout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Vout[7] <= Vout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
nVOE <= PHI1.DB_MAX_OUTPUT_PORT_TYPE
CKE <= CKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
nCS <= nCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
BA[0] <= BA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
BA[1] <= BA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[0] <= RA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[1] <= RA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[2] <= RA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[3] <= RA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[4] <= RA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[5] <= RA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[6] <= RA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[7] <= RA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[8] <= RA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[9] <= RA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[10] <= RA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[11] <= RA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[0] <> RD[0]
RD[1] <> RD[1]
RD[2] <> RD[2]
RD[3] <> RD[3]
RD[4] <> RD[4]
RD[5] <> RD[5]
RD[6] <> RD[6]
RD[7] <> RD[7]
DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
|RAM2E|UFM:UFM_inst
arclk => arclk.IN1
ardin => ardin.IN1
arshft => arshft.IN1
drclk => drclk.IN1
drdin => drdin.IN1
drshft => drshft.IN1
erase => erase.IN1
oscena => oscena.IN1
program => program.IN1
busy <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.busy
drdout <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.drdout
osc <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.osc
rtpbusy <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.rtpbusy
|RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component
arclk => maxii_ufm_block1.ARCLK
ardin => maxii_ufm_block1.ARDIN
arshft => maxii_ufm_block1.ARSHFT
busy <= maxii_ufm_block1.BUSY
drclk => maxii_ufm_block1.DRCLK
drdin => maxii_ufm_block1.DRDIN
drdout <= maxii_ufm_block1.DRDOUT
drshft => maxii_ufm_block1.DRSHFT
erase => maxii_ufm_block1.ERASE
osc <= maxii_ufm_block1.OSC
oscena => maxii_ufm_block1.OSCENA
program => maxii_ufm_block1.PROGRAM
rtpbusy <= maxii_ufm_block1.BGPBUSY
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