637 lines
16 KiB
Verilog
637 lines
16 KiB
Verilog
module RAM2E(C14M, PHI1,
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nWE, nWE80, nEN80, nC07X,
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Ain, Din, Dout, nDOE, Vout, nVOE,
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CKE, nCS, nRAS, nCAS, nRWE,
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BA, RA, RD, DQML, DQMH);
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/* Clocks */
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input C14M, PHI1;
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/* Control inputs */
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input nWE, nWE80, nEN80, nC07X;
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/* Delay for EN80 signal */
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//output DelayOut = 1'b0;
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//input DelayIn;
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wire EN80 = ~nEN80;
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/* Address Bus */
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input [7:0] Ain; // Multiplexed DRAM address input
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/* 6502 Data Bus */
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input [7:0] Din; // 6502 data bus inputs
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reg DOEEN = 0; // 6502 data bus output enable from state machine
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output nDOE = ~(EN80 & nWE & DOEEN); // 6502 data bus output enable
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output reg [7:0] Dout; // 6502 data Bus output
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/* Video Data Bus */
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output nVOE = ~(~PHI1); /// Video data bus output enable
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output reg [7:0] Vout; // Video data bus
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/* SDRAM */
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output reg CKE = 0;
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output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1;
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output reg [1:0] BA;
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output reg [11:0] RA;
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output reg DQML = 1, DQMH = 1;
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wire RDOE = EN80 & ~nWE80;
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inout [7:0] RD = RDOE ? Din[7:0] : 8'bZ;
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/* RAMWorks Bank Register and Capacity Mask */
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reg [7:0] RWBank = 0; // RAMWorks bank register
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reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask
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reg RWSel = 0; // RAMWorks bank register select
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reg RWMaskSet = 0; // RAMWorks Mask register set flag
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reg SetRWBankFF = 0; // Causes RWBank to be zeroed next RWSel access
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/* Command Sequence Detector */
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reg [2:0] CS = 0; // Command sequence state
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reg [2:0] CmdTout = 0; // Command sequence timeout
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/* UFM Interface */
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reg [15:8] UFMD = 0; // *Parallel* UFM data register
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reg ARCLK = 0; // UFM address register clock
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// UFM address register data input tied to 0
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reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
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reg DRCLK = 0; // UFM data register clock
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reg DRDIn = 0; // UFM data register input
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reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
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reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
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reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
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wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
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wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
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wire DRDOut; // UFM data output
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// UFM oscillator always enabled
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wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
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UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
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.arclk (ARCLK),
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.ardin (1'b0),
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.arshft (ARShift),
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.drclk (DRCLK),
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.drdin (DRDIn),
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.drshft (DRShift),
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.erase (UFMErase),
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.oscena (1'b1),
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.program (UFMProgram),
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.busy (UFMBusy),
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.drdout (DRDOut),
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.osc (UFMOsc),
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.rtpbusy (RTPBusy));
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reg UFMBusyReg = 0; // UFMBusy registered to sync with C14M
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reg RTPBusyReg = 0; // RTPBusy registered to sync with C14M
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/* UFM State & User Command Triggers */
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reg UFMInitDone = 0; // 1 if UFM initialization finished
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reg UFMReqErase = 0; // 1 if UFM requires erase
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reg UFMBitbang = 0; // Set by user command. Loads UFM outputs next RWSel
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reg UFMPrgmEN = 0; // Set by user command. Programs UFM
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reg UFMEraseEN = 0; // Set by user command. Erases UFM
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reg DRCLKPulse = 0; // Set by user command. Causes DRCLK pulse next C14M
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/* State Counters */
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reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
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reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15
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reg [15:0] FS = 0; // Fast state counter
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reg [3:0] S = 0; // IIe State counter
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/* State Counters */
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always @(posedge C14M) begin
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// Increment fast state counter
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FS <= FS+1;
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// Synchronize Apple state counter to S1 when just entering PHI1
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PHI1reg <= PHI1; // Save old PHI1
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S <= (PHI1 & ~PHI1reg & Ready) ? 4'h1 :
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S==4'h0 ? 4'h0 :
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S==4'hF ? 4'hF : S+1;
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end
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/* UFM Control */
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always @(posedge C14M) begin
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// Synchronize asynchronous UFM signals
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UFMBusyReg <= UFMBusy;
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RTPBusyReg <= RTPBusy;
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if (S==4'h0) begin
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if ((FS[15:13]==3'b101) | (FS[15:13]==3'b111 & UFMReqErase)) begin
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// In states AXXX-BXXX and also EXXX-FXXX if erase/wrap req'd
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// shift in 0's to address register
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ARCLK <= FS[0]; // Clock address register
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DRCLK <= 1'b0; // Don't clock data register
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ARShift <= 1'b1; // Shift address registers
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DRDIn <= 1'b0; // Don't care DRDIn
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DRShift <= 1'b0; // Don't care DRDShift
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end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4:1]==4'h4) begin
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// In states CXXX-DXXX (substep 4)
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// Xfer to data reg (repeat 256x 1x)
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ARCLK <= 1'b0; // Don't clock address register
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DRCLK <= FS[0]; // Clock data register
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ARShift <= 1'b0; // Don't care ARShift
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DRDIn <= 1'b0; // Don't care DRDIn
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DRShift <= 1'b0; // Don't care DRShift
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end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4]==1'b1) begin
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// In states CXXX-DXXX (substeps 8-F)
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// Save UFM D15-8, shift out D14-7 (repeat 256x 8x)
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DRCLK <= FS[0]; // Clock data register
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ARShift <= 1'b0; // ARShift is 0 because we want to increment
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DRDIn <= 1'b0; // Don't care what to shift into data register
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DRShift <= 1'b1; // Shift data register
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// Shift into UFMD
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if (FS[0]) UFMD[15:8] <= {UFMD[14:8], DRDOut};
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// Compare and store mask
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if (FS[4:1]==4'hF) begin
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ARCLK <= FS[0]; // Clock address register to increment
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// If byte is erased (0xFF, i.e. all 1's, is erased)...
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if (UFMD[14:8]==7'b1111111 & DRDOut==1'b1) begin
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// Current UFM address is where we want to store
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UFMInitDone <= 1'b1; // Quit iterating
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// Otherwise byte is valid setting (i.e. some bit is 0)...
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end else begin
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// Set RWMask, but if saved mask is 0x80, store ~0xFF
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if (UFMD[14:8]==7'b1000000 & DRDOut==1'b0) begin
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RWMask[7:0] <= {1'b1, ~7'h7F};
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end else RWMask[7:0] <= {UFMD[14], ~UFMD[13:8], ~DRDOut};
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// If last byte in sector...
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if (FS[12:5]==8'hFF) begin
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UFMReqErase <= 1'b1; // Mark need to erase
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end
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end
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end else ARCLK <= 1'b0; // Don't clock address register
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end else begin
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ARCLK <= 1'b0;
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DRCLK <= 1'b0;
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ARShift <= 1'b0;
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DRDIn <= 1'b0;
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DRShift <= 1'b0;
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end
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// Don't erase or program UFM during initialization
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UFMErase <= 1'b0;
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UFMProgram <= 1'b0;
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// Keep DRCLK pulse control disabled during init
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DRCLKPulse <= 1'b0;
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end else begin
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// Can only shift UFM data register now
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ARCLK <= 1'b0;
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ARShift <= 1'b0;
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DRShift <= 1'b1;
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// UFM bitbang control
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if (UFMBitbang & CS==3'h7 & RWSel & S==4'hC) begin
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DRDIn <= Din[6];
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DRCLKPulse <= Din[7];
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DRCLK <= 1'b0;
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end else begin
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DRCLKPulse <= 1'b0;
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DRCLK <= DRCLKPulse;
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end
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// Set capacity mask
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if (RWMaskSet & RWSel & S==4'hC) RWMask[7:0] <= {Din[7], ~Din[6:0]};
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// UFM programming sequence
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if (UFMPrgmEN | UFMEraseEN) begin
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if (~UFMBusyReg & ~RTPBusyReg) begin
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if (UFMReqErase | UFMEraseEN) UFMErase <= 1'b1;
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else if (UFMPrgmEN) UFMProgram <= 1'b1;
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end else if (UFMBusyReg) UFMReqErase <= 1'b0;
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end
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end
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end
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/* SDRAM Control */
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always @(posedge C14M) begin
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if (S==4'h0) begin
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// SDRAM initialization
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if (FS[15:0]==16'hFFC0) begin
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// Precharge All
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nCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nRWE <= 1'b0;
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RA[10] <= 1'b1; // "all"
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end else if (FS[15:4]==16'hFFD & FS[0]==1'b0) begin // Repeat 8x
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// Auto-refresh
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nCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nRWE <= 1'b1;
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RA[10] <= 1'b0;
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end else if (FS[15:0]==16'hFFE8) begin
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// Set Mode Register
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nCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nRWE <= 1'b0;
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RA[10] <= 1'b0; // Reserved in mode register
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end else if (FS[15:4]==12'hFFF & FS[0]==1'b0) begin // Repeat 8x
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// Auto-refresh
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nCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nRWE <= 1'b1;
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RA[10] <= 1'b0;
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end else begin // Otherwise send no-op
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// NOP
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nCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nRWE <= 1'b1;
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RA[10] <= 1'b0;
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end
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// Enable SDRAM clock after 65,280 cycles (~4.56ms)
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CKE <= FS[15:8] == 8'hFF;
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// Mode register contents
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BA[1:0] <= 2'b00; // Reserved
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RA[11] <= 1'b0; // Reserved
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// RA[10] set above ^
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RA[9] <= 1'b1; // "1" for single write mode
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RA[8] <= 1'b0; // Reserved
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RA[7] <= 1'b0; // "0" for not test mode
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RA[6:4] <= 3'b010; // "2" for CAS latency 2
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RA[3] <= 1'b0; // "0" for sequential burst (not used)
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RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
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// Mask everything
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DQML <= 1'b1;
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DQMH <= 1'b1;
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// Inhibit data bus output
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DOEEN <= 1'b0;
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// Begin normal operation after 128k init cycles (~9.15ms)
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if (FS == 16'hFFFF) Ready <= 1'b1;
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end else if (S==4'h1) begin
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// Enable clock
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CKE <= 1'b1;
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// NOP
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nCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nRWE <= 1'b1;
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// Don't care bank, RA[11:8]
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BA <= 2'b00;
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RA[11:8] <= 4'b0000;
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// Mask everything
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DQML <= 1'b1;
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DQMH <= 1'b1;
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// Inhibit data bus output
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DOEEN <= 1'b0;
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end else if (S==4'h2) begin
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// Enable clock
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CKE <= 1'b1;
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// Activate
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nCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nRWE <= 1'b1;
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// SDRAM bank 0, high-order row address is 0
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BA <= 2'b00;
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RA[11:8] <= 4'b0000;
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// Row address is as previously latched
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// Mask everything
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DQML <= 1'b1;
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DQMH <= 1'b1;
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// Inhibit data bus output
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DOEEN <= 1'b0;
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end else if (S==4'h3) begin
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// Enable clock
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CKE <= 1'b1;
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// Read
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nCS <= 1'b0;
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nRAS <= 1'b1;
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nCAS <= 1'b0;
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nRWE <= 1'b1;
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// SDRAM bank 0, RA[11,9:8] don't care
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BA <= 2'b00;
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RA[11] <= 1'b0;
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RA[10] <= 1'b1; // (A10 set to auto-precharge)
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RA[9] <= 1'b0;
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RA[8] <= 1'b0;
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// Latch column address for read command
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RA[7:0] <= Ain[7:0];
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// Read low byte (high byte is +4MB in ramworks)
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DQML <= 1'b0;
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DQMH <= 1'b1;
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// Inhibit data bus output
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DOEEN <= 1'b0;
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end else if (S==4'h4) begin
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// Enable clock
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CKE <= 1'b1;
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// NOP
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nCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nRWE <= 1'b1;
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// Don't care bank, RA[11:8]
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BA <= 2'b00;
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RA[11:8] <= 4'b0000;
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// Mask everything
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DQML <= 1'b1;
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DQMH <= 1'b1;
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// Inhibit data bus output
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DOEEN <= 1'b0;
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end else if (S==4'h5) begin
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// Enable clock
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CKE <= 1'b1;
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// NOP
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nCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nRWE <= 1'b1;
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// Don't care bank, RA[11:8]
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BA <= 2'b00;
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RA[11:8] <= 4'b0000;
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// Mask everything
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DQML <= 1'b1;
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DQMH <= 1'b1;
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// Inhibit data bus output
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DOEEN <= 1'b0;
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end else if (S==4'h6) begin
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// Enable clock
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CKE <= 1'b1;
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if (FS[5:4]==0) begin
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// Auto-refresh
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nCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nRWE <= 1'b1;
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end else begin
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// NOP
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nCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nRWE <= 1'b1;
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end
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// Don't care bank, RA[11:8]
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BA <= 2'b00;
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RA[11:8] <= 4'b0000;
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// Mask everything
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DQML <= 1'b1;
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DQMH <= 1'b1;
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// Inhibit data bus output
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DOEEN <= 1'b0;
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end else if (S==4'h7) begin
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// Enable clock
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CKE <= 1'b1;
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// NOP
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nCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nRWE <= 1'b1;
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// Don't care bank, RA[11:8]
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BA <= 2'b00;
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RA[11:8] <= 4'b0000;
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// Latch row address for activate command
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RA[7:0] <= Ain[7:0];
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// Mask everything
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DQML <= 1'b1;
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DQMH <= 1'b1;
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// Inhibit data bus output
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DOEEN <= 1'b0;
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end else if (S==4'h8) begin
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// Enable clock if '245 output enabled
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CKE <= EN80;
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// Activate if '245 output enabled
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nCS <= nEN80;
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nRWE <= 1'b1;
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// SDRAM bank, RA[11:8] determine by RamWorks bank
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BA <= RWBank[5:4];
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RA[11:8] <= RWBank[3:0];
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// Row address is as previously latched
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// Mask everything
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DQML <= 1'b1;
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DQMH <= 1'b1;
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// Inhibit data bus output
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DOEEN <= 1'b0;
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end else if (S==4'h9) begin
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// Enable clock if '245 output enabled
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CKE <= EN80;
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// Read/Write if '245 output enabled
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nCS <= nEN80;
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nRAS <= 1'b1;
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nCAS <= 1'b0;
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nRWE <= nWE80;
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// SDRAM bank still determined by RamWorks, RA[11,9:8] don't care
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BA <= RWBank[5:4];
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RA[11] <= 1'b0;
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RA[10] <= 1'b1; // (A10 set to auto-precharge)
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RA[9] <= 1'b0;
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RA[8] <= RWBank[7];
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// Latch column address for R/W command
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RA[7:0] <= Ain[7:0];
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// Latch RAMWorks low nybble write select using old row address
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RWSel <= RA[0] & ~RA[3] & ~nWE & ~nC07X;
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// Mask according to RAMWorks bank (high byte is +4MB)
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DQML <= RWBank[6];
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DQMH <= ~RWBank[6];
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// Inhibit data bus output
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DOEEN <= 1'b0;
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end else if (S==4'hA) begin
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// Enable clock if '245 output enabled
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CKE <= EN80;
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// NOP
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nCS <= 1'b1;
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|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Inhibit data bus output
|
|
DOEEN <= 1'b0;
|
|
end else if (S==4'hB) begin
|
|
// Disable clock
|
|
CKE <= 1'b0;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Enable data bus output
|
|
DOEEN <= 1'b1;
|
|
end else if (S==4'hC) begin
|
|
// Disable clock
|
|
CKE <= 1'b0;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Enable data bus output
|
|
DOEEN <= 1'b1;
|
|
|
|
// RAMWorks Bank Register Select
|
|
if (RWSel) begin
|
|
// Latch RAMWorks bank if accessed
|
|
if (SetRWBankFF) RWBank <= 8'hFF;
|
|
else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]};
|
|
|
|
// Recognize command sequence and advance CS state
|
|
if ((CS==3'h0 & Din[7:0]==8'hFF) |
|
|
(CS==3'h1 & Din[7:0]==8'h00) |
|
|
(CS==3'h2 & Din[7:0]==8'h55) |
|
|
(CS==3'h3 & Din[7:0]==8'hAA) |
|
|
(CS==3'h4 & Din[7:0]==8'hC1) |
|
|
(CS==3'h5 & Din[7:0]==8'hAD) |
|
|
CS==3'h6 | CS==3'h7) CS <= CS+1;
|
|
else CS <= 0; // Back to beginning if it's not right
|
|
|
|
if (CS==3'h6) begin // Recognize and submit command in CS6
|
|
SetRWBankFF <= Din[7:0]==8'hFF;
|
|
if (Din[7:0]==8'hEF) UFMPrgmEN <= 1'b1;
|
|
if (Din[7:0]==8'hEE) UFMEraseEN <= 1'b1;
|
|
UFMBitbang <= Din[7:0]==8'hEA;
|
|
RWMaskSet <= Din[7:0]==8'hE0;
|
|
end else begin // Reset command triggers
|
|
SetRWBankFF <= 1'b0;
|
|
UFMBitbang <= 1'b0;
|
|
RWMaskSet <= 1'b0;
|
|
end
|
|
|
|
CmdTout <= 0; // Reset command timeout if RWSel accessed
|
|
end else begin
|
|
CmdTout <= CmdTout+1; // Increment command timeout
|
|
// If command sequence times out, reset sequence state
|
|
if (CmdTout==3'h7) CS <= 0;
|
|
end
|
|
end else if (S==4'hD) begin
|
|
// Disable clock
|
|
CKE <= 1'b0;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Enable data bus output
|
|
DOEEN <= 1'b1;
|
|
end else if (S==4'hE) begin
|
|
// Disable clock
|
|
CKE <= 1'b0;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
// Latch row address for next video read
|
|
RA[7:0] <= Ain[7:0];
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Enable data bus output
|
|
DOEEN <= 1'b1;
|
|
end else if (S==4'hF) begin
|
|
// Disable clock
|
|
CKE <= 1'b0;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
// Latch row address for next video read
|
|
RA[7:0] <= Ain[7:0];
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Enable data bus output
|
|
DOEEN <= 1'b1;
|
|
end
|
|
end
|
|
always @(negedge C14M) begin
|
|
// Latch video and read data outputs
|
|
if (S==4'h6) Vout[7:0] <= RD[7:0];
|
|
if (S==4'hC) Dout[7:0] <= RD[7:0];
|
|
end
|
|
endmodule
|