mirror of
https://github.com/garrettsworkshop/RAM2E.git
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20 lines
8.7 KiB
Plaintext
Executable File
20 lines
8.7 KiB
Plaintext
Executable File
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1591131661124 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1591131661125 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 02 17:01:01 2020 " "Processing started: Tue Jun 02 17:01:01 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1591131661125 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1591131661125 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1591131661125 ""}
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{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1591131661364 ""}
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{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(37) " "Verilog HDL warning at RAM2E.v(37): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 37 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1591131661398 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1591131661400 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1591131661400 ""}
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{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1591131661445 ""}
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{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1591131661445 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_a7r " "Found entity 1: UFM_altufm_none_a7r" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1591131661445 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1591131661445 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1591131661445 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1591131661478 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(99) " "Verilog HDL assignment warning at RAM2E.v(99): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 99 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591131661481 "|RAM2E"}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(102) " "Verilog HDL assignment warning at RAM2E.v(102): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 102 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591131661481 "|RAM2E"}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(504) " "Verilog HDL assignment warning at RAM2E.v(504): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 504 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591131661481 "|RAM2E"}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(521) " "Verilog HDL assignment warning at RAM2E.v(521): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 521 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1591131661481 "|RAM2E"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1591131661483 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_a7r UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component " "Elaborating entity \"UFM_altufm_none_a7r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component\"" { } { { "UFM.v" "UFM_altufm_none_a7r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1591131661485 ""}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "263 " "Implemented 263 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1591131662068 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1591131662068 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1591131662068 ""} { "Info" "ICUT_CUT_TM_LCELLS" "193 " "Implemented 193 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1591131662068 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1591131662068 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1591131662068 ""}
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{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1591131662109 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4574 " "Peak virtual memory: 4574 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1591131662156 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 02 17:01:02 2020 " "Processing ended: Tue Jun 02 17:01:02 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1591131662156 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1591131662156 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1591131662156 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1591131662156 ""}
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