mirror of
https://github.com/garrettsworkshop/RAM2E.git
synced 2024-11-24 15:31:38 +00:00
834 lines
28 KiB
Verilog
834 lines
28 KiB
Verilog
module RAM2E(C14M, PHI1, LED,
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nWE, nWE80, nEN80, nC07X,
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Ain, Din, Dout, nDOE, Vout, nVOE,
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CKE, nCS, nRAS, nCAS, nRWE,
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BA, RA, RD, DQML, DQMH);
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/* Clocks */
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input C14M, PHI1;
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/* SDRAM clock output */
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output RCLK;
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ODDRXE rclk_oddr(.D0(1'b0), .D1(1'b1),
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.SCLK(C14M), .RST(1'b0), .Q(RCLK));
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/* Control inputs */
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input nWE, nWE80, nEN80, nC07X;
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/* Activity LED */
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reg LEDEN = 0;
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output LED;
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assign LED = !(!nEN80 && LEDEN && Ready);
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/* Address Bus */
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input [7:0] Ain; // Multiplexed DRAM address input
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/* 6502 Data Bus */
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input [7:0] Din; // 6502 data bus inputs
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reg DOEEN = 0; // 6502 data bus output enable from state machine
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output nDOE;
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assign nDOE = !(!nEN80 && nWE && DOEEN); // 6502 data bus output enable
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output reg [7:0] Dout; // 6502 data Bus output
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/* Video Data Bus */
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output nVOE;
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assign nVOE = !(!PHI1); /// Video data bus output enable
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output reg [7:0] Vout; // Video data bus
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/* SDRAM */
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output reg CKE = 0;
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output nCS;
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assign nCS = 0;
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output reg nRAS = 1, nCAS = 1, nRWE = 1;
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output reg [1:0] BA;
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output reg [11:0] RA;
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output reg DQML = 1, DQMH = 1;
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wire RDOE = !nEN80 && !nWE80;
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inout [7:0] RD;
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assign RD[7:0] = RDOE ? Din[7:0] : 8'bZ;
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/* RAMWorks Bank Register and Capacity Mask */
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reg [7:0] RWBank = 0; // RAMWorks bank register
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reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask
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reg RWSel = 0; // RAMWorks bank register select
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reg CmdRWMaskSet = 0; // RAMWorks Mask register set flag
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// Causes RWBank to be zeroed next RWSel access
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//reg CmdSetRWBankFFMAX = 0;
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//reg CmdSetRWBankFFSPI = 0;
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reg CmdSetRWBankFFMXO2 = 0;
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reg CmdSetRWBankFFLED = 0;
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reg CmdLEDSet = 0;
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reg CmdLEDGet = 0;
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/* Command Sequence Detector */
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reg [2:0] CS = 0; // Command sequence state
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reg [2:0] CmdTout = 0; // Command sequence timeout
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/* UFM Interface */
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reg wb_rst;
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reg wb_cyc_stb;
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reg wb_req;
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reg wb_we;
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reg [7:0] wb_adr;
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reg [7:0] wb_dati;
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wire wb_ack;
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wire [7:0] wb_dato;
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wire ufm_irq;
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REFB ufmefb(
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.wb_clk_i(C14M),
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.wb_rst_i(wb_rst),
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.wb_cyc_i(wb_cyc_stb),
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.wb_stb_i(wb_cyc_stb),
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.wb_we_i(wb_we),
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.wb_adr_i(wb_adr),
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.wb_dat_i(wb_dati),
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.wb_dat_o(wb_dato),
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.wb_ack_o(wb_ack),
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.wbc_ufm_irq(ufm_irq));
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/* UFM State and User Command Triggers */
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//reg CmdBitbangMAX = 0; // Set by user command. Loads UFM outputs next RWSel
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//reg CmdBitbangSPI = 0;
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reg CmdBitbangMXO2 = 0;
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reg CmdExecMXO2 = 0;
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//reg CmdPrgmMAX = 0; // Set by user command. Programs UFM
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//reg CmdEraseMAX = 0; // Set by user command. Erases UFM
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/* State Counters */
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reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
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reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15
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reg [15:0] FS = 0; // Fast state counter
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reg [3:0] S = 0; // IIe State counter
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/* State Counters */
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always @(posedge C14M) begin
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// Increment fast state counter
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FS <= FS+16'h0001;
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// Synchronize Apple state counter to S1 when just entering PHI1
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PHI1reg <= PHI1; // Save old PHI1
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S <= (PHI1 && !PHI1reg && Ready) ? 4'h1 :
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S==4'h0 ? 4'h0 :
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S==4'hF ? 4'hF : S+4'h1;
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end
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/* UFM Control */
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always @(posedge C14M) begin
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if (S==4'h0) begin
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if (FS[15:14]==2'b00) wb_rst <= 1'b1;
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else if (FS[15:14]==2'b01) wb_rst <= 1'b0;
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else if (FS[15:14]==2'b10) begin
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wb_rst <= 1'b0;
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if (wb_ack || (FS[7:0]==0)) wb_cyc_stb <= 0;
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else if ((FS[7:0]==1) && wb_req) wb_cyc_stb <= 1;
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case (FS[13:8])
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0: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 1: begin // Enable configuration interface - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h74;
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wb_req <= 1;
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end 2: begin // Enable configuration interface - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h08;
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wb_req <= 1;
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end 3: begin // Enable configuration interface - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 4: begin // Enable configuration interface - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 5: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 6: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 7: begin // Poll status register - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h3C;
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wb_req <= 1;
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end 8: begin // Poll status register - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 9: begin // Poll status register - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 10: begin // Poll status register - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 11, 12, 13, 14: begin // Read status register 1-4
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h3C;
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wb_req <= 1;
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end 15: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 16: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 17: begin // Set UFM address - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'hB4;
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wb_req <= 1;
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end 18: begin // Set UFM address - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 19: begin // Set UFM address - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 20: begin // Set UFM address - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 21: begin // Set UFM address - data 1/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h40;
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wb_req <= 1;
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end 22: begin // Set UFM address - data 2/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 23: begin // Set UFM address - data 3/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 24: begin // Set UFM address - data 4/4
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 190;
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wb_req <= 1;
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end 25: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 26: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 27: begin // Read UFM page - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'hCA;
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wb_req <= 1;
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end 28: begin // Read UFM page - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h10;
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wb_req <= 1;
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end 29: begin // Read UFM page - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 30: begin // Read UFM page - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h01;
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wb_req <= 1;
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end 31: begin // Read UFM page - data 0
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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if (wb_ack) RWMask[7:0] <= wb_dato[7:0];
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end 32: begin // Read UFM page - data 1
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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if (wb_ack) LEDEN <= wb_dato[0];
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end 33, 34,
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35, 36, 37, 38,
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39, 40, 41, 42,
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43, 44, 45, 46: begin // Read UFM page - data 2-15
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 47: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 48: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 49: begin // Disable configuration interface - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h26;
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wb_req <= 1;
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end 50: begin // Disable configuration interface - operand 1/2
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 51: begin // Disable configuration interface - operand 2/2
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 52: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end 53: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_req <= 1;
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end 54: begin // Bypass - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'hFF;
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wb_req <= 1;
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end 55: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 1;
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end default: begin
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_req <= 0;
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end
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endcase
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end else begin
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wb_rst <= 1'b0;
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wb_cyc_stb <= 1'b0;
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wb_req <= 1'b0;
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h00;
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wb_dati[7:0] <= 8'h00;
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end
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end else begin
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// UFM bitbang control
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wb_rst <= 1'b0;
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wb_req <= 1'b0;
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if (RWSel && S==4'hC) begin
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// LED control
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if (CmdLEDSet) LEDEN <= Din[0];
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// Set capacity mask
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if (CmdRWMaskSet) RWMask[7:0] <= {Din[7], ~Din[6:0]};
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// Set EFB address
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if (CmdBitbangMXO2) begin
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wb_adr[7:0] <= Din[7:0];
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wb_dati[7:0] <= wb_adr[7:0];
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end
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// Excecute EFB R/W cycle
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if (CmdExecMXO2) begin
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wb_we <= Din[0];
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wb_cyc_stb <= 1;
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end else if (wb_ack) wb_cyc_stb <= 0;
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end
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end
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end
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/* SDRAM Control */
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always @(posedge C14M) begin
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if (S==4'h0) begin
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// SDRAM initialization
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if (FS[15:0]==16'hFFC0) begin
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// Precharge All
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nCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nRWE <= 1'b0;
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RA[10] <= 1'b1; // "all"
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end else if (FS[15:4]==16'hFFD && FS[0]==1'b0) begin // Repeat 8x
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// Auto-refresh
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nCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nRWE <= 1'b1;
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RA[10] <= 1'b0;
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end else if (FS[15:0]==16'hFFE8) begin
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// Set Mode Register
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nCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nRWE <= 1'b0;
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RA[10] <= 1'b0; // Reserved in mode register
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end else if (FS[15:4]==12'hFFF && FS[0]==1'b0) begin // Repeat 8x
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// Auto-refresh
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nCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nRWE <= 1'b1;
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RA[10] <= 1'b0;
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end else begin // Otherwise send no-op
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// NOP
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nCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nRWE <= 1'b1;
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RA[10] <= 1'b0;
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end
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// Enable SDRAM clock after 65,280 cycles (~4.56ms)
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CKE <= FS[15:8] == 8'hFF;
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// Mode register contents
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BA[1:0] <= 2'b00; // Reserved
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RA[11] <= 1'b0; // Reserved
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// RA[10] set above ^
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RA[9] <= 1'b1; // "1" for single write mode
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RA[8] <= 1'b0; // Reserved
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RA[7] <= 1'b0; // "0" for not test mode
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RA[6:4] <= 3'b010; // "2" for CAS latency 2
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RA[3] <= 1'b0; // "0" for sequential burst (not used)
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RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
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// Mask everything
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DQML <= 1'b1;
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DQMH <= 1'b1;
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// Inhibit data bus output
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DOEEN <= 1'b0;
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// Begin normal operation after 128k init cycles (~9.15ms)
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if (FS == 16'hFFFF) Ready <= 1'b1;
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end else if (S==4'h1) begin
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// Enable clock
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CKE <= 1'b1;
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// NOP
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nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Inhibit data bus output
|
|
DOEEN <= 1'b0;
|
|
end else if (S==4'h2) begin
|
|
// Enable clock
|
|
CKE <= 1'b1;
|
|
|
|
// Activate
|
|
nCS <= 1'b0;
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// SDRAM bank 0, high-order row address is 0
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
// Row address is as previously latched
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Inhibit data bus output
|
|
DOEEN <= 1'b0;
|
|
end else if (S==4'h3) begin
|
|
// Enable clock
|
|
CKE <= 1'b1;
|
|
|
|
// Read
|
|
nCS <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b0;
|
|
nRWE <= 1'b1;
|
|
|
|
// SDRAM bank 0, RA[11,9:8] don't care
|
|
BA[1:0] <= 2'b00;
|
|
RA[11] <= 1'b0;
|
|
RA[10] <= 1'b1; // (A10 set to auto-precharge)
|
|
RA[9] <= 1'b0;
|
|
RA[8] <= 1'b0;
|
|
// Latch column address for read command
|
|
RA[7:0] <= Ain[7:0];
|
|
|
|
// Read low byte (high byte is +4MB in ramworks)
|
|
DQML <= 1'b0;
|
|
DQMH <= 1'b1;
|
|
|
|
// Inhibit data bus output
|
|
DOEEN <= 1'b0;
|
|
end else if (S==4'h4) begin
|
|
// Enable clock
|
|
CKE <= 1'b1;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Inhibit data bus output
|
|
DOEEN <= 1'b0;
|
|
end else if (S==4'h5) begin
|
|
// Enable clock
|
|
CKE <= 1'b1;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Inhibit data bus output
|
|
DOEEN <= 1'b0;
|
|
end else if (S==4'h6) begin
|
|
// Enable clock
|
|
CKE <= 1'b1;
|
|
|
|
if (FS[5:4]==0) begin
|
|
// Auto-refresh
|
|
nCS <= 1'b0;
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b0;
|
|
nRWE <= 1'b1;
|
|
end else begin
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
end
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Inhibit data bus output
|
|
DOEEN <= 1'b0;
|
|
end else if (S==4'h7) begin
|
|
// Enable clock
|
|
CKE <= 1'b1;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
// Latch row address for activate command
|
|
RA[7:0] <= Ain[7:0];
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Inhibit data bus output
|
|
DOEEN <= 1'b0;
|
|
end else if (S==4'h8) begin
|
|
// Enable clock if '245 output enabled
|
|
CKE <= !nEN80;
|
|
|
|
// Activate if '245 output enabled
|
|
nCS <= nEN80;
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// SDRAM bank, RA[11:8] determine by RamWorks bank
|
|
BA[1:0] <= RWBank[5:4];
|
|
RA[11:8] <= RWBank[3:0];
|
|
// Row address is as previously latched
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Inhibit data bus output
|
|
DOEEN <= 1'b0;
|
|
end else if (S==4'h9) begin
|
|
// Enable clock if '245 output enabled
|
|
CKE <= !nEN80;
|
|
|
|
// Read/Write if '245 output enabled
|
|
nCS <= nEN80;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b0;
|
|
nRWE <= nWE80;
|
|
|
|
// SDRAM bank still determined by RamWorks, RA[11,9:8] don't care
|
|
BA[1:0] <= RWBank[5:4];
|
|
RA[11] <= 1'b0;
|
|
RA[10] <= 1'b1; // (A10 set to auto-precharge)
|
|
RA[9] <= 1'b0;
|
|
RA[8] <= RWBank[7];
|
|
// Latch column address for R/W command
|
|
RA[7:0] <= Ain[7:0];
|
|
|
|
// Latch RAMWorks low nybble write select using old row address
|
|
RWSel <= RA[0] && !RA[3] && !nWE && !nC07X;
|
|
|
|
// Mask according to RAMWorks bank (high byte is +4MB)
|
|
DQML <= RWBank[6];
|
|
DQMH <= !RWBank[6];
|
|
|
|
// Inhibit data bus output
|
|
DOEEN <= 1'b0;
|
|
end else if (S==4'hA) begin
|
|
// Enable clock if '245 output enabled
|
|
CKE <= !nEN80;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Inhibit data bus output
|
|
DOEEN <= 1'b0;
|
|
end else if (S==4'hB) begin
|
|
// Disable clock
|
|
CKE <= 1'b0;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Enable data bus output
|
|
DOEEN <= 1'b1;
|
|
end else if (S==4'hC) begin
|
|
// Disable clock
|
|
CKE <= 1'b0;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Enable data bus output
|
|
DOEEN <= 1'b1;
|
|
|
|
// RAMWorks Bank Register Select
|
|
if (RWSel) begin
|
|
// Latch RAMWorks bank if accessed
|
|
if (CmdSetRWBankFFLED ||
|
|
//CmdSetRWBankFFMAX ||
|
|
//CmdSetRWBankFFSPI ||
|
|
CmdSetRWBankFFMXO2 ||
|
|
(CmdLEDGet && LEDEN)) RWBank <= 8'hFF;
|
|
else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]};
|
|
|
|
// Recognize command sequence and advance CS state
|
|
if ((CS==3'h0 && Din[7:0]==8'hFF) ||
|
|
(CS==3'h1 && Din[7:0]==8'h00) ||
|
|
(CS==3'h2 && Din[7:0]==8'h55) ||
|
|
(CS==3'h3 && Din[7:0]==8'hAA) ||
|
|
(CS==3'h4 && Din[7:0]==8'hC1) ||
|
|
(CS==3'h5 && Din[7:0]==8'hAD) ||
|
|
CS==3'h6 || CS==3'h7) CS <= CS+3'h1;
|
|
else CS <= 0; // Back to beginning if it's not right
|
|
|
|
if (CS==3'h6) begin // Recognize and submit command in CS6
|
|
//CmdSetRWBankFFMAX <= Din[7:0]==8'hFF;
|
|
//CmdSetRWBankFFSPI <= Din[7:0]==8'hFE;
|
|
CmdSetRWBankFFMXO2 <= Din[7:0]==8'hFD;
|
|
CmdSetRWBankFFLED <= Din[7:0]==8'hF0;
|
|
|
|
CmdRWMaskSet <= Din[7:0]==8'hE0;
|
|
CmdLEDSet <= Din[7:0]==8'hE2;
|
|
CmdLEDGet <= Din[7:0]==8'hE3;
|
|
|
|
//CmdBitbangMAX <= Din[7:0]==8'hEA;
|
|
//CmdBitbangSPI <= Din[7:0]==8'hEB;
|
|
CmdBitbangMXO2 <= Din[7:0]==8'hEC;
|
|
CmdExecMXO2 <= Din[7:0]==8'hED;
|
|
|
|
//if (Din[7:0]==8'hEE) CmdEraseMAX <= 1;
|
|
//if (Din[7:0]==8'hEF) CmdPrgmMAX <= 1;
|
|
end else begin // Reset command triggers
|
|
//CmdSetRWBankFFMAX <= 0;
|
|
//CmdSetRWBankFFSPI <= 0;
|
|
CmdSetRWBankFFMXO2 <= 0;
|
|
CmdSetRWBankFFLED <= 0;
|
|
CmdRWMaskSet <= 0;
|
|
CmdLEDSet <= 0;
|
|
CmdLEDGet <= 0;
|
|
//CmdBitbangMAX <= 0;
|
|
//CmdBitbangSPI <= 0;
|
|
CmdBitbangMXO2 <= 0;
|
|
CmdExecMXO2 <= 0;
|
|
end
|
|
|
|
CmdTout <= 0; // Reset command timeout if RWSel accessed
|
|
end else begin
|
|
CmdTout <= CmdTout+3'h1; // Increment command timeout
|
|
// If command sequence times out, reset sequence state
|
|
if (CmdTout==3'h7) CS <= 0;
|
|
end
|
|
end else if (S==4'hD) begin
|
|
// Disable clock
|
|
CKE <= 1'b0;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Enable data bus output
|
|
DOEEN <= 1'b1;
|
|
end else if (S==4'hE) begin
|
|
// Disable clock
|
|
CKE <= 1'b0;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
// Latch row address for next video read
|
|
RA[7:0] <= Ain[7:0];
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Enable data bus output
|
|
DOEEN <= 1'b1;
|
|
end else if (S==4'hF) begin
|
|
// Disable clock
|
|
CKE <= 1'b0;
|
|
|
|
// NOP
|
|
nCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nRWE <= 1'b1;
|
|
|
|
// Don't care bank, RA[11:8]
|
|
BA[1:0] <= 2'b00;
|
|
RA[11:8] <= 4'b0000;
|
|
// Latch row address for next video read
|
|
RA[7:0] <= Ain[7:0];
|
|
|
|
// Mask everything
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
|
|
// Enable data bus output
|
|
DOEEN <= 1'b1;
|
|
end
|
|
end
|
|
always @(negedge C14M) begin
|
|
// Latch video and read data outputs
|
|
if (S==4'h6) Vout[7:0] <= RD[7:0];
|
|
if (S==4'hC) Dout[7:0] <= RD[7:0];
|
|
end
|
|
endmodule
|