93 lines
5.5 KiB
Plaintext
Executable File
93 lines
5.5 KiB
Plaintext
Executable File
EDA Netlist Writer report for RAM2E
|
|
Sun Feb 16 22:32:27 2020
|
|
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
|
|
|
|
|
---------------------
|
|
; Table of Contents ;
|
|
---------------------
|
|
1. Legal Notice
|
|
2. EDA Netlist Writer Summary
|
|
3. Simulation Settings
|
|
4. Simulation Generated Files
|
|
5. EDA Netlist Writer Messages
|
|
|
|
|
|
|
|
----------------
|
|
; Legal Notice ;
|
|
----------------
|
|
Copyright (C) 1991-2013 Altera Corporation
|
|
Your use of Altera Corporation's design tools, logic functions
|
|
and other software and tools, and its AMPP partner logic
|
|
functions, and any output files from any of the foregoing
|
|
(including device programming or simulation files), and any
|
|
associated documentation or information are expressly subject
|
|
to the terms and conditions of the Altera Program License
|
|
Subscription Agreement, Altera MegaCore Function License
|
|
Agreement, or other applicable license agreement, including,
|
|
without limitation, that your use is for the sole purpose of
|
|
programming logic devices manufactured by Altera and sold by
|
|
Altera or its authorized distributors. Please refer to the
|
|
applicable agreement for further details.
|
|
|
|
|
|
|
|
+-------------------------------------------------------------------+
|
|
; EDA Netlist Writer Summary ;
|
|
+---------------------------+---------------------------------------+
|
|
; EDA Netlist Writer Status ; Successful - Sun Feb 16 22:32:27 2020 ;
|
|
; Revision Name ; RAM2E ;
|
|
; Top-level Entity Name ; RAM2E ;
|
|
; Family ; MAX7000S ;
|
|
; Simulation Files Creation ; Successful ;
|
|
+---------------------------+---------------------------------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------+
|
|
; Simulation Settings ;
|
|
+---------------------------------------------------------------------------------------------------+---------------------------+
|
|
; Option ; Setting ;
|
|
+---------------------------------------------------------------------------------------------------+---------------------------+
|
|
; Tool Name ; ModelSim-Altera (Verilog) ;
|
|
; Generate netlist for functional simulation only ; On ;
|
|
; Truncate long hierarchy paths ; Off ;
|
|
; Map illegal HDL characters ; Off ;
|
|
; Flatten buses into individual nodes ; Off ;
|
|
; Maintain hierarchy ; Off ;
|
|
; Bring out device-wide set/reset signals as ports ; Off ;
|
|
; Enable glitch filtering ; Off ;
|
|
; Do not write top level VHDL entity ; Off ;
|
|
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
|
|
; Architecture name in VHDL output netlist ; structure ;
|
|
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
|
|
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
|
|
+---------------------------------------------------------------------------------------------------+---------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------+
|
|
; Simulation Generated Files ;
|
|
+------------------------------------------------------------------------+
|
|
; Generated Files ;
|
|
+------------------------------------------------------------------------+
|
|
; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/simulation/modelsim/RAM2E.vo ;
|
|
+------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------+
|
|
; EDA Netlist Writer Messages ;
|
|
+-----------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus II 64-Bit EDA Netlist Writer
|
|
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
|
Info: Processing started: Sun Feb 16 22:32:27 2020
|
|
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E
|
|
Info (204019): Generated file RAM2E.vo in folder "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/simulation/modelsim/" for EDA simulation tool
|
|
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
|
|
Info: Peak virtual memory: 4505 megabytes
|
|
Info: Processing ended: Sun Feb 16 22:32:27 2020
|
|
Info: Elapsed time: 00:00:00
|
|
Info: Total CPU time (on all processors): 00:00:00
|
|
|
|
|