216 lines
8.4 KiB
Plaintext
216 lines
8.4 KiB
Plaintext
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Loading design for application trce from file ram2e_lcmxo2_1200hc_impl1_map.ncd.
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Design name: RAM2E
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-1200HC
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Package: TQFP100
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Performance: 4
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Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
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Package Status: Final Version 1.44.
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Performance Hardware Data Status: Final Version 34.4.
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Setup and Hold Report
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
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Thu Sep 21 05:34:48 2023
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Report Information
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf
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Design file: ram2e_lcmxo2_1200hc_impl1_map.ncd
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Preference file: ram2e_lcmxo2_1200hc_impl1.prf
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Device,speed: LCMXO2-1200HC,4
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
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1491 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 58.471ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q FS[11] (from C14M_c +)
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Destination: FF Data in nRWE_0io (to C14M_c +)
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Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
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Constraint Details:
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11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
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69.930ns delay constraint less
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0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
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Physical Path Details:
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Data path SLICE_3 to nRWE_MGIOL:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 SLICE_3.CLK to SLICE_3.Q0 SLICE_3 (from C14M_c)
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ROUTE 19 e 1.234 SLICE_3.Q0 to SLICE_64.A1 FS[11]
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CTOF_DEL --- 0.495 SLICE_64.A1 to SLICE_64.F1 SLICE_64
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ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_97.D0 N_577
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CTOF_DEL --- 0.495 SLICE_97.D0 to SLICE_97.F0 SLICE_97
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ROUTE 3 e 1.234 SLICE_97.F0 to SLICE_75.D1 N_489
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CTOF_DEL --- 0.495 SLICE_75.D1 to SLICE_75.F1 SLICE_75
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ROUTE 3 e 0.480 SLICE_75.F1 to SLICE_75.A0 N_628
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CTOF_DEL --- 0.495 SLICE_75.A0 to SLICE_75.F0 SLICE_75
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ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_71.C1 N_640
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CTOF_DEL --- 0.495 SLICE_71.C1 to SLICE_71.F1 SLICE_71
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ROUTE 1 e 1.234 SLICE_71.F1 to SLICE_115.A0 un1_nCS61_1_i
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CTOF_DEL --- 0.495 SLICE_115.A0 to SLICE_115.F0 SLICE_115
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ROUTE 1 e 1.234 SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
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--------
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11.306 (30.3% logic, 69.7% route), 7 logic levels.
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Report: 87.268MHz is the maximum frequency for this preference.
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Report Summary
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--------------
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----------------------------------------------------------------------------
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Preference | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 87.268 MHz| 7
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----------------------------------------------------------------------------
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All preferences were met.
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Clock Domains Analysis
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------------------------
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Found 1 clocks:
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Clock Domain: C14M_c Source: C14M.PAD Loads: 84
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Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
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Timing summary (Setup):
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
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Thu Sep 21 05:34:49 2023
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Report Information
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf
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Design file: ram2e_lcmxo2_1200hc_impl1_map.ncd
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Preference file: ram2e_lcmxo2_1200hc_impl1.prf
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Device,speed: LCMXO2-1200HC,M
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
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1491 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.447ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q FS[0] (from C14M_c +)
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Destination: FF Data in FS[0] (to C14M_c +)
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Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
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Constraint Details:
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0.434ns physical path delay SLICE_0 to SLICE_0 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
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Physical Path Details:
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Data path SLICE_0 to SLICE_0:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c)
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ROUTE 5 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
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CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0
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ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c)
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--------
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0.434 (53.9% logic, 46.1% route), 2 logic levels.
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Report Summary
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--------------
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----------------------------------------------------------------------------
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Preference(MIN Delays) | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2
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----------------------------------------------------------------------------
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All preferences were met.
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Clock Domains Analysis
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------------------------
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Found 1 clocks:
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Clock Domain: C14M_c Source: C14M.PAD Loads: 84
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Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
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Timing summary (Hold):
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
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Timing summary (Setup and Hold):
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---------------
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Timing errors: 0 (setup), 0 (hold)
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Score: 0 (setup), 0 (hold)
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Cumulative negative slack: 0 (0+0)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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