32 lines
1.3 KiB
Plaintext
32 lines
1.3 KiB
Plaintext
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
|
# Your use of Intel Corporation's design tools, logic functions
|
|
# and other software and tools, and any partner logic
|
|
# functions, and any output files from any of the foregoing
|
|
# (including device programming or simulation files), and any
|
|
# associated documentation or information are expressly subject
|
|
# to the terms and conditions of the Intel Program License
|
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
# the Intel FPGA IP License Agreement, or other applicable license
|
|
# agreement, including, without limitation, that your use is for
|
|
# the sole purpose of programming logic devices manufactured by
|
|
# Intel and sold by Intel or its authorized distributors. Please
|
|
# refer to the applicable agreement for further details, at
|
|
# https://fpgasoftware.intel.com/eula.
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Quartus Prime
|
|
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
|
# Date created = 07:26:23 August 20, 2023
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
|
|
QUARTUS_VERSION = "19.1"
|
|
DATE = "07:26:23 August 20, 2023"
|
|
|
|
# Revisions
|
|
|
|
PROJECT_REVISION = "RAM2E"
|