153 lines
3.4 KiB
Plaintext
153 lines
3.4 KiB
Plaintext
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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# Written on Thu Dec 28 23:09:49 2023
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##### DESIGN INFO #######################################################
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Top View: "RAM2E"
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Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
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##### SUMMARY ############################################################
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Found 0 issues in 0 out of 1 constraints
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##### DETAILS ############################################################
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Clock Relationships
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*******************
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Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
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-----------------------------------------------------------------------------------------------------------------------------------
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System C14M | 69.841 | No paths | No paths | No paths
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C14M System | 69.841 | No paths | No paths | No paths
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C14M C14M | 69.841 | No paths | 34.920 | No paths
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===================================================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Unconstrained Start/End Points
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******************************
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p:Ain[0]
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p:Ain[1]
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p:Ain[2]
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p:Ain[3]
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p:Ain[4]
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p:Ain[5]
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p:Ain[6]
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p:Ain[7]
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p:BA[0]
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p:BA[1]
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p:CKEout
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p:DQMH
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p:DQML
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p:Din[0]
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p:Din[1]
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p:Din[2]
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p:Din[3]
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p:Din[4]
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p:Din[5]
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p:Din[6]
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p:Din[7]
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p:Dout[0]
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p:Dout[1]
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p:Dout[2]
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p:Dout[3]
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p:Dout[4]
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p:Dout[5]
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p:Dout[6]
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p:Dout[7]
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p:LED
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p:PHI1
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p:RAout[0]
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p:RAout[1]
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p:RAout[2]
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p:RAout[3]
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p:RAout[4]
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p:RAout[5]
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p:RAout[6]
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p:RAout[7]
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p:RAout[8]
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p:RAout[9]
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p:RAout[10]
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p:RAout[11]
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p:RD[0] (bidir end point)
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p:RD[0] (bidir start point)
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p:RD[1] (bidir end point)
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p:RD[1] (bidir start point)
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p:RD[2] (bidir end point)
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p:RD[2] (bidir start point)
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p:RD[3] (bidir end point)
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p:RD[3] (bidir start point)
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p:RD[4] (bidir end point)
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p:RD[4] (bidir start point)
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p:RD[5] (bidir end point)
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p:RD[5] (bidir start point)
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p:RD[6] (bidir end point)
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p:RD[6] (bidir start point)
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p:RD[7] (bidir end point)
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p:RD[7] (bidir start point)
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p:Vout[0]
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p:Vout[1]
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p:Vout[2]
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p:Vout[3]
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p:Vout[4]
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p:Vout[5]
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p:Vout[6]
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p:Vout[7]
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p:nC07X
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p:nCASout
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p:nCSout
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p:nDOE
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p:nEN80
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p:nRASout
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p:nRWEout
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p:nVOE
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p:nWE
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p:nWE80
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Inapplicable constraints
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************************
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(none)
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Applicable constraints with issues
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**********************************
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(none)
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Constraints with matching wildcard expressions
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**********************************************
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(none)
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Library Report
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**************
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# End of Constraint Checker Report
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