729 lines
86 KiB
Plaintext
729 lines
86 KiB
Plaintext
Timing Analyzer report for RAM2E
|
|
Thu Dec 28 23:09:52 2023
|
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
|
|
|
|
|
---------------------
|
|
; Table of Contents ;
|
|
---------------------
|
|
1. Legal Notice
|
|
2. Timing Analyzer Summary
|
|
3. Parallel Compilation
|
|
4. SDC File List
|
|
5. Clocks
|
|
6. Fmax Summary
|
|
7. Setup Summary
|
|
8. Hold Summary
|
|
9. Recovery Summary
|
|
10. Removal Summary
|
|
11. Minimum Pulse Width Summary
|
|
12. Setup: 'ram2e_ufm|DRCLK|regout'
|
|
13. Setup: 'ram2e_ufm|ARCLK|regout'
|
|
14. Setup: 'C14M'
|
|
15. Hold: 'ram2e_ufm|DRCLK|regout'
|
|
16. Hold: 'ram2e_ufm|ARCLK|regout'
|
|
17. Hold: 'C14M'
|
|
18. Setup Transfers
|
|
19. Hold Transfers
|
|
20. Report TCCS
|
|
21. Report RSKM
|
|
22. Unconstrained Paths Summary
|
|
23. Clock Status Summary
|
|
24. Unconstrained Input Ports
|
|
25. Unconstrained Output Ports
|
|
26. Unconstrained Input Ports
|
|
27. Unconstrained Output Ports
|
|
28. Timing Analyzer Messages
|
|
|
|
|
|
|
|
----------------
|
|
; Legal Notice ;
|
|
----------------
|
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
|
Your use of Intel Corporation's design tools, logic functions
|
|
and other software and tools, and any partner logic
|
|
functions, and any output files from any of the foregoing
|
|
(including device programming or simulation files), and any
|
|
associated documentation or information are expressly subject
|
|
to the terms and conditions of the Intel Program License
|
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
the Intel FPGA IP License Agreement, or other applicable license
|
|
agreement, including, without limitation, that your use is for
|
|
the sole purpose of programming logic devices manufactured by
|
|
Intel and sold by Intel or its authorized distributors. Please
|
|
refer to the applicable agreement for further details, at
|
|
https://fpgasoftware.intel.com/eula.
|
|
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------+
|
|
; Timing Analyzer Summary ;
|
|
+-----------------------+---------------------------------------------------------------------+
|
|
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
|
; Timing Analyzer ; Legacy Timing Analyzer ;
|
|
; Revision Name ; RAM2E ;
|
|
; Device Family ; MAX V ;
|
|
; Device Name ; 5M240ZT100C5 ;
|
|
; Timing Models ; Final ;
|
|
; Delay Model ; Slow Model ;
|
|
; Rise/Fall Delays ; Unavailable ;
|
|
+-----------------------+---------------------------------------------------------------------+
|
|
|
|
|
|
+------------------------------------------+
|
|
; Parallel Compilation ;
|
|
+----------------------------+-------------+
|
|
; Processors ; Number ;
|
|
+----------------------------+-------------+
|
|
; Number detected on machine ; 4 ;
|
|
; Maximum allowed ; 4 ;
|
|
; ; ;
|
|
; Average used ; 1.00 ;
|
|
; Maximum used ; 2 ;
|
|
; ; ;
|
|
; Usage by Processor ; % Time Used ;
|
|
; Processor 1 ; 100.0% ;
|
|
; Processor 2 ; 0.0% ;
|
|
+----------------------------+-------------+
|
|
|
|
|
|
+------------------------------------------------------+
|
|
; SDC File List ;
|
|
+------------------+--------+--------------------------+
|
|
; SDC File Path ; Status ; Read at ;
|
|
+------------------+--------+--------------------------+
|
|
; ../RAM2E.sdc ; OK ; Thu Dec 28 23:09:51 2023 ;
|
|
; ../RAM2E-MAX.sdc ; OK ; Thu Dec 28 23:09:51 2023 ;
|
|
+------------------+--------+--------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Clocks ;
|
|
+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
|
|
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
|
|
+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
|
|
; C14M ; Base ; 69.841 ; 14.32 MHz ; 0.000 ; 34.920 ; ; ; ; ; ; ; ; ; ; ; { C14M } ;
|
|
; ram2e_ufm|ARCLK|regout ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ram2e_ufm|ARCLK|regout } ;
|
|
; ram2e_ufm|DRCLK|regout ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ram2e_ufm|DRCLK|regout } ;
|
|
+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
|
|
|
|
|
|
+-------------------------------------------------------------+
|
|
; Fmax Summary ;
|
|
+-----------+-----------------+------------------------+------+
|
|
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
|
+-----------+-----------------+------------------------+------+
|
|
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|ARCLK|regout ; ;
|
|
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|DRCLK|regout ; ;
|
|
; 27.71 MHz ; 27.71 MHz ; C14M ; ;
|
|
+-----------+-----------------+------------------------+------+
|
|
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
|
|
|
|
|
+--------------------------------------------------+
|
|
; Setup Summary ;
|
|
+------------------------+---------+---------------+
|
|
; Clock ; Slack ; End Point TNS ;
|
|
+------------------------+---------+---------------+
|
|
; ram2e_ufm|DRCLK|regout ; -25.451 ; -25.451 ;
|
|
; ram2e_ufm|ARCLK|regout ; -25.441 ; -25.441 ;
|
|
; C14M ; -20.081 ; -208.886 ;
|
|
+------------------------+---------+---------------+
|
|
|
|
|
|
+--------------------------------------------------+
|
|
; Hold Summary ;
|
|
+------------------------+---------+---------------+
|
|
; Clock ; Slack ; End Point TNS ;
|
|
+------------------------+---------+---------------+
|
|
; ram2e_ufm|DRCLK|regout ; -14.567 ; -14.567 ;
|
|
; ram2e_ufm|ARCLK|regout ; -14.558 ; -14.558 ;
|
|
; C14M ; 3.133 ; 0.000 ;
|
|
+------------------------+---------+---------------+
|
|
|
|
|
|
--------------------
|
|
; Recovery Summary ;
|
|
--------------------
|
|
No paths to report.
|
|
|
|
|
|
-------------------
|
|
; Removal Summary ;
|
|
-------------------
|
|
No paths to report.
|
|
|
|
|
|
+-------------------------------------------------+
|
|
; Minimum Pulse Width Summary ;
|
|
+------------------------+--------+---------------+
|
|
; Clock ; Slack ; End Point TNS ;
|
|
+------------------------+--------+---------------+
|
|
; C14M ; 34.581 ; 0.000 ;
|
|
; ram2e_ufm|ARCLK|regout ; 70.000 ; 0.000 ;
|
|
; ram2e_ufm|DRCLK|regout ; 70.000 ; 0.000 ;
|
|
+------------------------+--------+---------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Setup: 'ram2e_ufm|DRCLK|regout' ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
; -25.451 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -0.970 ; 4.482 ;
|
|
; -25.432 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -0.970 ; 4.463 ;
|
|
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Setup: 'ram2e_ufm|ARCLK|regout' ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
; -25.441 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -0.977 ; 4.465 ;
|
|
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Setup: 'C14M' ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
|
|
; -20.081 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 20.731 ;
|
|
; -18.769 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 19.419 ;
|
|
; -18.109 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.759 ;
|
|
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
|
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
|
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
|
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
|
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
|
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
|
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
|
; -16.915 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 17.565 ;
|
|
; -11.924 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 12.574 ;
|
|
; 25.780 ; RA[5] ; RAout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.819 ;
|
|
; 26.401 ; RA[0] ; RAout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.198 ;
|
|
; 27.872 ; RA[10] ; RAout[10]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.727 ;
|
|
; 28.323 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.276 ;
|
|
; 28.531 ; RA[8] ; RAout[8]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.068 ;
|
|
; 28.539 ; RA[11] ; RAout[11]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.060 ;
|
|
; 28.589 ; RA[9] ; RAout[9]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.010 ;
|
|
; 30.107 ; RA[7] ; RAout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.492 ;
|
|
; 30.133 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.466 ;
|
|
; 30.360 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.239 ;
|
|
; 30.365 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.234 ;
|
|
; 30.369 ; RA[1] ; RAout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.230 ;
|
|
; 30.392 ; RA[6] ; RAout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.207 ;
|
|
; 31.173 ; RA[3] ; RAout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.426 ;
|
|
; 31.207 ; RA[2] ; RAout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.392 ;
|
|
; 31.456 ; RA[4] ; RAout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.143 ;
|
|
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
|
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
|
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
|
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
|
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
|
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
|
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
|
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
|
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
|
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
|
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
|
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
|
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
|
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
|
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
|
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
|
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
|
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
|
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
|
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
|
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
|
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
|
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
|
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
|
; 37.521 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 69.841 ; 0.000 ; 31.999 ;
|
|
; 37.937 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 69.841 ; 0.000 ; 31.583 ;
|
|
; 39.048 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 69.841 ; 0.000 ; 30.472 ;
|
|
; 40.235 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 69.841 ; 0.000 ; 29.285 ;
|
|
; 40.239 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 69.841 ; 0.000 ; 29.281 ;
|
|
; 40.355 ; S[1] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 29.165 ;
|
|
; 40.651 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 69.841 ; 0.000 ; 28.869 ;
|
|
; 40.655 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 69.841 ; 0.000 ; 28.865 ;
|
|
; 40.771 ; S[2] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 28.749 ;
|
|
; 41.239 ; FS[15] ; nCAS ; C14M ; C14M ; 69.841 ; 0.000 ; 28.281 ;
|
|
; 41.532 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.988 ;
|
|
; 41.557 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.963 ;
|
|
; 41.762 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 69.841 ; 0.000 ; 27.758 ;
|
|
; 41.766 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 69.841 ; 0.000 ; 27.754 ;
|
|
; 41.808 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.712 ;
|
|
; 41.882 ; S[3] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 27.638 ;
|
|
; 41.904 ; FS[13] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.616 ;
|
|
; 42.244 ; CS[0] ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 27.276 ;
|
|
; 42.246 ; CS[0] ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 27.274 ;
|
|
; 42.482 ; FS[15] ; nRAS ; C14M ; C14M ; 69.841 ; 0.000 ; 27.038 ;
|
|
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
|
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
|
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
|
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
|
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
|
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
|
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
|
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
|
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
|
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
|
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
|
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
|
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
|
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
|
; 42.780 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.740 ;
|
|
; 42.842 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.678 ;
|
|
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
|
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
|
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
|
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
|
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
|
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
|
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
|
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
|
; 42.991 ; FS[0] ; nCAS ; C14M ; C14M ; 69.841 ; 0.000 ; 26.529 ;
|
|
; 42.993 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.527 ;
|
|
; 42.993 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.527 ;
|
|
; 42.993 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.527 ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Hold: 'ram2e_ufm|DRCLK|regout' ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
; -14.567 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -0.970 ; 4.463 ;
|
|
; -14.548 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -0.970 ; 4.482 ;
|
|
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Hold: 'ram2e_ufm|ARCLK|regout' ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
; -14.558 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -0.977 ; 4.465 ;
|
|
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
|
|
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Hold: 'C14M' ;
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
|
; 3.133 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.172 ;
|
|
; 3.136 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.175 ;
|
|
; 3.429 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.468 ;
|
|
; 3.436 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.475 ;
|
|
; 3.453 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.492 ;
|
|
; 3.483 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.522 ;
|
|
; 3.527 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.566 ;
|
|
; 3.753 ; RWBank[7] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.792 ;
|
|
; 3.765 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 3.804 ;
|
|
; 3.767 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.806 ;
|
|
; 3.803 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.842 ;
|
|
; 3.833 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.872 ;
|
|
; 3.879 ; RC[2] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.918 ;
|
|
; 3.883 ; RC[2] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.922 ;
|
|
; 3.885 ; RC[2] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.924 ;
|
|
; 4.002 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.041 ;
|
|
; 4.318 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.357 ;
|
|
; 4.629 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 4.668 ;
|
|
; 4.854 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.893 ;
|
|
; 4.855 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.894 ;
|
|
; 4.859 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.898 ;
|
|
; 4.879 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.918 ;
|
|
; 5.050 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.089 ;
|
|
; 5.054 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.093 ;
|
|
; 5.156 ; S[2] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.195 ;
|
|
; 5.163 ; S[2] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.202 ;
|
|
; 5.217 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
|
|
; 5.217 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
|
|
; 5.228 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.267 ;
|
|
; 5.229 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 5.268 ;
|
|
; 5.233 ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.272 ;
|
|
; 5.253 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.292 ;
|
|
; 5.266 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.305 ;
|
|
; 5.272 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.311 ;
|
|
; 5.281 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.320 ;
|
|
; 5.290 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.329 ;
|
|
; 5.301 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.340 ;
|
|
; 5.312 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 5.351 ;
|
|
; 5.313 ; RC[0] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.352 ;
|
|
; 5.315 ; RC[0] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.354 ;
|
|
; 5.316 ; RC[0] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.355 ;
|
|
; 5.320 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.359 ;
|
|
; 5.329 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.368 ;
|
|
; 5.351 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.390 ;
|
|
; 5.354 ; S[3] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.393 ;
|
|
; 5.355 ; S[3] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.394 ;
|
|
; 5.429 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ;
|
|
; 5.429 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ;
|
|
; 5.443 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.482 ;
|
|
; 5.443 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.482 ;
|
|
; 5.449 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.488 ;
|
|
; 5.452 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
|
|
; 5.452 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
|
|
; 5.453 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ;
|
|
; 5.453 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ;
|
|
; 5.460 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.499 ;
|
|
; 5.464 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.503 ;
|
|
; 5.466 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.505 ;
|
|
; 5.552 ; RC[1] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.591 ;
|
|
; 5.559 ; RC[1] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.598 ;
|
|
; 5.561 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.600 ;
|
|
; 5.563 ; RC[1] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.602 ;
|
|
; 5.564 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.603 ;
|
|
; 5.565 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 5.604 ;
|
|
; 5.565 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.604 ;
|
|
; 5.570 ; S[1] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.609 ;
|
|
; 5.579 ; S[1] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.618 ;
|
|
; 5.613 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.652 ;
|
|
; 5.884 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.923 ;
|
|
; 5.988 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.027 ;
|
|
; 6.001 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.040 ;
|
|
; 6.016 ; S[0] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.055 ;
|
|
; 6.132 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.171 ;
|
|
; 6.145 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.184 ;
|
|
; 6.276 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.315 ;
|
|
; 6.315 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.354 ;
|
|
; 6.319 ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.358 ;
|
|
; 6.338 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.377 ;
|
|
; 6.365 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.404 ;
|
|
; 6.445 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.484 ;
|
|
; 6.451 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.490 ;
|
|
; 6.454 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
|
|
; 6.454 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
|
|
; 6.455 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.494 ;
|
|
; 6.462 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.501 ;
|
|
; 6.466 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.505 ;
|
|
; 6.516 ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.555 ;
|
|
; 6.536 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.575 ;
|
|
; 6.567 ; S[3] ; CKE ; C14M ; C14M ; 0.000 ; 0.000 ; 6.606 ;
|
|
; 6.598 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ;
|
|
; 6.598 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ;
|
|
; 6.610 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.649 ;
|
|
; 6.627 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.666 ;
|
|
; 6.628 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.667 ;
|
|
; 6.710 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.749 ;
|
|
; 6.735 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.774 ;
|
|
; 6.742 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.781 ;
|
|
; 6.754 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.793 ;
|
|
; 6.771 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.810 ;
|
|
; 6.787 ; S[0] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.826 ;
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------+
|
|
; Setup Transfers ;
|
|
+------------------------+------------------------+----------+----------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------------------+------------------------+----------+----------+----------+----------+
|
|
; C14M ; C14M ; 1625 ; 0 ; 16 ; 0 ;
|
|
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
|
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
|
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
|
; C14M ; ram2e_ufm|DRCLK|regout ; 2 ; 0 ; 0 ; 0 ;
|
|
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
|
+------------------------+------------------------+----------+----------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------+
|
|
; Hold Transfers ;
|
|
+------------------------+------------------------+----------+----------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------------------+------------------------+----------+----------+----------+----------+
|
|
; C14M ; C14M ; 1625 ; 0 ; 16 ; 0 ;
|
|
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
|
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
|
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
|
; C14M ; ram2e_ufm|DRCLK|regout ; 2 ; 0 ; 0 ; 0 ;
|
|
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
|
+------------------------+------------------------+----------+----------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
---------------
|
|
; Report TCCS ;
|
|
---------------
|
|
No dedicated SERDES Transmitter circuitry present in device or used in design
|
|
|
|
|
|
---------------
|
|
; Report RSKM ;
|
|
---------------
|
|
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
|
|
|
|
|
|
+------------------------------------------------+
|
|
; Unconstrained Paths Summary ;
|
|
+---------------------------------+-------+------+
|
|
; Property ; Setup ; Hold ;
|
|
+---------------------------------+-------+------+
|
|
; Illegal Clocks ; 0 ; 0 ;
|
|
; Unconstrained Clocks ; 0 ; 0 ;
|
|
; Unconstrained Input Ports ; 28 ; 28 ;
|
|
; Unconstrained Input Port Paths ; 176 ; 176 ;
|
|
; Unconstrained Output Ports ; 47 ; 47 ;
|
|
; Unconstrained Output Port Paths ; 76 ; 76 ;
|
|
+---------------------------------+-------+------+
|
|
|
|
|
|
+----------------------------------------------------------------------+
|
|
; Clock Status Summary ;
|
|
+------------------------+------------------------+------+-------------+
|
|
; Target ; Clock ; Type ; Status ;
|
|
+------------------------+------------------------+------+-------------+
|
|
; C14M ; C14M ; Base ; Constrained ;
|
|
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; Base ; Constrained ;
|
|
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; Base ; Constrained ;
|
|
+------------------------+------------------------+------+-------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Input Ports ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; Input Port ; Comment ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; Ain[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; PHI1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Output Ports ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; Output Port ; Comment ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; CKEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nCASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRWEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Input Ports ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; Input Port ; Comment ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; Ain[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Ain[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; PHI1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Output Ports ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; Output Port ; Comment ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; CKEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RAout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nCASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRWEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
|
|
|
|
+--------------------------+
|
|
; Timing Analyzer Messages ;
|
|
+--------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Timing Analyzer
|
|
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
|
Info: Processing started: Thu Dec 28 23:09:49 2023
|
|
Info: Command: quartus_sta RAM2E-MAXV -c RAM2E
|
|
Info: qsta_default_script.tcl version: #1
|
|
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
|
Info (21077): Low junction temperature is 0 degrees C
|
|
Info (21077): High junction temperature is 85 degrees C
|
|
Info (334003): Started post-fitting delay annotation
|
|
Info (334004): Delay annotation completed successfully
|
|
Info (332104): Reading SDC File: '../RAM2E.sdc'
|
|
Info (332104): Reading SDC File: '../RAM2E-MAX.sdc'
|
|
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
|
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
|
|
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
|
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
|
Critical Warning (332148): Timing requirements not met
|
|
Info (332146): Worst-case setup slack is -25.451
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -25.451 -25.451 ram2e_ufm|DRCLK|regout
|
|
Info (332119): -25.441 -25.441 ram2e_ufm|ARCLK|regout
|
|
Info (332119): -20.081 -208.886 C14M
|
|
Info (332146): Worst-case hold slack is -14.567
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -14.567 -14.567 ram2e_ufm|DRCLK|regout
|
|
Info (332119): -14.558 -14.558 ram2e_ufm|ARCLK|regout
|
|
Info (332119): 3.133 0.000 C14M
|
|
Info (332140): No Recovery paths to report
|
|
Info (332140): No Removal paths to report
|
|
Info (332146): Worst-case minimum pulse width slack is 34.581
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 34.581 0.000 C14M
|
|
Info (332119): 70.000 0.000 ram2e_ufm|ARCLK|regout
|
|
Info (332119): 70.000 0.000 ram2e_ufm|DRCLK|regout
|
|
Info (332001): The selected device family is not supported by the report_metastability command.
|
|
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
|
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
|
Info (332102): Design is not fully constrained for setup requirements
|
|
Info (332102): Design is not fully constrained for hold requirements
|
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
|
|
Info: Peak virtual memory: 13067 megabytes
|
|
Info: Processing ended: Thu Dec 28 23:09:52 2023
|
|
Info: Elapsed time: 00:00:03
|
|
Info: Total CPU time (on all processors): 00:00:02
|
|
|
|
|