Map TRACE Report

Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-640HC
Package:     TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.39.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Sat Oct 09 01:19:15 2021

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed:    LCMXO2-640HC,4
Report level:    verbose report, limited to 1 item per preference
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Preference Summary

  • PERIOD NET "PHI2_c" 350.000000 ns (0 errors)
  • 121 items scored, 0 timing errors detected.
  • PERIOD NET "nCCAS_c" 350.000000 ns (0 errors)
  • 0 items scored, 0 timing errors detected.
  • PERIOD NET "nCRAS_c" 350.000000 ns (0 errors)
  • 0 items scored, 0 timing errors detected.
  • PERIOD NET "RCLK_c" 16.000000 ns (0 errors)
  • 1409 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Derating parameters ------------------- Voltage: 3.300 V VCCIO Voltage: 3.135 V (Bank 0) 3.135 V (Bank 1) 3.135 V (Bank 2) 3.135 V (Bank 3) 2.375 V (Bank 4) 2.375 V (Bank 5) 2.375 V (Bank 6) 2.375 V (Bank 7) ================================================================================ Preference: PERIOD NET "PHI2_c" 350.000000 ns ; 121 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 161.658ns (weighted slack = 323.316ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_i5 (from PHI2_c +) Destination: FF Data in CmdEnable_541 (to PHI2_c -) Delay: 13.035ns (30.0% logic, 70.0% route), 8 logic levels. Constraint Details: 13.035ns physical path delay SLICE_111 to SLICE_19 meets 175.000ns delay constraint less 0.307ns CE_SET requirement (totaling 174.693ns) by 161.658ns Physical Path Details: Data path SLICE_111 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_111.CLK to SLICE_111.Q1 SLICE_111 (from PHI2_c) ROUTE 1 e 1.234 SLICE_111.Q1 to SLICE_158.B0 Bank_5 CTOF_DEL --- 0.495 SLICE_158.B0 to SLICE_158.F0 SLICE_158 ROUTE 1 e 1.234 SLICE_158.F0 to SLICE_139.B0 n4610 CTOF_DEL --- 0.495 SLICE_139.B0 to SLICE_139.F0 SLICE_139 ROUTE 2 e 1.234 SLICE_139.F0 to SLICE_114.B1 n4628 CTOF_DEL --- 0.495 SLICE_114.B1 to SLICE_114.F1 SLICE_114 ROUTE 4 e 1.234 SLICE_114.F1 to SLICE_116.B1 n2384 CTOF_DEL --- 0.495 SLICE_116.B1 to SLICE_116.F1 SLICE_116 ROUTE 2 e 0.480 SLICE_116.F1 to SLICE_116.D0 n4888 CTOF_DEL --- 0.495 SLICE_116.D0 to SLICE_116.F0 SLICE_116 ROUTE 1 e 1.234 SLICE_116.F0 to SLICE_19.B1 n4624 CTOF_DEL --- 0.495 SLICE_19.B1 to SLICE_19.F1 SLICE_19 ROUTE 4 e 1.234 SLICE_19.F1 to SLICE_130.C0 C1Submitted_N_232 CTOF_DEL --- 0.495 SLICE_130.C0 to SLICE_130.F0 SLICE_130 ROUTE 1 e 1.234 SLICE_130.F0 to SLICE_19.CE PHI2_N_151_enable_1 (to PHI2_c) -------- 13.035 (30.0% logic, 70.0% route), 8 logic levels. Report: 26.684ns is the minimum period for this preference. ================================================================================ Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 347.500ns The internal maximum frequency of the following component is 400.000 MHz Logical Details: Cell type Pin name Component name Destination: SLICE CLK SLICE_122 Delay: 2.500ns -- based on Minimum Pulse Width Report: 2.500ns is the minimum period for this preference. ================================================================================ Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 347.500ns The internal maximum frequency of the following component is 400.000 MHz Logical Details: Cell type Pin name Component name Destination: SLICE CLK SLICE_25 Delay: 2.500ns -- based on Minimum Pulse Width Report: 2.500ns is the minimum period for this preference. ================================================================================ Preference: PERIOD NET "RCLK_c" 16.000000 ns ; 1409 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.077ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS_972__i8 (from RCLK_c +) Destination: FF Data in wb_adr_i4 (to RCLK_c +) Delay: 13.757ns (33.7% logic, 66.3% route), 9 logic levels. Constraint Details: 13.757ns physical path delay SLICE_5 to SLICE_70 meets 16.000ns delay constraint less 0.166ns DIN_SET requirement (totaling 15.834ns) by 2.077ns Physical Path Details: Data path SLICE_5 to SLICE_70: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_5.CLK to SLICE_5.Q1 SLICE_5 (from RCLK_c) ROUTE 23 e 1.234 SLICE_5.Q1 to SLICE_98.B1 FS_8 CTOF_DEL --- 0.495 SLICE_98.B1 to SLICE_98.F1 SLICE_98 ROUTE 4 e 1.234 SLICE_98.F1 to SLICE_93.B1 n4924 CTOF_DEL --- 0.495 SLICE_93.B1 to SLICE_93.F1 SLICE_93 ROUTE 1 e 1.234 SLICE_93.F1 to SLICE_133.D0 n98 CTOF_DEL --- 0.495 SLICE_133.D0 to SLICE_133.F0 SLICE_133 ROUTE 2 e 0.480 SLICE_133.F0 to SLICE_133.B1 n2199 CTOF_DEL --- 0.495 SLICE_133.B1 to SLICE_133.F1 SLICE_133 ROUTE 1 e 1.234 SLICE_133.F1 to *9/SLICE_84.C1 n53 CTOOFX_DEL --- 0.721 *9/SLICE_84.C1 to *SLICE_84.OFX0 i29/SLICE_84 ROUTE 1 e 1.234 *SLICE_84.OFX0 to SLICE_148.C1 n14_adj_3 CTOF_DEL --- 0.495 SLICE_148.C1 to SLICE_148.F1 SLICE_148 ROUTE 2 e 1.234 SLICE_148.F1 to SLICE_135.C0 n12_adj_8 CTOF_DEL --- 0.495 SLICE_135.C0 to SLICE_135.F0 SLICE_135 ROUTE 2 e 1.234 SLICE_135.F0 to SLICE_70.A1 n14_adj_7 CTOF_DEL --- 0.495 SLICE_70.A1 to SLICE_70.F1 SLICE_70 ROUTE 1 e 0.001 SLICE_70.F1 to SLICE_70.DI1 wb_adr_7_N_60_4 (to RCLK_c) -------- 13.757 (33.7% logic, 66.3% route), 9 logic levels. Report: 13.923ns is the minimum period for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 4.343ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RA10_536 (from RCLK_c +) Destination: Port Pad RA[10] Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_54 and 5.791ns delay SLICE_54 to RA[10] (totaling 8.157ns) meets 12.500ns offset RCLK to RA[10] by 4.343ns Physical Path Details: Clock path RCLK to SLICE_54: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_54.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_54 to RA[10]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_54.CLK to SLICE_54.Q0 SLICE_54 (from RCLK_c) ROUTE 1 e 1.234 SLICE_54.Q0 to 64.PADDO n1975 DOPAD_DEL --- 4.105 64.PADDO to 64.PAD RA[10] -------- 5.791 (78.7% logic, 21.3% route), 2 logic levels. Report: 8.157ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[9] Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RA[9] (totaling 9.886ns) meets 12.500ns offset RCLK to RA[9] by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RA[9]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_151.C0 nRowColSel CTOF_DEL --- 0.495 SLICE_151.C0 to SLICE_151.F0 SLICE_151 ROUTE 1 e 1.234 SLICE_151.F0 to 62.PADDO RA_c_9 DOPAD_DEL --- 4.105 62.PADDO to 62.PAD RA[9] -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[8] Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RA[8] (totaling 9.886ns) meets 12.500ns offset RCLK to RA[8] by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RA[8]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_163.C1 nRowColSel CTOF_DEL --- 0.495 SLICE_163.C1 to SLICE_163.F1 SLICE_163 ROUTE 1 e 1.234 SLICE_163.F1 to 65.PADDO RA_c_8 DOPAD_DEL --- 4.105 65.PADDO to 65.PAD RA[8] -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[7] Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RA[7] (totaling 9.886ns) meets 12.500ns offset RCLK to RA[7] by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RA[7]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_155.C1 nRowColSel CTOF_DEL --- 0.495 SLICE_155.C1 to SLICE_155.F1 SLICE_155 ROUTE 1 e 1.234 SLICE_155.F1 to 75.PADDO RA_c_7 DOPAD_DEL --- 4.105 75.PADDO to 75.PAD RA[7] -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[6] Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RA[6] (totaling 9.886ns) meets 12.500ns offset RCLK to RA[6] by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RA[6]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_163.C0 nRowColSel CTOF_DEL --- 0.495 SLICE_163.C0 to SLICE_163.F0 SLICE_163 ROUTE 1 e 1.234 SLICE_163.F0 to 68.PADDO RA_c_6 DOPAD_DEL --- 4.105 68.PADDO to 68.PAD RA[6] -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[5] Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RA[5] (totaling 9.886ns) meets 12.500ns offset RCLK to RA[5] by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RA[5]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_157.C1 nRowColSel CTOF_DEL --- 0.495 SLICE_157.C1 to SLICE_157.F1 SLICE_157 ROUTE 1 e 1.234 SLICE_157.F1 to 70.PADDO RA_c_5 DOPAD_DEL --- 4.105 70.PADDO to 70.PAD RA[5] -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[4] Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RA[4] (totaling 9.886ns) meets 12.500ns offset RCLK to RA[4] by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RA[4]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_158.C1 nRowColSel CTOF_DEL --- 0.495 SLICE_158.C1 to SLICE_158.F1 SLICE_158 ROUTE 1 e 1.234 SLICE_158.F1 to 74.PADDO RA_c_4 DOPAD_DEL --- 4.105 74.PADDO to 74.PAD RA[4] -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[3] Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RA[3] (totaling 9.886ns) meets 12.500ns offset RCLK to RA[3] by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RA[3]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_162.C0 nRowColSel CTOF_DEL --- 0.495 SLICE_162.C0 to SLICE_162.F0 SLICE_162 ROUTE 1 e 1.234 SLICE_162.F0 to 71.PADDO RA_c_3 DOPAD_DEL --- 4.105 71.PADDO to 71.PAD RA[3] -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[2] Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RA[2] (totaling 9.886ns) meets 12.500ns offset RCLK to RA[2] by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RA[2]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_161.C0 nRowColSel CTOF_DEL --- 0.495 SLICE_161.C0 to SLICE_161.F0 SLICE_161 ROUTE 1 e 1.234 SLICE_161.F0 to 69.PADDO RA_c_2 DOPAD_DEL --- 4.105 69.PADDO to 69.PAD RA[2] -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[1] Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RA[1] (totaling 9.886ns) meets 12.500ns offset RCLK to RA[1] by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RA[1]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_162.C1 nRowColSel CTOF_DEL --- 0.495 SLICE_162.C1 to SLICE_162.F1 SLICE_162 ROUTE 1 e 1.234 SLICE_162.F1 to 67.PADDO RA_c_1 DOPAD_DEL --- 4.105 67.PADDO to 67.PAD RA[1] -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[0] Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RA[0] (totaling 9.886ns) meets 12.500ns offset RCLK to RA[0] by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RA[0]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_159.C1 nRowColSel CTOF_DEL --- 0.495 SLICE_159.C1 to SLICE_159.F1 SLICE_159 ROUTE 1 e 1.234 SLICE_159.F1 to 66.PADDO RA_c_0 DOPAD_DEL --- 4.105 66.PADDO to 66.PAD RA[0] -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 4.343ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRCS_532 (from RCLK_c +) Destination: Port Pad nRCS Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_59 and 5.791ns delay SLICE_59 to nRCS (totaling 8.157ns) meets 12.500ns offset RCLK to nRCS by 4.343ns Physical Path Details: Clock path RCLK to SLICE_59: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_59.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_59 to nRCS: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_59.CLK to SLICE_59.Q0 SLICE_59 (from RCLK_c) ROUTE 1 e 1.234 SLICE_59.Q0 to 57.PADDO nRCS_c DOPAD_DEL --- 4.105 57.PADDO to 57.PAD nRCS -------- 5.791 (78.7% logic, 21.3% route), 2 logic levels. Report: 8.157ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 4.343ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RCKE_531 (from RCLK_c +) Destination: Port Pad RCKE Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_35 and 5.791ns delay SLICE_35 to RCKE (totaling 8.157ns) meets 12.500ns offset RCLK to RCKE by 4.343ns Physical Path Details: Clock path RCLK to SLICE_35: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_35.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_35 to RCKE: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_35.CLK to SLICE_35.Q0 SLICE_35 (from RCLK_c) ROUTE 4 e 1.234 SLICE_35.Q0 to 53.PADDO RCKE_c DOPAD_DEL --- 4.105 53.PADDO to 53.PAD RCKE -------- 5.791 (78.7% logic, 21.3% route), 2 logic levels. Report: 8.157ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 4.343ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRWE_535 (from RCLK_c +) Destination: Port Pad nRWE Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_62 and 5.791ns delay SLICE_62 to nRWE (totaling 8.157ns) meets 12.500ns offset RCLK to nRWE by 4.343ns Physical Path Details: Clock path RCLK to SLICE_62: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_62.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_62 to nRWE: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_62.CLK to SLICE_62.Q0 SLICE_62 (from RCLK_c) ROUTE 1 e 1.234 SLICE_62.Q0 to 49.PADDO nRWE_c DOPAD_DEL --- 4.105 49.PADDO to 49.PAD nRWE -------- 5.791 (78.7% logic, 21.3% route), 2 logic levels. Report: 8.157ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 4.343ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRRAS_533 (from RCLK_c +) Destination: Port Pad nRRAS Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_60 and 5.791ns delay SLICE_60 to nRRAS (totaling 8.157ns) meets 12.500ns offset RCLK to nRRAS by 4.343ns Physical Path Details: Clock path RCLK to SLICE_60: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_60.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_60 to nRRAS: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c) ROUTE 1 e 1.234 SLICE_60.Q0 to 54.PADDO nRRAS_c DOPAD_DEL --- 4.105 54.PADDO to 54.PAD nRRAS -------- 5.791 (78.7% logic, 21.3% route), 2 logic levels. Report: 8.157ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 4.343ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRCAS_534 (from RCLK_c +) Destination: Port Pad nRCAS Data Path Delay: 5.791ns (78.7% logic, 21.3% route), 2 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_57 and 5.791ns delay SLICE_57 to nRCAS (totaling 8.157ns) meets 12.500ns offset RCLK to nRCAS by 4.343ns Physical Path Details: Clock path RCLK to SLICE_57: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_57.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_57 to nRCAS: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_57.CLK to SLICE_57.Q0 SLICE_57 (from RCLK_c) ROUTE 1 e 1.234 SLICE_57.Q0 to 52.PADDO nRCAS_c DOPAD_DEL --- 4.105 52.PADDO to 52.PAD nRCAS -------- 5.791 (78.7% logic, 21.3% route), 2 logic levels. Report: 8.157ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RDQMH Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RDQMH (totaling 9.886ns) meets 12.500ns offset RCLK to RDQMH by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RDQMH: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_151.B1 nRowColSel CTOF_DEL --- 0.495 SLICE_151.B1 to SLICE_151.F1 SLICE_151 ROUTE 1 e 1.234 SLICE_151.F1 to 51.PADDO RDQMH_c DOPAD_DEL --- 4.105 51.PADDO to 51.PAD RDQMH -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.614ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RDQML Data Path Delay: 7.520ns (67.2% logic, 32.8% route), 3 logic levels. Clock Path Delay: 2.366ns (47.8% logic, 52.2% route), 1 logic levels. Constraint Details: 2.366ns delay RCLK to SLICE_63 and 7.520ns delay SLICE_63 to RDQML (totaling 9.886ns) meets 12.500ns offset RCLK to RDQML by 2.614ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 63.PAD to 63.PADDI RCLK ROUTE 52 e 1.234 63.PADDI to SLICE_63.CLK RCLK_c -------- 2.366 (47.8% logic, 52.2% route), 1 logic levels. Data path SLICE_63 to RDQML: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 1.234 SLICE_63.Q0 to SLICE_161.B1 nRowColSel CTOF_DEL --- 0.495 SLICE_161.B1 to SLICE_161.F1 SLICE_161 ROUTE 1 e 1.234 SLICE_161.F1 to 48.PADDO RDQML_c DOPAD_DEL --- 4.105 48.PADDO to 48.PAD RDQML -------- 7.520 (67.2% logic, 32.8% route), 3 logic levels. Report: 9.886ns is the minimum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 26.684 ns| 8 | | | PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.500 ns| 0 | | | PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.500 ns| 0 | | | PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 13.923 ns| 9 | | | CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 | | | CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 | | | CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 | | | CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 | | | CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 | | | CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 8.157 ns| 2 | | | CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3 | | | CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 5 clocks: Clock Domain: wb_clk Source: SLICE_73.Q0 Loads: 1 No transfer within this clock domain is found Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 No transfer within this clock domain is found Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 No transfer within this clock domain is found Clock Domain: RCLK_c Source: RCLK.PAD Loads: 52 Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; Data transfers from: Clock Domain: wb_clk Source: SLICE_73.Q0 Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; Transfers: 2 Clock Domain: nCRAS_c Source: nCRAS.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: PHI2_c Source: PHI2.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 Sat Oct 09 01:19:15 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd Preference file: ram2gs_lcmxo2_640hc_impl1.prf Device,speed: LCMXO2-640HC,M Report level: verbose report, limited to 1 item per preference -------------------------------------------------------------------------------- Preference Summary
  • PERIOD NET "PHI2_c" 350.000000 ns (0 errors)
  • 121 items scored, 0 timing errors detected.
  • PERIOD NET "nCCAS_c" 350.000000 ns (0 errors)
  • 0 items scored, 0 timing errors detected.
  • PERIOD NET "nCRAS_c" 350.000000 ns (0 errors)
  • 0 items scored, 0 timing errors detected.
  • PERIOD NET "RCLK_c" 16.000000 ns (0 errors)
  • 1409 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 1 item scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected.
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
  • 0 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Derating parameters ------------------- Voltage: 3.300 V VCCIO Voltage: 3.135 V (Bank 0) 3.135 V (Bank 1) 3.135 V (Bank 2) 3.135 V (Bank 3) 2.375 V (Bank 4) 2.375 V (Bank 5) 2.375 V (Bank 6) 2.375 V (Bank 7) ================================================================================ Preference: PERIOD NET "PHI2_c" 350.000000 ns ; 121 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.447ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q C1Submitted_542 (from PHI2_c -) Destination: FF Data in C1Submitted_542 (to PHI2_c -) Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. Constraint Details: 0.434ns physical path delay SLICE_15 to SLICE_15 meets -0.013ns DIN_HLD and 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns Physical Path Details: Data path SLICE_15 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_15.CLK to SLICE_15.Q0 SLICE_15 (from PHI2_c) ROUTE 2 e 0.199 SLICE_15.Q0 to SLICE_15.D0 C1Submitted CTOF_DEL --- 0.101 SLICE_15.D0 to SLICE_15.F0 SLICE_15 ROUTE 1 e 0.001 SLICE_15.F0 to SLICE_15.DI0 n2549 (to PHI2_c) -------- 0.434 (53.9% logic, 46.1% route), 2 logic levels. ================================================================================ Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: PERIOD NET "RCLK_c" 16.000000 ns ; 1409 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.351ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS_FSM__i2 (from RCLK_c +) Destination: FF Data in IS_FSM__i3 (to RCLK_c +) Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. Constraint Details: 0.332ns physical path delay SLICE_118 to SLICE_118 meets -0.019ns M_HLD and 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns Physical Path Details: Data path SLICE_118 to SLICE_118: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_118.CLK to SLICE_118.Q0 SLICE_118 (from RCLK_c) ROUTE 1 e 0.199 SLICE_118.Q0 to SLICE_118.M1 n1197 (to RCLK_c) -------- 0.332 (40.1% logic, 59.9% route), 1 logic levels. ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.284ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RA10_536 (from RCLK_c +) Destination: Port Pad RA[10] Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_54 and 2.321ns delay SLICE_54 to RA[10] (totaling 3.284ns) meets 0.000ns hold offset RCLK to RA[10] by 3.284ns Physical Path Details: Clock path RCLK to SLICE_54: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_54.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_54 to RA[10]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_54.CLK to SLICE_54.Q0 SLICE_54 (from RCLK_c) ROUTE 1 e 0.515 SLICE_54.Q0 to 64.PADDO n1975 DOPAD_DEL --- 1.673 64.PADDO to 64.PAD RA[10] -------- 2.321 (77.8% logic, 22.2% route), 2 logic levels. Report: 3.284ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[9] Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RA[9] (totaling 3.900ns) meets 0.000ns hold offset RCLK to RA[9] by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RA[9]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_151.C0 nRowColSel CTOF_DEL --- 0.101 SLICE_151.C0 to SLICE_151.F0 SLICE_151 ROUTE 1 e 0.515 SLICE_151.F0 to 62.PADDO RA_c_9 DOPAD_DEL --- 1.673 62.PADDO to 62.PAD RA[9] -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[8] Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RA[8] (totaling 3.900ns) meets 0.000ns hold offset RCLK to RA[8] by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RA[8]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_163.C1 nRowColSel CTOF_DEL --- 0.101 SLICE_163.C1 to SLICE_163.F1 SLICE_163 ROUTE 1 e 0.515 SLICE_163.F1 to 65.PADDO RA_c_8 DOPAD_DEL --- 1.673 65.PADDO to 65.PAD RA[8] -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[7] Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RA[7] (totaling 3.900ns) meets 0.000ns hold offset RCLK to RA[7] by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RA[7]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_155.C1 nRowColSel CTOF_DEL --- 0.101 SLICE_155.C1 to SLICE_155.F1 SLICE_155 ROUTE 1 e 0.515 SLICE_155.F1 to 75.PADDO RA_c_7 DOPAD_DEL --- 1.673 75.PADDO to 75.PAD RA[7] -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[6] Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RA[6] (totaling 3.900ns) meets 0.000ns hold offset RCLK to RA[6] by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RA[6]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_163.C0 nRowColSel CTOF_DEL --- 0.101 SLICE_163.C0 to SLICE_163.F0 SLICE_163 ROUTE 1 e 0.515 SLICE_163.F0 to 68.PADDO RA_c_6 DOPAD_DEL --- 1.673 68.PADDO to 68.PAD RA[6] -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[5] Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RA[5] (totaling 3.900ns) meets 0.000ns hold offset RCLK to RA[5] by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RA[5]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_157.C1 nRowColSel CTOF_DEL --- 0.101 SLICE_157.C1 to SLICE_157.F1 SLICE_157 ROUTE 1 e 0.515 SLICE_157.F1 to 70.PADDO RA_c_5 DOPAD_DEL --- 1.673 70.PADDO to 70.PAD RA[5] -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[4] Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RA[4] (totaling 3.900ns) meets 0.000ns hold offset RCLK to RA[4] by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RA[4]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_158.C1 nRowColSel CTOF_DEL --- 0.101 SLICE_158.C1 to SLICE_158.F1 SLICE_158 ROUTE 1 e 0.515 SLICE_158.F1 to 74.PADDO RA_c_4 DOPAD_DEL --- 1.673 74.PADDO to 74.PAD RA[4] -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[3] Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RA[3] (totaling 3.900ns) meets 0.000ns hold offset RCLK to RA[3] by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RA[3]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_162.C0 nRowColSel CTOF_DEL --- 0.101 SLICE_162.C0 to SLICE_162.F0 SLICE_162 ROUTE 1 e 0.515 SLICE_162.F0 to 71.PADDO RA_c_3 DOPAD_DEL --- 1.673 71.PADDO to 71.PAD RA[3] -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[2] Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RA[2] (totaling 3.900ns) meets 0.000ns hold offset RCLK to RA[2] by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RA[2]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_161.C0 nRowColSel CTOF_DEL --- 0.101 SLICE_161.C0 to SLICE_161.F0 SLICE_161 ROUTE 1 e 0.515 SLICE_161.F0 to 69.PADDO RA_c_2 DOPAD_DEL --- 1.673 69.PADDO to 69.PAD RA[2] -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[1] Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RA[1] (totaling 3.900ns) meets 0.000ns hold offset RCLK to RA[1] by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RA[1]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_162.C1 nRowColSel CTOF_DEL --- 0.101 SLICE_162.C1 to SLICE_162.F1 SLICE_162 ROUTE 1 e 0.515 SLICE_162.F1 to 67.PADDO RA_c_1 DOPAD_DEL --- 1.673 67.PADDO to 67.PAD RA[1] -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RA[0] Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RA[0] (totaling 3.900ns) meets 0.000ns hold offset RCLK to RA[0] by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RA[0]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_159.C1 nRowColSel CTOF_DEL --- 0.101 SLICE_159.C1 to SLICE_159.F1 SLICE_159 ROUTE 1 e 0.515 SLICE_159.F1 to 66.PADDO RA_c_0 DOPAD_DEL --- 1.673 66.PADDO to 66.PAD RA[0] -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.284ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRCS_532 (from RCLK_c +) Destination: Port Pad nRCS Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_59 and 2.321ns delay SLICE_59 to nRCS (totaling 3.284ns) meets 0.000ns hold offset RCLK to nRCS by 3.284ns Physical Path Details: Clock path RCLK to SLICE_59: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_59.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_59 to nRCS: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_59.CLK to SLICE_59.Q0 SLICE_59 (from RCLK_c) ROUTE 1 e 0.515 SLICE_59.Q0 to 57.PADDO nRCS_c DOPAD_DEL --- 1.673 57.PADDO to 57.PAD nRCS -------- 2.321 (77.8% logic, 22.2% route), 2 logic levels. Report: 3.284ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.284ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RCKE_531 (from RCLK_c +) Destination: Port Pad RCKE Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_35 and 2.321ns delay SLICE_35 to RCKE (totaling 3.284ns) meets 0.000ns hold offset RCLK to RCKE by 3.284ns Physical Path Details: Clock path RCLK to SLICE_35: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_35.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_35 to RCKE: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_35.CLK to SLICE_35.Q0 SLICE_35 (from RCLK_c) ROUTE 4 e 0.515 SLICE_35.Q0 to 53.PADDO RCKE_c DOPAD_DEL --- 1.673 53.PADDO to 53.PAD RCKE -------- 2.321 (77.8% logic, 22.2% route), 2 logic levels. Report: 3.284ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.284ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRWE_535 (from RCLK_c +) Destination: Port Pad nRWE Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_62 and 2.321ns delay SLICE_62 to nRWE (totaling 3.284ns) meets 0.000ns hold offset RCLK to nRWE by 3.284ns Physical Path Details: Clock path RCLK to SLICE_62: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_62.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_62 to nRWE: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_62.CLK to SLICE_62.Q0 SLICE_62 (from RCLK_c) ROUTE 1 e 0.515 SLICE_62.Q0 to 49.PADDO nRWE_c DOPAD_DEL --- 1.673 49.PADDO to 49.PAD nRWE -------- 2.321 (77.8% logic, 22.2% route), 2 logic levels. Report: 3.284ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.284ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRRAS_533 (from RCLK_c +) Destination: Port Pad nRRAS Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_60 and 2.321ns delay SLICE_60 to nRRAS (totaling 3.284ns) meets 0.000ns hold offset RCLK to nRRAS by 3.284ns Physical Path Details: Clock path RCLK to SLICE_60: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_60.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_60 to nRRAS: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c) ROUTE 1 e 0.515 SLICE_60.Q0 to 54.PADDO nRRAS_c DOPAD_DEL --- 1.673 54.PADDO to 54.PAD nRRAS -------- 2.321 (77.8% logic, 22.2% route), 2 logic levels. Report: 3.284ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.284ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRCAS_534 (from RCLK_c +) Destination: Port Pad nRCAS Data Path Delay: 2.321ns (77.8% logic, 22.2% route), 2 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_57 and 2.321ns delay SLICE_57 to nRCAS (totaling 3.284ns) meets 0.000ns hold offset RCLK to nRCAS by 3.284ns Physical Path Details: Clock path RCLK to SLICE_57: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_57.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_57 to nRCAS: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_57.CLK to SLICE_57.Q0 SLICE_57 (from RCLK_c) ROUTE 1 e 0.515 SLICE_57.Q0 to 52.PADDO nRCAS_c DOPAD_DEL --- 1.673 52.PADDO to 52.PAD nRCAS -------- 2.321 (77.8% logic, 22.2% route), 2 logic levels. Report: 3.284ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RDQMH Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RDQMH (totaling 3.900ns) meets 0.000ns hold offset RCLK to RDQMH by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RDQMH: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_151.B1 nRowColSel CTOF_DEL --- 0.101 SLICE_151.B1 to SLICE_151.F1 SLICE_151 ROUTE 1 e 0.515 SLICE_151.F1 to 51.PADDO RDQMH_c DOPAD_DEL --- 1.673 51.PADDO to 51.PAD RDQMH -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 3.900ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_538 (from RCLK_c +) Destination: Port Pad RDQML Data Path Delay: 2.937ns (64.9% logic, 35.1% route), 3 logic levels. Clock Path Delay: 0.963ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.963ns delay RCLK to SLICE_63 and 2.937ns delay SLICE_63 to RDQML (totaling 3.900ns) meets 0.000ns hold offset RCLK to RDQML by 3.900ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.448 63.PAD to 63.PADDI RCLK ROUTE 52 e 0.515 63.PADDI to SLICE_63.CLK RCLK_c -------- 0.963 (46.5% logic, 53.5% route), 1 logic levels. Data path SLICE_63 to RDQML: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) ROUTE 12 e 0.515 SLICE_63.Q0 to SLICE_161.B1 nRowColSel CTOF_DEL --- 0.101 SLICE_161.B1 to SLICE_161.F1 SLICE_161 ROUTE 1 e 0.515 SLICE_161.F1 to 48.PADDO RDQML_c DOPAD_DEL --- 1.673 48.PADDO to 48.PAD RDQML -------- 2.937 (64.9% logic, 35.1% route), 3 logic levels. Report: 3.900ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2 | | | PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0 | | | PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0 | | | PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1 | | | CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 | | | CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 | | | CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 | | | CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 | | | CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 | | | CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.284 ns| 2 | | | CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 3.900 ns| 3 | | | CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 5 clocks: Clock Domain: wb_clk Source: SLICE_73.Q0 Loads: 1 No transfer within this clock domain is found Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 No transfer within this clock domain is found Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 No transfer within this clock domain is found Clock Domain: RCLK_c Source: RCLK.PAD Loads: 52 Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; Data transfers from: Clock Domain: wb_clk Source: SLICE_73.Q0 Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; Transfers: 2 Clock Domain: nCRAS_c Source: nCRAS.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: PHI2_c Source: PHI2.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------