--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Mon Aug 16 20:38:58 2021

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design file:     RAM2GS
Device,speed:    LCMXO640C,3
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------


Derating parameters
-------------------
Voltage:    3.300 V



================================================================================
Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
            10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 

Passed: The following path meets requirements by 163.925ns (weighted slack = 327.850ns)
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Bank_i6  (from PHI2_c +)
   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
                   FF                        CmdUFMCLK_380

   Delay:              10.810ns  (25.8% logic, 74.2% route), 7 logic levels.

 Constraint Details:

     10.810ns physical path delay SLICE_98 to SLICE_83 meets
    175.000ns delay constraint less
      0.000ns skew and
      0.265ns CE_SET requirement (totaling 174.735ns) by 163.925ns

 Physical Path Details:

      Data path SLICE_98 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_98 (from PHI2_c)
ROUTE         1     1.018       R2C2A.Q0 to R2C2B.B1       Bank_6
CTOF_DEL    ---     0.371       R2C2B.B1 to       R2C2B.F1 SLICE_90
ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
                  --------
                   10.810   (25.8% logic, 74.2% route), 7 logic levels.

 Clock Skew Details: 

      Source Clock Path PHI2 to SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path PHI2 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 164.114ns (weighted slack = 328.228ns)
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Bank_i7  (from PHI2_c +)
   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
                   FF                        CmdUFMCLK_380

   Delay:              10.621ns  (26.2% logic, 73.8% route), 7 logic levels.

 Constraint Details:

     10.621ns physical path delay SLICE_98 to SLICE_83 meets
    175.000ns delay constraint less
      0.000ns skew and
      0.265ns CE_SET requirement (totaling 174.735ns) by 164.114ns

 Physical Path Details:

      Data path SLICE_98 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_98 (from PHI2_c)
ROUTE         1     1.487       R2C2A.Q1 to R2C5B.A0       Bank_7
CTOF_DEL    ---     0.371       R2C5B.A0 to       R2C5B.F0 SLICE_84
ROUTE         1     0.497       R2C5B.F0 to R2C5B.C1       n2136
CTOF_DEL    ---     0.371       R2C5B.C1 to       R2C5B.F1 SLICE_84
ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
                  --------
                   10.621   (26.2% logic, 73.8% route), 7 logic levels.

 Clock Skew Details: 

      Source Clock Path PHI2 to SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path PHI2 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 164.237ns (weighted slack = 328.474ns)
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Bank_i4  (from PHI2_c +)
   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
                   FF                        CmdUFMCLK_380

   Delay:              10.498ns  (23.0% logic, 77.0% route), 6 logic levels.

 Constraint Details:

     10.498ns physical path delay SLICE_90 to SLICE_83 meets
    175.000ns delay constraint less
      0.000ns skew and
      0.265ns CE_SET requirement (totaling 174.735ns) by 164.237ns

 Physical Path Details:

      Data path SLICE_90 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_90 (from PHI2_c)
ROUTE         1     1.643       R2C2B.Q0 to R2C6C.B0       Bank_4
CTOF_DEL    ---     0.371       R2C6C.B0 to       R2C6C.F0 SLICE_101
ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
                  --------
                   10.498   (23.0% logic, 77.0% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path PHI2 to SLICE_90:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path PHI2 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 164.307ns (weighted slack = 328.614ns)
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Bank_i5  (from PHI2_c +)
   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
                   FF                        CmdUFMCLK_380

   Delay:              10.428ns  (26.7% logic, 73.3% route), 7 logic levels.

 Constraint Details:

     10.428ns physical path delay SLICE_90 to SLICE_83 meets
    175.000ns delay constraint less
      0.000ns skew and
      0.265ns CE_SET requirement (totaling 174.735ns) by 164.307ns

 Physical Path Details:

      Data path SLICE_90 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q1 SLICE_90 (from PHI2_c)
ROUTE         1     0.636       R2C2B.Q1 to R2C2B.A1       Bank_5
CTOF_DEL    ---     0.371       R2C2B.A1 to       R2C2B.F1 SLICE_90
ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
                  --------
                   10.428   (26.7% logic, 73.3% route), 7 logic levels.

 Clock Skew Details: 

      Source Clock Path PHI2 to SLICE_90:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path PHI2 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 164.317ns (weighted slack = 328.634ns)
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Bank_i0  (from PHI2_c +)
   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
                   FF                        CmdUFMCLK_380

   Delay:              10.418ns  (26.7% logic, 73.3% route), 7 logic levels.

 Constraint Details:

     10.418ns physical path delay SLICE_93 to SLICE_83 meets
    175.000ns delay constraint less
      0.000ns skew and
      0.265ns CE_SET requirement (totaling 174.735ns) by 164.317ns

 Physical Path Details:

      Data path SLICE_93 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_93 (from PHI2_c)
ROUTE         1     0.626       R2C2C.Q0 to R2C2B.D1       Bank_0
CTOF_DEL    ---     0.371       R2C2B.D1 to       R2C2B.F1 SLICE_90
ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
                  --------
                   10.418   (26.7% logic, 73.3% route), 7 logic levels.

 Clock Skew Details: 

      Source Clock Path PHI2 to SLICE_93:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R2C2C.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path PHI2 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 164.386ns (weighted slack = 328.772ns)
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Bank_i6  (from PHI2_c +)
   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)

   Delay:              10.349ns  (26.9% logic, 73.1% route), 7 logic levels.

 Constraint Details:

     10.349ns physical path delay SLICE_98 to SLICE_77 meets
    175.000ns delay constraint less
      0.000ns skew and
      0.265ns CE_SET requirement (totaling 174.735ns) by 164.386ns

 Physical Path Details:

      Data path SLICE_98 to SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_98 (from PHI2_c)
ROUTE         1     1.018       R2C2A.Q0 to R2C2B.B1       Bank_6
CTOF_DEL    ---     0.371       R2C2B.B1 to       R2C2B.F1 SLICE_90
ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
                  --------
                   10.349   (26.9% logic, 73.1% route), 7 logic levels.

 Clock Skew Details: 

      Source Clock Path PHI2 to SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path PHI2 to SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 164.575ns (weighted slack = 329.150ns)
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Bank_i7  (from PHI2_c +)
   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)

   Delay:              10.160ns  (27.4% logic, 72.6% route), 7 logic levels.

 Constraint Details:

     10.160ns physical path delay SLICE_98 to SLICE_77 meets
    175.000ns delay constraint less
      0.000ns skew and
      0.265ns CE_SET requirement (totaling 174.735ns) by 164.575ns

 Physical Path Details:

      Data path SLICE_98 to SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_98 (from PHI2_c)
ROUTE         1     1.487       R2C2A.Q1 to R2C5B.A0       Bank_7
CTOF_DEL    ---     0.371       R2C5B.A0 to       R2C5B.F0 SLICE_84
ROUTE         1     0.497       R2C5B.F0 to R2C5B.C1       n2136
CTOF_DEL    ---     0.371       R2C5B.C1 to       R2C5B.F1 SLICE_84
ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
                  --------
                   10.160   (27.4% logic, 72.6% route), 7 logic levels.

 Clock Skew Details: 

      Source Clock Path PHI2 to SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path PHI2 to SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 164.629ns (weighted slack = 329.258ns)
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Bank_i1  (from PHI2_c +)
   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
                   FF                        CmdUFMCLK_380

   Delay:              10.106ns  (23.9% logic, 76.1% route), 6 logic levels.

 Constraint Details:

     10.106ns physical path delay SLICE_93 to SLICE_83 meets
    175.000ns delay constraint less
      0.000ns skew and
      0.265ns CE_SET requirement (totaling 174.735ns) by 164.629ns

 Physical Path Details:

      Data path SLICE_93 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q1 SLICE_93 (from PHI2_c)
ROUTE         1     1.251       R2C2C.Q1 to R2C6C.D0       Bank_1
CTOF_DEL    ---     0.371       R2C6C.D0 to       R2C6C.F0 SLICE_101
ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
                  --------
                   10.106   (23.9% logic, 76.1% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path PHI2 to SLICE_93:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R2C2C.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path PHI2 to SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 164.698ns (weighted slack = 329.396ns)
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Bank_i4  (from PHI2_c +)
   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)

   Delay:              10.037ns  (24.1% logic, 75.9% route), 6 logic levels.

 Constraint Details:

     10.037ns physical path delay SLICE_90 to SLICE_77 meets
    175.000ns delay constraint less
      0.000ns skew and
      0.265ns CE_SET requirement (totaling 174.735ns) by 164.698ns

 Physical Path Details:

      Data path SLICE_90 to SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_90 (from PHI2_c)
ROUTE         1     1.643       R2C2B.Q0 to R2C6C.B0       Bank_4
CTOF_DEL    ---     0.371       R2C6C.B0 to       R2C6C.F0 SLICE_101
ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
                  --------
                   10.037   (24.1% logic, 75.9% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path PHI2 to SLICE_90:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path PHI2 to SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 164.768ns (weighted slack = 329.536ns)
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Bank_i5  (from PHI2_c +)
   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)

   Delay:               9.967ns  (28.0% logic, 72.0% route), 7 logic levels.

 Constraint Details:

      9.967ns physical path delay SLICE_90 to SLICE_77 meets
    175.000ns delay constraint less
      0.000ns skew and
      0.265ns CE_SET requirement (totaling 174.735ns) by 164.768ns

 Physical Path Details:

      Data path SLICE_90 to SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q1 SLICE_90 (from PHI2_c)
ROUTE         1     0.636       R2C2B.Q1 to R2C2B.A1       Bank_5
CTOF_DEL    ---     0.371       R2C2B.A1 to       R2C2B.F1 SLICE_90
ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
                  --------
                    9.967   (28.0% logic, 72.0% route), 7 logic levels.

 Clock Skew Details: 

      Source Clock Path PHI2 to SLICE_90:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path PHI2 to SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
                  --------
                    3.671   (0.0% logic, 100.0% route), 0 logic levels.

Report:   22.150ns is the minimum period for this preference.


================================================================================
Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 348.000ns
         The internal maximum frequency of the following component is 500.000 MHz

 Logical Details:  Cell type  Pin name       Component name

   Destination:    FSLICE     CLK            SLICE_73

   Delay:               2.000ns -- based on Minimum Pulse Width

Report:    2.000ns is the minimum period for this preference.


================================================================================
Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 348.000ns
         The internal maximum frequency of the following component is 500.000 MHz

 Logical Details:  Cell type  Pin name       Component name

   Destination:    FSLICE     CLK            SLICE_74

   Delay:               2.000ns -- based on Minimum Pulse Width

Report:    2.000ns is the minimum period for this preference.


================================================================================
Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
            10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 

Passed: The following path meets requirements by 7.341ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)

   Delay:               8.415ns  (28.7% logic, 71.3% route), 6 logic levels.

 Constraint Details:

      8.415ns physical path delay SLICE_7 to SLICE_56 meets
     16.000ns delay constraint less
      0.000ns skew and
      0.244ns CE_SET requirement (totaling 15.756ns) by 7.341ns

 Physical Path Details:

      Data path SLICE_7 to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
                  --------
                    8.415   (28.7% logic, 71.3% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path RCLK to SLICE_7:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path RCLK to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 7.520ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)

   Delay:               8.236ns  (29.3% logic, 70.7% route), 6 logic levels.

 Constraint Details:

      8.236ns physical path delay SLICE_7 to SLICE_85 meets
     16.000ns delay constraint less
      0.000ns skew and
      0.244ns CE_SET requirement (totaling 15.756ns) by 7.520ns

 Physical Path Details:

      Data path SLICE_7 to SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
                  --------
                    8.236   (29.3% logic, 70.7% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path RCLK to SLICE_7:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path RCLK to SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 7.549ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)

   Delay:               8.207ns  (29.4% logic, 70.6% route), 6 logic levels.

 Constraint Details:

      8.207ns physical path delay SLICE_7 to SLICE_56 meets
     16.000ns delay constraint less
      0.000ns skew and
      0.244ns CE_SET requirement (totaling 15.756ns) by 7.549ns

 Physical Path Details:

      Data path SLICE_7 to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q0 SLICE_7 (from RCLK_c)
ROUTE         3     1.267       R8C8D.Q0 to R8C9D.C1       FS_14
CTOF_DEL    ---     0.371       R8C9D.C1 to       R8C9D.F1 SLICE_78
ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
                  --------
                    8.207   (29.4% logic, 70.6% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path RCLK to SLICE_7:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path RCLK to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 7.728ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)

   Delay:               8.028ns  (30.1% logic, 69.9% route), 6 logic levels.

 Constraint Details:

      8.028ns physical path delay SLICE_7 to SLICE_85 meets
     16.000ns delay constraint less
      0.000ns skew and
      0.244ns CE_SET requirement (totaling 15.756ns) by 7.728ns

 Physical Path Details:

      Data path SLICE_7 to SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q0 SLICE_7 (from RCLK_c)
ROUTE         3     1.267       R8C8D.Q0 to R8C9D.C1       FS_14
CTOF_DEL    ---     0.371       R8C9D.C1 to       R8C9D.F1 SLICE_78
ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
                  --------
                    8.028   (30.1% logic, 69.9% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path RCLK to SLICE_7:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path RCLK to SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 7.768ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)

   Delay:               7.988ns  (30.2% logic, 69.8% route), 6 logic levels.

 Constraint Details:

      7.988ns physical path delay SLICE_8 to SLICE_56 meets
     16.000ns delay constraint less
      0.000ns skew and
      0.244ns CE_SET requirement (totaling 15.756ns) by 7.768ns

 Physical Path Details:

      Data path SLICE_8 to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q1 SLICE_8 (from RCLK_c)
ROUTE         3     1.048       R8C8C.Q1 to R8C9D.A1       FS_13
CTOF_DEL    ---     0.371       R8C9D.A1 to       R8C9D.F1 SLICE_78
ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
                  --------
                    7.988   (30.2% logic, 69.8% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path RCLK to SLICE_8:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path RCLK to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 7.947ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)

   Delay:               7.809ns  (30.9% logic, 69.1% route), 6 logic levels.

 Constraint Details:

      7.809ns physical path delay SLICE_8 to SLICE_85 meets
     16.000ns delay constraint less
      0.000ns skew and
      0.244ns CE_SET requirement (totaling 15.756ns) by 7.947ns

 Physical Path Details:

      Data path SLICE_8 to SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q1 SLICE_8 (from RCLK_c)
ROUTE         3     1.048       R8C8C.Q1 to R8C9D.A1       FS_13
CTOF_DEL    ---     0.371       R8C9D.A1 to       R8C9D.F1 SLICE_78
ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
                  --------
                    7.809   (30.9% logic, 69.1% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path RCLK to SLICE_8:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path RCLK to SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 8.079ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)

   Delay:               7.677ns  (26.6% logic, 73.4% route), 5 logic levels.

 Constraint Details:

      7.677ns physical path delay SLICE_7 to SLICE_56 meets
     16.000ns delay constraint less
      0.000ns skew and
      0.244ns CE_SET requirement (totaling 15.756ns) by 8.079ns

 Physical Path Details:

      Data path SLICE_7 to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
ROUTE         3     0.989       R8C9D.F1 to R8C9B.A1       n10
CTOF_DEL    ---     0.371       R8C9B.A1 to       R8C9B.F1 SLICE_94
ROUTE         1     1.384       R8C9B.F1 to R9C9A.A1       n2292
CTOF_DEL    ---     0.371       R9C9A.A1 to       R9C9A.F1 SLICE_77
ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
                  --------
                    7.677   (26.6% logic, 73.4% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path RCLK to SLICE_7:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path RCLK to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 8.092ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FS_571__i12  (from RCLK_c +)
   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)

   Delay:               7.664ns  (31.5% logic, 68.5% route), 6 logic levels.

 Constraint Details:

      7.664ns physical path delay SLICE_8 to SLICE_56 meets
     16.000ns delay constraint less
      0.000ns skew and
      0.244ns CE_SET requirement (totaling 15.756ns) by 8.092ns

 Physical Path Details:

      Data path SLICE_8 to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q0 SLICE_8 (from RCLK_c)
ROUTE         3     0.724       R8C8C.Q0 to R8C9D.D1       FS_12
CTOF_DEL    ---     0.371       R8C9D.D1 to       R8C9D.F1 SLICE_78
ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
                  --------
                    7.664   (31.5% logic, 68.5% route), 6 logic levels.

 Clock Skew Details: 

      Source Clock Path RCLK to SLICE_8:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path RCLK to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 8.177ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FS_571__i1  (from RCLK_c +)
   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)

   Delay:               7.579ns  (27.0% logic, 73.0% route), 5 logic levels.

 Constraint Details:

      7.579ns physical path delay SLICE_5 to SLICE_56 meets
     16.000ns delay constraint less
      0.000ns skew and
      0.244ns CE_SET requirement (totaling 15.756ns) by 8.177ns

 Physical Path Details:

      Data path SLICE_5 to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R8C7A.CLK to       R8C7A.Q1 SLICE_5 (from RCLK_c)
ROUTE         2     1.108       R8C7A.Q1 to R7C7D.B1       FS_1
CTOF_DEL    ---     0.371       R7C7D.B1 to       R7C7D.F1 SLICE_68
ROUTE         1     1.487       R7C7D.F1 to R6C9B.A0       n2164
CTOF_DEL    ---     0.371       R6C9B.A0 to       R6C9B.F0 SLICE_75
ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
                  --------
                    7.579   (27.0% logic, 73.0% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path RCLK to SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R8C7A.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path RCLK to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 8.243ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FS_571__i2  (from RCLK_c +)
   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)

   Delay:               7.513ns  (27.2% logic, 72.8% route), 5 logic levels.

 Constraint Details:

      7.513ns physical path delay SLICE_4 to SLICE_56 meets
     16.000ns delay constraint less
      0.000ns skew and
      0.244ns CE_SET requirement (totaling 15.756ns) by 8.243ns

 Physical Path Details:

      Data path SLICE_4 to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R8C7B.CLK to       R8C7B.Q0 SLICE_4 (from RCLK_c)
ROUTE         2     1.042       R8C7B.Q0 to R7C7D.A1       FS_2
CTOF_DEL    ---     0.371       R7C7D.A1 to       R7C7D.F1 SLICE_68
ROUTE         1     1.487       R7C7D.F1 to R6C9B.A0       n2164
CTOF_DEL    ---     0.371       R6C9B.A0 to       R6C9B.F0 SLICE_75
ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
                  --------
                    7.513   (27.2% logic, 72.8% route), 5 logic levels.

 Clock Skew Details: 

      Source Clock Path RCLK to SLICE_4:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R8C7B.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path RCLK to SLICE_56:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

Report:    8.659ns is the minimum period for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 4.999ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              RA10_368  (from RCLK_c +)
   Destination:    Port       Pad            RA[10]

   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_55 and
      5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
     12.500ns offset RCLK to RA[10] by 4.999ns

 Physical Path Details:

      Clock path RCLK to SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C5A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_55 to RA[10]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
ROUTE         1     0.817       R2C5A.Q0 to 87.PADDO       n974
DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
                  --------
                    5.013   (83.7% logic, 16.3% route), 2 logic levels.

Report:    7.501ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 6.396ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              RA10_368  (from RCLK_c +)
   Destination:    Port       Pad            RA[10]

   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_55 and
      4.797ns delay SLICE_55 to RA[10] (totaling 6.396ns) meets
      0.000ns hold offset RCLK to RA[10] by 6.396ns

 Physical Path Details:

      Clock path RCLK to SLICE_55:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C5A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_55 to RA[10]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
ROUTE         1     0.646       R2C5A.Q0 to 87.PADDO       n974
DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
                  --------
                    4.797   (86.5% logic, 13.5% route), 2 logic levels.

Report:    6.396ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 1.477ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[9]

   Data Path Delay:     8.535ns  (53.5% logic, 46.5% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      8.535ns delay SLICE_64 to RA[9] (totaling 11.023ns) meets
     12.500ns offset RCLK to RA[9] by 1.477ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RA[9]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.796       R2C6A.Q0 to R6C9A.D1       nRowColSel
CTOF_DEL    ---     0.371       R6C9A.D1 to       R6C9A.F1 SLICE_87
ROUTE         1     2.172       R6C9A.F1 to 85.PADDO       RA_c_9
DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
                  --------
                    8.535   (53.5% logic, 46.5% route), 3 logic levels.

Report:   11.023ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 9.323ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[9]

   Data Path Delay:     7.724ns  (57.6% logic, 42.4% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      7.724ns delay SLICE_64 to RA[9] (totaling 9.323ns) meets
      0.000ns hold offset RCLK to RA[9] by 9.323ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RA[9]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.549       R2C6A.Q0 to R6C9A.D1       nRowColSel
CTOF_DEL    ---     0.301       R6C9A.D1 to       R6C9A.F1 SLICE_87
ROUTE         1     1.723       R6C9A.F1 to 85.PADDO       RA_c_9
DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
                  --------
                    7.724   (57.6% logic, 42.4% route), 3 logic levels.

Report:    9.323ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 2.460ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[8]

   Data Path Delay:     7.552ns  (60.5% logic, 39.5% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      7.552ns delay SLICE_64 to RA[8] (totaling 10.040ns) meets
     12.500ns offset RCLK to RA[8] by 2.460ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RA[8]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.459       R2C6A.Q0 to R2C2A.C0       nRowColSel
CTOF_DEL    ---     0.371       R2C2A.C0 to       R2C2A.F0 SLICE_98
ROUTE         1     1.526       R2C2A.F0 to 96.PADDO       RA_c_8
DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
                  --------
                    7.552   (60.5% logic, 39.5% route), 3 logic levels.

Report:   10.040ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 8.446ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[8]

   Data Path Delay:     6.847ns  (65.0% logic, 35.0% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      6.847ns delay SLICE_64 to RA[8] (totaling 8.446ns) meets
      0.000ns hold offset RCLK to RA[8] by 8.446ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RA[8]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.230       R2C6A.Q0 to R2C2A.C0       nRowColSel
CTOF_DEL    ---     0.301       R2C2A.C0 to       R2C2A.F0 SLICE_98
ROUTE         1     1.165       R2C2A.F0 to 96.PADDO       RA_c_8
DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
                  --------
                    6.847   (65.0% logic, 35.0% route), 3 logic levels.

Report:    8.446ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 2.106ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[7]

   Data Path Delay:     7.906ns  (57.8% logic, 42.2% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      7.906ns delay SLICE_64 to RA[7] (totaling 10.394ns) meets
     12.500ns offset RCLK to RA[7] by 2.106ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RA[7]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     0.895       R2C6A.Q0 to R2C6A.C1       nRowColSel
CTOF_DEL    ---     0.371       R2C6A.C1 to       R2C6A.F1 SLICE_64
ROUTE         1     2.444       R2C6A.F1 to 100.PADDO      RA_c_7
DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
                  --------
                    7.906   (57.8% logic, 42.2% route), 3 logic levels.

Report:   10.394ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 8.766ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[7]

   Data Path Delay:     7.167ns  (62.1% logic, 37.9% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      7.167ns delay SLICE_64 to RA[7] (totaling 8.766ns) meets
      0.000ns hold offset RCLK to RA[7] by 8.766ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RA[7]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     0.741       R2C6A.Q0 to R2C6A.C1       nRowColSel
CTOF_DEL    ---     0.301       R2C6A.C1 to       R2C6A.F1 SLICE_64
ROUTE         1     1.974       R2C6A.F1 to 100.PADDO      RA_c_7
DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
                  --------
                    7.167   (62.1% logic, 37.9% route), 3 logic levels.

Report:    8.766ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 2.002ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[6]

   Data Path Delay:     8.010ns  (57.0% logic, 43.0% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      8.010ns delay SLICE_64 to RA[6] (totaling 10.498ns) meets
     12.500ns offset RCLK to RA[6] by 2.002ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RA[6]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.459       R2C6A.Q0 to R2C2A.C1       nRowColSel
CTOF_DEL    ---     0.371       R2C2A.C1 to       R2C2A.F1 SLICE_98
ROUTE         1     1.984       R2C2A.F1 to 91.PADDO       RA_c_6
DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
                  --------
                    8.010   (57.0% logic, 43.0% route), 3 logic levels.

Report:   10.498ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 8.813ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[6]

   Data Path Delay:     7.214ns  (61.7% logic, 38.3% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      7.214ns delay SLICE_64 to RA[6] (totaling 8.813ns) meets
      0.000ns hold offset RCLK to RA[6] by 8.813ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RA[6]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.230       R2C6A.Q0 to R2C2A.C1       nRowColSel
CTOF_DEL    ---     0.301       R2C2A.C1 to       R2C2A.F1 SLICE_98
ROUTE         1     1.532       R2C2A.F1 to 91.PADDO       RA_c_6
DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
                  --------
                    7.214   (61.7% logic, 38.3% route), 3 logic levels.

Report:    8.813ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 1.141ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[5]

   Data Path Delay:     8.871ns  (51.5% logic, 48.5% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      8.871ns delay SLICE_64 to RA[5] (totaling 11.359ns) meets
     12.500ns offset RCLK to RA[5] by 1.141ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RA[5]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.736       R2C6A.Q0 to R8C9C.D1       nRowColSel
CTOF_DEL    ---     0.371       R8C9C.D1 to       R8C9C.F1 SLICE_95
ROUTE         1     2.568       R8C9C.F1 to 95.PADDO       RA_c_5
DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
                  --------
                    8.871   (51.5% logic, 48.5% route), 3 logic levels.

Report:   11.359ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 9.559ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[5]

   Data Path Delay:     7.960ns  (55.9% logic, 44.1% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      7.960ns delay SLICE_64 to RA[5] (totaling 9.559ns) meets
      0.000ns hold offset RCLK to RA[5] by 9.559ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RA[5]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.466       R2C6A.Q0 to R8C9C.D1       nRowColSel
CTOF_DEL    ---     0.301       R8C9C.D1 to       R8C9C.F1 SLICE_95
ROUTE         1     2.042       R8C9C.F1 to 95.PADDO       RA_c_5
DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
                  --------
                    7.960   (55.9% logic, 44.1% route), 3 logic levels.

Report:    9.559ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 2.458ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[4]

   Data Path Delay:     7.554ns  (60.5% logic, 39.5% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      7.554ns delay SLICE_64 to RA[4] (totaling 10.042ns) meets
     12.500ns offset RCLK to RA[4] by 2.458ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RA[4]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.459       R2C6A.Q0 to R2C2C.C1       nRowColSel
CTOF_DEL    ---     0.371       R2C2C.C1 to       R2C2C.F1 SLICE_93
ROUTE         1     1.528       R2C2C.F1 to 99.PADDO       RA_c_4
DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
                  --------
                    7.554   (60.5% logic, 39.5% route), 3 logic levels.

Report:   10.042ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 8.445ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[4]

   Data Path Delay:     6.846ns  (65.0% logic, 35.0% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      6.846ns delay SLICE_64 to RA[4] (totaling 8.445ns) meets
      0.000ns hold offset RCLK to RA[4] by 8.445ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RA[4]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.230       R2C6A.Q0 to R2C2C.C1       nRowColSel
CTOF_DEL    ---     0.301       R2C2C.C1 to       R2C2C.F1 SLICE_93
ROUTE         1     1.164       R2C2C.F1 to 99.PADDO       RA_c_4
DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
                  --------
                    6.846   (65.0% logic, 35.0% route), 3 logic levels.

Report:    8.445ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 2.216ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[3]

   Data Path Delay:     7.796ns  (58.6% logic, 41.4% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      7.796ns delay SLICE_64 to RA[3] (totaling 10.284ns) meets
     12.500ns offset RCLK to RA[3] by 2.216ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RA[3]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.245       R2C6A.Q0 to R2C3A.D1       nRowColSel
CTOF_DEL    ---     0.371       R2C3A.D1 to       R2C3A.F1 SLICE_92
ROUTE         1     1.984       R2C3A.F1 to 97.PADDO       RA_c_3
DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
                  --------
                    7.796   (58.6% logic, 41.4% route), 3 logic levels.

Report:   10.284ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 8.599ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[3]

   Data Path Delay:     7.000ns  (63.6% logic, 36.4% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      7.000ns delay SLICE_64 to RA[3] (totaling 8.599ns) meets
      0.000ns hold offset RCLK to RA[3] by 8.599ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RA[3]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.016       R2C6A.Q0 to R2C3A.D1       nRowColSel
CTOF_DEL    ---     0.301       R2C3A.D1 to       R2C3A.F1 SLICE_92
ROUTE         1     1.532       R2C3A.F1 to 97.PADDO       RA_c_3
DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
                  --------
                    7.000   (63.6% logic, 36.4% route), 3 logic levels.

Report:    8.599ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 1.999ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[2]

   Data Path Delay:     8.013ns  (57.0% logic, 43.0% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      8.013ns delay SLICE_64 to RA[2] (totaling 10.501ns) meets
     12.500ns offset RCLK to RA[2] by 1.999ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RA[2]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.459       R2C6A.Q0 to R2C2B.C0       nRowColSel
CTOF_DEL    ---     0.371       R2C2B.C0 to       R2C2B.F0 SLICE_90
ROUTE         1     1.987       R2C2B.F0 to 94.PADDO       RA_c_2
DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
                  --------
                    8.013   (57.0% logic, 43.0% route), 3 logic levels.

Report:   10.501ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 8.849ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[2]

   Data Path Delay:     7.250ns  (61.4% logic, 38.6% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      7.250ns delay SLICE_64 to RA[2] (totaling 8.849ns) meets
      0.000ns hold offset RCLK to RA[2] by 8.849ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RA[2]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.230       R2C6A.Q0 to R2C2B.C0       nRowColSel
CTOF_DEL    ---     0.301       R2C2B.C0 to       R2C2B.F0 SLICE_90
ROUTE         1     1.568       R2C2B.F0 to 94.PADDO       RA_c_2
DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
                  --------
                    7.250   (61.4% logic, 38.6% route), 3 logic levels.

Report:    8.849ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 2.216ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[1]

   Data Path Delay:     7.796ns  (58.6% logic, 41.4% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      7.796ns delay SLICE_64 to RA[1] (totaling 10.284ns) meets
     12.500ns offset RCLK to RA[1] by 2.216ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RA[1]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.245       R2C6A.Q0 to R2C3A.D0       nRowColSel
CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_92
ROUTE         1     1.984       R2C3A.F0 to 89.PADDO       RA_c_1
DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
                  --------
                    7.796   (58.6% logic, 41.4% route), 3 logic levels.

Report:   10.284ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 8.599ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[1]

   Data Path Delay:     7.000ns  (63.6% logic, 36.4% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      7.000ns delay SLICE_64 to RA[1] (totaling 8.599ns) meets
      0.000ns hold offset RCLK to RA[1] by 8.599ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RA[1]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.016       R2C6A.Q0 to R2C3A.D0       nRowColSel
CTOF_DEL    ---     0.301       R2C3A.D0 to       R2C3A.F0 SLICE_92
ROUTE         1     1.532       R2C3A.F0 to 89.PADDO       RA_c_1
DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
                  --------
                    7.000   (63.6% logic, 36.4% route), 3 logic levels.

Report:    8.599ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 2.454ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[0]

   Data Path Delay:     7.558ns  (60.4% logic, 39.6% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      7.558ns delay SLICE_64 to RA[0] (totaling 10.046ns) meets
     12.500ns offset RCLK to RA[0] by 2.454ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RA[0]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.459       R2C6A.Q0 to R2C2C.C0       nRowColSel
CTOF_DEL    ---     0.371       R2C2C.C0 to       R2C2C.F0 SLICE_93
ROUTE         1     1.532       R2C2C.F0 to 98.PADDO       RA_c_0
DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
                  --------
                    7.558   (60.4% logic, 39.6% route), 3 logic levels.

Report:   10.046ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 8.442ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RA[0]

   Data Path Delay:     6.843ns  (65.1% logic, 34.9% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      6.843ns delay SLICE_64 to RA[0] (totaling 8.442ns) meets
      0.000ns hold offset RCLK to RA[0] by 8.442ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RA[0]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.230       R2C6A.Q0 to R2C2C.C0       nRowColSel
CTOF_DEL    ---     0.301       R2C2C.C0 to       R2C2C.F0 SLICE_93
ROUTE         1     1.161       R2C2C.F0 to 98.PADDO       RA_c_0
DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
                  --------
                    6.843   (65.1% logic, 34.9% route), 3 logic levels.

Report:    8.442ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 4.999ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRCS_364  (from RCLK_c +)
   Destination:    Port       Pad            nRCS

   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_60 and
      5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
     12.500ns offset RCLK to nRCS by 4.999ns

 Physical Path Details:

      Clock path RCLK to SLICE_60:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C9C.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_60 to nRCS:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
ROUTE         1     0.817       R2C9C.Q0 to 77.PADDO       nRCS_c
DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
                  --------
                    5.013   (83.7% logic, 16.3% route), 2 logic levels.

Report:    7.501ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 6.396ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRCS_364  (from RCLK_c +)
   Destination:    Port       Pad            nRCS

   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_60 and
      4.797ns delay SLICE_60 to nRCS (totaling 6.396ns) meets
      0.000ns hold offset RCLK to nRCS by 6.396ns

 Physical Path Details:

      Clock path RCLK to SLICE_60:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C9C.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_60 to nRCS:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
ROUTE         1     0.646       R2C9C.Q0 to 77.PADDO       nRCS_c
DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
                  --------
                    4.797   (86.5% logic, 13.5% route), 2 logic levels.

Report:    6.396ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 4.999ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              RCKE_363  (from RCLK_c +)
   Destination:    Port       Pad            RCKE

   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_34 and
      5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
     12.500ns offset RCLK to RCKE by 4.999ns

 Physical Path Details:

      Clock path RCLK to SLICE_34:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C7C.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_34 to RCKE:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
ROUTE         4     0.817       R2C7C.Q0 to 82.PADDO       RCKE_c
DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
                  --------
                    5.013   (83.7% logic, 16.3% route), 2 logic levels.

Report:    7.501ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 6.396ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              RCKE_363  (from RCLK_c +)
   Destination:    Port       Pad            RCKE

   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_34 and
      4.797ns delay SLICE_34 to RCKE (totaling 6.396ns) meets
      0.000ns hold offset RCLK to RCKE by 6.396ns

 Physical Path Details:

      Clock path RCLK to SLICE_34:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C7C.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_34 to RCKE:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
ROUTE         4     0.646       R2C7C.Q0 to 82.PADDO       RCKE_c
DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
                  --------
                    4.797   (86.5% logic, 13.5% route), 2 logic levels.

Report:    6.396ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 3.833ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRWE_367  (from RCLK_c +)
   Destination:    Port       Pad            nRWE

   Data Path Delay:     6.179ns  (67.9% logic, 32.1% route), 2 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_63 and
      6.179ns delay SLICE_63 to nRWE (totaling 8.667ns) meets
     12.500ns offset RCLK to nRWE by 3.833ns

 Physical Path Details:

      Clock path RCLK to SLICE_63:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C7A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_63 to nRWE:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C7A.CLK to       R2C7A.Q0 SLICE_63 (from RCLK_c)
ROUTE         1     1.983       R2C7A.Q0 to 72.PADDO       nRWE_c
DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
                  --------
                    6.179   (67.9% logic, 32.1% route), 2 logic levels.

Report:    8.667ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 7.321ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRWE_367  (from RCLK_c +)
   Destination:    Port       Pad            nRWE

   Data Path Delay:     5.722ns  (72.5% logic, 27.5% route), 2 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_63 and
      5.722ns delay SLICE_63 to nRWE (totaling 7.321ns) meets
      0.000ns hold offset RCLK to nRWE by 7.321ns

 Physical Path Details:

      Clock path RCLK to SLICE_63:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C7A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_63 to nRWE:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C7A.CLK to       R2C7A.Q0 SLICE_63 (from RCLK_c)
ROUTE         1     1.571       R2C7A.Q0 to 72.PADDO       nRWE_c
DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
                  --------
                    5.722   (72.5% logic, 27.5% route), 2 logic levels.

Report:    7.321ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 3.813ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
   Destination:    Port       Pad            nRRAS

   Data Path Delay:     6.199ns  (67.7% logic, 32.3% route), 2 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_61 and
      6.199ns delay SLICE_61 to nRRAS (totaling 8.687ns) meets
     12.500ns offset RCLK to nRRAS by 3.813ns

 Physical Path Details:

      Clock path RCLK to SLICE_61:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R4C9B.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_61 to nRRAS:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R4C9B.CLK to       R4C9B.Q0 SLICE_61 (from RCLK_c)
ROUTE         2     2.003       R4C9B.Q0 to 73.PADDO       nRRAS_c
DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
                  --------
                    6.199   (67.7% logic, 32.3% route), 2 logic levels.

Report:    8.687ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 7.334ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
   Destination:    Port       Pad            nRRAS

   Data Path Delay:     5.735ns  (72.4% logic, 27.6% route), 2 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_61 and
      5.735ns delay SLICE_61 to nRRAS (totaling 7.334ns) meets
      0.000ns hold offset RCLK to nRRAS by 7.334ns

 Physical Path Details:

      Clock path RCLK to SLICE_61:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R4C9B.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_61 to nRRAS:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R4C9B.CLK to       R4C9B.Q0 SLICE_61 (from RCLK_c)
ROUTE         2     1.584       R4C9B.Q0 to 73.PADDO       nRRAS_c
DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
                  --------
                    5.735   (72.4% logic, 27.6% route), 2 logic levels.

Report:    7.334ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 4.999ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
   Destination:    Port       Pad            nRCAS

   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_58 and
      5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
     12.500ns offset RCLK to nRCAS by 4.999ns

 Physical Path Details:

      Clock path RCLK to SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C9B.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_58 to nRCAS:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
ROUTE         1     0.817       R2C9B.Q0 to 78.PADDO       nRCAS_c
DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
                  --------
                    5.013   (83.7% logic, 16.3% route), 2 logic levels.

Report:    7.501ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 6.396ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
   Destination:    Port       Pad            nRCAS

   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_58 and
      4.797ns delay SLICE_58 to nRCAS (totaling 6.396ns) meets
      0.000ns hold offset RCLK to nRCAS by 6.396ns

 Physical Path Details:

      Clock path RCLK to SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C9B.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_58 to nRCAS:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
ROUTE         1     0.646       R2C9B.Q0 to 78.PADDO       nRCAS_c
DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
                  --------
                    4.797   (86.5% logic, 13.5% route), 2 logic levels.

Report:    6.396ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 1.989ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RDQMH

   Data Path Delay:     8.023ns  (56.9% logic, 43.1% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      8.023ns delay SLICE_64 to RDQMH (totaling 10.511ns) meets
     12.500ns offset RCLK to RDQMH by 1.989ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RDQMH:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.796       R2C6A.Q0 to R6C9A.D0       nRowColSel
CTOF_DEL    ---     0.371       R6C9A.D0 to       R6C9A.F0 SLICE_87
ROUTE         1     1.660       R6C9A.F0 to 76.PADDO       RDQMH_c
DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
                  --------
                    8.023   (56.9% logic, 43.1% route), 3 logic levels.

Report:   10.511ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 8.888ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RDQMH

   Data Path Delay:     7.289ns  (61.1% logic, 38.9% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      7.289ns delay SLICE_64 to RDQMH (totaling 8.888ns) meets
      0.000ns hold offset RCLK to RDQMH by 8.888ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RDQMH:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.549       R2C6A.Q0 to R6C9A.D0       nRowColSel
CTOF_DEL    ---     0.301       R6C9A.D0 to       R6C9A.F0 SLICE_87
ROUTE         1     1.288       R6C9A.F0 to 76.PADDO       RDQMH_c
DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
                  --------
                    7.289   (61.1% logic, 38.9% route), 3 logic levels.

Report:    8.888ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 2.892ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RDQML

   Data Path Delay:     7.120ns  (64.1% logic, 35.9% route), 3 logic levels.

   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.

 Constraint Details:
      2.488ns delay RCLK to SLICE_64 and
      7.120ns delay SLICE_64 to RDQML (totaling 9.608ns) meets
     12.500ns offset RCLK to RDQML by 2.892ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    2.488   (42.7% logic, 57.3% route), 1 logic levels.

      Data path SLICE_64 to RDQML:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.736       R2C6A.Q0 to R8C9C.D0       nRowColSel
CTOF_DEL    ---     0.371       R8C9C.D0 to       R8C9C.F0 SLICE_95
ROUTE         1     0.817       R8C9C.F0 to 61.PADDO       RDQML_c
DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
                  --------
                    7.120   (64.1% logic, 35.9% route), 3 logic levels.

Report:    9.608ns is the minimum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 8.163ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
   Destination:    Port       Pad            RDQML

   Data Path Delay:     6.564ns  (67.8% logic, 32.2% route), 3 logic levels.

   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.

 Constraint Details:
      1.599ns delay RCLK to SLICE_64 and
      6.564ns delay SLICE_64 to RDQML (totaling 8.163ns) meets
      0.000ns hold offset RCLK to RDQML by 8.163ns

 Physical Path Details:

      Clock path RCLK to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
                  --------
                    1.599   (54.2% logic, 45.8% route), 1 logic levels.

      Data path SLICE_64 to RDQML:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
ROUTE        13     1.466       R2C6A.Q0 to R8C9C.D0       nRowColSel
CTOF_DEL    ---     0.301       R8C9C.D0 to       R8C9C.F0 SLICE_95
ROUTE         1     0.646       R8C9C.F0 to 61.PADDO       RDQML_c
DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
                  --------
                    6.564   (67.8% logic, 32.2% route), 3 logic levels.

Report:    8.163ns is the maximum offset for this preference.


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    22.150 ns|   7  
                                        |             |             |
PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
                                        |             |             |
PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
                                        |             |             |
PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     8.659 ns|   6  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    11.023 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.323 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.040 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.446 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.394 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.766 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.498 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.813 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    11.359 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.559 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.042 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.445 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.284 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.599 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.501 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.849 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.284 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.599 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.046 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.442 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.667 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.321 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.687 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.334 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
                                        |             |             |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.511 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.888 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.608 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.163 ns|   3  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
                                        |             |             |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 4 clocks:

Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: RCLK_c   Source: RCLK.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.

Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
   No transfer within this clock domain is found

Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;

   Data transfers from:
   Clock Domain: nCRAS_c   Source: nCRAS.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.

   Clock Domain: PHI2_c   Source: PHI2.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.

Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;

   Data transfers from:
   Clock Domain: RCLK_c   Source: RCLK.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.


Timing summary (Setup):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 538 paths, 6 nets, and 440 connections (71.54% coverage)