-------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 Mon Aug 16 20:38:58 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: RAM2GS Device,speed: LCMXO640C,M Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Derating parameters ------------------- Voltage: 3.300 V ================================================================================ Preference: PERIOD NET "PHI2_c" 350.000000 ns ; 10 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.447ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ADSubmitted_375 (from PHI2_c -) Destination: FF Data in ADSubmitted_375 (to PHI2_c -) Delay: 0.424ns (61.8% logic, 38.2% route), 2 logic levels. Constraint Details: 0.424ns physical path delay SLICE_9 to SLICE_9 meets -0.023ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.023ns) by 0.447ns Physical Path Details: Data path SLICE_9 to SLICE_9: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.170 R4C5C.CLK to R4C5C.Q0 SLICE_9 (from PHI2_c) ROUTE 2 0.162 R4C5C.Q0 to R4C5C.A0 ADSubmitted CTOF_DEL --- 0.092 R4C5C.A0 to R4C5C.F0 SLICE_9 ROUTE 1 0.000 R4C5C.F0 to R4C5C.DI0 n1355 (to PHI2_c) -------- 0.424 (61.8% logic, 38.2% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C5C.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C5C.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 1.244ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q C1Submitted_374 (from PHI2_c -) Destination: FF Data in CmdEnable_373 (to PHI2_c -) Delay: 1.215ns (41.6% logic, 58.4% route), 4 logic levels. Constraint Details: 1.215ns physical path delay SLICE_14 to SLICE_18 meets -0.029ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.029ns) by 1.244ns Physical Path Details: Data path SLICE_14 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.170 R4C5A.CLK to R4C5A.Q0 SLICE_14 (from PHI2_c) ROUTE 1 0.222 R4C5A.Q0 to R4C6C.C1 C1Submitted CTOOFX_DEL --- 0.151 R4C6C.C1 to R4C6C.OFX0 i26/SLICE_70 ROUTE 1 0.204 R4C6C.OFX0 to R4C6D.C1 n13 CTOF_DEL --- 0.092 R4C6D.C1 to R4C6D.F1 SLICE_80 ROUTE 1 0.123 R4C6D.F1 to R4C6D.C0 n6 CTOF_DEL --- 0.092 R4C6D.C0 to R4C6D.F0 SLICE_80 ROUTE 1 0.161 R4C6D.F0 to R4C6B.CE PHI2_N_114_enable_8 (to PHI2_c) -------- 1.215 (41.6% logic, 58.4% route), 4 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C5A.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C6B.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 1.249ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable_373 (from PHI2_c -) Destination: FF Data in CmdSubmitted_378 (to PHI2_c -) Delay: 1.220ns (29.0% logic, 71.0% route), 3 logic levels. Constraint Details: 1.220ns physical path delay SLICE_18 to SLICE_19 meets -0.029ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.029ns) by 1.249ns Physical Path Details: Data path SLICE_18 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.170 R4C6B.CLK to R4C6B.Q0 SLICE_18 (from PHI2_c) ROUTE 1 0.271 R4C6B.Q0 to R4C5B.B1 CmdEnable CTOF_DEL --- 0.092 R4C5B.B1 to R4C5B.F1 SLICE_76 ROUTE 3 0.132 R4C5B.F1 to R4C5B.C0 XOR8MEG_N_112 CTOF_DEL --- 0.092 R4C5B.C0 to R4C5B.F0 SLICE_76 ROUTE 2 0.463 R4C5B.F0 to R7C7C.CE PHI2_N_114_enable_6 (to PHI2_c) -------- 1.220 (29.0% logic, 71.0% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C6B.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R7C7C.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 1.287ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ADSubmitted_375 (from PHI2_c -) Destination: FF Data in CmdEnable_373 (to PHI2_c -) Delay: 1.258ns (40.5% logic, 59.5% route), 4 logic levels. Constraint Details: 1.258ns physical path delay SLICE_9 to SLICE_18 meets -0.029ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.029ns) by 1.287ns Physical Path Details: Data path SLICE_9 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.170 R4C5C.CLK to R4C5C.Q0 SLICE_9 (from PHI2_c) ROUTE 2 0.261 R4C5C.Q0 to R4C6C.A0 ADSubmitted CTOOFX_DEL --- 0.155 R4C6C.A0 to R4C6C.OFX0 i26/SLICE_70 ROUTE 1 0.204 R4C6C.OFX0 to R4C6D.C1 n13 CTOF_DEL --- 0.092 R4C6D.C1 to R4C6D.F1 SLICE_80 ROUTE 1 0.123 R4C6D.F1 to R4C6D.C0 n6 CTOF_DEL --- 0.092 R4C6D.C0 to R4C6D.F0 SLICE_80 ROUTE 1 0.161 R4C6D.F0 to R4C6B.CE PHI2_N_114_enable_8 (to PHI2_c) -------- 1.258 (40.5% logic, 59.5% route), 4 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C5C.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C6B.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 1.372ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable_373 (from PHI2_c -) Destination: FF Data in Cmdn8MEGEN_377 (to PHI2_c -) Delay: 1.343ns (26.4% logic, 73.6% route), 3 logic levels. Constraint Details: 1.343ns physical path delay SLICE_18 to SLICE_23 meets -0.029ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.029ns) by 1.372ns Physical Path Details: Data path SLICE_18 to SLICE_23: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.170 R4C6B.CLK to R4C6B.Q0 SLICE_18 (from PHI2_c) ROUTE 1 0.271 R4C6B.Q0 to R4C5B.B1 CmdEnable CTOF_DEL --- 0.092 R4C5B.B1 to R4C5B.F1 SLICE_76 ROUTE 3 0.132 R4C5B.F1 to R4C5B.C0 XOR8MEG_N_112 CTOF_DEL --- 0.092 R4C5B.C0 to R4C5B.F0 SLICE_76 ROUTE 2 0.586 R4C5B.F0 to R6C6A.CE PHI2_N_114_enable_6 (to PHI2_c) -------- 1.343 (26.4% logic, 73.6% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C6B.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_23: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R6C6A.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 1.447ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable_373 (from PHI2_c -) Destination: FF Data in XOR8MEG_376 (to PHI2_c -) Delay: 1.418ns (25.0% logic, 75.0% route), 3 logic levels. Constraint Details: 1.418ns physical path delay SLICE_18 to SLICE_94 meets -0.029ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.029ns) by 1.447ns Physical Path Details: Data path SLICE_18 to SLICE_94: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.170 R4C6B.CLK to R4C6B.Q0 SLICE_18 (from PHI2_c) ROUTE 1 0.271 R4C6B.Q0 to R4C5B.B1 CmdEnable CTOF_DEL --- 0.092 R4C5B.B1 to R4C5B.F1 SLICE_76 ROUTE 3 0.383 R4C5B.F1 to R7C6D.C0 XOR8MEG_N_112 CTOF_DEL --- 0.092 R7C6D.C0 to R7C6D.F0 SLICE_97 ROUTE 1 0.410 R7C6D.F0 to R8C9B.CE PHI2_N_114_enable_2 (to PHI2_c) -------- 1.418 (25.0% logic, 75.0% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C6B.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_94: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R8C9B.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 1.656ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable_373 (from PHI2_c -) Destination: FF Data in CmdUFMSDI_381 (to PHI2_c -) Delay: 1.627ns (21.8% logic, 78.2% route), 3 logic levels. Constraint Details: 1.627ns physical path delay SLICE_18 to SLICE_77 meets -0.029ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.029ns) by 1.656ns Physical Path Details: Data path SLICE_18 to SLICE_77: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.170 R4C6B.CLK to R4C6B.Q0 SLICE_18 (from PHI2_c) ROUTE 1 0.271 R4C6B.Q0 to R4C5B.B1 CmdEnable CTOF_DEL --- 0.092 R4C5B.B1 to R4C5B.F1 SLICE_76 ROUTE 3 0.335 R4C5B.F1 to R5C2A.D1 XOR8MEG_N_112 CTOF_DEL --- 0.092 R5C2A.D1 to R5C2A.F1 SLICE_73 ROUTE 2 0.667 R5C2A.F1 to R9C9A.CE PHI2_N_114_enable_7 (to PHI2_c) -------- 1.627 (21.8% logic, 78.2% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C6B.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_77: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R9C9A.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 1.779ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable_373 (from PHI2_c -) Destination: FF Data in CmdUFMCS_379 (to PHI2_c -) FF CmdUFMCLK_380 Delay: 1.750ns (20.2% logic, 79.8% route), 3 logic levels. Constraint Details: 1.750ns physical path delay SLICE_18 to SLICE_83 meets -0.029ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.029ns) by 1.779ns Physical Path Details: Data path SLICE_18 to SLICE_83: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.170 R4C6B.CLK to R4C6B.Q0 SLICE_18 (from PHI2_c) ROUTE 1 0.271 R4C6B.Q0 to R4C5B.B1 CmdEnable CTOF_DEL --- 0.092 R4C5B.B1 to R4C5B.F1 SLICE_76 ROUTE 3 0.335 R4C5B.F1 to R5C2A.D1 XOR8MEG_N_112 CTOF_DEL --- 0.092 R5C2A.D1 to R5C2A.F1 SLICE_73 ROUTE 2 0.790 R5C2A.F1 to R5C8B.CE PHI2_N_114_enable_7 (to PHI2_c) -------- 1.750 (20.2% logic, 79.8% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C6B.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_83: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R5C8B.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 175.792ns (weighted slack = 351.584ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q XOR8MEG_376 (from PHI2_c -) Destination: FF Data in RA11_353 (to PHI2_c +) Delay: 0.781ns (33.5% logic, 66.5% route), 2 logic levels. Constraint Details: 0.781ns physical path delay SLICE_94 to SLICE_31 meets -0.011ns DIN_HLD and -175.000ns delay constraint less 0.000ns skew requirement (totaling -175.011ns) by 175.792ns Physical Path Details: Data path SLICE_94 to SLICE_31: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.170 R8C9B.CLK to R8C9B.Q0 SLICE_94 (from PHI2_c) ROUTE 1 0.519 R8C9B.Q0 to R2C9A.B0 XOR8MEG CTOF_DEL --- 0.092 R2C9A.B0 to R2C9A.F0 SLICE_31 ROUTE 1 0.000 R2C9A.F0 to R2C9A.DI0 RA11_N_180 (to PHI2_c) -------- 0.781 (33.5% logic, 66.5% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_94: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R8C9B.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_31: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R2C9A.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 176.113ns (weighted slack = 352.226ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_i3 (from PHI2_c +) Destination: FF Data in C1Submitted_374 (to PHI2_c -) Delay: 1.084ns (31.5% logic, 68.5% route), 3 logic levels. Constraint Details: 1.084ns physical path delay SLICE_92 to SLICE_14 meets -0.029ns CE_HLD and -175.000ns delay constraint less 0.000ns skew requirement (totaling -175.029ns) by 176.113ns Physical Path Details: Data path SLICE_92 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C3A.CLK to R2C3A.Q1 SLICE_92 (from PHI2_c) ROUTE 1 0.344 R2C3A.Q1 to R2C5C.A1 Bank_3 CTOF_DEL --- 0.092 R2C5C.A1 to R2C5C.F1 SLICE_74 ROUTE 5 0.132 R2C5C.F1 to R2C5C.C0 n1279 CTOF_DEL --- 0.092 R2C5C.C0 to R2C5C.F0 SLICE_74 ROUTE 1 0.267 R2C5C.F0 to R4C5A.CE PHI2_N_114_enable_1 (to PHI2_c) -------- 1.084 (31.5% logic, 68.5% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_92: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R2C3A.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 14 1.120 39.PADDI to R4C5A.CLK PHI2_c -------- 1.120 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: PERIOD NET "RCLK_c" 16.000000 ns ; 10 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.339ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS_FSM__i2 (from RCLK_c +) Destination: FF Data in IS_FSM__i3 (to RCLK_c +) Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. Constraint Details: 0.318ns physical path delay SLICE_101 to SLICE_101 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.339ns Physical Path Details: Data path SLICE_101 to SLICE_101: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6C.CLK to R2C6C.Q0 SLICE_101 (from RCLK_c) ROUTE 1 0.161 R2C6C.Q0 to R2C6C.M1 n705 (to RCLK_c) -------- 0.318 (49.4% logic, 50.6% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_101: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R2C6C.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_101: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R2C6C.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.339ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS_FSM__i3 (from RCLK_c +) Destination: FF Data in IS_FSM__i4 (to RCLK_c +) Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. Constraint Details: 0.318ns physical path delay SLICE_101 to SLICE_81 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.339ns Physical Path Details: Data path SLICE_101 to SLICE_81: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6C.CLK to R2C6C.Q1 SLICE_101 (from RCLK_c) ROUTE 1 0.161 R2C6C.Q1 to R2C6B.M0 n704 (to RCLK_c) -------- 0.318 (49.4% logic, 50.6% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_101: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R2C6C.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_81: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R2C6B.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.339ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS_FSM__i6 (from RCLK_c +) Destination: FF Data in IS_FSM__i7 (to RCLK_c +) Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. Constraint Details: 0.318ns physical path delay SLICE_80 to SLICE_80 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.339ns Physical Path Details: Data path SLICE_80 to SLICE_80: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R4C6D.CLK to R4C6D.Q0 SLICE_80 (from RCLK_c) ROUTE 1 0.161 R4C6D.Q0 to R4C6D.M1 n701 (to RCLK_c) -------- 0.318 (49.4% logic, 50.6% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_80: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R4C6D.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_80: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R4C6D.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.339ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS_FSM__i4 (from RCLK_c +) Destination: FF Data in IS_FSM__i5 (to RCLK_c +) Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. Constraint Details: 0.318ns physical path delay SLICE_81 to SLICE_81 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.339ns Physical Path Details: Data path SLICE_81 to SLICE_81: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6B.CLK to R2C6B.Q0 SLICE_81 (from RCLK_c) ROUTE 1 0.161 R2C6B.Q0 to R2C6B.M1 n703 (to RCLK_c) -------- 0.318 (49.4% logic, 50.6% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_81: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R2C6B.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_81: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R2C6B.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.339ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS_FSM__i12 (from RCLK_c +) Destination: FF Data in IS_FSM__i13 (to RCLK_c +) Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. Constraint Details: 0.318ns physical path delay SLICE_84 to SLICE_84 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.339ns Physical Path Details: Data path SLICE_84 to SLICE_84: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C5B.CLK to R2C5B.Q0 SLICE_84 (from RCLK_c) ROUTE 1 0.161 R2C5B.Q0 to R2C5B.M1 n695 (to RCLK_c) -------- 0.318 (49.4% logic, 50.6% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_84: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R2C5B.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_84: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R2C5B.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.339ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS_FSM__i8 (from RCLK_c +) Destination: FF Data in IS_FSM__i9 (to RCLK_c +) Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. Constraint Details: 0.318ns physical path delay SLICE_95 to SLICE_95 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.339ns Physical Path Details: Data path SLICE_95 to SLICE_95: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R8C9C.CLK to R8C9C.Q0 SLICE_95 (from RCLK_c) ROUTE 1 0.161 R8C9C.Q0 to R8C9C.M1 n699 (to RCLK_c) -------- 0.318 (49.4% logic, 50.6% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_95: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R8C9C.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_95: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R8C9C.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.339ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS_FSM__i10 (from RCLK_c +) Destination: FF Data in IS_FSM__i11 (to RCLK_c +) Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. Constraint Details: 0.318ns physical path delay SLICE_96 to SLICE_96 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.339ns Physical Path Details: Data path SLICE_96 to SLICE_96: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R4C7A.CLK to R4C7A.Q0 SLICE_96 (from RCLK_c) ROUTE 1 0.161 R4C7A.Q0 to R4C7A.M1 n697 (to RCLK_c) -------- 0.318 (49.4% logic, 50.6% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_96: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R4C7A.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_96: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R4C7A.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.339ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS_FSM__i14 (from RCLK_c +) Destination: FF Data in IS_FSM__i15 (to RCLK_c +) Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. Constraint Details: 0.318ns physical path delay SLICE_99 to SLICE_99 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.339ns Physical Path Details: Data path SLICE_99 to SLICE_99: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C7B.CLK to R2C7B.Q0 SLICE_99 (from RCLK_c) ROUTE 1 0.161 R2C7B.Q0 to R2C7B.M1 n693 (to RCLK_c) -------- 0.318 (49.4% logic, 50.6% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_99: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R2C7B.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_99: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R2C7B.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.345ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RASr2_348 (from RCLK_c +) Destination: FF Data in RASr3_349 (to RCLK_c +) Delay: 0.324ns (48.5% logic, 51.5% route), 1 logic levels. Constraint Details: 0.324ns physical path delay SLICE_61 to SLICE_29 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.345ns Physical Path Details: Data path SLICE_61 to SLICE_29: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R4C9B.CLK to R4C9B.Q1 SLICE_61 (from RCLK_c) ROUTE 16 0.167 R4C9B.Q1 to R4C9D.M1 RASr2 (to RCLK_c) -------- 0.324 (48.5% logic, 51.5% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_61: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R4C9B.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_29: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R4C9D.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.345ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q IS_FSM__i0 (from RCLK_c +) Destination: FF Data in IS_FSM__i1 (to RCLK_c +) Delay: 0.324ns (48.5% logic, 51.5% route), 1 logic levels. Constraint Details: 0.324ns physical path delay SLICE_87 to SLICE_87 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.345ns Physical Path Details: Data path SLICE_87 to SLICE_87: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R6C9A.CLK to R6C9A.Q0 SLICE_87 (from RCLK_c) ROUTE 6 0.167 R6C9A.Q0 to R6C9A.M1 nRCS_N_135 (to RCLK_c) -------- 0.324 (48.5% logic, 51.5% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_87: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R6C9A.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_87: Name Fanout Delay (ns) Site Resource ROUTE 39 0.435 86.PADDI to R6C9A.CLK RCLK_c -------- 0.435 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 1.949ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RA10_368 (from RCLK_c +) Destination: Port Pad RA[10] Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_55 and 1.462ns delay SLICE_55 to RA[10] (totaling 1.949ns) meets 0.000ns hold offset RCLK to RA[10] by 1.949ns Physical Path Details: Clock path RCLK to SLICE_55: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C5A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_55 to RA[10]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C5A.CLK to R2C5A.Q0 SLICE_55 (from RCLK_c) ROUTE 1 0.197 R2C5A.Q0 to 87.PADDO n974 DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10] -------- 1.462 (86.5% logic, 13.5% route), 2 logic levels. Report: 1.949ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.844ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RA[9] Data Path Delay: 2.357ns (57.6% logic, 42.4% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.357ns delay SLICE_64 to RA[9] (totaling 2.844ns) meets 0.000ns hold offset RCLK to RA[9] by 2.844ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RA[9]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.473 R2C6A.Q0 to R6C9A.D1 nRowColSel CTOF_DEL --- 0.092 R6C9A.D1 to R6C9A.F1 SLICE_87 ROUTE 1 0.527 R6C9A.F1 to 85.PADDO RA_c_9 DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9] -------- 2.357 (57.6% logic, 42.4% route), 3 logic levels. Report: 2.844ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.575ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RA[8] Data Path Delay: 2.088ns (65.0% logic, 35.0% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.088ns delay SLICE_64 to RA[8] (totaling 2.575ns) meets 0.000ns hold offset RCLK to RA[8] by 2.575ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RA[8]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.375 R2C6A.Q0 to R2C2A.C0 nRowColSel CTOF_DEL --- 0.092 R2C2A.C0 to R2C2A.F0 SLICE_98 ROUTE 1 0.356 R2C2A.F0 to 96.PADDO RA_c_8 DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8] -------- 2.088 (65.0% logic, 35.0% route), 3 logic levels. Report: 2.575ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.673ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RA[7] Data Path Delay: 2.186ns (62.1% logic, 37.9% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.186ns delay SLICE_64 to RA[7] (totaling 2.673ns) meets 0.000ns hold offset RCLK to RA[7] by 2.673ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RA[7]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.226 R2C6A.Q0 to R2C6A.C1 nRowColSel CTOF_DEL --- 0.092 R2C6A.C1 to R2C6A.F1 SLICE_64 ROUTE 1 0.603 R2C6A.F1 to 100.PADDO RA_c_7 DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7] -------- 2.186 (62.1% logic, 37.9% route), 3 logic levels. Report: 2.673ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.687ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RA[6] Data Path Delay: 2.200ns (61.7% logic, 38.3% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.200ns delay SLICE_64 to RA[6] (totaling 2.687ns) meets 0.000ns hold offset RCLK to RA[6] by 2.687ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RA[6]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.375 R2C6A.Q0 to R2C2A.C1 nRowColSel CTOF_DEL --- 0.092 R2C2A.C1 to R2C2A.F1 SLICE_98 ROUTE 1 0.468 R2C2A.F1 to 91.PADDO RA_c_6 DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6] -------- 2.200 (61.7% logic, 38.3% route), 3 logic levels. Report: 2.687ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.915ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RA[5] Data Path Delay: 2.428ns (55.9% logic, 44.1% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.428ns delay SLICE_64 to RA[5] (totaling 2.915ns) meets 0.000ns hold offset RCLK to RA[5] by 2.915ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RA[5]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.447 R2C6A.Q0 to R8C9C.D1 nRowColSel CTOF_DEL --- 0.092 R8C9C.D1 to R8C9C.F1 SLICE_95 ROUTE 1 0.624 R8C9C.F1 to 95.PADDO RA_c_5 DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5] -------- 2.428 (55.9% logic, 44.1% route), 3 logic levels. Report: 2.915ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.574ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RA[4] Data Path Delay: 2.087ns (65.0% logic, 35.0% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.087ns delay SLICE_64 to RA[4] (totaling 2.574ns) meets 0.000ns hold offset RCLK to RA[4] by 2.574ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RA[4]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.375 R2C6A.Q0 to R2C2C.C1 nRowColSel CTOF_DEL --- 0.092 R2C2C.C1 to R2C2C.F1 SLICE_93 ROUTE 1 0.355 R2C2C.F1 to 99.PADDO RA_c_4 DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4] -------- 2.087 (65.0% logic, 35.0% route), 3 logic levels. Report: 2.574ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.622ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RA[3] Data Path Delay: 2.135ns (63.6% logic, 36.4% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.135ns delay SLICE_64 to RA[3] (totaling 2.622ns) meets 0.000ns hold offset RCLK to RA[3] by 2.622ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RA[3]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.310 R2C6A.Q0 to R2C3A.D1 nRowColSel CTOF_DEL --- 0.092 R2C3A.D1 to R2C3A.F1 SLICE_92 ROUTE 1 0.468 R2C3A.F1 to 97.PADDO RA_c_3 DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3] -------- 2.135 (63.6% logic, 36.4% route), 3 logic levels. Report: 2.622ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.698ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RA[2] Data Path Delay: 2.211ns (61.4% logic, 38.6% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.211ns delay SLICE_64 to RA[2] (totaling 2.698ns) meets 0.000ns hold offset RCLK to RA[2] by 2.698ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RA[2]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.375 R2C6A.Q0 to R2C2B.C0 nRowColSel CTOF_DEL --- 0.092 R2C2B.C0 to R2C2B.F0 SLICE_90 ROUTE 1 0.479 R2C2B.F0 to 94.PADDO RA_c_2 DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2] -------- 2.211 (61.4% logic, 38.6% route), 3 logic levels. Report: 2.698ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.622ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RA[1] Data Path Delay: 2.135ns (63.6% logic, 36.4% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.135ns delay SLICE_64 to RA[1] (totaling 2.622ns) meets 0.000ns hold offset RCLK to RA[1] by 2.622ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RA[1]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.310 R2C6A.Q0 to R2C3A.D0 nRowColSel CTOF_DEL --- 0.092 R2C3A.D0 to R2C3A.F0 SLICE_92 ROUTE 1 0.468 R2C3A.F0 to 89.PADDO RA_c_1 DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1] -------- 2.135 (63.6% logic, 36.4% route), 3 logic levels. Report: 2.622ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.573ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RA[0] Data Path Delay: 2.086ns (65.1% logic, 34.9% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.086ns delay SLICE_64 to RA[0] (totaling 2.573ns) meets 0.000ns hold offset RCLK to RA[0] by 2.573ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RA[0]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.375 R2C6A.Q0 to R2C2C.C0 nRowColSel CTOF_DEL --- 0.092 R2C2C.C0 to R2C2C.F0 SLICE_93 ROUTE 1 0.354 R2C2C.F0 to 98.PADDO RA_c_0 DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0] -------- 2.086 (65.1% logic, 34.9% route), 3 logic levels. Report: 2.573ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 1.949ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRCS_364 (from RCLK_c +) Destination: Port Pad nRCS Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_60 and 1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets 0.000ns hold offset RCLK to nRCS by 1.949ns Physical Path Details: Clock path RCLK to SLICE_60: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C9C.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_60 to nRCS: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C9C.CLK to R2C9C.Q0 SLICE_60 (from RCLK_c) ROUTE 1 0.197 R2C9C.Q0 to 77.PADDO nRCS_c DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS -------- 1.462 (86.5% logic, 13.5% route), 2 logic levels. Report: 1.949ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 1.949ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RCKE_363 (from RCLK_c +) Destination: Port Pad RCKE Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_34 and 1.462ns delay SLICE_34 to RCKE (totaling 1.949ns) meets 0.000ns hold offset RCLK to RCKE by 1.949ns Physical Path Details: Clock path RCLK to SLICE_34: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C7C.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_34 to RCKE: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C7C.CLK to R2C7C.Q0 SLICE_34 (from RCLK_c) ROUTE 4 0.197 R2C7C.Q0 to 82.PADDO RCKE_c DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE -------- 1.462 (86.5% logic, 13.5% route), 2 logic levels. Report: 1.949ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.232ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRWE_367 (from RCLK_c +) Destination: Port Pad nRWE Data Path Delay: 1.745ns (72.5% logic, 27.5% route), 2 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_63 and 1.745ns delay SLICE_63 to nRWE (totaling 2.232ns) meets 0.000ns hold offset RCLK to nRWE by 2.232ns Physical Path Details: Clock path RCLK to SLICE_63: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C7A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_63 to nRWE: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C7A.CLK to R2C7A.Q0 SLICE_63 (from RCLK_c) ROUTE 1 0.480 R2C7A.Q0 to 72.PADDO nRWE_c DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE -------- 1.745 (72.5% logic, 27.5% route), 2 logic levels. Report: 2.232ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.236ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRRAS_365 (from RCLK_c +) Destination: Port Pad nRRAS Data Path Delay: 1.749ns (72.3% logic, 27.7% route), 2 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_61 and 1.749ns delay SLICE_61 to nRRAS (totaling 2.236ns) meets 0.000ns hold offset RCLK to nRRAS by 2.236ns Physical Path Details: Clock path RCLK to SLICE_61: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R4C9B.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_61 to nRRAS: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R4C9B.CLK to R4C9B.Q0 SLICE_61 (from RCLK_c) ROUTE 2 0.484 R4C9B.Q0 to 73.PADDO nRRAS_c DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS -------- 1.749 (72.3% logic, 27.7% route), 2 logic levels. Report: 2.236ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 1.949ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRCAS_366 (from RCLK_c +) Destination: Port Pad nRCAS Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_58 and 1.462ns delay SLICE_58 to nRCAS (totaling 1.949ns) meets 0.000ns hold offset RCLK to nRCAS by 1.949ns Physical Path Details: Clock path RCLK to SLICE_58: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C9B.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_58 to nRCAS: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C9B.CLK to R2C9B.Q0 SLICE_58 (from RCLK_c) ROUTE 1 0.197 R2C9B.Q0 to 78.PADDO nRCAS_c DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS -------- 1.462 (86.5% logic, 13.5% route), 2 logic levels. Report: 1.949ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.711ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RDQMH Data Path Delay: 2.224ns (61.0% logic, 39.0% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.224ns delay SLICE_64 to RDQMH (totaling 2.711ns) meets 0.000ns hold offset RCLK to RDQMH by 2.711ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RDQMH: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.473 R2C6A.Q0 to R6C9A.D0 nRowColSel CTOF_DEL --- 0.092 R6C9A.D0 to R6C9A.F0 SLICE_87 ROUTE 1 0.394 R6C9A.F0 to 76.PADDO RDQMH_c DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH -------- 2.224 (61.0% logic, 39.0% route), 3 logic levels. Report: 2.711ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.488ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q nRowColSel_370 (from RCLK_c +) Destination: Port Pad RDQML Data Path Delay: 2.001ns (67.8% logic, 32.2% route), 3 logic levels. Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. Constraint Details: 0.487ns delay RCLK to SLICE_64 and 2.001ns delay SLICE_64 to RDQML (totaling 2.488ns) meets 0.000ns hold offset RCLK to RDQML by 2.488ns Physical Path Details: Clock path RCLK to SLICE_64: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK ROUTE 39 0.223 86.PADDI to R2C6A.CLK RCLK_c -------- 0.487 (54.2% logic, 45.8% route), 1 logic levels. Data path SLICE_64 to RDQML: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.157 R2C6A.CLK to R2C6A.Q0 SLICE_64 (from RCLK_c) ROUTE 13 0.447 R2C6A.Q0 to R8C9C.D0 nRowColSel CTOF_DEL --- 0.092 R8C9C.D0 to R8C9C.F0 SLICE_95 ROUTE 1 0.197 R8C9C.F0 to 61.PADDO RDQML_c DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML -------- 2.001 (67.8% logic, 32.2% route), 3 logic levels. Report: 2.488ns is the maximum offset for this preference. ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2 | | | PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0 | | | PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0 | | | PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1 | | | CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | ns CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2 | | | CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.844 ns| 3 | | | CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.575 ns| 3 | | | CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.673 ns| 3 | | | CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.687 ns| 3 | | | CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.915 ns| 3 | | | CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.574 ns| 3 | | | CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.622 ns| 3 | | | CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.698 ns| 3 | | | CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.622 ns| 3 | | | CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.573 ns| 3 | | | CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2 | | | CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2 | | | CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.232 ns| 2 | | | CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.236 ns| 2 | | | CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2 | | | CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.711 ns| 3 | | | CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | CLKPORT "RCLK" ; | 0.000 ns| 2.488 ns| 3 | | | CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | CLKPORT "RCLK" ; | -| -| 0 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 4 clocks: Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 No transfer within this clock domain is found Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 No transfer within this clock domain is found Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; Data transfers from: Clock Domain: nCRAS_c Source: nCRAS.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: PHI2_c Source: PHI2.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 520 paths, 6 nets, and 440 connections (71.54% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0)