{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484987367 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:27 2020 " "Processing started: Thu Jul 23 02:16:27 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595484989226 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595484989445 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989617 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989633 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" {  } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595484989805 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" {  } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484989883 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" {  } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484990008 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" {  } {  } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595484991726 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595484991726 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595484992133 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:32 2020 " "Processing ended: Thu Jul 23 02:16:32 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484995336 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:33 2020 " "Processing started: Thu Jul 23 02:16:33 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1595484995351 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1595484995367 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1595484995523 ""}
{ "Info" "0" "" "Project  = RAM4GS" {  } {  } 0 0 "Project  = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""}
{ "Info" "0" "" "Revision = RAM4GS" {  } {  } 0 0 "Revision = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595484996148 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595484996164 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595484996648 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595484996679 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595484996992 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595484997164 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595484997179 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595484997210 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595484997210 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        ARCLK " "   1.000        ARCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        DRCLK " "   1.000        DRCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCCAS " "   1.000        nCCAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCRAS " "   1.000        nCRAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         PHI2 " "   1.000         PHI2" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         RCLK " "   1.000         RCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595484997210 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997210 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997226 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997226 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""}  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""}  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" {  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""}  } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595484997273 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595484997320 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595484997320 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997382 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997398 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595484997414 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595484997414 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484997445 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595484997742 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484998117 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595484998132 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595484999460 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484999460 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595484999507 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595484999976 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595484999976 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000632 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.50 " "Total time spent on timing analysis during the Fitter is 0.50 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485000663 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000679 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485000742 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485001117 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:41 2020 " "Processing ended: Thu Jul 23 02:16:41 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485001429 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1595485004085 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:43 2020 " "Processing started: Thu Jul 23 02:16:43 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485005116 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485005148 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:45 2020 " "Processing ended: Thu Jul 23 02:16:45 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485005632 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1595485006413 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1595485008366 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:47 2020 " "Processing started: Thu Jul 23 02:16:47 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485008413 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485008601 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485009444 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485009898 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485010507 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485010726 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485010773 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485010851 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 ARCLK  " "  -99.000       -99.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 DRCLK  " "  -99.000       -99.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -9.292       -92.804 PHI2  " "   -9.292       -92.804 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -8.365      -253.063 RCLK  " "   -8.365      -253.063 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.490        -0.577 nCRAS  " "   -0.490        -0.577 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.306       -16.306 DRCLK  " "  -16.306       -16.306 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.272       -16.272 ARCLK  " "  -16.272       -16.272 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.874        -0.874 RCLK  " "   -0.874        -0.874 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.396        -0.396 PHI2  " "   -0.396        -0.396 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.125        -0.125 nCRAS  " "   -0.125        -0.125 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010913 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010929 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 ARCLK  " "  -29.500       -59.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 DRCLK  " "  -29.500       -59.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 PHI2  " "   -2.289        -2.289 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 RCLK  " "   -2.289        -2.289 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCCAS  " "   -2.289        -2.289 nCCAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCRAS  " "   -2.289        -2.289 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485011241 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1  Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:51 2020 " "Processing ended: Thu Jul 23 02:16:51 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus II Full Compilation was successful. 0 errors, 14 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485012647 ""}
