Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Tue Aug 17 05:43:37 2021 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: RAM2GS Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] 120 items scored, 116 timing errors detected. -------------------------------------------------------------------------------- Error: The following path violates requirements by 10.528ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AX CK Bank_i1 (from PHI2_c +) Destination: FD1P3AX SP CmdEnable_541 (to PHI2_c -) Delay: 12.743ns (30.6% logic, 69.4% route), 8 logic levels. Constraint Details: 12.743ns data_path Bank_i1 to CmdEnable_541 violates 2.500ns delay constraint less 0.285ns LCE_S requirement (totaling 2.215ns) by 10.528ns Path Details: Bank_i1 to CmdEnable_541 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q Bank_i1 (from PHI2_c) Route 2 e 1.198 Bank[1] LUT4 --- 0.493 B to Z i1819_2_lut Route 1 e 0.941 n2427 LUT4 --- 0.493 C to Z i1857_4_lut Route 1 e 0.941 n2465 LUT4 --- 0.493 A to Z i13_4_lut_adj_4 Route 5 e 1.405 n1712 LUT4 --- 0.493 A to Z i1_2_lut_rep_12 Route 2 e 1.141 n2551 LUT4 --- 0.493 D to Z i1827_4_lut Route 1 e 0.941 n2435 LUT4 --- 0.493 B to Z i3_4_lut_adj_1 Route 4 e 1.340 C1Submitted_N_200 LUT4 --- 0.493 C to Z i34_4_lut Route 1 e 0.941 PHI2_N_119_enable_1 -------- 12.743 (30.6% logic, 69.4% route), 8 logic levels. Error: The following path violates requirements by 10.471ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AX CK Bank_i3 (from PHI2_c +) Destination: FD1P3AX SP CmdEnable_541 (to PHI2_c -) Delay: 12.686ns (30.7% logic, 69.3% route), 8 logic levels. Constraint Details: 12.686ns data_path Bank_i3 to CmdEnable_541 violates 2.500ns delay constraint less 0.285ns LCE_S requirement (totaling 2.215ns) by 10.471ns Path Details: Bank_i3 to CmdEnable_541 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q Bank_i3 (from PHI2_c) Route 1 e 0.941 Bank[3] LUT4 --- 0.493 B to Z i1799_2_lut Route 2 e 1.141 n2407 LUT4 --- 0.493 A to Z i1857_4_lut Route 1 e 0.941 n2465 LUT4 --- 0.493 A to Z i13_4_lut_adj_4 Route 5 e 1.405 n1712 LUT4 --- 0.493 A to Z i1_2_lut_rep_12 Route 2 e 1.141 n2551 LUT4 --- 0.493 D to Z i1827_4_lut Route 1 e 0.941 n2435 LUT4 --- 0.493 B to Z i3_4_lut_adj_1 Route 4 e 1.340 C1Submitted_N_200 LUT4 --- 0.493 C to Z i34_4_lut Route 1 e 0.941 PHI2_N_119_enable_1 -------- 12.686 (30.7% logic, 69.3% route), 8 logic levels. Error: The following path violates requirements by 10.471ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AX CK Bank_i6 (from PHI2_c +) Destination: FD1P3AX SP CmdEnable_541 (to PHI2_c -) Delay: 12.686ns (30.7% logic, 69.3% route), 8 logic levels. Constraint Details: 12.686ns data_path Bank_i6 to CmdEnable_541 violates 2.500ns delay constraint less 0.285ns LCE_S requirement (totaling 2.215ns) by 10.471ns Path Details: Bank_i6 to CmdEnable_541 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q Bank_i6 (from PHI2_c) Route 1 e 0.941 Bank[6] LUT4 --- 0.493 A to Z i1799_2_lut Route 2 e 1.141 n2407 LUT4 --- 0.493 A to Z i1857_4_lut Route 1 e 0.941 n2465 LUT4 --- 0.493 A to Z i13_4_lut_adj_4 Route 5 e 1.405 n1712 LUT4 --- 0.493 A to Z i1_2_lut_rep_12 Route 2 e 1.141 n2551 LUT4 --- 0.493 D to Z i1827_4_lut Route 1 e 0.941 n2435 LUT4 --- 0.493 B to Z i3_4_lut_adj_1 Route 4 e 1.340 C1Submitted_N_200 LUT4 --- 0.493 C to Z i34_4_lut Route 1 e 0.941 PHI2_N_119_enable_1 -------- 12.686 (30.7% logic, 69.3% route), 8 logic levels. Warning: 13.028 ns is the maximum delay for this constraint. ================================================================================ Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] 466 items scored, 158 timing errors detected. -------------------------------------------------------------------------------- Error: The following path violates requirements by 3.233ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AX CK FS_725__i9 (from RCLK_c +) Destination: FD1P3IX SP n8MEGEN_557 (to RCLK_c +) Delay: 7.948ns (33.3% logic, 66.7% route), 6 logic levels. Constraint Details: 7.948ns data_path FS_725__i9 to n8MEGEN_557 violates 5.000ns delay constraint less 0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns Path Details: FS_725__i9 to n8MEGEN_557 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q FS_725__i9 (from RCLK_c) Route 3 e 1.315 FS[9] LUT4 --- 0.493 A to Z i1847_4_lut Route 1 e 0.941 n2455 LUT4 --- 0.493 B to Z i1855_4_lut Route 1 e 0.941 n2463 LUT4 --- 0.493 B to Z i14_4_lut Route 1 e 0.941 n2384 LUT4 --- 0.493 D to Z i3_4_lut_adj_13 Route 1 e 0.020 n2385 MUXL5 --- 0.233 BLUT to Z i26 Route 2 e 1.141 RCLK_c_enable_10 -------- 7.948 (33.3% logic, 66.7% route), 6 logic levels. Error: The following path violates requirements by 3.233ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AX CK FS_725__i9 (from RCLK_c +) Destination: FD1P3IX SP LEDEN_556 (to RCLK_c +) Delay: 7.948ns (33.3% logic, 66.7% route), 6 logic levels. Constraint Details: 7.948ns data_path FS_725__i9 to LEDEN_556 violates 5.000ns delay constraint less 0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns Path Details: FS_725__i9 to LEDEN_556 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q FS_725__i9 (from RCLK_c) Route 3 e 1.315 FS[9] LUT4 --- 0.493 A to Z i1847_4_lut Route 1 e 0.941 n2455 LUT4 --- 0.493 B to Z i1855_4_lut Route 1 e 0.941 n2463 LUT4 --- 0.493 B to Z i14_4_lut Route 1 e 0.941 n2384 LUT4 --- 0.493 D to Z i3_4_lut_adj_13 Route 1 e 0.020 n2385 MUXL5 --- 0.233 BLUT to Z i26 Route 2 e 1.141 RCLK_c_enable_10 -------- 7.948 (33.3% logic, 66.7% route), 6 logic levels. Error: The following path violates requirements by 3.233ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AX CK FS_725__i8 (from RCLK_c +) Destination: FD1P3IX SP n8MEGEN_557 (to RCLK_c +) Delay: 7.948ns (33.3% logic, 66.7% route), 6 logic levels. Constraint Details: 7.948ns data_path FS_725__i8 to n8MEGEN_557 violates 5.000ns delay constraint less 0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns Path Details: FS_725__i8 to n8MEGEN_557 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q FS_725__i8 (from RCLK_c) Route 3 e 1.315 FS[8] LUT4 --- 0.493 B to Z i1821_2_lut Route 1 e 0.941 n2429 LUT4 --- 0.493 C to Z i1855_4_lut Route 1 e 0.941 n2463 LUT4 --- 0.493 B to Z i14_4_lut Route 1 e 0.941 n2384 LUT4 --- 0.493 D to Z i3_4_lut_adj_13 Route 1 e 0.020 n2385 MUXL5 --- 0.233 BLUT to Z i26 Route 2 e 1.141 RCLK_c_enable_10 -------- 7.948 (33.3% logic, 66.7% route), 6 logic levels. Warning: 8.233 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk3 [get_nets nCCAS_c] | -| -| 0 | | | create_clock -period 5.000000 -name | | | clk2 [get_nets nCRAS_c] | -| -| 0 | | | create_clock -period 5.000000 -name | | | clk1 [get_nets PHI2_c] | 5.000 ns| 26.056 ns| 8 * | | | create_clock -period 5.000000 -name | | | clk0 [get_nets RCLK_c] | 5.000 ns| 8.233 ns| 6 * | | | -------------------------------------------------------------------------------- 2 constraints not met. -------------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total -------------------------------------------------------------------------------- n1712 | 5| 104| 37.96% | | | n2465 | 1| 52| 18.98% | | | n2251 | 1| 41| 14.96% | | | n2551 | 2| 40| 14.60% | | | n2250 | 1| 39| 14.23% | | | n2252 | 1| 39| 14.23% | | | XOR8MEG_N_117 | 3| 34| 12.41% | | | n2249 | 1| 33| 12.04% | | | n2253 | 1| 33| 12.04% | | | C1Submitted_N_200 | 4| 32| 11.68% | | | n2379 | 2| 32| 11.68% | | | n2435 | 1| 32| 11.68% | | | RCLK_c_enable_10 | 2| 30| 10.95% | | | n2384 | 1| 30| 10.95% | | | n2385 | 1| 30| 10.95% | | | n2407 | 2| 28| 10.22% | | | n2453 | 2| 28| 10.22% | | | -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 274 Score: 1700966 Constraints cover 587 paths, 177 nets, and 436 connections (66.4% coverage) Peak memory: 55074816 bytes, TRCE: 434176 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs