Project Settings
Project Name proj_1 Device Name impl1: Lattice MachXO2 : LCMXO2_640HC
Implementation Name impl1 Top Module RAM2GS
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 8 0 0 - 00m:00s - 8/16/2023
8:59:29 PM
(premap)Complete 23 1 0 0m:01s 0m:01s 175MB 8/16/2023
8:59:32 PM
(fpga_mapper)Complete 22 7 0 0m:03s 0m:03s 193MB 8/16/2023
8:59:35 PM

Area Summary
Register bits 109 I/O cells 63
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 206

Timing Summary
Clock NameReq FreqEst FreqSlack
PHI22.9 MHz1.0 MHz-1.832
RCLK62.5 MHz22.1 MHz-0.784
nCCAS2.9 MHzNANA
nCRAS2.9 MHz1.0 MHz-1.725
System100.0 MHzNA15.472

Optimizations Summary
Combined Clock Conversion 4 / 0