Place & Route TRACE Report
Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO640C
Package: TQFP100
Performance: 3
Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.17.
Performance Hardware Data Status: Version 1.124.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Mon Aug 16 21:33:37 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf
Design file: ram2gs_lcmxo640c_impl1.ncd
Preference file: ram2gs_lcmxo640c_impl1.prf
Device,speed: LCMXO640C,3
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
PERIOD NET "PHI2_c" 350.000000 ns (0 errors) 113 items scored, 0 timing errors detected.
PERIOD NET "nCCAS_c" 350.000000 ns (0 errors) 0 items scored, 0 timing errors detected.
PERIOD NET "nCRAS_c" 350.000000 ns (0 errors) 0 items scored, 0 timing errors detected.
PERIOD NET "RCLK_c" 16.000000 ns (0 errors) 395 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
113 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 161.362ns (weighted slack = 322.724ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i7 (from PHI2_c +)
Destination: FF Data in CmdSubmitted_384 (to PHI2_c -)
Delay: 13.373ns (20.8% logic, 79.2% route), 7 logic levels.
Constraint Details:
13.373ns physical path delay SLICE_95 to SLICE_19 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 161.362ns
Physical Path Details:
Data path SLICE_95 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R3C2B.CLK to R3C2B.Q1 SLICE_95 (from PHI2_c)
ROUTE 1 2.044 R3C2B.Q1 to R4C9C.A1 Bank_7
CTOF_DEL --- 0.371 R4C9C.A1 to R4C9C.F1 SLICE_67
ROUTE 1 1.905 R4C9C.F1 to R3C2C.C1 n2154
CTOF_DEL --- 0.371 R3C2C.C1 to R3C2C.F1 SLICE_82
ROUTE 1 1.026 R3C2C.F1 to R4C2A.A1 n26
CTOF_DEL --- 0.371 R4C2A.A1 to R4C2A.F1 SLICE_76
ROUTE 4 2.142 R4C2A.F1 to R5C6A.B0 n1285
CTOF_DEL --- 0.371 R5C6A.B0 to R5C6A.F0 SLICE_89
ROUTE 3 0.899 R5C6A.F0 to R5C5A.C1 n2290
CTOF_DEL --- 0.371 R5C5A.C1 to R5C5A.F1 SLICE_18
ROUTE 3 0.899 R5C5A.F1 to R5C7C.C0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R5C7C.C0 to R5C7C.F0 SLICE_90
ROUTE 2 1.672 R5C7C.F0 to R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
13.373 (20.8% logic, 79.2% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R3C2B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R9C8B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i7 (from PHI2_c +)
Destination: FF Data in CmdUFMCS_385 (to PHI2_c -)
FF CmdUFMCLK_386
Delay: 13.241ns (21.0% logic, 79.0% route), 7 logic levels.
Constraint Details:
13.241ns physical path delay SLICE_95 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
Physical Path Details:
Data path SLICE_95 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R3C2B.CLK to R3C2B.Q1 SLICE_95 (from PHI2_c)
ROUTE 1 2.044 R3C2B.Q1 to R4C9C.A1 Bank_7
CTOF_DEL --- 0.371 R4C9C.A1 to R4C9C.F1 SLICE_67
ROUTE 1 1.905 R4C9C.F1 to R3C2C.C1 n2154
CTOF_DEL --- 0.371 R3C2C.C1 to R3C2C.F1 SLICE_82
ROUTE 1 1.026 R3C2C.F1 to R4C2A.A1 n26
CTOF_DEL --- 0.371 R4C2A.A1 to R4C2A.F1 SLICE_76
ROUTE 4 2.142 R4C2A.F1 to R5C6A.B0 n1285
CTOF_DEL --- 0.371 R5C6A.B0 to R5C6A.F0 SLICE_89
ROUTE 3 0.899 R5C6A.F0 to R5C5A.C1 n2290
CTOF_DEL --- 0.371 R5C5A.C1 to R5C5A.F1 SLICE_18
ROUTE 3 0.899 R5C5A.F1 to R5C7A.C0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R5C7A.C0 to R5C7A.F0 SLICE_72
ROUTE 2 1.540 R5C7A.F0 to R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
13.241 (21.0% logic, 79.0% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R3C2B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R7C8B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i7 (from PHI2_c +)
Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -)
Delay: 13.241ns (21.0% logic, 79.0% route), 7 logic levels.
Constraint Details:
13.241ns physical path delay SLICE_95 to SLICE_88 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
Physical Path Details:
Data path SLICE_95 to SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R3C2B.CLK to R3C2B.Q1 SLICE_95 (from PHI2_c)
ROUTE 1 2.044 R3C2B.Q1 to R4C9C.A1 Bank_7
CTOF_DEL --- 0.371 R4C9C.A1 to R4C9C.F1 SLICE_67
ROUTE 1 1.905 R4C9C.F1 to R3C2C.C1 n2154
CTOF_DEL --- 0.371 R3C2C.C1 to R3C2C.F1 SLICE_82
ROUTE 1 1.026 R3C2C.F1 to R4C2A.A1 n26
CTOF_DEL --- 0.371 R4C2A.A1 to R4C2A.F1 SLICE_76
ROUTE 4 2.142 R4C2A.F1 to R5C6A.B0 n1285
CTOF_DEL --- 0.371 R5C6A.B0 to R5C6A.F0 SLICE_89
ROUTE 3 0.899 R5C6A.F0 to R5C5A.C1 n2290
CTOF_DEL --- 0.371 R5C5A.C1 to R5C5A.F1 SLICE_18
ROUTE 3 0.899 R5C5A.F1 to R5C7A.C0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R5C7A.C0 to R5C7A.F0 SLICE_72
ROUTE 2 1.540 R5C7A.F0 to R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
13.241 (21.0% logic, 79.0% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R3C2B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R4C9A.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 161.945ns (weighted slack = 323.890ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i7 (from PHI2_c +)
Destination: FF Data in Cmdn8MEGEN_383 (to PHI2_c -)
Delay: 12.790ns (21.8% logic, 78.2% route), 7 logic levels.
Constraint Details:
12.790ns physical path delay SLICE_95 to SLICE_23 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 161.945ns
Physical Path Details:
Data path SLICE_95 to SLICE_23:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R3C2B.CLK to R3C2B.Q1 SLICE_95 (from PHI2_c)
ROUTE 1 2.044 R3C2B.Q1 to R4C9C.A1 Bank_7
CTOF_DEL --- 0.371 R4C9C.A1 to R4C9C.F1 SLICE_67
ROUTE 1 1.905 R4C9C.F1 to R3C2C.C1 n2154
CTOF_DEL --- 0.371 R3C2C.C1 to R3C2C.F1 SLICE_82
ROUTE 1 1.026 R3C2C.F1 to R4C2A.A1 n26
CTOF_DEL --- 0.371 R4C2A.A1 to R4C2A.F1 SLICE_76
ROUTE 4 2.142 R4C2A.F1 to R5C6A.B0 n1285
CTOF_DEL --- 0.371 R5C6A.B0 to R5C6A.F0 SLICE_89
ROUTE 3 0.899 R5C6A.F0 to R5C5A.C1 n2290
CTOF_DEL --- 0.371 R5C5A.C1 to R5C5A.F1 SLICE_18
ROUTE 3 0.899 R5C5A.F1 to R5C7C.C0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R5C7C.C0 to R5C7C.F0 SLICE_90
ROUTE 2 1.089 R5C7C.F0 to R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
12.790 (21.8% logic, 78.2% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R3C2B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R6C7B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 161.961ns (weighted slack = 323.922ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i7 (from PHI2_c +)
Destination: FF Data in XOR8MEG_381 (to PHI2_c -)
Delay: 12.774ns (21.8% logic, 78.2% route), 7 logic levels.
Constraint Details:
12.774ns physical path delay SLICE_95 to SLICE_96 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 161.961ns
Physical Path Details:
Data path SLICE_95 to SLICE_96:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R3C2B.CLK to R3C2B.Q1 SLICE_95 (from PHI2_c)
ROUTE 1 2.044 R3C2B.Q1 to R4C9C.A1 Bank_7
CTOF_DEL --- 0.371 R4C9C.A1 to R4C9C.F1 SLICE_67
ROUTE 1 1.905 R4C9C.F1 to R3C2C.C1 n2154
CTOF_DEL --- 0.371 R3C2C.C1 to R3C2C.F1 SLICE_82
ROUTE 1 1.026 R3C2C.F1 to R4C2A.A1 n26
CTOF_DEL --- 0.371 R4C2A.A1 to R4C2A.F1 SLICE_76
ROUTE 4 2.142 R4C2A.F1 to R5C6A.B0 n1285
CTOF_DEL --- 0.371 R5C6A.B0 to R5C6A.F0 SLICE_89
ROUTE 3 0.899 R5C6A.F0 to R5C5A.C1 n2290
CTOF_DEL --- 0.371 R5C5A.C1 to R5C5A.F1 SLICE_18
ROUTE 3 0.899 R5C5A.F1 to R5C7C.C1 XOR8MEG_N_112
CTOF_DEL --- 0.371 R5C7C.C1 to R5C7C.F1 SLICE_90
ROUTE 1 1.073 R5C7C.F1 to R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
--------
12.774 (21.8% logic, 78.2% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R3C2B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R5C8B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i7 (from PHI2_c +)
Destination: FF Data in CmdEnable_378 (to PHI2_c -)
Delay: 12.703ns (21.9% logic, 78.1% route), 7 logic levels.
Constraint Details:
12.703ns physical path delay SLICE_95 to SLICE_18 meets
175.000ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
Physical Path Details:
Data path SLICE_95 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R3C2B.CLK to R3C2B.Q1 SLICE_95 (from PHI2_c)
ROUTE 1 2.044 R3C2B.Q1 to R4C9C.A1 Bank_7
CTOF_DEL --- 0.371 R4C9C.A1 to R4C9C.F1 SLICE_67
ROUTE 1 1.905 R4C9C.F1 to R3C2C.C1 n2154
CTOF_DEL --- 0.371 R3C2C.C1 to R3C2C.F1 SLICE_82
ROUTE 1 1.026 R3C2C.F1 to R4C2A.A1 n26
CTOF_DEL --- 0.371 R4C2A.A1 to R4C2A.F1 SLICE_76
ROUTE 4 2.134 R4C2A.F1 to R6C9A.B1 n1285
CTOF_DEL --- 0.371 R6C9A.B1 to R6C9A.F1 SLICE_80
ROUTE 1 0.696 R6C9A.F1 to R6C9A.B0 n2289
CTOF_DEL --- 0.371 R6C9A.B0 to R6C9A.F0 SLICE_80
ROUTE 2 2.112 R6C9A.F0 to R5C5A.B0 ADSubmitted_N_234
CTOF_DEL --- 0.371 R5C5A.B0 to R5C5A.F0 SLICE_18
ROUTE 1 0.000 R5C5A.F0 to R5C5A.DI0 CmdEnable_N_236 (to PHI2_c)
--------
12.703 (21.9% logic, 78.1% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R3C2B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R5C5A.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i7 (from PHI2_c +)
Destination: FF Data in ADSubmitted_380 (to PHI2_c -)
Delay: 12.703ns (21.9% logic, 78.1% route), 7 logic levels.
Constraint Details:
12.703ns physical path delay SLICE_95 to SLICE_9 meets
175.000ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
Physical Path Details:
Data path SLICE_95 to SLICE_9:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R3C2B.CLK to R3C2B.Q1 SLICE_95 (from PHI2_c)
ROUTE 1 2.044 R3C2B.Q1 to R4C9C.A1 Bank_7
CTOF_DEL --- 0.371 R4C9C.A1 to R4C9C.F1 SLICE_67
ROUTE 1 1.905 R4C9C.F1 to R3C2C.C1 n2154
CTOF_DEL --- 0.371 R3C2C.C1 to R3C2C.F1 SLICE_82
ROUTE 1 1.026 R3C2C.F1 to R4C2A.A1 n26
CTOF_DEL --- 0.371 R4C2A.A1 to R4C2A.F1 SLICE_76
ROUTE 4 2.134 R4C2A.F1 to R6C9A.B1 n1285
CTOF_DEL --- 0.371 R6C9A.B1 to R6C9A.F1 SLICE_80
ROUTE 1 0.696 R6C9A.F1 to R6C9A.B0 n2289
CTOF_DEL --- 0.371 R6C9A.B0 to R6C9A.F0 SLICE_80
ROUTE 2 2.112 R6C9A.F0 to R5C5B.B0 ADSubmitted_N_234
CTOF_DEL --- 0.371 R5C5B.B0 to R5C5B.F0 SLICE_9
ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 n1361 (to PHI2_c)
--------
12.703 (21.9% logic, 78.1% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R3C2B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R5C5B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.710ns (weighted slack = 325.420ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i5 (from PHI2_c +)
Destination: FF Data in CmdSubmitted_384 (to PHI2_c -)
Delay: 12.025ns (23.2% logic, 76.8% route), 7 logic levels.
Constraint Details:
12.025ns physical path delay SLICE_97 to SLICE_19 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.710ns
Physical Path Details:
Data path SLICE_97 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_97 (from PHI2_c)
ROUTE 1 1.643 R2C2A.Q1 to R3C2C.B0 Bank_5
CTOF_DEL --- 0.371 R3C2C.B0 to R3C2C.F0 SLICE_82
ROUTE 1 0.958 R3C2C.F0 to R3C2C.A1 n2166
CTOF_DEL --- 0.371 R3C2C.A1 to R3C2C.F1 SLICE_82
ROUTE 1 1.026 R3C2C.F1 to R4C2A.A1 n26
CTOF_DEL --- 0.371 R4C2A.A1 to R4C2A.F1 SLICE_76
ROUTE 4 2.142 R4C2A.F1 to R5C6A.B0 n1285
CTOF_DEL --- 0.371 R5C6A.B0 to R5C6A.F0 SLICE_89
ROUTE 3 0.899 R5C6A.F0 to R5C5A.C1 n2290
CTOF_DEL --- 0.371 R5C5A.C1 to R5C5A.F1 SLICE_18
ROUTE 3 0.899 R5C5A.F1 to R5C7C.C0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R5C7C.C0 to R5C7C.F0 SLICE_90
ROUTE 2 1.672 R5C7C.F0 to R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
12.025 (23.2% logic, 76.8% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_97:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R2C2A.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R9C8B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i5 (from PHI2_c +)
Destination: FF Data in CmdUFMCS_385 (to PHI2_c -)
FF CmdUFMCLK_386
Delay: 11.893ns (23.4% logic, 76.6% route), 7 logic levels.
Constraint Details:
11.893ns physical path delay SLICE_97 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
Physical Path Details:
Data path SLICE_97 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_97 (from PHI2_c)
ROUTE 1 1.643 R2C2A.Q1 to R3C2C.B0 Bank_5
CTOF_DEL --- 0.371 R3C2C.B0 to R3C2C.F0 SLICE_82
ROUTE 1 0.958 R3C2C.F0 to R3C2C.A1 n2166
CTOF_DEL --- 0.371 R3C2C.A1 to R3C2C.F1 SLICE_82
ROUTE 1 1.026 R3C2C.F1 to R4C2A.A1 n26
CTOF_DEL --- 0.371 R4C2A.A1 to R4C2A.F1 SLICE_76
ROUTE 4 2.142 R4C2A.F1 to R5C6A.B0 n1285
CTOF_DEL --- 0.371 R5C6A.B0 to R5C6A.F0 SLICE_89
ROUTE 3 0.899 R5C6A.F0 to R5C5A.C1 n2290
CTOF_DEL --- 0.371 R5C5A.C1 to R5C5A.F1 SLICE_18
ROUTE 3 0.899 R5C5A.F1 to R5C7A.C0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R5C7A.C0 to R5C7A.F0 SLICE_72
ROUTE 2 1.540 R5C7A.F0 to R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
11.893 (23.4% logic, 76.6% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_97:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R2C2A.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R7C8B.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i5 (from PHI2_c +)
Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -)
Delay: 11.893ns (23.4% logic, 76.6% route), 7 logic levels.
Constraint Details:
11.893ns physical path delay SLICE_97 to SLICE_88 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
Physical Path Details:
Data path SLICE_97 to SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_97 (from PHI2_c)
ROUTE 1 1.643 R2C2A.Q1 to R3C2C.B0 Bank_5
CTOF_DEL --- 0.371 R3C2C.B0 to R3C2C.F0 SLICE_82
ROUTE 1 0.958 R3C2C.F0 to R3C2C.A1 n2166
CTOF_DEL --- 0.371 R3C2C.A1 to R3C2C.F1 SLICE_82
ROUTE 1 1.026 R3C2C.F1 to R4C2A.A1 n26
CTOF_DEL --- 0.371 R4C2A.A1 to R4C2A.F1 SLICE_76
ROUTE 4 2.142 R4C2A.F1 to R5C6A.B0 n1285
CTOF_DEL --- 0.371 R5C6A.B0 to R5C6A.F0 SLICE_89
ROUTE 3 0.899 R5C6A.F0 to R5C5A.C1 n2290
CTOF_DEL --- 0.371 R5C5A.C1 to R5C5A.F1 SLICE_18
ROUTE 3 0.899 R5C5A.F1 to R5C7A.C0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R5C7A.C0 to R5C7A.F0 SLICE_72
ROUTE 2 1.540 R5C7A.F0 to R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
11.893 (23.4% logic, 76.6% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_97:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R2C2A.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671 39.PADDI to R4C9A.CLK PHI2_c
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Report: 27.276ns is the minimum period for this preference.
================================================================================
Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 348.000ns
The internal maximum frequency of the following component is 500.000 MHz
Logical Details: Cell type Pin name Component name
Destination: FSLICE CLK SLICE_76
Delay: 2.000ns -- based on Minimum Pulse Width
Report: 2.000ns is the minimum period for this preference.
================================================================================
Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 348.000ns
The internal maximum frequency of the following component is 500.000 MHz
Logical Details: Cell type Pin name Component name
Destination: FSLICE CLK SLICE_77
Delay: 2.000ns -- based on Minimum Pulse Width
Report: 2.000ns is the minimum period for this preference.
================================================================================
Preference: PERIOD NET "RCLK_c" 16.000000 ns ;
395 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.557ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S_FSM_i4 (from RCLK_c +)
Destination: FF Data in nRRAS_370 (to RCLK_c +)
Delay: 9.262ns (20.9% logic, 79.1% route), 4 logic levels.
Constraint Details:
9.262ns physical path delay SLICE_65 to SLICE_61 meets
16.000ns delay constraint less
0.000ns skew and
0.181ns DIN_SET requirement (totaling 15.819ns) by 6.557ns
Physical Path Details:
Data path SLICE_65 to SLICE_61:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9C.CLK to R5C9C.Q0 SLICE_65 (from RCLK_c)
ROUTE 7 2.149 R5C9C.Q0 to R3C2A.B1 nRowColSel_N_32
CTOF_DEL --- 0.371 R3C2A.B1 to R3C2A.F1 SLICE_61
ROUTE 2 2.624 R3C2A.F1 to R8C9D.B0 n50
CTOOFX_DEL --- 0.631 R8C9D.B0 to R8C9D.OFX0 i1912/SLICE_70
ROUTE 1 2.556 R8C9D.OFX0 to R3C2A.A0 n2244
CTOF_DEL --- 0.371 R3C2A.A0 to R3C2A.F0 SLICE_61
ROUTE 1 0.000 R3C2A.F0 to R3C2A.DI0 n33 (to RCLK_c)
--------
9.262 (20.9% logic, 79.1% route), 4 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R5C9C.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R3C2A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.573ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S_FSM_i4 (from RCLK_c +)
Destination: FF Data in nRRAS_370 (to RCLK_c +)
Delay: 9.246ns (20.7% logic, 79.3% route), 4 logic levels.
Constraint Details:
9.246ns physical path delay SLICE_65 to SLICE_61 meets
16.000ns delay constraint less
0.000ns skew and
0.181ns DIN_SET requirement (totaling 15.819ns) by 6.573ns
Physical Path Details:
Data path SLICE_65 to SLICE_61:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9C.CLK to R5C9C.Q0 SLICE_65 (from RCLK_c)
ROUTE 7 2.149 R5C9C.Q0 to R3C2A.B1 nRowColSel_N_32
CTOF_DEL --- 0.371 R3C2A.B1 to R3C2A.F1 SLICE_61
ROUTE 2 2.624 R3C2A.F1 to R8C9D.B1 n50
CTOOFX_DEL --- 0.615 R8C9D.B1 to R8C9D.OFX0 i1912/SLICE_70
ROUTE 1 2.556 R8C9D.OFX0 to R3C2A.A0 n2244
CTOF_DEL --- 0.371 R3C2A.A0 to R3C2A.F0 SLICE_61
ROUTE 1 0.000 R3C2A.F0 to R3C2A.DI0 n33 (to RCLK_c)
--------
9.246 (20.7% logic, 79.3% route), 4 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R5C9C.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R3C2A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.866ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i15 (from RCLK_c +)
Destination: FF Data in LEDEN_392 (to RCLK_c +)
Delay: 8.890ns (27.2% logic, 72.8% route), 6 logic levels.
Constraint Details:
8.890ns physical path delay SLICE_7 to SLICE_89 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 6.866ns
Physical Path Details:
Data path SLICE_7 to SLICE_89:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R10C7D.CLK to R10C7D.Q1 SLICE_7 (from RCLK_c)
ROUTE 3 1.466 R10C7D.Q1 to R10C8D.B0 FS_15
CTOF_DEL --- 0.371 R10C8D.B0 to R10C8D.F0 SLICE_78
ROUTE 3 1.117 R10C8D.F0 to R9C8A.B1 n10
CTOF_DEL --- 0.371 R9C8A.B1 to R9C8A.F1 SLICE_73
ROUTE 4 0.727 R9C8A.F1 to R9C8A.B0 n2300
CTOF_DEL --- 0.371 R9C8A.B0 to R9C8A.F0 SLICE_73
ROUTE 1 0.626 R9C8A.F0 to R9C8D.D0 n11
CTOF_DEL --- 0.371 R9C8D.D0 to R9C8D.F0 SLICE_75
ROUTE 2 0.513 R9C8D.F0 to R9C8D.C1 n2119
CTOF_DEL --- 0.371 R9C8D.C1 to R9C8D.F1 SLICE_75
ROUTE 1 2.026 R9C8D.F1 to R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
--------
8.890 (27.2% logic, 72.8% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R10C7D.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R5C6A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.963ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S_FSM_i3 (from RCLK_c +)
Destination: FF Data in nRRAS_370 (to RCLK_c +)
Delay: 8.856ns (21.8% logic, 78.2% route), 4 logic levels.
Constraint Details:
8.856ns physical path delay SLICE_66 to SLICE_61 meets
16.000ns delay constraint less
0.000ns skew and
0.181ns DIN_SET requirement (totaling 15.819ns) by 6.963ns
Physical Path Details:
Data path SLICE_66 to SLICE_61:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9D.CLK to R5C9D.Q0 SLICE_66 (from RCLK_c)
ROUTE 6 1.743 R5C9D.Q0 to R3C2A.D1 nRowColSel_N_33
CTOF_DEL --- 0.371 R3C2A.D1 to R3C2A.F1 SLICE_61
ROUTE 2 2.624 R3C2A.F1 to R8C9D.B0 n50
CTOOFX_DEL --- 0.631 R8C9D.B0 to R8C9D.OFX0 i1912/SLICE_70
ROUTE 1 2.556 R8C9D.OFX0 to R3C2A.A0 n2244
CTOF_DEL --- 0.371 R3C2A.A0 to R3C2A.F0 SLICE_61
ROUTE 1 0.000 R3C2A.F0 to R3C2A.DI0 n33 (to RCLK_c)
--------
8.856 (21.8% logic, 78.2% route), 4 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_66:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R5C9D.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R3C2A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.979ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S_FSM_i3 (from RCLK_c +)
Destination: FF Data in nRRAS_370 (to RCLK_c +)
Delay: 8.840ns (21.7% logic, 78.3% route), 4 logic levels.
Constraint Details:
8.840ns physical path delay SLICE_66 to SLICE_61 meets
16.000ns delay constraint less
0.000ns skew and
0.181ns DIN_SET requirement (totaling 15.819ns) by 6.979ns
Physical Path Details:
Data path SLICE_66 to SLICE_61:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9D.CLK to R5C9D.Q0 SLICE_66 (from RCLK_c)
ROUTE 6 1.743 R5C9D.Q0 to R3C2A.D1 nRowColSel_N_33
CTOF_DEL --- 0.371 R3C2A.D1 to R3C2A.F1 SLICE_61
ROUTE 2 2.624 R3C2A.F1 to R8C9D.B1 n50
CTOOFX_DEL --- 0.615 R8C9D.B1 to R8C9D.OFX0 i1912/SLICE_70
ROUTE 1 2.556 R8C9D.OFX0 to R3C2A.A0 n2244
CTOF_DEL --- 0.371 R3C2A.A0 to R3C2A.F0 SLICE_61
ROUTE 1 0.000 R3C2A.F0 to R3C2A.DI0 n33 (to RCLK_c)
--------
8.840 (21.7% logic, 78.3% route), 4 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_66:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R5C9D.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R3C2A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.065ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i14 (from RCLK_c +)
Destination: FF Data in LEDEN_392 (to RCLK_c +)
Delay: 8.691ns (27.8% logic, 72.2% route), 6 logic levels.
Constraint Details:
8.691ns physical path delay SLICE_7 to SLICE_89 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.065ns
Physical Path Details:
Data path SLICE_7 to SLICE_89:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R10C7D.CLK to R10C7D.Q0 SLICE_7 (from RCLK_c)
ROUTE 3 1.267 R10C7D.Q0 to R10C8D.C0 FS_14
CTOF_DEL --- 0.371 R10C8D.C0 to R10C8D.F0 SLICE_78
ROUTE 3 1.117 R10C8D.F0 to R9C8A.B1 n10
CTOF_DEL --- 0.371 R9C8A.B1 to R9C8A.F1 SLICE_73
ROUTE 4 0.727 R9C8A.F1 to R9C8A.B0 n2300
CTOF_DEL --- 0.371 R9C8A.B0 to R9C8A.F0 SLICE_73
ROUTE 1 0.626 R9C8A.F0 to R9C8D.D0 n11
CTOF_DEL --- 0.371 R9C8D.D0 to R9C8D.F0 SLICE_75
ROUTE 2 0.513 R9C8D.F0 to R9C8D.C1 n2119
CTOF_DEL --- 0.371 R9C8D.C1 to R9C8D.F1 SLICE_75
ROUTE 1 2.026 R9C8D.F1 to R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
--------
8.691 (27.8% logic, 72.2% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R10C7D.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R5C6A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.284ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i13 (from RCLK_c +)
Destination: FF Data in LEDEN_392 (to RCLK_c +)
Delay: 8.472ns (28.5% logic, 71.5% route), 6 logic levels.
Constraint Details:
8.472ns physical path delay SLICE_8 to SLICE_89 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.284ns
Physical Path Details:
Data path SLICE_8 to SLICE_89:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R10C7C.CLK to R10C7C.Q1 SLICE_8 (from RCLK_c)
ROUTE 3 1.048 R10C7C.Q1 to R10C8D.A0 FS_13
CTOF_DEL --- 0.371 R10C8D.A0 to R10C8D.F0 SLICE_78
ROUTE 3 1.117 R10C8D.F0 to R9C8A.B1 n10
CTOF_DEL --- 0.371 R9C8A.B1 to R9C8A.F1 SLICE_73
ROUTE 4 0.727 R9C8A.F1 to R9C8A.B0 n2300
CTOF_DEL --- 0.371 R9C8A.B0 to R9C8A.F0 SLICE_73
ROUTE 1 0.626 R9C8A.F0 to R9C8D.D0 n11
CTOF_DEL --- 0.371 R9C8D.D0 to R9C8D.F0 SLICE_75
ROUTE 2 0.513 R9C8D.F0 to R9C8D.C1 n2119
CTOF_DEL --- 0.371 R9C8D.C1 to R9C8D.F1 SLICE_75
ROUTE 1 2.026 R9C8D.F1 to R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
--------
8.472 (28.5% logic, 71.5% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R10C7C.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R5C6A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.601ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i12 (from RCLK_c +)
Destination: FF Data in LEDEN_392 (to RCLK_c +)
Delay: 8.155ns (29.6% logic, 70.4% route), 6 logic levels.
Constraint Details:
8.155ns physical path delay SLICE_8 to SLICE_89 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.601ns
Physical Path Details:
Data path SLICE_8 to SLICE_89:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R10C7C.CLK to R10C7C.Q0 SLICE_8 (from RCLK_c)
ROUTE 3 0.731 R10C7C.Q0 to R10C8D.D0 FS_12
CTOF_DEL --- 0.371 R10C8D.D0 to R10C8D.F0 SLICE_78
ROUTE 3 1.117 R10C8D.F0 to R9C8A.B1 n10
CTOF_DEL --- 0.371 R9C8A.B1 to R9C8A.F1 SLICE_73
ROUTE 4 0.727 R9C8A.F1 to R9C8A.B0 n2300
CTOF_DEL --- 0.371 R9C8A.B0 to R9C8A.F0 SLICE_73
ROUTE 1 0.626 R9C8A.F0 to R9C8D.D0 n11
CTOF_DEL --- 0.371 R9C8D.D0 to R9C8D.F0 SLICE_75
ROUTE 2 0.513 R9C8D.F0 to R9C8D.C1 n2119
CTOF_DEL --- 0.371 R9C8D.C1 to R9C8D.F1 SLICE_75
ROUTE 1 2.026 R9C8D.F1 to R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
--------
8.155 (29.6% logic, 70.4% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R10C7C.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R5C6A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.732ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRRAS_370 (from RCLK_c +)
Destination: FF Data in nRRAS_370 (to RCLK_c +)
Delay: 8.087ns (23.9% logic, 76.1% route), 4 logic levels.
Constraint Details:
8.087ns physical path delay SLICE_61 to SLICE_61 meets
16.000ns delay constraint less
0.000ns skew and
0.181ns DIN_SET requirement (totaling 15.819ns) by 7.732ns
Physical Path Details:
Data path SLICE_61 to SLICE_61:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R3C2A.CLK to R3C2A.Q0 SLICE_61 (from RCLK_c)
ROUTE 2 0.974 R3C2A.Q0 to R3C2A.A1 nRRAS_c
CTOF_DEL --- 0.371 R3C2A.A1 to R3C2A.F1 SLICE_61
ROUTE 2 2.624 R3C2A.F1 to R8C9D.B0 n50
CTOOFX_DEL --- 0.631 R8C9D.B0 to R8C9D.OFX0 i1912/SLICE_70
ROUTE 1 2.556 R8C9D.OFX0 to R3C2A.A0 n2244
CTOF_DEL --- 0.371 R3C2A.A0 to R3C2A.F0 SLICE_61
ROUTE 1 0.000 R3C2A.F0 to R3C2A.DI0 n33 (to RCLK_c)
--------
8.087 (23.9% logic, 76.1% route), 4 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R3C2A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R3C2A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.748ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRRAS_370 (from RCLK_c +)
Destination: FF Data in nRRAS_370 (to RCLK_c +)
Delay: 8.071ns (23.8% logic, 76.2% route), 4 logic levels.
Constraint Details:
8.071ns physical path delay SLICE_61 to SLICE_61 meets
16.000ns delay constraint less
0.000ns skew and
0.181ns DIN_SET requirement (totaling 15.819ns) by 7.748ns
Physical Path Details:
Data path SLICE_61 to SLICE_61:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R3C2A.CLK to R3C2A.Q0 SLICE_61 (from RCLK_c)
ROUTE 2 0.974 R3C2A.Q0 to R3C2A.A1 nRRAS_c
CTOF_DEL --- 0.371 R3C2A.A1 to R3C2A.F1 SLICE_61
ROUTE 2 2.624 R3C2A.F1 to R8C9D.B1 n50
CTOOFX_DEL --- 0.615 R8C9D.B1 to R8C9D.OFX0 i1912/SLICE_70
ROUTE 1 2.556 R8C9D.OFX0 to R3C2A.A0 n2244
CTOF_DEL --- 0.371 R3C2A.A0 to R3C2A.F0 SLICE_61
ROUTE 1 0.000 R3C2A.F0 to R3C2A.DI0 n33 (to RCLK_c)
--------
8.071 (23.8% logic, 76.2% route), 4 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R3C2A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425 86.PADDI to R3C2A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Report: 9.443ns is the minimum period for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.999ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RA10_373 (from RCLK_c +)
Destination: Port Pad RA[10]
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_55 and
5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
12.500ns offset RCLK to RA[10] by 4.999ns
Physical Path Details:
Clock path RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R2C5A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_55 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C5A.CLK to R2C5A.Q0 SLICE_55 (from RCLK_c)
ROUTE 1 0.817 R2C5A.Q0 to 87.PADDO n980
DOPAD_DEL --- 3.636 87.PADDO to 87.PAD RA[10]
--------
5.013 (83.7% logic, 16.3% route), 2 logic levels.
Report: 7.501ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.088ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[9]
Data Path Delay: 7.924ns (57.6% logic, 42.4% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.924ns delay SLICE_64 to RA[9] (totaling 10.412ns) meets
12.500ns offset RCLK to RA[9] by 2.088ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.793 R5C9A.Q0 to R4C9A.D1 nRowColSel
CTOF_DEL --- 0.371 R4C9A.D1 to R4C9A.F1 SLICE_88
ROUTE 1 2.564 R4C9A.F1 to 85.PADDO RA_c_9
DOPAD_DEL --- 3.636 85.PADDO to 85.PAD RA[9]
--------
7.924 (57.6% logic, 42.4% route), 3 logic levels.
Report: 10.412ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.035ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[8]
Data Path Delay: 7.977ns (57.3% logic, 42.7% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.977ns delay SLICE_64 to RA[8] (totaling 10.465ns) meets
12.500ns offset RCLK to RA[8] by 2.035ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 1.750 R5C9A.Q0 to R3C2B.D0 nRowColSel
CTOF_DEL --- 0.371 R3C2B.D0 to R3C2B.F0 SLICE_95
ROUTE 1 1.660 R3C2B.F0 to 96.PADDO RA_c_8
DOPAD_DEL --- 3.636 96.PADDO to 96.PAD RA[8]
--------
7.977 (57.3% logic, 42.7% route), 3 logic levels.
Report: 10.465ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.583ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[7]
Data Path Delay: 7.429ns (61.5% logic, 38.5% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.429ns delay SLICE_64 to RA[7] (totaling 9.917ns) meets
12.500ns offset RCLK to RA[7] by 2.583ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 2.045 R5C9A.Q0 to R2C2A.C0 nRowColSel
CTOF_DEL --- 0.371 R2C2A.C0 to R2C2A.F0 SLICE_97
ROUTE 1 0.817 R2C2A.F0 to 100.PADDO RA_c_7
DOPAD_DEL --- 3.636 100.PADDO to 100.PAD RA[7]
--------
7.429 (61.5% logic, 38.5% route), 3 logic levels.
Report: 9.917ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[6]
Data Path Delay: 7.846ns (58.2% logic, 41.8% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.846ns delay SLICE_64 to RA[6] (totaling 10.334ns) meets
12.500ns offset RCLK to RA[6] by 2.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 1.753 R5C9A.Q0 to R2C3A.D0 nRowColSel
CTOF_DEL --- 0.371 R2C3A.D0 to R2C3A.F0 SLICE_98
ROUTE 1 1.526 R2C3A.F0 to 91.PADDO RA_c_6
DOPAD_DEL --- 3.636 91.PADDO to 91.PAD RA[6]
--------
7.846 (58.2% logic, 41.8% route), 3 logic levels.
Report: 10.334ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[5]
Data Path Delay: 7.846ns (58.2% logic, 41.8% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.846ns delay SLICE_64 to RA[5] (totaling 10.334ns) meets
12.500ns offset RCLK to RA[5] by 2.166ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 1.753 R5C9A.Q0 to R2C3A.D1 nRowColSel
CTOF_DEL --- 0.371 R2C3A.D1 to R2C3A.F1 SLICE_98
ROUTE 1 1.526 R2C3A.F1 to 95.PADDO RA_c_5
DOPAD_DEL --- 3.636 95.PADDO to 95.PAD RA[5]
--------
7.846 (58.2% logic, 41.8% route), 3 logic levels.
Report: 10.334ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.742ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[4]
Data Path Delay: 8.270ns (55.2% logic, 44.8% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
8.270ns delay SLICE_64 to RA[4] (totaling 10.758ns) meets
12.500ns offset RCLK to RA[4] by 1.742ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.702 R5C9A.Q0 to R5C9A.D1 nRowColSel
CTOF_DEL --- 0.371 R5C9A.D1 to R5C9A.F1 SLICE_64
ROUTE 1 3.001 R5C9A.F1 to 99.PADDO RA_c_4
DOPAD_DEL --- 3.636 99.PADDO to 99.PAD RA[4]
--------
8.270 (55.2% logic, 44.8% route), 3 logic levels.
Report: 10.758ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.725ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[3]
Data Path Delay: 8.287ns (55.1% logic, 44.9% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
8.287ns delay SLICE_64 to RA[3] (totaling 10.775ns) meets
12.500ns offset RCLK to RA[3] by 1.725ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 2.198 R5C9A.Q0 to R2C2C.D1 nRowColSel
CTOF_DEL --- 0.371 R2C2C.D1 to R2C2C.F1 SLICE_94
ROUTE 1 1.522 R2C2C.F1 to 97.PADDO RA_c_3
DOPAD_DEL --- 3.636 97.PADDO to 97.PAD RA[3]
--------
8.287 (55.1% logic, 44.9% route), 3 logic levels.
Report: 10.775ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.643ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[2]
Data Path Delay: 8.369ns (54.6% logic, 45.4% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
8.369ns delay SLICE_64 to RA[2] (totaling 10.857ns) meets
12.500ns offset RCLK to RA[2] by 1.643ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 1.750 R5C9A.Q0 to R3C2B.D1 nRowColSel
CTOF_DEL --- 0.371 R3C2B.D1 to R3C2B.F1 SLICE_95
ROUTE 1 2.052 R3C2B.F1 to 94.PADDO RA_c_2
DOPAD_DEL --- 3.636 94.PADDO to 94.PAD RA[2]
--------
8.369 (54.6% logic, 45.4% route), 3 logic levels.
Report: 10.857ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.417ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[1]
Data Path Delay: 8.595ns (53.1% logic, 46.9% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
8.595ns delay SLICE_64 to RA[1] (totaling 11.083ns) meets
12.500ns offset RCLK to RA[1] by 1.417ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 2.045 R5C9A.Q0 to R2C2C.C0 nRowColSel
CTOF_DEL --- 0.371 R2C2C.C0 to R2C2C.F0 SLICE_94
ROUTE 1 1.983 R2C2C.F0 to 89.PADDO RA_c_1
DOPAD_DEL --- 3.636 89.PADDO to 89.PAD RA[1]
--------
8.595 (53.1% logic, 46.9% route), 3 logic levels.
Report: 11.083ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.213ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[0]
Data Path Delay: 8.799ns (51.9% logic, 48.1% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
8.799ns delay SLICE_64 to RA[0] (totaling 11.287ns) meets
12.500ns offset RCLK to RA[0] by 1.213ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 1.245 R5C9A.Q0 to R8C9C.D1 nRowColSel
CTOF_DEL --- 0.371 R8C9C.D1 to R8C9C.F1 SLICE_92
ROUTE 1 2.987 R8C9C.F1 to 98.PADDO RA_c_0
DOPAD_DEL --- 3.636 98.PADDO to 98.PAD RA[0]
--------
8.799 (51.9% logic, 48.1% route), 3 logic levels.
Report: 11.287ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.999ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCS_369 (from RCLK_c +)
Destination: Port Pad nRCS
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_60 and
5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
12.500ns offset RCLK to nRCS by 4.999ns
Physical Path Details:
Clock path RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R2C9C.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_60 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C9C.CLK to R2C9C.Q0 SLICE_60 (from RCLK_c)
ROUTE 1 0.817 R2C9C.Q0 to 77.PADDO nRCS_c
DOPAD_DEL --- 3.636 77.PADDO to 77.PAD nRCS
--------
5.013 (83.7% logic, 16.3% route), 2 logic levels.
Report: 7.501ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.999ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RCKE_368 (from RCLK_c +)
Destination: Port Pad RCKE
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_34 and
5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
12.500ns offset RCLK to RCKE by 4.999ns
Physical Path Details:
Clock path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R2C7C.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_34 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C7C.CLK to R2C7C.Q0 SLICE_34 (from RCLK_c)
ROUTE 4 0.817 R2C7C.Q0 to 82.PADDO RCKE_c
DOPAD_DEL --- 3.636 82.PADDO to 82.PAD RCKE
--------
5.013 (83.7% logic, 16.3% route), 2 logic levels.
Report: 7.501ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.359ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRWE_372 (from RCLK_c +)
Destination: Port Pad nRWE
Data Path Delay: 6.653ns (63.1% logic, 36.9% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_63 and
6.653ns delay SLICE_63 to nRWE (totaling 9.141ns) meets
12.500ns offset RCLK to nRWE by 3.359ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R10C9C.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_63 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R10C9C.CLK to R10C9C.Q0 SLICE_63 (from RCLK_c)
ROUTE 1 2.457 R10C9C.Q0 to 72.PADDO nRWE_c
DOPAD_DEL --- 3.636 72.PADDO to 72.PAD nRWE
--------
6.653 (63.1% logic, 36.9% route), 2 logic levels.
Report: 9.141ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.325ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRRAS_370 (from RCLK_c +)
Destination: Port Pad nRRAS
Data Path Delay: 6.687ns (62.7% logic, 37.3% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_61 and
6.687ns delay SLICE_61 to nRRAS (totaling 9.175ns) meets
12.500ns offset RCLK to nRRAS by 3.325ns
Physical Path Details:
Clock path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R3C2A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_61 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R3C2A.CLK to R3C2A.Q0 SLICE_61 (from RCLK_c)
ROUTE 2 2.491 R3C2A.Q0 to 73.PADDO nRRAS_c
DOPAD_DEL --- 3.636 73.PADDO to 73.PAD nRRAS
--------
6.687 (62.7% logic, 37.3% route), 2 logic levels.
Report: 9.175ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.999ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCAS_371 (from RCLK_c +)
Destination: Port Pad nRCAS
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_58 and
5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
12.500ns offset RCLK to nRCAS by 4.999ns
Physical Path Details:
Clock path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R2C9B.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_58 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C9B.CLK to R2C9B.Q0 SLICE_58 (from RCLK_c)
ROUTE 1 0.817 R2C9B.Q0 to 78.PADDO nRCAS_c
DOPAD_DEL --- 3.636 78.PADDO to 78.PAD nRCAS
--------
5.013 (83.7% logic, 16.3% route), 2 logic levels.
Report: 7.501ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.669ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQMH
Data Path Delay: 7.343ns (62.2% logic, 37.8% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.343ns delay SLICE_64 to RDQMH (totaling 9.831ns) meets
12.500ns offset RCLK to RDQMH by 2.669ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.793 R5C9A.Q0 to R4C9A.D0 nRowColSel
CTOF_DEL --- 0.371 R4C9A.D0 to R4C9A.F0 SLICE_88
ROUTE 1 1.983 R4C9A.F0 to 76.PADDO RDQMH_c
DOPAD_DEL --- 3.636 76.PADDO to 76.PAD RDQMH
--------
7.343 (62.2% logic, 37.8% route), 3 logic levels.
Report: 9.831ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.383ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQML
Data Path Delay: 6.629ns (68.9% logic, 31.1% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
6.629ns delay SLICE_64 to RDQML (totaling 9.117ns) meets
12.500ns offset RCLK to RDQML by 3.383ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.425 86.PADDI to R5C9A.CLK RCLK_c
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
Data path SLICE_64 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 1.245 R5C9A.Q0 to R8C9C.D0 nRowColSel
CTOF_DEL --- 0.371 R8C9C.D0 to R8C9C.F0 SLICE_92
ROUTE 1 0.817 R8C9C.F0 to 61.PADDO RDQML_c
DOPAD_DEL --- 3.636 61.PADDO to 61.PAD RDQML
--------
6.629 (68.9% logic, 31.1% route), 3 logic levels.
Report: 9.117ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 27.276 ns| 7
| | |
PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
| | |
PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
| | |
PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 9.443 ns| 4
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 7.501 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.412 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.465 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.917 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.334 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.334 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.758 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.775 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.857 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 11.083 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 11.287 ns| 3
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 7.501 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 7.501 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.141 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.175 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 7.501 ns| 2
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.831 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.117 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Mon Aug 16 21:33:37 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf
Design file: ram2gs_lcmxo640c_impl1.ncd
Preference file: ram2gs_lcmxo640c_impl1.prf
Device,speed: LCMXO640C,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
PERIOD NET "PHI2_c" 350.000000 ns (0 errors) 113 items scored, 0 timing errors detected.
PERIOD NET "nCCAS_c" 350.000000 ns (0 errors) 0 items scored, 0 timing errors detected.
PERIOD NET "nCRAS_c" 350.000000 ns (0 errors) 0 items scored, 0 timing errors detected.
PERIOD NET "RCLK_c" 16.000000 ns (0 errors) 395 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors) 1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors) 0 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
113 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted_380 (from PHI2_c -)
Destination: FF Data in ADSubmitted_380 (to PHI2_c -)
Delay: 0.424ns (61.8% logic, 38.2% route), 2 logic levels.
Constraint Details:
0.424ns physical path delay SLICE_9 to SLICE_9 meets
-0.023ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.023ns) by 0.447ns
Physical Path Details:
Data path SLICE_9 to SLICE_9:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C5B.CLK to R5C5B.Q0 SLICE_9 (from PHI2_c)
ROUTE 2 0.162 R5C5B.Q0 to R5C5B.A0 ADSubmitted
CTOF_DEL --- 0.092 R5C5B.A0 to R5C5B.F0 SLICE_9
ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 n1361 (to PHI2_c)
--------
0.424 (61.8% logic, 38.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5B.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5B.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.113ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_378 (from PHI2_c -)
Destination: FF Data in XOR8MEG_381 (to PHI2_c -)
Delay: 1.084ns (32.7% logic, 67.3% route), 3 logic levels.
Constraint Details:
1.084ns physical path delay SLICE_18 to SLICE_96 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.113ns
Physical Path Details:
Data path SLICE_18 to SLICE_96:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C5A.CLK to R5C5A.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.238 R5C5A.Q0 to R5C5A.A1 CmdEnable
CTOF_DEL --- 0.092 R5C5A.A1 to R5C5A.F1 SLICE_18
ROUTE 3 0.225 R5C5A.F1 to R5C7C.C1 XOR8MEG_N_112
CTOF_DEL --- 0.092 R5C7C.C1 to R5C7C.F1 SLICE_90
ROUTE 1 0.267 R5C7C.F1 to R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
--------
1.084 (32.7% logic, 67.3% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5A.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C8B.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.118ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_378 (from PHI2_c -)
Destination: FF Data in Cmdn8MEGEN_383 (to PHI2_c -)
Delay: 1.089ns (32.5% logic, 67.5% route), 3 logic levels.
Constraint Details:
1.089ns physical path delay SLICE_18 to SLICE_23 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.118ns
Physical Path Details:
Data path SLICE_18 to SLICE_23:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C5A.CLK to R5C5A.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.238 R5C5A.Q0 to R5C5A.A1 CmdEnable
CTOF_DEL --- 0.092 R5C5A.A1 to R5C5A.F1 SLICE_18
ROUTE 3 0.225 R5C5A.F1 to R5C7C.C0 XOR8MEG_N_112
CTOF_DEL --- 0.092 R5C7C.C0 to R5C7C.F0 SLICE_90
ROUTE 2 0.272 R5C7C.F0 to R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
1.089 (32.5% logic, 67.5% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5A.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R6C7B.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.238ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_378 (from PHI2_c -)
Destination: FF Data in CmdUFMCS_385 (to PHI2_c -)
FF CmdUFMCLK_386
Delay: 1.209ns (29.3% logic, 70.7% route), 3 logic levels.
Constraint Details:
1.209ns physical path delay SLICE_18 to SLICE_83 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.238ns
Physical Path Details:
Data path SLICE_18 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C5A.CLK to R5C5A.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.238 R5C5A.Q0 to R5C5A.A1 CmdEnable
CTOF_DEL --- 0.092 R5C5A.A1 to R5C5A.F1 SLICE_18
ROUTE 3 0.225 R5C5A.F1 to R5C7A.C0 XOR8MEG_N_112
CTOF_DEL --- 0.092 R5C7A.C0 to R5C7A.F0 SLICE_72
ROUTE 2 0.392 R5C7A.F0 to R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
1.209 (29.3% logic, 70.7% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5A.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R7C8B.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.238ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_378 (from PHI2_c -)
Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -)
Delay: 1.209ns (29.3% logic, 70.7% route), 3 logic levels.
Constraint Details:
1.209ns physical path delay SLICE_18 to SLICE_88 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.238ns
Physical Path Details:
Data path SLICE_18 to SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C5A.CLK to R5C5A.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.238 R5C5A.Q0 to R5C5A.A1 CmdEnable
CTOF_DEL --- 0.092 R5C5A.A1 to R5C5A.F1 SLICE_18
ROUTE 3 0.225 R5C5A.F1 to R5C7A.C0 XOR8MEG_N_112
CTOF_DEL --- 0.092 R5C7A.C0 to R5C7A.F0 SLICE_72
ROUTE 2 0.392 R5C7A.F0 to R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
1.209 (29.3% logic, 70.7% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5A.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R4C9A.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.270ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted_380 (from PHI2_c -)
Destination: FF Data in CmdEnable_378 (to PHI2_c -)
Delay: 1.241ns (35.9% logic, 64.1% route), 4 logic levels.
Constraint Details:
1.241ns physical path delay SLICE_9 to SLICE_18 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.270ns
Physical Path Details:
Data path SLICE_9 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C5B.CLK to R5C5B.Q0 SLICE_9 (from PHI2_c)
ROUTE 2 0.258 R5C5B.Q0 to R5C5B.B1 ADSubmitted
CTOF_DEL --- 0.092 R5C5B.B1 to R5C5B.F1 SLICE_9
ROUTE 1 0.123 R5C5B.F1 to R5C5D.C1 n2080
CTOF_DEL --- 0.092 R5C5D.C1 to R5C5D.F1 SLICE_77
ROUTE 1 0.253 R5C5D.F1 to R5C5D.B0 n2286
CTOF_DEL --- 0.092 R5C5D.B0 to R5C5D.F0 SLICE_77
ROUTE 1 0.161 R5C5D.F0 to R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
--------
1.241 (35.9% logic, 64.1% route), 4 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5B.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5A.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.276ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_378 (from PHI2_c -)
Destination: FF Data in CmdSubmitted_384 (to PHI2_c -)
Delay: 1.247ns (28.4% logic, 71.6% route), 3 logic levels.
Constraint Details:
1.247ns physical path delay SLICE_18 to SLICE_19 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.276ns
Physical Path Details:
Data path SLICE_18 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C5A.CLK to R5C5A.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.238 R5C5A.Q0 to R5C5A.A1 CmdEnable
CTOF_DEL --- 0.092 R5C5A.A1 to R5C5A.F1 SLICE_18
ROUTE 3 0.225 R5C5A.F1 to R5C7C.C0 XOR8MEG_N_112
CTOF_DEL --- 0.092 R5C7C.C0 to R5C7C.F0 SLICE_90
ROUTE 2 0.430 R5C7C.F0 to R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
1.247 (28.4% logic, 71.6% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5A.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R9C8B.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.299ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted_379 (from PHI2_c -)
Destination: FF Data in CmdEnable_378 (to PHI2_c -)
Delay: 1.270ns (35.1% logic, 64.9% route), 4 logic levels.
Constraint Details:
1.270ns physical path delay SLICE_14 to SLICE_18 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.299ns
Physical Path Details:
Data path SLICE_14 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C5C.CLK to R5C5C.Q0 SLICE_14 (from PHI2_c)
ROUTE 1 0.238 R5C5C.Q0 to R5C5C.A1 C1Submitted
CTOF_DEL --- 0.092 R5C5C.A1 to R5C5C.F1 SLICE_14
ROUTE 1 0.172 R5C5C.F1 to R5C5D.B1 n2098
CTOF_DEL --- 0.092 R5C5D.B1 to R5C5D.F1 SLICE_77
ROUTE 1 0.253 R5C5D.F1 to R5C5D.B0 n2286
CTOF_DEL --- 0.092 R5C5D.B0 to R5C5D.F0 SLICE_77
ROUTE 1 0.161 R5C5D.F0 to R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
--------
1.270 (35.1% logic, 64.9% route), 4 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5C.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5A.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 175.790ns (weighted slack = 351.580ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q XOR8MEG_381 (from PHI2_c -)
Destination: FF Data in RA11_358 (to PHI2_c +)
Delay: 0.779ns (33.6% logic, 66.4% route), 2 logic levels.
Constraint Details:
0.779ns physical path delay SLICE_96 to SLICE_31 meets
-0.011ns DIN_HLD and
-175.000ns delay constraint less
0.000ns skew requirement (totaling -175.011ns) by 175.790ns
Physical Path Details:
Data path SLICE_96 to SLICE_31:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C8B.CLK to R5C8B.Q0 SLICE_96 (from PHI2_c)
ROUTE 1 0.517 R5C8B.Q0 to R2C9A.B0 XOR8MEG
CTOF_DEL --- 0.092 R2C9A.B0 to R2C9A.F0 SLICE_31
ROUTE 1 0.000 R2C9A.F0 to R2C9A.DI0 RA11_N_180 (to PHI2_c)
--------
0.779 (33.6% logic, 66.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C8B.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_31:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R2C9A.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 176.484ns (weighted slack = 352.968ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i3 (from PHI2_c +)
Destination: FF Data in C1Submitted_379 (to PHI2_c -)
Delay: 1.455ns (23.4% logic, 76.6% route), 3 logic levels.
Constraint Details:
1.455ns physical path delay SLICE_98 to SLICE_14 meets
-0.029ns CE_HLD and
-175.000ns delay constraint less
0.000ns skew requirement (totaling -175.029ns) by 176.484ns
Physical Path Details:
Data path SLICE_98 to SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C3A.CLK to R2C3A.Q1 SLICE_98 (from PHI2_c)
ROUTE 1 0.382 R2C3A.Q1 to R4C2A.B1 Bank_3
CTOF_DEL --- 0.092 R4C2A.B1 to R4C2A.F1 SLICE_76
ROUTE 4 0.556 R4C2A.F1 to R5C6A.B1 n1285
CTOF_DEL --- 0.092 R5C6A.B1 to R5C6A.F1 SLICE_89
ROUTE 1 0.176 R5C6A.F1 to R5C5C.CE PHI2_N_114_enable_1 (to PHI2_c)
--------
1.455 (23.4% logic, 76.6% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_98:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R2C3A.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.120 39.PADDI to R5C5C.CLK PHI2_c
--------
1.120 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: PERIOD NET "RCLK_c" 16.000000 ns ;
395 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i11 (from RCLK_c +)
Destination: FF Data in IS_FSM__i12 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_72 to SLICE_72 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_72 to SLICE_72:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C7A.CLK to R5C7A.Q0 SLICE_72 (from RCLK_c)
ROUTE 1 0.161 R5C7A.Q0 to R5C7A.M1 n702 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R5C7A.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R5C7A.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i12 (from RCLK_c +)
Destination: FF Data in IS_FSM__i13 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_72 to SLICE_90 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_72 to SLICE_90:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C7A.CLK to R5C7A.Q1 SLICE_72 (from RCLK_c)
ROUTE 1 0.161 R5C7A.Q1 to R5C7C.M0 n701 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R5C7A.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_90:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R5C7C.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i7 (from RCLK_c +)
Destination: FF Data in IS_FSM__i8 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_73 to SLICE_73 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_73 to SLICE_73:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R9C8A.CLK to R9C8A.Q0 SLICE_73 (from RCLK_c)
ROUTE 1 0.161 R9C8A.Q0 to R9C8A.M1 n706 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_73:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R9C8A.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_73:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R9C8A.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i3 (from RCLK_c +)
Destination: FF Data in IS_FSM__i4 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_74 to SLICE_74 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_74 to SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C6C.CLK to R5C6C.Q0 SLICE_74 (from RCLK_c)
ROUTE 1 0.161 R5C6C.Q0 to R5C6C.M1 n710 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R5C6C.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R5C6C.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i6 (from RCLK_c +)
Destination: FF Data in IS_FSM__i7 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_75 to SLICE_73 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_75 to SLICE_73:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R9C8D.CLK to R9C8D.Q1 SLICE_75 (from RCLK_c)
ROUTE 1 0.161 R9C8D.Q1 to R9C8A.M0 n707 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R9C8D.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_73:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R9C8A.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i5 (from RCLK_c +)
Destination: FF Data in IS_FSM__i6 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_75 to SLICE_75 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_75 to SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R9C8D.CLK to R9C8D.Q0 SLICE_75 (from RCLK_c)
ROUTE 1 0.161 R9C8D.Q0 to R9C8D.M1 n708 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R9C8D.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R9C8D.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PHI2r_349 (from RCLK_c +)
Destination: FF Data in PHI2r2_350 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_85 to SLICE_78 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_85 to SLICE_78:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R10C8C.CLK to R10C8C.Q1 SLICE_85 (from RCLK_c)
ROUTE 1 0.161 R10C8C.Q1 to R10C8D.M1 PHI2r (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_85:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R10C8C.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_78:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R10C8D.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i2 (from RCLK_c +)
Destination: FF Data in IS_FSM__i3 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_87 to SLICE_74 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_87 to SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C6B.CLK to R5C6B.Q1 SLICE_87 (from RCLK_c)
ROUTE 1 0.161 R5C6B.Q1 to R5C6C.M0 n711 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_87:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R5C6B.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R5C6C.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i13 (from RCLK_c +)
Destination: FF Data in IS_FSM__i14 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_90 to SLICE_90 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_90 to SLICE_90:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C7C.CLK to R5C7C.Q0 SLICE_90 (from RCLK_c)
ROUTE 1 0.161 R5C7C.Q0 to R5C7C.M1 n700 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_90:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R5C7C.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_90:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R5C7C.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.345ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PHI2r2_350 (from RCLK_c +)
Destination: FF Data in PHI2r3_351 (to RCLK_c +)
Delay: 0.324ns (48.5% logic, 51.5% route), 1 logic levels.
Constraint Details:
0.324ns physical path delay SLICE_78 to SLICE_85 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.345ns
Physical Path Details:
Data path SLICE_78 to SLICE_85:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R10C8D.CLK to R10C8D.Q1 SLICE_78 (from RCLK_c)
ROUTE 3 0.167 R10C8D.Q1 to R10C8C.M0 PHI2r2 (to RCLK_c)
--------
0.324 (48.5% logic, 51.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_78:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R10C8D.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_85:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.435 86.PADDI to R10C8C.CLK RCLK_c
--------
0.435 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.949ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RA10_373 (from RCLK_c +)
Destination: Port Pad RA[10]
Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_55 and
1.462ns delay SLICE_55 to RA[10] (totaling 1.949ns) meets
0.000ns hold offset RCLK to RA[10] by 1.949ns
Physical Path Details:
Clock path RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C5A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_55 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C5A.CLK to R2C5A.Q0 SLICE_55 (from RCLK_c)
ROUTE 1 0.197 R2C5A.Q0 to 87.PADDO n980
DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10]
--------
1.462 (86.5% logic, 13.5% route), 2 logic levels.
Report: 1.949ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.668ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[9]
Data Path Delay: 2.181ns (62.2% logic, 37.8% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.181ns delay SLICE_64 to RA[9] (totaling 2.668ns) meets
0.000ns hold offset RCLK to RA[9] by 2.668ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.199 R5C9A.Q0 to R4C9A.D1 nRowColSel
CTOF_DEL --- 0.092 R4C9A.D1 to R4C9A.F1 SLICE_88
ROUTE 1 0.625 R4C9A.F1 to 85.PADDO RA_c_9
DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9]
--------
2.181 (62.2% logic, 37.8% route), 3 logic levels.
Report: 2.668ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.689ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[8]
Data Path Delay: 2.202ns (61.6% logic, 38.4% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.202ns delay SLICE_64 to RA[8] (totaling 2.689ns) meets
0.000ns hold offset RCLK to RA[8] by 2.689ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.451 R5C9A.Q0 to R3C2B.D0 nRowColSel
CTOF_DEL --- 0.092 R3C2B.D0 to R3C2B.F0 SLICE_95
ROUTE 1 0.394 R3C2B.F0 to 96.PADDO RA_c_8
DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8]
--------
2.202 (61.6% logic, 38.4% route), 3 logic levels.
Report: 2.689ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.572ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[7]
Data Path Delay: 2.085ns (65.1% logic, 34.9% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.085ns delay SLICE_64 to RA[7] (totaling 2.572ns) meets
0.000ns hold offset RCLK to RA[7] by 2.572ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.531 R5C9A.Q0 to R2C2A.C0 nRowColSel
CTOF_DEL --- 0.092 R2C2A.C0 to R2C2A.F0 SLICE_97
ROUTE 1 0.197 R2C2A.F0 to 100.PADDO RA_c_7
DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7]
--------
2.085 (65.1% logic, 34.9% route), 3 logic levels.
Report: 2.572ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.652ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[6]
Data Path Delay: 2.165ns (62.7% logic, 37.3% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.165ns delay SLICE_64 to RA[6] (totaling 2.652ns) meets
0.000ns hold offset RCLK to RA[6] by 2.652ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.452 R5C9A.Q0 to R2C3A.D0 nRowColSel
CTOF_DEL --- 0.092 R2C3A.D0 to R2C3A.F0 SLICE_98
ROUTE 1 0.356 R2C3A.F0 to 91.PADDO RA_c_6
DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6]
--------
2.165 (62.7% logic, 37.3% route), 3 logic levels.
Report: 2.652ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.652ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[5]
Data Path Delay: 2.165ns (62.7% logic, 37.3% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.165ns delay SLICE_64 to RA[5] (totaling 2.652ns) meets
0.000ns hold offset RCLK to RA[5] by 2.652ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.452 R5C9A.Q0 to R2C3A.D1 nRowColSel
CTOF_DEL --- 0.092 R2C3A.D1 to R2C3A.F1 SLICE_98
ROUTE 1 0.356 R2C3A.F1 to 95.PADDO RA_c_5
DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5]
--------
2.165 (62.7% logic, 37.3% route), 3 logic levels.
Report: 2.652ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.776ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[4]
Data Path Delay: 2.289ns (59.3% logic, 40.7% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.289ns delay SLICE_64 to RA[4] (totaling 2.776ns) meets
0.000ns hold offset RCLK to RA[4] by 2.776ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.178 R5C9A.Q0 to R5C9A.D1 nRowColSel
CTOF_DEL --- 0.092 R5C9A.D1 to R5C9A.F1 SLICE_64
ROUTE 1 0.754 R5C9A.F1 to 99.PADDO RA_c_4
DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4]
--------
2.289 (59.3% logic, 40.7% route), 3 logic levels.
Report: 2.776ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.772ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[3]
Data Path Delay: 2.285ns (59.4% logic, 40.6% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.285ns delay SLICE_64 to RA[3] (totaling 2.772ns) meets
0.000ns hold offset RCLK to RA[3] by 2.772ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.571 R5C9A.Q0 to R2C2C.D1 nRowColSel
CTOF_DEL --- 0.092 R2C2C.D1 to R2C2C.F1 SLICE_94
ROUTE 1 0.357 R2C2C.F1 to 97.PADDO RA_c_3
DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3]
--------
2.285 (59.4% logic, 40.6% route), 3 logic levels.
Report: 2.772ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.787ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[2]
Data Path Delay: 2.300ns (59.0% logic, 41.0% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.300ns delay SLICE_64 to RA[2] (totaling 2.787ns) meets
0.000ns hold offset RCLK to RA[2] by 2.787ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.451 R5C9A.Q0 to R3C2B.D1 nRowColSel
CTOF_DEL --- 0.092 R3C2B.D1 to R3C2B.F1 SLICE_95
ROUTE 1 0.492 R3C2B.F1 to 94.PADDO RA_c_2
DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2]
--------
2.300 (59.0% logic, 41.0% route), 3 logic levels.
Report: 2.787ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.855ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[1]
Data Path Delay: 2.368ns (57.3% logic, 42.7% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.368ns delay SLICE_64 to RA[1] (totaling 2.855ns) meets
0.000ns hold offset RCLK to RA[1] by 2.855ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.531 R5C9A.Q0 to R2C2C.C0 nRowColSel
CTOF_DEL --- 0.092 R2C2C.C0 to R2C2C.F0 SLICE_94
ROUTE 1 0.480 R2C2C.F0 to 89.PADDO RA_c_1
DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1]
--------
2.368 (57.3% logic, 42.7% route), 3 logic levels.
Report: 2.855ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.893ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[0]
Data Path Delay: 2.406ns (56.4% logic, 43.6% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.406ns delay SLICE_64 to RA[0] (totaling 2.893ns) meets
0.000ns hold offset RCLK to RA[0] by 2.893ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.310 R5C9A.Q0 to R8C9C.D1 nRowColSel
CTOF_DEL --- 0.092 R8C9C.D1 to R8C9C.F1 SLICE_92
ROUTE 1 0.739 R8C9C.F1 to 98.PADDO RA_c_0
DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0]
--------
2.406 (56.4% logic, 43.6% route), 3 logic levels.
Report: 2.893ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.949ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCS_369 (from RCLK_c +)
Destination: Port Pad nRCS
Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_60 and
1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
0.000ns hold offset RCLK to nRCS by 1.949ns
Physical Path Details:
Clock path RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C9C.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_60 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C9C.CLK to R2C9C.Q0 SLICE_60 (from RCLK_c)
ROUTE 1 0.197 R2C9C.Q0 to 77.PADDO nRCS_c
DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS
--------
1.462 (86.5% logic, 13.5% route), 2 logic levels.
Report: 1.949ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.949ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RCKE_368 (from RCLK_c +)
Destination: Port Pad RCKE
Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_34 and
1.462ns delay SLICE_34 to RCKE (totaling 1.949ns) meets
0.000ns hold offset RCLK to RCKE by 1.949ns
Physical Path Details:
Clock path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C7C.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_34 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C7C.CLK to R2C7C.Q0 SLICE_34 (from RCLK_c)
ROUTE 4 0.197 R2C7C.Q0 to 82.PADDO RCKE_c
DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE
--------
1.462 (86.5% logic, 13.5% route), 2 logic levels.
Report: 1.949ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.356ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRWE_372 (from RCLK_c +)
Destination: Port Pad nRWE
Data Path Delay: 1.869ns (67.7% logic, 32.3% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_63 and
1.869ns delay SLICE_63 to nRWE (totaling 2.356ns) meets
0.000ns hold offset RCLK to nRWE by 2.356ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R10C9C.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_63 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R10C9C.CLK to R10C9C.Q0 SLICE_63 (from RCLK_c)
ROUTE 1 0.604 R10C9C.Q0 to 72.PADDO nRWE_c
DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE
--------
1.869 (67.7% logic, 32.3% route), 2 logic levels.
Report: 2.356ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.363ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRRAS_370 (from RCLK_c +)
Destination: Port Pad nRRAS
Data Path Delay: 1.876ns (67.4% logic, 32.6% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_61 and
1.876ns delay SLICE_61 to nRRAS (totaling 2.363ns) meets
0.000ns hold offset RCLK to nRRAS by 2.363ns
Physical Path Details:
Clock path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R3C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_61 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R3C2A.CLK to R3C2A.Q0 SLICE_61 (from RCLK_c)
ROUTE 2 0.611 R3C2A.Q0 to 73.PADDO nRRAS_c
DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS
--------
1.876 (67.4% logic, 32.6% route), 2 logic levels.
Report: 2.363ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.949ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCAS_371 (from RCLK_c +)
Destination: Port Pad nRCAS
Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_58 and
1.462ns delay SLICE_58 to nRCAS (totaling 1.949ns) meets
0.000ns hold offset RCLK to nRCAS by 1.949ns
Physical Path Details:
Clock path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C9B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_58 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C9B.CLK to R2C9B.Q0 SLICE_58 (from RCLK_c)
ROUTE 1 0.197 R2C9B.Q0 to 78.PADDO nRCAS_c
DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS
--------
1.462 (86.5% logic, 13.5% route), 2 logic levels.
Report: 1.949ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.523ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQMH
Data Path Delay: 2.036ns (66.7% logic, 33.3% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.036ns delay SLICE_64 to RDQMH (totaling 2.523ns) meets
0.000ns hold offset RCLK to RDQMH by 2.523ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.199 R5C9A.Q0 to R4C9A.D0 nRowColSel
CTOF_DEL --- 0.092 R4C9A.D0 to R4C9A.F0 SLICE_88
ROUTE 1 0.480 R4C9A.F0 to 76.PADDO RDQMH_c
DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH
--------
2.036 (66.7% logic, 33.3% route), 3 logic levels.
Report: 2.523ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQML
Data Path Delay: 1.864ns (72.8% logic, 27.2% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.864ns delay SLICE_64 to RDQML (totaling 2.351ns) meets
0.000ns hold offset RCLK to RDQML by 2.351ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C9A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C9A.CLK to R5C9A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.310 R5C9A.Q0 to R8C9C.D0 nRowColSel
CTOF_DEL --- 0.092 R8C9C.D0 to R8C9C.F0 SLICE_92
ROUTE 1 0.197 R8C9C.F0 to 61.PADDO RDQML_c
DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML
--------
1.864 (72.8% logic, 27.2% route), 3 logic levels.
Report: 2.351ns is the maximum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2
| | |
PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.668 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.689 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.572 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.652 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.652 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.776 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.772 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.787 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.855 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.893 ns| 3
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.356 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.363 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.523 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.351 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------