
            Lattice Mapping Report File for Design Module 'RAM2GS'


Design Information
------------------

Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
     RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
     RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf //Ma
     c/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_s
     ynplify.lpf -lpf //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui
     -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml 
Target Vendor:  LATTICE
Target Device:  LCMXO2-1200HCTQFP100
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
Mapped on:  10/19/23  23:50:56

Design Summary
--------------

   Number of registers:    110 out of  1520 (7%)
      PFU registers:           85 out of  1280 (7%)
      PIO registers:           25 out of   240 (10%)
   Number of SLICEs:       115 out of   640 (18%)
      SLICEs as Logic/ROM:    115 out of   640 (18%)
      SLICEs as RAM:            0 out of   480 (0%)
      SLICEs as Carry:         10 out of   640 (2%)
   Number of LUT4s:        229 out of  1280 (18%)
      Number used as logic LUTs:        209
      Number used as distributed RAM:     0
      Number used as ripple logic:       20
      Number used as shift registers:     0
   Number of PIO sites used: 64 + 4(JTAG) out of 80 (85%)
   Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
      Number of IDDR cells:   0
      Number of ODDR cells:   1
      Number of TDDR cells:   0
   Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
      Number of PIO using IDDR only:        0 (0 differential)
      Number of PIO using ODDR only:        1 (0 differential)
      Number of PIO using TDDR only:        0 (0 differential)
      Number of PIO using IDDR/ODDR:        0 (0 differential)
      Number of PIO using IDDR/TDDR:        0 (0 differential)
      Number of PIO using ODDR/TDDR:        0 (0 differential)
      Number of PIO using IDDR/ODDR/TDDR:   0 (0 differential)
   Number of block RAMs:  0 out of 7 (0%)
   Number of GSRs:        0 out of 1 (0%)
   EFB used :        Yes
   JTAG used :       No
   Readback used :   No
   Oscillator used : No
   Startup used :    No
   POR :             On
   Bandgap :         On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 1 (0%)

                                    Page 1




Design:  RAM2GS                                        Date:  10/19/23  23:50:56

Design Summary (cont)
---------------------
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  4
     Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
     Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK )
     Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
     Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
   Number of Clock Enables:  5
     Net N_103: 1 loads, 1 LSLICEs
     Net XOR8MEG18: 5 loads, 5 LSLICEs
     Net N_122: 9 loads, 9 LSLICEs
     Net N_244_i: 2 loads, 2 LSLICEs
     Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
   Number of LSRs:  5
     Net RA10s_i: 1 loads, 0 LSLICEs
     Net wb_rst10: 3 loads, 3 LSLICEs
     Net wb_rst: 1 loads, 0 LSLICEs
     Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
     Net RASr2: 2 loads, 2 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net InitReady: 31 loads
     Net FS[12]: 23 loads
     Net FS[13]: 23 loads
     Net FS[11]: 21 loads
     Net N_132: 20 loads
     Net FS[14]: 18 loads
     Net FS[10]: 16 loads
     Net FS[9]: 14 loads
     Net Ready: 14 loads
     Net Ready_fast: 14 loads




   Number of warnings:  1
   Number of errors:    0
     

Design Errors/Warnings
----------------------

WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
     temporarily disable certain features of the device including Power
     Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
     Functionality is restored after the Flash Memory (UFM/Configuration)
     Interface is disabled using Disable Configuration Interface command 0x26
     followed by Bypass command 0xFF. 


                                    Page 2




Design:  RAM2GS                                        Date:  10/19/23  23:50:56

IO (PIO) Attributes
-------------------

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| RD[0]               | BIDIR     | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| Dout[0]             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| PHI2                | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| RDQML               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RDQMH               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| nRCAS               | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| nRRAS               | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| nRWE                | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RCKE                | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RCLKout             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RCLK                | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| nRCS                | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RD[7]               | BIDIR     | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RD[6]               | BIDIR     | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RD[5]               | BIDIR     | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RD[4]               | BIDIR     | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RD[3]               | BIDIR     | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RD[2]               | BIDIR     | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RD[1]               | BIDIR     | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RA[11]              | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RA[10]              | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RA[9]               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RA[8]               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RA[7]               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RA[6]               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RA[5]               | OUTPUT    | LVCMOS33  |            |

                                    Page 3




Design:  RAM2GS                                        Date:  10/19/23  23:50:56

IO (PIO) Attributes (cont)
--------------------------
+---------------------+-----------+-----------+------------+
| RA[4]               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RA[3]               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RA[2]               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RA[1]               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RA[0]               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| RBA[1]              | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| RBA[0]              | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| LED                 | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| nFWE                | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| nCRAS               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| nCCAS               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Dout[7]             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Dout[6]             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Dout[5]             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Dout[4]             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Dout[3]             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Dout[2]             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Dout[1]             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Din[7]              | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| Din[6]              | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| Din[5]              | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| Din[4]              | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| Din[3]              | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| Din[2]              | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| Din[1]              | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| Din[0]              | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| CROW[1]             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| CROW[0]             | INPUT     | LVCMOS33  |            |

                                    Page 4




Design:  RAM2GS                                        Date:  10/19/23  23:50:56

IO (PIO) Attributes (cont)
--------------------------
+---------------------+-----------+-----------+------------+
| MAin[9]             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| MAin[8]             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| MAin[7]             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| MAin[6]             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| MAin[5]             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| MAin[4]             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| MAin[3]             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| MAin[2]             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| MAin[1]             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| MAin[0]             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+

Removed logic
-------------

Block GSR_INST undriven or does not drive anything - clipped.
Signal nCRAS_c_i was merged into signal nCRAS_c
Signal RASr2_i was merged into signal RASr2
Signal XOR8MEG.CN was merged into signal PHI2_c
Signal ufmefb/VCC undriven or does not drive anything - clipped.
Signal ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.

                                    Page 5




Design:  RAM2GS                                        Date:  10/19/23  23:50:56

Removed logic (cont)
--------------------
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block nCRAS_pad_RNIBPVB was optimized away.
Block RASr2_RNIAFR1 was optimized away.
Block XOR8MEG.CN was optimized away.
Block ufmefb/VCC was optimized away.
Block ufmefb/GND was optimized away.

     

Embedded Functional Block Connection Summary
--------------------------------------------

   Desired WISHBONE clock frequency: 66.7 MHz
   Clock source:                     RCLK_c
   Reset source:                     wb_rst
   Functions mode:
      I2C #1 (Primary) Function:     DISABLED
      I2C #2 (Secondary) Function:   DISABLED
      SPI Function:                  DISABLED
      Timer/Counter Function:        DISABLED
      Timer/Counter Mode:            WB
      UFM Connection:                ENABLED
      PLL0 Connection:               DISABLED

                                    Page 6




Design:  RAM2GS                                        Date:  10/19/23  23:50:56

Embedded Functional Block Connection Summary (cont)
---------------------------------------------------
      PLL1 Connection:               DISABLED
   I2C Function Summary:
   --------------------
      None
   SPI Function Summary:
   --------------------
      None
   Timer/Counter Function Summary:
   ------------------------------
      None
   UFM Function Summary:
   --------------------
      UFM Utilization:        General Purpose Flash Memory
      Initialized UFM Pages:  321 Pages (321*128 Bits)
      Available General
      Purpose Flash Memory:   511 Pages (511*128 Bits)

           EBR Blocks with Unique
      Initialization Data:    0

           WID		EBR Instance
      ---		------------


ASIC Components
---------------

Instance Name: ufmefb/EFBInst_0
         Type: EFB

Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs  
   Total REAL Time: 0 secs  
   Peak Memory Usage: 63 MB
        




















                                    Page 7


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