# Lattice Map TRACE Report

    Map TRACE Report

    Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd.
    Design name: RAM2GS
    NCD version: 3.3
    Vendor:      LATTICE
    Device:      LCMXO2-1200HC
    Package:     TQFP100
    Performance: 4
    Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
    Package Status:                     Final          Version 1.44.
    Performance Hardware Data Status:   Final          Version 34.4.
    Setup and Hold Report

    --------------------------------------------------------------------------------
    Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
    Thu Oct 19 23:50:57 2023

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
    Design file:     ram2gs_lcmxo2_1200hc_impl1_map.ncd
    Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
    Device,speed:    LCMXO2-1200HC,4
    Report level:    verbose report, limited to 1 item per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)            147 items scored, 0 timing errors detected.
    Report:   57.904MHz is the maximum frequency for this preference.

    FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.
    Report:  150.150MHz is the maximum frequency for this preference.

    FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.
    Report:  150.150MHz is the maximum frequency for this preference.

    FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)            868 items scored, 0 timing errors detected.
    Report:   97.666MHz is the maximum frequency for this preference.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
                147 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 163.779ns (weighted slack = 327.558ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
       Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)

       Delay:               8.469ns  (36.0% logic, 64.0% route), 6 logic levels.

     Constraint Details:

          8.469ns physical path delay Din[0]_MGIOL to SLICE_10 meets
        172.414ns delay constraint less
          0.166ns DIN_SET requirement (totaling 172.248ns) by 163.779ns

     Physical Path Details:

          Data path Din[0]_MGIOL to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    C2INP_DEL   ---     0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
    ROUTE         1   e 1.234 *n[0]_MGIOL.IN to    SLICE_89.A0 Bank[0]
    CTOF_DEL    ---     0.495    SLICE_89.A0 to    SLICE_89.F0 SLICE_89
    ROUTE         1   e 1.234    SLICE_89.F0 to    SLICE_75.C1 un1_ADWR_i_o2_10
    CTOF_DEL    ---     0.495    SLICE_75.C1 to    SLICE_75.F1 SLICE_75
    ROUTE         8   e 0.480    SLICE_75.F1 to    SLICE_75.B0 N_294
    CTOF_DEL    ---     0.495    SLICE_75.B0 to    SLICE_75.F0 SLICE_75
    ROUTE         2   e 1.234    SLICE_75.F0 to    SLICE_73.C0 N_382
    CTOF_DEL    ---     0.495    SLICE_73.C0 to    SLICE_73.F0 SLICE_73
    ROUTE         2   e 1.234    SLICE_73.F0 to    SLICE_10.C0 CmdEnable17
    CTOF_DEL    ---     0.495    SLICE_10.C0 to    SLICE_10.F0 SLICE_10
    ROUTE         1   e 0.001    SLICE_10.F0 to   SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c)
                      --------
                        8.469   (36.0% logic, 64.0% route), 6 logic levels.

    Report:   57.904MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed:  The following path meets requirements by 338.168ns
             The internal maximum frequency of the following component is 150.150 MHz

     Logical Details:  Cell type  Pin name       Component name

       Destination:    PIO        PAD            nCCAS

       Delay:               6.660ns -- based on Minimum Pulse Width

    Report:  150.150MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed:  The following path meets requirements by 338.168ns
             The internal maximum frequency of the following component is 150.150 MHz

     Logical Details:  Cell type  Pin name       Component name

       Destination:    PIO        PAD            nCRAS

       Delay:               6.660ns -- based on Minimum Pulse Width

    Report:  150.150MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
                868 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 5.761ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[11]  (from RCLK_c +)
       Destination:    FF         Data in        wb_adr[0]  (to RCLK_c +)

       Delay:              10.073ns  (34.0% logic, 66.0% route), 7 logic levels.

     Constraint Details:

         10.073ns physical path delay SLICE_4 to SLICE_48 meets
         16.000ns delay constraint less
          0.166ns DIN_SET requirement (totaling 15.834ns) by 5.761ns

     Physical Path Details:

          Data path SLICE_4 to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452    SLICE_4.CLK to     SLICE_4.Q0 SLICE_4 (from RCLK_c)
    ROUTE        21   e 1.234     SLICE_4.Q0 to    SLICE_66.B1 FS[11]
    CTOF_DEL    ---     0.495    SLICE_66.B1 to    SLICE_66.F1 SLICE_66
    ROUTE         1   e 0.480    SLICE_66.F1 to    SLICE_66.D0 wb_adr_5_i_i_a2_3_0[0]
    CTOF_DEL    ---     0.495    SLICE_66.D0 to    SLICE_66.F0 SLICE_66
    ROUTE         1   e 1.234    SLICE_66.F0 to    SLICE_86.D0 wb_adr_5_i_i_1_0_tz_0[0]
    CTOF_DEL    ---     0.495    SLICE_86.D0 to    SLICE_86.F0 SLICE_86
    ROUTE         1   e 1.234    SLICE_86.F0 to    SLICE_85.C0 wb_adr_5_i_i_1_0[0]
    CTOF_DEL    ---     0.495    SLICE_85.C0 to    SLICE_85.F0 SLICE_85
    ROUTE         1   e 1.234    SLICE_85.F0 to    SLICE_77.D0 wb_adr_5_i_i_1[0]
    CTOF_DEL    ---     0.495    SLICE_77.D0 to    SLICE_77.F0 SLICE_77
    ROUTE         1   e 1.234    SLICE_77.F0 to    SLICE_48.D0 wb_adr_5_i_i_5[0]
    CTOF_DEL    ---     0.495    SLICE_48.D0 to    SLICE_48.F0 SLICE_48
    ROUTE         1   e 0.001    SLICE_48.F0 to   SLICE_48.DI0 N_283 (to RCLK_c)
                      --------
                       10.073   (34.0% logic, 66.0% route), 7 logic levels.

    Report:   97.666MHz is the maximum frequency for this preference.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference                              |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   57.904 MHz|   6
                                            |             |             |
    FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0
                                            |             |             |
    FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0
                                            |             |             |
    FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|   97.666 MHz|   7
                                            |             |             |
    ----------------------------------------------------------------------------

    All preferences were met.

    Clock Domains Analysis
    ------------------------

    Found 4 clocks:

    Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
       No transfer within this clock domain is found

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
       No transfer within this clock domain is found

    Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 48
       Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;

       Data transfers from:
       Clock Domain: nCRAS_c   Source: nCRAS.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

       Clock Domain: PHI2_c   Source: PHI2.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 21
       Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Timing summary (Setup):
    ---------------

    Timing errors: 0  Score: 0
    Cumulative negative slack: 0

    Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage)

    --------------------------------------------------------------------------------
    Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
    Thu Oct 19 23:50:58 2023

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
    Design file:     ram2gs_lcmxo2_1200hc_impl1_map.ncd
    Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
    Device,speed:    LCMXO2-1200HC,M
    Report level:    verbose report, limited to 1 item per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)            147 items scored, 0 timing errors detected.

    FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.

    FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.

    FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)            868 items scored, 0 timing errors detected.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
                147 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.447ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              ADSubmitted  (from PHI2_c -)
       Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)

       Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.

     Constraint Details:

          0.434ns physical path delay SLICE_10 to SLICE_10 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns

     Physical Path Details:

          Data path SLICE_10 to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133   SLICE_10.CLK to    SLICE_10.Q0 SLICE_10 (from PHI2_c)
    ROUTE         2   e 0.199    SLICE_10.Q0 to    SLICE_10.A0 ADSubmitted
    CTOF_DEL    ---     0.101    SLICE_10.A0 to    SLICE_10.F0 SLICE_10
    ROUTE         1   e 0.001    SLICE_10.F0 to   SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c)
                      --------
                        0.434   (53.9% logic, 46.1% route), 2 logic levels.

    ================================================================================
    Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
                868 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.351ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              CASr  (from RCLK_c +)
       Destination:    FF         Data in        CASr2  (to RCLK_c +)

       Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.

     Constraint Details:

          0.332ns physical path delay SLICE_12 to SLICE_12 meets
         -0.019ns M_HLD and
          0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns

     Physical Path Details:

          Data path SLICE_12 to SLICE_12:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133   SLICE_12.CLK to    SLICE_12.Q0 SLICE_12 (from RCLK_c)
    ROUTE         1   e 0.199    SLICE_12.Q0 to    SLICE_12.M1 CASr (to RCLK_c)
                      --------
                        0.332   (40.1% logic, 59.9% route), 1 logic levels.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference(MIN Delays)                  |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2
                                            |             |             |
    FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0
                                            |             |             |
    FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0
                                            |             |             |
    FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1
                                            |             |             |
    ----------------------------------------------------------------------------

    All preferences were met.

    Clock Domains Analysis
    ------------------------

    Found 4 clocks:

    Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
       No transfer within this clock domain is found

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
       No transfer within this clock domain is found

    Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 48
       Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;

       Data transfers from:
       Clock Domain: nCRAS_c   Source: nCRAS.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

       Clock Domain: PHI2_c   Source: PHI2.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 21
       Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Timing summary (Hold):
    ---------------

    Timing errors: 0  Score: 0
    Cumulative negative slack: 0

    Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage)

    Timing summary (Setup and Hold):
    ---------------

    Timing errors: 0 (setup), 0 (hold)
    Score: 0 (setup), 0 (hold)
    Cumulative negative slack: 0 (0+0)
    --------------------------------------------------------------------------------

    --------------------------------------------------------------------------------