# Lattice TRACE Report

    Place & Route TRACE Report

    Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd.
    Design name: RAM2GS
    NCD version: 3.3
    Vendor:      LATTICE
    Device:      LCMXO2-1200HC
    Package:     TQFP100
    Performance: 4
    Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
    Package Status:                     Final          Version 1.44.
    Performance Hardware Data Status:   Final          Version 34.4.
    Setup and Hold Report

    --------------------------------------------------------------------------------
    Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
    Thu Oct 19 23:51:11 2023

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
    Design file:     ram2gs_lcmxo2_1200hc_impl1.ncd
    Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
    Device,speed:    LCMXO2-1200HC,4
    Report level:    verbose report, limited to 10 items per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)            147 items scored, 0 timing errors detected.
    Report:   50.206MHz is the maximum frequency for this preference.

    FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.
    Report:  150.150MHz is the maximum frequency for this preference.

    FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.
    Report:  150.150MHz is the maximum frequency for this preference.

    FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)            868 items scored, 0 timing errors detected.
    Report:   98.020MHz is the maximum frequency for this preference.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
                147 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 162.455ns (weighted slack = 324.910ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
       Destination:    FF         Data in        CmdEnable  (to PHI2_c -)

       Delay:               9.620ns  (31.7% logic, 68.3% route), 6 logic levels.

     Constraint Details:

          9.620ns physical path delay Din[0]_MGIOL to SLICE_17 meets
        172.414ns delay constraint less
          0.173ns skew and
          0.166ns DIN_SET requirement (totaling 172.075ns) by 162.455ns

     Physical Path Details:

          Data path Din[0]_MGIOL to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    C2INP_DEL   ---     0.577    IOL_L3A.CLK to     IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
    ROUTE         1     2.751     IOL_L3A.IN to      R4C11A.B0 Bank[0]
    CTOF_DEL    ---     0.495      R4C11A.B0 to      R4C11A.F0 SLICE_89
    ROUTE         1     1.001      R4C11A.F0 to      R4C10A.B1 un1_ADWR_i_o2_10
    CTOF_DEL    ---     0.495      R4C10A.B1 to      R4C10A.F1 SLICE_75
    ROUTE         8     0.710      R4C10A.F1 to      R4C10A.B0 N_294
    CTOF_DEL    ---     0.495      R4C10A.B0 to      R4C10A.F0 SLICE_75
    ROUTE         2     1.093      R4C10A.F0 to      R5C11A.C0 N_382
    CTOF_DEL    ---     0.495      R5C11A.C0 to      R5C11A.F0 SLICE_73
    ROUTE         2     1.013      R5C11A.F0 to      R5C11D.B0 CmdEnable17
    CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_17
    ROUTE         1     0.000      R5C11D.F0 to     R5C11D.DI0 CmdEnable_s (to PHI2_c)
                      --------
                        9.620   (31.7% logic, 68.3% route), 6 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to Din[0]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.369        8.PADDI to    IOL_L3A.CLK PHI2_c
                      --------
                        4.369   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.196        8.PADDI to     R5C11D.CLK PHI2_c
                      --------
                        4.196   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 162.715ns (weighted slack = 325.430ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
       Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)

       Delay:               9.360ns  (32.6% logic, 67.4% route), 6 logic levels.

     Constraint Details:

          9.360ns physical path delay Din[0]_MGIOL to SLICE_10 meets
        172.414ns delay constraint less
          0.173ns skew and
          0.166ns DIN_SET requirement (totaling 172.075ns) by 162.715ns

     Physical Path Details:

          Data path Din[0]_MGIOL to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    C2INP_DEL   ---     0.577    IOL_L3A.CLK to     IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
    ROUTE         1     2.751     IOL_L3A.IN to      R4C11A.B0 Bank[0]
    CTOF_DEL    ---     0.495      R4C11A.B0 to      R4C11A.F0 SLICE_89
    ROUTE         1     1.001      R4C11A.F0 to      R4C10A.B1 un1_ADWR_i_o2_10
    CTOF_DEL    ---     0.495      R4C10A.B1 to      R4C10A.F1 SLICE_75
    ROUTE         8     0.710      R4C10A.F1 to      R4C10A.B0 N_294
    CTOF_DEL    ---     0.495      R4C10A.B0 to      R4C10A.F0 SLICE_75
    ROUTE         2     1.093      R4C10A.F0 to      R5C11A.C0 N_382
    CTOF_DEL    ---     0.495      R5C11A.C0 to      R5C11A.F0 SLICE_73
    ROUTE         2     0.753      R5C11A.F0 to      R5C12C.C0 CmdEnable17
    CTOF_DEL    ---     0.495      R5C12C.C0 to      R5C12C.F0 SLICE_10
    ROUTE         1     0.000      R5C12C.F0 to     R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
                      --------
                        9.360   (32.6% logic, 67.4% route), 6 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to Din[0]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.369        8.PADDI to    IOL_L3A.CLK PHI2_c
                      --------
                        4.369   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.196        8.PADDI to     R5C12C.CLK PHI2_c
                      --------
                        4.196   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 162.913ns (weighted slack = 325.826ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank_0io[7]  (from PHI2_c +)
       Destination:    FF         Data in        CmdEnable  (to PHI2_c -)

       Delay:               9.162ns  (33.3% logic, 66.7% route), 6 logic levels.

     Constraint Details:

          9.162ns physical path delay Din[7]_MGIOL to SLICE_17 meets
        172.414ns delay constraint less
          0.173ns skew and
          0.166ns DIN_SET requirement (totaling 172.075ns) by 162.913ns

     Physical Path Details:

          Data path Din[7]_MGIOL to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    C2INP_DEL   ---     0.577    IOL_L2C.CLK to     IOL_L2C.IN Din[7]_MGIOL (from PHI2_c)
    ROUTE         1     2.215     IOL_L2C.IN to       R3C9D.A0 Bank[7]
    CTOF_DEL    ---     0.495       R3C9D.A0 to       R3C9D.F0 SLICE_32
    ROUTE         1     1.079       R3C9D.F0 to      R4C10A.C1 un1_ADWR_i_o2_11
    CTOF_DEL    ---     0.495      R4C10A.C1 to      R4C10A.F1 SLICE_75
    ROUTE         8     0.710      R4C10A.F1 to      R4C10A.B0 N_294
    CTOF_DEL    ---     0.495      R4C10A.B0 to      R4C10A.F0 SLICE_75
    ROUTE         2     1.093      R4C10A.F0 to      R5C11A.C0 N_382
    CTOF_DEL    ---     0.495      R5C11A.C0 to      R5C11A.F0 SLICE_73
    ROUTE         2     1.013      R5C11A.F0 to      R5C11D.B0 CmdEnable17
    CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_17
    ROUTE         1     0.000      R5C11D.F0 to     R5C11D.DI0 CmdEnable_s (to PHI2_c)
                      --------
                        9.162   (33.3% logic, 66.7% route), 6 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to Din[7]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.369        8.PADDI to    IOL_L2C.CLK PHI2_c
                      --------
                        4.369   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.196        8.PADDI to     R5C11D.CLK PHI2_c
                      --------
                        4.196   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 163.173ns (weighted slack = 326.346ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank_0io[7]  (from PHI2_c +)
       Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)

       Delay:               8.902ns  (34.3% logic, 65.7% route), 6 logic levels.

     Constraint Details:

          8.902ns physical path delay Din[7]_MGIOL to SLICE_10 meets
        172.414ns delay constraint less
          0.173ns skew and
          0.166ns DIN_SET requirement (totaling 172.075ns) by 163.173ns

     Physical Path Details:

          Data path Din[7]_MGIOL to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    C2INP_DEL   ---     0.577    IOL_L2C.CLK to     IOL_L2C.IN Din[7]_MGIOL (from PHI2_c)
    ROUTE         1     2.215     IOL_L2C.IN to       R3C9D.A0 Bank[7]
    CTOF_DEL    ---     0.495       R3C9D.A0 to       R3C9D.F0 SLICE_32
    ROUTE         1     1.079       R3C9D.F0 to      R4C10A.C1 un1_ADWR_i_o2_11
    CTOF_DEL    ---     0.495      R4C10A.C1 to      R4C10A.F1 SLICE_75
    ROUTE         8     0.710      R4C10A.F1 to      R4C10A.B0 N_294
    CTOF_DEL    ---     0.495      R4C10A.B0 to      R4C10A.F0 SLICE_75
    ROUTE         2     1.093      R4C10A.F0 to      R5C11A.C0 N_382
    CTOF_DEL    ---     0.495      R5C11A.C0 to      R5C11A.F0 SLICE_73
    ROUTE         2     0.753      R5C11A.F0 to      R5C12C.C0 CmdEnable17
    CTOF_DEL    ---     0.495      R5C12C.C0 to      R5C12C.F0 SLICE_10
    ROUTE         1     0.000      R5C12C.F0 to     R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
                      --------
                        8.902   (34.3% logic, 65.7% route), 6 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to Din[7]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.369        8.PADDI to    IOL_L2C.CLK PHI2_c
                      --------
                        4.369   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.196        8.PADDI to     R5C12C.CLK PHI2_c
                      --------
                        4.196   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
       Destination:    FF         Data in        CmdLEDEN  (to PHI2_c -)

       Delay:               8.671ns  (23.8% logic, 76.2% route), 4 logic levels.

     Constraint Details:

          8.671ns physical path delay Din[0]_MGIOL to SLICE_18 meets
        172.414ns delay constraint less
          0.173ns skew and
          0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns

     Physical Path Details:

          Data path Din[0]_MGIOL to SLICE_18:

       Name    Fanout   Delay (ns)          Site               Resource
    C2INP_DEL   ---     0.577    IOL_L3A.CLK to     IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
    ROUTE         1     2.751     IOL_L3A.IN to      R4C11A.B0 Bank[0]
    CTOF_DEL    ---     0.495      R4C11A.B0 to      R4C11A.F0 SLICE_89
    ROUTE         1     1.001      R4C11A.F0 to      R4C10A.B1 un1_ADWR_i_o2_10
    CTOF_DEL    ---     0.495      R4C10A.B1 to      R4C10A.F1 SLICE_75
    ROUTE         8     1.444      R4C10A.F1 to      R5C11C.A1 N_294
    CTOF_DEL    ---     0.495      R5C11C.A1 to      R5C11C.F1 SLICE_106
    ROUTE         5     1.413      R5C11C.F1 to      R3C10B.CE XOR8MEG18 (to PHI2_c)
                      --------
                        8.671   (23.8% logic, 76.2% route), 4 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to Din[0]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.369        8.PADDI to    IOL_L3A.CLK PHI2_c
                      --------
                        4.369   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_18:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.196        8.PADDI to     R3C10B.CLK PHI2_c
                      --------
                        4.196   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
       Destination:    FF         Data in        CmdUFMShift  (to PHI2_c -)

       Delay:               8.671ns  (23.8% logic, 76.2% route), 4 logic levels.

     Constraint Details:

          8.671ns physical path delay Din[0]_MGIOL to SLICE_20 meets
        172.414ns delay constraint less
          0.173ns skew and
          0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns

     Physical Path Details:

          Data path Din[0]_MGIOL to SLICE_20:

       Name    Fanout   Delay (ns)          Site               Resource
    C2INP_DEL   ---     0.577    IOL_L3A.CLK to     IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
    ROUTE         1     2.751     IOL_L3A.IN to      R4C11A.B0 Bank[0]
    CTOF_DEL    ---     0.495      R4C11A.B0 to      R4C11A.F0 SLICE_89
    ROUTE         1     1.001      R4C11A.F0 to      R4C10A.B1 un1_ADWR_i_o2_10
    CTOF_DEL    ---     0.495      R4C10A.B1 to      R4C10A.F1 SLICE_75
    ROUTE         8     1.444      R4C10A.F1 to      R5C11C.A1 N_294
    CTOF_DEL    ---     0.495      R5C11C.A1 to      R5C11C.F1 SLICE_106
    ROUTE         5     1.413      R5C11C.F1 to      R4C10B.CE XOR8MEG18 (to PHI2_c)
                      --------
                        8.671   (23.8% logic, 76.2% route), 4 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to Din[0]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.369        8.PADDI to    IOL_L3A.CLK PHI2_c
                      --------
                        4.369   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_20:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.196        8.PADDI to     R4C10B.CLK PHI2_c
                      --------
                        4.196   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
       Destination:    FF         Data in        CmdUFMWrite  (to PHI2_c -)

       Delay:               8.671ns  (23.8% logic, 76.2% route), 4 logic levels.

     Constraint Details:

          8.671ns physical path delay Din[0]_MGIOL to SLICE_21 meets
        172.414ns delay constraint less
          0.173ns skew and
          0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns

     Physical Path Details:

          Data path Din[0]_MGIOL to SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    C2INP_DEL   ---     0.577    IOL_L3A.CLK to     IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
    ROUTE         1     2.751     IOL_L3A.IN to      R4C11A.B0 Bank[0]
    CTOF_DEL    ---     0.495      R4C11A.B0 to      R4C11A.F0 SLICE_89
    ROUTE         1     1.001      R4C11A.F0 to      R4C10A.B1 un1_ADWR_i_o2_10
    CTOF_DEL    ---     0.495      R4C10A.B1 to      R4C10A.F1 SLICE_75
    ROUTE         8     1.444      R4C10A.F1 to      R5C11C.A1 N_294
    CTOF_DEL    ---     0.495      R5C11C.A1 to      R5C11C.F1 SLICE_106
    ROUTE         5     1.413      R5C11C.F1 to      R4C10D.CE XOR8MEG18 (to PHI2_c)
                      --------
                        8.671   (23.8% logic, 76.2% route), 4 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to Din[0]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.369        8.PADDI to    IOL_L3A.CLK PHI2_c
                      --------
                        4.369   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.196        8.PADDI to     R4C10D.CLK PHI2_c
                      --------
                        4.196   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 163.263ns (weighted slack = 326.526ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
       Destination:    FF         Data in        Cmdn8MEGEN  (to PHI2_c -)

       Delay:               8.671ns  (23.8% logic, 76.2% route), 4 logic levels.

     Constraint Details:

          8.671ns physical path delay Din[0]_MGIOL to SLICE_24 meets
        172.414ns delay constraint less
          0.173ns skew and
          0.307ns CE_SET requirement (totaling 171.934ns) by 163.263ns

     Physical Path Details:

          Data path Din[0]_MGIOL to SLICE_24:

       Name    Fanout   Delay (ns)          Site               Resource
    C2INP_DEL   ---     0.577    IOL_L3A.CLK to     IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
    ROUTE         1     2.751     IOL_L3A.IN to      R4C11A.B0 Bank[0]
    CTOF_DEL    ---     0.495      R4C11A.B0 to      R4C11A.F0 SLICE_89
    ROUTE         1     1.001      R4C11A.F0 to      R4C10A.B1 un1_ADWR_i_o2_10
    CTOF_DEL    ---     0.495      R4C10A.B1 to      R4C10A.F1 SLICE_75
    ROUTE         8     1.444      R4C10A.F1 to      R5C11C.A1 N_294
    CTOF_DEL    ---     0.495      R5C11C.A1 to      R5C11C.F1 SLICE_106
    ROUTE         5     1.413      R5C11C.F1 to      R3C10C.CE XOR8MEG18 (to PHI2_c)
                      --------
                        8.671   (23.8% logic, 76.2% route), 4 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to Din[0]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.369        8.PADDI to    IOL_L3A.CLK PHI2_c
                      --------
                        4.369   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_24:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.196        8.PADDI to     R3C10C.CLK PHI2_c
                      --------
                        4.196   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 163.326ns (weighted slack = 326.652ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank_0io[6]  (from PHI2_c +)
       Destination:    FF         Data in        CmdEnable  (to PHI2_c -)

       Delay:               8.749ns  (34.9% logic, 65.1% route), 6 logic levels.

     Constraint Details:

          8.749ns physical path delay Din[6]_MGIOL to SLICE_17 meets
        172.414ns delay constraint less
          0.173ns skew and
          0.166ns DIN_SET requirement (totaling 172.075ns) by 163.326ns

     Physical Path Details:

          Data path Din[6]_MGIOL to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    C2INP_DEL   ---     0.577    IOL_L2D.CLK to     IOL_L2D.IN Din[6]_MGIOL (from PHI2_c)
    ROUTE         1     1.802     IOL_L2D.IN to       R3C9D.D0 Bank[6]
    CTOF_DEL    ---     0.495       R3C9D.D0 to       R3C9D.F0 SLICE_32
    ROUTE         1     1.079       R3C9D.F0 to      R4C10A.C1 un1_ADWR_i_o2_11
    CTOF_DEL    ---     0.495      R4C10A.C1 to      R4C10A.F1 SLICE_75
    ROUTE         8     0.710      R4C10A.F1 to      R4C10A.B0 N_294
    CTOF_DEL    ---     0.495      R4C10A.B0 to      R4C10A.F0 SLICE_75
    ROUTE         2     1.093      R4C10A.F0 to      R5C11A.C0 N_382
    CTOF_DEL    ---     0.495      R5C11A.C0 to      R5C11A.F0 SLICE_73
    ROUTE         2     1.013      R5C11A.F0 to      R5C11D.B0 CmdEnable17
    CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_17
    ROUTE         1     0.000      R5C11D.F0 to     R5C11D.DI0 CmdEnable_s (to PHI2_c)
                      --------
                        8.749   (34.9% logic, 65.1% route), 6 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to Din[6]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.369        8.PADDI to    IOL_L2D.CLK PHI2_c
                      --------
                        4.369   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.196        8.PADDI to     R5C11D.CLK PHI2_c
                      --------
                        4.196   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 163.343ns (weighted slack = 326.686ns)

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
       Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)

       Delay:               8.732ns  (29.3% logic, 70.7% route), 5 logic levels.

     Constraint Details:

          8.732ns physical path delay Din[0]_MGIOL to SLICE_10 meets
        172.414ns delay constraint less
          0.173ns skew and
          0.166ns DIN_SET requirement (totaling 172.075ns) by 163.343ns

     Physical Path Details:

          Data path Din[0]_MGIOL to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    C2INP_DEL   ---     0.577    IOL_L3A.CLK to     IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
    ROUTE         1     2.751     IOL_L3A.IN to      R4C11A.B0 Bank[0]
    CTOF_DEL    ---     0.495      R4C11A.B0 to      R4C11A.F0 SLICE_89
    ROUTE         1     1.001      R4C11A.F0 to      R4C10A.B1 un1_ADWR_i_o2_10
    CTOF_DEL    ---     0.495      R4C10A.B1 to      R4C10A.F1 SLICE_75
    ROUTE         8     1.456      R4C10A.F1 to      R5C12C.A1 N_294
    CTOF_DEL    ---     0.495      R5C12C.A1 to      R5C12C.F1 SLICE_10
    ROUTE         1     0.967      R5C12C.F1 to      R5C12C.A0 N_22_i
    CTOF_DEL    ---     0.495      R5C12C.A0 to      R5C12C.F0 SLICE_10
    ROUTE         1     0.000      R5C12C.F0 to     R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
                      --------
                        8.732   (29.3% logic, 70.7% route), 5 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to Din[0]_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.369        8.PADDI to    IOL_L3A.CLK PHI2_c
                      --------
                        4.369   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     4.196        8.PADDI to     R5C12C.CLK PHI2_c
                      --------
                        4.196   (0.0% logic, 100.0% route), 0 logic levels.

    Report:   50.206MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed:  The following path meets requirements by 338.168ns
             The internal maximum frequency of the following component is 150.150 MHz

     Logical Details:  Cell type  Pin name       Component name

       Destination:    PIO        PAD            nCCAS

       Delay:               6.660ns -- based on Minimum Pulse Width

    Report:  150.150MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed:  The following path meets requirements by 338.168ns
             The internal maximum frequency of the following component is 150.150 MHz

     Logical Details:  Cell type  Pin name       Component name

       Destination:    PIO        PAD            nCRAS

       Delay:               6.660ns -- based on Minimum Pulse Width

    Report:  150.150MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
                868 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 5.798ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[12]  (from RCLK_c +)
       Destination:    FF         Data in        wb_adr[1]  (to RCLK_c +)

       Delay:              10.036ns  (24.2% logic, 75.8% route), 5 logic levels.

     Constraint Details:

         10.036ns physical path delay SLICE_4 to SLICE_48 meets
         16.000ns delay constraint less
          0.000ns skew and
          0.166ns DIN_SET requirement (totaling 15.834ns) by 5.798ns

     Physical Path Details:

          Data path SLICE_4 to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452      R5C5C.CLK to       R5C5C.Q1 SLICE_4 (from RCLK_c)
    ROUTE        23     2.663       R5C5C.Q1 to       R2C7A.A1 FS[12]
    CTOF_DEL    ---     0.495       R2C7A.A1 to       R2C7A.F1 SLICE_101
    ROUTE         4     2.173       R2C7A.F1 to       R4C7C.B1 N_142
    CTOF_DEL    ---     0.495       R4C7C.B1 to       R4C7C.F1 SLICE_65
    ROUTE         1     0.967       R4C7C.F1 to       R4C7A.A0 N_428_tz
    CTOF_DEL    ---     0.495       R4C7A.A0 to       R4C7A.F0 SLICE_61
    ROUTE         1     1.801       R4C7A.F0 to       R4C6C.A1 wb_adr_5_i_i_0[1]
    CTOF_DEL    ---     0.495       R4C6C.A1 to       R4C6C.F1 SLICE_48
    ROUTE         1     0.000       R4C6C.F1 to      R4C6C.DI1 N_282 (to RCLK_c)
                      --------
                       10.036   (24.2% logic, 75.8% route), 5 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_4:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R5C5C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R4C6C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 6.138ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         EFB        Port           ufmefb/EFBInst_0(ASIC)  (from RCLK_c +)
       Destination:    FF         Data in        n8MEGEN  (to RCLK_c +)

       Delay:               9.523ns  (76.3% logic, 23.7% route), 3 logic levels.

     Constraint Details:

          9.523ns physical path delay ufmefb/EFBInst_0 to SLICE_46 meets
         16.000ns delay constraint less
          0.173ns skew and
          0.166ns DIN_SET requirement (totaling 15.661ns) by 6.138ns

     Physical Path Details:

          Data path ufmefb/EFBInst_0 to SLICE_46:

       Name    Fanout   Delay (ns)          Site               Resource
    WCLKI2WBDA  ---     6.278     EFB.WBCLKI to    EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c)
    ROUTE         1     1.297    EFB.WBDATO0 to       R3C5B.C1 wb_dato[0]
    CTOF_DEL    ---     0.495       R3C5B.C1 to       R3C5B.F1 SLICE_108
    ROUTE         1     0.958       R3C5B.F1 to       R3C8B.D0 n8MEGENe_1_0
    CTOF_DEL    ---     0.495       R3C8B.D0 to       R3C8B.F0 SLICE_46
    ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 n8MEGENe_0 (to RCLK_c)
                      --------
                        9.523   (76.3% logic, 23.7% route), 3 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to ufmefb/EFBInst_0:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.437       63.PADDI to     EFB.WBCLKI RCLK_c
                      --------
                        2.437   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_46:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R3C8B.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 6.414ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[12]  (from RCLK_c +)
       Destination:    FF         Data in        wb_adr[0]  (to RCLK_c +)

       Delay:               9.420ns  (36.3% logic, 63.7% route), 7 logic levels.

     Constraint Details:

          9.420ns physical path delay SLICE_4 to SLICE_48 meets
         16.000ns delay constraint less
          0.000ns skew and
          0.166ns DIN_SET requirement (totaling 15.834ns) by 6.414ns

     Physical Path Details:

          Data path SLICE_4 to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452      R5C5C.CLK to       R5C5C.Q1 SLICE_4 (from RCLK_c)
    ROUTE        23     2.237       R5C5C.Q1 to       R2C7D.A1 FS[12]
    CTOF_DEL    ---     0.495       R2C7D.A1 to       R2C7D.F1 SLICE_66
    ROUTE         1     0.436       R2C7D.F1 to       R2C7D.C0 wb_adr_5_i_i_a2_3_0[0]
    CTOF_DEL    ---     0.495       R2C7D.C0 to       R2C7D.F0 SLICE_66
    ROUTE         1     0.967       R2C7D.F0 to       R2C7B.A0 wb_adr_5_i_i_1_0_tz_0[0]
    CTOF_DEL    ---     0.495       R2C7B.A0 to       R2C7B.F0 SLICE_86
    ROUTE         1     1.001       R2C7B.F0 to       R2C6A.B0 wb_adr_5_i_i_1_0[0]
    CTOF_DEL    ---     0.495       R2C6A.B0 to       R2C6A.F0 SLICE_85
    ROUTE         1     1.042       R2C6A.F0 to       R4C6D.D0 wb_adr_5_i_i_1[0]
    CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_77
    ROUTE         1     0.315       R4C6D.F0 to       R4C6C.D0 wb_adr_5_i_i_5[0]
    CTOF_DEL    ---     0.495       R4C6C.D0 to       R4C6C.F0 SLICE_48
    ROUTE         1     0.000       R4C6C.F0 to      R4C6C.DI0 N_283 (to RCLK_c)
                      --------
                        9.420   (36.3% logic, 63.7% route), 7 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_4:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R5C5C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R4C6C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 6.769ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[9]  (from RCLK_c +)
       Destination:    FF         Data in        wb_adr[1]  (to RCLK_c +)

       Delay:               9.065ns  (32.3% logic, 67.7% route), 6 logic levels.

     Constraint Details:

          9.065ns physical path delay SLICE_5 to SLICE_48 meets
         16.000ns delay constraint less
          0.000ns skew and
          0.166ns DIN_SET requirement (totaling 15.834ns) by 6.769ns

     Physical Path Details:

          Data path SLICE_5 to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452      R5C5B.CLK to       R5C5B.Q0 SLICE_5 (from RCLK_c)
    ROUTE        14     1.803       R5C5B.Q0 to       R3C6D.B1 FS[9]
    CTOF_DEL    ---     0.495       R3C6D.B1 to       R3C6D.F1 SLICE_80
    ROUTE         7     1.131       R3C6D.F1 to       R4C7C.C0 N_125
    CTOF_DEL    ---     0.495       R4C7C.C0 to       R4C7C.F0 SLICE_65
    ROUTE         1     0.436       R4C7C.F0 to       R4C7C.C1 wb_adr_5_i_i_a2_0[1]
    CTOF_DEL    ---     0.495       R4C7C.C1 to       R4C7C.F1 SLICE_65
    ROUTE         1     0.967       R4C7C.F1 to       R4C7A.A0 N_428_tz
    CTOF_DEL    ---     0.495       R4C7A.A0 to       R4C7A.F0 SLICE_61
    ROUTE         1     1.801       R4C7A.F0 to       R4C6C.A1 wb_adr_5_i_i_0[1]
    CTOF_DEL    ---     0.495       R4C6C.A1 to       R4C6C.F1 SLICE_48
    ROUTE         1     0.000       R4C6C.F1 to      R4C6C.DI1 N_282 (to RCLK_c)
                      --------
                        9.065   (32.3% logic, 67.7% route), 6 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_5:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R5C5B.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R4C6C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 7.019ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[13]  (from RCLK_c +)
       Destination:    FF         Data in        wb_dati[7]  (to RCLK_c +)

       Delay:               8.815ns  (33.2% logic, 66.8% route), 6 logic levels.

     Constraint Details:

          8.815ns physical path delay SLICE_3 to SLICE_56 meets
         16.000ns delay constraint less
          0.000ns skew and
          0.166ns DIN_SET requirement (totaling 15.834ns) by 7.019ns

     Physical Path Details:

          Data path SLICE_3 to SLICE_56:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452      R5C5D.CLK to       R5C5D.Q0 SLICE_3 (from RCLK_c)
    ROUTE        23     1.929       R5C5D.Q0 to       R3C5D.A1 FS[13]
    CTOF_DEL    ---     0.495       R3C5D.A1 to       R3C5D.F1 SLICE_70
    ROUTE         3     1.021       R3C5D.F1 to       R3C5D.B0 N_348_2
    CTOF_DEL    ---     0.495       R3C5D.B0 to       R3C5D.F0 SLICE_70
    ROUTE         1     0.967       R3C5D.F0 to       R3C5B.A0 wb_dati_5_1_iv_0_a2_3_0[7]
    CTOF_DEL    ---     0.495       R3C5B.A0 to       R3C5B.F0 SLICE_108
    ROUTE         1     0.967       R3C5B.F0 to       R3C5A.A1 wb_dati_5_1_iv_0_0[7]
    CTOF_DEL    ---     0.495       R3C5A.A1 to       R3C5A.F1 SLICE_69
    ROUTE         1     1.004       R3C5A.F1 to       R3C5C.B1 wb_dati_5_1_iv_0_1[7]
    CTOF_DEL    ---     0.495       R3C5C.B1 to       R3C5C.F1 SLICE_56
    ROUTE         1     0.000       R3C5C.F1 to      R3C5C.DI1 wb_dati_5[7] (to RCLK_c)
                      --------
                        8.815   (33.2% logic, 66.8% route), 6 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_3:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R5C5D.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_56:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R3C5C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 7.040ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[13]  (from RCLK_c +)
       Destination:    FF         Data in        wb_adr[1]  (to RCLK_c +)

       Delay:               8.794ns  (27.7% logic, 72.3% route), 5 logic levels.

     Constraint Details:

          8.794ns physical path delay SLICE_3 to SLICE_48 meets
         16.000ns delay constraint less
          0.000ns skew and
          0.166ns DIN_SET requirement (totaling 15.834ns) by 7.040ns

     Physical Path Details:

          Data path SLICE_3 to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452      R5C5D.CLK to       R5C5D.Q0 SLICE_3 (from RCLK_c)
    ROUTE        23     3.158       R5C5D.Q0 to       R4C7C.A0 FS[13]
    CTOF_DEL    ---     0.495       R4C7C.A0 to       R4C7C.F0 SLICE_65
    ROUTE         1     0.436       R4C7C.F0 to       R4C7C.C1 wb_adr_5_i_i_a2_0[1]
    CTOF_DEL    ---     0.495       R4C7C.C1 to       R4C7C.F1 SLICE_65
    ROUTE         1     0.967       R4C7C.F1 to       R4C7A.A0 N_428_tz
    CTOF_DEL    ---     0.495       R4C7A.A0 to       R4C7A.F0 SLICE_61
    ROUTE         1     1.801       R4C7A.F0 to       R4C6C.A1 wb_adr_5_i_i_0[1]
    CTOF_DEL    ---     0.495       R4C6C.A1 to       R4C6C.F1 SLICE_48
    ROUTE         1     0.000       R4C6C.F1 to      R4C6C.DI1 N_282 (to RCLK_c)
                      --------
                        8.794   (27.7% logic, 72.3% route), 5 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_3:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R5C5D.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R4C6C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 7.108ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[12]  (from RCLK_c +)
       Destination:    FF         Data in        wb_dati[7]  (to RCLK_c +)

       Delay:               8.726ns  (33.5% logic, 66.5% route), 6 logic levels.

     Constraint Details:

          8.726ns physical path delay SLICE_4 to SLICE_56 meets
         16.000ns delay constraint less
          0.000ns skew and
          0.166ns DIN_SET requirement (totaling 15.834ns) by 7.108ns

     Physical Path Details:

          Data path SLICE_4 to SLICE_56:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452      R5C5C.CLK to       R5C5C.Q1 SLICE_4 (from RCLK_c)
    ROUTE        23     1.840       R5C5C.Q1 to       R3C5D.B1 FS[12]
    CTOF_DEL    ---     0.495       R3C5D.B1 to       R3C5D.F1 SLICE_70
    ROUTE         3     1.021       R3C5D.F1 to       R3C5D.B0 N_348_2
    CTOF_DEL    ---     0.495       R3C5D.B0 to       R3C5D.F0 SLICE_70
    ROUTE         1     0.967       R3C5D.F0 to       R3C5B.A0 wb_dati_5_1_iv_0_a2_3_0[7]
    CTOF_DEL    ---     0.495       R3C5B.A0 to       R3C5B.F0 SLICE_108
    ROUTE         1     0.967       R3C5B.F0 to       R3C5A.A1 wb_dati_5_1_iv_0_0[7]
    CTOF_DEL    ---     0.495       R3C5A.A1 to       R3C5A.F1 SLICE_69
    ROUTE         1     1.004       R3C5A.F1 to       R3C5C.B1 wb_dati_5_1_iv_0_1[7]
    CTOF_DEL    ---     0.495       R3C5C.B1 to       R3C5C.F1 SLICE_56
    ROUTE         1     0.000       R3C5C.F1 to      R3C5C.DI1 wb_dati_5[7] (to RCLK_c)
                      --------
                        8.726   (33.5% logic, 66.5% route), 6 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_4:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R5C5C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_56:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R3C5C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 7.132ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[10]  (from RCLK_c +)
       Destination:    FF         Data in        wb_adr[1]  (to RCLK_c +)

       Delay:               8.702ns  (33.6% logic, 66.4% route), 6 logic levels.

     Constraint Details:

          8.702ns physical path delay SLICE_5 to SLICE_48 meets
         16.000ns delay constraint less
          0.000ns skew and
          0.166ns DIN_SET requirement (totaling 15.834ns) by 7.132ns

     Physical Path Details:

          Data path SLICE_5 to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452      R5C5B.CLK to       R5C5B.Q1 SLICE_5 (from RCLK_c)
    ROUTE        16     1.440       R5C5B.Q1 to       R3C6D.A1 FS[10]
    CTOF_DEL    ---     0.495       R3C6D.A1 to       R3C6D.F1 SLICE_80
    ROUTE         7     1.131       R3C6D.F1 to       R4C7C.C0 N_125
    CTOF_DEL    ---     0.495       R4C7C.C0 to       R4C7C.F0 SLICE_65
    ROUTE         1     0.436       R4C7C.F0 to       R4C7C.C1 wb_adr_5_i_i_a2_0[1]
    CTOF_DEL    ---     0.495       R4C7C.C1 to       R4C7C.F1 SLICE_65
    ROUTE         1     0.967       R4C7C.F1 to       R4C7A.A0 N_428_tz
    CTOF_DEL    ---     0.495       R4C7A.A0 to       R4C7A.F0 SLICE_61
    ROUTE         1     1.801       R4C7A.F0 to       R4C6C.A1 wb_adr_5_i_i_0[1]
    CTOF_DEL    ---     0.495       R4C6C.A1 to       R4C6C.F1 SLICE_48
    ROUTE         1     0.000       R4C6C.F1 to      R4C6C.DI1 N_282 (to RCLK_c)
                      --------
                        8.702   (33.6% logic, 66.4% route), 6 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_5:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R5C5B.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R4C6C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 7.246ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[11]  (from RCLK_c +)
       Destination:    FF         Data in        wb_adr[1]  (to RCLK_c +)

       Delay:               8.588ns  (28.3% logic, 71.7% route), 5 logic levels.

     Constraint Details:

          8.588ns physical path delay SLICE_4 to SLICE_48 meets
         16.000ns delay constraint less
          0.000ns skew and
          0.166ns DIN_SET requirement (totaling 15.834ns) by 7.246ns

     Physical Path Details:

          Data path SLICE_4 to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452      R5C5C.CLK to       R5C5C.Q0 SLICE_4 (from RCLK_c)
    ROUTE        21     1.215       R5C5C.Q0 to       R2C7A.D1 FS[11]
    CTOF_DEL    ---     0.495       R2C7A.D1 to       R2C7A.F1 SLICE_101
    ROUTE         4     2.173       R2C7A.F1 to       R4C7C.B1 N_142
    CTOF_DEL    ---     0.495       R4C7C.B1 to       R4C7C.F1 SLICE_65
    ROUTE         1     0.967       R4C7C.F1 to       R4C7A.A0 N_428_tz
    CTOF_DEL    ---     0.495       R4C7A.A0 to       R4C7A.F0 SLICE_61
    ROUTE         1     1.801       R4C7A.F0 to       R4C6C.A1 wb_adr_5_i_i_0[1]
    CTOF_DEL    ---     0.495       R4C6C.A1 to       R4C6C.F1 SLICE_48
    ROUTE         1     0.000       R4C6C.F1 to      R4C6C.DI1 N_282 (to RCLK_c)
                      --------
                        8.588   (28.3% logic, 71.7% route), 5 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_4:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R5C5C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R4C6C.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 7.249ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              InitReady  (from RCLK_c +)
       Destination:    FF         Data in        nRWE_0io  (to RCLK_c +)

       Delay:               8.771ns  (27.7% logic, 72.3% route), 5 logic levels.

     Constraint Details:

          8.771ns physical path delay SLICE_30 to nRWE_MGIOL meets
         16.000ns delay constraint less
         -0.173ns skew and
          0.153ns DO_SET requirement (totaling 16.020ns) by 7.249ns

     Physical Path Details:

          Data path SLICE_30 to nRWE_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.452      R4C8D.CLK to       R4C8D.Q0 SLICE_30 (from RCLK_c)
    ROUTE        31     1.714       R4C8D.Q0 to      R7C15A.D1 InitReady
    CTOF_DEL    ---     0.495      R7C15A.D1 to      R7C15A.F1 SLICE_62
    ROUTE         6     1.032      R7C15A.F1 to      R7C16A.B1 N_43
    CTOF_DEL    ---     0.495      R7C16A.B1 to      R7C16A.F1 SLICE_78
    ROUTE         2     0.775      R7C16A.F1 to      R7C14B.C1 IS_0_sqmuxa_0_o2
    CTOF_DEL    ---     0.495      R7C14B.C1 to      R7C14B.F1 SLICE_68
    ROUTE         1     1.023      R7C14B.F1 to      R8C14C.B1 nRWE_0io_RNO_0
    CTOF_DEL    ---     0.495      R8C14C.B1 to      R8C14C.F1 SLICE_92
    ROUTE         1     1.795      R8C14C.F1 to  IOL_B20D.OPOS N_37_i (to RCLK_c)
                      --------
                        8.771   (27.7% logic, 72.3% route), 5 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_30:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.264       63.PADDI to      R4C8D.CLK RCLK_c
                      --------
                        2.264   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to nRWE_MGIOL:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     2.437       63.PADDI to   IOL_B20D.CLK RCLK_c
                      --------
                        2.437   (0.0% logic, 100.0% route), 0 logic levels.

    Report:   98.020MHz is the maximum frequency for this preference.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference                              |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   50.206 MHz|   6
                                            |             |             |
    FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0
                                            |             |             |
    FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0
                                            |             |             |
    FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|   98.020 MHz|   5
                                            |             |             |
    ----------------------------------------------------------------------------

    All preferences were met.

    Clock Domains Analysis
    ------------------------

    Found 4 clocks:

    Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
       No transfer within this clock domain is found

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
       No transfer within this clock domain is found

    Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 48
       Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;

       Data transfers from:
       Clock Domain: nCRAS_c   Source: nCRAS.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

       Clock Domain: PHI2_c   Source: PHI2.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 21
       Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Timing summary (Setup):
    ---------------

    Timing errors: 0  Score: 0
    Cumulative negative slack: 0

    Constraints cover 1015 paths, 4 nets, and 725 connections (73.01% coverage)

    --------------------------------------------------------------------------------
    Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
    Thu Oct 19 23:51:11 2023

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
    Design file:     ram2gs_lcmxo2_1200hc_impl1.ncd
    Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
    Device,speed:    LCMXO2-1200HC,m
    Report level:    verbose report, limited to 10 items per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)            147 items scored, 0 timing errors detected.

    FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.

    FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)            0 items scored, 0 timing errors detected.

    FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)            868 items scored, 0 timing errors detected.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
                147 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              C1Submitted  (from PHI2_c -)
       Destination:    FF         Data in        C1Submitted  (to PHI2_c -)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_11 to SLICE_11 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_11 to SLICE_11:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R5C12A.CLK to      R5C12A.Q0 SLICE_11 (from PHI2_c)
    ROUTE         2     0.132      R5C12A.Q0 to      R5C12A.A0 C1Submitted
    CTOF_DEL    ---     0.101      R5C12A.A0 to      R5C12A.F0 SLICE_11
    ROUTE         1     0.000      R5C12A.F0 to     R5C12A.DI0 C1Submitted_RNO (to PHI2_c)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to SLICE_11:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R5C12A.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_11:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R5C12A.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              CmdUFMShift  (from PHI2_c -)
       Destination:    FF         Data in        CmdUFMShift  (to PHI2_c -)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_20 to SLICE_20 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_20 to SLICE_20:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R4C10B.CLK to      R4C10B.Q0 SLICE_20 (from PHI2_c)
    ROUTE         2     0.132      R4C10B.Q0 to      R4C10B.A0 CmdUFMShift
    CTOF_DEL    ---     0.101      R4C10B.A0 to      R4C10B.F0 SLICE_20
    ROUTE         1     0.000      R4C10B.F0 to     R4C10B.DI0 CmdUFMShift_3 (to PHI2_c)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to SLICE_20:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R4C10B.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_20:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R4C10B.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.382ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              ADSubmitted  (from PHI2_c -)
       Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)

       Delay:               0.369ns  (63.4% logic, 36.6% route), 2 logic levels.

     Constraint Details:

          0.369ns physical path delay SLICE_10 to SLICE_10 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.382ns

     Physical Path Details:

          Data path SLICE_10 to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R5C12C.CLK to      R5C12C.Q0 SLICE_10 (from PHI2_c)
    ROUTE         2     0.135      R5C12C.Q0 to      R5C12C.D0 ADSubmitted
    CTOF_DEL    ---     0.101      R5C12C.D0 to      R5C12C.F0 SLICE_10
    ROUTE         1     0.000      R5C12C.F0 to     R5C12C.DI0 ADSubmitted_r_0 (to PHI2_c)
                      --------
                        0.369   (63.4% logic, 36.6% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R5C12C.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_10:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R5C12C.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.387ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              CmdEnable  (from PHI2_c -)
       Destination:    FF         Data in        CmdEnable  (to PHI2_c -)

       Delay:               0.374ns  (62.6% logic, 37.4% route), 2 logic levels.

     Constraint Details:

          0.374ns physical path delay SLICE_17 to SLICE_17 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.387ns

     Physical Path Details:

          Data path SLICE_17 to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R5C11D.CLK to      R5C11D.Q0 SLICE_17 (from PHI2_c)
    ROUTE         4     0.140      R5C11D.Q0 to      R5C11D.D0 CmdEnable
    CTOF_DEL    ---     0.101      R5C11D.D0 to      R5C11D.F0 SLICE_17
    ROUTE         1     0.000      R5C11D.F0 to     R5C11D.DI0 CmdEnable_s (to PHI2_c)
                      --------
                        0.374   (62.6% logic, 37.4% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R5C11D.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R5C11D.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.616ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              CmdUFMWrite  (from PHI2_c -)
       Destination:    FF         Data in        CmdUFMWrite  (to PHI2_c -)

       Delay:               0.603ns  (55.6% logic, 44.4% route), 3 logic levels.

     Constraint Details:

          0.603ns physical path delay SLICE_21 to SLICE_21 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.616ns

     Physical Path Details:

          Data path SLICE_21 to SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R4C10D.CLK to      R4C10D.Q0 SLICE_21 (from PHI2_c)
    ROUTE         2     0.212      R4C10D.Q0 to      R4C10D.A1 CmdUFMWrite
    CTOF_DEL    ---     0.101      R4C10D.A1 to      R4C10D.F1 SLICE_21
    ROUTE         1     0.056      R4C10D.F1 to      R4C10D.C0 N_279
    CTOF_DEL    ---     0.101      R4C10D.C0 to      R4C10D.F0 SLICE_21
    ROUTE         1     0.000      R4C10D.F0 to     R4C10D.DI0 CmdUFMWrite_3 (to PHI2_c)
                      --------
                        0.603   (55.6% logic, 44.4% route), 3 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R4C10D.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R4C10D.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.616ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              Cmdn8MEGEN  (from PHI2_c -)
       Destination:    FF         Data in        Cmdn8MEGEN  (to PHI2_c -)

       Delay:               0.603ns  (55.6% logic, 44.4% route), 3 logic levels.

     Constraint Details:

          0.603ns physical path delay SLICE_24 to SLICE_24 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.616ns

     Physical Path Details:

          Data path SLICE_24 to SLICE_24:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R3C10C.CLK to      R3C10C.Q0 SLICE_24 (from PHI2_c)
    ROUTE         2     0.212      R3C10C.Q0 to      R3C10C.A1 Cmdn8MEGEN
    CTOF_DEL    ---     0.101      R3C10C.A1 to      R3C10C.F1 SLICE_24
    ROUTE         1     0.056      R3C10C.F1 to      R3C10C.C0 Cmdn8MEGEN_4_u_i_0
    CTOF_DEL    ---     0.101      R3C10C.C0 to      R3C10C.F0 SLICE_24
    ROUTE         1     0.000      R3C10C.F0 to     R3C10C.DI0 N_285_i (to PHI2_c)
                      --------
                        0.603   (55.6% logic, 44.4% route), 3 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to SLICE_24:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R3C10C.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_24:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R3C10C.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.616ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              XOR8MEG  (from PHI2_c -)
       Destination:    FF         Data in        XOR8MEG  (to PHI2_c -)

       Delay:               0.603ns  (55.6% logic, 44.4% route), 3 logic levels.

     Constraint Details:

          0.603ns physical path delay SLICE_45 to SLICE_45 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.616ns

     Physical Path Details:

          Data path SLICE_45 to SLICE_45:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R5C10D.CLK to      R5C10D.Q0 SLICE_45 (from PHI2_c)
    ROUTE         2     0.212      R5C10D.Q0 to      R5C10D.A1 XOR8MEG
    CTOF_DEL    ---     0.101      R5C10D.A1 to      R5C10D.F1 SLICE_45
    ROUTE         1     0.056      R5C10D.F1 to      R5C10D.C0 N_274
    CTOF_DEL    ---     0.101      R5C10D.C0 to      R5C10D.F0 SLICE_45
    ROUTE         1     0.000      R5C10D.F0 to     R5C10D.DI0 XOR8MEG_3 (to PHI2_c)
                      --------
                        0.603   (55.6% logic, 44.4% route), 3 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to SLICE_45:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R5C10D.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_45:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R5C10D.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.628ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              CmdLEDEN  (from PHI2_c -)
       Destination:    FF         Data in        CmdLEDEN  (to PHI2_c -)

       Delay:               0.615ns  (54.5% logic, 45.5% route), 3 logic levels.

     Constraint Details:

          0.615ns physical path delay SLICE_18 to SLICE_18 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.628ns

     Physical Path Details:

          Data path SLICE_18 to SLICE_18:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R3C10B.CLK to      R3C10B.Q0 SLICE_18 (from PHI2_c)
    ROUTE         2     0.224      R3C10B.Q0 to      R3C10B.B1 CmdLEDEN
    CTOF_DEL    ---     0.101      R3C10B.B1 to      R3C10B.F1 SLICE_18
    ROUTE         1     0.056      R3C10B.F1 to      R3C10B.C0 CmdLEDEN_4_u_i_0
    CTOF_DEL    ---     0.101      R3C10B.C0 to      R3C10B.F0 SLICE_18
    ROUTE         1     0.000      R3C10B.F0 to     R3C10B.DI0 N_284_i (to PHI2_c)
                      --------
                        0.615   (54.5% logic, 45.5% route), 3 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to SLICE_18:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R3C10B.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_18:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R3C10B.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.632ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              CmdEnable  (from PHI2_c -)
       Destination:    FF         Data in        CmdValid_fast  (to PHI2_c -)

       Delay:               0.619ns  (54.1% logic, 45.9% route), 3 logic levels.

     Constraint Details:

          0.619ns physical path delay SLICE_17 to SLICE_23 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.632ns

     Physical Path Details:

          Data path SLICE_17 to SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R5C11D.CLK to      R5C11D.Q0 SLICE_17 (from PHI2_c)
    ROUTE         4     0.226      R5C11D.Q0 to      R4C10C.C1 CmdEnable
    CTOF_DEL    ---     0.101      R4C10C.C1 to      R4C10C.F1 SLICE_23
    ROUTE         2     0.058      R4C10C.F1 to      R4C10C.C0 XOR8MEG18_i
    CTOF_DEL    ---     0.101      R4C10C.C0 to      R4C10C.F0 SLICE_23
    ROUTE         1     0.000      R4C10C.F0 to     R4C10C.DI0 N_36_fast (to PHI2_c)
                      --------
                        0.619   (54.1% logic, 45.9% route), 3 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R5C11D.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R4C10C.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.661ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              CmdEnable  (from PHI2_c -)
       Destination:    FF         Data in        XOR8MEG  (to PHI2_c -)

       Delay:               0.633ns  (37.0% logic, 63.0% route), 2 logic levels.

     Constraint Details:

          0.633ns physical path delay SLICE_17 to SLICE_45 meets
         -0.028ns CE_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.028ns) by 0.661ns

     Physical Path Details:

          Data path SLICE_17 to SLICE_45:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R5C11D.CLK to      R5C11D.Q0 SLICE_17 (from PHI2_c)
    ROUTE         4     0.140      R5C11D.Q0 to      R5C11C.D1 CmdEnable
    CTOF_DEL    ---     0.101      R5C11C.D1 to      R5C11C.F1 SLICE_106
    ROUTE         5     0.259      R5C11C.F1 to      R5C10D.CE XOR8MEG18 (to PHI2_c)
                      --------
                        0.633   (37.0% logic, 63.0% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path PHI2 to SLICE_17:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R5C11D.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path PHI2 to SLICE_45:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        21     1.423        8.PADDI to     R5C10D.CLK PHI2_c
                      --------
                        1.423   (0.0% logic, 100.0% route), 0 logic levels.

    ================================================================================
    Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
                868 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.304ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              CASr  (from RCLK_c +)
       Destination:    FF         Data in        CASr2  (to RCLK_c +)

       Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.

     Constraint Details:

          0.285ns physical path delay SLICE_12 to SLICE_12 meets
         -0.019ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.019ns) by 0.304ns

     Physical Path Details:

          Data path SLICE_12 to SLICE_12:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R5C12B.CLK to      R5C12B.Q0 SLICE_12 (from RCLK_c)
    ROUTE         1     0.152      R5C12B.Q0 to      R5C12B.M1 CASr (to RCLK_c)
                      --------
                        0.285   (46.7% logic, 53.3% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_12:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to     R5C12B.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_12:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to     R5C12B.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.306ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              CASr2  (from RCLK_c +)
       Destination:    FF         Data in        CASr3  (to RCLK_c +)

       Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.

     Constraint Details:

          0.287ns physical path delay SLICE_12 to SLICE_76 meets
         -0.019ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.019ns) by 0.306ns

     Physical Path Details:

          Data path SLICE_12 to SLICE_76:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R5C12B.CLK to      R5C12B.Q1 SLICE_12 (from RCLK_c)
    ROUTE         4     0.154      R5C12B.Q1 to      R5C12D.M0 CASr2 (to RCLK_c)
                      --------
                        0.287   (46.3% logic, 53.7% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_12:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to     R5C12B.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_76:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to     R5C12D.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.306ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              RASr  (from RCLK_c +)
       Destination:    FF         Data in        RASr2  (to RCLK_c +)

       Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.

     Constraint Details:

          0.287ns physical path delay SLICE_33 to SLICE_33 meets
         -0.019ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.019ns) by 0.306ns

     Physical Path Details:

          Data path SLICE_33 to SLICE_33:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133     R7C10D.CLK to      R7C10D.Q0 SLICE_33 (from RCLK_c)
    ROUTE         2     0.154      R7C10D.Q0 to      R7C10D.M1 RASr (to RCLK_c)
                      --------
                        0.287   (46.3% logic, 53.7% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_33:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to     R7C10D.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_33:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to     R7C10D.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.311ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              PHI2r2  (from RCLK_c +)
       Destination:    FF         Data in        PHI2r3  (to RCLK_c +)

       Delay:               0.292ns  (45.5% logic, 54.5% route), 1 logic levels.

     Constraint Details:

          0.292ns physical path delay SLICE_32 to SLICE_32 meets
         -0.019ns M_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.019ns) by 0.311ns

     Physical Path Details:

          Data path SLICE_32 to SLICE_32:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133      R3C9D.CLK to       R3C9D.Q0 SLICE_32 (from RCLK_c)
    ROUTE         5     0.159       R3C9D.Q0 to       R3C9D.M1 PHI2r2 (to RCLK_c)
                      --------
                        0.292   (45.5% logic, 54.5% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_32:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R3C9D.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_32:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R3C9D.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.347ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              wb_dati[3]  (from RCLK_c +)
       Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to RCLK_c +)

       Delay:               0.306ns  (43.5% logic, 56.5% route), 1 logic levels.

     Constraint Details:

          0.306ns physical path delay SLICE_54 to ufmefb/EFBInst_0 meets
         -0.095ns WBDATI_HLD and
          0.000ns delay constraint less
         -0.054ns skew requirement (totaling -0.041ns) by 0.347ns

     Physical Path Details:

          Data path SLICE_54 to ufmefb/EFBInst_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133      R2C6D.CLK to       R2C6D.Q1 SLICE_54 (from RCLK_c)
    ROUTE         2     0.173       R2C6D.Q1 to    EFB.WBDATI3 wb_dati[3] (to RCLK_c)
                      --------
                        0.306   (43.5% logic, 56.5% route), 1 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_54:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R2C6D.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to ufmefb/EFBInst_0:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.842       63.PADDI to     EFB.WBCLKI RCLK_c
                      --------
                        0.842   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[0]  (from RCLK_c +)
       Destination:    FF         Data in        FS[0]  (to RCLK_c +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_0 to SLICE_0 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_0 to SLICE_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133      R5C4A.CLK to       R5C4A.Q1 SLICE_0 (from RCLK_c)
    ROUTE         3     0.132       R5C4A.Q1 to       R5C4A.A1 FS[0]
    CTOF_DEL    ---     0.101       R5C4A.A1 to       R5C4A.F1 SLICE_0
    ROUTE         1     0.000       R5C4A.F1 to      R5C4A.DI1 FS_s[0] (to RCLK_c)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_0:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R5C4A.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_0:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R5C4A.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[17]  (from RCLK_c +)
       Destination:    FF         Data in        FS[17]  (to RCLK_c +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_1 to SLICE_1 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_1 to SLICE_1:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133      R5C6B.CLK to       R5C6B.Q0 SLICE_1 (from RCLK_c)
    ROUTE         5     0.132       R5C6B.Q0 to       R5C6B.A0 FS[17]
    CTOF_DEL    ---     0.101       R5C6B.A0 to       R5C6B.F0 SLICE_1
    ROUTE         1     0.000       R5C6B.F0 to      R5C6B.DI0 FS_s[17] (to RCLK_c)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_1:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R5C6B.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_1:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R5C6B.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[15]  (from RCLK_c +)
       Destination:    FF         Data in        FS[15]  (to RCLK_c +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_2 to SLICE_2 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_2 to SLICE_2:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133      R5C6A.CLK to       R5C6A.Q0 SLICE_2 (from RCLK_c)
    ROUTE         4     0.132       R5C6A.Q0 to       R5C6A.A0 FS[15]
    CTOF_DEL    ---     0.101       R5C6A.A0 to       R5C6A.F0 SLICE_2
    ROUTE         1     0.000       R5C6A.F0 to      R5C6A.DI0 FS_s[15] (to RCLK_c)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_2:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R5C6A.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_2:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R5C6A.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[16]  (from RCLK_c +)
       Destination:    FF         Data in        FS[16]  (to RCLK_c +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_2 to SLICE_2 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_2 to SLICE_2:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133      R5C6A.CLK to       R5C6A.Q1 SLICE_2 (from RCLK_c)
    ROUTE         5     0.132       R5C6A.Q1 to       R5C6A.A1 FS[16]
    CTOF_DEL    ---     0.101       R5C6A.A1 to       R5C6A.F1 SLICE_2
    ROUTE         1     0.000       R5C6A.F1 to      R5C6A.DI1 FS_s[16] (to RCLK_c)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_2:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R5C6A.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_2:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R5C6A.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              FS[12]  (from RCLK_c +)
       Destination:    FF         Data in        FS[12]  (to RCLK_c +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay SLICE_4 to SLICE_4 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path SLICE_4 to SLICE_4:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133      R5C5C.CLK to       R5C5C.Q1 SLICE_4 (from RCLK_c)
    ROUTE        23     0.132       R5C5C.Q1 to       R5C5C.A1 FS[12]
    CTOF_DEL    ---     0.101       R5C5C.A1 to       R5C5C.F1 SLICE_4
    ROUTE         1     0.000       R5C5C.F1 to      R5C5C.DI1 FS_s[12] (to RCLK_c)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path RCLK to SLICE_4:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R5C5C.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path RCLK to SLICE_4:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        48     0.788       63.PADDI to      R5C5C.CLK RCLK_c
                      --------
                        0.788   (0.0% logic, 100.0% route), 0 logic levels.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference(MIN Delays)                  |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2
                                            |             |             |
    FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0
                                            |             |             |
    FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0
                                            |             |             |
    FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1
                                            |             |             |
    ----------------------------------------------------------------------------

    All preferences were met.

    Clock Domains Analysis
    ------------------------

    Found 4 clocks:

    Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 12
       No transfer within this clock domain is found

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
       No transfer within this clock domain is found

    Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 48
       Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;

       Data transfers from:
       Clock Domain: nCRAS_c   Source: nCRAS.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

       Clock Domain: PHI2_c   Source: PHI2.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 21
       Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;

       Data transfers from:
       Clock Domain: RCLK_c   Source: RCLK.PAD
          Not reported because source and destination domains are unrelated.
          To report these transfers please refer to preference CLKSKEWDIFF to define
          external clock skew between clock ports.

    Timing summary (Hold):
    ---------------

    Timing errors: 0  Score: 0
    Cumulative negative slack: 0

    Constraints cover 1015 paths, 4 nets, and 725 connections (73.01% coverage)

    Timing summary (Setup and Hold):
    ---------------

    Timing errors: 0 (setup), 0 (hold)
    Score: 0 (setup), 0 (hold)
    Cumulative negative slack: 0 (0+0)
    --------------------------------------------------------------------------------

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