
Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-640HC
Package:     TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.39.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Sep 21 05:39:45 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed:    LCMXO2-640HC,4
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
            147 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Bank_0io[0]  (from PHI2_c +)
   Destination:    FF         Data in        CmdEnable  (to PHI2_c -)

   Delay:               9.223ns  (33.1% logic, 66.9% route), 6 logic levels.

 Constraint Details:

      9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets
    172.414ns delay constraint less
      0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns

 Physical Path Details:

      Data path Din[0]_MGIOL to SLICE_17:

   Name    Fanout   Delay (ns)          Site               Resource
C2INP_DEL   ---     0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
ROUTE         1   e 1.234 *n[0]_MGIOL.IN to    SLICE_93.A0 Bank[0]
CTOF_DEL    ---     0.495    SLICE_93.A0 to    SLICE_93.F0 SLICE_93
ROUTE         1   e 1.234    SLICE_93.F0 to    SLICE_84.C0 un1_CmdEnable20_0_0_o3_10
CTOF_DEL    ---     0.495    SLICE_84.C0 to    SLICE_84.F0 SLICE_84
ROUTE         6   e 1.234    SLICE_84.F0 to    SLICE_11.C1 un1_CmdEnable20_0_0_o3
CTOF_DEL    ---     0.495    SLICE_11.C1 to    SLICE_11.F1 SLICE_11
ROUTE         3   e 1.234    SLICE_11.F1 to    SLICE_33.B0 CmdEnable16
CTOF_DEL    ---     0.495    SLICE_33.B0 to    SLICE_33.F0 SLICE_33
ROUTE         1   e 1.234    SLICE_33.F0 to    SLICE_17.D0 CmdEnable_0_sqmuxa
CTOF_DEL    ---     0.495    SLICE_17.D0 to    SLICE_17.F0 SLICE_17
ROUTE         1   e 0.001    SLICE_17.F0 to   SLICE_17.DI0 CmdEnable_s (to PHI2_c)
                  --------
                    9.223   (33.1% logic, 66.9% route), 6 logic levels.

Report:   53.254MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 338.168ns
         The internal maximum frequency of the following component is 150.150 MHz

 Logical Details:  Cell type  Pin name       Component name

   Destination:    PIO        PAD            nCCAS

   Delay:               6.660ns -- based on Minimum Pulse Width

Report:  150.150MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 338.168ns
         The internal maximum frequency of the following component is 150.150 MHz

 Logical Details:  Cell type  Pin name       Component name

   Destination:    PIO        PAD            nCRAS

   Delay:               6.660ns -- based on Minimum Pulse Width

Report:  150.150MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
            878 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 6.049ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              IS[1]  (from RCLK_c +)
   Destination:    FF         Data in        nRCAS_0io  (to RCLK_c +)

   Delay:               9.798ns  (34.9% logic, 65.1% route), 7 logic levels.

 Constraint Details:

      9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets
     16.000ns delay constraint less
      0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns

 Physical Path Details:

      Data path SLICE_27 to nRCAS_MGIOL:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452   SLICE_27.CLK to    SLICE_27.Q0 SLICE_27 (from RCLK_c)
ROUTE         7   e 1.234    SLICE_27.Q0 to    SLICE_74.A1 IS[1]
CTOF_DEL    ---     0.495    SLICE_74.A1 to    SLICE_74.F1 SLICE_74
ROUTE         2   e 0.480    SLICE_74.F1 to    SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0
CTOF_DEL    ---     0.495    SLICE_74.B0 to    SLICE_74.F0 SLICE_74
ROUTE         2   e 1.234    SLICE_74.F0 to    SLICE_61.B1 N_408
CTOF_DEL    ---     0.495    SLICE_61.B1 to    SLICE_61.F1 SLICE_61
ROUTE         1   e 0.480    SLICE_61.F1 to    SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0
CTOF_DEL    ---     0.495    SLICE_61.A0 to    SLICE_61.F0 SLICE_61
ROUTE         1   e 1.234    SLICE_61.F0 to    SLICE_94.D0 nRCAS_r_i_0_o2_0_0
CTOF_DEL    ---     0.495    SLICE_94.D0 to    SLICE_94.F0 SLICE_94
ROUTE         1   e 0.480    SLICE_94.F0 to    SLICE_94.A1 N_248_i_1
CTOF_DEL    ---     0.495    SLICE_94.A1 to    SLICE_94.F1 SLICE_94
ROUTE         1   e 1.234    SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c)
                  --------
                    9.798   (34.9% logic, 65.1% route), 7 logic levels.

Report:  100.492MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY PORT "PHI2" 2.900000 MHz ;    |    2.900 MHz|   53.254 MHz|   6  
                                        |             |             |
FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
                                        |             |             |
FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |    2.900 MHz|  150.150 MHz|   0  
                                        |             |             |
FREQUENCY PORT "RCLK" 62.500000 MHz ;   |   62.500 MHz|  100.492 MHz|   7  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 4 clocks:

Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 11
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: RCLK_c   Source: RCLK.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.

Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
   No transfer within this clock domain is found

Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 47
   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;

   Data transfers from:
   Clock Domain: nCRAS_c   Source: nCRAS.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.

   Clock Domain: PHI2_c   Source: PHI2.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.

Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 21
   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;

   Data transfers from:
   Clock Domain: RCLK_c   Source: RCLK.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.


Timing summary (Setup):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)

--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Thu Sep 21 05:39:45 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed:    LCMXO2-640HC,M
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
            147 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.447ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              ADSubmitted  (from PHI2_c -)
   Destination:    FF         Data in        ADSubmitted  (to PHI2_c -)

   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.

 Constraint Details:

      0.434ns physical path delay SLICE_10 to SLICE_10 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns

 Physical Path Details:

      Data path SLICE_10 to SLICE_10:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133   SLICE_10.CLK to    SLICE_10.Q0 SLICE_10 (from PHI2_c)
ROUTE         2   e 0.199    SLICE_10.Q0 to    SLICE_10.A0 ADSubmitted
CTOF_DEL    ---     0.101    SLICE_10.A0 to    SLICE_10.F0 SLICE_10
ROUTE         1   e 0.001    SLICE_10.F0 to   SLICE_10.DI0 ADSubmitted_r_0_0 (to PHI2_c)
                  --------
                    0.434   (53.9% logic, 46.1% route), 2 logic levels.


================================================================================
Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
            878 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.351ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              CASr  (from RCLK_c +)
   Destination:    FF         Data in        CASr2  (to RCLK_c +)

   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.

 Constraint Details:

      0.332ns physical path delay SLICE_12 to SLICE_12 meets
     -0.019ns M_HLD and
      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns

 Physical Path Details:

      Data path SLICE_12 to SLICE_12:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133   SLICE_12.CLK to    SLICE_12.Q0 SLICE_12 (from RCLK_c)
ROUTE         1   e 0.199    SLICE_12.Q0 to    SLICE_12.M1 CASr (to RCLK_c)
                  --------
                    0.332   (40.1% logic, 59.9% route), 1 logic levels.

Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY PORT "PHI2" 2.900000 MHz ;    |            -|            -|   2  
                                        |             |             |
FREQUENCY PORT "nCCAS" 2.900000 MHz ;   |            -|            -|   0  
                                        |             |             |
FREQUENCY PORT "nCRAS" 2.900000 MHz ;   |            -|            -|   0  
                                        |             |             |
FREQUENCY PORT "RCLK" 62.500000 MHz ;   |            -|            -|   1  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 4 clocks:

Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 11
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: RCLK_c   Source: RCLK.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.

Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 10
   No transfer within this clock domain is found

Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 47
   Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;

   Data transfers from:
   Clock Domain: nCRAS_c   Source: nCRAS.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.

   Clock Domain: PHI2_c   Source: PHI2.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.

Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 21
   Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;

   Data transfers from:
   Clock Domain: RCLK_c   Source: RCLK.PAD
      Not reported because source and destination domains are unrelated.
      To report these transfers please refer to preference CLKSKEWDIFF to define
      external clock skew between clock ports.


Timing summary (Hold):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------

