Synthesis Report
#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
#install: C:\lscc\diamond\3.12\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEPC

# Tue Aug 15 23:12:41 2023

#Implementation: impl1


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2

Hostname: ZANEPC

Implementation : impl1
Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2

Hostname: ZANEPC

Implementation : impl1
Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module RAM2GS
@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
Running optimization stage 1 on RAM2GS .......
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
Running optimization stage 2 on RAM2GS .......
Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug 15 23:12:41 2023

###########################################################]
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2

Hostname: ZANEPC

Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug 15 23:12:41 2023

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug 15 23:12:41 2023

###########################################################]
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2

Hostname: ZANEPC

Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

@N|Running in 64-bit mode
File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug 15 23:12:42 2023

###########################################################]
# Tue Aug 15 23:12:42 2023


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2

Hostname: ZANEPC

Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)


Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)

Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt 
See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt"
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N: FX493 |Applying initial value "0" on instance InitReady.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@N: FX493 |Applying initial value "0" on instance Ready.
@N: FX493 |Applying initial value "0" on instance RCKE.
@N: FX493 |Applying initial value "1" on instance nRCAS.
@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
@N: FX493 |Applying initial value "1" on instance nRCS.
@N: FX493 |Applying initial value "0" on instance LEDEN.
@N: FX493 |Applying initial value "0" on instance n8MEGEN.
@N: FX493 |Applying initial value "1" on instance nRRAS.
@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
@N: FX493 |Applying initial value "0" on instance C1Submitted.
@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
@N: FX493 |Applying initial value "0" on instance ADSubmitted.
@N: FX493 |Applying initial value "0" on instance XOR8MEG.
@N: FX493 |Applying initial value "1" on instance nUFMCS.
@N: FX493 |Applying initial value "0" on instance UFMSDI.
@N: FX493 |Applying initial value "0" on instance UFMCLK.
@N: FX493 |Applying initial value "0" on instance CmdEnable.
@N: FX493 |Applying initial value "1" on instance nRWE.

Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)

@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS 

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)



Clock Summary
******************

          Start     Requested     Requested     Clock        Clock                Clock
Level     Clock     Frequency     Period        Type         Group                Load 
---------------------------------------------------------------------------------------
0 -       RCLK      62.5 MHz      16.000        declared     default_clkgroup     48   
                                                                                       
0 -       PHI2      2.9 MHz       350.000       declared     default_clkgroup     19   
                                                                                       
0 -       nCRAS     2.9 MHz       350.000       declared     default_clkgroup     14   
                                                                                       
0 -       nCCAS     2.9 MHz       350.000       declared     default_clkgroup     8    
=======================================================================================



Clock Load Summary
***********************

          Clock     Source          Clock Pin       Non-clock Pin     Non-clock Pin     
Clock     Load      Pin             Seq Example     Seq Example       Comb Example      
----------------------------------------------------------------------------------------
RCLK      48        RCLK(port)      CASr2.C         -                 -                 
                                                                                        
PHI2      19        PHI2(port)      Bank[7:0].C     PHI2r.D[0]        un1_PHI2.I[0](inv)
                                                                                        
nCRAS     14        nCRAS(port)     CBR.C           RASr.D[0]         RASr_2.I[0](inv)  
                                                                                        
nCCAS     8         nCCAS(port)     WRD[7:0].C      CASr.D[0]         CASr_2.I[0](inv)  
========================================================================================

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0
For details review file gcc_ICG_report.rpt


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       RCLK                port                   48         nRWE           
@KP:ckid0_1       PHI2                port                   19         RA11           
@KP:ckid0_2       nCCAS               port                   8          WRD[7:0]       
@KP:ckid0_3       nCRAS               port                   14         RowA[9:0]      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)


Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 174MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Aug 15 23:12:44 2023

###########################################################]
# Tue Aug 15 23:12:44 2023


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2

Hostname: ZANEPC

Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)

@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0] 
@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0] 
@N: FX493 |Applying initial value "0" on instance IS[0].
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@N: FX493 |Applying initial value "0" on instance IS[1].
@N: FX493 |Applying initial value "0" on instance IS[2].
@N: FX493 |Applying initial value "0" on instance IS[3].

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 173MB peak: 173MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 174MB)


Available hyper_sources - for debug and ip models
	None Found


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 175MB peak: 175MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -2.34ns		 128 /        89
   2		0h:00m:01s		    -2.34ns		 140 /        89
   3		0h:00m:01s		    -2.34ns		 140 /        89
@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication

   4		0h:00m:01s		    -2.04ns		 140 /        90


   5		0h:00m:01s		    -2.04ns		 141 /        90
   6		0h:00m:01s		    -2.04ns		 141 /        90
   7		0h:00m:01s		    -2.04ns		 141 /        90
   8		0h:00m:01s		    -2.04ns		 141 /        90
   9		0h:00m:01s		    -2.04ns		 141 /        90

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 178MB)

Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)

Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)


Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB)


Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 184MB)

@N: MT615 |Found clock RCLK with period 16.00ns 
@N: MT615 |Found clock PHI2 with period 350.00ns 
@N: MT615 |Found clock nCRAS with period 350.00ns 
@N: MT615 |Found clock nCCAS with period 350.00ns 


##### START OF TIMING REPORT #####[
# Timing report written on Tue Aug 15 23:12:47 2023
#


Top view:               RAM2GS
Requested Frequency:    2.9 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
                       
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -2.389

                   Requested     Estimated     Requested     Estimated                Clock        Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
-------------------------------------------------------------------------------------------------------------------
PHI2               2.9 MHz       0.8 MHz       350.000       1186.150      -2.389     declared     default_clkgroup
RCLK               62.5 MHz      18.4 MHz      16.000        54.224        -0.784     declared     default_clkgroup
nCCAS              2.9 MHz       NA            350.000       NA            NA         declared     default_clkgroup
nCRAS              2.9 MHz       1.0 MHz       350.000       987.210       -1.821     declared     default_clkgroup
===================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform


@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  
@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  
@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  
@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  



Clock Relationships
*******************

Clocks            |    rise  to  rise   |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
--------------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack  |  constraint  slack    |  constraint  slack    |  constraint  slack  
--------------------------------------------------------------------------------------------------------------
RCLK      RCLK    |  16.000      8.400  |  No paths    -        |  No paths    -        |  No paths    -      
RCLK      PHI2    |  2.000       0.216  |  No paths    -        |  1.000       -0.636   |  No paths    -      
RCLK      nCRAS   |  No paths    -      |  No paths    -        |  1.000       -0.784   |  No paths    -      
PHI2      RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -2.389 
PHI2      PHI2    |  No paths    -      |  350.000     345.378  |  175.000     167.920  |  175.000     173.428
nCRAS     RCLK    |  No paths    -      |  No paths    -        |  No paths    -        |  1.000       -1.821 
==============================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: PHI2
====================================



Starting Points with Worst Slack
********************************

                 Starting                                            Arrival            
Instance         Reference     Type         Pin     Net              Time        Slack  
                 Clock                                                                  
----------------------------------------------------------------------------------------
CmdSubmitted     PHI2          FD1S3AX      Q       CmdSubmitted     1.148       -2.389 
CmdUFMCS         PHI2          FD1P3AX      Q       CmdUFMCS         0.972       -1.517 
CmdUFMSDI        PHI2          FD1P3AX      Q       CmdUFMSDI        0.972       -0.740 
CmdLEDEN         PHI2          FD1P3AX      Q       CmdLEDEN         1.044       -0.572 
Cmdn8MEGEN       PHI2          FD1P3AX      Q       Cmdn8MEGEN       1.044       -0.572 
CmdUFMCLK        PHI2          FD1P3AX      Q       CmdUFMCLK        0.972       -0.500 
Bank_0io[0]      PHI2          IFS1P3DX     Q       Bank[0]          0.972       167.920
Bank_0io[1]      PHI2          IFS1P3DX     Q       Bank[1]          0.972       167.920
Bank_0io[2]      PHI2          IFS1P3DX     Q       Bank[2]          0.972       167.920
Bank_0io[3]      PHI2          IFS1P3DX     Q       Bank[3]          0.972       167.920
========================================================================================


Ending Points with Worst Slack
******************************

                Starting                                                Required            
Instance        Reference     Type         Pin     Net                  Time         Slack  
                Clock                                                                       
--------------------------------------------------------------------------------------------
UFMCLK_0io      PHI2          OFS1P3DX     SP      i2_i                 0.528        -2.389 
nUFMCS          PHI2          FD1S3AY      D       nUFMCS_s_0_N_5_i     1.089        -1.829 
UFMSDI          PHI2          FD1S3AX      D       UFMSDI_RNO           1.462        -1.751 
LEDEN           PHI2          FD1P3AX      SP      N_28                 0.528        -1.236 
n8MEGEN         PHI2          FD1P3AX      SP      N_26                 0.528        -1.236 
LEDEN           PHI2          FD1P3AX      D       N_74_i               1.089        -0.572 
n8MEGEN         PHI2          FD1P3AX      D       N_131                1.089        -0.572 
UFMCLK_0io      PHI2          OFS1P3DX     D       i1_i                 1.089        -0.500 
ADSubmitted     PHI2          FD1S3AX      D       ADSubmitted_r_0      175.089      167.920
C1Submitted     PHI2          FD1S3AX      D       C1Submitted_s_0      175.089      167.920
============================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.528

    - Propagation time:                      2.917
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.389

    Number of logic level(s):                2
    Starting point:                          CmdSubmitted / Q
    Ending point:                            UFMCLK_0io / SP
    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK

Instance / Net                    Pin      Pin               Arrival     No. of    
Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
CmdSubmitted         Net          -        -       -         -           4         
PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
N_141_i              Net          -        -       -         -           3         
UFMCLK_0io_RNO_0     ORCALUT4     A        In      0.000     2.301 r     -         
UFMCLK_0io_RNO_0     ORCALUT4     Z        Out     0.617     2.917 r     -         
i2_i                 Net          -        -       -         -           1         
UFMCLK_0io           OFS1P3DX     SP       In      0.000     2.917 r     -         
===================================================================================


Path information for path number 2: 
      Requested Period:                      1.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.089

    - Propagation time:                      2.917
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.829

    Number of logic level(s):                2
    Starting point:                          CmdSubmitted / Q
    Ending point:                            nUFMCS / D
    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK

Instance / Net                    Pin      Pin               Arrival     No. of    
Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
CmdSubmitted         FD1S3AX      Q        Out     1.148     1.148 r     -         
CmdSubmitted         Net          -        -       -         -           4         
PHI2r3_RNITCN41      ORCALUT4     A        In      0.000     1.148 r     -         
PHI2r3_RNITCN41      ORCALUT4     Z        Out     1.153     2.301 r     -         
N_141_i              Net          -        -       -         -           3         
nUFMCS_s_0_N_5_i     ORCALUT4     A        In      0.000     2.301 r     -         
nUFMCS_s_0_N_5_i     ORCALUT4     Z        Out     0.617     2.917 r     -         
nUFMCS_s_0_N_5_i     Net          -        -       -         -           1         
nUFMCS               FD1S3AY      D        In      0.000     2.917 r     -         
===================================================================================


Path information for path number 3: 
      Requested Period:                      1.000
    - Setup time:                            -0.462
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.462

    - Propagation time:                      3.214
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.751

    Number of logic level(s):                2
    Starting point:                          CmdSubmitted / Q
    Ending point:                            UFMSDI / D
    The start point is clocked by            PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK

Instance / Net                   Pin      Pin               Arrival     No. of    
Name                Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
CmdSubmitted        FD1S3AX      Q        Out     1.148     1.148 r     -         
CmdSubmitted        Net          -        -       -         -           4         
PHI2r3_RNITCN41     ORCALUT4     A        In      0.000     1.148 r     -         
PHI2r3_RNITCN41     ORCALUT4     Z        Out     1.153     2.301 r     -         
N_141_i             Net          -        -       -         -           3         
UFMSDI_RNO          PFUMX        C0       In      0.000     2.301 r     -         
UFMSDI_RNO          PFUMX        Z        Out     0.913     3.214 r     -         
UFMSDI_RNO          Net          -        -       -         -           1         
UFMSDI              FD1S3AX      D        In      0.000     3.214 r     -         
==================================================================================




====================================
Detailed Report for Clock: RCLK
====================================



Starting Points with Worst Slack
********************************

               Starting                                         Arrival           
Instance       Reference     Type        Pin     Net            Time        Slack 
               Clock                                                              
----------------------------------------------------------------------------------
Ready_fast     RCLK          FD1S3AX     Q       Ready_fast     1.256       -0.784
LEDEN          RCLK          FD1P3AX     Q       LEDEN          1.108       -0.636
n8MEGEN        RCLK          FD1P3AX     Q       n8MEGEN        1.044       -0.572
FS[12]         RCLK          FD1S3AX     Q       FS[12]         1.108       8.400 
FS[13]         RCLK          FD1S3AX     Q       FS[13]         1.108       8.400 
FS[14]         RCLK          FD1S3AX     Q       FS[14]         1.108       8.400 
FS[17]         RCLK          FD1S3AX     Q       FS[17]         1.108       8.400 
FS[16]         RCLK          FD1S3AX     Q       FS[16]         1.148       9.377 
FS[15]         RCLK          FD1S3AX     Q       FS[15]         1.108       9.417 
InitReady      RCLK          FD1S3AX     Q       InitReady      1.268       9.849 
==================================================================================


Ending Points with Worst Slack
******************************

               Starting                                          Required           
Instance       Reference     Type         Pin     Net            Time         Slack 
               Clock                                                                
------------------------------------------------------------------------------------
RBA_0io[0]     RCLK          OFS1P3DX     D       RBAd_0[0]      1.089        -0.784
RBA_0io[1]     RCLK          OFS1P3DX     D       RBAd_0[1]      1.089        -0.784
RowA[0]        RCLK          FD1S3AX      D       RowAd_0[0]     1.089        -0.784
RowA[1]        RCLK          FD1S3AX      D       RowAd_0[1]     1.089        -0.784
RowA[2]        RCLK          FD1S3AX      D       RowAd_0[2]     1.089        -0.784
RowA[3]        RCLK          FD1S3AX      D       RowAd_0[3]     1.089        -0.784
RowA[4]        RCLK          FD1S3AX      D       RowAd_0[4]     1.089        -0.784
RowA[5]        RCLK          FD1S3AX      D       RowAd_0[5]     1.089        -0.784
RowA[6]        RCLK          FD1S3AX      D       RowAd_0[6]     1.089        -0.784
RowA[7]        RCLK          FD1S3AX      D       RowAd_0[7]     1.089        -0.784
====================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.089

    - Propagation time:                      1.873
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.784

    Number of logic level(s):                1
    Starting point:                          Ready_fast / Q
    Ending point:                            RBA_0io[0] / D
    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name               Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
Ready_fast         Net          -        -       -         -           14        
RBAd[0]            ORCALUT4     B        In      0.000     1.256 r     -         
RBAd[0]            ORCALUT4     Z        Out     0.617     1.873 r     -         
RBAd_0[0]          Net          -        -       -         -           1         
RBA_0io[0]         OFS1P3DX     D        In      0.000     1.873 r     -         
=================================================================================


Path information for path number 2: 
      Requested Period:                      1.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.089

    - Propagation time:                      1.873
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.784

    Number of logic level(s):                1
    Starting point:                          Ready_fast / Q
    Ending point:                            RowA[9] / D
    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name               Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
Ready_fast         Net          -        -       -         -           14        
RowAd[9]           ORCALUT4     B        In      0.000     1.256 r     -         
RowAd[9]           ORCALUT4     Z        Out     0.617     1.873 f     -         
RowAd_0[9]         Net          -        -       -         -           1         
RowA[9]            FD1S3AX      D        In      0.000     1.873 f     -         
=================================================================================


Path information for path number 3: 
      Requested Period:                      1.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.089

    - Propagation time:                      1.873
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.784

    Number of logic level(s):                1
    Starting point:                          Ready_fast / Q
    Ending point:                            RowA[8] / D
    The start point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
    The end   point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK

Instance / Net                  Pin      Pin               Arrival     No. of    
Name               Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
Ready_fast         FD1S3AX      Q        Out     1.256     1.256 r     -         
Ready_fast         Net          -        -       -         -           14        
RowAd[8]           ORCALUT4     B        In      0.000     1.256 r     -         
RowAd[8]           ORCALUT4     Z        Out     0.617     1.873 r     -         
RowAd_0[8]         Net          -        -       -         -           1         
RowA[8]            FD1S3AX      D        In      0.000     1.873 r     -         
=================================================================================




====================================
Detailed Report for Clock: nCRAS
====================================



Starting Points with Worst Slack
********************************

             Starting                                   Arrival           
Instance     Reference     Type        Pin     Net      Time        Slack 
             Clock                                                        
--------------------------------------------------------------------------
CBR          nCRAS         FD1S3AX     Q       CBR      1.204       -1.821
FWEr         nCRAS         FD1S3AX     Q       FWEr     1.148       -1.765
==========================================================================


Ending Points with Worst Slack
******************************

               Starting                                              Required           
Instance       Reference     Type         Pin     Net                Time         Slack 
               Clock                                                                    
----------------------------------------------------------------------------------------
nRCAS_0io      nCRAS         OFS1P3BX     D       N_179_i            1.089        -1.821
nRWE_0io       nCRAS         OFS1P3BX     D       N_180_i            1.089        -1.821
nRCS_0io       nCRAS         OFS1P3BX     D       N_27_i             1.089        -1.765
nRowColSel     nCRAS         FD1S3IX      D       nRowColSel_0_0     1.089        -1.749
RCKEEN         nCRAS         FD1S3AX      D       RCKEEN_8           1.089        -1.693
========================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.089

    - Propagation time:                      2.909
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.821

    Number of logic level(s):                2
    Starting point:                          CBR / Q
    Ending point:                            nRCAS_0io / D
    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK

Instance / Net                         Pin      Pin               Arrival     No. of    
Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
CBR                       Net          -        -       -         -           7         
nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
nRCAS_0io_RNO             ORCALUT4     B        In      0.000     2.293 r     -         
nRCAS_0io_RNO             ORCALUT4     Z        Out     0.617     2.909 f     -         
N_179_i                   Net          -        -       -         -           1         
nRCAS_0io                 OFS1P3BX     D        In      0.000     2.909 f     -         
========================================================================================


Path information for path number 2: 
      Requested Period:                      1.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.089

    - Propagation time:                      2.909
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.821

    Number of logic level(s):                2
    Starting point:                          CBR / Q
    Ending point:                            nRWE_0io / D
    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK

Instance / Net                         Pin      Pin               Arrival     No. of    
Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
CBR                       FD1S3AX      Q        Out     1.204     1.204 r     -         
CBR                       Net          -        -       -         -           7         
nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     A        In      0.000     1.204 r     -         
nRCAS_0_sqmuxa_1_0_a3     ORCALUT4     Z        Out     1.089     2.293 r     -         
nRCAS_0_sqmuxa_1          Net          -        -       -         -           2         
nRWE_0io_RNO              ORCALUT4     A        In      0.000     2.293 r     -         
nRWE_0io_RNO              ORCALUT4     Z        Out     0.617     2.909 r     -         
N_180_i                   Net          -        -       -         -           1         
nRWE_0io                  OFS1P3BX     D        In      0.000     2.909 r     -         
========================================================================================


Path information for path number 3: 
      Requested Period:                      1.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.089

    - Propagation time:                      2.853
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.765

    Number of logic level(s):                2
    Starting point:                          FWEr / Q
    Ending point:                            nRCAS_0io / D
    The start point is clocked by            nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
    The end   point is clocked by            RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK

Instance / Net                       Pin      Pin               Arrival     No. of    
Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
FWEr                    FD1S3AX      Q        Out     1.148     1.148 r     -         
FWEr                    Net          -        -       -         -           4         
nRCAS_r_i_a3_1_1_tz     ORCALUT4     D        In      0.000     1.148 r     -         
nRCAS_r_i_a3_1_1_tz     ORCALUT4     Z        Out     1.089     2.237 r     -         
N_27_i_1                Net          -        -       -         -           2         
nRCAS_0io_RNO           ORCALUT4     A        In      0.000     2.237 r     -         
nRCAS_0io_RNO           ORCALUT4     Z        Out     0.617     2.853 f     -         
N_179_i                 Net          -        -       -         -           1         
nRCAS_0io               OFS1P3BX     D        In      0.000     2.853 f     -         
======================================================================================



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)


Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 182MB peak: 184MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2_640hc-4

Register bits: 90 of 640 (14%)
PIC Latch:       0
I/O cells:       67


Details:
BB:             8
CCU2D:          10
FD1P3AX:        11
FD1S3AX:        49
FD1S3AY:        1
FD1S3IX:        3
GSR:            1
IB:             26
IFS1P3DX:       9
INV:            7
OB:             33
OFS1P3BX:       4
OFS1P3DX:       12
OFS1P3JX:       1
ORCALUT4:       135
PFUMX:          1
PUR:            1
VHI:            1
VLO:            1
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 67MB peak: 184MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Aug 15 23:12:47 2023

###########################################################]