Project Settings
Project Name proj_1 Device Name impl1: Lattice MachXO : LCMXO640C
Implementation Name impl1 Top Module RAM2GS
Pipelining 0 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 4 0 0 - 00m:01s - 8/16/2023
4:50:38 AM
(premap)Complete 27 1 0 0m:01s 0m:01s 173MB 8/16/2023
4:50:41 AM
(fpga_mapper)Complete 20 6 0 0m:04s 0m:04s 185MB 8/16/2023
4:50:45 AM
Multi-srs Generator Complete8/16/2023
4:50:39 AM

Area Summary
Register bits 92 I/O cells 67
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 119

Timing Summary
Clock NameReq FreqEst FreqSlack
PHI22.9 MHz0.6 MHz-3.705
RCLK62.5 MHz13.3 MHz-2.312
nCCAS2.9 MHzNANA
nCRAS2.9 MHz0.6 MHz-3.609

Optimizations Summary
Combined Clock Conversion 4 / 0