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RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html

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idk
2021-10-09 01:29:42 +00:00
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<HEAD><TITLE>Place & Route Report</TITLE>
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MachXO2 stuff
2023-08-17 01:04:05 +00:00
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.12.1.454.
idk
2021-10-09 01:29:42 +00:00
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
2.1?
2023-11-03 08:26:41 +00:00
Thu Oct 19 23:50:59 2023
idk
2021-10-09 01:29:42 +00:00
RC
2023-09-21 09:45:45 +00:00
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
idk
2021-10-09 01:29:42 +00:00
RC
2023-09-21 09:45:45 +00:00
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
idk
2021-10-09 01:29:42 +00:00
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
2.1?
2023-11-03 08:26:41 +00:00
5_1 * 0 5.798 0 0.304 0 12 Completed
idk
2021-10-09 01:29:42 +00:00
* : Design saved.
2.1?
2023-11-03 08:26:41 +00:00
Total (real) run time for 1-seed: 12 secs
idk
2021-10-09 01:29:42 +00:00
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
RC
2023-09-21 09:45:45 +00:00
Lattice Place and Route Report for Design &quot;RAM2GS_LCMXO2_1200HC_impl1_map.ncd&quot;
2.1?
2023-11-03 08:26:41 +00:00
Thu Oct 19 23:50:59 2023
idk
2021-10-09 01:29:42 +00:00
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
MachXO2 stuff
2023-08-17 01:04:05 +00:00
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
RC
2023-09-21 09:45:45 +00:00
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
idk
2021-10-09 01:29:42 +00:00
Placement level-cost: 5-1.
Routing Iterations: 6
RC
2023-09-21 09:45:45 +00:00
Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
idk
2021-10-09 01:29:42 +00:00
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
RC
2023-09-21 09:45:45 +00:00
Device: LCMXO2-1200HC
idk
2021-10-09 01:29:42 +00:00
Package: TQFP100
Performance: 4
RC
2023-09-21 09:45:45 +00:00
Loading device for application par from file &apos;xo2c1200.nph&apos; in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
idk
2021-10-09 01:29:42 +00:00
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
2.1?
2023-11-03 08:26:41 +00:00
PIO (prelim) 64+4(JTAG)/108 63% used
64+4(JTAG)/80 85% bonded
IOLOGIC 26/108 24% used
idk
2021-10-09 01:29:42 +00:00
2.1?
2023-11-03 08:26:41 +00:00
SLICE 115/640 17% used
idk
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EFB 1/1 100% used
2.1?
2023-11-03 08:26:41 +00:00
Number of Signals: 383
Number of Connections: 993
idk
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Pin Constraint Summary:
2.1?
2023-11-03 08:26:41 +00:00
64 out of 64 pins locked (100% locked).
idk
2021-10-09 01:29:42 +00:00
2.1?
2023-11-03 08:26:41 +00:00
The following 3 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 48)
RC
2023-09-21 09:45:45 +00:00
PHI2_c (driver: PHI2, clk load #: 20)
2.1?
2023-11-03 08:26:41 +00:00
nCRAS_c (driver: nCRAS, clk load #: 10)
idk
2021-10-09 01:29:42 +00:00
WARNING - par: Signal &quot;PHI2_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;PHI2&quot; is located at &quot;8&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
2.1?
2023-11-03 08:26:41 +00:00
WARNING - par: Signal &quot;nCRAS_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;nCRAS&quot; is located at &quot;17&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
idk
2021-10-09 01:29:42 +00:00
2.1?
2023-11-03 08:26:41 +00:00
The following 1 signal is selected to use the secondary clock routing resources:
MachXO2 stuff
2023-08-17 01:04:05 +00:00
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
idk
2021-10-09 01:29:42 +00:00
MachXO2 stuff
2023-08-17 01:04:05 +00:00
WARNING - par: Signal &quot;nCCAS_c&quot; is selected to use Secondary clock resources. However, its driver comp &quot;nCCAS&quot; is located at &quot;9&quot;, which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
idk
2021-10-09 01:29:42 +00:00
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
2.1?
2023-11-03 08:26:41 +00:00
........
Finished Placer Phase 0. REAL time: 2 secs
idk
2021-10-09 01:29:42 +00:00
Starting Placer Phase 1.
2.1?
2023-11-03 08:26:41 +00:00
.....................
Placer score = 66969.
Finished Placer Phase 1. REAL time: 6 secs
idk
2021-10-09 01:29:42 +00:00
Starting Placer Phase 2.
.
2.1?
2023-11-03 08:26:41 +00:00
Placer score = 66494
Finished Placer Phase 2. REAL time: 6 secs
idk
2021-10-09 01:29:42 +00:00
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
RC
2023-09-21 09:45:45 +00:00
CLK_PIN : 1 out of 8 (12%)
General PIO: 3 out of 108 (2%)
PLL : 0 out of 1 (0%)
idk
2021-10-09 01:29:42 +00:00
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
2.1?
2023-11-03 08:26:41 +00:00
PRIMARY &quot;RCLK_c&quot; from comp &quot;RCLK&quot; on CLK_PIN site &quot;63 (PR5C)&quot;, clk load = 48
RC
2023-09-21 09:45:45 +00:00
PRIMARY &quot;PHI2_c&quot; from comp &quot;PHI2&quot; on PIO site &quot;8 (PL3D)&quot;, clk load = 20
2.1?
2023-11-03 08:26:41 +00:00
PRIMARY &quot;nCRAS_c&quot; from comp &quot;nCRAS&quot; on PIO site &quot;17 (PL8B)&quot;, clk load = 10
RC
2023-09-21 09:45:45 +00:00
SECONDARY &quot;nCCAS_c&quot; from comp &quot;nCCAS&quot; on PIO site &quot;9 (PL4A)&quot;, clk load = 8, ce load = 0, sr load = 0
idk
2021-10-09 01:29:42 +00:00
2.1?
2023-11-03 08:26:41 +00:00
PRIMARY : 3 out of 8 (37%)
SECONDARY: 1 out of 8 (12%)
RC
2023-09-21 09:45:45 +00:00
Edge Clocks:
No edge clock selected.
idk
2021-10-09 01:29:42 +00:00
I/O Usage Summary (final):
2.1?
2023-11-03 08:26:41 +00:00
64 + 4(JTAG) out of 108 (63.0%) PIO sites used.
64 + 4(JTAG) out of 80 (85.0%) bonded PIO sites used.
Number of PIO comps: 64; differential: 0.
idk
2021-10-09 01:29:42 +00:00
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 3.3V | - |
RC
2023-09-21 09:45:45 +00:00
| 1 | 20 / 21 ( 95%) | 3.3V | - |
2.1?
2023-11-03 08:26:41 +00:00
| 2 | 13 / 20 ( 65%) | 3.3V | - |
idk
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| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
2.1?
2023-11-03 08:26:41 +00:00
Total placer CPU time: 5 secs
idk
2021-10-09 01:29:42 +00:00
RC
2023-09-21 09:45:45 +00:00
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
idk
2021-10-09 01:29:42 +00:00
2.1?
2023-11-03 08:26:41 +00:00
0 connections routed; 993 unrouted.
idk
2021-10-09 01:29:42 +00:00
Starting router resource preassignment
2.1?
2023-11-03 08:26:41 +00:00
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
idk
2021-10-09 01:29:42 +00:00
2.1?
2023-11-03 08:26:41 +00:00
Completed router resource preassignment. Real time: 10 secs
idk
2021-10-09 01:29:42 +00:00
2.1?
2023-11-03 08:26:41 +00:00
Start NBR router at 23:51:09 10/19/23
idk
2021-10-09 01:29:42 +00:00
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
2.1?
2023-11-03 08:26:41 +00:00
Start NBR special constraint process at 23:51:09 10/19/23
idk
2021-10-09 01:29:42 +00:00
2.1?
2023-11-03 08:26:41 +00:00
Start NBR section for initial routing at 23:51:09 10/19/23
idk
2021-10-09 01:29:42 +00:00
Level 1, iteration 1
2.1?
2023-11-03 08:26:41 +00:00
0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 6.138ns/0.000ns; real time: 10 secs
idk
2021-10-09 01:29:42 +00:00
Level 2, iteration 1
2.1?
2023-11-03 08:26:41 +00:00
0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 6.138ns/0.000ns; real time: 10 secs
idk
2021-10-09 01:29:42 +00:00
Level 3, iteration 1
2.1?
2023-11-03 08:26:41 +00:00
0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 6.138ns/0.000ns; real time: 10 secs
idk
2021-10-09 01:29:42 +00:00
Level 4, iteration 1
2.1?
2023-11-03 08:26:41 +00:00
17(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.804ns/0.000ns; real time: 11 secs
idk
2021-10-09 01:29:42 +00:00
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
2.1?
2023-11-03 08:26:41 +00:00
Start NBR section for normal routing at 23:51:10 10/19/23
idk
2021-10-09 01:29:42 +00:00
Level 4, iteration 1
2.1?
2023-11-03 08:26:41 +00:00
11(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
idk
2021-10-09 01:29:42 +00:00
Level 4, iteration 2
2.1?
2023-11-03 08:26:41 +00:00
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
Level 4, iteration 3
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
Level 4, iteration 4
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
Level 4, iteration 5
idk
2021-10-09 01:29:42 +00:00
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
2.1?
2023-11-03 08:26:41 +00:00
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
idk
2021-10-09 01:29:42 +00:00
2.1?
2023-11-03 08:26:41 +00:00
Start NBR section for setup/hold timing optimization with effort level 3 at 23:51:10 10/19/23
idk
2021-10-09 01:29:42 +00:00
2.1?
2023-11-03 08:26:41 +00:00
Start NBR section for re-routing at 23:51:10 10/19/23
idk
2021-10-09 01:29:42 +00:00
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
2.1?
2023-11-03 08:26:41 +00:00
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
idk
2021-10-09 01:29:42 +00:00
2.1?
2023-11-03 08:26:41 +00:00
Start NBR section for post-routing at 23:51:10 10/19/23
idk
2021-10-09 01:29:42 +00:00
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
2.1?
2023-11-03 08:26:41 +00:00
Estimated worst slack&lt;setup&gt; : 5.798ns
idk
2021-10-09 01:29:42 +00:00
Timing score&lt;setup&gt; : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
2.1?
2023-11-03 08:26:41 +00:00
Total CPU time 11 secs
Total REAL time: 12 secs
idk
2021-10-09 01:29:42 +00:00
Completely routed.
2.1?
2023-11-03 08:26:41 +00:00
End of route. 993 routed (100.00%); 0 unrouted.
idk
2021-10-09 01:29:42 +00:00
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
RC
2023-09-21 09:45:45 +00:00
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
idk
2021-10-09 01:29:42 +00:00
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
2.1?
2023-11-03 08:26:41 +00:00
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 5.798
idk
2021-10-09 01:29:42 +00:00
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.304
idk
2021-10-09 01:29:42 +00:00
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0
2.1?
2023-11-03 08:26:41 +00:00
Total CPU time to completion: 11 secs
Total REAL time to completion: 12 secs
idk
2021-10-09 01:29:42 +00:00
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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