2023-08-15 09:05:47 +00:00
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<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
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Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO640C
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Package: TQFP100
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Performance: 3
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Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
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Package Status: Final Version 1.17.
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Performance Hardware Data Status: Version 1.124.
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Setup and Hold Report
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--------------------------------------------------------------------------------
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<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
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2023-08-15 09:23:06 +00:00
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Tue Aug 15 05:22:27 2023
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2023-08-15 09:05:47 +00:00
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf
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Design file: ram2gs_lcmxo640c_impl1_map.ncd
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Preference file: ram2gs_lcmxo640c_impl1.prf
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Device,speed: LCMXO640C,3
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
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<FONT COLOR=red><LI><A href='#map_twr_pref_0_0' Target='right'><FONT COLOR=red>FREQUENCY NET "RCLK_c" 283.768000 MHz (213 errors)</FONT></A></LI>
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</FONT> 383 items scored, 213 timing errors detected.
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Warning: 116.104MHz is the maximum frequency for this preference.
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<FONT COLOR=red><LI><A href='#map_twr_pref_0_1' Target='right'><FONT COLOR=red>FREQUENCY NET "PHI2_c" 120.077000 MHz (97 errors)</FONT></A></LI>
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</FONT> 106 items scored, 97 timing errors detected.
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Warning: 42.739MHz is the maximum frequency for this preference.
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Report Type: based on TRACE automatically generated preferences
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
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383 items scored, 213 timing errors detected.
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Error: The following path exceeds requirements by 5.089ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q FS_610__i14 (from RCLK_c +)
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Destination: FF Data in n8MEGEN_418 (to RCLK_c +)
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Delay: 8.369ns (24.4% logic, 75.6% route), 5 logic levels.
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Constraint Details:
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8.369ns physical path delay SLICE_1 to SLICE_56 exceeds
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3.524ns delay constraint less
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0.244ns CE_SET requirement (totaling 3.280ns) by 5.089ns
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Physical Path Details:
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Data path SLICE_1 to SLICE_56:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q0 SLICE_1 (from RCLK_c)
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ROUTE 5 e 1.441 SLICE_1.Q0 to SLICE_90.C1 FS_14
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CTOF_DEL --- 0.371 SLICE_90.C1 to SLICE_90.F1 SLICE_90
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ROUTE 1 e 1.441 SLICE_90.F1 to SLICE_75.B0 n2328
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CTOF_DEL --- 0.371 SLICE_75.B0 to SLICE_75.F0 SLICE_75
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ROUTE 2 e 1.441 SLICE_75.F0 to SLICE_87.B1 n2214
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CTOF_DEL --- 0.371 SLICE_87.B1 to SLICE_87.F1 SLICE_87
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ROUTE 1 e 0.561 SLICE_87.F1 to SLICE_87.A0 n7
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CTOF_DEL --- 0.371 SLICE_87.A0 to SLICE_87.F0 SLICE_87
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ROUTE 1 e 1.441 SLICE_87.F0 to SLICE_56.CE RCLK_c_enable_11 (to RCLK_c)
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--------
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8.369 (24.4% logic, 75.6% route), 5 logic levels.
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Warning: 116.104MHz is the maximum frequency for this preference.
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================================================================================
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<A name="map_twr_pref_0_1"></A>Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
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106 items scored, 97 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path exceeds requirements by 7.535ns (weighted slack = -15.070ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q Bank_i0 (from PHI2_c +)
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Destination: FF Data in C1Submitted_406 (to PHI2_c -)
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Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels.
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Constraint Details:
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11.061ns physical path delay SLICE_88 to SLICE_14 exceeds
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4.164ns delay constraint less
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0.638ns LSR_SET requirement (totaling 3.526ns) by 7.535ns
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Physical Path Details:
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Data path SLICE_88 to SLICE_14:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.560 SLICE_88.CLK to SLICE_88.Q0 SLICE_88 (from PHI2_c)
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ROUTE 1 e 1.441 SLICE_88.Q0 to SLICE_97.D0 Bank_0
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CTOF_DEL --- 0.371 SLICE_97.D0 to SLICE_97.F0 SLICE_97
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ROUTE 1 e 1.441 SLICE_97.F0 to SLICE_81.B0 n2314
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CTOF_DEL --- 0.371 SLICE_81.B0 to SLICE_81.F0 SLICE_81
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ROUTE 1 e 1.441 SLICE_81.F0 to SLICE_18.B1 n26
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CTOF_DEL --- 0.371 SLICE_18.B1 to SLICE_18.F1 SLICE_18
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ROUTE 8 e 1.441 SLICE_18.F1 to SLICE_89.B0 n1326
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CTOF_DEL --- 0.371 SLICE_89.B0 to SLICE_89.F0 SLICE_89
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ROUTE 1 e 1.441 SLICE_89.F0 to SLICE_79.C0 n1280
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CTOF_DEL --- 0.371 SLICE_79.C0 to SLICE_79.F0 SLICE_79
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ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_14.LSR C1Submitted_N_237 (to PHI2_c)
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--------
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11.061 (21.8% logic, 78.2% route), 6 logic levels.
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Warning: 42.739MHz is the maximum frequency for this preference.
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<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 283.768 MHz| 116.104 MHz| 5 *
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FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 120.077 MHz| 42.739 MHz| 6 *
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----------------------------------------------------------------------------
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2 preferences(marked by "*" above) not met.
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----------------------------------------------------------------------------
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Critical Nets | Loads| Errors| % of total
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----------------------------------------------------------------------------
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n1326 | 8| 96| 30.97%
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n26 | 1| 72| 23.23%
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----------------------------------------------------------------------------
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<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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------------------------
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Found 4 clocks:
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Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
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No transfer within this clock domain is found
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Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
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No transfer within this clock domain is found
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Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40
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Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
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Data transfers from:
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Clock Domain: nCRAS_c Source: nCRAS.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
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Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
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---------------
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Timing errors: 310 Score: 1346529
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Cumulative negative slack: 874289
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Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
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--------------------------------------------------------------------------------
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<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
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2023-08-15 09:23:06 +00:00
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Tue Aug 15 05:22:27 2023
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2023-08-15 09:05:47 +00:00
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf
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Design file: ram2gs_lcmxo640c_impl1_map.ncd
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Preference file: ram2gs_lcmxo640c_impl1.prf
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Device,speed: LCMXO640C,M
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
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<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY NET "RCLK_c" 283.768000 MHz (0 errors)</A></LI> 383 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY NET "PHI2_c" 120.077000 MHz (0 errors)</A></LI> 106 items scored, 0 timing errors detected.
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
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383 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.342ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q IS_FSM__i4 (from RCLK_c +)
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Destination: FF Data in IS_FSM__i5 (to RCLK_c +)
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Delay: 0.325ns (38.8% logic, 61.2% route), 1 logic levels.
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Constraint Details:
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0.325ns physical path delay SLICE_100 to SLICE_100 meets
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-0.017ns M_HLD and
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0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns
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Physical Path Details:
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Data path SLICE_100 to SLICE_100:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.126 SLICE_100.CLK to SLICE_100.Q0 SLICE_100 (from RCLK_c)
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ROUTE 1 e 0.199 SLICE_100.Q0 to SLICE_100.M1 n736 (to RCLK_c)
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--------
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0.325 (38.8% logic, 61.2% route), 1 logic levels.
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================================================================================
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<A name="map_twr_pref_1_1"></A>Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
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106 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.430ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q C1Submitted_406 (from PHI2_c -)
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Destination: FF Data in C1Submitted_406 (to PHI2_c -)
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Delay: 0.411ns (51.3% logic, 48.7% route), 2 logic levels.
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Constraint Details:
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0.411ns physical path delay SLICE_14 to SLICE_14 meets
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-0.019ns DIN_HLD and
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0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns
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Physical Path Details:
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Data path SLICE_14 to SLICE_14:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.137 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from PHI2_c)
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ROUTE 2 e 0.199 SLICE_14.Q0 to SLICE_14.C0 C1Submitted
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CTOF_DEL --- 0.074 SLICE_14.C0 to SLICE_14.F0 SLICE_14
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ROUTE 1 e 0.001 SLICE_14.F0 to SLICE_14.DI0 n6_adj_3 (to PHI2_c)
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--------
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0.411 (51.3% logic, 48.7% route), 2 logic levels.
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<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference(MIN Delays) | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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| | |
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FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 0.000 ns| 0.342 ns| 1
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FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 0.000 ns| 0.430 ns| 2
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----------------------------------------------------------------------------
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All preferences were met.
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<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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------------------------
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Found 4 clocks:
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Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
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No transfer within this clock domain is found
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Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
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No transfer within this clock domain is found
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Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40
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Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
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Data transfers from:
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Clock Domain: nCRAS_c Source: nCRAS.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
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Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
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<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
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---------------
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Timing errors: 310 (setup), 0 (hold)
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Score: 1346529 (setup), 0 (hold)
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Cumulative negative slack: 874289 (874289+0)
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--------------------------------------------------------------------------------
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</HTML>
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