mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-12-10 21:49:26 +00:00
967 lines
48 KiB
Plaintext
967 lines
48 KiB
Plaintext
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#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
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#install: C:\lscc\diamond\3.12\synpbase
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#OS: Windows 8 6.2
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#Hostname: ZANEPC
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# Wed Aug 16 04:50:37 2023
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#Implementation: impl1
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEPC
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Implementation : impl1
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Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
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@N|Running in 64-bit mode
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###########################################################[
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEPC
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Implementation : impl1
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Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
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@N|Running in 64-bit mode
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@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo.v" (library work)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
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@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
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Verilog syntax check successful!
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Compiler output is up to date. No re-compile necessary
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Selecting top level module RAM2GS
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@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
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Running optimization stage 1 on RAM2GS .......
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Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
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Running optimization stage 2 on RAM2GS .......
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Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
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For a summary of runtime and memory usage per design unit, please see file:
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==========================================================
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@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\layer0.rt.csv
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At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 90MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Aug 16 04:50:38 2023
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###########################################################]
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###########################################################[
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEPC
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Implementation : impl1
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Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
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@N|Running in 64-bit mode
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Aug 16 04:50:38 2023
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###########################################################]
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For a summary of runtime and memory usage for all design units, please see file:
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==========================================================
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@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.rt.csv
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Aug 16 04:50:38 2023
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###########################################################]
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###########################################################[
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
||
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||
|
Synopsys software or the associated documentation is strictly prohibited.
|
||
|
Tool: Synplify Pro (R)
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|
Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEPC
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Implementation : impl1
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Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
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@N|Running in 64-bit mode
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File D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_comp.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Aug 16 04:50:39 2023
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###########################################################]
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# Wed Aug 16 04:50:39 2023
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Copyright (C) 1994-2021 Synopsys, Inc.
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||
|
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
||
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||
|
Synopsys software or the associated documentation is strictly prohibited.
|
||
|
Tool: Synplify Pro (R)
|
||
|
Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEPC
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Implementation : impl1
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Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
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Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)
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Reading constraint file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
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@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt
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See clock summary report "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1_scck.rpt"
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@N: MF916 |Option synthesis_strategy=base is enabled.
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
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@N: FX493 |Applying initial value "0" on instance InitReady.
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@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
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@N: FX493 |Applying initial value "0" on instance Ready.
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@N: FX493 |Applying initial value "0" on instance RCKE.
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@N: FX493 |Applying initial value "1" on instance nRCAS.
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@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
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@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
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@N: FX493 |Applying initial value "1" on instance nRCS.
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@N: FX493 |Applying initial value "0" on instance LEDEN.
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@N: FX493 |Applying initial value "0" on instance n8MEGEN.
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@N: FX493 |Applying initial value "1" on instance nRRAS.
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@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
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@N: FX493 |Applying initial value "0" on instance CmdUFMCS.
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@N: FX493 |Applying initial value "0" on instance CmdUFMSDI.
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@N: FX493 |Applying initial value "0" on instance C1Submitted.
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@N: FX493 |Applying initial value "0" on instance CmdSubmitted.
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@N: FX493 |Applying initial value "0" on instance ADSubmitted.
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@N: FX493 |Applying initial value "0" on instance XOR8MEG.
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@N: FX493 |Applying initial value "1" on instance nUFMCS.
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@N: FX493 |Applying initial value "0" on instance UFMSDI.
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@N: FX493 |Applying initial value "0" on instance UFMCLK.
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@N: FX493 |Applying initial value "0" on instance CmdEnable.
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@N: FX493 |Applying initial value "1" on instance nRWE.
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Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
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Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
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Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 171MB)
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Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
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@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS
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Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
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Clock Summary
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******************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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---------------------------------------------------------------------------------------
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0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 48
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0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19
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0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14
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0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8
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=======================================================================================
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Clock Load Summary
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***********************
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Clock Source Clock Pin Non-clock Pin Non-clock Pin
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Clock Load Pin Seq Example Seq Example Comb Example
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----------------------------------------------------------------------------------------
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RCLK 48 RCLK(port) CASr2.C - -
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PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
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nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)
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nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv)
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========================================================================================
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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For details review file gcc_ICG_report.rpt
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@S |Clock Optimization Summary
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#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
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4 non-gated/non-generated clock tree(s) driving 89 clock pin(s) of sequential element(s)
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0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
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0 instances converted, 0 sequential instances remain driven by gated/generated clocks
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=========================== Non-Gated/Non-Generated Clocks ============================
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
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---------------------------------------------------------------------------------------
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@KP:ckid0_0 RCLK port 48 nRWE
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@KP:ckid0_1 PHI2 port 19 RA11
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@KP:ckid0_2 nCCAS port 8 WRD[7:0]
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@KP:ckid0_3 nCRAS port 14 RowA[9:0]
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=======================================================================================
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##### END OF CLOCK OPTIMIZATION REPORT ######
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@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
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Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB)
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Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 173MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Wed Aug 16 04:50:41 2023
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###########################################################]
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# Wed Aug 16 04:50:41 2023
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||
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Copyright (C) 1994-2021 Synopsys, Inc.
|
||
|
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
||
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||
|
Synopsys software or the associated documentation is strictly prohibited.
|
||
|
Tool: Synplify Pro (R)
|
||
|
Build: R-2021.03L-SP1
|
||
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEPC
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Implementation : impl1
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Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
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@N: MF916 |Option synthesis_strategy=base is enabled.
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 130MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB)
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB)
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@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
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@N: MO231 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":134:1:134:6|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
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@N: FX493 |Applying initial value "0" on instance IS[0].
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||
|
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||
|
@N: FX493 |Applying initial value "0" on instance IS[1].
|
||
|
@N: FX493 |Applying initial value "0" on instance IS[2].
|
||
|
@N: FX493 |Applying initial value "0" on instance IS[3].
|
||
|
|
||
|
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB)
|
||
|
|
||
|
|
||
|
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB)
|
||
|
|
||
|
|
||
|
Available hyper_sources - for debug and ip models
|
||
|
None Found
|
||
|
|
||
|
|
||
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
|
||
|
|
||
|
|
||
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
|
||
|
|
||
|
|
||
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
|
||
|
|
||
|
|
||
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
|
||
|
|
||
|
|
||
|
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)
|
||
|
|
||
|
|
||
|
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
|
||
|
|
||
|
Pass CPU time Worst Slack Luts / Registers
|
||
|
------------------------------------------------------------
|
||
|
1 0h:00m:01s -3.26ns 127 / 89
|
||
|
2 0h:00m:01s -3.23ns 123 / 89
|
||
|
3 0h:00m:01s -3.23ns 123 / 89
|
||
|
4 0h:00m:01s -3.23ns 123 / 89
|
||
|
5 0h:00m:01s -3.23ns 124 / 89
|
||
|
6 0h:00m:01s -3.23ns 124 / 89
|
||
|
@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
|
||
|
@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":105:1:105:6|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
|
||
|
@N: FX271 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":147:1:147:6|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
|
||
|
Timing driven replication report
|
||
|
Added 3 Registers via timing driven replication
|
||
|
Added 1 LUTs via timing driven replication
|
||
|
|
||
|
7 0h:00m:02s -2.99ns 128 / 92
|
||
|
|
||
|
|
||
|
8 0h:00m:02s -2.99ns 127 / 92
|
||
|
9 0h:00m:02s -3.09ns 127 / 92
|
||
|
10 0h:00m:02s -3.19ns 127 / 92
|
||
|
11 0h:00m:02s -3.19ns 127 / 92
|
||
|
12 0h:00m:02s -3.19ns 127 / 92
|
||
|
|
||
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
|
||
|
|
||
|
|
||
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 179MB)
|
||
|
|
||
|
|
||
|
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 179MB)
|
||
|
|
||
|
Writing Analyst data base D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\synwork\RAM2GS_LCMXO640C_impl1_m.srm
|
||
|
|
||
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 179MB)
|
||
|
|
||
|
Writing EDIF Netlist and constraint files
|
||
|
@N: FX1056 |Writing EDF file: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO640C\impl1\RAM2GS_LCMXO640C_impl1.edi
|
||
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||
|
|
||
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 184MB)
|
||
|
|
||
|
|
||
|
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 185MB)
|
||
|
|
||
|
|
||
|
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 185MB)
|
||
|
|
||
|
@N: MT615 |Found clock RCLK with period 16.00ns
|
||
|
@N: MT615 |Found clock PHI2 with period 350.00ns
|
||
|
@N: MT615 |Found clock nCRAS with period 350.00ns
|
||
|
@N: MT615 |Found clock nCCAS with period 350.00ns
|
||
|
|
||
|
|
||
|
##### START OF TIMING REPORT #####[
|
||
|
# Timing report written on Wed Aug 16 04:50:45 2023
|
||
|
#
|
||
|
|
||
|
|
||
|
Top view: RAM2GS
|
||
|
Requested Frequency: 2.9 MHz
|
||
|
Wire load mode: top
|
||
|
Paths requested: 3
|
||
|
Constraint File(s): D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc
|
||
|
|
||
|
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
||
|
|
||
|
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
|
||
|
|
||
|
|
||
|
|
||
|
Performance Summary
|
||
|
*******************
|
||
|
|
||
|
|
||
|
Worst slack in design: -3.705
|
||
|
|
||
|
Requested Estimated Requested Estimated Clock Clock
|
||
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||
|
-------------------------------------------------------------------------------------------------------------------
|
||
|
PHI2 2.9 MHz 0.6 MHz 350.000 1646.750 -3.705 declared default_clkgroup
|
||
|
RCLK 62.5 MHz 13.3 MHz 16.000 75.280 -2.312 declared default_clkgroup
|
||
|
nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup
|
||
|
nCRAS 2.9 MHz 0.6 MHz 350.000 1613.150 -3.609 declared default_clkgroup
|
||
|
===================================================================================================================
|
||
|
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||
|
|
||
|
|
||
|
@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||
|
@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
|
||
|
@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||
|
@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
|
||
|
@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
|
||
|
|
||
|
|
||
|
|
||
|
Clock Relationships
|
||
|
*******************
|
||
|
|
||
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
||
|
---------------------------------------------------------------------------------------------------------------
|
||
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||
|
---------------------------------------------------------------------------------------------------------------
|
||
|
RCLK RCLK | 16.000 7.560 | No paths - | No paths - | No paths -
|
||
|
RCLK PHI2 | 2.000 -1.216 | No paths - | 1.000 -2.312 | No paths -
|
||
|
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -3.705
|
||
|
PHI2 PHI2 | No paths - | 350.000 343.998 | 175.000 166.500 | 175.000 171.784
|
||
|
nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -3.609
|
||
|
===============================================================================================================
|
||
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||
|
|
||
|
|
||
|
|
||
|
Interface Information
|
||
|
*********************
|
||
|
|
||
|
No IO constraint found
|
||
|
|
||
|
|
||
|
|
||
|
====================================
|
||
|
Detailed Report for Clock: PHI2
|
||
|
====================================
|
||
|
|
||
|
|
||
|
|
||
|
Starting Points with Worst Slack
|
||
|
********************************
|
||
|
|
||
|
Starting Arrival
|
||
|
Instance Reference Type Pin Net Time Slack
|
||
|
Clock
|
||
|
---------------------------------------------------------------------------------------
|
||
|
CmdSubmitted PHI2 FD1S3AX Q CmdSubmitted 1.552 -3.705
|
||
|
CmdUFMCLK PHI2 FD1P3AX Q CmdUFMCLK 1.348 -3.297
|
||
|
CmdUFMCS PHI2 FD1P3AX Q CmdUFMCS 1.348 -3.297
|
||
|
CmdUFMSDI PHI2 FD1P3AX Q CmdUFMSDI 1.348 -3.297
|
||
|
CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.456 -2.216
|
||
|
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.456 -2.216
|
||
|
Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 166.500
|
||
|
Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 166.500
|
||
|
Bank[4] PHI2 FD1S3AX Q Bank[4] 1.348 166.500
|
||
|
Bank[5] PHI2 FD1S3AX Q Bank[5] 1.348 166.500
|
||
|
=======================================================================================
|
||
|
|
||
|
|
||
|
Ending Points with Worst Slack
|
||
|
******************************
|
||
|
|
||
|
Starting Required
|
||
|
Instance Reference Type Pin Net Time Slack
|
||
|
Clock
|
||
|
--------------------------------------------------------------------------------------------
|
||
|
UFMCLK PHI2 FD1S3AX D UFMCLK_RNO -0.003 -3.705
|
||
|
UFMSDI PHI2 FD1S3AX D UFMSDI_RNO -0.003 -3.705
|
||
|
nUFMCS PHI2 FD1S3AY D nUFMCS_s_0_N_5_i -0.003 -3.705
|
||
|
LEDEN PHI2 FD1P3AX SP N_33 0.806 -2.800
|
||
|
n8MEGEN PHI2 FD1P3AX SP N_31 0.806 -2.800
|
||
|
LEDEN PHI2 FD1P3AX D N_70 -0.003 -2.216
|
||
|
n8MEGEN PHI2 FD1P3AX D N_69 -0.003 -2.216
|
||
|
CmdSubmitted PHI2 FD1S3AX D N_460_0 173.997 166.500
|
||
|
ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 167.797
|
||
|
C1Submitted PHI2 FD1S3AX D C1Submitted_RNO 173.997 167.797
|
||
|
============================================================================================
|
||
|
|
||
|
|
||
|
|
||
|
Worst Path Information
|
||
|
***********************
|
||
|
|
||
|
|
||
|
Path information for path number 1:
|
||
|
Requested Period: 1.000
|
||
|
- Setup time: 1.003
|
||
|
+ Clock delay at ending point: 0.000 (ideal)
|
||
|
= Required time: -0.003
|
||
|
|
||
|
- Propagation time: 3.702
|
||
|
- Clock delay at starting point: 0.000 (ideal)
|
||
|
= Slack (critical) : -3.705
|
||
|
|
||
|
Number of logic level(s): 2
|
||
|
Starting point: CmdSubmitted / Q
|
||
|
Ending point: UFMCLK / D
|
||
|
The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||
|
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||
|
|
||
|
Instance / Net Pin Pin Arrival No. of
|
||
|
Name Type Name Dir Delay Time Fan Out(s)
|
||
|
----------------------------------------------------------------------------------
|
||
|
CmdSubmitted FD1S3AX Q Out 1.552 1.552 r -
|
||
|
CmdSubmitted Net - - - - 3
|
||
|
PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r -
|
||
|
PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r -
|
||
|
N_139_i Net - - - - 3
|
||
|
UFMCLK_RNO ORCALUT4 A In 0.000 2.945 r -
|
||
|
UFMCLK_RNO ORCALUT4 Z Out 0.757 3.702 r -
|
||
|
UFMCLK_RNO Net - - - - 1
|
||
|
UFMCLK FD1S3AX D In 0.000 3.702 r -
|
||
|
==================================================================================
|
||
|
|
||
|
|
||
|
Path information for path number 2:
|
||
|
Requested Period: 1.000
|
||
|
- Setup time: 1.003
|
||
|
+ Clock delay at ending point: 0.000 (ideal)
|
||
|
= Required time: -0.003
|
||
|
|
||
|
- Propagation time: 3.702
|
||
|
- Clock delay at starting point: 0.000 (ideal)
|
||
|
= Slack (critical) : -3.705
|
||
|
|
||
|
Number of logic level(s): 2
|
||
|
Starting point: CmdSubmitted / Q
|
||
|
Ending point: nUFMCS / D
|
||
|
The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||
|
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||
|
|
||
|
Instance / Net Pin Pin Arrival No. of
|
||
|
Name Type Name Dir Delay Time Fan Out(s)
|
||
|
-----------------------------------------------------------------------------------
|
||
|
CmdSubmitted FD1S3AX Q Out 1.552 1.552 r -
|
||
|
CmdSubmitted Net - - - - 3
|
||
|
PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r -
|
||
|
PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r -
|
||
|
N_139_i Net - - - - 3
|
||
|
nUFMCS_s_0_N_5_i ORCALUT4 A In 0.000 2.945 r -
|
||
|
nUFMCS_s_0_N_5_i ORCALUT4 Z Out 0.757 3.702 r -
|
||
|
nUFMCS_s_0_N_5_i Net - - - - 1
|
||
|
nUFMCS FD1S3AY D In 0.000 3.702 r -
|
||
|
===================================================================================
|
||
|
|
||
|
|
||
|
Path information for path number 3:
|
||
|
Requested Period: 1.000
|
||
|
- Setup time: 1.003
|
||
|
+ Clock delay at ending point: 0.000 (ideal)
|
||
|
= Required time: -0.003
|
||
|
|
||
|
- Propagation time: 3.702
|
||
|
- Clock delay at starting point: 0.000 (ideal)
|
||
|
= Slack (critical) : -3.705
|
||
|
|
||
|
Number of logic level(s): 2
|
||
|
Starting point: CmdSubmitted / Q
|
||
|
Ending point: UFMSDI / D
|
||
|
The start point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||
|
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||
|
|
||
|
Instance / Net Pin Pin Arrival No. of
|
||
|
Name Type Name Dir Delay Time Fan Out(s)
|
||
|
----------------------------------------------------------------------------------
|
||
|
CmdSubmitted FD1S3AX Q Out 1.552 1.552 r -
|
||
|
CmdSubmitted Net - - - - 3
|
||
|
PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r -
|
||
|
PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r -
|
||
|
N_139_i Net - - - - 3
|
||
|
UFMSDI_RNO ORCALUT4 A In 0.000 2.945 r -
|
||
|
UFMSDI_RNO ORCALUT4 Z Out 0.757 3.702 r -
|
||
|
UFMSDI_RNO Net - - - - 1
|
||
|
UFMSDI FD1S3AX D In 0.000 3.702 r -
|
||
|
==================================================================================
|
||
|
|
||
|
|
||
|
|
||
|
|
||
|
====================================
|
||
|
Detailed Report for Clock: RCLK
|
||
|
====================================
|
||
|
|
||
|
|
||
|
|
||
|
Starting Points with Worst Slack
|
||
|
********************************
|
||
|
|
||
|
Starting Arrival
|
||
|
Instance Reference Type Pin Net Time Slack
|
||
|
Clock
|
||
|
-----------------------------------------------------------------------------
|
||
|
LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312
|
||
|
n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216
|
||
|
FS[13] RCLK FD1S3AX Q FS[13] 1.552 7.560
|
||
|
FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.560
|
||
|
FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.560
|
||
|
FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.560
|
||
|
S[1] RCLK FD1S3IX Q S[1] 1.768 8.533
|
||
|
S[0] RCLK FD1S3IX Q CO0 1.756 8.545
|
||
|
FS[16] RCLK FD1S3AX Q FS[16] 1.612 8.689
|
||
|
FS[12] RCLK FD1S3AX Q FS[12] 1.552 8.749
|
||
|
=============================================================================
|
||
|
|
||
|
|
||
|
Ending Points with Worst Slack
|
||
|
******************************
|
||
|
|
||
|
Starting Required
|
||
|
Instance Reference Type Pin Net Time Slack
|
||
|
Clock
|
||
|
-----------------------------------------------------------------------------------------
|
||
|
CmdLEDEN RCLK FD1P3AX D N_21_i -0.003 -2.312
|
||
|
XOR8MEG RCLK FD1P3AX D XOR8MEG_3 -0.003 -2.312
|
||
|
Cmdn8MEGEN RCLK FD1P3AX D N_19_i -0.003 -2.216
|
||
|
RA11 RCLK FD1S3IX D RA11_2 0.997 -1.216
|
||
|
UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.560
|
||
|
UFMCLK RCLK FD1S3AX D UFMCLK_RNO 14.997 7.668
|
||
|
LEDEN RCLK FD1P3AX SP N_33 15.806 8.261
|
||
|
n8MEGEN RCLK FD1P3AX SP N_31 15.806 8.261
|
||
|
nRCS RCLK FD1S3AY D N_28_i 14.997 8.533
|
||
|
nUFMCS RCLK FD1S3AY D nUFMCS_s_0_N_5_i 14.997 8.653
|
||
|
=========================================================================================
|
||
|
|
||
|
|
||
|
|
||
|
Worst Path Information
|
||
|
***********************
|
||
|
|
||
|
|
||
|
Path information for path number 1:
|
||
|
Requested Period: 1.000
|
||
|
- Setup time: 1.003
|
||
|
+ Clock delay at ending point: 0.000 (ideal)
|
||
|
= Required time: -0.003
|
||
|
|
||
|
- Propagation time: 2.309
|
||
|
- Clock delay at starting point: 0.000 (ideal)
|
||
|
= Slack (non-critical) : -2.312
|
||
|
|
||
|
Number of logic level(s): 1
|
||
|
Starting point: LEDEN / Q
|
||
|
Ending point: CmdLEDEN / D
|
||
|
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||
|
The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||
|
|
||
|
Instance / Net Pin Pin Arrival No. of
|
||
|
Name Type Name Dir Delay Time Fan Out(s)
|
||
|
---------------------------------------------------------------------------------
|
||
|
LEDEN FD1P3AX Q Out 1.552 1.552 r -
|
||
|
LEDEN Net - - - - 3
|
||
|
CmdLEDEN_RNO ORCALUT4 A In 0.000 1.552 r -
|
||
|
CmdLEDEN_RNO ORCALUT4 Z Out 0.757 2.309 r -
|
||
|
N_21_i Net - - - - 1
|
||
|
CmdLEDEN FD1P3AX D In 0.000 2.309 r -
|
||
|
=================================================================================
|
||
|
|
||
|
|
||
|
Path information for path number 2:
|
||
|
Requested Period: 1.000
|
||
|
- Setup time: 1.003
|
||
|
+ Clock delay at ending point: 0.000 (ideal)
|
||
|
= Required time: -0.003
|
||
|
|
||
|
- Propagation time: 2.309
|
||
|
- Clock delay at starting point: 0.000 (ideal)
|
||
|
= Slack (non-critical) : -2.312
|
||
|
|
||
|
Number of logic level(s): 1
|
||
|
Starting point: LEDEN / Q
|
||
|
Ending point: XOR8MEG / D
|
||
|
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||
|
The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||
|
|
||
|
Instance / Net Pin Pin Arrival No. of
|
||
|
Name Type Name Dir Delay Time Fan Out(s)
|
||
|
-------------------------------------------------------------------------------------
|
||
|
LEDEN FD1P3AX Q Out 1.552 1.552 r -
|
||
|
LEDEN Net - - - - 3
|
||
|
XOR8MEG_3_u_0_a3_3 ORCALUT4 B In 0.000 1.552 r -
|
||
|
XOR8MEG_3_u_0_a3_3 ORCALUT4 Z Out 0.757 2.309 f -
|
||
|
XOR8MEG_3 Net - - - - 1
|
||
|
XOR8MEG FD1P3AX D In 0.000 2.309 f -
|
||
|
=====================================================================================
|
||
|
|
||
|
|
||
|
Path information for path number 3:
|
||
|
Requested Period: 1.000
|
||
|
- Setup time: 1.003
|
||
|
+ Clock delay at ending point: 0.000 (ideal)
|
||
|
= Required time: -0.003
|
||
|
|
||
|
- Propagation time: 2.213
|
||
|
- Clock delay at starting point: 0.000 (ideal)
|
||
|
= Slack (non-critical) : -2.216
|
||
|
|
||
|
Number of logic level(s): 1
|
||
|
Starting point: n8MEGEN / Q
|
||
|
Ending point: Cmdn8MEGEN / D
|
||
|
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||
|
The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||
|
|
||
|
Instance / Net Pin Pin Arrival No. of
|
||
|
Name Type Name Dir Delay Time Fan Out(s)
|
||
|
---------------------------------------------------------------------------------
|
||
|
n8MEGEN FD1P3AX Q Out 1.456 1.456 r -
|
||
|
n8MEGEN Net - - - - 2
|
||
|
Cmdn8MEGEN_RNO ORCALUT4 C In 0.000 1.456 r -
|
||
|
Cmdn8MEGEN_RNO ORCALUT4 Z Out 0.757 2.213 r -
|
||
|
N_19_i Net - - - - 1
|
||
|
Cmdn8MEGEN FD1P3AX D In 0.000 2.213 r -
|
||
|
=================================================================================
|
||
|
|
||
|
|
||
|
|
||
|
|
||
|
====================================
|
||
|
Detailed Report for Clock: nCRAS
|
||
|
====================================
|
||
|
|
||
|
|
||
|
|
||
|
Starting Points with Worst Slack
|
||
|
********************************
|
||
|
|
||
|
Starting Arrival
|
||
|
Instance Reference Type Pin Net Time Slack
|
||
|
Clock
|
||
|
--------------------------------------------------------------------------------
|
||
|
CBR nCRAS FD1S3AX Q CBR 1.660 -3.609
|
||
|
CBR_fast nCRAS FD1S3AX Q CBR_fast 1.456 -3.513
|
||
|
FWEr nCRAS FD1S3AX Q FWEr 1.552 -3.501
|
||
|
FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.456 -3.405
|
||
|
================================================================================
|
||
|
|
||
|
|
||
|
Ending Points with Worst Slack
|
||
|
******************************
|
||
|
|
||
|
Starting Required
|
||
|
Instance Reference Type Pin Net Time Slack
|
||
|
Clock
|
||
|
---------------------------------------------------------------------------------------
|
||
|
nRWE nCRAS FD1S3AY D N_39_i -0.003 -3.609
|
||
|
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.609
|
||
|
nRCAS nCRAS FD1S3AY D N_37_i -0.003 -3.513
|
||
|
RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.405
|
||
|
nRCS nCRAS FD1S3AY D N_28_i -0.003 -3.405
|
||
|
=======================================================================================
|
||
|
|
||
|
|
||
|
|
||
|
Worst Path Information
|
||
|
***********************
|
||
|
|
||
|
|
||
|
Path information for path number 1:
|
||
|
Requested Period: 1.000
|
||
|
- Setup time: 1.003
|
||
|
+ Clock delay at ending point: 0.000 (ideal)
|
||
|
= Required time: -0.003
|
||
|
|
||
|
- Propagation time: 3.606
|
||
|
- Clock delay at starting point: 0.000 (ideal)
|
||
|
= Slack (non-critical) : -3.609
|
||
|
|
||
|
Number of logic level(s): 2
|
||
|
Starting point: CBR / Q
|
||
|
Ending point: nRWE / D
|
||
|
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||
|
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||
|
|
||
|
Instance / Net Pin Pin Arrival No. of
|
||
|
Name Type Name Dir Delay Time Fan Out(s)
|
||
|
---------------------------------------------------------------------------------
|
||
|
CBR FD1S3AX Q Out 1.660 1.660 r -
|
||
|
CBR Net - - - - 5
|
||
|
nRWE_RNO_0 ORCALUT4 A In 0.000 1.660 r -
|
||
|
nRWE_RNO_0 ORCALUT4 Z Out 1.189 2.849 f -
|
||
|
G_17_1 Net - - - - 1
|
||
|
nRWE_RNO ORCALUT4 B In 0.000 2.849 f -
|
||
|
nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r -
|
||
|
N_39_i Net - - - - 1
|
||
|
nRWE FD1S3AY D In 0.000 3.606 r -
|
||
|
=================================================================================
|
||
|
|
||
|
|
||
|
Path information for path number 2:
|
||
|
Requested Period: 1.000
|
||
|
- Setup time: 1.003
|
||
|
+ Clock delay at ending point: 0.000 (ideal)
|
||
|
= Required time: -0.003
|
||
|
|
||
|
- Propagation time: 3.606
|
||
|
- Clock delay at starting point: 0.000 (ideal)
|
||
|
= Slack (non-critical) : -3.609
|
||
|
|
||
|
Number of logic level(s): 2
|
||
|
Starting point: CBR / Q
|
||
|
Ending point: nRowColSel / D
|
||
|
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||
|
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||
|
|
||
|
Instance / Net Pin Pin Arrival No. of
|
||
|
Name Type Name Dir Delay Time Fan Out(s)
|
||
|
--------------------------------------------------------------------------------------
|
||
|
CBR FD1S3AX Q Out 1.660 1.660 r -
|
||
|
CBR Net - - - - 5
|
||
|
nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.660 r -
|
||
|
nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.189 2.849 f -
|
||
|
N_179 Net - - - - 1
|
||
|
nRowColSel_0_0 ORCALUT4 B In 0.000 2.849 f -
|
||
|
nRowColSel_0_0 ORCALUT4 Z Out 0.757 3.606 f -
|
||
|
nRowColSel_0_0 Net - - - - 1
|
||
|
nRowColSel FD1S3IX D In 0.000 3.606 f -
|
||
|
======================================================================================
|
||
|
|
||
|
|
||
|
Path information for path number 3:
|
||
|
Requested Period: 1.000
|
||
|
- Setup time: 1.003
|
||
|
+ Clock delay at ending point: 0.000 (ideal)
|
||
|
= Required time: -0.003
|
||
|
|
||
|
- Propagation time: 3.510
|
||
|
- Clock delay at starting point: 0.000 (ideal)
|
||
|
= Slack (non-critical) : -3.513
|
||
|
|
||
|
Number of logic level(s): 2
|
||
|
Starting point: CBR_fast / Q
|
||
|
Ending point: nRCAS / D
|
||
|
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||
|
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||
|
|
||
|
Instance / Net Pin Pin Arrival No. of
|
||
|
Name Type Name Dir Delay Time Fan Out(s)
|
||
|
----------------------------------------------------------------------------------------
|
||
|
CBR_fast FD1S3AX Q Out 1.456 1.456 r -
|
||
|
CBR_fast Net - - - - 2
|
||
|
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.456 r -
|
||
|
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.753 r -
|
||
|
nRCAS_0_sqmuxa_1 Net - - - - 2
|
||
|
nRCAS_RNO ORCALUT4 B In 0.000 2.753 r -
|
||
|
nRCAS_RNO ORCALUT4 Z Out 0.757 3.510 f -
|
||
|
N_37_i Net - - - - 1
|
||
|
nRCAS FD1S3AY D In 0.000 3.510 f -
|
||
|
========================================================================================
|
||
|
|
||
|
|
||
|
|
||
|
##### END OF TIMING REPORT #####]
|
||
|
|
||
|
Timing exceptions that could not be applied
|
||
|
|
||
|
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
|
||
|
|
||
|
|
||
|
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB)
|
||
|
|
||
|
---------------------------------------
|
||
|
Resource Usage Report
|
||
|
Part: lcmxo640c-3
|
||
|
|
||
|
Register bits: 92 of 640 (14%)
|
||
|
PIC Latch: 0
|
||
|
I/O cells: 67
|
||
|
|
||
|
|
||
|
Details:
|
||
|
BB: 8
|
||
|
CCU2: 9
|
||
|
FD1P3AX: 11
|
||
|
FD1S3AX: 59
|
||
|
FD1S3AY: 5
|
||
|
FD1S3IX: 14
|
||
|
FD1S3JX: 3
|
||
|
GSR: 1
|
||
|
IB: 26
|
||
|
INV: 8
|
||
|
OB: 33
|
||
|
ORCALUT4: 119
|
||
|
PFUMX: 2
|
||
|
PUR: 1
|
||
|
VHI: 1
|
||
|
VLO: 1
|
||
|
Mapper successful!
|
||
|
|
||
|
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 66MB peak: 185MB)
|
||
|
|
||
|
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
|
||
|
# Wed Aug 16 04:50:45 2023
|
||
|
|
||
|
###########################################################]
|