mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-12-11 13:49:28 +00:00
156 lines
6.5 KiB
Plaintext
156 lines
6.5 KiB
Plaintext
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VOLTAGE 3.300 V;
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BLOCK RESETPATHS ;
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BLOCK ASYNCPATHS ;
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IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "LED" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ;
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IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ;
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PERIOD NET "PHI2_c" 350.000000 ns ;
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PERIOD NET "nCCAS_c" 350.000000 ns ;
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PERIOD NET "nCRAS_c" 350.000000 ns ;
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PERIOD NET "RCLK_c" 15.000000 ns ;
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CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
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CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
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OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
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OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
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OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
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OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
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OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
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OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
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OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
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OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
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OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
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OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
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OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
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OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
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OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
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OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
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OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
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OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
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OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
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OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
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OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
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OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
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OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
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OUTPUT PORT "LED" LOAD 25.000000 pF ;
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OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
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OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
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OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
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OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
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OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
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OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
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OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
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OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
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VCCIO_DERATE BANK 0 PERCENT -5;
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VCCIO_DERATE PERCENT -5;
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VCCIO_DERATE BANK 1 PERCENT -5;
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