Apple-2-HW/RAM2GS
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RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo

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All compiling
2023-08-15 09:05:47 +00:00
// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
// ldbanno -n Verilog -o RAM2GS_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd
// Netlist created on Tue Aug 15 05:03:24 2023
// Netlist written on Tue Aug 15 05:03:26 2023
// Design is for device LCMXO2-640HC
// Design is for package TQFP100
// Design is for performance grade 4
`timescale 1 ns / 1 ps
module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS,
UFMCLK, UFMSDI, UFMSDO );
input PHI2;
input [9:0] MAin;
input [1:0] CROW;
input [7:0] Din;
input nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
output [7:0] Dout;
output LED;
output [1:0] RBA;
output [11:0] RA;
output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
inout [7:0] RD;
wire FS_14, FS_13, n81, n82, RCLK_c, n1998, n1999, FS_12, FS_11, n83, n84,
n1997, FS_8, FS_7, n87, n88, n1995, n1996, FS_6, FS_5, n89, n90,
n1994, FS_2, FS_1, n93, n94, n1992, n1993, FS_0, n95, CASr2, CASr3,
FS_10, FS_9, n85, n86, FS_17, n78, n2000, FS_4, FS_3, n91, n92, FS_16,
FS_15, n79, n80, Din_c_4, Din_c_6, Din_c_1, Din_c_7, n2382, n8, n2225,
n2180, ADSubmitted_N_246, PHI2_N_120_enable_2, C1Submitted_N_237,
PHI2_c, ADSubmitted, n26, MAin_c_5, n22, MAin_c_2, MAin_c_1,
C1Submitted, n2365, nFWE_c, n1398, nCCAS_c, nCCAS_N_3, CASr, n2254,
Din_c_5, n2191, n2183, n15_adj_1, n2208, n2363, CmdEnable_N_248,
PHI2_N_120_enable_1, CmdEnable, \n2447\001/BUF1 , PHI2_N_120_enable_7,
CmdSubmitted, n1314, n8MEGEN, Din_c_0, Cmdn8MEGEN_N_264,
PHI2_N_120_enable_6, Cmdn8MEGEN, Din_c_3, n2373, nCRAS_c, FWEr, CBR,
\n2447\000/BUF1 , RCLK_c_enable_28, InitReady, n2447,
RCLK_c_enable_16, LEDEN, nCRAS_c__inv, RASr, LED_c, RASr2,
nRowColSel_N_35, nRCAS_N_165, Ready, n2381, nRCS_N_139, n2036,
nRWE_N_177, RA_0, XOR8MEG, RA11_N_184, RA_c, n6_adj_2, PHI2r2, PHI2r3,
n15_adj_4, RCKEEN_N_121, RCLK_c_enable_6, RCKEEN, RCLK_c_enable_10,
RASr3, RCKE_N_132, PHI2r, RCKE_c, \n2447\002/BUF1 , Ready_N_292,
n2267, n13_adj_6, CmdUFMCLK, n1893, UFMCLK_N_224, n2366, UFMCLK_c,
n10, n7, n4, CmdUFMSDI, n2174, UFMSDI_N_231, UFMSDI_c, n2260, Din_c_2,
XOR8MEG_N_110, PHI2_N_120_enable_3, n2375, UFMSDO_c, n2367,
n8MEGEN_N_91, RCLK_c_enable_15, nRCS_N_142, nRCAS_N_166, n2371,
nRCAS_N_161, nRCAS_c, nRCS_N_141, nRCS_N_137, nRCS_N_136, nRCS_c,
n2379, nRRAS_N_156, nRRAS_c, nRWE_N_178, n1765, nRWE_N_171,
RCLK_c_enable_5, nRWE_c, nRowColSel_N_34, nRowColSel_N_33, n2376,
n1060, n2372, n917, nRowColSel, nRowColSel_N_32, n827, n2227, n1406,
Bank_3, Bank_6, n2287, n13, n2374, n2368, CmdUFMCS, n64, nUFMCS_N_199,
nUFMCS_c, n6_adj_3, Ready_N_296, n2204, n2369, MAin_c_0,
PHI2_N_120_enable_8, Bank_5, n2277, Bank_2, n2220, RowA_0, RowA_1,
n2370, n2228, n732, n733, RCLK_c_enable_27, n2055, MAin_c_9, MAin_c_8,
RowA_8, RowA_9, n2210, nRWE_N_182, nRCS_N_146, n728, n729, n727, n730,
n2378, n726, n12, MAin_c_4, RowA_4, RowA_5, n1277, n4_adj_7, n2377,
n738, n737, n14, n15, n6, CROW_c_1, CROW_c_0, RBA_c_0, RBA_c_1,
n7_adj_5, n2362, WRD_6, WRD_7, WRD_4, WRD_5, WRD_0, WRD_1, MAin_c_3,
RowA_2, RowA_3, WRD_2, WRD_3, RA_1_9, Bank_0, RDQML_c, Bank_1, n734,
n735, RA_1_8, RDQMH_c, Bank_4, MAin_c_7, RowA_7, RA_1_7, Bank_7,
MAin_c_6, RowA_6, RA_1_6, RA_1_5, RA_1_0, RA_1_4, RA_1_1, RA_1_3,
RA_1_2, n984, n736, Dout_c, Dout_0, Dout_1, Dout_2, Dout_3, Dout_4,
Dout_5, Dout_6, VCCI;
SLICE_0 SLICE_0( .A1(FS_14), .A0(FS_13), .DI1(n81), .DI0(n82), .CLK(RCLK_c),
.FCI(n1998), .F0(n82), .Q0(FS_13), .F1(n81), .Q1(FS_14), .FCO(n1999));
SLICE_1 SLICE_1( .A1(FS_12), .A0(FS_11), .DI1(n83), .DI0(n84), .CLK(RCLK_c),
.FCI(n1997), .F0(n84), .Q0(FS_11), .F1(n83), .Q1(FS_12), .FCO(n1998));
SLICE_2 SLICE_2( .A1(FS_8), .A0(FS_7), .DI1(n87), .DI0(n88), .CLK(RCLK_c),
.FCI(n1995), .F0(n88), .Q0(FS_7), .F1(n87), .Q1(FS_8), .FCO(n1996));
SLICE_3 SLICE_3( .A1(FS_6), .A0(FS_5), .DI1(n89), .DI0(n90), .CLK(RCLK_c),
.FCI(n1994), .F0(n90), .Q0(FS_5), .F1(n89), .Q1(FS_6), .FCO(n1995));
SLICE_4 SLICE_4( .A1(FS_2), .A0(FS_1), .DI1(n93), .DI0(n94), .CLK(RCLK_c),
.FCI(n1992), .F0(n94), .Q0(FS_1), .F1(n93), .Q1(FS_2), .FCO(n1993));
SLICE_5 SLICE_5( .A1(FS_0), .DI1(n95), .M0(CASr2), .CLK(RCLK_c), .Q0(CASr3),
.F1(n95), .Q1(FS_0), .FCO(n1992));
SLICE_6 SLICE_6( .A1(FS_10), .A0(FS_9), .DI1(n85), .DI0(n86), .CLK(RCLK_c),
.FCI(n1996), .F0(n86), .Q0(FS_9), .F1(n85), .Q1(FS_10), .FCO(n1997));
SLICE_7 SLICE_7( .A0(FS_17), .DI0(n78), .CLK(RCLK_c), .FCI(n2000), .F0(n78),
.Q0(FS_17));
SLICE_8 SLICE_8( .A1(FS_4), .A0(FS_3), .DI1(n91), .DI0(n92), .CLK(RCLK_c),
.FCI(n1993), .F0(n92), .Q0(FS_3), .F1(n91), .Q1(FS_4), .FCO(n1994));
SLICE_9 SLICE_9( .A1(FS_16), .A0(FS_15), .DI1(n79), .DI0(n80), .CLK(RCLK_c),
.FCI(n1999), .F0(n80), .Q0(FS_15), .F1(n79), .Q1(FS_16), .FCO(n2000));
SLICE_10 SLICE_10( .D1(Din_c_4), .C1(Din_c_6), .B1(Din_c_1), .A1(Din_c_7),
.D0(n2382), .C0(n8), .B0(n2225), .A0(n2180), .DI0(ADSubmitted_N_246),
.CE(PHI2_N_120_enable_2), .LSR(C1Submitted_N_237), .CLK(PHI2_c),
.F0(ADSubmitted_N_246), .Q0(ADSubmitted), .F1(n8));
SLICE_15 SLICE_15( .D1(n26), .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2),
.D0(MAin_c_1), .C0(C1Submitted), .B0(n2365), .A0(nFWE_c), .DI0(n1398),
.LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n1398), .Q0(C1Submitted),
.F1(n2365));
SLICE_16 SLICE_16( .A0(nCCAS_c), .DI0(nCCAS_N_3), .M1(CASr), .CLK(RCLK_c),
.F0(nCCAS_N_3), .Q0(CASr), .Q1(CASr2));
SLICE_19 SLICE_19( .D1(n2254), .C1(Din_c_5), .B1(n2191), .A1(n2183),
.D0(n15_adj_1), .C0(n2208), .B0(MAin_c_1), .A0(n2363),
.DI0(CmdEnable_N_248), .CE(PHI2_N_120_enable_1), .CLK(PHI2_c),
.F0(CmdEnable_N_248), .Q0(CmdEnable), .F1(n15_adj_1));
SLICE_20 SLICE_20( .DI0(\n2447\001/BUF1 ), .CE(PHI2_N_120_enable_7),
.CLK(PHI2_c), .F0(\n2447\001/BUF1 ), .Q0(CmdSubmitted));
SLICE_24 SLICE_24( .C1(Din_c_5), .B1(Din_c_7), .A1(Din_c_6), .D0(n1314),
.C0(Din_c_4), .B0(n8MEGEN), .A0(Din_c_0), .DI0(Cmdn8MEGEN_N_264),
.CE(PHI2_N_120_enable_6), .CLK(PHI2_c), .F0(Cmdn8MEGEN_N_264),
.Q0(Cmdn8MEGEN), .F1(n1314));
SLICE_25 SLICE_25( .C1(Din_c_3), .B1(Din_c_5), .A1(nFWE_c), .A0(nFWE_c),
.DI0(n2373), .M1(nCCAS_N_3), .CLK(nCRAS_c), .F0(n2373), .Q0(FWEr),
.F1(n2180), .Q1(CBR));
SLICE_26 SLICE_26( .DI0(\n2447\000/BUF1 ), .CE(RCLK_c_enable_28),
.CLK(RCLK_c), .F0(\n2447\000/BUF1 ), .Q0(InitReady));
SLICE_27 SLICE_27( .DI0(n2447), .CE(RCLK_c_enable_16), .CLK(RCLK_c),
.F0(n2447), .Q0(LEDEN));
SLICE_30 SLICE_30( .C1(CBR), .B1(LEDEN), .A1(nCRAS_c), .A0(nCRAS_c),
.DI0(nCRAS_c__inv), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c__inv), .Q0(RASr),
.F1(LED_c), .Q1(RASr2));
SLICE_32 SLICE_32( .C1(nRowColSel_N_35), .B1(InitReady), .A1(RASr2),
.D0(nRCAS_N_165), .C0(Ready), .B0(n2381), .A0(nRCS_N_139), .DI0(n2036),
.LSR(nRWE_N_177), .CLK(RCLK_c), .F0(n2036), .Q0(RA_0), .F1(n2381));
SLICE_33 SLICE_33( .C1(Din_c_4), .B1(Din_c_7), .A1(Din_c_6), .C0(n8MEGEN),
.B0(XOR8MEG), .A0(Din_c_6), .DI0(RA11_N_184), .LSR(Ready), .CLK(PHI2_c),
.F0(RA11_N_184), .Q0(RA_c), .F1(n6_adj_2));
SLICE_35 SLICE_35( .D1(InitReady), .C1(CmdSubmitted), .B1(PHI2r2),
.A1(PHI2r3), .C0(Ready), .B0(n15_adj_4), .A0(InitReady),
.DI0(RCKEEN_N_121), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(RCKEEN_N_121),
.Q0(RCKEEN), .F1(RCLK_c_enable_10));
SLICE_36 SLICE_36( .D0(RASr3), .C0(RASr2), .B0(RCKEEN), .A0(RASr),
.DI0(RCKE_N_132), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKE_N_132), .Q0(RCKE_c),
.Q1(PHI2r2));
SLICE_37 SLICE_37( .DI0(\n2447\002/BUF1 ), .CE(Ready_N_292), .CLK(RCLK_c),
.F0(\n2447\002/BUF1 ), .Q0(Ready));
SLICE_44 SLICE_44( .D1(FS_1), .C1(n2267), .B1(n13_adj_6), .A1(FS_4),
.C0(InitReady), .B0(CmdUFMCLK), .A0(n1893), .DI0(UFMCLK_N_224),
.CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMCLK_N_224),
.Q0(UFMCLK_c), .F1(n1893));
SLICE_45 SLICE_45( .D1(n10), .C1(FS_10), .B1(FS_8), .A1(n7), .D0(n4),
.C0(InitReady), .B0(CmdUFMSDI), .A0(n2174), .DI0(UFMSDI_N_231),
.CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMSDI_N_231),
.Q0(UFMSDI_c), .F1(n2174));
SLICE_50 SLICE_50( .D1(LEDEN), .C1(n1314), .B1(Din_c_1), .A1(Din_c_4),
.D0(Din_c_3), .C0(n2260), .B0(Din_c_2), .A0(Din_c_0), .DI0(XOR8MEG_N_110),
.CE(PHI2_N_120_enable_3), .CLK(PHI2_c), .F0(XOR8MEG_N_110), .Q0(XOR8MEG),
.F1(n2260));
SLICE_57 SLICE_57( .D1(FS_10), .C1(FS_11), .B1(n2375), .A1(n10),
.D0(Cmdn8MEGEN), .C0(UFMSDO_c), .B0(n2367), .A0(InitReady),
.DI0(n8MEGEN_N_91), .CE(RCLK_c_enable_15), .CLK(RCLK_c), .F0(n8MEGEN_N_91),
.Q0(n8MEGEN), .F1(n2367));
SLICE_59 SLICE_59( .D1(CBR), .C1(nRowColSel_N_35), .B1(RASr2),
.A1(nRCS_N_142), .D0(nRCAS_N_166), .C0(Ready), .B0(nRCAS_N_165),
.A0(n2371), .DI0(nRCAS_N_161), .CE(RCLK_c_enable_6), .CLK(RCLK_c),
.F0(nRCAS_N_161), .Q0(nRCAS_c), .F1(nRCAS_N_166));
SLICE_61 SLICE_61( .D1(nRCS_N_142), .C1(nRowColSel_N_35), .B1(RASr2),
.A1(RCKE_c), .C0(Ready), .B0(nRCS_N_141), .A0(nRCS_N_137),
.DI0(nRCS_N_136), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(nRCS_N_136),
.Q0(nRCS_c), .F1(nRCS_N_141));
SLICE_62 SLICE_62( .D1(RASr2), .C1(nRowColSel_N_35), .B1(InitReady),
.A1(nRCS_N_139), .D0(nRowColSel_N_35), .C0(Ready), .B0(n2379),
.A0(nRCS_N_137), .DI0(nRRAS_N_156), .CE(RCLK_c_enable_6), .CLK(RCLK_c),
.F0(nRRAS_N_156), .Q0(nRRAS_c), .F1(nRCS_N_137));
SLICE_64 SLICE_64( .B1(nRCAS_N_165), .A1(nRWE_N_177), .D0(n2371), .C0(Ready),
.B0(nRWE_N_178), .A0(n1765), .DI0(nRWE_N_171), .CE(RCLK_c_enable_5),
.CLK(RCLK_c), .F0(nRWE_N_171), .Q0(nRWE_c), .F1(n1765));
SLICE_65 SLICE_65( .B1(nRowColSel_N_34), .A1(nRowColSel_N_33), .D0(n2376),
.C0(n1060), .B0(n2372), .A0(FWEr), .DI0(n917), .CE(RCLK_c_enable_5),
.CLK(RCLK_c), .F0(n917), .Q0(nRowColSel), .F1(n1060));
SLICE_66 SLICE_66( .B1(CASr2), .A1(nRowColSel_N_33), .B0(nRowColSel_N_32),
.A0(nRowColSel_N_33), .DI0(n827), .LSR(RASr2), .CLK(RCLK_c), .F0(n827),
.Q0(nRowColSel_N_32), .F1(n2227));
SLICE_67 SLICE_67( .B0(nRowColSel_N_32), .A0(RASr2), .DI0(n1406),
.LSR(nRowColSel_N_34), .CLK(RCLK_c), .F0(n1406), .Q0(nRowColSel_N_33));
SLICE_68 SLICE_68( .B1(FS_0), .A1(FS_8), .B0(Bank_3), .A0(Bank_6),
.M0(n1406), .LSR(nRowColSel_N_35), .CLK(RCLK_c), .F0(n2287),
.Q0(nRowColSel_N_34), .F1(n13));
SLICE_69 SLICE_69( .B1(RASr2), .A1(RCKE_c), .A0(RASr2), .DI0(n2374),
.M1(PHI2r2), .CLK(RCLK_c), .F0(n2374), .Q0(nRowColSel_N_35), .F1(n2379),
.Q1(PHI2r3));
SLICE_70 SLICE_70( .D1(FS_10), .C1(InitReady), .B1(n2368), .A1(FS_11),
.D0(InitReady), .C0(CmdUFMCS), .B0(n64), .A0(n13_adj_6),
.DI0(nUFMCS_N_199), .CE(RCLK_c_enable_10), .CLK(RCLK_c), .F0(nUFMCS_N_199),
.Q0(nUFMCS_c), .F1(n64));
i30_SLICE_71 \i30/SLICE_71 ( .C1(RASr2), .B1(FWEr), .A1(CBR),
.D0(nRowColSel_N_34), .C0(FWEr), .B0(n2227), .A0(CBR),
.M0(nRowColSel_N_35), .OFX0(n15_adj_4));
SLICE_72 SLICE_72( .D1(Ready), .C1(nRowColSel_N_32), .B1(n6_adj_3),
.A1(RASr2), .B0(Ready_N_296), .A0(InitReady), .F0(n6_adj_3),
.F1(Ready_N_292));
SLICE_73 SLICE_73( .D1(n2204), .C1(n2180), .B1(n26), .A1(n2369),
.D0(n6_adj_2), .C0(CmdEnable), .B0(MAin_c_0), .A0(MAin_c_1), .F0(n2204),
.F1(PHI2_N_120_enable_8));
SLICE_74 SLICE_74( .D1(Bank_5), .C1(n2287), .B1(n2277), .A1(Bank_2),
.D0(nFWE_c), .C0(n2204), .B0(n26), .A0(n2369), .M1(MAin_c_1),
.M0(MAin_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n2220), .Q0(RowA_0),
.F1(n26), .Q1(RowA_1));
SLICE_75 SLICE_75( .D1(n2370), .C1(n2183), .B1(n2228), .A1(Din_c_5),
.B0(Din_c_3), .A0(Din_c_6), .M1(n732), .M0(n733), .CE(RCLK_c_enable_27),
.CLK(RCLK_c), .F0(n2183), .Q0(n732), .F1(n2055), .Q1(nRWE_N_177));
SLICE_76 SLICE_76( .C1(n10), .B1(FS_14), .A1(FS_12), .D0(InitReady),
.C0(n2368), .B0(FS_11), .A0(FS_10), .M1(MAin_c_9), .M0(MAin_c_8),
.LSR(Ready), .CLK(nCRAS_c), .F0(RCLK_c_enable_16), .Q0(RowA_8), .F1(n2368),
.Q1(RowA_9));
SLICE_77 SLICE_77( .D1(n2208), .C1(C1Submitted), .B1(n2191), .A1(Din_c_5),
.D0(MAin_c_0), .C0(Din_c_6), .B0(Din_c_3), .A0(Din_c_2), .F0(n2191),
.F1(n2210));
SLICE_78 SLICE_78( .D1(nRowColSel_N_35), .C1(nRWE_N_182), .B1(n1060),
.A1(nRCS_N_146), .B0(RASr2), .A0(RCKE_c), .M1(n728), .M0(n729),
.CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRWE_N_182), .Q0(n728),
.F1(nRWE_N_178), .Q1(n727));
SLICE_79 SLICE_79( .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2), .D0(MAin_c_1),
.C0(nFWE_c), .B0(n26), .A0(n2369), .M1(n730), .M0(nRWE_N_177),
.CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(PHI2_N_120_enable_2), .Q0(n730),
.F1(n2369), .Q1(n729));
SLICE_80 SLICE_80( .B1(FS_14), .A1(FS_12), .D0(FS_11), .C0(InitReady),
.B0(n2375), .A0(n10), .F0(n2366), .F1(n2375));
SLICE_81 SLICE_81( .B1(CBR), .A1(FWEr), .D0(nRowColSel_N_33), .C0(n2378),
.B0(nRowColSel_N_34), .A0(nRCS_N_146), .M1(n726), .M0(n727),
.CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRCS_N_142), .Q0(n726),
.F1(n2378), .Q1(Ready_N_296));
SLICE_82 SLICE_82( .D1(FS_17), .C1(FS_14), .B1(n12), .A1(FS_11),
.B0(n13_adj_6), .A0(FS_10), .M1(MAin_c_5), .M0(MAin_c_4), .LSR(Ready),
.CLK(nCRAS_c), .F0(RCLK_c_enable_28), .Q0(RowA_4), .F1(n13_adj_6),
.Q1(RowA_5));
SLICE_83 SLICE_83( .D1(n1314), .C1(n1277), .B1(CmdEnable), .A1(n2228),
.D0(MAin_c_1), .C0(MAin_c_0), .B0(n26), .A0(n2369), .F0(n1277),
.F1(PHI2_N_120_enable_3));
SLICE_84 SLICE_84( .C1(CmdSubmitted), .B1(PHI2r2), .A1(PHI2r3),
.D0(n4_adj_7), .C0(InitReady), .B0(n2377), .A0(n2367), .M1(n738),
.M0(nRCAS_N_165), .CE(RCLK_c_enable_27), .CLK(RCLK_c),
.F0(RCLK_c_enable_15), .Q0(n738), .F1(n2377), .Q1(n737));
SLICE_85 SLICE_85( .D1(n10), .C1(FS_11), .B1(FS_14), .A1(FS_12), .D0(FS_16),
.C0(FS_15), .B0(FS_13), .A0(FS_17), .F0(n10), .F1(n2267));
SLICE_86 SLICE_86( .C1(FS_6), .B1(FS_9), .A1(FS_3), .D0(n14), .C0(n13),
.B0(n15), .A0(FS_4), .M1(RASr2), .M0(PHI2_c), .CLK(RCLK_c), .F0(n4_adj_7),
.Q0(PHI2r), .F1(n14), .Q1(RASr3));
SLICE_87 SLICE_87( .D1(n6), .C1(nRowColSel_N_32), .B1(nRowColSel_N_33),
.A1(nRowColSel_N_35), .B0(nRowColSel_N_34), .A0(Ready), .M1(CROW_c_1),
.M0(CROW_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n6), .Q0(RBA_c_0),
.F1(RCLK_c_enable_6), .Q1(RBA_c_1));
SLICE_88 SLICE_88( .D1(n2363), .C1(C1Submitted_N_237), .B1(ADSubmitted),
.A1(n7_adj_5), .D0(n2362), .C0(MAin_c_0), .B0(n2055), .A0(Din_c_2),
.M1(Din_c_7), .M0(Din_c_6), .CLK(nCCAS_c), .F0(C1Submitted_N_237),
.Q0(WRD_6), .F1(PHI2_N_120_enable_1), .Q1(WRD_7));
SLICE_89 SLICE_89( .D1(Din_c_5), .C1(Din_c_3), .B1(Din_c_4), .A1(n2220),
.D0(Din_c_3), .C0(Din_c_4), .B0(n2220), .A0(Din_c_5), .M1(Din_c_5),
.M0(Din_c_4), .CLK(nCCAS_c), .F0(PHI2_N_120_enable_6), .Q0(WRD_4),
.F1(PHI2_N_120_enable_7), .Q1(WRD_5));
SLICE_90 SLICE_90( .D1(Din_c_0), .C1(Din_c_4), .B1(Din_c_1), .A1(Din_c_7),
.C0(Din_c_0), .B0(Din_c_1), .A0(Din_c_7), .M1(Din_c_1), .M0(Din_c_0),
.CLK(nCCAS_c), .F0(n2370), .Q0(WRD_0), .F1(n2208), .Q1(WRD_1));
SLICE_91 SLICE_91( .C1(MAin_c_1), .B1(n26), .A1(n2369), .D0(MAin_c_1),
.C0(MAin_c_0), .B0(n26), .A0(n2369), .M1(MAin_c_3), .M0(MAin_c_2),
.LSR(Ready), .CLK(nCRAS_c), .F0(n2225), .Q0(RowA_2), .F1(n2362),
.Q1(RowA_3));
SLICE_92 SLICE_92( .D1(Ready), .C1(nRowColSel_N_35), .B1(InitReady),
.A1(RASr2), .D0(nRCS_N_139), .C0(nRowColSel_N_35), .B0(InitReady),
.A0(RASr2), .M1(Din_c_3), .M0(Din_c_2), .CLK(nCCAS_c), .F0(n2371),
.Q0(WRD_2), .F1(RCLK_c_enable_27), .Q1(WRD_3));
SLICE_93 SLICE_93( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel),
.B0(MAin_c_9), .A0(RowA_9), .M1(Din_c_1), .M0(Din_c_0), .CLK(PHI2_c),
.F0(RA_1_9), .Q0(Bank_0), .F1(RDQML_c), .Q1(Bank_1));
SLICE_94 SLICE_94( .B1(nRowColSel_N_35), .A1(Ready), .D0(nRowColSel_N_35),
.C0(nRowColSel_N_32), .B0(n1060), .A0(Ready), .F0(RCLK_c_enable_5),
.F1(n2372));
SLICE_95 SLICE_95( .D1(FS_5), .C1(FS_9), .B1(FS_7), .A1(n2375), .D0(FS_2),
.C0(FS_1), .B0(FS_7), .A0(FS_5), .F0(n15), .F1(n7));
SLICE_96 SLICE_96( .B1(CASr3), .A1(CBR), .D0(CASr2), .C0(FWEr), .B0(CASr3),
.A0(CBR), .F0(nRCS_N_146), .F1(n2376));
SLICE_97 SLICE_97( .C1(MAin_c_1), .B1(n2210), .A1(MAin_c_0), .B0(Din_c_2),
.A0(MAin_c_0), .M1(n734), .M0(n735), .CE(RCLK_c_enable_27), .CLK(RCLK_c),
.F0(n2254), .Q0(n734), .F1(n7_adj_5), .Q1(n733));
SLICE_98 SLICE_98( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel),
.B0(MAin_c_8), .A0(RowA_8), .M1(nRCS_N_139), .M0(Ready_N_296),
.CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(RA_1_8), .Q0(nRCS_N_139),
.F1(RDQMH_c), .Q1(nRCAS_N_165));
SLICE_99 SLICE_99( .D1(Bank_1), .C1(Bank_4), .B1(MAin_c_3), .A1(MAin_c_7),
.C0(nRowColSel), .B0(MAin_c_7), .A0(RowA_7), .M0(Din_c_0),
.CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_7), .Q0(CmdUFMSDI),
.F1(n22));
SLICE_100 SLICE_100( .D1(Bank_0), .C1(Bank_7), .B1(MAin_c_4), .A1(MAin_c_6),
.C0(nRowColSel), .B0(MAin_c_6), .A0(RowA_6), .M1(Din_c_2), .M0(Din_c_1),
.CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_6), .Q0(CmdUFMCLK),
.F1(n2277), .Q1(CmdUFMCS));
SLICE_101 SLICE_101( .C1(nRowColSel), .B1(MAin_c_0), .A1(RowA_0),
.C0(nRowColSel), .B0(MAin_c_5), .A0(RowA_5), .M1(Din_c_7), .M0(Din_c_6),
.CLK(PHI2_c), .F0(RA_1_5), .Q0(Bank_6), .F1(RA_1_0), .Q1(Bank_7));
SLICE_102 SLICE_102( .C1(nRowColSel), .B1(MAin_c_1), .A1(RowA_1),
.C0(nRowColSel), .B0(MAin_c_4), .A0(RowA_4), .M1(Din_c_5), .M0(Din_c_4),
.CLK(PHI2_c), .F0(RA_1_4), .Q0(Bank_4), .F1(RA_1_1), .Q1(Bank_5));
SLICE_103 SLICE_103( .C1(nRowColSel), .B1(MAin_c_2), .A1(RowA_2),
.C0(nRowColSel), .B0(MAin_c_3), .A0(RowA_3), .M1(Din_c_3), .M0(Din_c_2),
.CLK(PHI2_c), .F0(RA_1_3), .Q0(Bank_2), .F1(RA_1_2), .Q1(Bank_3));
SLICE_104 SLICE_104( .B1(nFWE_c), .A1(nCCAS_c), .C0(nFWE_c), .B0(n26),
.A0(n2369), .M1(MAin_c_7), .M0(MAin_c_6), .LSR(Ready), .CLK(nCRAS_c),
.F0(n2363), .Q0(RowA_6), .F1(n984), .Q1(RowA_7));
SLICE_105 SLICE_105( .B1(FS_6), .A1(FS_11), .D0(FS_16), .C0(FS_15),
.B0(FS_12), .A0(FS_13), .F0(n12), .F1(n4));
SLICE_106 SLICE_106( .B1(Din_c_2), .A1(Din_c_0), .B0(Din_c_4), .A0(nFWE_c),
.M1(n736), .M0(n737), .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(n2228),
.Q0(n736), .F1(n2382), .Q1(n735));
RD_7_ \RD[7]_I ( .PADDI(Dout_c), .PADDT(n984), .PADDO(WRD_7), .RD7(RD[7]));
RD_6_ \RD[6]_I ( .PADDI(Dout_0), .PADDT(n984), .PADDO(WRD_6), .RD6(RD[6]));
RD_5_ \RD[5]_I ( .PADDI(Dout_1), .PADDT(n984), .PADDO(WRD_5), .RD5(RD[5]));
RD_4_ \RD[4]_I ( .PADDI(Dout_2), .PADDT(n984), .PADDO(WRD_4), .RD4(RD[4]));
RD_3_ \RD[3]_I ( .PADDI(Dout_3), .PADDT(n984), .PADDO(WRD_3), .RD3(RD[3]));
RD_2_ \RD[2]_I ( .PADDI(Dout_4), .PADDT(n984), .PADDO(WRD_2), .RD2(RD[2]));
RD_1_ \RD[1]_I ( .PADDI(Dout_5), .PADDT(n984), .PADDO(WRD_1), .RD1(RD[1]));
RD_0_ \RD[0]_I ( .PADDI(Dout_6), .PADDT(n984), .PADDO(WRD_0), .RD0(RD[0]));
Dout_7_ \Dout[7]_I ( .PADDO(Dout_c), .Dout7(Dout[7]));
Dout_6_ \Dout[6]_I ( .PADDO(Dout_0), .Dout6(Dout[6]));
Dout_5_ \Dout[5]_I ( .PADDO(Dout_1), .Dout5(Dout[5]));
Dout_4_ \Dout[4]_I ( .PADDO(Dout_2), .Dout4(Dout[4]));
Dout_3_ \Dout[3]_I ( .PADDO(Dout_3), .Dout3(Dout[3]));
Dout_2_ \Dout[2]_I ( .PADDO(Dout_4), .Dout2(Dout[2]));
Dout_1_ \Dout[1]_I ( .PADDO(Dout_5), .Dout1(Dout[1]));
Dout_0_ \Dout[0]_I ( .PADDO(Dout_6), .Dout0(Dout[0]));
LED LED_I( .PADDO(LED_c), .LED(LED));
RBA_1_ \RBA[1]_I ( .PADDO(RBA_c_1), .RBA1(RBA[1]));
RBA_0_ \RBA[0]_I ( .PADDO(RBA_c_0), .RBA0(RBA[0]));
RA_11_ \RA[11]_I ( .PADDO(RA_c), .RA11(RA[11]));
RA_10_ \RA[10]_I ( .PADDO(RA_0), .RA10(RA[10]));
RA_9_ \RA[9]_I ( .PADDO(RA_1_9), .RA9(RA[9]));
RA_8_ \RA[8]_I ( .PADDO(RA_1_8), .RA8(RA[8]));
RA_7_ \RA[7]_I ( .PADDO(RA_1_7), .RA7(RA[7]));
RA_6_ \RA[6]_I ( .PADDO(RA_1_6), .RA6(RA[6]));
RA_5_ \RA[5]_I ( .PADDO(RA_1_5), .RA5(RA[5]));
RA_4_ \RA[4]_I ( .PADDO(RA_1_4), .RA4(RA[4]));
RA_3_ \RA[3]_I ( .PADDO(RA_1_3), .RA3(RA[3]));
RA_2_ \RA[2]_I ( .PADDO(RA_1_2), .RA2(RA[2]));
RA_1_ \RA[1]_I ( .PADDO(RA_1_1), .RA1(RA[1]));
RA_0_ \RA[0]_I ( .PADDO(RA_1_0), .RA0(RA[0]));
nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS));
RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE));
nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS));
nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS));
RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS));
UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK));
UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI));
PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
MAin_9_ \MAin[9]_I ( .PADDI(MAin_c_9), .MAin9(MAin[9]));
MAin_8_ \MAin[8]_I ( .PADDI(MAin_c_8), .MAin8(MAin[8]));
MAin_7_ \MAin[7]_I ( .PADDI(MAin_c_7), .MAin7(MAin[7]));
MAin_6_ \MAin[6]_I ( .PADDI(MAin_c_6), .MAin6(MAin[6]));
MAin_5_ \MAin[5]_I ( .PADDI(MAin_c_5), .MAin5(MAin[5]));
MAin_4_ \MAin[4]_I ( .PADDI(MAin_c_4), .MAin4(MAin[4]));
MAin_3_ \MAin[3]_I ( .PADDI(MAin_c_3), .MAin3(MAin[3]));
MAin_2_ \MAin[2]_I ( .PADDI(MAin_c_2), .MAin2(MAin[2]));
MAin_1_ \MAin[1]_I ( .PADDI(MAin_c_1), .MAin1(MAin[1]));
MAin_0_ \MAin[0]_I ( .PADDI(MAin_c_0), .MAin0(MAin[0]));
CROW_1_ \CROW[1]_I ( .PADDI(CROW_c_1), .CROW1(CROW[1]));
CROW_0_ \CROW[0]_I ( .PADDI(CROW_c_0), .CROW0(CROW[0]));
Din_7_ \Din[7]_I ( .PADDI(Din_c_7), .Din7(Din[7]));
Din_6_ \Din[6]_I ( .PADDI(Din_c_6), .Din6(Din[6]));
Din_5_ \Din[5]_I ( .PADDI(Din_c_5), .Din5(Din[5]));
Din_4_ \Din[4]_I ( .PADDI(Din_c_4), .Din4(Din[4]));
Din_3_ \Din[3]_I ( .PADDI(Din_c_3), .Din3(Din[3]));
Din_2_ \Din[2]_I ( .PADDI(Din_c_2), .Din2(Din[2]));
Din_1_ \Din[1]_I ( .PADDI(Din_c_1), .Din1(Din[1]));
Din_0_ \Din[0]_I ( .PADDI(Din_c_0), .Din0(Din[0]));
nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
VHI VHI_INST( .Z(VCCI));
PUR PUR_INST( .PUR(VCCI));
GSR GSR_INST( .GSR(VCCI));
endmodule
module SLICE_0 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre FS_610__i14( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre FS_610__i13( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 FS_610_add_4_15( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
module vcc ( output PWR1 );
VHI INST1( .Z(PWR1));
endmodule
module gnd ( output PWR0 );
VLO INST1( .Z(PWR0));
endmodule
module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
defparam inst1.INIT0 = 16'hfaaa;
defparam inst1.INIT1 = 16'hfaaa;
defparam inst1.INJECT1_0 = "NO";
defparam inst1.INJECT1_1 = "NO";
endmodule
module SLICE_1 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre FS_610__i12( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre FS_610__i11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 FS_610_add_4_13( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre FS_610__i8( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre FS_610__i7( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 FS_610_add_4_9( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre FS_610__i6( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre FS_610__i5( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 FS_610_add_4_7( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre FS_610__i2( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre FS_610__i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 FS_610_add_4_3( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_5 ( input A1, DI1, M0, CLK, output Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, M0_dly;
vmuxregsre FS_610__i0( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CASr3_384( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu20001 FS_610_add_4_1( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
defparam inst1.INIT0 = 16'hF000;
defparam inst1.INIT1 = 16'h0555;
defparam inst1.INJECT1_0 = "NO";
defparam inst1.INJECT1_1 = "NO";
endmodule
module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre FS_610__i10( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre FS_610__i9( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 FS_610_add_4_11( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_7 ( input A0, DI0, CLK, FCI, output F0, Q0 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
vmuxregsre FS_610__i17( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
ccu20002 FS_610_add_4_19( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI),
.A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(),
.CO1());
specify
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
defparam inst1.INIT0 = 16'hfaaa;
defparam inst1.INIT1 = 16'h0000;
defparam inst1.INJECT1_0 = "NO";
defparam inst1.INJECT1_1 = "NO";
endmodule
module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre FS_610__i4( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre FS_610__i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 FS_610_add_4_5( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre FS_610__i16( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre FS_610__i15( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 FS_610_add_4_17( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_10 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
output F0, Q0, F1 );
wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly;
lut4 i3_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40003 i1_4_lut_adj_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0004 ADSubmitted_407( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
.SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
endspecify
endmodule
module lut4 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40003 ( input A, B, C, D, output Z );
ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q );
FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
module inverter ( input I, output Z );
INV INST1( .A(I), .Z(Z));
endmodule
module SLICE_15 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output
F0, Q0, F1 );
wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly;
lut40005 i13_2_lut_rep_16_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40006 i1110_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0007 C1Submitted_406( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
.SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
endspecify
endmodule
module lut40005 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40006 ( input A, B, C, D, output Z );
ROM16X1A #(16'hE0F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q );
FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
module SLICE_16 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
lut40008 i2045( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CASr2_383( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre CASr_382( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40008 ( input A, B, C, D, output Z );
ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_19 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
F0, Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
lut40009 i26_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40010 i2_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CmdEnable_405( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
module lut40009 ( input A, B, C, D, output Z );
ROM16X1A #(16'hC0CA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40010 ( input A, B, C, D, output Z );
ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_20 ( input DI0, CE, CLK, output F0, Q0 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
lut40011 \n2447\001/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI),
.Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdSubmitted_411( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
module lut40011 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
lut40012 i1_2_lut_3_lut_adj_15( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40013 Cmdn8MEGEN_I_93_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre Cmdn8MEGEN_410( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
module lut40012 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40013 ( input A, B, C, D, output Z );
ROM16X1A #(16'hCC5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_25 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly;
lut40014 i2_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40008 i2_1_lut_rep_24( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre CBR_390( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre FWEr_389( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
endspecify
endmodule
module lut40014 ( input A, B, C, D, output Z );
ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_26 ( input DI0, CE, CLK, output F0, Q0 );
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
lut40011 \n2447\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI),
.Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre InitReady_394( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_27 ( input DI0, CE, CLK, output F0, Q0 );
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
lut40011 m1_lut( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre LEDEN_419( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_30 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
lut40015 i2010_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40008 i2044( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre RASr2_380( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre RASr_379( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40015 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_32 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0,
Q0, F1 );
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
lut40016 i2_3_lut_rep_32( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40017 i2_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0007 RA10_400( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40016 ( input A, B, C, D, output Z );
ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40017 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
lut40018 i1_2_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40019 RA11_I_54_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre0004 RA11_385( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40018 ( input A, B, C, D, output Z );
ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40019 ( input A, B, C, D, output Z );
ROM16X1A #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_35 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
lut40020 i1_2_lut_4_lut_adj_25( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40021 i29_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre RCKEEN_401( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40020 ( input A, B, C, D, output Z );
ROM16X1A #(16'h20FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40021 ( input A, B, C, D, output Z );
ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_36 ( input D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, Q1 );
wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
lut40022 i1404_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre PHI2r2_377( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre RCKE_395( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40022 ( input A, B, C, D, output Z );
ROM16X1A #(16'hCFC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_37 ( input DI0, CE, CLK, output F0, Q0 );
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
lut40011 \n2447\002/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI),
.Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre Ready_404( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_44 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output
F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
lut40023 i1970_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40021 i1603_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0004 UFMCLK_416( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40023 ( input A, B, C, D, output Z );
ROM16X1A #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
output F0, Q0, F1 );
wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
lut4 i4_4_lut_adj_17( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40024 i1589_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0004 UFMSDI_417( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40024 ( input A, B, C, D, output Z );
ROM16X1A #(16'hCAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
F0, Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
lut40025 i1962_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40026 i2_3_lut_4_lut_adj_11( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre XOR8MEG_408( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
module lut40025 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40026 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
F0, Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
lut40027 i2_3_lut_rep_18_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40028 n8MEGEN_I_14_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre n8MEGEN_418( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40027 ( input A, B, C, D, output Z );
ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40028 ( input A, B, C, D, output Z );
ROM16X1A #(16'hBF04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
F0, Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
lut40029 nRCAS_I_43_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40030 nRCAS_I_0_452_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0031 nRCAS_398( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40029 ( input A, B, C, D, output Z );
ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40030 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFE0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module vmuxregsre0031 ( input D0, D1, SD, SP, CK, LSR, output Q );
FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
module SLICE_61 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
lut40032 nRCS_I_31_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40021 nRCS_I_0_448_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0031 nRCS_396( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40032 ( input A, B, C, D, output Z );
ROM16X1A #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
F0, Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
lut40033 i3_4_lut_adj_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40029 nRCS_N_137_I_0_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0031 nRRAS_397( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40033 ( input A, B, C, D, output Z );
ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_64 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
lut40034 i1477_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40035 nRWE_I_0_455_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0031 nRWE_399( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40034 ( input A, B, C, D, output Z );
ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40035 ( input A, B, C, D, output Z );
ROM16X1A #(16'hCFC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_65 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
lut40034 i786_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40036 i1432_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre nRowColSel_402( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40036 ( input A, B, C, D, output Z );
ROM16X1A #(16'h3032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_66 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
lut40037 i1_2_lut_adj_23( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40034 i1439_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre0004 S_FSM_i4( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40037 ( input A, B, C, D, output Z );
ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_67 ( input B0, A0, DI0, LSR, CLK, output F0, Q0 );
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
lut40038 i1_2_lut_adj_10( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0004 S_FSM_i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
specify
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40038 ( input A, B, C, D, output Z );
ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_68 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly;
lut40034 i4_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40039 i1989_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre0004 S_FSM_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40039 ( input A, B, C, D, output Z );
ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_69 ( input B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
lut40034 i1491_2_lut_rep_30( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40008 RASr2_I_0_1_lut_rep_25( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI),
.Z(F0));
vmuxregsre PHI2r3_378( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre S_FSM_i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
F0, Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
lut40040 i1_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40041 i1448_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0031 nUFMCS_415( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40040 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40041 ( input A, B, C, D, output Z );
ROM16X1A #(16'h3FBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module i30_SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 );
wire GNDI, \i30/SLICE_71/i30/SLICE_71_K1_H1 , \i30/SLICE_71/i30/GATE_H0 ;
lut40042 \i30/SLICE_71_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI),
.Z(\i30/SLICE_71/i30/SLICE_71_K1_H1 ));
gnd DRIVEGND( .PWR0(GNDI));
lut40043 \i30/GATE ( .A(A0), .B(B0), .C(C0), .D(D0),
.Z(\i30/SLICE_71/i30/GATE_H0 ));
selmux2 \i30/SLICE_71_K0K1MUX ( .D0(\i30/SLICE_71/i30/GATE_H0 ),
.D1(\i30/SLICE_71/i30/SLICE_71_K1_H1 ), .SD(M0), .Z(OFX0));
specify
(C1 => OFX0) = (0:0:0,0:0:0);
(B1 => OFX0) = (0:0:0,0:0:0);
(A1 => OFX0) = (0:0:0,0:0:0);
(D0 => OFX0) = (0:0:0,0:0:0);
(C0 => OFX0) = (0:0:0,0:0:0);
(B0 => OFX0) = (0:0:0,0:0:0);
(A0 => OFX0) = (0:0:0,0:0:0);
(M0 => OFX0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40042 ( input A, B, C, D, output Z );
ROM16X1A #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40043 ( input A, B, C, D, output Z );
ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module selmux2 ( input D0, D1, SD, output Z );
MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
endmodule
module SLICE_72 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
wire GNDI;
lut40044 i1_4_lut_4_lut_adj_12( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40039 i2_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40044 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40003 i2_3_lut_4_lut_adj_14( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40010 i4_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK,
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
lut40033 i12_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40045 i1_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0004 RowA_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
vmuxregsre0004 RowA_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
endspecify
endmodule
module lut40045 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_75 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly;
lut40027 i3_4_lut_adj_18( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40038 i1_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre IS_FSM__i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre IS_FSM__i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_76 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output
F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
lut40012 i1_2_lut_rep_19_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40026 i1_2_lut_rep_15_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0007 RowA_i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
vmuxregsre0004 RowA_i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
endspecify
endmodule
module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40046 i3_4_lut_adj_22( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40046 i3_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40046 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_78 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly;
lut40047 nRCS_N_146_bdd_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40048 i1423_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre IS_FSM__i13( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre IS_FSM__i12( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40047 ( input A, B, C, D, output Z );
ROM16X1A #(16'hF0DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40048 ( input A, B, C, D, output Z );
ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0,
Q0, F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly;
lut40016 i11_3_lut_rep_20( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40049 MAin_c_0_bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre IS_FSM__i11( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre IS_FSM__i10( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40049 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
lut40034 i3_2_lut_rep_26( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40050 i2005_3_lut_rep_17_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40050 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_81 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly;
lut40034 i1_2_lut_rep_29( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40051 i1427_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre IS_FSM__i15( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre IS_FSM__i14( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40051 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFCDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0,
Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
lut40052 i6_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40039 i1_2_lut_adj_3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0007 RowA_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
vmuxregsre0004 RowA_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
endspecify
endmodule
module lut40052 ( input A, B, C, D, output Z );
ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40053 i2_4_lut_adj_21( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40054 i2_3_lut_4_lut_adj_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40053 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40054 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_84 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0,
Q0, F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly;
lut40055 i2_3_lut_rep_28( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40024 i1573_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre IS_FSM__i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre IS_FSM__i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40055 ( input A, B, C, D, output Z );
ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40056 i1969_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40040 i3_4_lut_adj_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40056 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_86 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
lut40012 i5_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut4 i1_4_lut_adj_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre RASr3_381( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre PHI2r_376( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_87 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0,
Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
lut40040 i4_4_lut_adj_16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40048 i1_2_lut_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0004 RBA__i2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
vmuxregsre0004 RBA__i1( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
endspecify
endmodule
module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0,
Q0, F1, Q1 );
wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
lut40057 i34_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40053 i1_4_lut_adj_13( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre WRD_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre WRD_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
endspecify
endmodule
module lut40057 ( input A, B, C, D, output Z );
ROM16X1A #(16'hC0C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0,
Q0, F1, Q1 );
wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
lut40058 i2_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40059 i1_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre WRD_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre WRD_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
endspecify
endmodule
module lut40058 ( input A, B, C, D, output Z );
ROM16X1A #(16'h8088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40059 ( input A, B, C, D, output Z );
ROM16X1A #(16'hC444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
lut40049 i1_2_lut_3_lut_4_lut_adj_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40055 i1_2_lut_rep_21_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre WRD_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre WRD_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
endspecify
endmodule
module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output
F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
lut40060 i1_2_lut_rep_13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40061 i1_2_lut_3_lut_4_lut_adj_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0004 RowA_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
vmuxregsre0004 RowA_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
endspecify
endmodule
module lut40060 ( input A, B, C, D, output Z );
ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40061 ( input A, B, C, D, output Z );
ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0,
Q0, F1, Q1 );
wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
lut40062 i2008_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40005 i1_2_lut_rep_22_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre WRD_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre WRD_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
endspecify
endmodule
module lut40062 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_93 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
lut40063 i2001_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40021 MAin_9__I_0_427_i10_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre Bank_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre Bank_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40063 ( input A, B, C, D, output Z );
ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
lut40048 i771_2_lut_rep_23_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40064 i2_3_lut_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40064 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40065 i2_4_lut_adj_20( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40040 i6_4_lut_adj_9( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40065 ( input A, B, C, D, output Z );
ROM16X1A #(16'h1404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
lut40034 i1_2_lut_rep_27( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40027 i2_3_lut_4_lut_adj_24( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module SLICE_97 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1,
Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly;
lut40066 i13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40034 i1956_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre IS_FSM__i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre IS_FSM__i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40066 ( input A, B, C, D, output Z );
ROM16X1A #(16'hC5C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_98 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1,
Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly;
lut40037 i1416_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40021 MAin_9__I_0_427_i9_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre IS_FSM__i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre IS_FSM__i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_99 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
lut40052 i8_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40021 MAin_9__I_0_427_i8_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdUFMSDI_414( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
module SLICE_100 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output
F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly;
lut40052 i1979_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40021 MAin_9__I_0_427_i7_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdUFMCS_412( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre CmdUFMCLK_413( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
module SLICE_101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
lut40021 MAin_9__I_0_427_i1_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40021 MAin_9__I_0_427_i6_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre Bank_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre Bank_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_102 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
lut40021 MAin_9__I_0_427_i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40021 MAin_9__I_0_427_i5_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre Bank_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre Bank_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_103 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
lut40021 MAin_9__I_0_427_i3_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40021 MAin_9__I_0_427_i4_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre Bank_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre Bank_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_104 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
lut40034 i1417_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40067 i1_2_lut_rep_14_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre0004 RowA_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
vmuxregsre0004 RowA_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
endspecify
endmodule
module lut40067 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
lut40039 i1_2_lut_adj_19( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40052 i5_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module SLICE_106 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1,
Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly;
lut40039 i1_2_lut_rep_33( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40034 i1930_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre IS_FSM__i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre IS_FSM__i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
xo2iobuf Dout_pad_7__713( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7),
.PADI(RD7));
specify
(PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD7) = (0:0:0,0:0:0);
(RD7 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD7, 0:0:0);
$width (negedge RD7, 0:0:0);
endspecify
endmodule
module xo2iobuf ( input I, T, output Z, PAD, input PADI );
IBPD INST1( .I(PADI), .O(Z));
OBZPD INST2( .I(I), .T(T), .O(PAD));
endmodule
module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );
xo2iobuf Dout_pad_6__714( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6),
.PADI(RD6));
specify
(PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD6) = (0:0:0,0:0:0);
(RD6 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD6, 0:0:0);
$width (negedge RD6, 0:0:0);
endspecify
endmodule
module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );
xo2iobuf Dout_pad_5__715( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5),
.PADI(RD5));
specify
(PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD5) = (0:0:0,0:0:0);
(RD5 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD5, 0:0:0);
$width (negedge RD5, 0:0:0);
endspecify
endmodule
module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );
xo2iobuf Dout_pad_4__716( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4),
.PADI(RD4));
specify
(PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD4) = (0:0:0,0:0:0);
(RD4 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD4, 0:0:0);
$width (negedge RD4, 0:0:0);
endspecify
endmodule
module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );
xo2iobuf Dout_pad_3__717( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3),
.PADI(RD3));
specify
(PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD3) = (0:0:0,0:0:0);
(RD3 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD3, 0:0:0);
$width (negedge RD3, 0:0:0);
endspecify
endmodule
module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );
xo2iobuf Dout_pad_2__718( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2),
.PADI(RD2));
specify
(PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD2) = (0:0:0,0:0:0);
(RD2 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD2, 0:0:0);
$width (negedge RD2, 0:0:0);
endspecify
endmodule
module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
xo2iobuf Dout_pad_1__719( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1),
.PADI(RD1));
specify
(PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD1) = (0:0:0,0:0:0);
(RD1 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD1, 0:0:0);
$width (negedge RD1, 0:0:0);
endspecify
endmodule
module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
xo2iobuf Dout_pad_0__720( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0),
.PADI(RD0));
specify
(PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD0) = (0:0:0,0:0:0);
(RD0 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD0, 0:0:0);
$width (negedge RD0, 0:0:0);
endspecify
endmodule
module Dout_7_ ( input PADDO, output Dout7 );
wire GNDI;
xo2iobuf0068 Dout_pad_7( .I(PADDO), .T(GNDI), .PAD(Dout7));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => Dout7) = (0:0:0,0:0:0);
endspecify
endmodule
module xo2iobuf0068 ( input I, T, output PAD );
OBZPD INST5( .I(I), .T(T), .O(PAD));
endmodule
module Dout_6_ ( input PADDO, output Dout6 );
wire GNDI;
xo2iobuf0068 Dout_pad_6( .I(PADDO), .T(GNDI), .PAD(Dout6));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => Dout6) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_5_ ( input PADDO, output Dout5 );
wire GNDI;
xo2iobuf0068 Dout_pad_5( .I(PADDO), .T(GNDI), .PAD(Dout5));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => Dout5) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_4_ ( input PADDO, output Dout4 );
wire GNDI;
xo2iobuf0068 Dout_pad_4( .I(PADDO), .T(GNDI), .PAD(Dout4));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => Dout4) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_3_ ( input PADDO, output Dout3 );
wire GNDI;
xo2iobuf0068 Dout_pad_3( .I(PADDO), .T(GNDI), .PAD(Dout3));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => Dout3) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_2_ ( input PADDO, output Dout2 );
wire GNDI;
xo2iobuf0068 Dout_pad_2( .I(PADDO), .T(GNDI), .PAD(Dout2));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => Dout2) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_1_ ( input PADDO, output Dout1 );
wire GNDI;
xo2iobuf0068 Dout_pad_1( .I(PADDO), .T(GNDI), .PAD(Dout1));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => Dout1) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_0_ ( input PADDO, output Dout0 );
wire GNDI;
xo2iobuf0068 Dout_pad_0( .I(PADDO), .T(GNDI), .PAD(Dout0));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => Dout0) = (0:0:0,0:0:0);
endspecify
endmodule
module LED ( input PADDO, output LED );
wire GNDI;
xo2iobuf0068 LED_pad( .I(PADDO), .T(GNDI), .PAD(LED));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => LED) = (0:0:0,0:0:0);
endspecify
endmodule
module RBA_1_ ( input PADDO, output RBA1 );
wire GNDI;
xo2iobuf0068 RBA_pad_1( .I(PADDO), .T(GNDI), .PAD(RBA1));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RBA1) = (0:0:0,0:0:0);
endspecify
endmodule
module RBA_0_ ( input PADDO, output RBA0 );
wire GNDI;
xo2iobuf0068 RBA_pad_0( .I(PADDO), .T(GNDI), .PAD(RBA0));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RBA0) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_11_ ( input PADDO, output RA11 );
wire GNDI;
xo2iobuf0068 RA_pad_11( .I(PADDO), .T(GNDI), .PAD(RA11));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA11) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_10_ ( input PADDO, output RA10 );
wire GNDI;
xo2iobuf0068 RA_pad_10( .I(PADDO), .T(GNDI), .PAD(RA10));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA10) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_9_ ( input PADDO, output RA9 );
wire GNDI;
xo2iobuf0068 RA_pad_9( .I(PADDO), .T(GNDI), .PAD(RA9));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA9) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_8_ ( input PADDO, output RA8 );
wire GNDI;
xo2iobuf0068 RA_pad_8( .I(PADDO), .T(GNDI), .PAD(RA8));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA8) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_7_ ( input PADDO, output RA7 );
wire GNDI;
xo2iobuf0068 RA_pad_7( .I(PADDO), .T(GNDI), .PAD(RA7));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA7) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_6_ ( input PADDO, output RA6 );
wire GNDI;
xo2iobuf0068 RA_pad_6( .I(PADDO), .T(GNDI), .PAD(RA6));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA6) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_5_ ( input PADDO, output RA5 );
wire GNDI;
xo2iobuf0068 RA_pad_5( .I(PADDO), .T(GNDI), .PAD(RA5));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA5) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_4_ ( input PADDO, output RA4 );
wire GNDI;
xo2iobuf0068 RA_pad_4( .I(PADDO), .T(GNDI), .PAD(RA4));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA4) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_3_ ( input PADDO, output RA3 );
wire GNDI;
xo2iobuf0068 RA_pad_3( .I(PADDO), .T(GNDI), .PAD(RA3));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA3) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_2_ ( input PADDO, output RA2 );
wire GNDI;
xo2iobuf0068 RA_pad_2( .I(PADDO), .T(GNDI), .PAD(RA2));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA2) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_1_ ( input PADDO, output RA1 );
wire GNDI;
xo2iobuf0068 RA_pad_1( .I(PADDO), .T(GNDI), .PAD(RA1));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA1) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_0_ ( input PADDO, output RA0 );
wire GNDI;
xo2iobuf0068 RA_pad_0( .I(PADDO), .T(GNDI), .PAD(RA0));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RA0) = (0:0:0,0:0:0);
endspecify
endmodule
module nRCS ( input PADDO, output nRCS );
wire GNDI;
xo2iobuf0068 nRCS_pad( .I(PADDO), .T(GNDI), .PAD(nRCS));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => nRCS) = (0:0:0,0:0:0);
endspecify
endmodule
module RCKE ( input PADDO, output RCKE );
wire GNDI;
xo2iobuf0068 RCKE_pad( .I(PADDO), .T(GNDI), .PAD(RCKE));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RCKE) = (0:0:0,0:0:0);
endspecify
endmodule
module nRWE ( input PADDO, output nRWE );
wire GNDI;
xo2iobuf0068 nRWE_pad( .I(PADDO), .T(GNDI), .PAD(nRWE));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => nRWE) = (0:0:0,0:0:0);
endspecify
endmodule
module nRRAS ( input PADDO, output nRRAS );
wire GNDI;
xo2iobuf0068 nRRAS_pad( .I(PADDO), .T(GNDI), .PAD(nRRAS));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => nRRAS) = (0:0:0,0:0:0);
endspecify
endmodule
module nRCAS ( input PADDO, output nRCAS );
wire GNDI;
xo2iobuf0068 nRCAS_pad( .I(PADDO), .T(GNDI), .PAD(nRCAS));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => nRCAS) = (0:0:0,0:0:0);
endspecify
endmodule
module RDQMH ( input PADDO, output RDQMH );
wire GNDI;
xo2iobuf0068 RDQMH_pad( .I(PADDO), .T(GNDI), .PAD(RDQMH));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RDQMH) = (0:0:0,0:0:0);
endspecify
endmodule
module RDQML ( input PADDO, output RDQML );
wire GNDI;
xo2iobuf0068 RDQML_pad( .I(PADDO), .T(GNDI), .PAD(RDQML));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => RDQML) = (0:0:0,0:0:0);
endspecify
endmodule
module nUFMCS ( input PADDO, output nUFMCS );
wire GNDI;
xo2iobuf0068 nUFMCS_pad( .I(PADDO), .T(GNDI), .PAD(nUFMCS));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => nUFMCS) = (0:0:0,0:0:0);
endspecify
endmodule
module UFMCLK ( input PADDO, output UFMCLK );
wire GNDI;
xo2iobuf0068 UFMCLK_pad( .I(PADDO), .T(GNDI), .PAD(UFMCLK));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => UFMCLK) = (0:0:0,0:0:0);
endspecify
endmodule
module UFMSDI ( input PADDO, output UFMSDI );
wire GNDI;
xo2iobuf0068 UFMSDI_pad( .I(PADDO), .T(GNDI), .PAD(UFMSDI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(PADDO => UFMSDI) = (0:0:0,0:0:0);
endspecify
endmodule
module PHI2 ( output PADDI, input PHI2 );
xo2iobuf0069 PHI2_pad( .Z(PADDI), .PAD(PHI2));
specify
(PHI2 => PADDI) = (0:0:0,0:0:0);
$width (posedge PHI2, 0:0:0);
$width (negedge PHI2, 0:0:0);
endspecify
endmodule
module xo2iobuf0069 ( output Z, input PAD );
IBPD INST1( .I(PAD), .O(Z));
endmodule
module MAin_9_ ( output PADDI, input MAin9 );
xo2iobuf0069 MAin_pad_9( .Z(PADDI), .PAD(MAin9));
specify
(MAin9 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin9, 0:0:0);
$width (negedge MAin9, 0:0:0);
endspecify
endmodule
module MAin_8_ ( output PADDI, input MAin8 );
xo2iobuf0069 MAin_pad_8( .Z(PADDI), .PAD(MAin8));
specify
(MAin8 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin8, 0:0:0);
$width (negedge MAin8, 0:0:0);
endspecify
endmodule
module MAin_7_ ( output PADDI, input MAin7 );
xo2iobuf0069 MAin_pad_7( .Z(PADDI), .PAD(MAin7));
specify
(MAin7 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin7, 0:0:0);
$width (negedge MAin7, 0:0:0);
endspecify
endmodule
module MAin_6_ ( output PADDI, input MAin6 );
xo2iobuf0069 MAin_pad_6( .Z(PADDI), .PAD(MAin6));
specify
(MAin6 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin6, 0:0:0);
$width (negedge MAin6, 0:0:0);
endspecify
endmodule
module MAin_5_ ( output PADDI, input MAin5 );
xo2iobuf0069 MAin_pad_5( .Z(PADDI), .PAD(MAin5));
specify
(MAin5 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin5, 0:0:0);
$width (negedge MAin5, 0:0:0);
endspecify
endmodule
module MAin_4_ ( output PADDI, input MAin4 );
xo2iobuf0069 MAin_pad_4( .Z(PADDI), .PAD(MAin4));
specify
(MAin4 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin4, 0:0:0);
$width (negedge MAin4, 0:0:0);
endspecify
endmodule
module MAin_3_ ( output PADDI, input MAin3 );
xo2iobuf0069 MAin_pad_3( .Z(PADDI), .PAD(MAin3));
specify
(MAin3 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin3, 0:0:0);
$width (negedge MAin3, 0:0:0);
endspecify
endmodule
module MAin_2_ ( output PADDI, input MAin2 );
xo2iobuf0069 MAin_pad_2( .Z(PADDI), .PAD(MAin2));
specify
(MAin2 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin2, 0:0:0);
$width (negedge MAin2, 0:0:0);
endspecify
endmodule
module MAin_1_ ( output PADDI, input MAin1 );
xo2iobuf0069 MAin_pad_1( .Z(PADDI), .PAD(MAin1));
specify
(MAin1 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin1, 0:0:0);
$width (negedge MAin1, 0:0:0);
endspecify
endmodule
module MAin_0_ ( output PADDI, input MAin0 );
xo2iobuf0069 MAin_pad_0( .Z(PADDI), .PAD(MAin0));
specify
(MAin0 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin0, 0:0:0);
$width (negedge MAin0, 0:0:0);
endspecify
endmodule
module CROW_1_ ( output PADDI, input CROW1 );
xo2iobuf0069 CROW_pad_1( .Z(PADDI), .PAD(CROW1));
specify
(CROW1 => PADDI) = (0:0:0,0:0:0);
$width (posedge CROW1, 0:0:0);
$width (negedge CROW1, 0:0:0);
endspecify
endmodule
module CROW_0_ ( output PADDI, input CROW0 );
xo2iobuf0069 CROW_pad_0( .Z(PADDI), .PAD(CROW0));
specify
(CROW0 => PADDI) = (0:0:0,0:0:0);
$width (posedge CROW0, 0:0:0);
$width (negedge CROW0, 0:0:0);
endspecify
endmodule
module Din_7_ ( output PADDI, input Din7 );
xo2iobuf0069 Din_pad_7( .Z(PADDI), .PAD(Din7));
specify
(Din7 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din7, 0:0:0);
$width (negedge Din7, 0:0:0);
endspecify
endmodule
module Din_6_ ( output PADDI, input Din6 );
xo2iobuf0069 Din_pad_6( .Z(PADDI), .PAD(Din6));
specify
(Din6 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din6, 0:0:0);
$width (negedge Din6, 0:0:0);
endspecify
endmodule
module Din_5_ ( output PADDI, input Din5 );
xo2iobuf0069 Din_pad_5( .Z(PADDI), .PAD(Din5));
specify
(Din5 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din5, 0:0:0);
$width (negedge Din5, 0:0:0);
endspecify
endmodule
module Din_4_ ( output PADDI, input Din4 );
xo2iobuf0069 Din_pad_4( .Z(PADDI), .PAD(Din4));
specify
(Din4 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din4, 0:0:0);
$width (negedge Din4, 0:0:0);
endspecify
endmodule
module Din_3_ ( output PADDI, input Din3 );
xo2iobuf0069 Din_pad_3( .Z(PADDI), .PAD(Din3));
specify
(Din3 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din3, 0:0:0);
$width (negedge Din3, 0:0:0);
endspecify
endmodule
module Din_2_ ( output PADDI, input Din2 );
xo2iobuf0069 Din_pad_2( .Z(PADDI), .PAD(Din2));
specify
(Din2 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din2, 0:0:0);
$width (negedge Din2, 0:0:0);
endspecify
endmodule
module Din_1_ ( output PADDI, input Din1 );
xo2iobuf0069 Din_pad_1( .Z(PADDI), .PAD(Din1));
specify
(Din1 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din1, 0:0:0);
$width (negedge Din1, 0:0:0);
endspecify
endmodule
module Din_0_ ( output PADDI, input Din0 );
xo2iobuf0069 Din_pad_0( .Z(PADDI), .PAD(Din0));
specify
(Din0 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din0, 0:0:0);
$width (negedge Din0, 0:0:0);
endspecify
endmodule
module nCCAS ( output PADDI, input nCCAS );
xo2iobuf0069 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
specify
(nCCAS => PADDI) = (0:0:0,0:0:0);
$width (posedge nCCAS, 0:0:0);
$width (negedge nCCAS, 0:0:0);
endspecify
endmodule
module nCRAS ( output PADDI, input nCRAS );
xo2iobuf0069 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
specify
(nCRAS => PADDI) = (0:0:0,0:0:0);
$width (posedge nCRAS, 0:0:0);
$width (negedge nCRAS, 0:0:0);
endspecify
endmodule
module nFWE ( output PADDI, input nFWE );
xo2iobuf0069 nFWE_pad( .Z(PADDI), .PAD(nFWE));
specify
(nFWE => PADDI) = (0:0:0,0:0:0);
$width (posedge nFWE, 0:0:0);
$width (negedge nFWE, 0:0:0);
endspecify
endmodule
module RCLK ( output PADDI, input RCLK );
xo2iobuf0069 RCLK_pad( .Z(PADDI), .PAD(RCLK));
specify
(RCLK => PADDI) = (0:0:0,0:0:0);
$width (posedge RCLK, 0:0:0);
$width (negedge RCLK, 0:0:0);
endspecify
endmodule
module UFMSDO ( output PADDI, input UFMSDO );
xo2iobuf0069 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
specify
(UFMSDO => PADDI) = (0:0:0,0:0:0);
$width (posedge UFMSDO, 0:0:0);
$width (negedge UFMSDO, 0:0:0);
endspecify
endmodule
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