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357 lines
16 KiB
HTML
357 lines
16 KiB
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<HEAD><TITLE>Lattice Synthesis Timing Report</TITLE>
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<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
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--------------------------------------------------------------------------------
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Lattice Synthesis Timing Report, Version
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Tue Aug 15 05:03:20 2023
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Design: RAM2GS
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Constraint file:
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Report level: verbose report, limited to 3 items per constraint
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
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115 items scored, 112 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path violates requirements by 8.575ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i3 (from PHI2_c +)
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Destination: FD1P3AX SP CmdUFMCS_412 (to PHI2_c -)
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Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels.
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Constraint Details:
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10.811ns data_path Bank_i3 to CmdUFMCS_412 violates
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2.500ns delay constraint less
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0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
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Path Details: Bank_i3 to CmdUFMCS_412
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c)
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Route 1 e 1.220 Bank[3]
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LUT4 --- 0.390 B to Z i1982_2_lut
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Route 1 e 1.220 n2278
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LUT4 --- 0.390 C to Z i12_4_lut
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Route 1 e 1.220 n26
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LUT4 --- 0.390 B to Z i13_4_lut
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Route 8 e 1.719 n1326
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LUT4 --- 0.390 B to Z i1990_2_lut_rep_17
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Route 2 e 1.386 n2460
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LUT4 --- 0.390 C to Z i1_2_lut_4_lut
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Route 3 e 1.483 PHI2_N_120_enable_6
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--------
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10.811 (23.7% logic, 76.3% route), 6 logic levels.
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Error: The following path violates requirements by 8.575ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i3 (from PHI2_c +)
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Destination: FD1P3AX SP CmdUFMSDI_414 (to PHI2_c -)
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Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels.
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Constraint Details:
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10.811ns data_path Bank_i3 to CmdUFMSDI_414 violates
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2.500ns delay constraint less
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0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
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Path Details: Bank_i3 to CmdUFMSDI_414
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c)
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Route 1 e 1.220 Bank[3]
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LUT4 --- 0.390 B to Z i1982_2_lut
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Route 1 e 1.220 n2278
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LUT4 --- 0.390 C to Z i12_4_lut
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Route 1 e 1.220 n26
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LUT4 --- 0.390 B to Z i13_4_lut
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Route 8 e 1.719 n1326
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LUT4 --- 0.390 B to Z i1990_2_lut_rep_17
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Route 2 e 1.386 n2460
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LUT4 --- 0.390 C to Z i1_2_lut_4_lut
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Route 3 e 1.483 PHI2_N_120_enable_6
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--------
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10.811 (23.7% logic, 76.3% route), 6 logic levels.
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Error: The following path violates requirements by 8.575ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i3 (from PHI2_c +)
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Destination: FD1P3AX SP CmdUFMCLK_413 (to PHI2_c -)
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Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels.
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Constraint Details:
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10.811ns data_path Bank_i3 to CmdUFMCLK_413 violates
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2.500ns delay constraint less
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0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
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Path Details: Bank_i3 to CmdUFMCLK_413
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c)
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Route 1 e 1.220 Bank[3]
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LUT4 --- 0.390 B to Z i1982_2_lut
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Route 1 e 1.220 n2278
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LUT4 --- 0.390 C to Z i12_4_lut
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Route 1 e 1.220 n26
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LUT4 --- 0.390 B to Z i13_4_lut
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Route 8 e 1.719 n1326
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LUT4 --- 0.390 B to Z i1990_2_lut_rep_17
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Route 2 e 1.386 n2460
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LUT4 --- 0.390 C to Z i1_2_lut_4_lut
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Route 3 e 1.483 PHI2_N_120_enable_6
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--------
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10.811 (23.7% logic, 76.3% route), 6 logic levels.
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Warning: 11.075 ns is the maximum delay for this constraint.
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
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357 items scored, 234 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path violates requirements by 4.364ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_610__i13 (from RCLK_c +)
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Destination: FD1P3AX D n8MEGEN_418 (to RCLK_c +)
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Delay: 9.182ns (23.7% logic, 76.3% route), 5 logic levels.
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Constraint Details:
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9.182ns data_path FS_610__i13 to n8MEGEN_418 violates
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5.000ns delay constraint less
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0.182ns L_S requirement (totaling 4.818ns) by 4.364ns
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Path Details: FS_610__i13 to n8MEGEN_418
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q FS_610__i13 (from RCLK_c)
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Route 3 e 1.603 FS[13]
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LUT4 --- 0.390 A to Z i1976_2_lut
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Route 3 e 1.483 n2272
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LUT4 --- 0.390 C to Z i5_3_lut_rep_21_4_lut
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Route 3 e 1.483 n2464
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LUT4 --- 0.390 B to Z i1_2_lut_3_lut_adj_4
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Route 1 e 1.220 n1325
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LUT4 --- 0.390 D to Z n8MEGEN_I_14_4_lut
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Route 1 e 1.220 n8MEGEN_N_91
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--------
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9.182 (23.7% logic, 76.3% route), 5 logic levels.
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Error: The following path violates requirements by 4.364ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_610__i15 (from RCLK_c +)
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Destination: FD1P3AX D n8MEGEN_418 (to RCLK_c +)
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Delay: 9.182ns (23.7% logic, 76.3% route), 5 logic levels.
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Constraint Details:
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9.182ns data_path FS_610__i15 to n8MEGEN_418 violates
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5.000ns delay constraint less
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0.182ns L_S requirement (totaling 4.818ns) by 4.364ns
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Path Details: FS_610__i15 to n8MEGEN_418
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q FS_610__i15 (from RCLK_c)
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Route 3 e 1.603 FS[15]
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LUT4 --- 0.390 B to Z i1976_2_lut
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Route 3 e 1.483 n2272
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LUT4 --- 0.390 C to Z i5_3_lut_rep_21_4_lut
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Route 3 e 1.483 n2464
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LUT4 --- 0.390 B to Z i1_2_lut_3_lut_adj_4
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Route 1 e 1.220 n1325
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LUT4 --- 0.390 D to Z n8MEGEN_I_14_4_lut
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Route 1 e 1.220 n8MEGEN_N_91
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--------
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9.182 (23.7% logic, 76.3% route), 5 logic levels.
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Error: The following path violates requirements by 4.349ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_610__i13 (from RCLK_c +)
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Destination: FD1P3AX SP n8MEGEN_418 (to RCLK_c +)
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Delay: 9.085ns (23.9% logic, 76.1% route), 5 logic levels.
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Constraint Details:
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9.085ns data_path FS_610__i13 to n8MEGEN_418 violates
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5.000ns delay constraint less
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0.264ns LCE_S requirement (totaling 4.736ns) by 4.349ns
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Path Details: FS_610__i13 to n8MEGEN_418
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q FS_610__i13 (from RCLK_c)
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Route 3 e 1.603 FS[13]
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LUT4 --- 0.390 A to Z i1976_2_lut
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Route 3 e 1.483 n2272
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LUT4 --- 0.390 C to Z i7_4_lut
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Route 2 e 1.386 n2214
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LUT4 --- 0.390 B to Z i2_2_lut
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Route 1 e 1.220 n7
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LUT4 --- 0.390 A to Z i17_4_lut
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Route 1 e 1.220 RCLK_c_enable_11
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--------
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9.085 (23.9% logic, 76.1% route), 5 logic levels.
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Warning: 9.364 ns is the maximum delay for this constraint.
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<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
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--------------
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--------------------------------------------------------------------------------
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Constraint | Constraint| Actual|Levels
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--------------------------------------------------------------------------------
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create_clock -period 5.000000 -name | | |
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clk3 [get_nets nCCAS_c] | -| -| 0
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create_clock -period 5.000000 -name | | |
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clk2 [get_nets nCRAS_c] | -| -| 0
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create_clock -period 5.000000 -name | | |
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clk1 [get_nets PHI2_c] | 5.000 ns| 22.150 ns| 6 *
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create_clock -period 5.000000 -name | | |
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clk0 [get_nets RCLK_c] | 5.000 ns| 9.364 ns| 5 *
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--------------------------------------------------------------------------------
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2 constraints not met.
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--------------------------------------------------------------------------------
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Critical Nets | Loads| Errors| % of total
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--------------------------------------------------------------------------------
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n1326 | 8| 104| 30.06%
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n26 | 1| 78| 22.54%
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RCLK_c_enable_23 | 16| 64| 18.50%
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--------------------------------------------------------------------------------
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<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
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---------------
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Timing errors: 346 Score: 1874657
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Constraints cover 476 paths, 187 nets, and 480 connections (64.3% coverage)
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Peak memory: 52895744 bytes, TRCE: 1204224 bytes, DLYMAN: 163840 bytes
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CPU_TIME_REPORT: 0 secs
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