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9 lines
544 B
Plaintext
9 lines
544 B
Plaintext
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<?xml version="1.0" encoding="UTF-8"?>
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<DiamondModule name="RPLL" module="RPLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2024 07 14 22:23:23.515" version="5.8" type="Module" synthesis="synplify" source_format="Verilog HDL">
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<Package>
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<File name="RPLL.lpc" type="lpc" modified="2024 07 14 22:23:22.367"/>
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<File name="RPLL.v" type="top_level_verilog" modified="2024 07 14 22:23:22.464"/>
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<File name="RPLL_tmpl.v" type="template_verilog" modified="2024 07 14 22:23:22.465"/>
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</Package>
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</DiamondModule>
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