mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-30 18:51:48 +00:00
116 lines
3.0 KiB
Tcl
116 lines
3.0 KiB
Tcl
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#!/usr/local/bin/wish
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proc GetPlatform {} {
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global tcl_platform
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set cpu $tcl_platform(machine)
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switch $cpu {
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intel -
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i*86* {
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set cpu ix86
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}
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x86_64 {
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if {$tcl_platform(wordSize) == 4} {
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set cpu ix86
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}
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}
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}
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switch $tcl_platform(platform) {
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windows {
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if {$cpu == "amd64"} {
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# Do not check wordSize, win32-x64 is an IL32P64 platform.
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set cpu x86_64
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}
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if {$cpu == "x86_64"} {
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return "nt64"
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} else {
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return "nt"
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}
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}
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unix {
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if {$tcl_platform(os) == "Linux"} {
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if {$cpu == "x86_64"} {
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return "lin64"
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} else {
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return "lin"
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}
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} else {
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return "sol"
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}
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}
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}
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return "nt"
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}
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set platformpath [GetPlatform]
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set Para(sbp_path) [file dirname [info script]]
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set Para(install_dir) $env(TOOLRTF)
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set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
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set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
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set Para(ModuleName) "RPLL"
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set Para(Module) "PLL"
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set Para(libname) machxo2
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set Para(arch_name) xo2c00
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set Para(PartType) "LCMXO2-1200HC"
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set Para(tech_syn) machxo2
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set Para(tech_cae) machxo2
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set Para(Package) "TQFP100"
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set Para(SpeedGrade) "4"
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set Para(FMax) "100"
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set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
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#create response file(*.cmd) for Synpwrap
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proc CreateCmdFile {} {
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global Para
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file mkdir "$Para(sbp_path)/syn_results"
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if [catch {open $Para(ModuleName).cmd w} rspFile] {
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puts "Cannot create response file $Para(ModuleName).cmd."
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exit -1
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} else {
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puts $rspFile "PROJECT: $Para(ModuleName)
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working_path: \"$Para(sbp_path)/syn_results\"
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module: $Para(ModuleName)
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verilog_file_list: \"$Para(install_dir)/cae_library/synthesis/verilog/$Para(tech_cae).v\" \"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\" \"$Para(sbp_path)/$Para(ModuleName).v\"
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vlog_std_v2001: true
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constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\"
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suffix_name: edn
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output_file_name: $Para(ModuleName)
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write_prf: true
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disable_io_insertion: true
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force_gsr: false
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frequency: $Para(FMax)
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fanout_limit: 50
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retiming: false
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pipe: false
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part: $Para(PartType)
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speed_grade: $Para(SpeedGrade)
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"
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close $rspFile
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}
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}
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#synpwrap
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CreateCmdFile
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set synpwrap "$Para(bin_dir)/synpwrap"
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if {[file exists $fdcfile] == 0} {
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set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg]
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} else {
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set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg]
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}
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#puts $msg
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#edif2ngd
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set edif2ngd "$Para(FPGAPath)/edif2ngd"
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set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg]
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#puts $msg
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#ngdbuild
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set ngdbuild "$Para(FPGAPath)/ngdbuild"
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set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
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#puts $msg
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