RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd

[ActiveSupport PAR]
; Global primary clocks
GLOBAL_PRIMARY_USED = 2;
; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_0_LOADNUM = 39;
; Global primary clock #1
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_1_LOADNUM = 18;
; # of global secondary clocks
GLOBAL_SECONDARY_USED = 2;
; Global secondary clock #0
GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c;
GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
GLOBAL_SECONDARY_0_LOADNUM = 11;
GLOBAL_SECONDARY_0_SIGTYPE = CLK;
; Global secondary clock #1
GLOBAL_SECONDARY_1_SIGNALNAME = nCCAS_c;
GLOBAL_SECONDARY_1_DRIVERTYPE = PIO;
GLOBAL_SECONDARY_1_LOADNUM = 10;
GLOBAL_SECONDARY_1_SIGTYPE = CLK;
; I/O Bank 0 Usage
BANK_0_USED = 13;
BANK_0_AVAIL = 19;
BANK_0_VCCIO = 3.3V;
BANK_0_VREF1 = NA;
; I/O Bank 1 Usage
BANK_1_USED = 20;
BANK_1_AVAIL = 20;
BANK_1_VCCIO = 3.3V;
BANK_1_VREF1 = NA;
; I/O Bank 2 Usage
BANK_2_USED = 16;
BANK_2_AVAIL = 20;
BANK_2_VCCIO = 3.3V;
BANK_2_VREF1 = NA;
; I/O Bank 3 Usage
BANK_3_USED = 18;
BANK_3_AVAIL = 20;
BANK_3_VCCIO = 3.3V;
BANK_3_VREF1 = NA;