2023-08-15 09:05:47 +00:00
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<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
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</HEAD>
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
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Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO256C
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Package: TQFP100
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Performance: 3
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Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
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Package Status: Final Version 1.19.
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Performance Hardware Data Status: Version 1.124.
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Setup and Hold Report
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--------------------------------------------------------------------------------
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<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
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2023-08-16 09:11:25 +00:00
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Wed Aug 16 04:50:40 2023
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2023-08-15 09:05:47 +00:00
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf
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Design file: ram2gs_lcmxo256c_impl1_map.ncd
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Preference file: ram2gs_lcmxo256c_impl1.prf
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Device,speed: LCMXO256C,3
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
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2023-08-16 09:11:25 +00:00
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<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 129 items scored, 0 timing errors detected.
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Report: 51.046MHz is the maximum frequency for this preference.
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2023-08-15 09:05:47 +00:00
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2023-08-16 09:11:25 +00:00
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<LI><A href='#map_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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Report: 400.000MHz is the maximum frequency for this preference.
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<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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Report: 400.000MHz is the maximum frequency for this preference.
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<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 388 items scored, 0 timing errors detected.
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Report: 88.456MHz is the maximum frequency for this preference.
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2023-08-15 09:05:47 +00:00
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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2023-08-16 09:11:25 +00:00
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<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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129 items scored, 0 timing errors detected.
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2023-08-15 09:05:47 +00:00
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--------------------------------------------------------------------------------
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2023-08-16 09:11:25 +00:00
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Passed: The following path meets requirements by 162.619ns (weighted slack = 325.238ns)
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2023-08-15 09:05:47 +00:00
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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2023-08-16 09:11:25 +00:00
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Source: FF Q Bank[2] (from PHI2_c +)
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Destination: FF Data in CmdSubmitted (to PHI2_c -)
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2023-08-15 09:05:47 +00:00
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2023-08-16 09:11:25 +00:00
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Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels.
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2023-08-15 09:05:47 +00:00
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Constraint Details:
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2023-08-16 09:11:25 +00:00
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9.621ns physical path delay SLICE_71 to SLICE_22 meets
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172.414ns delay constraint less
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0.174ns DIN_SET requirement (totaling 172.240ns) by 162.619ns
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2023-08-15 09:05:47 +00:00
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Physical Path Details:
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2023-08-16 09:11:25 +00:00
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Data path SLICE_71 to SLICE_22:
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2023-08-15 09:05:47 +00:00
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Name Fanout Delay (ns) Site Resource
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2023-08-16 09:11:25 +00:00
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REG_DEL --- 0.560 SLICE_71.CLK to SLICE_71.Q0 SLICE_71 (from PHI2_c)
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ROUTE 1 e 1.441 SLICE_71.Q0 to SLICE_56.A1 Bank[2]
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CTOF_DEL --- 0.371 SLICE_56.A1 to SLICE_56.F1 SLICE_56
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ROUTE 1 e 1.441 SLICE_56.F1 to SLICE_70.D1 C1WR_0_a2_0_11
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CTOF_DEL --- 0.371 SLICE_70.D1 to SLICE_70.F1 SLICE_70
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ROUTE 6 e 1.441 SLICE_70.F1 to SLICE_67.D0 N_147
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CTOF_DEL --- 0.371 SLICE_67.D0 to SLICE_67.F0 SLICE_67
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ROUTE 5 e 1.441 SLICE_67.F0 to SLICE_82.A0 XOR8MEG18
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CTOF_DEL --- 0.371 SLICE_82.A0 to SLICE_82.F0 SLICE_82
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ROUTE 1 e 1.441 SLICE_82.F0 to SLICE_22.A0 CmdSubmitted_1_sqmuxa
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CTOF_DEL --- 0.371 SLICE_22.A0 to SLICE_22.F0 SLICE_22
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ROUTE 1 e 0.001 SLICE_22.F0 to SLICE_22.DI0 N_460_0 (to PHI2_c)
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2023-08-15 09:05:47 +00:00
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--------
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2023-08-16 09:11:25 +00:00
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9.621 (25.1% logic, 74.9% route), 6 logic levels.
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2023-08-15 09:05:47 +00:00
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2023-08-16 09:11:25 +00:00
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Report: 51.046MHz is the maximum frequency for this preference.
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2023-08-15 09:05:47 +00:00
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================================================================================
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2023-08-16 09:11:25 +00:00
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<A name="map_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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2023-08-15 09:05:47 +00:00
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--------------------------------------------------------------------------------
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2023-08-16 09:11:25 +00:00
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Passed: The following path meets requirements by 342.328ns
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The internal maximum frequency of the following component is 400.000 MHz
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Logical Details: Cell type Pin name Component name
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Destination: PIO PAD nCCAS
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Delay: 2.500ns -- based on Minimum Pulse Width
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Report: 400.000MHz is the maximum frequency for this preference.
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================================================================================
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<A name="map_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 342.328ns
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The internal maximum frequency of the following component is 400.000 MHz
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Logical Details: Cell type Pin name Component name
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Destination: PIO PAD nCRAS
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Delay: 2.500ns -- based on Minimum Pulse Width
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Report: 400.000MHz is the maximum frequency for this preference.
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================================================================================
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<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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388 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 4.695ns
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2023-08-15 09:05:47 +00:00
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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2023-08-16 09:11:25 +00:00
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Source: FF Q FS[17] (from RCLK_c +)
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Destination: FF Data in LEDEN (to RCLK_c +)
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2023-08-15 09:05:47 +00:00
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Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels.
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Constraint Details:
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2023-08-16 09:11:25 +00:00
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11.061ns physical path delay SLICE_1 to SLICE_33 meets
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16.000ns delay constraint less
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0.244ns CE_SET requirement (totaling 15.756ns) by 4.695ns
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2023-08-15 09:05:47 +00:00
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Physical Path Details:
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2023-08-16 09:11:25 +00:00
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Data path SLICE_1 to SLICE_33:
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2023-08-15 09:05:47 +00:00
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Name Fanout Delay (ns) Site Resource
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2023-08-16 09:11:25 +00:00
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REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q1 SLICE_1 (from RCLK_c)
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ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_81.D1 FS[17]
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CTOF_DEL --- 0.371 SLICE_81.D1 to SLICE_81.F1 SLICE_81
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ROUTE 1 e 1.441 SLICE_81.F1 to SLICE_72.C1 UFMSDI_ens2_i_o2_0_3
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CTOF_DEL --- 0.371 SLICE_72.C1 to SLICE_72.F1 SLICE_72
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ROUTE 4 e 1.441 SLICE_72.F1 to SLICE_58.C1 N_51
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CTOF_DEL --- 0.371 SLICE_58.C1 to SLICE_58.F1 SLICE_58
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ROUTE 2 e 1.441 SLICE_58.F1 to SLICE_87.D0 N_151
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CTOF_DEL --- 0.371 SLICE_87.D0 to SLICE_87.F0 SLICE_87
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ROUTE 2 e 1.441 SLICE_87.F0 to SLICE_69.C0 N_137_8
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CTOF_DEL --- 0.371 SLICE_69.C0 to SLICE_69.F0 SLICE_69
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ROUTE 1 e 1.441 SLICE_69.F0 to SLICE_33.CE N_33 (to RCLK_c)
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2023-08-15 09:05:47 +00:00
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--------
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11.061 (21.8% logic, 78.2% route), 6 logic levels.
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2023-08-16 09:11:25 +00:00
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Report: 88.456MHz is the maximum frequency for this preference.
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2023-08-15 09:05:47 +00:00
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<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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2023-08-16 09:11:25 +00:00
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FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 51.046 MHz| 6
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FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0
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FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0
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2023-08-15 09:05:47 +00:00
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2023-08-16 09:11:25 +00:00
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FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 88.456 MHz| 6
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2023-08-15 09:05:47 +00:00
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----------------------------------------------------------------------------
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2023-08-16 09:11:25 +00:00
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All preferences were met.
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2023-08-15 09:05:47 +00:00
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<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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------------------------
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Found 4 clocks:
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2023-08-16 09:11:25 +00:00
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Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 10
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2023-08-15 09:05:47 +00:00
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No transfer within this clock domain is found
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2023-08-16 09:11:25 +00:00
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 8
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2023-08-15 09:05:47 +00:00
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No transfer within this clock domain is found
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2023-08-16 09:11:25 +00:00
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Clock Domain: RCLK_c Source: RCLK.PAD Loads: 32
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Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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2023-08-15 09:05:47 +00:00
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Data transfers from:
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Clock Domain: nCRAS_c Source: nCRAS.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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2023-08-16 09:11:25 +00:00
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Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15
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Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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2023-08-15 09:05:47 +00:00
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
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---------------
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2023-08-16 09:11:25 +00:00
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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2023-08-15 09:05:47 +00:00
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2023-08-16 09:11:25 +00:00
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Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
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2023-08-15 09:05:47 +00:00
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--------------------------------------------------------------------------------
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<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
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2023-08-16 09:11:25 +00:00
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Wed Aug 16 04:50:40 2023
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2023-08-15 09:05:47 +00:00
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf
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Design file: ram2gs_lcmxo256c_impl1_map.ncd
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Preference file: ram2gs_lcmxo256c_impl1.prf
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Device,speed: LCMXO256C,M
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
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2023-08-16 09:11:25 +00:00
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<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 129 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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2023-08-15 09:05:47 +00:00
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2023-08-16 09:11:25 +00:00
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<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 388 items scored, 0 timing errors detected.
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2023-08-15 09:05:47 +00:00
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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2023-08-16 09:11:25 +00:00
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<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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129 items scored, 0 timing errors detected.
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2023-08-15 09:05:47 +00:00
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--------------------------------------------------------------------------------
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2023-08-16 09:11:25 +00:00
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Passed: The following path meets requirements by 0.430ns
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2023-08-15 09:05:47 +00:00
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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2023-08-16 09:11:25 +00:00
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Source: FF Q C1Submitted (from PHI2_c -)
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Destination: FF Data in C1Submitted (to PHI2_c -)
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2023-08-15 09:05:47 +00:00
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2023-08-16 09:11:25 +00:00
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Delay: 0.411ns (51.3% logic, 48.7% route), 2 logic levels.
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2023-08-15 09:05:47 +00:00
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Constraint Details:
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2023-08-16 09:11:25 +00:00
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0.411ns physical path delay SLICE_14 to SLICE_14 meets
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-0.019ns DIN_HLD and
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0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns
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2023-08-15 09:05:47 +00:00
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Physical Path Details:
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2023-08-16 09:11:25 +00:00
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Data path SLICE_14 to SLICE_14:
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2023-08-15 09:05:47 +00:00
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Name Fanout Delay (ns) Site Resource
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2023-08-16 09:11:25 +00:00
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REG_DEL --- 0.137 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from PHI2_c)
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ROUTE 2 e 0.199 SLICE_14.Q0 to SLICE_14.B0 C1Submitted
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CTOF_DEL --- 0.074 SLICE_14.B0 to SLICE_14.F0 SLICE_14
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ROUTE 1 e 0.001 SLICE_14.F0 to SLICE_14.DI0 C1Submitted_RNO (to PHI2_c)
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2023-08-15 09:05:47 +00:00
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--------
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2023-08-16 09:11:25 +00:00
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0.411 (51.3% logic, 48.7% route), 2 logic levels.
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2023-08-15 09:05:47 +00:00
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================================================================================
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2023-08-16 09:11:25 +00:00
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<A name="map_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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2023-08-15 09:05:47 +00:00
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--------------------------------------------------------------------------------
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2023-08-16 09:11:25 +00:00
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================================================================================
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<A name="map_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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388 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.342ns
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2023-08-15 09:05:47 +00:00
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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2023-08-16 09:11:25 +00:00
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Source: FF Q CASr (from RCLK_c +)
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Destination: FF Data in CASr2 (to RCLK_c +)
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2023-08-15 09:05:47 +00:00
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2023-08-16 09:11:25 +00:00
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Delay: 0.325ns (38.8% logic, 61.2% route), 1 logic levels.
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2023-08-15 09:05:47 +00:00
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Constraint Details:
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2023-08-16 09:11:25 +00:00
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0.325ns physical path delay SLICE_75 to SLICE_75 meets
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-0.017ns M_HLD and
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0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns
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2023-08-15 09:05:47 +00:00
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Physical Path Details:
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2023-08-16 09:11:25 +00:00
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Data path SLICE_75 to SLICE_75:
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2023-08-15 09:05:47 +00:00
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Name Fanout Delay (ns) Site Resource
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2023-08-16 09:11:25 +00:00
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REG_DEL --- 0.126 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from RCLK_c)
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ROUTE 1 e 0.199 SLICE_75.Q0 to SLICE_75.M1 CASr (to RCLK_c)
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2023-08-15 09:05:47 +00:00
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--------
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2023-08-16 09:11:25 +00:00
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0.325 (38.8% logic, 61.2% route), 1 logic levels.
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2023-08-15 09:05:47 +00:00
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<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference(MIN Delays) | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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2023-08-16 09:11:25 +00:00
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FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
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FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
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2023-08-15 09:05:47 +00:00
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2023-08-16 09:11:25 +00:00
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FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
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FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
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2023-08-15 09:05:47 +00:00
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----------------------------------------------------------------------------
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All preferences were met.
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<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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------------------------
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Found 4 clocks:
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2023-08-16 09:11:25 +00:00
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Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 10
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2023-08-15 09:05:47 +00:00
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No transfer within this clock domain is found
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2023-08-16 09:11:25 +00:00
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 8
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2023-08-15 09:05:47 +00:00
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No transfer within this clock domain is found
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2023-08-16 09:11:25 +00:00
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Clock Domain: RCLK_c Source: RCLK.PAD Loads: 32
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Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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2023-08-15 09:05:47 +00:00
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Data transfers from:
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Clock Domain: nCRAS_c Source: nCRAS.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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2023-08-16 09:11:25 +00:00
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Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15
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Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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2023-08-15 09:05:47 +00:00
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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2023-08-16 09:11:25 +00:00
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Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
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2023-08-15 09:05:47 +00:00
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<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
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---------------
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2023-08-16 09:11:25 +00:00
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Timing errors: 0 (setup), 0 (hold)
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Score: 0 (setup), 0 (hold)
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Cumulative negative slack: 0 (0+0)
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2023-08-15 09:05:47 +00:00
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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