RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_map.cam

[ START MERGED ]
RASr2_i RASr2
XOR8MEG.CN PHI2_c
nCRAS_c_i nCRAS_c
InitReady_i InitReady
[ END MERGED ]
[ START CLIPPED ]
GND
ufmefb/VCC
ufmefb/GND
FS_s_0_S1[17]
FS_s_0_COUT[17]
ufmefb/CFGSTDBY
ufmefb/CFGWAKE
ufmefb/wbc_ufm_irq
ufmefb/TCOC
ufmefb/TCINT
ufmefb/SPIIRQO
ufmefb/SPICSNEN
ufmefb/SPIMCSN7
ufmefb/SPIMCSN6
ufmefb/SPIMCSN5
ufmefb/SPIMCSN4
ufmefb/SPIMCSN3
ufmefb/SPIMCSN2
ufmefb/SPIMCSN1
ufmefb/SPIMCSN0
ufmefb/SPIMOSIEN
ufmefb/SPIMOSIO
ufmefb/SPIMISOEN
ufmefb/SPIMISOO
ufmefb/SPISCKEN
ufmefb/SPISCKO
ufmefb/I2C2IRQO
ufmefb/I2C1IRQO
ufmefb/I2C2SDAOEN
ufmefb/I2C2SDAO
ufmefb/I2C2SCLOEN
ufmefb/I2C2SCLO
ufmefb/I2C1SDAOEN
ufmefb/I2C1SDAO
ufmefb/I2C1SCLOEN
ufmefb/I2C1SCLO
ufmefb/PLLDATO0
ufmefb/PLLDATO1
ufmefb/PLLDATO2
ufmefb/PLLDATO3
ufmefb/PLLDATO4
ufmefb/PLLDATO5
ufmefb/PLLDATO6
ufmefb/PLLDATO7
ufmefb/PLLADRO0
ufmefb/PLLADRO1
ufmefb/PLLADRO2
ufmefb/PLLADRO3
ufmefb/PLLADRO4
ufmefb/PLLWEO
ufmefb/PLL1STBO
ufmefb/PLL0STBO
ufmefb/PLLRSTO
ufmefb/PLLCLKO
ufmefb/wb_ack_o
ufmefb/wb_dat_o_1[2]
ufmefb/wb_dat_o_1[3]
ufmefb/wb_dat_o_1[4]
ufmefb/wb_dat_o_1[5]
ufmefb/wb_dat_o_1[6]
ufmefb/wb_dat_o_1[7]
FS_cry_0_S0[0]
N_1
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 20:59:37 2023

SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;
LOCATE COMP "Dout[0]" SITE "76" ;
LOCATE COMP "PHI2" SITE "8" ;
LOCATE COMP "RDQML" SITE "48" ;
LOCATE COMP "RDQMH" SITE "51" ;
LOCATE COMP "nRCAS" SITE "52" ;
LOCATE COMP "nRRAS" SITE "54" ;
LOCATE COMP "nRWE" SITE "49" ;
LOCATE COMP "RCKE" SITE "53" ;
LOCATE COMP "RCLK" SITE "62" ;
LOCATE COMP "nRCS" SITE "57" ;
LOCATE COMP "RD[7]" SITE "43" ;
LOCATE COMP "RD[6]" SITE "42" ;
LOCATE COMP "RD[5]" SITE "41" ;
LOCATE COMP "RD[4]" SITE "40" ;
LOCATE COMP "RD[3]" SITE "39" ;
LOCATE COMP "RD[2]" SITE "38" ;
LOCATE COMP "RD[1]" SITE "37" ;
LOCATE COMP "RA[11]" SITE "59" ;
LOCATE COMP "RA[10]" SITE "64" ;
LOCATE COMP "RA[9]" SITE "63" ;
LOCATE COMP "RA[8]" SITE "65" ;
LOCATE COMP "RA[7]" SITE "75" ;
LOCATE COMP "RA[6]" SITE "68" ;
LOCATE COMP "RA[5]" SITE "70" ;
LOCATE COMP "RA[4]" SITE "74" ;
LOCATE COMP "RA[3]" SITE "71" ;
LOCATE COMP "RA[2]" SITE "69" ;
LOCATE COMP "RA[1]" SITE "67" ;
LOCATE COMP "RA[0]" SITE "66" ;
LOCATE COMP "RBA[1]" SITE "60" ;
LOCATE COMP "RBA[0]" SITE "58" ;
LOCATE COMP "LED" SITE "34" ;
LOCATE COMP "nFWE" SITE "15" ;
LOCATE COMP "nCRAS" SITE "17" ;
LOCATE COMP "nCCAS" SITE "9" ;
LOCATE COMP "Dout[7]" SITE "82" ;
LOCATE COMP "Dout[6]" SITE "78" ;
LOCATE COMP "Dout[5]" SITE "84" ;
LOCATE COMP "Dout[4]" SITE "83" ;
LOCATE COMP "Dout[3]" SITE "85" ;
LOCATE COMP "Dout[2]" SITE "87" ;
LOCATE COMP "Dout[1]" SITE "86" ;
LOCATE COMP "Din[7]" SITE "1" ;
LOCATE COMP "Din[6]" SITE "2" ;
LOCATE COMP "Din[5]" SITE "98" ;
LOCATE COMP "Din[4]" SITE "99" ;
LOCATE COMP "Din[3]" SITE "97" ;
LOCATE COMP "Din[2]" SITE "88" ;
LOCATE COMP "Din[1]" SITE "96" ;
LOCATE COMP "Din[0]" SITE "3" ;
LOCATE COMP "CROW[1]" SITE "16" ;
LOCATE COMP "CROW[0]" SITE "10" ;
LOCATE COMP "MAin[9]" SITE "32" ;
LOCATE COMP "MAin[8]" SITE "25" ;
LOCATE COMP "MAin[7]" SITE "18" ;
LOCATE COMP "MAin[6]" SITE "24" ;
LOCATE COMP "MAin[5]" SITE "19" ;
LOCATE COMP "MAin[4]" SITE "20" ;
LOCATE COMP "MAin[3]" SITE "21" ;
LOCATE COMP "MAin[2]" SITE "13" ;
LOCATE COMP "MAin[1]" SITE "12" ;
LOCATE COMP "MAin[0]" SITE "14" ;
FREQUENCY PORT "PHI2" 2.900000 MHz ;
FREQUENCY PORT "nCCAS" 2.900000 MHz ;
FREQUENCY PORT "nCRAS" 2.900000 MHz ;
FREQUENCY PORT "RCLK" 62.500000 MHz ;
SCHEMATIC END ;
[ END DESIGN PREFS ]