mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-28 21:49:21 +00:00
239 lines
8.0 KiB
Plaintext
239 lines
8.0 KiB
Plaintext
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synthesis: version Diamond (64-bit) 3.12.1.454
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Tue Aug 15 05:03:20 2023
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Command Line: synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
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Synthesis options:
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The -a option is MachXO.
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The -s option is 3.
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The -t option is TQFP100.
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The -d option is LCMXO256C.
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Using package TQFP100.
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Using performance grade 3.
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##########################################################
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### Lattice Family : MachXO
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### Device : LCMXO256C
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### Package : TQFP100
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### Speed : 3
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##########################################################
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INFO - synthesis: User-Selected Strategy Settings
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Optimization goal = Balanced
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Top-level module name = RAM2GS.
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Target frequency = 200.000000 MHz.
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Maximum fanout = 1000.
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Timing path count = 3
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BRAM utilization = 100.000000 %
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DSP usage = true
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DSP utilization = 100.000000 %
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fsm_encoding_style = auto
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resolve_mixed_drivers = 0
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fix_gated_clocks = 1
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Mux style = Auto
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Use Carry Chain = true
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carry_chain_length = 0
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Loop Limit = 1950.
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Use IO Insertion = TRUE
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Use IO Reg = AUTO
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Resource Sharing = TRUE
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Propagate Constants = TRUE
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Remove Duplicate Registers = TRUE
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force_gsr = auto
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ROM style = auto
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RAM style = auto
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The -comp option is FALSE.
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The -syn option is FALSE.
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-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added)
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-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
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-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1 (searchpath added)
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-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added)
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Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
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NGD file = RAM2GS_LCMXO256C_impl1.ngd
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-sdc option: SDC file input not used.
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-lpf option: Output file option is ON.
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Hardtimer checking is enabled (default). The -dt option is not used.
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The -r option is OFF. [ Remove LOC Properties is OFF. ]
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Technology check ok...
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Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
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Compile design.
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Compile Design Begin
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Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
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Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
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Top module name (Verilog): RAM2GS
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INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
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WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
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WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
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WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
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Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
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Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
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Package Status: Final Version 1.19.
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Top-level module name = RAM2GS.
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INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
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original encoding -> new encoding (one-hot encoding)
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0000 -> 0000000000000001
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0001 -> 0000000000000010
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0010 -> 0000000000000100
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0011 -> 0000000000001000
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0100 -> 0000000000010000
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0101 -> 0000000000100000
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0110 -> 0000000001000000
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0111 -> 0000000010000000
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1000 -> 0000000100000000
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1001 -> 0000001000000000
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1010 -> 0000010000000000
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1011 -> 0000100000000000
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1100 -> 0001000000000000
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1101 -> 0010000000000000
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1110 -> 0100000000000000
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1111 -> 1000000000000000
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INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
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original encoding -> new encoding (one-hot encoding)
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00 -> 0001
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01 -> 0010
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10 -> 0100
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11 -> 1000
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GSR will not be inferred because no asynchronous signal was found in the netlist.
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WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
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Applying 200.000000 MHz constraint to all clocks
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WARNING - synthesis: No user .sdc file.
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Results of NGD DRC are available in RAM2GS_drc.log.
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Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
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Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
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All blocks are expanded and NGD expansion is successful.
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Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
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################### Begin Area Report (RAM2GS)######################
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Number of register bits => 102 of 490 (20 % )
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BB => 8
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CCU2 => 9
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FD1P3AX => 28
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FD1P3AY => 3
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FD1P3IX => 2
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FD1S3AX => 47
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FD1S3AY => 1
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FD1S3IX => 16
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FD1S3JX => 5
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GSR => 1
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IB => 26
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INV => 3
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OB => 33
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ORCALUT4 => 127
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PFUMX => 6
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################### End Area Report ##################
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################### Begin BlackBox Report ######################
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TSALL => 1
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################### End BlackBox Report ##################
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################### Begin Clock Report ######################
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Clock Nets
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Number of Clocks: 4
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Net : RCLK_c, loads : 62
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Net : PHI2_c, loads : 11
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Net : nCCAS_c, loads : 2
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Net : nCRAS_c, loads : 2
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Clock Enable Nets
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Number of Clock Enables: 13
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Top 10 highest fanout Clock Enables:
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Net : RCLK_c_enable_23, loads : 16
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Net : RCLK_c_enable_4, loads : 3
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Net : PHI2_N_120_enable_6, loads : 3
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Net : RCLK_c_enable_24, loads : 2
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Net : RCLK_c_enable_12, loads : 1
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Net : PHI2_N_120_enable_1, loads : 1
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Net : PHI2_N_120_enable_4, loads : 1
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Net : RCLK_c_enable_3, loads : 1
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Net : PHI2_N_120_enable_5, loads : 1
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Net : RCLK_c_enable_11, loads : 1
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Highest fanout non-clock nets
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Top 10 highest fanout non-clock nets:
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Net : InitReady, loads : 17
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Net : Ready, loads : 17
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Net : RCLK_c_enable_23, loads : 16
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Net : nCRAS_N_9, loads : 15
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Net : RASr2, loads : 13
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Net : nRowColSel, loads : 13
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Net : n2477, loads : 13
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Net : MAin_c_0, loads : 12
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Net : nRowColSel_N_35, loads : 12
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Net : Din_c_6, loads : 11
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################### End Clock Report ##################
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Timing Report Summary
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--------------
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--------------------------------------------------------------------------------
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Constraint | Constraint| Actual|Levels
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--------------------------------------------------------------------------------
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create_clock -period 5.000000 -name | | |
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clk3 [get_nets nCCAS_c] | -| -| 0
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create_clock -period 5.000000 -name | | |
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clk2 [get_nets nCRAS_c] | -| -| 0
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create_clock -period 5.000000 -name | | |
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clk1 [get_nets PHI2_c] | 200.000 MHz| 45.147 MHz| 6 *
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create_clock -period 5.000000 -name | | |
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clk0 [get_nets RCLK_c] | 200.000 MHz| 106.792 MHz| 5 *
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--------------------------------------------------------------------------------
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2 constraints not met.
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Peak Memory Usage: 50.672 MB
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--------------------------------------------------------------
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Elapsed CPU time for LSE flow : 0.516 secs
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--------------------------------------------------------------
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