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2023-08-17 01:04:05 +00:00
< PRE > < A name = "Par" > < / A > PAR: Place And Route Diamond (64-bit) 3.12.1.454.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT& T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
2023-08-20 11:10:11 +00:00
Sat Aug 19 21:55:01 2023
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C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
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-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
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Preference file: LCMXO2_640HC_impl1.prf.
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< A name = "par_cts" > < / A > < B > < U > < big > Cost Table Summary< / big > < / U > < / B >
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
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5_1 * 0 6.966 0 0.304 0 10 Completed
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* : Design saved.
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Total (real) run time for 1-seed: 10 secs
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par done!
Note: user must run ' Trace' for timing closure signoff.
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Lattice Place and Route Report for Design " LCMXO2_640HC_impl1_map.ncd"
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Sat Aug 19 21:55:01 2023
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< A name = "par_best" > < / A > < B > < U > < big > Best Par Run< / big > < / U > < / B >
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PAR: Place And Route Diamond (64-bit) 3.12.1.454.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
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Preference file: LCMXO2_640HC_impl1.prf.
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Placement level-cost: 5-1.
Routing Iterations: 6
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Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
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Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application par from file ' xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
< A name = "par_dus" > < / A > < B > < U > < big > Device utilization summary:< / big > < / U > < / B >
PIO (prelim) 63+4(JTAG)/80 84% used
63+4(JTAG)/79 85% bonded
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IOLOGIC 25/80 31% used
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SLICE 113/320 35% used
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EFB 1/1 100% used
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Number of Signals: 374
Number of Connections: 978
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Pin Constraint Summary:
63 out of 63 pins locked (100% locked).
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The following 3 signals are selected to use the primary clock routing resources:
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RCLK_c (driver: RCLK, clk load #: 47)
PHI2_c (driver: PHI2, clk load #: 21)
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nCRAS_c (driver: nCRAS, clk load #: 10)
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WARNING - par: Signal " RCLK_c" is selected to use Primary clock resources. However, its driver comp " RCLK" is located at " 62" , which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
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WARNING - par: Signal " PHI2_c" is selected to use Primary clock resources. However, its driver comp " PHI2" is located at " 8" , which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal " nCRAS_c" is selected to use Primary clock resources. However, its driver comp " nCRAS" is located at " 17" , which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
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The following 1 signal is selected to use the secondary clock routing resources:
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nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
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WARNING - par: Signal " nCCAS_c" is selected to use Secondary clock resources. However, its driver comp " nCCAS" is located at " 9" , which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
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No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
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............
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Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
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....................
Placer score = 53481.
Finished Placer Phase 1. REAL time: 5 secs
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Starting Placer Phase 2.
.
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Placer score = 53406
Finished Placer Phase 2. REAL time: 5 secs
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< A name = "par_clk" > < / A > < B > < U > < big > Clock Report< / big > < / U > < / B >
Global Clock Resources:
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CLK_PIN : 0 out of 8 (0%)
General PIO: 4 out of 80 (5%)
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DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
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PRIMARY " RCLK_c" from comp " RCLK" on PIO site " 62 (PR5D)" , clk load = 47
PRIMARY " PHI2_c" from comp " PHI2" on PIO site " 8 (PL3B)" , clk load = 21
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PRIMARY " nCRAS_c" from comp " nCRAS" on PIO site " 17 (PL6B)" , clk load = 10
SECONDARY " nCCAS_c" from comp " nCCAS" on PIO site " 9 (PL3C)" , clk load = 8, ce load = 0, sr load = 0
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PRIMARY : 3 out of 8 (37%)
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SECONDARY: 1 out of 8 (12%)
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I/O Usage Summary (final):
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
Number of PIO comps: 63; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 3.3V | - |
| 1 | 20 / 20 (100%) | 3.3V | - |
| 2 | 12 / 20 ( 60%) | 3.3V | - |
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
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Total placer CPU time: 5 secs
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Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
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0 connections routed; 978 unrouted.
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Starting router resource preassignment
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WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
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WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
2023-08-20 11:10:11 +00:00
Completed router resource preassignment. Real time: 8 secs
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Start NBR router at 21:55:09 08/19/23
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*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
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Start NBR special constraint process at 21:55:09 08/19/23
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Start NBR section for initial routing at 21:55:10 08/19/23
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Level 1, iteration 1
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0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack< setup> : 7.085ns/0.000ns; real time: 9 secs
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Level 2, iteration 1
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0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack< setup> : 7.138ns/0.000ns; real time: 9 secs
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Level 3, iteration 1
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0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack< setup> : 7.276ns/0.000ns; real time: 9 secs
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Level 4, iteration 1
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10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack< setup> : 6.966ns/0.000ns; real time: 9 secs
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Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
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Start NBR section for normal routing at 21:55:10 08/19/23
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Level 4, iteration 1
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3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack< setup> : 6.966ns/0.000ns; real time: 9 secs
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Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack< setup> : 6.966ns/0.000ns; real time: 9 secs
2021-10-09 01:29:42 +00:00
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Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
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Start NBR section for re-routing at 21:55:10 08/19/23
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Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack< setup> : 6.966ns/0.000ns; real time: 9 secs
2021-10-09 01:29:42 +00:00
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Start NBR section for post-routing at 21:55:10 08/19/23
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End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
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Estimated worst slack< setup> : 6.966ns
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Timing score< setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
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Total CPU time 9 secs
Total REAL time: 9 secs
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Completely routed.
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End of route. 978 routed (100.00%); 0 unrouted.
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Hold time timing score: 0, hold timing errors: 0
Timing score: 0
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Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
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All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
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PAR_SUMMARY::Worst slack< setup/< ns> > = 6.966
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PAR_SUMMARY::Timing score< setup/< ns> > = 0.000
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PAR_SUMMARY::Worst slack< hold /< ns> > = 0.304
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PAR_SUMMARY::Timing score< hold /< ns> > = 0.000
PAR_SUMMARY::Number of errors = 0
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Total CPU time to completion: 9 secs
Total REAL time to completion: 10 secs
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par done!
Note: user must run ' Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT& T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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