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Zane Kaminski
2021-04-29 19:44:34 -04:00
parent afb2690e49
commit 1d56e3a1f7
165 changed files with 310 additions and 1666 deletions
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Hardware/AGM/cpld-src/RAM4GS.qpf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 21:16:34 March 08, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "21:16:34 March 08, 2020"
# Revisions
PROJECT_REVISION = "RAM4GS"
Hardware/AGM/cpld-src/RAM4GS.qsf
-213
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 21:16:34 March 08, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# RAM4GS_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM4GS
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34 MARCH 08, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name SDC_FILE constraints.sdc
set_global_assignment -name VERILOG_FILE RAM4GS.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON
set_global_assignment -name SAFE_STATE_MACHINE ON
set_location_assignment PIN_12 -to RCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK
set_location_assignment PIN_52 -to PHI2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI2
set_location_assignment PIN_67 -to nCRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCRAS
set_location_assignment PIN_53 -to nCCAS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCCAS
set_location_assignment PIN_48 -to nFWE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nFWE
set_location_assignment PIN_49 -to MAin[0]
set_location_assignment PIN_51 -to MAin[1]
set_location_assignment PIN_50 -to MAin[2]
set_location_assignment PIN_71 -to MAin[3]
set_location_assignment PIN_70 -to MAin[4]
set_location_assignment PIN_69 -to MAin[5]
set_location_assignment PIN_72 -to MAin[6]
set_location_assignment PIN_68 -to MAin[7]
set_location_assignment PIN_73 -to MAin[8]
set_location_assignment PIN_74 -to MAin[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MAin
set_location_assignment PIN_54 -to CROW[0]
set_location_assignment PIN_55 -to CROW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CROW
set_location_assignment PIN_35 -to Din[2]
set_location_assignment PIN_36 -to Din[1]
set_location_assignment PIN_37 -to Din[3]
set_location_assignment PIN_38 -to Din[5]
set_location_assignment PIN_39 -to Din[4]
set_location_assignment PIN_40 -to Din[7]
set_location_assignment PIN_41 -to Din[6]
set_location_assignment PIN_42 -to Din[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
set_location_assignment PIN_33 -to Dout[0]
set_location_assignment PIN_57 -to Dout[1]
set_location_assignment PIN_56 -to Dout[2]
set_location_assignment PIN_47 -to Dout[3]
set_location_assignment PIN_44 -to Dout[4]
set_location_assignment PIN_28 -to Dout[5]
set_location_assignment PIN_34 -to Dout[6]
set_location_assignment PIN_43 -to Dout[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
set_location_assignment PIN_8 -to RCKE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCKE
set_location_assignment PIN_3 -to nRCS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCS
set_location_assignment PIN_100 -to nRWE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
set_location_assignment PIN_6 -to nRRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRRAS
set_location_assignment PIN_4 -to nRCAS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCAS
set_location_assignment PIN_5 -to RBA[0]
set_location_assignment PIN_14 -to RBA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RBA
set_location_assignment PIN_18 -to RA[0]
set_location_assignment PIN_20 -to RA[1]
set_location_assignment PIN_30 -to RA[2]
set_location_assignment PIN_27 -to RA[3]
set_location_assignment PIN_26 -to RA[4]
set_location_assignment PIN_29 -to RA[5]
set_location_assignment PIN_21 -to RA[6]
set_location_assignment PIN_19 -to RA[7]
set_location_assignment PIN_17 -to RA[8]
set_location_assignment PIN_15 -to RA[9]
set_location_assignment PIN_16 -to RA[10]
set_location_assignment PIN_7 -to RA[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
set_location_assignment PIN_2 -to RDQMH
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQMH
set_location_assignment PIN_98 -to RDQML
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQML
set_location_assignment PIN_96 -to RD[0]
set_location_assignment PIN_90 -to RD[1]
set_location_assignment PIN_89 -to RD[2]
set_location_assignment PIN_99 -to RD[3]
set_location_assignment PIN_92 -to RD[4]
set_location_assignment PIN_91 -to RD[5]
set_location_assignment PIN_95 -to RD[6]
set_location_assignment PIN_97 -to RD[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
set_global_assignment -name MIF_FILE RAM4GS.mif
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to MAin
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to CROW
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to Din
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to Dout
set_instance_assignment -name SLOW_SLEW_RATE OFF -to Dout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCKE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RCKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRRAS
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCAS
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RBA
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RBA
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RBA
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RA
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RA
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQMH
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQML
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
set_global_assignment -name QIP_FILE UFM.qip
Hardware/AGM/cpld-src/RAM4GS.v
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module RAM4GS(PHI2, MAin, CROW, Din, Dout,
nCCAS, nCRAS, nFWE,
RBA, RA, RD, nRCS, RCLK, RCKE,
nRWE, nRRAS, nRCAS, RDQMH, RDQML,
nUFMCSout, UFMCLKout, UFMSDIout, UFMSDOout,
nUFMCSin , UFMCLKin , UFMSDIin , UFMSDOin);
/* 65816 Phase 2 Clock */
input PHI2;
/* Async. DRAM Control Inputs */
input nCCAS, nCRAS;
/* Synchronized PHI2 and DRAM signals */
reg PHI2r, PHI2r2, PHI2r3;
reg RASr, RASr2, RASr3;
reg CASr, CASr2, CASr3;
reg FWEr;
reg CBR;
/* 65816 Data */
input [7:0] Din;
output [7:0] Dout = RD[7:0];
/* Latched 65816 Bank Address */
reg [7:0] Bank;
/* Async. DRAM Address Bus */
input [1:0] CROW;
input [9:0] MAin;
input nFWE;
reg n8MEGEN = 0;
reg XOR8MEG = 0;
/* SDRAM Clock */
input RCLK;
/* SDRAM */
reg RCKEEN;
output reg RCKE = 0;
output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
output reg [1:0] RBA;
reg nRowColSel;
reg RA11;
reg RA10;
reg [9:0] RowA;
output [11:0] RA;
assign RA[11] = RA11;
assign RA[10] = RA10;
assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
output RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
output RDQMH = ~nRowColSel ? 1'b1 : MAin[9];
reg [7:0] WRD;
inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
/* UFM Interface */
reg nUFMCS = 1;
reg UFMCLK = 0;
reg UFMSDI = 0;
wire UFMSDO;
wire UFMOsc;
alta_ufms u_alta_ufms (
.i_ufm_set (1'b1),
.i_osc_ena (1'b1),
.i_ufm_flash_csn (nUFMCS),
.i_ufm_flash_sclk (UFMCLK),
.i_ufm_flash_sdi (UFMSDI),
.o_ufm_flash_sdo (UFMSDO),
.o_osc (UFMOsc)
);
/* UFM Command Interface */
reg C1Submitted = 0;
reg ADSubmitted = 0;
reg CmdEnable = 0;
reg CmdSubmitted = 0;
reg Cmdn8MEGEN = 0;
reg CmdUFMCLK = 0;
reg CmdUFMSDI = 0;
reg CmdUFMCS = 0;
wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
/* State Counters */
reg InitReady = 0; // 1 if ready for init sequence
reg Ready = 0; // 1 if done with init sequence
reg [1:0] S = 0; // post-RAS State counter
reg [17:0] FS = 0; // Fast init state counter
reg [3:0] IS = 0; // Init state counter
reg WriteDone;
/* Synchronize PHI2, RAS, CAS */
always @(posedge RCLK) begin
PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
end
/* Latch 65816 bank when PHI2 rises */
always @(posedge PHI2) begin
if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
else RA11 <= 1'b0; // Reserved in mode register
Bank[7:0] <= Din[7:0]; // Latch bank
end
/* Latch bank address, row address, WE, and CAS when RAS falls */
always @(negedge nCRAS) begin
if (Ready) begin
RBA[1:0] <= CROW[1:0];
RowA[9:0] <= MAin[9:0];
end else begin
RBA[1:0] <= 2'b00; // Reserved in mode register
RowA[9] <= 1'b1; // "1" for single write mode
RowA[8] <= 1'b0; // Reserved
RowA[7] <= 1'b0; // "0" for not test mode
RowA[6:4] <= 3'b010; // "2" for CAS latency 2
RowA[3] <= 1'b0; // "0" for sequential burst (not used)
RowA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
end
FWEr <= ~nFWE;
CBR <= ~nCCAS;
end
/* Latch write data when CAS falls */
always @(negedge nCCAS) begin
WRD[7:0] <= Din[7:0];
end
/* State counter from RAS */
always @(posedge RCLK) begin
if (~RASr2) S <= 0;
else if (S==2'h3) S <= 2'h3;
else S <= S+1;
end
/* Init state counter */
always @(posedge RCLK) begin
// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
FS <= FS+1;
if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
end
/* SDRAM CKE */
always @(posedge RCLK) begin
// Only 1 LUT4 allowed for this function!
RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
end
/* SDRAM command */
always @(posedge RCLK) begin
if (Ready) begin
if (S==0) begin
if (RASr2) begin
if (CBR) begin
// AREF
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b0;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end else begin
// ACT
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // Bank RA10 consistently "1"
end
// Enable clock only for reads
RCKEEN <= ~CBR & ~FWEr;
end else if (RCKE) begin
// PCall
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b1;
nRWE <= 1'b0;
RA10 <= 1'b1; // "all"
RCKEEN <= 1'b1;
end else begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
RCKEEN <= 1'b1;
end
nRowColSel <= 1'b0; // Select registered row addres
end else if (S==1) begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
nRowColSel <= 1'b1; // Select asynchronous column address
RCKEEN <= ~CBR; // Disable clock if refresh cycle
end else if (S==2) begin
if (~FWEr & ~CBR) begin
// RD
nRCS <= 1'b0;
nRRAS <= 1'b1;
nRCAS <= 1'b0;
nRWE <= 1'b1;
RA10 <= 1'b1; // Auto-precharge
end else begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end
nRowColSel <= 1'b1; // Select asynchronous column address
RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
end else if (S==3) begin
if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
// WR
nRCS <= 1'b0;
nRRAS <= 1'b1;
nRCAS <= 1'b0;
nRWE <= 1'b0;
RA10 <= 1'b1; // Auto-precharge
end else begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end
nRowColSel <= ~(~FWEr | CASr3 | CBR);
RCKEEN <= ~(~FWEr | CASr2 | CBR);
end
end else if (InitReady) begin
if (S==0 & RASr2) begin
if (IS==0) begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end else if (IS==1) begin
// PC all
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b1;
nRWE <= 1'b0;
RA10 <= 1'b1; // "all"
end else if (IS==9) begin
// Load mode register
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b0;
nRWE <= 1'b0;
RA10 <= 1'b0; // Reserved in mode register
end else begin
// AREF
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b0;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end
IS <= IS+1;
end else begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end
if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
nRowColSel <= 1'b0; // Select registered row address
RCKEEN <= 1'b1;
end else begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
nRowColSel <= 1'b0; // Select registered row address
RCKEEN <= 1'b0;
end
end
/* Submit command when PHI2 falls */
always @(negedge PHI2) begin
// Magic number check
if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
if (ADSubmitted) begin
CmdEnable <= 1'b1;
end
C1Submitted <= 1'b1;
ADSubmitted <= 1'b0;
end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
if (C1Submitted) begin
CmdEnable <= 1'b1;
end
ADSubmitted <= 1'b1;
C1Submitted <= 1'b0;
end else if (C1WR | ADWR) begin // wrong magic number submitted
CmdEnable <= 1'b0;
C1Submitted <= 1'b0;
ADSubmitted <= 1'b0;
end else if (CMDWR) CmdEnable <= 1'b0;
// Submit command
if (CMDWR & CmdEnable) begin
if (Din[7:4]==4'h0) begin
XOR8MEG <= Din[0];
end else if (Din[7:4]==4'h1) begin
Cmdn8MEGEN <= ~Din[0];
CmdSubmitted <= 1'b1;
end else if (Din[7:4]==4'h3) begin
Cmdn8MEGEN <= n8MEGEN;
CmdUFMCS <= Din[2];
CmdUFMCLK <= Din[1];
CmdUFMSDI <= Din[0];
CmdSubmitted <= 1'b1;
end
end
end
/* UFM Control */
output nUFMCSout = nUFMCS;
output UFMCLKout = UFMCLK;
output UFMSDIout = UFMSDI;
output UFMSDOout = UFMSDO;
input nUFMCSin;
input UFMCLKin;
input UFMSDIin;
input UFMSDOin;
always @(posedge RCLK) begin
if (~InitReady && FS[17:10]==8'h00) begin
nUFMCS <= 1'b1;
UFMCLK <= 1'b0;
UFMSDI <= 1'b0;
end else if (~InitReady && FS[17:10]==8'h01) begin
nUFMCS <= 1'b0;
UFMCLK <= 1'b0;
UFMSDI <= 1'b0;
end else if (~InitReady && FS[17:10]==8'h02) begin
nUFMCS <= 1'b0;
UFMCLK <= FS[4];
case (FS[9:5]) // Shift out read data command (0x03)
5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
endcase
end else if (~InitReady && FS[17:10]==8'h03) begin
nUFMCS <= 1'b0;
UFMCLK <= 1'b0;
UFMSDI <= 1'b0;
// Latch n8MEGEN
if (FS[9:4]==6'h00 && FS[3:0]==4'hF) n8MEGEN <= ~UFMSDO;
end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
nUFMCS <= 1'b0;
UFMCLK <= FS[1];
UFMSDI <= 1'b0;
end else if (~InitReady) begin
nUFMCS <= 1'b1;
UFMCLK <= 1'b0;
UFMSDI <= 1'b0;
end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
// Set user command signals after PHI2 falls
// Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
n8MEGEN <= Cmdn8MEGEN;
nUFMCS <= ~CmdUFMCS;
UFMCLK <= CmdUFMCLK;
UFMSDI <= CmdUFMSDI;
end
end
endmodule
Hardware/AGM/cpld-src/constraints.sdc
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485253603 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:53 2020 " "Processing started: Thu Jul 23 02:20:53 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485254775 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485254806 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:55 2020 " "Processing ended: Thu Jul 23 02:20:55 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485255322 ""}
Hardware/AGM/cpld-src/db/RAM4GS.asm.rdb
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595485244993 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595485245024 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595485245680 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595485245711 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595485246102 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595485246305 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595485246336 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595485246383 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595485246383 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595485246399 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246415 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246430 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246446 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246461 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595485246493 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595485246555 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595485246555 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246633 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246649 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595485246665 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595485246665 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485246712 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595485247071 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485247462 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595485247477 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595485248884 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485248899 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595485248946 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595485249462 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595485249462 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250243 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485250259 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250275 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485250290 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485250525 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:50 2020 " "Processing ended: Thu Jul 23 02:20:50 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485250759 ""}
Hardware/AGM/cpld-src/db/RAM4GS.hier_info
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|RAM4GS
PHI2 => Bank[0].CLK
PHI2 => Bank[1].CLK
PHI2 => Bank[2].CLK
PHI2 => Bank[3].CLK
PHI2 => Bank[4].CLK
PHI2 => Bank[5].CLK
PHI2 => Bank[6].CLK
PHI2 => Bank[7].CLK
PHI2 => RA11.CLK
PHI2 => PHI2r.DATAIN
PHI2 => CmdDRDIn.CLK
PHI2 => CmdDRCLK.CLK
PHI2 => CmdUFMPrgm.CLK
PHI2 => CmdUFMErase.CLK
PHI2 => CmdSubmitted.CLK
PHI2 => Cmdn8MEGEN.CLK
PHI2 => XOR8MEG.CLK
PHI2 => ADSubmitted.CLK
PHI2 => C1Submitted.CLK
PHI2 => UFMOscEN.CLK
PHI2 => CmdEnable.CLK
MAin[0] => RA.DATAA
MAin[0] => RowA.DATAB
MAin[0] => Equal0.IN7
MAin[0] => Equal1.IN7
MAin[0] => Equal3.IN6
MAin[1] => RA.DATAA
MAin[1] => RowA.DATAB
MAin[1] => Equal0.IN6
MAin[1] => Equal1.IN6
MAin[1] => Equal3.IN7
MAin[2] => RA.DATAA
MAin[2] => RowA.DATAB
MAin[2] => Equal0.IN5
MAin[2] => Equal1.IN5
MAin[2] => Equal3.IN5
MAin[3] => RA.DATAA
MAin[3] => RowA.DATAB
MAin[3] => Equal0.IN4
MAin[3] => Equal1.IN4
MAin[3] => Equal3.IN4
MAin[4] => RA.DATAA
MAin[4] => RowA.DATAB
MAin[4] => Equal0.IN3
MAin[4] => Equal1.IN3
MAin[4] => Equal3.IN3
MAin[5] => RA.DATAA
MAin[5] => RowA.DATAB
MAin[5] => Equal0.IN2
MAin[5] => Equal1.IN2
MAin[5] => Equal3.IN2
MAin[6] => RA.DATAA
MAin[6] => RowA.DATAB
MAin[6] => Equal0.IN1
MAin[6] => Equal1.IN1
MAin[6] => Equal3.IN1
MAin[7] => RA.DATAA
MAin[7] => RowA.DATAB
MAin[7] => Equal0.IN0
MAin[7] => Equal1.IN0
MAin[7] => Equal3.IN0
MAin[8] => RA.DATAA
MAin[8] => RowA.DATAB
MAin[9] => RA.DATAA
MAin[9] => comb.DATAA
MAin[9] => RowA.DATAB
MAin[9] => comb.DATAA
CROW[0] => RBA.DATAB
CROW[1] => RBA.DATAB
Din[0] => CmdDRDIn.DATAB
Din[0] => XOR8MEG.DATAB
Din[0] => WRD[0].DATAIN
Din[0] => Bank[0].DATAIN
Din[0] => Equal14.IN2
Din[0] => Equal15.IN4
Din[0] => Cmdn8MEGEN.DATAB
Din[1] => CmdDRCLK.DATAB
Din[1] => WRD[1].DATAIN
Din[1] => Bank[1].DATAIN
Din[1] => Equal14.IN7
Din[1] => Equal15.IN7
Din[2] => CmdUFMPrgm.DATAB
Din[2] => WRD[2].DATAIN
Din[2] => Bank[2].DATAIN
Din[2] => Equal14.IN6
Din[2] => Equal15.IN3
Din[3] => CmdUFMErase.DATAB
Din[3] => WRD[3].DATAIN
Din[3] => Bank[3].DATAIN
Din[3] => Equal14.IN5
Din[3] => Equal15.IN2
Din[4] => WRD[4].DATAIN
Din[4] => Bank[4].DATAIN
Din[4] => Equal14.IN4
Din[4] => Equal15.IN6
Din[4] => Equal16.IN3
Din[4] => Equal17.IN0
Din[4] => Equal18.IN3
Din[5] => WRD[5].DATAIN
Din[5] => Bank[5].DATAIN
Din[5] => Equal14.IN3
Din[5] => Equal15.IN1
Din[5] => Equal16.IN2
Din[5] => Equal17.IN3
Din[5] => Equal18.IN0
Din[6] => RA11.IN1
Din[6] => WRD[6].DATAIN
Din[6] => Bank[6].DATAIN
Din[6] => Equal14.IN1
Din[6] => Equal15.IN5
Din[6] => Equal16.IN1
Din[6] => Equal17.IN2
Din[6] => Equal18.IN2
Din[7] => WRD[7].DATAIN
Din[7] => Bank[7].DATAIN
Din[7] => Equal14.IN0
Din[7] => Equal15.IN0
Din[7] => Equal16.IN0
Din[7] => Equal17.IN1
Din[7] => Equal18.IN1
Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE
Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE
Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE
Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE
Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE
Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE
Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE
Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE
nCCAS => WRD[0].CLK
nCCAS => WRD[1].CLK
nCCAS => WRD[2].CLK
nCCAS => WRD[3].CLK
nCCAS => WRD[4].CLK
nCCAS => WRD[5].CLK
nCCAS => WRD[6].CLK
nCCAS => WRD[7].CLK
nCCAS => comb.IN0
nCCAS => CBR.DATAIN
nCCAS => CASr.DATAIN
nCRAS => CBR.CLK
nCRAS => FWEr.CLK
nCRAS => RowA[0].CLK
nCRAS => RowA[1].CLK
nCRAS => RowA[2].CLK
nCRAS => RowA[3].CLK
nCRAS => RowA[4].CLK
nCRAS => RowA[5].CLK
nCRAS => RowA[6].CLK
nCRAS => RowA[7].CLK
nCRAS => RowA[8].CLK
nCRAS => RowA[9].CLK
nCRAS => RBA[0]~reg0.CLK
nCRAS => RBA[1]~reg0.CLK
nCRAS => RASr.DATAIN
nFWE => comb.IN1
nFWE => CMDWR.IN1
nFWE => ADWR.IN1
nFWE => C1WR.IN1
nFWE => FWEr.DATAIN
RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE
RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE
RD[0] <> RD[0]
RD[1] <> RD[1]
RD[2] <> RD[2]
RD[3] <> RD[3]
RD[4] <> RD[4]
RD[5] <> RD[5]
RD[6] <> RD[6]
RD[7] <> RD[7]
nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
RCLK => UFMProgram.CLK
RCLK => UFMErase.CLK
RCLK => UFMReqErase.CLK
RCLK => n8MEGEN.CLK
RCLK => UFMInitDone.CLK
RCLK => UFMD.CLK
RCLK => DRShift.CLK
RCLK => DRDIn.CLK
RCLK => DRCLK.CLK
RCLK => ARShift.CLK
RCLK => ARCLK.CLK
RCLK => Ready.CLK
RCLK => IS[0].CLK
RCLK => IS[1].CLK
RCLK => IS[2].CLK
RCLK => IS[3].CLK
RCLK => nRowColSel.CLK
RCLK => RCKEEN.CLK
RCLK => RA10.CLK
RCLK => nRWE~reg0.CLK
RCLK => nRCAS~reg0.CLK
RCLK => nRRAS~reg0.CLK
RCLK => nRCS~reg0.CLK
RCLK => RCKE~reg0.CLK
RCLK => InitReady.CLK
RCLK => FS[0].CLK
RCLK => FS[1].CLK
RCLK => FS[2].CLK
RCLK => FS[3].CLK
RCLK => FS[4].CLK
RCLK => FS[5].CLK
RCLK => FS[6].CLK
RCLK => FS[7].CLK
RCLK => FS[8].CLK
RCLK => FS[9].CLK
RCLK => FS[10].CLK
RCLK => FS[11].CLK
RCLK => FS[12].CLK
RCLK => FS[13].CLK
RCLK => FS[14].CLK
RCLK => FS[15].CLK
RCLK => FS[16].CLK
RCLK => FS[17].CLK
RCLK => S[0].CLK
RCLK => S[1].CLK
RCLK => CASr3.CLK
RCLK => CASr2.CLK
RCLK => CASr.CLK
RCLK => RASr3.CLK
RCLK => RASr2.CLK
RCLK => RASr.CLK
RCLK => PHI2r3.CLK
RCLK => PHI2r2.CLK
RCLK => PHI2r.CLK
RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDQMH <= comb.DB_MAX_OUTPUT_PORT_TYPE
RDQML <= comb.DB_MAX_OUTPUT_PORT_TYPE
|RAM4GS|UFM:UFM_inst
arclk => arclk.IN1
ardin => ardin.IN1
arshft => arshft.IN1
drclk => drclk.IN1
drdin => drdin.IN1
drshft => drshft.IN1
erase => erase.IN1
oscena => oscena.IN1
program => program.IN1
busy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.busy
drdout <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.drdout
osc <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.osc
rtpbusy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.rtpbusy
|RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component
arclk => maxii_ufm_block1.ARCLK
ardin => maxii_ufm_block1.ARDIN
arshft => maxii_ufm_block1.ARSHFT
busy <= maxii_ufm_block1.BUSY
drclk => maxii_ufm_block1.DRCLK
drdin => maxii_ufm_block1.DRDIN
drdout <= maxii_ufm_block1.DRDOUT
drshft => maxii_ufm_block1.DRSHFT
erase => maxii_ufm_block1.ERASE
osc <= maxii_ufm_block1.OSC
oscena => maxii_ufm_block1.OSCENA
program => maxii_ufm_block1.PROGRAM
rtpbusy <= maxii_ufm_block1.BGPBUSY
Hardware/AGM/cpld-src/db/RAM4GS.hif
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Hardware/AGM/cpld-src/db/RAM4GS.ipinfo
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Hardware/AGM/cpld-src/db/RAM4GS.lpc.html
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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >UFM_inst|UFM_altufm_none_1br_component</TD>
<TD >9</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >UFM_inst</TD>
<TD >9</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >4</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>
Hardware/AGM/cpld-src/db/RAM4GS.lpc.rdb
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Hardware/AGM/cpld-src/db/RAM4GS.lpc.txt
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; UFM_inst|UFM_altufm_none_1br_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; UFM_inst ; 9 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
Hardware/AGM/cpld-src/db/RAM4GS.map.cdb
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Hardware/AGM/cpld-src/db/RAM4GS.map.logdb
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v1
Hardware/AGM/cpld-src/db/RAM4GS.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485235413 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:35 2020 " "Processing started: Thu Jul 23 02:20:35 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485237304 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595485237601 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595485238085 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238195 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238320 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595485240523 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595485240523 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595485240929 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:41 2020 " "Processing ended: Thu Jul 23 02:20:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""}
Hardware/AGM/cpld-src/db/RAM4GS.map.rdb
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Hardware/AGM/cpld-src/db/RAM4GS.sta.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485258541 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:57 2020 " "Processing started: Thu Jul 23 02:20:57 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485258573 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485258791 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485259791 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485260260 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485260838 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485261042 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485261120 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485261260 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261339 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261354 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485261854 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "288 " "Peak virtual memory: 288 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:21:02 2020 " "Processing ended: Thu Jul 23 02:21:02 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""}
Hardware/AGM/cpld-src/db/RAM4GS.sta.rdb
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484987367 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:27 2020 " "Processing started: Thu Jul 23 02:16:27 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595484989226 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595484989445 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989617 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989633 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595484989805 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484989883 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484990008 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595484991726 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595484991726 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595484992133 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:32 2020 " "Processing ended: Thu Jul 23 02:16:32 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484995336 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:33 2020 " "Processing started: Thu Jul 23 02:16:33 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1595484995351 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1595484995367 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1595484995523 ""}
{ "Info" "0" "" "Project = RAM4GS" { } { } 0 0 "Project = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""}
{ "Info" "0" "" "Revision = RAM4GS" { } { } 0 0 "Revision = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595484996148 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595484996164 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595484996648 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595484996679 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595484996992 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595484997164 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595484997179 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595484997210 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595484997210 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997210 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997226 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997226 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595484997273 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595484997320 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595484997320 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997382 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997398 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595484997414 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595484997414 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484997445 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595484997742 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484998117 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595484998132 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595484999460 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484999460 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595484999507 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595484999976 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595484999976 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000632 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.50 " "Total time spent on timing analysis during the Fitter is 0.50 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485000663 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000679 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485000742 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485001117 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:41 2020 " "Processing ended: Thu Jul 23 02:16:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485001429 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1595485004085 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:43 2020 " "Processing started: Thu Jul 23 02:16:43 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485005116 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485005148 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:45 2020 " "Processing ended: Thu Jul 23 02:16:45 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485005632 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1595485006413 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1595485008366 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:47 2020 " "Processing started: Thu Jul 23 02:16:47 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485008413 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485008601 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485009444 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485009898 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485010507 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485010726 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485010773 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485010851 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010913 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010929 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485011241 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:51 2020 " "Processing ended: Thu Jul 23 02:16:51 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus II Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485012647 ""}
Hardware/AGM/cpld-src/greybox_tmp/cbx_args.txt
-26
View File
@@ -1,26 +0,0 @@
ERASE_TIME=500000000
INTENDED_DEVICE_FAMILY="MAX II"
LPM_FILE=RAM4GS.mif
LPM_HINT=UNUSED
LPM_TYPE=altufm_none
OSC_FREQUENCY=180000
PORT_ARCLKENA=PORT_UNUSED
PORT_DRCLKENA=PORT_UNUSED
PROGRAM_TIME=1600000
WIDTH_UFM_ADDRESS=9
DEVICE_FAMILY="MAX II"
CBX_AUTO_BLACKBOX=ALL
CBX_AUTO_BLACKBOX=ALL
arclk
ardin
arshft
busy
drclk
drdin
drdout
drshft
erase
osc
oscena
program
rtpbusy
Hardware/AGM/cpld-src/incremental_db/README
-11
View File
@@ -1,11 +0,0 @@
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
Hardware/AGM/cpld-src/incremental_db/compiled_partitions/RAM4GS.db_info
-3
View File
@@ -1,3 +0,0 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Mon Jun 15 13:43:18 2020
Hardware/AGM/cpld-src/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt
BIN
View File
Binary file not shown.
Hardware/AGM/cpld-src/output_files/RAM4GS.asm.rpt
-114
View File
@@ -1,114 +0,0 @@
Assembler report for RAM4GS
Thu Jul 23 02:20:55 2020
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: /Repos/RAM4GS/cpld/output_files/RAM4GS.pof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Jul 23 02:20:55 2020 ;
; Revision Name ; RAM4GS ;
; Top-level Entity Name ; RAM4GS ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
+-----------------------+---------------------------------------+
+---------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+-----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+-----------+---------------+
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; On ; On ;
; Security bit ; Off ; Off ;
; Use configuration device ; On ; On ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
; In-System Programming Default Clamp State ; Tri-state ; Tri-state ;
+-----------------------------------------------------------------------------+-----------+---------------+
+--------------------------------------------+
; Assembler Generated Files ;
+--------------------------------------------+
; File Name ;
+--------------------------------------------+
; /Repos/RAM4GS/cpld/output_files/RAM4GS.pof ;
+--------------------------------------------+
+----------------------------------------------------------------------+
; Assembler Device Options: /Repos/RAM4GS/cpld/output_files/RAM4GS.pof ;
+----------------+-----------------------------------------------------+
; Option ; Setting ;
+----------------+-----------------------------------------------------+
; Device ; EPM240T100C5 ;
; JTAG usercode ; 0x00173F26 ;
; Checksum ; 0x0017428E ;
+----------------+-----------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Jul 23 02:20:53 2020
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 296 megabytes
Info: Processing ended: Thu Jul 23 02:20:55 2020
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
Hardware/AGM/cpld-src/output_files/RAM4GS.cdf
-13
View File
@@ -1,13 +0,0 @@
/* Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPM240T100) Path("Z:/Repos/RAM4GS/cpld/output_files/") File("RAM4GS.pof") MfrSpec(OpMask(3) SEC_Device(EPM240T100) Child_OpMask(2 3 3));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;
Hardware/AGM/cpld-src/output_files/RAM4GS.done
-1
View File
@@ -1 +0,0 @@
Thu Jul 23 02:21:03 2020
Hardware/AGM/cpld-src/output_files/RAM4GS.fit.rpt
-993
View File
@@ -1,993 +0,0 @@
Fitter report for RAM4GS
Thu Jul 23 02:20:50 2020
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
5. Pin-Out File
6. Fitter Resource Usage Summary
7. Input Pins
8. Output Pins
9. Bidir Pins
10. I/O Bank Usage
11. All Package Pins
12. Output Pin Default Load For Reported TCO
13. Fitter Resource Utilization by Entity
14. Delay Chain Summary
15. Control Signals
16. Global & Other Fast Signals
17. Non-Global High Fan-Out Signals
18. Other Routing Usage Summary
19. LAB Logic Elements
20. LAB-wide Signals
21. LAB Signals Sourced
22. LAB Signals Sourced Out
23. LAB Distinct Inputs
24. Fitter Device Options
25. Estimated Delay Added for Hold Timing Summary
26. Estimated Delay Added for Hold Timing Details
27. Fitter Messages
28. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Thu Jul 23 02:20:50 2020 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM4GS ;
; Top-level Entity Name ; RAM4GS ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 170 / 240 ( 71 % ) ;
; Total pins ; 62 / 80 ( 78 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+---------------------------+-------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EPM240T100C5 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Placement Effort Multiplier ; 10 ; 1.0 ;
; Router Effort Multiplier ; 10 ; 1.0 ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Device I/O Standard ; 3.3-V LVTTL ; ;
; Optimize Multi-Corner Timing ; On ; Off ;
; Optimize IOC Register Placement for Timing ; Pack All IO Registers ; Normal ;
; Enable Bus-Hold Circuitry ; On ; Off ;
; Fitter Effort ; Standard Fit ; Auto Fit ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Always Enable Input Buffers ; Off ; Off ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize Timing for ECOs ; Off ; Off ;
; Regenerate full fit report during ECO compiles ; Off ; Off ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Auto Delay Chains ; On ; On ;
; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Auto ; Auto ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.33 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 33.3% ;
+----------------------------+-------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.pin.
+------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+--------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------+
; Total logic elements ; 170 / 240 ( 71 % ) ;
; -- Combinational with no register ; 74 ;
; -- Register only ; 21 ;
; -- Combinational with a register ; 75 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 57 ;
; -- 3 input functions ; 41 ;
; -- 2 input functions ; 42 ;
; -- 1 input functions ; 8 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 154 ;
; -- arithmetic mode ; 16 ;
; -- qfbk mode ; 6 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 25 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 96 / 240 ( 40 % ) ;
; Total LABs ; 22 / 24 ( 92 % ) ;
; Logic elements in carry chains ; 17 ;
; Virtual pins ; 0 ;
; I/O pins ; 62 / 80 ( 78 % ) ;
; -- Clock pins ; 2 / 4 ( 50 % ) ;
; ; ;
; Global signals ; 4 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 25% / 27% / 23% ;
; Peak interconnect usage (total/H/V) ; 25% / 27% / 23% ;
; Maximum fan-out ; 54 ;
; Highest non-global fan-out ; 38 ;
; Total fan-out ; 644 ;
; Average fan-out ; 2.76 ;
+---------------------------------------------+--------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; CROW[0] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 4 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 5 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 7 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 7 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 6 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; MAin[2] ; 50 ; 1 ; 7 ; 0 ; 1 ; 3 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; MAin[3] ; 71 ; 2 ; 8 ; 4 ; 3 ; 3 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; MAin[4] ; 70 ; 2 ; 8 ; 4 ; 4 ; 3 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; MAin[5] ; 69 ; 2 ; 8 ; 3 ; 0 ; 3 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 4 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 4 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 21 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 54 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; nCCAS ; 53 ; 2 ; 8 ; 1 ; 3 ; 11 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 15 ; 0 ; yes ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 3 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; User ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Dout[0] ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; Dout[1] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; Dout[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; Dout[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; Dout[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; Dout[5] ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; Dout[6] ; 34 ; 1 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Bidir Pins ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~2 ; - ;
; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+-------------------------------------------------------------+
; I/O Bank Usage ;
+----------+-------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+-------------------+---------------+--------------+
; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ;
; 2 ; 24 / 42 ( 57 % ) ; 3.3V ; -- ;
+----------+-------------------+---------------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
; 1 ; 83 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 2 ; 0 ; 1 ; RDQMH ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 3 ; 1 ; 1 ; nRCS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 4 ; 2 ; 1 ; nRCAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 5 ; 3 ; 1 ; RBA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 6 ; 4 ; 1 ; nRRAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 7 ; 5 ; 1 ; RA[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 8 ; 6 ; 1 ; RCKE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 12 ; 7 ; 1 ; RCLK ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 14 ; 8 ; 1 ; RBA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 15 ; 9 ; 1 ; RA[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 16 ; 10 ; 1 ; RA[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 17 ; 11 ; 1 ; RA[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 18 ; 12 ; 1 ; RA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 19 ; 13 ; 1 ; RA[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 20 ; 14 ; 1 ; RA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 21 ; 15 ; 1 ; RA[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 26 ; 20 ; 1 ; RA[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 27 ; 21 ; 1 ; RA[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 28 ; 22 ; 1 ; Dout[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 29 ; 23 ; 1 ; RA[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 30 ; 24 ; 1 ; RA[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 33 ; 25 ; 1 ; Dout[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 34 ; 26 ; 1 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 35 ; 27 ; 1 ; Din[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 36 ; 28 ; 1 ; Din[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 37 ; 29 ; 1 ; Din[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 38 ; 30 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 39 ; 31 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 40 ; 32 ; 1 ; Din[7] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 41 ; 33 ; 1 ; Din[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 42 ; 34 ; 1 ; Din[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 43 ; 35 ; 1 ; Dout[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 44 ; 36 ; 1 ; Dout[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 47 ; 37 ; 1 ; Dout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 48 ; 38 ; 1 ; nFWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 49 ; 39 ; 1 ; MAin[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 50 ; 40 ; 1 ; MAin[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 51 ; 41 ; 1 ; MAin[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 52 ; 42 ; 2 ; PHI2 ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 53 ; 43 ; 2 ; nCCAS ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 54 ; 44 ; 2 ; CROW[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 55 ; 45 ; 2 ; CROW[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 56 ; 46 ; 2 ; Dout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 57 ; 47 ; 2 ; Dout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 58 ; 48 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 62 ; 50 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 67 ; 53 ; 2 ; nCRAS ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 68 ; 54 ; 2 ; MAin[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 69 ; 55 ; 2 ; MAin[5] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 70 ; 56 ; 2 ; MAin[4] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 71 ; 57 ; 2 ; MAin[3] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 72 ; 58 ; 2 ; MAin[6] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 73 ; 59 ; 2 ; MAin[8] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 74 ; 60 ; 2 ; MAin[9] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; yes ; Off ;
; 75 ; 61 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 76 ; 62 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 77 ; 63 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 84 ; 68 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 85 ; 69 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 89 ; 73 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 92 ; 76 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 96 ; 78 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 97 ; 79 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 98 ; 80 ; 2 ; RDQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 99 ; 81 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 100 ; 82 ; 2 ; nRWE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+-------------------------------------------------------------+
; Output Pin Default Load For Reported TCO ;
+----------------------------+-------+------------------------+
; I/O Standard ; Load ; Termination Resistance ;
+----------------------------+-------+------------------------+
; 3.3-V LVTTL ; 10 pF ; Not Available ;
; 3.3-V LVCMOS ; 10 pF ; Not Available ;
; 2.5 V ; 10 pF ; Not Available ;
; 1.8 V ; 10 pF ; Not Available ;
; 1.5 V ; 10 pF ; Not Available ;
; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ;
; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ;
+----------------------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; |RAM4GS ; 170 (170) ; 96 ; 1 ; 62 ; 0 ; 74 (74) ; 21 (21) ; 75 (75) ; 17 (17) ; 6 (6) ; |RAM4GS ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst ; work ;
; |UFM_altufm_none_1br:UFM_altufm_none_1br_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------+
; Delay Chain Summary ;
+---------+----------+---------------+
; Name ; Pin Type ; Pad to Core 0 ;
+---------+----------+---------------+
; MAin[0] ; Input ; (0) ;
; MAin[1] ; Input ; (0) ;
; MAin[2] ; Input ; (0) ;
; MAin[3] ; Input ; (0) ;
; MAin[4] ; Input ; (0) ;
; MAin[5] ; Input ; (0) ;
; MAin[6] ; Input ; (0) ;
; MAin[7] ; Input ; (0) ;
; MAin[8] ; Input ; (0) ;
; MAin[9] ; Input ; (0) ;
; CROW[0] ; Input ; (1) ;
; nCRAS ; Input ; (0) ;
; CROW[1] ; Input ; (1) ;
; RCLK ; Input ; (0) ;
; PHI2 ; Input ; (0) ;
; Din[6] ; Input ; (1) ;
; nFWE ; Input ; (1) ;
; Din[0] ; Input ; (1) ;
; Din[7] ; Input ; (1) ;
; Din[1] ; Input ; (1) ;
; Din[4] ; Input ; (1) ;
; Din[5] ; Input ; (1) ;
; Din[2] ; Input ; (1) ;
; Din[3] ; Input ; (1) ;
; nCCAS ; Input ; (0) ;
; Dout[0] ; Output ; -- ;
; Dout[1] ; Output ; -- ;
; Dout[2] ; Output ; -- ;
; Dout[3] ; Output ; -- ;
; Dout[4] ; Output ; -- ;
; Dout[5] ; Output ; -- ;
; Dout[6] ; Output ; -- ;
; Dout[7] ; Output ; -- ;
; RBA[0] ; Output ; -- ;
; RBA[1] ; Output ; -- ;
; RA[0] ; Output ; -- ;
; RA[1] ; Output ; -- ;
; RA[2] ; Output ; -- ;
; RA[3] ; Output ; -- ;
; RA[4] ; Output ; -- ;
; RA[5] ; Output ; -- ;
; RA[6] ; Output ; -- ;
; RA[7] ; Output ; -- ;
; RA[8] ; Output ; -- ;
; RA[9] ; Output ; -- ;
; RA[10] ; Output ; -- ;
; RA[11] ; Output ; -- ;
; nRCS ; Output ; -- ;
; RCKE ; Output ; -- ;
; nRWE ; Output ; -- ;
; nRRAS ; Output ; -- ;
; nRCAS ; Output ; -- ;
; RDQMH ; Output ; -- ;
; RDQML ; Output ; -- ;
; RD[0] ; Bidir ; (0) ;
; RD[1] ; Bidir ; (0) ;
; RD[2] ; Bidir ; (0) ;
; RD[3] ; Bidir ; (0) ;
; RD[4] ; Bidir ; (0) ;
; RD[5] ; Bidir ; (0) ;
; RD[6] ; Bidir ; (0) ;
; RD[7] ; Bidir ; (0) ;
+---------+----------+---------------+
+---------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; CmdDRDIn~1 ; LC_X6_Y3_N3 ; 4 ; Clock enable ; no ; -- ; -- ;
; CmdSubmitted~0 ; LC_X6_Y3_N9 ; 2 ; Clock enable ; no ; -- ; -- ;
; DRDIn~1 ; LC_X2_Y1_N3 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI2 ; PIN_52 ; 21 ; Clock ; yes ; Global Clock ; GCLK3 ;
; RCLK ; PIN_12 ; 54 ; Clock ; yes ; Global Clock ; GCLK0 ;
; Ready ; LC_X3_Y2_N1 ; 38 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; always8~5 ; LC_X5_Y3_N0 ; 3 ; Clock enable ; no ; -- ; -- ;
; comb~2 ; LC_X4_Y4_N6 ; 8 ; Output enable ; no ; -- ; -- ;
; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ;
; nCRAS ; PIN_67 ; 15 ; Clock ; yes ; Global Clock ; GCLK1 ;
+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+----------------------------------------------------------------------+
; Global & Other Fast Signals ;
+-------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-------+----------+---------+----------------------+------------------+
; PHI2 ; PIN_52 ; 21 ; Global Clock ; GCLK3 ;
; RCLK ; PIN_12 ; 54 ; Global Clock ; GCLK0 ;
; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK2 ;
; nCRAS ; PIN_67 ; 15 ; Global Clock ; GCLK1 ;
+-------+----------+---------+----------------------+------------------+
+-------------------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals ;
+---------------------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+---------------------------------------------------------------------------------------------+---------+
; Ready ; 38 ;
; nRowColSel ; 13 ;
; S[1] ; 12 ;
; S[0] ; 12 ;
; RASr2 ; 9 ;
; Din[6] ; 8 ;
; comb~2 ; 8 ;
; FS[4] ; 8 ;
; Din[5] ; 7 ;
; Din[4] ; 7 ;
; FS[5] ; 7 ;
; IS[0]~0 ; 7 ;
; Din[7] ; 6 ;
; Din[0] ; 6 ;
; MAin[1] ; 6 ;
; FS[6] ; 6 ;
; always9~1 ; 6 ;
; IS[0] ; 6 ;
; Din[3] ; 5 ;
; Din[2] ; 5 ;
; MAin[0] ; 5 ;
; FS[8]~27 ; 5 ;
; FS[3]~13 ; 5 ;
; FS[3] ; 5 ;
; always9~2 ; 5 ;
; FS[17] ; 5 ;
; FS[16] ; 5 ;
; IS[1] ; 5 ;
; CBR ; 5 ;
; FWEr ; 5 ;
; Din[1] ; 4 ;
; MAin[9] ; 4 ;
; MAin[7] ; 4 ;
; MAin[6] ; 4 ;
; CmdDRDIn~1 ; 4 ;
; UFMD ; 4 ;
; FS[13]~21 ; 4 ;
; CMDWR~2 ; 4 ;
; UFMReqErase ; 4 ;
; Equal9~0 ; 4 ;
; n8MEGEN ; 4 ;
; IS[3] ; 4 ;
; IS[2] ; 4 ;
; InitReady ; 4 ;
; nFWE ; 3 ;
; MAin[5] ; 3 ;
; MAin[4] ; 3 ;
; MAin[3] ; 3 ;
; MAin[2] ; 3 ;
; FS[0] ; 3 ;
; always8~5 ; 3 ;
; CMDWR ; 3 ;
; CmdEnable ; 3 ;
; always8~4 ; 3 ;
; always8~2 ; 3 ;
; Equal0~0 ; 3 ;
; always9~3 ; 3 ;
; UFMInitDone ; 3 ;
; nRCS~3 ; 3 ;
; RCKE~reg0 ; 3 ;
; MAin[8] ; 2 ;
; FS[1] ; 2 ;
; FS[2] ; 2 ;
; Equal25~0 ; 2 ;
; FS[9] ; 2 ;
; FS[8] ; 2 ;
; CmdSubmitted~0 ; 2 ;
; Equal17~0 ; 2 ;
; CmdDRDIn~0 ; 2 ;
; XOR8MEG~0 ; 2 ;
; Equal0~3 ; 2 ;
; Equal5~1 ; 2 ;
; FS[15] ; 2 ;
; FS[14] ; 2 ;
; FS[13] ; 2 ;
; FS[12] ; 2 ;
; FS[11] ; 2 ;
; FS[10] ; 2 ;
; Ready~0 ; 2 ;
; UFMOscEN~0 ; 2 ;
; C1Submitted ; 2 ;
; Equal0~1 ; 2 ;
; always8~0 ; 2 ;
; CmdUFMErase ; 2 ;
; CmdUFMPrgm ; 2 ;
; always9~6 ; 2 ;
; always9~5 ; 2 ;
; ARCLK~1 ; 2 ;
; always9~4 ; 2 ;
; DRDIn~1 ; 2 ;
; FS[7] ; 2 ;
; always9~0 ; 2 ;
; PHI2r2 ; 2 ;
; RASr ; 2 ;
; RCKEEN ; 2 ;
; CASr2 ; 2 ;
; nRRAS~0 ; 2 ;
; nRCS~1 ; 2 ;
; nRCS~0 ; 2 ;
; XOR8MEG ; 2 ;
; RA10~0 ; 2 ;
; nRowColSel~0 ; 2 ;
; UFMOscEN ; 2 ;
; UFMErase ; 2 ;
; UFMProgram ; 2 ;
; ARShift ; 2 ;
; ARCLK ; 2 ;
; DRShift ; 2 ;
; UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component|wire_maxii_ufm_block1_drdout ; 2 ;
; UFMProgram~_wirecell ; 1 ;
; UFMOscEN~_wirecell ; 1 ;
; UFMErase~_wirecell ; 1 ;
; RD[7]~7 ; 1 ;
; RD[6]~6 ; 1 ;
; RD[5]~5 ; 1 ;
; RD[4]~4 ; 1 ;
; RD[3]~3 ; 1 ;
; RD[2]~2 ; 1 ;
; RD[1]~1 ; 1 ;
; RD[0]~0 ; 1 ;
; CROW[1] ; 1 ;
; CROW[0] ; 1 ;
; CmdEnable~1 ; 1 ;
; CmdEnable~0 ; 1 ;
; UFMD~1 ; 1 ;
; FS[1]~33COUT1_50 ; 1 ;
; FS[1]~33 ; 1 ;
; UFMD~0 ; 1 ;
; UFMReqErase~0 ; 1 ;
; FS[2]~31COUT1_52 ; 1 ;
; FS[2]~31 ; 1 ;
; FS[9]~29COUT1_62 ; 1 ;
; FS[9]~29 ; 1 ;
; UFMInitDone~0 ; 1 ;
; PHI2r ; 1 ;
; RCKEEN~2 ; 1 ;
; RCKEEN~1 ; 1 ;
; RCKEEN~0 ; 1 ;
; CASr ; 1 ;
; Equal16~0 ; 1 ;
; n8MEGEN~0 ; 1 ;
; Cmdn8MEGEN ; 1 ;
; IS[0]~3 ; 1 ;
; FS[15]~25COUT1_72 ; 1 ;
; FS[15]~25 ; 1 ;
; FS[14]~23COUT1_70 ; 1 ;
; FS[14]~23 ; 1 ;
; Equal5~0 ; 1 ;
; FS[12]~19COUT1_68 ; 1 ;
; FS[12]~19 ; 1 ;
; FS[11]~17COUT1_66 ; 1 ;
; FS[11]~17 ; 1 ;
; FS[10]~15COUT1_64 ; 1 ;
; FS[10]~15 ; 1 ;
; Ready~1 ; 1 ;
; WRD[7] ; 1 ;
; WRD[6] ; 1 ;
; WRD[5] ; 1 ;
; WRD[4] ; 1 ;
; WRD[3] ; 1 ;
; WRD[2] ; 1 ;
; WRD[1] ; 1 ;
; WRD[0] ; 1 ;
; ADSubmitted ; 1 ;
; always8~3 ; 1 ;
; Equal0~2 ; 1 ;
; always8~1 ; 1 ;
; Equal1~0 ; 1 ;
; CMDWR~1 ; 1 ;
; Bank[7] ; 1 ;
; Bank[6] ; 1 ;
; Bank[5] ; 1 ;
; CMDWR~0 ; 1 ;
; Bank[2] ; 1 ;
; Bank[3] ; 1 ;
; Bank[1] ; 1 ;
; ARShift~0 ; 1 ;
; ARCLK~3 ; 1 ;
; ARCLK~2 ; 1 ;
; ARCLK~0 ; 1 ;
; CmdDRCLK ; 1 ;
; DRCLK~0 ; 1 ;
; FS[6]~11COUT1_58 ; 1 ;
; FS[6]~11 ; 1 ;
; FS[7]~9COUT1_60 ; 1 ;
; FS[7]~9 ; 1 ;
; FS[16]~5COUT1_74 ; 1 ;
; FS[16]~5 ; 1 ;
; FS[4]~3COUT1_54 ; 1 ;
; FS[4]~3 ; 1 ;
; FS[5]~1COUT1_56 ; 1 ;
; FS[5]~1 ; 1 ;
; CmdSubmitted ; 1 ;
; CmdDRDIn ; 1 ;
; nRCAS~1 ; 1 ;
; nRCAS~0 ; 1 ;
; nRWE~0 ; 1 ;
; RASr3 ; 1 ;
; nRCS~4 ; 1 ;
; nRCS~2 ; 1 ;
; nRowColSel~1 ; 1 ;
; DRCLK ; 1 ;
; DRDIn ; 1 ;
; comb~1 ; 1 ;
; comb~0 ; 1 ;
; nRCAS~reg0 ; 1 ;
; nRRAS~reg0 ; 1 ;
; nRWE~reg0 ; 1 ;
; nRCS~reg0 ; 1 ;
; RA11 ; 1 ;
; RA10 ; 1 ;
; RA~9 ; 1 ;
; RowA[9] ; 1 ;
; RA~8 ; 1 ;
; RowA[8] ; 1 ;
; RA~7 ; 1 ;
; RowA[7] ; 1 ;
; RA~6 ; 1 ;
; RowA[6] ; 1 ;
; RA~5 ; 1 ;
; RowA[5] ; 1 ;
; RA~4 ; 1 ;
; RowA[4] ; 1 ;
; RA~3 ; 1 ;
; RowA[3] ; 1 ;
; RA~2 ; 1 ;
; RowA[2] ; 1 ;
; RA~1 ; 1 ;
; RowA[1] ; 1 ;
; RA~0 ; 1 ;
; RowA[0] ; 1 ;
; RBA[1]~reg0 ; 1 ;
; RBA[0]~reg0 ; 1 ;
+---------------------------------------------------------------------------------------------+---------+
+--------------------------------------------------+
; Other Routing Usage Summary ;
+-----------------------------+--------------------+
; Other Routing Resource Type ; Usage ;
+-----------------------------+--------------------+
; C4s ; 152 / 784 ( 19 % ) ;
; Direct links ; 45 / 888 ( 5 % ) ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; LAB clocks ; 15 / 32 ( 47 % ) ;
; LUT chains ; 22 / 216 ( 10 % ) ;
; Local interconnects ; 270 / 888 ( 30 % ) ;
; R4s ; 155 / 704 ( 22 % ) ;
+-----------------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 7.73) ; Number of LABs (Total = 22) ;
+--------------------------------------------+------------------------------+
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 2 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 2 ;
; 9 ; 0 ;
; 10 ; 13 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.18) ; Number of LABs (Total = 22) ;
+------------------------------------+------------------------------+
; 1 Clock ; 14 ;
; 1 Clock enable ; 2 ;
; 1 Sync. clear ; 3 ;
; 1 Sync. load ; 1 ;
; 2 Clocks ; 6 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 7.91) ; Number of LABs (Total = 22) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 2 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 11 ;
; 11 ; 1 ;
; 12 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 5.73) ; Number of LABs (Total = 22) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 2 ;
; 3 ; 3 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 4 ;
; 7 ; 2 ;
; 8 ; 1 ;
; 9 ; 3 ;
; 10 ; 3 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 10.18) ; Number of LABs (Total = 22) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 2 ;
; 9 ; 4 ;
; 10 ; 1 ;
; 11 ; 1 ;
; 12 ; 2 ;
; 13 ; 3 ;
; 14 ; 1 ;
; 15 ; 0 ;
; 16 ; 1 ;
; 17 ; 1 ;
; 18 ; 0 ;
; 19 ; 1 ;
+----------------------------------------------+------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Summary ;
+-----------------+----------------------+-------------------+
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
; I/O ; nCRAS ; 1.3 ;
; I/O ; RCLK ; 1.2 ;
+-----------------+----------------------+-------------------+
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer.
+------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Details ;
+-----------------+----------------------+-------------------+
; Source Register ; Destination Register ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
; nCCAS ; CBR ; 1.303 ;
; PHI2 ; PHI2r ; 0.610 ;
; nCRAS ; RASr ; 0.301 ;
+-----------------+----------------------+-------------------+
Note: This table only shows the top 3 path(s) that have the largest delay added for hold.
+-----------------+
; Fitter Messages ;
+-----------------+
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (119006): Selected device EPM240T100C5 for design "RAM4GS"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EPM240T100I5 is compatible
Info (176445): Device EPM240T100A5 is compatible
Info (176445): Device EPM570T100C5 is compatible
Info (176445): Device EPM570T100I5 is compatible
Info (176445): Device EPM570T100A5 is compatible
Info (332104): Reading SDC File: 'constraints.sdc'
Info (332144): No user constrained base clocks found in the design
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info (332127): Assuming a default timing requirement
Info (332111): Found 6 clocks
Info (332111): Period Clock Name
Info (332111): ======== ============
Info (332111): 1.000 ARCLK
Info (332111): 1.000 DRCLK
Info (332111): 1.000 nCCAS
Info (332111): 1.000 nCRAS
Info (332111): 1.000 PHI2
Info (332111): 1.000 RCLK
Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12
Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock
Info (186217): Destination "PHI2r" may be non-global or may not use global clock
Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position
Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock
Info (186217): Destination "RASr" may be non-global or may not use global clock
Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position
Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock
Info (186217): Destination "CBR" may be non-global or may not use global clock
Info (186217): Destination "comb~2" may be non-global or may not use global clock
Info (186217): Destination "CASr" may be non-global or may not use global clock
Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186391): Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 20% of the available device resources
Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.53 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg
Info: Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 376 megabytes
Info: Processing ended: Thu Jul 23 02:20:50 2020
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:08
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg.
Hardware/AGM/cpld-src/output_files/RAM4GS.fit.smsg
-4
View File
@@ -1,4 +0,0 @@
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176244): Moving registers into LUTs to improve timing and density
Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00
Hardware/AGM/cpld-src/output_files/RAM4GS.fit.summary
-11
View File
@@ -1,11 +0,0 @@
Fitter Status : Successful - Thu Jul 23 02:20:50 2020
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM4GS
Top-level Entity Name : RAM4GS
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Total logic elements : 170 / 240 ( 71 % )
Total pins : 62 / 80 ( 78 % )
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )
Hardware/AGM/cpld-src/output_files/RAM4GS.flow.rpt
-126
View File
@@ -1,126 +0,0 @@
Flow report for RAM4GS
Thu Jul 23 02:21:02 2020
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Thu Jul 23 02:20:55 2020 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM4GS ;
; Top-level Entity Name ; RAM4GS ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 170 / 240 ( 71 % ) ;
; Total pins ; 62 / 80 ( 78 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+---------------------------+-------------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 07/23/2020 02:20:37 ;
; Main task ; Compilation ;
; Revision Name ; RAM4GS ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+--------------------------------------------+--------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+--------------------------------------------+--------------------------------+---------------+-------------+------------+
; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 44085571633675.159548523602288 ; -- ; -- ; -- ;
; ENABLE_BUS_HOLD_CIRCUITRY ; On ; Off ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ;
; OPTIMIZE_MULTI_CORNER_TIMING ; On ; Off ; -- ; -- ;
; PLACEMENT_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ;
; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; ROUTER_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ;
; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ;
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
+--------------------------------------------+--------------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 303 MB ; 00:00:05 ;
; Fitter ; 00:00:08 ; 1.3 ; 376 MB ; 00:00:07 ;
; Assembler ; 00:00:02 ; 1.0 ; 295 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 288 MB ; 00:00:04 ;
; Total ; 00:00:20 ; -- ; -- ; 00:00:18 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+-----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ;
; Fitter ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ;
; Assembler ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ;
; TimeQuest Timing Analyzer ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ;
+---------------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS
quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS
quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS
quartus_sta RAM4GS -c RAM4GS
Hardware/AGM/cpld-src/output_files/RAM4GS.jdi
-8
View File
@@ -1,8 +0,0 @@
<sld_project_info>
<project>
<hash md5_digest_80b="6d7ef2df313eca11db51"/>
</project>
<file_info>
<file device="EPM240T100C5" path="RAM4GS.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>
Hardware/AGM/cpld-src/output_files/RAM4GS.map.rpt
-315
View File
@@ -1,315 +0,0 @@
Analysis & Synthesis report for RAM4GS
Thu Jul 23 02:20:40 2020
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis IP Cores Summary
9. General Register Statistics
10. Inverted Register Statistics
11. Multiplexer Restructuring Statistics (Restructuring Performed)
12. Port Connectivity Checks: "UFM:UFM_inst"
13. Analysis & Synthesis Messages
14. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Jul 23 02:20:40 2020 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM4GS ;
; Top-level Entity Name ; RAM4GS ;
; Family ; MAX II ;
; Total logic elements ; 178 ;
; Total pins ; 62 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+-------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EPM240T100C5 ; ;
; Top-level entity name ; RAM4GS ; RAM4GS ;
; Family name ; MAX II ; Cyclone IV GX ;
; Safe State Machine ; On ; Off ;
; Power-Up Don't Care ; Off ; On ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.0% ;
+----------------------------+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
; RAM4GS.v ; yes ; User Verilog HDL File ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v ; ;
; RAM4GS.mif ; yes ; User Memory Initialization File ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.mif ; ;
; UFM.v ; yes ; User Wizard-Generated File ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v ; ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 178 ;
; -- Combinational with no register ; 82 ;
; -- Register only ; 29 ;
; -- Combinational with a register ; 67 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 57 ;
; -- 3 input functions ; 41 ;
; -- 2 input functions ; 42 ;
; -- 1 input functions ; 8 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 162 ;
; -- arithmetic mode ; 16 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 9 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 96 ;
; Total logic cells in carry chains ; 17 ;
; I/O pins ; 62 ;
; UFM blocks ; 1 ;
; Maximum fan-out node ; RCLK ;
; Maximum fan-out ; 54 ;
; Total fan-out ; 643 ;
; Average fan-out ; 2.67 ;
+---------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; |RAM4GS ; 178 (178) ; 96 ; 1 ; 62 ; 0 ; 82 (82) ; 29 (29) ; 67 (67) ; 17 (17) ; 0 (0) ; |RAM4GS ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst ; work ;
; |UFM_altufm_none_1br:UFM_altufm_none_1br_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+
; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM4GS|UFM:UFM_inst ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v ;
+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 96 ;
; Number of registers using Synchronous Clear ; 6 ;
; Number of registers using Synchronous Load ; 3 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 10 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; nRCS~reg0 ; 1 ;
; nRWE~reg0 ; 1 ;
; nRRAS~reg0 ; 1 ;
; nRCAS~reg0 ; 1 ;
; Total number of inverted registers = 4 ; ;
+----------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM4GS|S[0] ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM4GS|C1Submitted ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFM:UFM_inst" ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; ardin ; Input ; Info ; Stuck at GND ;
; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Jul 23 02:20:35 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file ram4gs.v
Info (12023): Found entity 1: RAM4GS
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Info (12023): Found entity 1: UFM_altufm_none_1br
Info (12023): Found entity 2: UFM
Info (12127): Elaborating entity "RAM4GS" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
Info (12128): Elaborating entity "UFM_altufm_none_1br" for hierarchy "UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component"
Warning (18029): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated
Warning (18029): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated
Warning (18029): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated
Warning (18029): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated
Warning (18029): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated
Warning (18029): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated
Warning (18029): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated
Warning (18029): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated
Info (21057): Implemented 241 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 25 input pins
Info (21059): Implemented 29 output pins
Info (21060): Implemented 8 bidirectional pins
Info (21061): Implemented 178 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings
Info: Peak virtual memory: 303 megabytes
Info: Processing ended: Thu Jul 23 02:20:41 2020
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg.
Hardware/AGM/cpld-src/output_files/RAM4GS.map.smsg
-3
View File
@@ -1,3 +0,0 @@
Warning (10273): Verilog HDL warning at RAM4GS.v(52): extended using "x" or "z"
Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword
Hardware/AGM/cpld-src/output_files/RAM4GS.map.summary
-9
View File
@@ -1,9 +0,0 @@
Analysis & Synthesis Status : Successful - Thu Jul 23 02:20:40 2020
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM4GS
Top-level Entity Name : RAM4GS
Family : MAX II
Total logic elements : 178
Total pins : 62
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )
Hardware/AGM/cpld-src/output_files/RAM4GS.pin
-164
View File
@@ -1,164 +0,0 @@
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
CHIP "RAM4GS" ASSIGNED TO AN: EPM240T100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND* : 1 : : : : 2 :
RDQMH : 2 : output : 3.3-V LVCMOS : : 1 : Y
nRCS : 3 : output : 3.3-V LVCMOS : : 1 : Y
nRCAS : 4 : output : 3.3-V LVCMOS : : 1 : Y
RBA[0] : 5 : output : 3.3-V LVCMOS : : 1 : Y
nRRAS : 6 : output : 3.3-V LVCMOS : : 1 : Y
RA[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y
RCKE : 8 : output : 3.3-V LVCMOS : : 1 : Y
VCCIO1 : 9 : power : : 3.3V : 1 :
GNDIO : 10 : gnd : : : :
GNDINT : 11 : gnd : : : :
RCLK : 12 : input : 3.3-V LVCMOS : : 1 : Y
VCCINT : 13 : power : : 2.5V/3.3V : :
RBA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y
RA[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y
RA[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y
RA[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y
RA[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y
RA[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y
RA[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y
RA[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y
TMS : 22 : input : : : 1 :
TDI : 23 : input : : : 1 :
TCK : 24 : input : : : 1 :
TDO : 25 : output : : : 1 :
RA[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y
RA[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y
Dout[5] : 28 : output : 3.3-V LVCMOS : : 1 : Y
RA[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y
RA[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y
VCCIO1 : 31 : power : : 3.3V : 1 :
GNDIO : 32 : gnd : : : :
Dout[0] : 33 : output : 3.3-V LVCMOS : : 1 : Y
Dout[6] : 34 : output : 3.3-V LVCMOS : : 1 : Y
Din[2] : 35 : input : 3.3-V LVCMOS : : 1 : Y
Din[1] : 36 : input : 3.3-V LVCMOS : : 1 : Y
Din[3] : 37 : input : 3.3-V LVCMOS : : 1 : Y
Din[5] : 38 : input : 3.3-V LVCMOS : : 1 : Y
Din[4] : 39 : input : 3.3-V LVCMOS : : 1 : Y
Din[7] : 40 : input : 3.3-V LVCMOS : : 1 : Y
Din[6] : 41 : input : 3.3-V LVCMOS : : 1 : Y
Din[0] : 42 : input : 3.3-V LVCMOS : : 1 : Y
Dout[7] : 43 : output : 3.3-V LVCMOS : : 1 : Y
Dout[4] : 44 : output : 3.3-V LVCMOS : : 1 : Y
VCCIO1 : 45 : power : : 3.3V : 1 :
GNDIO : 46 : gnd : : : :
Dout[3] : 47 : output : 3.3-V LVCMOS : : 1 : Y
nFWE : 48 : input : 3.3-V LVCMOS : : 1 : Y
MAin[0] : 49 : input : 3.3-V LVCMOS : : 1 : Y
MAin[2] : 50 : input : 3.3-V LVCMOS : : 1 : Y
MAin[1] : 51 : input : 3.3-V LVCMOS : : 1 : Y
PHI2 : 52 : input : 3.3-V LVCMOS : : 2 : Y
nCCAS : 53 : input : 3.3-V LVCMOS : : 2 : Y
CROW[0] : 54 : input : 3.3-V LVCMOS : : 2 : Y
CROW[1] : 55 : input : 3.3-V LVCMOS : : 2 : Y
Dout[2] : 56 : output : 3.3-V LVCMOS : : 2 : Y
Dout[1] : 57 : output : 3.3-V LVCMOS : : 2 : Y
GND* : 58 : : : : 2 :
VCCIO2 : 59 : power : : 3.3V : 2 :
GNDIO : 60 : gnd : : : :
GND* : 61 : : : : 2 :
GND* : 62 : : : : 2 :
VCCINT : 63 : power : : 2.5V/3.3V : :
GND* : 64 : : : : 2 :
GNDINT : 65 : gnd : : : :
GND* : 66 : : : : 2 :
nCRAS : 67 : input : 3.3-V LVCMOS : : 2 : Y
MAin[7] : 68 : input : 3.3-V LVCMOS : : 2 : Y
MAin[5] : 69 : input : 3.3-V LVCMOS : : 2 : Y
MAin[4] : 70 : input : 3.3-V LVCMOS : : 2 : Y
MAin[3] : 71 : input : 3.3-V LVCMOS : : 2 : Y
MAin[6] : 72 : input : 3.3-V LVCMOS : : 2 : Y
MAin[8] : 73 : input : 3.3-V LVCMOS : : 2 : Y
MAin[9] : 74 : input : 3.3-V LVCMOS : : 2 : Y
GND* : 75 : : : : 2 :
GND* : 76 : : : : 2 :
GND* : 77 : : : : 2 :
GND* : 78 : : : : 2 :
GNDIO : 79 : gnd : : : :
VCCIO2 : 80 : power : : 3.3V : 2 :
GND* : 81 : : : : 2 :
GND* : 82 : : : : 2 :
GND* : 83 : : : : 2 :
GND* : 84 : : : : 2 :
GND* : 85 : : : : 2 :
GND* : 86 : : : : 2 :
GND* : 87 : : : : 2 :
GND* : 88 : : : : 2 :
RD[2] : 89 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[5] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[4] : 92 : bidir : 3.3-V LVCMOS : : 2 : Y
GNDIO : 93 : gnd : : : :
VCCIO2 : 94 : power : : 3.3V : 2 :
RD[6] : 95 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[0] : 96 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[7] : 97 : bidir : 3.3-V LVCMOS : : 2 : Y
RDQML : 98 : output : 3.3-V LVCMOS : : 2 : Y
RD[3] : 99 : bidir : 3.3-V LVCMOS : : 2 : Y
nRWE : 100 : output : 3.3-V LVCMOS : : 2 : Y
Hardware/AGM/cpld-src/output_files/RAM4GS.pof
BIN
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Binary file not shown.
Hardware/AGM/cpld-src/output_files/RAM4GS.sta.rpt
-1588
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File diff suppressed because it is too large Load Diff
Hardware/AGM/cpld-src/output_files/RAM4GS.sta.summary
-69
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@@ -1,69 +0,0 @@
------------------------------------------------------------
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'ARCLK'
Slack : -99.000
TNS : -99.000
Type : Setup 'DRCLK'
Slack : -99.000
TNS : -99.000
Type : Setup 'PHI2'
Slack : -9.292
TNS : -92.804
Type : Setup 'RCLK'
Slack : -8.365
TNS : -253.063
Type : Setup 'nCRAS'
Slack : -0.490
TNS : -0.577
Type : Hold 'DRCLK'
Slack : -16.306
TNS : -16.306
Type : Hold 'ARCLK'
Slack : -16.272
TNS : -16.272
Type : Hold 'RCLK'
Slack : -0.874
TNS : -0.874
Type : Hold 'PHI2'
Slack : -0.396
TNS : -0.396
Type : Hold 'nCRAS'
Slack : -0.125
TNS : -0.125
Type : Minimum Pulse Width 'ARCLK'
Slack : -29.500
TNS : -59.000
Type : Minimum Pulse Width 'DRCLK'
Slack : -29.500
TNS : -59.000
Type : Minimum Pulse Width 'PHI2'
Slack : -2.289
TNS : -2.289
Type : Minimum Pulse Width 'RCLK'
Slack : -2.289
TNS : -2.289
Type : Minimum Pulse Width 'nCCAS'
Slack : -2.289
TNS : -2.289
Type : Minimum Pulse Width 'nCRAS'
Slack : -2.289
TNS : -2.289
------------------------------------------------------------
Hardware/AGM/cpld-src/output_files/greybox_tmp/cbx_args.txt
-25
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@@ -1,25 +0,0 @@
ERASE_TIME=500000000
INTENDED_DEVICE_FAMILY="MAX II"
LPM_FILE=RAM4GS.mif
LPM_HINT=UNUSED
LPM_TYPE=altufm_none
OSC_FREQUENCY=180000
PORT_ARCLKENA=PORT_UNUSED
PORT_DRCLKENA=PORT_UNUSED
PROGRAM_TIME=1600000
WIDTH_UFM_ADDRESS=9
DEVICE_FAMILY="MAX II"
CBX_AUTO_BLACKBOX=ALL
arclk
ardin
arshft
busy
drclk
drdin
drdout
drshft
erase
osc
oscena
program
rtpbusy
Hardware/MAX/cpld/RAM4GS.mif
-27
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@@ -1,27 +0,0 @@
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II generated Memory Initialization File (.mif)
WIDTH=16;
DEPTH=512;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
[000..0FD] : 0000;
0FE : 7FFF;
[0FF..1FF] : FFFF;
END;
Hardware/MAX/cpld/RAM4GS.qpf
-30
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@@ -1,30 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 21:16:34 March 08, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "21:16:34 March 08, 2020"
# Revisions
PROJECT_REVISION = "RAM4GS"
Hardware/MAX/cpld/RAM4GS.qsf
-213
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@@ -1,213 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 21:16:34 March 08, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# RAM4GS_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM4GS
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34 MARCH 08, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name SDC_FILE constraints.sdc
set_global_assignment -name VERILOG_FILE RAM4GS.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON
set_global_assignment -name SAFE_STATE_MACHINE ON
set_location_assignment PIN_12 -to RCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK
set_location_assignment PIN_52 -to PHI2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI2
set_location_assignment PIN_67 -to nCRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCRAS
set_location_assignment PIN_53 -to nCCAS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCCAS
set_location_assignment PIN_48 -to nFWE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nFWE
set_location_assignment PIN_49 -to MAin[0]
set_location_assignment PIN_51 -to MAin[1]
set_location_assignment PIN_50 -to MAin[2]
set_location_assignment PIN_71 -to MAin[3]
set_location_assignment PIN_70 -to MAin[4]
set_location_assignment PIN_69 -to MAin[5]
set_location_assignment PIN_72 -to MAin[6]
set_location_assignment PIN_68 -to MAin[7]
set_location_assignment PIN_73 -to MAin[8]
set_location_assignment PIN_74 -to MAin[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MAin
set_location_assignment PIN_54 -to CROW[0]
set_location_assignment PIN_55 -to CROW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CROW
set_location_assignment PIN_35 -to Din[2]
set_location_assignment PIN_36 -to Din[1]
set_location_assignment PIN_37 -to Din[3]
set_location_assignment PIN_38 -to Din[5]
set_location_assignment PIN_39 -to Din[4]
set_location_assignment PIN_40 -to Din[7]
set_location_assignment PIN_41 -to Din[6]
set_location_assignment PIN_42 -to Din[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
set_location_assignment PIN_33 -to Dout[0]
set_location_assignment PIN_57 -to Dout[1]
set_location_assignment PIN_56 -to Dout[2]
set_location_assignment PIN_47 -to Dout[3]
set_location_assignment PIN_44 -to Dout[4]
set_location_assignment PIN_28 -to Dout[5]
set_location_assignment PIN_34 -to Dout[6]
set_location_assignment PIN_43 -to Dout[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
set_location_assignment PIN_8 -to RCKE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCKE
set_location_assignment PIN_3 -to nRCS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCS
set_location_assignment PIN_100 -to nRWE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
set_location_assignment PIN_6 -to nRRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRRAS
set_location_assignment PIN_4 -to nRCAS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCAS
set_location_assignment PIN_5 -to RBA[0]
set_location_assignment PIN_14 -to RBA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RBA
set_location_assignment PIN_18 -to RA[0]
set_location_assignment PIN_20 -to RA[1]
set_location_assignment PIN_30 -to RA[2]
set_location_assignment PIN_27 -to RA[3]
set_location_assignment PIN_26 -to RA[4]
set_location_assignment PIN_29 -to RA[5]
set_location_assignment PIN_21 -to RA[6]
set_location_assignment PIN_19 -to RA[7]
set_location_assignment PIN_17 -to RA[8]
set_location_assignment PIN_15 -to RA[9]
set_location_assignment PIN_16 -to RA[10]
set_location_assignment PIN_7 -to RA[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
set_location_assignment PIN_2 -to RDQMH
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQMH
set_location_assignment PIN_98 -to RDQML
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQML
set_location_assignment PIN_96 -to RD[0]
set_location_assignment PIN_90 -to RD[1]
set_location_assignment PIN_89 -to RD[2]
set_location_assignment PIN_99 -to RD[3]
set_location_assignment PIN_92 -to RD[4]
set_location_assignment PIN_91 -to RD[5]
set_location_assignment PIN_95 -to RD[6]
set_location_assignment PIN_97 -to RD[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
set_global_assignment -name MIF_FILE RAM4GS.mif
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to MAin
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to CROW
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to Din
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to Dout
set_instance_assignment -name SLOW_SLEW_RATE OFF -to Dout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCKE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RCKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRRAS
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCAS
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RBA
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RBA
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RBA
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RA
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RA
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQMH
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQML
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
set_global_assignment -name QIP_FILE UFM.qip
Hardware/MAX/cpld/RAM4GS.v
-436
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@@ -1,436 +0,0 @@
module RAM4GS(PHI2, MAin, CROW, Din, Dout,
nCCAS, nCRAS, nFWE,
RBA, RA, RD, nRCS, RCLK, RCKE,
nRWE, nRRAS, nRCAS, RDQMH, RDQML);
/* 65816 Phase 2 Clock */
input PHI2;
/* Async. DRAM Control Inputs */
input nCCAS, nCRAS;
/* Synchronized PHI2 and DRAM signals */
reg PHI2r, PHI2r2, PHI2r3;
reg RASr, RASr2, RASr3;
reg CASr, CASr2, CASr3;
reg FWEr;
reg CBR;
/* 65816 Data */
input [7:0] Din;
output [7:0] Dout = RD[7:0];
/* Latched 65816 Bank Address */
reg [7:0] Bank;
/* Async. DRAM Address Bus */
input [1:0] CROW;
input [9:0] MAin;
input nFWE;
reg n8MEGEN = 0;
reg XOR8MEG = 0;
/* SDRAM Clock */
input RCLK;
/* SDRAM */
reg RCKEEN;
output reg RCKE = 0;
output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
output reg [1:0] RBA;
reg nRowColSel;
reg RA11;
reg RA10;
reg [9:0] RowA;
output [11:0] RA;
assign RA[11] = RA11;
assign RA[10] = RA10;
assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
output RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
output RDQMH = ~nRowColSel ? 1'b1 : MAin[9];
reg [7:0] WRD;
inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
/* UFM Interface */
reg UFMD = 0; // UFM data register bit 15
reg ARCLK = 0; // UFM address register clock
// UFM address register data input tied to 0
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
reg DRCLK = 0; // UFM data register clock
reg DRDIn = 0; // UFM data register input
reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
reg UFMOscEN = 0; // UFM oscillator enable
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
wire DRDOut; // UFM data output
// UFM oscillator always enabled
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
.arclk (ARCLK),
.ardin (1'b0),
.arshft (ARShift),
.drclk (DRCLK),
.drdin (DRDIn),
.drshft (DRShift),
.erase (UFMErase),
.oscena (UFMOscEN),
.program (UFMProgram),
.busy (UFMBusy),
.drdout (DRDOut),
.osc (UFMOsc),
.rtpbusy (RTPBusy));
reg UFMBusyReg = 0; // UFMBusy registered to sync with RCLK
reg RTPBusyReg = 0; // RTPBusy registered to sync with RCLK
/* UFM State */
reg UFMInitDone = 0; // 1 if UFM initialization finished
reg UFMReqErase = 0; // 1 if UFM requires erase
/* UFM Command Interface */
reg C1Submitted = 0;
reg ADSubmitted = 0;
reg CmdEnable = 0;
reg CmdSubmitted = 0;
reg Cmdn8MEGEN = 0;
reg CmdDRCLK = 0;
reg CmdDRDIn = 0;
reg CmdUFMErase = 0; // Set by user command. Programs UFM
reg CmdUFMPrgm = 0; // Set by user command. Erases UFM
wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
/* State Counters */
reg InitReady = 0; // 1 if ready for init sequence
reg Ready = 0; // 1 if done with init sequence
reg [1:0] S = 0; // post-RAS State counter
reg [17:0] FS = 0; // Fast init state counter
reg [3:0] IS = 0; // Init state counter
reg WriteDone;
/* Synchronize PHI2, RAS, CAS */
always @(posedge RCLK) begin
PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
end
/* Latch 65816 bank when PHI2 rises */
always @(posedge PHI2) begin
if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
else RA11 <= 1'b0; // Reserved in mode register
Bank[7:0] <= Din[7:0]; // Latch bank
end
/* Latch bank address, row address, WE, and CAS when RAS falls */
always @(negedge nCRAS) begin
if (Ready) begin
RBA[1:0] <= CROW[1:0];
RowA[9:0] <= MAin[9:0];
end else begin
RBA[1:0] <= 2'b00; // Reserved in mode register
RowA[9] <= 1'b1; // "1" for single write mode
RowA[8] <= 1'b0; // Reserved
RowA[7] <= 1'b0; // "0" for not test mode
RowA[6:4] <= 3'b010; // "2" for CAS latency 2
RowA[3] <= 1'b0; // "0" for sequential burst (not used)
RowA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
end
FWEr <= ~nFWE;
CBR <= ~nCCAS;
end
/* Latch write data when CAS falls */
always @(negedge nCCAS) begin
WRD[7:0] <= Din[7:0];
end
/* State counter from RAS */
always @(posedge RCLK) begin
if (~RASr2) S <= 0;
else if (S==2'h3) S <= 2'h3;
else S <= S+1;
end
/* Init state counter */
always @(posedge RCLK) begin
// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
FS <= FS+1;
if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
end
/* SDRAM CKE */
always @(posedge RCLK) begin
// Only 1 LUT4 allowed for this function!
RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
end
/* SDRAM command */
always @(posedge RCLK) begin
if (Ready) begin
if (S==0) begin
if (RASr2) begin
if (CBR) begin
// AREF
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b0;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end else begin
// ACT
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // Bank RA10 consistently "1"
end
// Enable clock only for reads
RCKEEN <= ~CBR & ~FWEr;
end else if (RCKE) begin
// PCall
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b1;
nRWE <= 1'b0;
RA10 <= 1'b1; // "all"
RCKEEN <= 1'b1;
end else begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
RCKEEN <= 1'b1;
end
nRowColSel <= 1'b0; // Select registered row addres
end else if (S==1) begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
nRowColSel <= 1'b1; // Select asynchronous column address
RCKEEN <= ~CBR; // Disable clock if refresh cycle
end else if (S==2) begin
if (~FWEr & ~CBR) begin
// RD
nRCS <= 1'b0;
nRRAS <= 1'b1;
nRCAS <= 1'b0;
nRWE <= 1'b1;
RA10 <= 1'b1; // Auto-precharge
end else begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end
nRowColSel <= 1'b1; // Select asynchronous column address
RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
end else if (S==3) begin
if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
// WR
nRCS <= 1'b0;
nRRAS <= 1'b1;
nRCAS <= 1'b0;
nRWE <= 1'b0;
RA10 <= 1'b1; // Auto-precharge
end else begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end
nRowColSel <= ~(~FWEr | CASr3 | CBR);
RCKEEN <= ~(~FWEr | CASr2 | CBR);
end
end else if (InitReady) begin
if (S==0 & RASr2) begin
if (IS==0) begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end else if (IS==1) begin
// PC all
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b1;
nRWE <= 1'b0;
RA10 <= 1'b1; // "all"
end else if (IS==9) begin
// Load mode register
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b0;
nRWE <= 1'b0;
RA10 <= 1'b0; // Reserved in mode register
end else begin
// AREF
nRCS <= 1'b0;
nRRAS <= 1'b0;
nRCAS <= 1'b0;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end
IS <= IS+1;
end else begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
end
if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
nRowColSel <= 1'b0; // Select registered row address
RCKEEN <= 1'b1;
end else begin
// NOP
nRCS <= 1'b1;
nRRAS <= 1'b1;
nRCAS <= 1'b1;
nRWE <= 1'b1;
RA10 <= 1'b1; // RA10 is don't care
nRowColSel <= 1'b0; // Select registered row address
RCKEEN <= 1'b0;
end
end
/* Submit command when PHI2 falls */
always @(negedge PHI2) begin
// Magic number check
if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
if (ADSubmitted) begin
CmdEnable <= 1'b1;
UFMOscEN <= 1'b1;
end
C1Submitted <= 1'b1;
ADSubmitted <= 1'b0;
end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
if (C1Submitted) begin
CmdEnable <= 1'b1;
UFMOscEN <= 1'b1;
end
ADSubmitted <= 1'b1;
C1Submitted <= 1'b0;
end else if (C1WR | ADWR) begin // wrong magic number submitted
CmdEnable <= 1'b0;
C1Submitted <= 1'b0;
ADSubmitted <= 1'b0;
end else if (CMDWR) CmdEnable <= 1'b0;
// Submit command
if (CMDWR & CmdEnable) begin
if (Din[7:4]==4'h0) begin
XOR8MEG <= Din[0];
end else if (Din[7:4]==4'h1) begin
Cmdn8MEGEN <= ~Din[0];
CmdSubmitted <= 1'b1;
end else if (Din[7:4]==4'h2) begin
Cmdn8MEGEN <= n8MEGEN;
CmdUFMErase <= Din[3];
CmdUFMPrgm <= Din[2];
CmdDRCLK <= Din[1];
CmdDRDIn <= Din[0];
CmdSubmitted <= 1'b1;
end
end
end
/* UFM Control */
always @(posedge RCLK) begin
if (~Ready) begin
if (~UFMInitDone & FS[17:16]==2'b00) begin
// Shift 0 into address register
ARCLK <= FS[3]; // Clock address register
ARShift <= 1'b1; // Shift 0 into address register
DRCLK <= 1'b0; // Don't clock data register
DRDIn <= 1'b0; // DRDIn is don't care
DRShift <= 1'b0; // DRShift is don't care
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h0) begin
// Parallel transfer UFM data to shift register
ARCLK <= 1'b0; // Don't clock address register
ARShift <= 1'b0; // ARShift is don't care
DRCLK <= FS[3]; // Clock data register
DRDIn <= 1'b0; // DRDIn is don't care
DRShift <= 1'b0; // Parallel transfer to data register
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h4) begin
// Shift UFM
ARCLK <= 1'b0; // Don't clock address register
ARShift <= 1'b0; // ARShift is don't care
DRCLK <= FS[3]; // Clock data register
DRDIn <= 1'b0; // DRDIn is don't care
DRShift <= 1'b1; // Shift data register
// Capture bit 15 of this UFM word in UFMD register
if (FS[3:0]==4'h7) UFMD <= DRDOut;
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h5) begin
// Check saved capacity entry
if (UFMD) UFMInitDone <= 1'b1; // If erased, quit iterating
else begin // If valid setting here
n8MEGEN <= ~DRDOut; // Set capacity setting
// If last byte in sector, mark need to erase
if (FS[15:8]==8'hFF) begin
UFMReqErase <= 1'b1; // Mark need to wrap around
UFMInitDone <= 1'b1; // Quit iterating
end
end
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h6) begin
// Increment UFM address
ARCLK <= FS[3]; // Clock address register
ARShift <= 1'b0; // Increment UFM address
DRCLK <= 1'b0; // Don't clock data register
DRDIn <= 1'b0; // DRDIn is don't care
DRShift <= 1'b0; // DRShift is don't care
end else if (FS[17:16]==2'b10 & UFMReqErase) begin
// Shift 0 into address register
ARCLK <= FS[3]; // Clock address register
ARShift <= 1'b1; // Shift 0 into address register
DRCLK <= 1'b0; // Don't clock data register
DRDIn <= 1'b0; // DRDIn is don't care
DRShift <= 1'b0; // DRShift is don't care
end else begin
// Don't do anything with UFM
ARCLK <= 1'b0; // Don't clock address register
ARShift <= 1'b0; // ARShift is don't care
DRCLK <= 1'b0; // Don't clock data register
DRDIn <= 1'b0; // DRDIn is don't care
DRShift <= 1'b0; // DRShift is don't care
end
// Don't erase or program UFM during initialization
UFMErase <= 1'b0;
UFMProgram <= 1'b0;
end else begin
// Can only shift UFM data register now
ARCLK <= 1'b0;
ARShift <= 1'b0;
DRShift <= 1'b1;
// Set user command signals after PHI2 falls
if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
n8MEGEN <= Cmdn8MEGEN;
DRCLK <= CmdDRCLK;
DRDIn <= CmdDRDIn;
end
// UFM programming sequence
if (CmdUFMPrgm | CmdUFMErase) begin
if (~UFMBusyReg & ~RTPBusyReg) begin
if (UFMReqErase | CmdUFMErase) UFMErase <= 1'b1;
else if (CmdUFMPrgm) UFMProgram <= 1'b1;
end else if (UFMBusyReg) UFMReqErase <= 1'b0;
end
end
end
endmodule
Hardware/MAX/cpld/UFM.qip
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set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"]
Hardware/MAX/cpld/UFM.v
-268
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// megafunction wizard: %ALTUFM_NONE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTUFM_NONE
// ============================================================
// File Name: UFM.v
// Megafunction Name(s):
// ALTUFM_NONE
//
// Simulation Library Files(s):
// maxii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM4GS.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:39:SJ cbx_a_graycounter 2013:06:12:18:03:39:SJ cbx_altufm_none 2013:06:12:18:03:40:SJ cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_lpm_compare 2013:06:12:18:03:40:SJ cbx_lpm_counter 2013:06:12:18:03:40:SJ cbx_lpm_decode 2013:06:12:18:03:40:SJ cbx_lpm_mux 2013:06:12:18:03:40:SJ cbx_maxii 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ cbx_util_mgl 2013:06:12:18:03:40:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = maxii_ufm 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module UFM_altufm_none_1br
(
arclk,
ardin,
arshft,
busy,
drclk,
drdin,
drdout,
drshft,
erase,
osc,
oscena,
program,
rtpbusy) ;
input arclk;
input ardin;
input arshft;
output busy;
input drclk;
input drdin;
output drdout;
input drshft;
input erase;
output osc;
input oscena;
input program;
output rtpbusy;
wire wire_maxii_ufm_block1_bgpbusy;
wire wire_maxii_ufm_block1_busy;
wire wire_maxii_ufm_block1_drdout;
wire wire_maxii_ufm_block1_osc;
wire ufm_arclk;
wire ufm_ardin;
wire ufm_arshft;
wire ufm_bgpbusy;
wire ufm_busy;
wire ufm_drclk;
wire ufm_drdin;
wire ufm_drdout;
wire ufm_drshft;
wire ufm_erase;
wire ufm_osc;
wire ufm_oscena;
wire ufm_program;
maxii_ufm maxii_ufm_block1
(
.arclk(ufm_arclk),
.ardin(ufm_ardin),
.arshft(ufm_arshft),
.bgpbusy(wire_maxii_ufm_block1_bgpbusy),
.busy(wire_maxii_ufm_block1_busy),
.drclk(ufm_drclk),
.drdin(ufm_drdin),
.drdout(wire_maxii_ufm_block1_drdout),
.drshft(ufm_drshft),
.erase(ufm_erase),
.osc(wire_maxii_ufm_block1_osc),
.oscena(ufm_oscena),
.program(ufm_program)
// synopsys translate_off
,
.ctrl_bgpbusy(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.sbdin(1'b0),
.sbdout()
// synopsys translate_on
);
defparam
maxii_ufm_block1.address_width = 9,
maxii_ufm_block1.erase_time = 500000000,
maxii_ufm_block1.init_file = "RAM4GS.mif",
maxii_ufm_block1.mem1 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem10 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem11 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem12 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem13 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem14 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem15 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem16 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem2 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem3 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem4 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem5 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem6 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem7 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem8 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem9 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.osc_sim_setting = 180000,
maxii_ufm_block1.program_time = 1600000,
maxii_ufm_block1.lpm_type = "maxii_ufm";
assign
busy = ufm_busy,
drdout = ufm_drdout,
osc = ufm_osc,
rtpbusy = ufm_bgpbusy,
ufm_arclk = arclk,
ufm_ardin = ardin,
ufm_arshft = arshft,
ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy,
ufm_busy = wire_maxii_ufm_block1_busy,
ufm_drclk = drclk,
ufm_drdin = drdin,
ufm_drdout = wire_maxii_ufm_block1_drdout,
ufm_drshft = drshft,
ufm_erase = erase,
ufm_osc = wire_maxii_ufm_block1_osc,
ufm_oscena = oscena,
ufm_program = program;
endmodule //UFM_altufm_none_1br
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module UFM (
arclk,
ardin,
arshft,
drclk,
drdin,
drshft,
erase,
oscena,
program,
busy,
drdout,
osc,
rtpbusy);
input arclk;
input ardin;
input arshft;
input drclk;
input drdin;
input drshft;
input erase;
input oscena;
input program;
output busy;
output drdout;
output osc;
output rtpbusy;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire osc = sub_wire0;
wire rtpbusy = sub_wire1;
wire drdout = sub_wire2;
wire busy = sub_wire3;
UFM_altufm_none_1br UFM_altufm_none_1br_component (
.arshft (arshft),
.drclk (drclk),
.erase (erase),
.program (program),
.arclk (arclk),
.drdin (drdin),
.oscena (oscena),
.ardin (ardin),
.drshft (drshft),
.osc (sub_wire0),
.rtpbusy (sub_wire1),
.drdout (sub_wire2),
.busy (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: LPM_FILE STRING "RAM4GS.mif"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000"
// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9"
// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk"
// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0
// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin"
// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0
// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft"
// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk"
// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0
// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin"
// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0
// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout"
// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0
// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft"
// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0
// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase"
// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0
// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc"
// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0
// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena"
// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0
// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program"
// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0
// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy"
// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
// Retrieval info: LIB_FILE: maxii
Hardware/MAX/cpld/constraints.sdc
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485253603 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:53 2020 " "Processing started: Thu Jul 23 02:20:53 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485254775 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485254806 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:55 2020 " "Processing ended: Thu Jul 23 02:20:55 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485255322 ""}
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@@ -1,43 +0,0 @@
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595485244993 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595485245024 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595485245680 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595485245711 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595485246102 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595485246305 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595485246336 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595485246383 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595485246383 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595485246399 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246415 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246430 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246446 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246461 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595485246493 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595485246555 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595485246555 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246633 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246649 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595485246665 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595485246665 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485246712 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595485247071 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485247462 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595485247477 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595485248884 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485248899 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595485248946 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595485249462 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595485249462 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250243 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485250259 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250275 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485250290 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485250525 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:50 2020 " "Processing ended: Thu Jul 23 02:20:50 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485250759 ""}
Hardware/MAX/cpld/db/RAM4GS.hier_info
-277
View File
@@ -1,277 +0,0 @@
|RAM4GS
PHI2 => Bank[0].CLK
PHI2 => Bank[1].CLK
PHI2 => Bank[2].CLK
PHI2 => Bank[3].CLK
PHI2 => Bank[4].CLK
PHI2 => Bank[5].CLK
PHI2 => Bank[6].CLK
PHI2 => Bank[7].CLK
PHI2 => RA11.CLK
PHI2 => PHI2r.DATAIN
PHI2 => CmdDRDIn.CLK
PHI2 => CmdDRCLK.CLK
PHI2 => CmdUFMPrgm.CLK
PHI2 => CmdUFMErase.CLK
PHI2 => CmdSubmitted.CLK
PHI2 => Cmdn8MEGEN.CLK
PHI2 => XOR8MEG.CLK
PHI2 => ADSubmitted.CLK
PHI2 => C1Submitted.CLK
PHI2 => UFMOscEN.CLK
PHI2 => CmdEnable.CLK
MAin[0] => RA.DATAA
MAin[0] => RowA.DATAB
MAin[0] => Equal0.IN7
MAin[0] => Equal1.IN7
MAin[0] => Equal3.IN6
MAin[1] => RA.DATAA
MAin[1] => RowA.DATAB
MAin[1] => Equal0.IN6
MAin[1] => Equal1.IN6
MAin[1] => Equal3.IN7
MAin[2] => RA.DATAA
MAin[2] => RowA.DATAB
MAin[2] => Equal0.IN5
MAin[2] => Equal1.IN5
MAin[2] => Equal3.IN5
MAin[3] => RA.DATAA
MAin[3] => RowA.DATAB
MAin[3] => Equal0.IN4
MAin[3] => Equal1.IN4
MAin[3] => Equal3.IN4
MAin[4] => RA.DATAA
MAin[4] => RowA.DATAB
MAin[4] => Equal0.IN3
MAin[4] => Equal1.IN3
MAin[4] => Equal3.IN3
MAin[5] => RA.DATAA
MAin[5] => RowA.DATAB
MAin[5] => Equal0.IN2
MAin[5] => Equal1.IN2
MAin[5] => Equal3.IN2
MAin[6] => RA.DATAA
MAin[6] => RowA.DATAB
MAin[6] => Equal0.IN1
MAin[6] => Equal1.IN1
MAin[6] => Equal3.IN1
MAin[7] => RA.DATAA
MAin[7] => RowA.DATAB
MAin[7] => Equal0.IN0
MAin[7] => Equal1.IN0
MAin[7] => Equal3.IN0
MAin[8] => RA.DATAA
MAin[8] => RowA.DATAB
MAin[9] => RA.DATAA
MAin[9] => comb.DATAA
MAin[9] => RowA.DATAB
MAin[9] => comb.DATAA
CROW[0] => RBA.DATAB
CROW[1] => RBA.DATAB
Din[0] => CmdDRDIn.DATAB
Din[0] => XOR8MEG.DATAB
Din[0] => WRD[0].DATAIN
Din[0] => Bank[0].DATAIN
Din[0] => Equal14.IN2
Din[0] => Equal15.IN4
Din[0] => Cmdn8MEGEN.DATAB
Din[1] => CmdDRCLK.DATAB
Din[1] => WRD[1].DATAIN
Din[1] => Bank[1].DATAIN
Din[1] => Equal14.IN7
Din[1] => Equal15.IN7
Din[2] => CmdUFMPrgm.DATAB
Din[2] => WRD[2].DATAIN
Din[2] => Bank[2].DATAIN
Din[2] => Equal14.IN6
Din[2] => Equal15.IN3
Din[3] => CmdUFMErase.DATAB
Din[3] => WRD[3].DATAIN
Din[3] => Bank[3].DATAIN
Din[3] => Equal14.IN5
Din[3] => Equal15.IN2
Din[4] => WRD[4].DATAIN
Din[4] => Bank[4].DATAIN
Din[4] => Equal14.IN4
Din[4] => Equal15.IN6
Din[4] => Equal16.IN3
Din[4] => Equal17.IN0
Din[4] => Equal18.IN3
Din[5] => WRD[5].DATAIN
Din[5] => Bank[5].DATAIN
Din[5] => Equal14.IN3
Din[5] => Equal15.IN1
Din[5] => Equal16.IN2
Din[5] => Equal17.IN3
Din[5] => Equal18.IN0
Din[6] => RA11.IN1
Din[6] => WRD[6].DATAIN
Din[6] => Bank[6].DATAIN
Din[6] => Equal14.IN1
Din[6] => Equal15.IN5
Din[6] => Equal16.IN1
Din[6] => Equal17.IN2
Din[6] => Equal18.IN2
Din[7] => WRD[7].DATAIN
Din[7] => Bank[7].DATAIN
Din[7] => Equal14.IN0
Din[7] => Equal15.IN0
Din[7] => Equal16.IN0
Din[7] => Equal17.IN1
Din[7] => Equal18.IN1
Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE
Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE
Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE
Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE
Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE
Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE
Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE
Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE
nCCAS => WRD[0].CLK
nCCAS => WRD[1].CLK
nCCAS => WRD[2].CLK
nCCAS => WRD[3].CLK
nCCAS => WRD[4].CLK
nCCAS => WRD[5].CLK
nCCAS => WRD[6].CLK
nCCAS => WRD[7].CLK
nCCAS => comb.IN0
nCCAS => CBR.DATAIN
nCCAS => CASr.DATAIN
nCRAS => CBR.CLK
nCRAS => FWEr.CLK
nCRAS => RowA[0].CLK
nCRAS => RowA[1].CLK
nCRAS => RowA[2].CLK
nCRAS => RowA[3].CLK
nCRAS => RowA[4].CLK
nCRAS => RowA[5].CLK
nCRAS => RowA[6].CLK
nCRAS => RowA[7].CLK
nCRAS => RowA[8].CLK
nCRAS => RowA[9].CLK
nCRAS => RBA[0]~reg0.CLK
nCRAS => RBA[1]~reg0.CLK
nCRAS => RASr.DATAIN
nFWE => comb.IN1
nFWE => CMDWR.IN1
nFWE => ADWR.IN1
nFWE => C1WR.IN1
nFWE => FWEr.DATAIN
RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE
RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE
RD[0] <> RD[0]
RD[1] <> RD[1]
RD[2] <> RD[2]
RD[3] <> RD[3]
RD[4] <> RD[4]
RD[5] <> RD[5]
RD[6] <> RD[6]
RD[7] <> RD[7]
nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
RCLK => UFMProgram.CLK
RCLK => UFMErase.CLK
RCLK => UFMReqErase.CLK
RCLK => n8MEGEN.CLK
RCLK => UFMInitDone.CLK
RCLK => UFMD.CLK
RCLK => DRShift.CLK
RCLK => DRDIn.CLK
RCLK => DRCLK.CLK
RCLK => ARShift.CLK
RCLK => ARCLK.CLK
RCLK => Ready.CLK
RCLK => IS[0].CLK
RCLK => IS[1].CLK
RCLK => IS[2].CLK
RCLK => IS[3].CLK
RCLK => nRowColSel.CLK
RCLK => RCKEEN.CLK
RCLK => RA10.CLK
RCLK => nRWE~reg0.CLK
RCLK => nRCAS~reg0.CLK
RCLK => nRRAS~reg0.CLK
RCLK => nRCS~reg0.CLK
RCLK => RCKE~reg0.CLK
RCLK => InitReady.CLK
RCLK => FS[0].CLK
RCLK => FS[1].CLK
RCLK => FS[2].CLK
RCLK => FS[3].CLK
RCLK => FS[4].CLK
RCLK => FS[5].CLK
RCLK => FS[6].CLK
RCLK => FS[7].CLK
RCLK => FS[8].CLK
RCLK => FS[9].CLK
RCLK => FS[10].CLK
RCLK => FS[11].CLK
RCLK => FS[12].CLK
RCLK => FS[13].CLK
RCLK => FS[14].CLK
RCLK => FS[15].CLK
RCLK => FS[16].CLK
RCLK => FS[17].CLK
RCLK => S[0].CLK
RCLK => S[1].CLK
RCLK => CASr3.CLK
RCLK => CASr2.CLK
RCLK => CASr.CLK
RCLK => RASr3.CLK
RCLK => RASr2.CLK
RCLK => RASr.CLK
RCLK => PHI2r3.CLK
RCLK => PHI2r2.CLK
RCLK => PHI2r.CLK
RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDQMH <= comb.DB_MAX_OUTPUT_PORT_TYPE
RDQML <= comb.DB_MAX_OUTPUT_PORT_TYPE
|RAM4GS|UFM:UFM_inst
arclk => arclk.IN1
ardin => ardin.IN1
arshft => arshft.IN1
drclk => drclk.IN1
drdin => drdin.IN1
drshft => drshft.IN1
erase => erase.IN1
oscena => oscena.IN1
program => program.IN1
busy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.busy
drdout <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.drdout
osc <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.osc
rtpbusy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.rtpbusy
|RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component
arclk => maxii_ufm_block1.ARCLK
ardin => maxii_ufm_block1.ARDIN
arshft => maxii_ufm_block1.ARSHFT
busy <= maxii_ufm_block1.BUSY
drclk => maxii_ufm_block1.DRCLK
drdin => maxii_ufm_block1.DRDIN
drdout <= maxii_ufm_block1.DRDOUT
drshft => maxii_ufm_block1.DRSHFT
erase => maxii_ufm_block1.ERASE
osc <= maxii_ufm_block1.OSC
oscena => maxii_ufm_block1.OSCENA
program => maxii_ufm_block1.PROGRAM
rtpbusy <= maxii_ufm_block1.BGPBUSY
Hardware/MAX/cpld/db/RAM4GS.hif
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Hardware/MAX/cpld/db/RAM4GS.ipinfo
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