From 3caa56c1afa0ee0a798aaf608cb4a2ab00f4bad4 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Tue, 15 Aug 2023 05:23:06 -0400 Subject: [PATCH] Delete old PLD stuff --- CPLD-old/LCMXO/LCMXO256C/.run_manager.ini | 9 - CPLD-old/LCMXO/LCMXO256C/.setting.ini | 4 - CPLD-old/LCMXO/LCMXO256C/.spread_sheet.ini | 3 - .../LCMXO/LCMXO256C/.spreadsheet_view.ini | 65 - CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ccl | 0 CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf | 14 - CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.lpf | 226 - .../LCMXO/LCMXO256C/RAM2GS_LCMXO256C1.sty | 205 - .../LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcl.html | 91 - .../pn210816194012.tcr | 17 - .../pn210816202808.tcr | 5 - .../pn210816213322.tcr | 4 - .../pn210816214112.tcr | 6 - CPLD-old/LCMXO/LCMXO256C/impl1/.build_status | 46 - .../.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb | Bin 65077 -> 0 bytes .../LCMXO256C/impl1/.vdbs/RAM2GS_rtl.vdb | Bin 72408 -> 0 bytes .../LCMXO256C/impl1/.vdbs/RAM2GS_tech.vdb | Bin 67067 -> 0 bytes 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{CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/RAM2GS_drc.log (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/RAM2GS_lse.twr (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/RAM2GS_lse_lsetwr.html (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/RAM2GS_prim.v (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/automake.log (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/hdla_gen_hierarchy.html (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/ram2gs_lcmxo2_640hc_impl1.ior (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/synthesis.log (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/synthesis_lse.html (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/xxx_lse_cp_file_list (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/impl1/xxx_lse_sign_file (100%) rename {CPLD-old/LCMXO2/LCMXO2-640HC => CPLD/LCMXO2-640HC-old}/msg_file.log (100%) create mode 100644 CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815052238.tcr rename CPLD/LCMXO640C/{RAM2GS_LCMXO256C1.sty => RAM2GS_LCMXO640C1.sty} (100%) create mode 100644 CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230815052236.tcr create mode 100644 CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230815052239.tcr rename {CPLD-old/LCMXO2 => CPLD}/RAM2GS-LCMXO2.v (100%) diff --git a/CPLD-old/LCMXO/LCMXO256C/.run_manager.ini b/CPLD-old/LCMXO/LCMXO256C/.run_manager.ini deleted file mode 100644 index be682d1..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/.run_manager.ini +++ /dev/null @@ -1,9 +0,0 @@ -[Runmanager] -Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) -windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x2\xc9\0\0\x2i\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) -headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) - -[impl1%3CStrategy1%3E] -isChecked=true -isHidden=false -isExpanded=true diff --git a/CPLD-old/LCMXO/LCMXO256C/.setting.ini b/CPLD-old/LCMXO/LCMXO256C/.setting.ini deleted file mode 100644 index c145fb8..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/.setting.ini +++ /dev/null @@ -1,4 +0,0 @@ -[General] -Export.auto_tasks=IBIS, Bitgen -Map.auto_tasks=MapEqu, MapTrace -PAR.auto_tasks=PARTrace, IOTiming diff --git a/CPLD-old/LCMXO/LCMXO256C/.spread_sheet.ini b/CPLD-old/LCMXO/LCMXO256C/.spread_sheet.ini deleted file mode 100644 index 6c511f4..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/.spread_sheet.ini +++ /dev/null @@ -1,3 +0,0 @@ -[General] -COLUMN_POS_INFO_NAME_-1_0=Prioritize -COLUMN_POS_INFO_NAME_-1_1=PIO Register diff --git a/CPLD-old/LCMXO/LCMXO256C/.spreadsheet_view.ini b/CPLD-old/LCMXO/LCMXO256C/.spreadsheet_view.ini deleted file mode 100644 index 0aa848d..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/.spreadsheet_view.ini +++ /dev/null @@ -1,65 +0,0 @@ -[General] -pin_sort_type=0 -pin_sort_ascending=true -sig_sort_type=0 -sig_sort_ascending=true -active_Sheet=Timing Preferences - -[Port%20Assignments] -Name="166,0" -Group%20By="84,1" -Pin="63,2" -BANK="62,3" -IO_TYPE="117,4" -PULLMODE="119,5" -DRIVE="67,6" -SLEWRATE="92,7" -OPENDRAIN="97,8" -Outload%20%28pF%29="103,9" -MaxSkew="87,10" -Clock%20Load%20Only="121,11" -sort_columns="Name,Ascending" - -[Pin%20Assignments] -Pin="90,0" -Pad%20Name="89,1" -Dual%20Function="109,2" -Polarity="77,3" -BANK="0,4" -IO_TYPE="117,5" -Signal%20Name="123,6" -Signal%20Type="115,7" -sort_columns="Pin,Ascending" - -[Clock%20Resource] -Clock%20Type="100,ELLIPSIS" -Clock%20Name="100,ELLIPSIS" -Selection="100,ELLIPSIS" - -[Global%20Preferences] -Preference%20Name="222,ELLIPSIS" -Preference%20Value="236,ELLIPSIS" - -[Cell%20Mapping] -Type="100,ELLIPSIS" -Name="100,ELLIPSIS" -Din\Dout="100,ELLIPSIS" -PIO%20Register="100,ELLIPSIS" - -[Route%20Priority] -Type="100,ELLIPSIS" -Name="100,ELLIPSIS" -Prioritize="100,ELLIPSIS" - -[Timing%20Preferences] -Preference%20Name="246,ELLIPSIS" -Preference%20Value="104,ELLIPSIS" -Preference%20Unit="1012,ELLIPSIS" - -[Group] -Group%20Type\Name="134,ELLIPSIS" -Value="1245,ELLIPSIS" - -[Misc%20Preferences] -Preference%20Name="117,ELLIPSIS" -Preference%20Value="104,ELLIPSIS" diff --git a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ccl b/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ccl deleted file mode 100644 index e69de29..0000000 diff --git a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf b/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf deleted file mode 100644 index 0accfcf..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.lpf b/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.lpf deleted file mode 100644 index 9fa278f..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.lpf +++ /dev/null @@ -1,226 +0,0 @@ -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -LOCATE COMP "Dout[0]" SITE "1" ; -LOCATE COMP "Dout[6]" SITE "2" ; -LOCATE COMP "Dout[7]" SITE "3" ; -LOCATE COMP "Dout[4]" SITE "4" ; -LOCATE COMP "Dout[5]" SITE "5" ; -LOCATE COMP "Dout[3]" SITE "6" ; -LOCATE COMP "Dout[1]" SITE "7" ; -LOCATE COMP "Dout[2]" SITE "8" ; -LOCATE COMP "Din[2]" SITE "14" ; -LOCATE COMP "Din[1]" SITE "15" ; -LOCATE COMP "Din[3]" SITE "16" ; -LOCATE COMP "Din[5]" SITE "17" ; -LOCATE COMP "Din[4]" SITE "18" ; -LOCATE COMP "Din[7]" SITE "19" ; -LOCATE COMP "Din[6]" SITE "20" ; -LOCATE COMP "Din[0]" SITE "21" ; -LOCATE COMP "LED" SITE "57" ; -LOCATE COMP "RA[0]" SITE "98" ; -LOCATE COMP "RA[1]" SITE "89" ; -LOCATE COMP "RA[2]" SITE "94" ; -LOCATE COMP "RA[3]" SITE "97" ; -LOCATE COMP "RA[4]" SITE "99" ; -LOCATE COMP "RA[5]" SITE "95" ; -LOCATE COMP "RA[6]" SITE "91" ; -LOCATE COMP "RA[7]" SITE "100" ; -LOCATE COMP "RA[8]" SITE "96" ; -LOCATE COMP "RA[9]" SITE "85" ; -LOCATE COMP "RA[10]" SITE "87" ; -LOCATE COMP "RA[11]" SITE "79" ; -LOCATE COMP "RBA[1]" SITE "83" ; -LOCATE COMP "RBA[0]" SITE "63" ; -LOCATE COMP "RCKE" SITE "82" ; -LOCATE COMP "RDQMH" SITE "76" ; -LOCATE COMP "RDQML" SITE "61" ; -LOCATE COMP "UFMCLK" SITE "58" ; -LOCATE COMP "UFMSDI" SITE "56" ; -LOCATE COMP "nUFMCS" SITE "53" ; -LOCATE COMP "nRCAS" SITE "78" ; -LOCATE COMP "nRCS" SITE "77" ; -LOCATE COMP "nRRAS" SITE "73" ; -LOCATE COMP "nRWE" SITE "72" ; -LOCATE COMP "RD[0]" SITE "64" ; -LOCATE COMP "RD[1]" SITE "65" ; -LOCATE COMP "RD[2]" SITE "66" ; -LOCATE COMP "RD[3]" SITE "67" ; -LOCATE COMP "RD[4]" SITE "68" ; -LOCATE COMP "RD[5]" SITE "69" ; -LOCATE COMP "RD[6]" SITE "70" ; -LOCATE COMP "RD[7]" SITE "71" ; -LOCATE COMP "PHI2" SITE "39" ; -LOCATE COMP "RCLK" SITE "86" ; -LOCATE COMP "nCCAS" SITE "27" ; -LOCATE COMP "nCRAS" SITE "43" ; -LOCATE COMP "CROW[0]" SITE "32" ; -LOCATE COMP "CROW[1]" SITE "34" ; -LOCATE COMP "UFMSDO" SITE "55" ; -LOCATE COMP "nFWE" SITE "22" ; -LOCATE COMP "MAin[0]" SITE "23" ; -LOCATE COMP "MAin[1]" SITE "38" ; -LOCATE COMP "MAin[2]" SITE "37" ; -LOCATE COMP "MAin[3]" SITE "47" ; -LOCATE COMP "MAin[4]" SITE "46" ; -LOCATE COMP "MAin[5]" SITE "45" ; -LOCATE COMP "MAin[6]" SITE "49" ; -LOCATE COMP "MAin[7]" SITE "44" ; -LOCATE COMP "MAin[8]" SITE "50" ; -LOCATE COMP "MAin[9]" SITE "51" ; -IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVTTL33 ; -IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ; -IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ; -IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ; -IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ; -OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; -OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; -OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; -OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; -OUTPUT PORT "nRWE" LOAD 10.000000 pF ; -OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; -OUTPUT PORT "nRCS" LOAD 10.000000 pF ; -OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; -OUTPUT PORT "RDQML" LOAD 10.000000 pF ; -OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; -OUTPUT PORT "RCKE" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "LED" LOAD 25.000000 pF ; -OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; -USE PRIMARY NET "PHI2_c" ; -USE PRIMARY NET "RCLK_c" ; -VOLTAGE 3.300 V; -VCCIO_DERATE BANK 0 PERCENT -5; -VCCIO_DERATE PERCENT -5; -VCCIO_DERATE BANK 1 PERCENT -5; -PERIOD NET "PHI2_c" 350.000000 ns ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -PERIOD NET "RCLK_c" 16.000000 ns ; -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; -USE PRIMARY NET "nCCAS_c" ; -USE PRIMARY NET "nCRAS_c" ; diff --git a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C1.sty b/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C1.sty deleted file mode 100644 index feec63c..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C1.sty +++ /dev/null @@ -1,205 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcl.html b/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcl.html deleted file mode 100644 index ddd739c..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcl.html +++ /dev/null @@ -1,91 +0,0 @@ - -Lattice TCL Log - - -
pn210816194012
-#Start recording tcl command: 8/16/2021 19:02:08
-#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
-prj_project new -name "RAM2GS_LCMXO256C" -impl "impl1" -dev LCMXO256C-3T100C -synthesis "lse"
-prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
-prj_project save
-prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
-prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
-prj_run PAR -impl impl1
-prj_run PAR -impl impl1
-prj_run Map -impl impl1
-prj_run Export -impl impl1
-prj_run PAR -impl impl1
-prj_run Map -impl impl1
-prj_run PAR -impl impl1
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-#Stop recording: 8/16/2021 19:40:12
-
-
-
-pn210816202808
-#Start recording tcl command: 8/16/2021 20:24:10
-#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
-prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf"
-prj_run Export -impl impl1 -forceAll
-#Stop recording: 8/16/2021 20:28:08
-
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- - diff --git a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816194012.tcr b/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816194012.tcr deleted file mode 100644 index c6ef2b4..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816194012.tcr +++ /dev/null @@ -1,17 +0,0 @@ -#Start recording tcl command: 8/16/2021 19:02:08 -#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C -prj_project new -name "RAM2GS_LCMXO256C" -impl "impl1" -dev LCMXO256C-3T100C -synthesis "lse" -prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v" -prj_project save -prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v" -prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v" -prj_run PAR -impl impl1 -prj_run PAR -impl impl1 -prj_run Map -impl impl1 -prj_run Export -impl impl1 -prj_run PAR -impl impl1 -prj_run Map -impl impl1 -prj_run PAR -impl impl1 -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceAll -#Stop recording: 8/16/2021 19:40:12 diff --git a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816202808.tcr b/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816202808.tcr deleted file mode 100644 index fa5fbe8..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816202808.tcr +++ /dev/null @@ -1,5 +0,0 @@ -#Start recording tcl command: 8/16/2021 20:24:10 -#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C -prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf" -prj_run Export -impl impl1 -forceAll -#Stop recording: 8/16/2021 20:28:08 diff --git a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816213322.tcr b/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816213322.tcr deleted file mode 100644 index 2a19da1..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816213322.tcr +++ /dev/null @@ -1,4 +0,0 @@ -#Start recording tcl command: 8/16/2021 21:33:16 -#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C -prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf" -#Stop recording: 8/16/2021 21:33:22 diff --git a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816214112.tcr b/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816214112.tcr deleted file mode 100644 index e2e3953..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn210816214112.tcr +++ /dev/null @@ -1,6 +0,0 @@ -#Start recording tcl command: 8/16/2021 21:32:14 -#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C -prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf" -prj_run Export -impl impl1 -forceAll -prj_run Export -impl impl1 -forceOne -#Stop recording: 8/16/2021 21:41:12 diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/.build_status b/CPLD-old/LCMXO/LCMXO256C/impl1/.build_status deleted file mode 100644 index b86a12b..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/.build_status +++ /dev/null @@ -1,46 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb b/CPLD-old/LCMXO/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb deleted file mode 100644 index 2ef13db145a25d3f598a8eb441654a402be32199..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 65077 zcmd6Q33OaXc3q>Xp4DHbrPW5KVdCvd3E%Cyw_$wqrZqm&v`gzWV=TPR>Dh zPWl|6>b-iu>eZ`P@4c#D|NnbGaCUMglX)$JU-VO7eReW8Soo|jo|t&s*}2?%o_yj< zh|fd|nPFz?;N{lU?R}E~JKvPQmj(^sCT8oWm(I@D?^&qxLLf3BW}>)vb^CgBZSV5U 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zY_ZoYDESrK^FXR&?DC5`D7Dc%E7d`7irHcHDIj(ixO>6G5r>Lb2FM5oIetN* z70gyz-4xAu)?!Si4-?He4Dd^$8M6$xjcr&x4XKX1{f2Cv^I%@{UP_&ap#cU* zDV}~~16t>2Q0K#iR`9^dmaXvzQ?VYqE=DYSxl6Oj*%GLG86t?L3M_K8d<9j{Es)`X;Q$xH{q0H)qI=Qu^5 z^b1TmR_3$5Vwd7X`=EmS(u*+&i(||@OAV}5u(nUaV%3-zNHHX6@rqAu#$wCsh{t7~G63sX^H|`Y8SjCZs_r2GK zZ@M5wq=&@JqrQ9CB36dh7LlBELe(6lV7_nj>|d&AW4`6#^Vp3;ta~aEfkVWg#U0h> zu3EKfR1mh4g-tHAYe-dxy(5Qt+?miR4k xjhDL0-m;DEOEy>)Ev%M}BzD++$R<|AUnO}cNAy(4q%@>tyyIR{wr_mn{{V8_x2pgE diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad deleted file mode 100644 index 0445323..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad +++ /dev/null @@ -1,271 +0,0 @@ -PAD Specification File -*************************** - -PART TYPE: LCMXO256C -Performance Grade: 3 -PACKAGE: TQFP100 -Package Status: Final Version 1.19 - -Mon Aug 16 21:32:33 2021 - -Pinout by Port Name: -+-----------+----------+--------------+------+----------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | Properties | -+-----------+----------+--------------+------+----------------------------------+ -| CROW[0] | 32/1 | LVTTL33_IN | PB2C | SLEW:FAST | -| CROW[1] | 34/1 | LVTTL33_IN | PB2D | SLEW:FAST | -| Din[0] | 21/1 | LVTTL33_IN | PL8A | SLEW:FAST | -| Din[1] | 15/1 | LVTTL33_IN | PL6A | SLEW:FAST | -| Din[2] | 14/1 | LVTTL33_IN | PL5D | SLEW:FAST | -| Din[3] | 16/1 | LVTTL33_IN | PL6B | SLEW:FAST | -| Din[4] | 18/1 | LVTTL33_IN | PL7B | SLEW:FAST | -| Din[5] | 17/1 | LVTTL33_IN | PL7A | SLEW:FAST | -| Din[6] | 20/1 | LVTTL33_IN | PL7D | SLEW:FAST | -| Din[7] | 19/1 | LVTTL33_IN | PL7C | SLEW:FAST | -| Dout[0] | 1/1 | LVTTL33_OUT | PL2A | DRIVE:4mA SLEW:SLOW | -| Dout[1] | 7/1 | LVTTL33_OUT | PL4A | DRIVE:4mA SLEW:SLOW | -| Dout[2] | 8/1 | LVTTL33_OUT | PL4B | DRIVE:4mA SLEW:SLOW | -| Dout[3] | 6/1 | LVTTL33_OUT | PL3D | DRIVE:4mA SLEW:SLOW | -| Dout[4] | 4/1 | LVTTL33_OUT | PL3B | DRIVE:4mA SLEW:SLOW | -| Dout[5] | 5/1 | LVTTL33_OUT | PL3C | DRIVE:4mA SLEW:SLOW | -| Dout[6] | 2/1 | LVTTL33_OUT | PL2B | DRIVE:4mA SLEW:SLOW | -| Dout[7] | 3/1 | LVTTL33_OUT | PL3A | DRIVE:4mA SLEW:SLOW | -| LED | 57/0 | LVTTL33_OUT | PR7B | DRIVE:16mA SLEW:SLOW | -| MAin[0] | 23/1 | LVTTL33_IN | PL9A | SLEW:FAST | -| MAin[1] | 38/1 | LVTTL33_IN | PB3C | SLEW:FAST | -| MAin[2] | 37/1 | LVTTL33_IN | PB3B | SLEW:FAST | -| MAin[3] | 47/1 | LVTTL33_IN | PB5A | SLEW:FAST | -| MAin[4] | 46/1 | LVTTL33_IN | PB4D | SLEW:FAST | -| MAin[5] | 45/1 | LVTTL33_IN | PB4C | SLEW:FAST | -| MAin[6] | 49/1 | LVTTL33_IN | PB5C | SLEW:FAST | -| MAin[7] | 44/1 | LVTTL33_IN | PB4B | SLEW:FAST | -| MAin[8] | 50/1 | LVTTL33_IN | PB5D | SLEW:FAST | -| MAin[9] | 51/0 | LVTTL33_IN | PR9B | SLEW:FAST | -| PHI2 | 39/1 | LVTTL33_IN | PB3D | SLEW:FAST | -| RA[0] | 98/0 | LVTTL33_OUT | PT2C | DRIVE:4mA SLEW:SLOW | -| RA[10] | 87/0 | LVTTL33_OUT | PT3D | DRIVE:4mA SLEW:SLOW | -| RA[11] | 79/0 | LVTTL33_OUT | PT5A | DRIVE:4mA SLEW:SLOW | -| RA[1] | 89/0 | LVTTL33_OUT | PT3C | DRIVE:4mA SLEW:SLOW | -| RA[2] | 94/0 | LVTTL33_OUT | PT3A | DRIVE:4mA SLEW:SLOW | -| RA[3] | 97/0 | LVTTL33_OUT | PT2D | DRIVE:4mA SLEW:SLOW | -| RA[4] | 99/0 | LVTTL33_OUT | PT2B | DRIVE:4mA SLEW:SLOW | -| RA[5] | 95/0 | LVTTL33_OUT | PT2F | DRIVE:4mA SLEW:SLOW | -| RA[6] | 91/0 | LVTTL33_OUT | PT3B | DRIVE:4mA SLEW:SLOW | -| RA[7] | 100/0 | LVTTL33_OUT | PT2A | DRIVE:4mA SLEW:SLOW | -| RA[8] | 96/0 | LVTTL33_OUT | PT2E | DRIVE:4mA SLEW:SLOW | -| RA[9] | 85/0 | LVTTL33_OUT | PT4B | DRIVE:4mA SLEW:SLOW | -| RBA[0] | 63/0 | LVTTL33_OUT | PR5D | DRIVE:4mA SLEW:SLOW | -| RBA[1] | 83/0 | LVTTL33_OUT | PT4C | DRIVE:4mA SLEW:SLOW | -| RCKE | 82/0 | LVTTL33_OUT | PT4D | DRIVE:4mA SLEW:SLOW | -| RCLK | 86/0 | LVTTL33_IN | PT4A | SLEW:FAST | -| RDQMH | 76/0 | LVTTL33_OUT | PR2A | DRIVE:4mA SLEW:SLOW | -| RDQML | 61/0 | LVTTL33_OUT | PR6A | DRIVE:4mA SLEW:SLOW | -| RD[0] | 64/0 | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[1] | 65/0 | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[2] | 66/0 | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[3] | 67/0 | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[4] | 68/0 | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[5] | 69/0 | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[6] | 70/0 | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[7] | 71/0 | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| UFMCLK | 58/0 | LVTTL33_OUT | PR7A | DRIVE:4mA SLEW:SLOW | -| UFMSDI | 56/0 | LVTTL33_OUT | PR7C | DRIVE:4mA SLEW:SLOW | -| UFMSDO | 55/0 | LVTTL33_IN | PR7D | SLEW:FAST PULL:KEEPER | -| nCCAS | 27/1 | LVTTL33_IN | PL9B | SLEW:FAST | -| nCRAS | 43/1 | LVTTL33_IN | PB4A | SLEW:FAST | -| nFWE | 22/1 | LVTTL33_IN | PL8B | SLEW:FAST | -| nRCAS | 78/0 | LVTTL33_OUT | PT5B | DRIVE:4mA SLEW:SLOW | -| nRCS | 77/0 | LVTTL33_OUT | PT5C | DRIVE:4mA SLEW:SLOW | -| nRRAS | 73/0 | LVTTL33_OUT | PR2B | DRIVE:4mA SLEW:SLOW | -| nRWE | 72/0 | LVTTL33_OUT | PR3A | DRIVE:4mA SLEW:SLOW | -| nUFMCS | 53/0 | LVTTL33_OUT | PR8B | DRIVE:4mA SLEW:SLOW | -+-----------+----------+--------------+------+----------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 3.3V | -| 1 | 3.3V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+---------------------+------------+--------------+------+---------------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | -+----------+---------------------+------------+--------------+------+---------------+ -| 1/1 | Dout[0] | LOCATED | LVTTL33_OUT | PL2A | | -| 2/1 | Dout[6] | LOCATED | LVTTL33_OUT | PL2B | | -| 3/1 | Dout[7] | LOCATED | LVTTL33_OUT | PL3A | | -| 4/1 | Dout[4] | LOCATED | LVTTL33_OUT | PL3B | | -| 5/1 | Dout[5] | LOCATED | LVTTL33_OUT | PL3C | | -| 6/1 | Dout[3] | LOCATED | LVTTL33_OUT | PL3D | | -| 7/1 | Dout[1] | LOCATED | LVTTL33_OUT | PL4A | | -| 8/1 | Dout[2] | LOCATED | LVTTL33_OUT | PL4B | | -| 9/1 | unused, PULL:UP | | | PL5A | | -| 11/1 | unused, PULL:UP | | | PL5B | | -| 13/1 | unused, PULL:UP | | | PL5C | | -| 14/1 | Din[2] | LOCATED | LVTTL33_IN | PL5D | GSR_PADN | -| 15/1 | Din[1] | LOCATED | LVTTL33_IN | PL6A | | -| 16/1 | Din[3] | LOCATED | LVTTL33_IN | PL6B | TSALLPAD | -| 17/1 | Din[5] | LOCATED | LVTTL33_IN | PL7A | | -| 18/1 | Din[4] | LOCATED | LVTTL33_IN | PL7B | | -| 19/1 | Din[7] | LOCATED | LVTTL33_IN | PL7C | | -| 20/1 | Din[6] | LOCATED | LVTTL33_IN | PL7D | | -| 21/1 | Din[0] | LOCATED | LVTTL33_IN | PL8A | | -| 22/1 | nFWE | LOCATED | LVTTL33_IN | PL8B | | -| 23/1 | MAin[0] | LOCATED | LVTTL33_IN | PL9A | | -| 27/1 | nCCAS | LOCATED | LVTTL33_IN | PL9B | | -| 29/1 | unused, PULL:UP | | | PB2A | | -| 30/1 | unused, PULL:UP | | | PB2B | | -| 32/1 | CROW[0] | LOCATED | LVTTL33_IN | PB2C | | -| 34/1 | CROW[1] | LOCATED | LVTTL33_IN | PB2D | | -| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 | -| 37/1 | MAin[2] | LOCATED | LVTTL33_IN | PB3B | | -| 38/1 | MAin[1] | LOCATED | LVTTL33_IN | PB3C | PCLKT1_0 | -| 39/1 | PHI2 | LOCATED | LVTTL33_IN | PB3D | | -| 43/1 | nCRAS | LOCATED | LVTTL33_IN | PB4A | | -| 44/1 | MAin[7] | LOCATED | LVTTL33_IN | PB4B | | -| 45/1 | MAin[5] | LOCATED | LVTTL33_IN | PB4C | | -| 46/1 | MAin[4] | LOCATED | LVTTL33_IN | PB4D | | -| 47/1 | MAin[3] | LOCATED | LVTTL33_IN | PB5A | | -| 49/1 | MAin[6] | LOCATED | LVTTL33_IN | PB5C | | -| 50/1 | MAin[8] | LOCATED | LVTTL33_IN | PB5D | | -| 51/0 | MAin[9] | LOCATED | LVTTL33_IN | PR9B | | -| 52/0 | unused, PULL:UP | | | PR9A | | -| 53/0 | nUFMCS | LOCATED | LVTTL33_OUT | PR8B | | -| 54/0 | unused, PULL:UP | | | PR8A | | -| 55/0 | UFMSDO | LOCATED | LVTTL33_IN | PR7D | | -| 56/0 | UFMSDI | LOCATED | LVTTL33_OUT | PR7C | | -| 57/0 | LED | LOCATED | LVTTL33_OUT | PR7B | | -| 58/0 | UFMCLK | LOCATED | LVTTL33_OUT | PR7A | | -| 59/0 | unused, PULL:UP | | | PR6B | | -| 61/0 | RDQML | LOCATED | LVTTL33_OUT | PR6A | | -| 63/0 | RBA[0] | LOCATED | LVTTL33_OUT | PR5D | | -| 64/0 | RD[0] | LOCATED | LVTTL33_BIDI | PR5C | | -| 65/0 | RD[1] | LOCATED | LVTTL33_BIDI | PR5B | | -| 66/0 | RD[2] | LOCATED | LVTTL33_BIDI | PR5A | | -| 67/0 | RD[3] | LOCATED | LVTTL33_BIDI | PR4B | | -| 68/0 | RD[4] | LOCATED | LVTTL33_BIDI | PR4A | | -| 69/0 | RD[5] | LOCATED | LVTTL33_BIDI | PR3D | | -| 70/0 | RD[6] | LOCATED | LVTTL33_BIDI | PR3C | | -| 71/0 | RD[7] | LOCATED | LVTTL33_BIDI | PR3B | | -| 72/0 | nRWE | LOCATED | LVTTL33_OUT | PR3A | | -| 73/0 | nRRAS | LOCATED | LVTTL33_OUT | PR2B | | -| 76/0 | RDQMH | LOCATED | LVTTL33_OUT | PR2A | | -| 77/0 | nRCS | LOCATED | LVTTL33_OUT | PT5C | | -| 78/0 | nRCAS | LOCATED | LVTTL33_OUT | PT5B | | -| 79/0 | RA[11] | LOCATED | LVTTL33_OUT | PT5A | | -| 80/0 | unused, PULL:UP | | | PT4F | | -| 81/0 | unused, PULL:UP | | | PT4E | | -| 82/0 | RCKE | LOCATED | LVTTL33_OUT | PT4D | | -| 83/0 | RBA[1] | LOCATED | LVTTL33_OUT | PT4C | | -| 85/0 | RA[9] | LOCATED | LVTTL33_OUT | PT4B | PCLKT0_1 | -| 86/0 | RCLK | LOCATED | LVTTL33_IN | PT4A | PCLKT0_0 | -| 87/0 | RA[10] | LOCATED | LVTTL33_OUT | PT3D | | -| 89/0 | RA[1] | LOCATED | LVTTL33_OUT | PT3C | | -| 91/0 | RA[6] | LOCATED | LVTTL33_OUT | PT3B | | -| 94/0 | RA[2] | LOCATED | LVTTL33_OUT | PT3A | | -| 95/0 | RA[5] | LOCATED | LVTTL33_OUT | PT2F | | -| 96/0 | RA[8] | LOCATED | LVTTL33_OUT | PT2E | | -| 97/0 | RA[3] | LOCATED | LVTTL33_OUT | PT2D | | -| 98/0 | RA[0] | LOCATED | LVTTL33_OUT | PT2C | | -| 99/0 | RA[4] | LOCATED | LVTTL33_OUT | PT2B | | -| 100/0 | RA[7] | LOCATED | LVTTL33_OUT | PT2A | | -| PB5B/0 | unused, PULL:UP | | | PB5B | | -| PT5D/0 | unused, PULL:UP | | | PT5D | | -| TCK/1 | | | | TCK | TCK | -| TDI/1 | | | | TDI | TDI | -| TDO/1 | | | | TDO | TDO | -| TMS/1 | | | | TMS | TMS | -+----------+---------------------+------------+--------------+------+---------------+ - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "CROW[0]" SITE "32"; -LOCATE COMP "CROW[1]" SITE "34"; -LOCATE COMP "Din[0]" SITE "21"; -LOCATE COMP "Din[1]" SITE "15"; -LOCATE COMP "Din[2]" SITE "14"; -LOCATE COMP "Din[3]" SITE "16"; -LOCATE COMP "Din[4]" SITE "18"; -LOCATE COMP "Din[5]" SITE "17"; -LOCATE COMP "Din[6]" SITE "20"; -LOCATE COMP "Din[7]" SITE "19"; -LOCATE COMP "Dout[0]" SITE "1"; -LOCATE COMP "Dout[1]" SITE "7"; -LOCATE COMP "Dout[2]" SITE "8"; -LOCATE COMP "Dout[3]" SITE "6"; -LOCATE COMP "Dout[4]" SITE "4"; -LOCATE COMP "Dout[5]" SITE "5"; -LOCATE COMP "Dout[6]" SITE "2"; -LOCATE COMP "Dout[7]" SITE "3"; -LOCATE COMP "LED" SITE "57"; -LOCATE COMP "MAin[0]" SITE "23"; -LOCATE COMP "MAin[1]" SITE "38"; -LOCATE COMP "MAin[2]" SITE "37"; -LOCATE COMP "MAin[3]" SITE "47"; -LOCATE COMP "MAin[4]" SITE "46"; -LOCATE COMP "MAin[5]" SITE "45"; -LOCATE COMP "MAin[6]" SITE "49"; -LOCATE COMP "MAin[7]" SITE "44"; -LOCATE COMP "MAin[8]" SITE "50"; -LOCATE COMP "MAin[9]" SITE "51"; -LOCATE COMP "PHI2" SITE "39"; -LOCATE COMP "RA[0]" SITE "98"; -LOCATE COMP "RA[10]" SITE "87"; -LOCATE COMP "RA[11]" SITE "79"; -LOCATE COMP "RA[1]" SITE "89"; -LOCATE COMP "RA[2]" SITE "94"; -LOCATE COMP "RA[3]" SITE "97"; -LOCATE COMP "RA[4]" SITE "99"; -LOCATE COMP "RA[5]" SITE "95"; -LOCATE COMP "RA[6]" SITE "91"; -LOCATE COMP "RA[7]" SITE "100"; -LOCATE COMP "RA[8]" SITE "96"; -LOCATE COMP "RA[9]" SITE "85"; -LOCATE COMP "RBA[0]" SITE "63"; -LOCATE COMP "RBA[1]" SITE "83"; -LOCATE COMP "RCKE" SITE "82"; -LOCATE COMP "RCLK" SITE "86"; -LOCATE COMP "RDQMH" SITE "76"; -LOCATE COMP "RDQML" SITE "61"; -LOCATE COMP "RD[0]" SITE "64"; -LOCATE COMP "RD[1]" SITE "65"; -LOCATE COMP "RD[2]" SITE "66"; -LOCATE COMP "RD[3]" SITE "67"; -LOCATE COMP "RD[4]" SITE "68"; -LOCATE COMP "RD[5]" SITE "69"; -LOCATE COMP "RD[6]" SITE "70"; -LOCATE COMP "RD[7]" SITE "71"; -LOCATE COMP "UFMCLK" SITE "58"; -LOCATE COMP "UFMSDI" SITE "56"; -LOCATE COMP "UFMSDO" SITE "55"; -LOCATE COMP "nCCAS" SITE "27"; -LOCATE COMP "nCRAS" SITE "43"; -LOCATE COMP "nFWE" SITE "22"; -LOCATE COMP "nRCAS" SITE "78"; -LOCATE COMP "nRCS" SITE "77"; -LOCATE COMP "nRRAS" SITE "73"; -LOCATE COMP "nRWE" SITE "72"; -LOCATE COMP "nUFMCS" SITE "53"; - - - - - -PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Mon Aug 16 21:32:33 2021 - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par deleted file mode 100644 index 5d8ae58..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par +++ /dev/null @@ -1,211 +0,0 @@ - -Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" -Mon Aug 16 21:32:27 2021 - -PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. -Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf -Preference file: RAM2GS_LCMXO256C_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 - -Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO256C -Package: TQFP100 -Performance: 3 -Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.19. -Performance Hardware Data Status: Version 1.124. -License checked out. - - -Ignore Preference Error(s): True -Device utilization summary: - - PIO (prelim) 67/79 84% used - 67/78 85% bonded - SLICE 65/128 50% used - - - -Number of Signals: 252 -Number of Connections: 618 - -Pin Constraint Summary: - 67 out of 67 pins locked (100% locked). - -The following 4 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 39) - PHI2_c (driver: PHI2, clk load #: 13) - nCCAS_c (driver: nCCAS, clk load #: 4) - nCRAS_c (driver: nCRAS, clk load #: 7) - -No signal is selected as secondary clock. - -No signal is selected as Global Set/Reset. -Starting Placer Phase 0. -........ -Finished Placer Phase 0. REAL time: 0 secs - -Starting Placer Phase 1. -............... -Placer score = 586066. -Finished Placer Phase 1. REAL time: 6 secs - -Starting Placer Phase 2. -. -Placer score = 584668 -Finished Placer Phase 2. REAL time: 6 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 1 out of 4 (25%) - General PIO: 3 out of 80 (3%) - -Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 - PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4 - PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7 - - PRIMARY : 4 out of 4 (100%) - SECONDARY: 0 out of 4 (0%) - ---------------- End of Clock Report --------------- - - -I/O Usage Summary (final): - 67 out of 79 (84.8%) PIO sites used. - 67 out of 78 (85.9%) bonded PIO sites used. - Number of PIO comps: 67; differential: 0. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+------------+------------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | -+----------+----------------+------------+------------+------------+ -| 0 | 36 / 41 ( 87%) | 3.3V | - | - | -| 1 | 31 / 37 ( 83%) | 3.3V | - | - | -+----------+----------------+------------+------------+------------+ - -Total placer CPU time: 6 secs - -Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. - -0 connections routed; 618 unrouted. -Starting router resource preassignment -WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. -WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. -WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. - -Completed router resource preassignment. Real time: 6 secs - -Start NBR router at 21:32:33 08/16/21 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at 21:32:33 08/16/21 - -Start NBR section for initial routing at 21:32:33 08/16/21 -Level 1, iteration 1 -0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs -Level 2, iteration 1 -0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs -Level 3, iteration 1 -0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.038ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at 21:32:33 08/16/21 -Level 1, iteration 1 -0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs -Level 4, iteration 2 -4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs -Level 4, iteration 3 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs - -Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21 - -Start NBR section for re-routing at 21:32:33 08/16/21 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs - -Start NBR section for post-routing at 21:32:33 08/16/21 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 0 (0.00%) - Estimated worst slack : 2.023ns - Timing score : 0 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - -Total CPU time 6 secs -Total REAL time: 7 secs -Completely routed. -End of route. 618 routed (100.00%); 0 unrouted. - -Hold time timing score: 0, hold timing errors: 0 - -Timing score: 0 - -Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. - - -All signals are completely routed. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = 2.023 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Worst slack> = 0.339 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 6 secs -Total REAL time to completion: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd deleted file mode 100644 index 6e5f093..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd +++ /dev/null @@ -1,33 +0,0 @@ -[ActiveSupport PAR] -; Global primary clocks -GLOBAL_PRIMARY_USED = 4; -; Global primary clock #0 -GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; -GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN; -GLOBAL_PRIMARY_0_LOADNUM = 39; -; Global primary clock #1 -GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; -GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_1_LOADNUM = 13; -; Global primary clock #2 -GLOBAL_PRIMARY_2_SIGNALNAME = nCCAS_c; -GLOBAL_PRIMARY_2_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_2_LOADNUM = 4; -; Global primary clock #3 -GLOBAL_PRIMARY_3_SIGNALNAME = nCRAS_c; -GLOBAL_PRIMARY_3_DRIVERTYPE = PIO; -GLOBAL_PRIMARY_3_LOADNUM = 7; -; # of global secondary clocks -GLOBAL_SECONDARY_USED = 0; -; I/O Bank 0 Usage -BANK_0_USED = 36; -BANK_0_AVAIL = 41; -BANK_0_VCCIO = 3.3V; -BANK_0_VREF1 = NA; -BANK_0_VREF2 = NA; -; I/O Bank 1 Usage -BANK_1_USED = 31; -BANK_1_AVAIL = 37; -BANK_1_VCCIO = 3.3V; -BANK_1_VREF1 = NA; -BANK_1_VREF2 = NA; diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par deleted file mode 100644 index feb14ae..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par +++ /dev/null @@ -1,28 +0,0 @@ -PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Mon Aug 16 21:32:27 2021 - -C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t -RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir -RAM2GS_LCMXO256C_impl1.prf -gui -msgset -C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml - - -Preference file: RAM2GS_LCMXO256C_impl1.prf. - -Level/ Number Worst Timing Worst Timing Run NCD -Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ----------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 2.023 0 0.339 0 07 Completed - -* : Design saved. - -Total (real) run time for 1-seed: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc deleted file mode 100644 index ec074a2..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc +++ /dev/null @@ -1 +0,0 @@ -DRC detected 0 errors and 0 warnings. diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed deleted file mode 100644 index b3a7f61..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed +++ /dev/null @@ -1,977 +0,0 @@ - -* -NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12* -NOTE Version: Diamond (64-bit) 3.12.0.240.2* -NOTE Readback: Off* -NOTE Security: Off* -NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * -NOTE All Rights Reserved * -NOTE DATE CREATED: Mon Aug 16 21:36:26 2021 * -NOTE DESIGN NAME: RAM2GS * -NOTE DEVICE NAME: LCMXO256C-3TQFP100 * -NOTE PIN ASSIGNMENTS * -NOTE PINS RD[7] : 71 : inout * -NOTE PINS RD[6] : 70 : inout * -NOTE PINS RD[5] : 69 : inout * -NOTE PINS RD[4] : 68 : inout * -NOTE PINS RD[3] : 67 : inout * -NOTE PINS RD[2] : 66 : inout * -NOTE PINS RD[1] : 65 : inout * -NOTE PINS RD[0] : 64 : inout * -NOTE PINS Dout[7] : 3 : out * -NOTE PINS Dout[6] : 2 : out * -NOTE PINS Dout[5] : 5 : out * -NOTE PINS Dout[4] : 4 : out * -NOTE PINS Dout[3] : 6 : out * -NOTE PINS Dout[2] : 8 : out * -NOTE PINS Dout[1] : 7 : out * -NOTE PINS Dout[0] : 1 : out * -NOTE PINS LED : 57 : out * -NOTE PINS RBA[1] : 83 : out * -NOTE PINS RBA[0] : 63 : out * -NOTE PINS RA[11] : 79 : out * -NOTE PINS RA[10] : 87 : out * -NOTE PINS RA[9] : 85 : out * -NOTE PINS RA[8] : 96 : out * -NOTE PINS RA[7] : 100 : out * -NOTE PINS RA[6] : 91 : out * -NOTE PINS RA[5] : 95 : out * -NOTE PINS RA[4] : 99 : out * -NOTE PINS RA[3] : 97 : out * -NOTE PINS RA[2] : 94 : out * -NOTE PINS RA[1] : 89 : out * -NOTE PINS RA[0] : 98 : out * -NOTE PINS nRCS : 77 : out * -NOTE PINS RCKE : 82 : out * -NOTE PINS nRWE : 72 : out * -NOTE PINS nRRAS : 73 : out * -NOTE PINS nRCAS : 78 : out * -NOTE PINS RDQMH : 76 : out * -NOTE PINS RDQML : 61 : out * -NOTE PINS nUFMCS : 53 : out * -NOTE PINS UFMCLK : 58 : out * -NOTE PINS UFMSDI : 56 : out * -NOTE PINS PHI2 : 39 : in * -NOTE PINS MAin[9] : 51 : in * -NOTE PINS MAin[8] : 50 : in * -NOTE PINS MAin[7] : 44 : in * -NOTE PINS MAin[6] : 49 : in * -NOTE PINS MAin[5] : 45 : in * -NOTE PINS MAin[4] : 46 : in * -NOTE PINS MAin[3] : 47 : in * -NOTE PINS MAin[2] : 37 : in * -NOTE PINS MAin[1] : 38 : in * -NOTE PINS MAin[0] : 23 : in * -NOTE PINS CROW[1] : 34 : in * -NOTE PINS CROW[0] : 32 : in * -NOTE PINS Din[7] : 19 : in * -NOTE PINS Din[6] : 20 : in * -NOTE PINS Din[5] : 17 : in * -NOTE PINS Din[4] : 18 : in * -NOTE PINS Din[3] : 16 : in * -NOTE PINS Din[2] : 14 : in * -NOTE PINS Din[1] : 15 : in * -NOTE PINS Din[0] : 21 : in * -NOTE PINS nCCAS : 27 : in * -NOTE PINS nCRAS : 43 : in * -NOTE PINS nFWE : 22 : in * -NOTE PINS RCLK : 86 : in * -NOTE PINS UFMSDO : 55 : in * -NOTE CONFIGURATION MODE: NONE * -NOTE COMPRESSION: off * - - -QF56640* -G0* -F0* -L00000 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp deleted file mode 100644 index d38f4ce..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp +++ /dev/null @@ -1,402 +0,0 @@ - - Lattice Mapping Report File for Design Module 'RAM2GS' - - -Design Information ------------------- - -Command line: map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial - RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr - RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf C:/Users/Dog - /Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1. - lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_L - CMXO256C.lpf -c 0 -gui -msgset - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -Target Vendor: LATTICE -Target Device: LCMXO256CTQFP100 -Target Performance: 3 -Mapper: mj5g00, version: Diamond (64-bit) 3.12.0.240.2 -Mapped on: 08/16/21 21:32:26 - -Design Summary --------------- - - Number of PFU registers: 102 out of 256 (40%) - Number of SLICEs: 65 out of 128 (51%) - SLICEs as Logic/ROM: 65 out of 128 (51%) - SLICEs as RAM: 0 out of 64 (0%) - SLICEs as Carry: 9 out of 128 (7%) - Number of LUT4s: 129 out of 256 (50%) - Number used as logic LUTs: 111 - Number used as distributed RAM: 0 - Number used as ripple logic: 18 - Number used as shift registers: 0 - Number of external PIOs: 67 out of 78 (86%) - Number of GSRs: 0 out of 1 (0%) - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - Number of TSALL: 0 out of 1 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of - distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and - ripple logic. - Number of clocks: 4 - Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK ) - Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) - Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) - Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) - Number of Clock Enables: 13 - Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs - Net RCLK_c_enable_6: 1 loads, 1 LSLICEs - Net RCLK_c_enable_4: 3 loads, 3 LSLICEs - Net RCLK_c_enable_24: 2 loads, 2 LSLICEs - Net RCLK_c_enable_3: 1 loads, 1 LSLICEs - Net RCLK_c_enable_7: 1 loads, 1 LSLICEs - Net RCLK_c_enable_23: 8 loads, 8 LSLICEs - Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs - Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs - Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs - Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs - - Page 1 - - - - -Design: RAM2GS Date: 08/16/21 21:32:26 - -Design Summary (cont) ---------------------- - Net RCLK_c_enable_25: 1 loads, 1 LSLICEs - Net Ready_N_268: 1 loads, 1 LSLICEs - Number of LSRs: 9 - Net RASr2: 1 loads, 1 LSLICEs - Net C1Submitted_N_225: 2 loads, 2 LSLICEs - Net n2299: 1 loads, 1 LSLICEs - Net nRowColSel_N_35: 1 loads, 1 LSLICEs - Net nRowColSel_N_34: 1 loads, 1 LSLICEs - Net LEDEN_N_88: 1 loads, 1 LSLICEs - Net n2291: 2 loads, 2 LSLICEs - Net Ready: 7 loads, 7 LSLICEs - Net nRWE_N_173: 1 loads, 1 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net Ready: 19 loads - Net InitReady: 17 loads - Net RASr2: 16 loads - Net nRowColSel_N_35: 14 loads - Net nRowColSel: 13 loads - Net Din_c_6: 9 loads - Net MAin_c_1: 9 loads - Net Din_c_5: 8 loads - Net FS_11: 8 loads - Net MAin_c_0: 8 loads - - - - - Number of warnings: 0 - Number of errors: 0 - - -Design Errors/Warnings ----------------------- - - No errors or warnings present. - -IO (PIO) Attributes -------------------- - -+---------------------+-----------+-----------+------------+------------+ -| IO Name | Direction | Levelmode | IO | FIXEDDELAY | -| | | IO_TYPE | Register | | -+---------------------+-----------+-----------+------------+------------+ -| RD[7] | BIDIR | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RD[6] | BIDIR | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RD[5] | BIDIR | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RD[4] | BIDIR | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RD[3] | BIDIR | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RD[2] | BIDIR | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ - - Page 2 - - - - -Design: RAM2GS Date: 08/16/21 21:32:26 - -IO (PIO) Attributes (cont) --------------------------- -| RD[1] | BIDIR | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RD[0] | BIDIR | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Dout[7] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Dout[6] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Dout[5] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Dout[4] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Dout[3] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Dout[2] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Dout[1] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Dout[0] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| LED | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RBA[1] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RBA[0] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[11] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[10] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[9] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[8] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[7] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[6] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[5] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[4] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[3] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[2] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[1] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RA[0] | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| nRCS | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RCKE | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| nRWE | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ - - Page 3 - - - - -Design: RAM2GS Date: 08/16/21 21:32:26 - -IO (PIO) Attributes (cont) --------------------------- -| nRRAS | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| nRCAS | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RDQMH | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RDQML | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| nUFMCS | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| UFMCLK | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| UFMSDI | OUTPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| PHI2 | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| MAin[9] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| MAin[8] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| MAin[7] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| MAin[6] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| MAin[5] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| MAin[4] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| MAin[3] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| MAin[2] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| MAin[1] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| MAin[0] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| CROW[1] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| CROW[0] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Din[7] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Din[6] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Din[5] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Din[4] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Din[3] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Din[2] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Din[1] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| Din[0] | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ - - Page 4 - - - - -Design: RAM2GS Date: 08/16/21 21:32:26 - -IO (PIO) Attributes (cont) --------------------------- -| nCCAS | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| nCRAS | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| nFWE | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| RCLK | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ -| UFMSDO | INPUT | LVTTL33 | | | -+---------------------+-----------+-----------+------------+------------+ - -Removed logic -------------- - -Block i2 undriven or does not drive anything - clipped. -Block GSR_INST undriven or does not drive anything - clipped. -Signal PHI2_N_114 was merged into signal PHI2_c -Signal nCRAS_N_9 was merged into signal nCRAS_c -Signal nCCAS_N_3 was merged into signal nCCAS_c -Signal n2302 was merged into signal nRowColSel_N_35 -Signal nRWE_N_172 was merged into signal nRWE_N_173 -Signal n2307 was merged into signal Ready -Signal RASr2_N_63 was merged into signal RASr2 -Signal n1377 was merged into signal nRowColSel_N_34 -Signal n2306 was merged into signal nFWE_c -Signal UFMSDO_N_74 was merged into signal UFMSDO_c -Signal GND_net undriven or does not drive anything - clipped. -Signal VCC_net undriven or does not drive anything - clipped. -Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped. -Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped. -Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped. -Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped. -Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped. -Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped. -Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped. -Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped. -Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped. -Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped. -Block i1962 was optimized away. -Block i1961 was optimized away. -Block i1963 was optimized away. -Block i1070_1_lut_rep_25 was optimized away. -Block nRWE_I_49_1_lut was optimized away. -Block i604_1_lut_rep_30 was optimized away. -Block RASr2_I_0_1_lut was optimized away. -Block i1069_1_lut was optimized away. -Block i1_1_lut_rep_29 was optimized away. -Block UFMSDO_I_0_1_lut was optimized away. -Block i1 was optimized away. - -Run Time and Memory Usage -------------------------- - - Total CPU Time: 0 secs - Total REAL Time: 0 secs - Peak Memory Usage: 29 MB - - Page 5 - - - - -Design: RAM2GS Date: 08/16/21 21:32:26 - -Run Time and Memory Usage (cont) --------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Page 6 - - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. - Copyright (c) 1995 AT&T Corp. All rights reserved. - Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. - Copyright (c) 2001 Agere Systems All rights reserved. - Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights - reserved. diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt deleted file mode 100644 index 2d70ad1..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt +++ /dev/null @@ -1,9 +0,0 @@ --v -1 - - --gt - - --mapchkpnt 0 --sethld diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e deleted file mode 100644 index c5da0e1..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e +++ /dev/null @@ -1,574 +0,0 @@ - -comp 0: SLICE_0 (FSLICE) - -comp 1: SLICE_1 (FSLICE) - -comp 2: SLICE_2 (FSLICE) - -comp 3: SLICE_3 (FSLICE) - -comp 4: SLICE_4 (FSLICE) - -comp 5: SLICE_5 (FSLICE) - -comp 6: SLICE_6 (FSLICE) - -comp 7: SLICE_7 (FSLICE) - -comp 8: SLICE_8 (FSLICE) - -comp 9: SLICE_9 (FSLICE) -n1361 = ((ADSubmitted*(~MAin_c_1+n2290))+ADSubmitted_N_234) -ADSubmitted.D = n1361 -ADSubmitted.CLK = ~PHI2_c -ADSubmitted.SP = VCC -ADSubmitted.LSR = C1Submitted_N_225 -n2080 = (~MAin_c_0*(~ADSubmitted*n2122)) - -comp 10: SLICE_14 (FSLICE) -n2386 = GND -C1Submitted.D = n2386 -C1Submitted.CLK = ~PHI2_c -C1Submitted.SP = PHI2_N_114_enable_1 -C1Submitted.LSR = C1Submitted_N_225 -n2098 = (MAin_c_0*(~C1Submitted*(MAin_c_1*n2108))) - -comp 11: SLICE_18 (FSLICE) -CmdEnable_N_236 = (ADSubmitted_N_234+C1Submitted_N_225) -CmdEnable.D = CmdEnable_N_236 -CmdEnable.CLK = ~PHI2_c -CmdEnable.SP = PHI2_N_114_enable_8 -CmdEnable.LSR = GND -XOR8MEG_N_112 = (~n2290*(CmdEnable*(MAin_c_0*~MAin_c_1))) - -comp 12: SLICE_19 (FSLICE) -n2387\000/BUF1 = VCC -CmdSubmitted.D = n2387\000/BUF1 -CmdSubmitted.CLK = ~PHI2_c -CmdSubmitted.SP = PHI2_N_114_enable_6 -CmdSubmitted.LSR = GND -n2308 = (~PHI2r2*(CmdSubmitted*PHI2r3)) - -comp 13: SLICE_23 (FSLICE) -Cmdn8MEGEN_N_248 = (~n2296*(~Din_c_5*~Din_c_0+Din_c_5*n8MEGEN)+n2296*n8MEGEN) -Cmdn8MEGEN.D = Cmdn8MEGEN_N_248 -Cmdn8MEGEN.CLK = ~PHI2_c -Cmdn8MEGEN.SP = PHI2_N_114_enable_6 -Cmdn8MEGEN.LSR = GND -n2296 = (~Din_c_4+(Din_c_6+Din_c_7)) - -comp 14: SLICE_25 (FSLICE) -n2387 = VCC -InitReady.D = n2387 -InitReady.CLK = RCLK_c -InitReady.SP = RCLK_c_enable_6 -InitReady.LSR = GND -RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3))) - -comp 15: SLICE_31 (FSLICE) -RA11_N_180 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG) -RA_c.D = RA11_N_180 -RA_c.CLK = PHI2_c -RA_c.SP = VCC -RA_c.LSR = ~Ready -n2385 = (Din_c_6+Din_c_7) - -comp 16: SLICE_33 (FSLICE) -RCKEEN_N_115 = (~Ready*InitReady+Ready*RCKEEN_N_116) -RCKEEN.D = RCKEEN_N_115 -RCKEEN.CLK = RCLK_c -RCKEEN.SP = RCLK_c_enable_4 -RCKEEN.LSR = GND -RCLK_c_enable_7 = (~n2119*(InitReady*n2308)+n2119*(~InitReady*~FS_5+InitReady*n2308)) - -comp 17: SLICE_34 (FSLICE) -RCKE_N_128 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN)) -RCKE_c.D = RCKE_N_128 -RCKE_c.CLK = RCLK_c -RCKE_c.SP = VCC -RCKE_c.LSR = GND -nRWE_N_178 = (~RCKE_c+RASr2) -CASr2.D = CASr -CASr2.CLK = RCLK_c -CASr2.SP = VCC -CASr2.LSR = GND - -comp 18: SLICE_35 (FSLICE) -n2387\001/BUF1 = VCC -Ready.D = n2387\001/BUF1 -Ready.CLK = RCLK_c -Ready.SP = Ready_N_268 -Ready.LSR = GND -RCLK_c_enable_23 = (InitReady*(RASr2*(nRowColSel_N_35*~Ready))) - -comp 19: SLICE_42 (FSLICE) -UFMCLK_N_212 = (~n2076*(~InitReady*FS_4+InitReady*CmdUFMCLK)+n2076*(InitReady*CmdUFMCLK)) -UFMCLK_c.D = UFMCLK_N_212 -UFMCLK_c.CLK = RCLK_c -UFMCLK_c.SP = RCLK_c_enable_24 -UFMCLK_c.LSR = n2291 -RCLK_c_enable_6 = (n2076*FS_10) - -comp 20: SLICE_43 (FSLICE) -UFMSDI_N_219 = (~InitReady*n1895+InitReady*CmdUFMSDI) -UFMSDI_c.D = UFMSDI_N_219 -UFMSDI_c.CLK = RCLK_c -UFMSDI_c.SP = RCLK_c_enable_24 -UFMSDI_c.LSR = n2291 -n1895 = (~FS_10*(n2103*(~n2293*FS_6))) - -comp 21: SLICE_55 (FSLICE) -n2128 = (((n2297+n2301)+nRCAS_N_161)+Ready) -n980.D = n2128 -n980.CLK = RCLK_c -n980.SP = VCC -n980.LSR = ~nRWE_N_173 -n2301 = (~InitReady+~RASr2) - -comp 22: SLICE_56 (FSLICE) -n8MEGEN_N_94 = (~n4*(~FS_10*Cmdn8MEGEN+FS_10*~UFMSDO_c)+n4*Cmdn8MEGEN) -n8MEGEN.D = n8MEGEN_N_94 -n8MEGEN.CLK = RCLK_c -n8MEGEN.SP = RCLK_c_enable_7 -n8MEGEN.LSR = GND -n4 = ((~FS_11+n2300)+InitReady) - -comp 23: SLICE_58 (FSLICE) -nRCAS_N_157 = (~nRowColSel_N_35*(~n2117+~Ready)+nRowColSel_N_35*n2287) -nRCAS_c.D = nRCAS_N_157 -nRCAS_c.CLK = RCLK_c -nRCAS_c.SP = RCLK_c_enable_4 -nRCAS_c.LSR = GND -n2287 = (~n2248*(~Ready*~RASr2+Ready*(~RASr2+~CBR))+n2248*(~Ready+(~RASr2+~CBR))) - -comp 24: SLICE_60 (FSLICE) -nRCS_N_132 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~n2117*~nRowColSel_N_35))*Ready)+((~InitReady+nRCS_N_135+~RASr2+~nRowColSel_N_35)*~Ready) -nRCS_c.D = nRCS_N_132 -nRCS_c.CLK = RCLK_c -nRCS_c.SP = RCLK_c_enable_4 -nRCS_c.LSR = GND - -comp 25: SLICE_61 (FSLICE) -n33 = (~Ready*(n2244+n2297)+Ready*(n2244+n18)) -nRRAS_c.D = n33 -nRRAS_c.CLK = RCLK_c -nRRAS_c.SP = VCC -nRRAS_c.LSR = GND -n50 = ((nRowColSel_N_33+nRRAS_c)+nRowColSel_N_32) -RASr.D = ~nCRAS_c -RASr.CLK = RCLK_c -RASr.SP = VCC -RASr.LSR = GND - -comp 26: SLICE_62 (FSLICE) -n1369 = (~n2308*nUFMCS_c+n2308*~CmdUFMCS) -nRWE_N_173.D = n705 -nRWE_N_173.CLK = RCLK_c -nRWE_N_173.SP = RCLK_c_enable_23 -nRWE_N_173.LSR = GND -nRCS_N_135.D = Ready_N_272 -nRCS_N_135.CLK = RCLK_c -nRCS_N_135.SP = RCLK_c_enable_23 -nRCS_N_135.LSR = GND - -comp 27: SLICE_63 (FSLICE) -nRWE_N_167 = (~n2292*(~Ready*~n2164+Ready*nRWE_N_174)+n2292*(~Ready+nRWE_N_174)) -nRWE_c.D = nRWE_N_167 -nRWE_c.CLK = RCLK_c -nRWE_c.SP = RCLK_c_enable_3 -nRWE_c.LSR = GND -nRWE_N_174 = (~nRowColSel_N_35*(~n1+n1627)+nRowColSel_N_35*nRWE_N_178) - -comp 28: SLICE_64 (FSLICE) -n1368 = (~nRowColSel_N_32*(nRowColSel+n1627)+nRowColSel_N_32*(~nRowColSel_N_28+n1627)) -nRowColSel.D = n1368 -nRowColSel.CLK = RCLK_c -nRowColSel.SP = VCC -nRowColSel.LSR = n2299 -RA_c_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4) - -comp 29: SLICE_65 (FSLICE) -n1628 = (nRowColSel_N_32+nRowColSel_N_33) -nRowColSel_N_32.D = n1628 -nRowColSel_N_32.CLK = RCLK_c -nRowColSel_N_32.SP = VCC -nRowColSel_N_32.LSR = ~RASr2 -RCLK_c_enable_4 = (((nRowColSel_N_32+n2299)+nRowColSel_N_34)+nRowColSel_N_33) - -comp 30: SLICE_66 (FSLICE) -n1135 = (RASr2*~nRowColSel_N_32) -nRowColSel_N_33.D = n1135 -nRowColSel_N_33.CLK = RCLK_c -nRowColSel_N_33.SP = VCC -nRowColSel_N_33.LSR = ~nRowColSel_N_34 -n2117 = (~nRowColSel_N_33*(n1*~nRowColSel_N_34)+nRowColSel_N_33*(~n2304*~nRowColSel_N_34)) - -comp 31: SLICE_67 (FSLICE) -LED_N_90 = (~LEDEN+nCRAS_c) -nRowColSel_N_34.D = n1135 -nRowColSel_N_34.CLK = RCLK_c -nRowColSel_N_34.SP = VCC -nRowColSel_N_34.LSR = ~nRowColSel_N_35 -n2154 = (MAin_c_4*Bank_7) - -comp 32: SLICE_68 (FSLICE) -n2168 = (FS_3*(FS_2*(FS_0*FS_1))) -nRowColSel_N_35.D = ~RASr2 -nRowColSel_N_35.CLK = RCLK_c -nRowColSel_N_35.SP = VCC -nRowColSel_N_35.LSR = GND -n962 = (nCCAS_c+nFWE_c) -CASr3.D = CASr2 -CASr3.CLK = RCLK_c -CASr3.SP = VCC -CASr3.LSR = GND - -comp 33: SLICE_69 (FSLICE) -n1348 = (~InitReady*n2076+InitReady*n1369) -nUFMCS_c.D = n1348 -nUFMCS_c.CLK = RCLK_c -nUFMCS_c.SP = VCC -nUFMCS_c.LSR = LEDEN_N_88 -n2076 = (FS_17*(FS_11*(n12_adj_2*FS_15))) - -comp 34: i1912/SLICE_70 (FSLICE) -n2244 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~nRowColSel_N_35*n50))*Ready)+(((~nRowColSel_N_35*n50)+~InitReady+~RASr2)*~Ready) - -comp 35: RCKEEN_I_0_419/SLICE_71 (FSLICE) -RCKEEN_N_116 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11_adj_3*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35) - -comp 36: SLICE_72 (FSLICE) -PHI2_N_114_enable_7 = (Din_c_5*(~n2296*(n2298*XOR8MEG_N_112))) -n702.D = n703 -n702.CLK = RCLK_c -n702.SP = RCLK_c_enable_23 -n702.LSR = GND -n2298 = (((Din_c_6+Din_c_7)+Din_c_5)+Din_c_4) -n701.D = n702 -n701.CLK = RCLK_c -n701.SP = RCLK_c_enable_23 -n701.LSR = GND - -comp 37: SLICE_73 (FSLICE) -n11 = (~n2168+((~FS_11+n2300)+FS_6)) -n706.D = n707 -n706.CLK = RCLK_c -n706.SP = RCLK_c_enable_23 -n706.LSR = GND -n2300 = ((FS_16+n10)+FS_17) -n705.D = n706 -n705.CLK = RCLK_c -n705.SP = RCLK_c_enable_23 -n705.LSR = GND - -comp 38: SLICE_74 (FSLICE) -C1Submitted_N_225 = (~n2131*(~Din_c_2*(n2295*n2122))) -n710.D = n711 -n710.CLK = RCLK_c -n710.SP = RCLK_c_enable_23 -n710.LSR = GND -n2295 = (n2114*~nFWE_c) -n709.D = n710 -n709.CLK = RCLK_c -n709.SP = RCLK_c_enable_23 -n709.LSR = GND - -comp 39: SLICE_75 (FSLICE) -n2119 = (~n12*(~n11*(FS_10*n2294))) -n708.D = n709 -n708.CLK = RCLK_c -n708.SP = RCLK_c_enable_23 -n708.LSR = GND -RCLK_c_enable_25 = (n2119*(FS_5*~InitReady)) -n707.D = n708 -n707.CLK = RCLK_c -n707.SP = RCLK_c_enable_23 -n707.LSR = GND - -comp 40: SLICE_76 (FSLICE) -n2131 = ((~MAin_c_1+n1285)+MAin_c_0) -WRD_0.D = Din_c_0 -WRD_0.CLK = ~nCCAS_c -WRD_0.SP = VCC -WRD_0.LSR = GND -n1285 = (~MAin_c_5+(~n2170+(~Bank_3+n26))) -WRD_1.D = Din_c_1 -WRD_1.CLK = ~nCCAS_c -WRD_1.SP = VCC -WRD_1.LSR = GND - -comp 41: SLICE_77 (FSLICE) -PHI2_N_114_enable_8 = (~MAin_c_1*(~n2286*(~n2290*MAin_c_0))+MAin_c_1*(~n2286*~n2290)) -RowA_2.D = MAin_c_2 -RowA_2.CLK = ~nCRAS_c -RowA_2.SP = VCC -RowA_2.LSR = ~Ready -n2286 = (n2114*(~Din_c_2*n2080+Din_c_2*n2098)) -RowA_3.D = MAin_c_3 -RowA_3.CLK = ~nCRAS_c -RowA_3.SP = VCC -RowA_3.LSR = ~Ready - -comp 42: SLICE_78 (FSLICE) -n10 = (((FS_14+FS_13)+FS_12)+FS_15) -CASr.D = ~nCCAS_c -CASr.CLK = RCLK_c -CASr.SP = VCC -CASr.LSR = GND -n2294 = (((FS_16+n10)+FS_17)+FS_11) -PHI2r2.D = PHI2r -PHI2r2.CLK = RCLK_c -PHI2r2.SP = VCC -PHI2r2.LSR = GND - -comp 43: SLICE_79 (FSLICE) -n1627 = (nRowColSel_N_34+nRowColSel_N_33) -WRD_2.D = Din_c_2 -WRD_2.CLK = ~nCCAS_c -WRD_2.SP = VCC -WRD_2.LSR = GND -RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1627)+nRowColSel_N_35) -WRD_3.D = Din_c_3 -WRD_3.CLK = ~nCCAS_c -WRD_3.SP = VCC -WRD_3.LSR = GND - -comp 44: SLICE_80 (FSLICE) -ADSubmitted_N_234 = (~n2289*(n4_adj_1*(MAin_c_0*n2108))) -WRD_6.D = Din_c_6 -WRD_6.CLK = ~nCCAS_c -WRD_6.SP = VCC -WRD_6.LSR = GND -n2289 = (~MAin_c_1+n1285) -WRD_7.D = Din_c_7 -WRD_7.CLK = ~nCCAS_c -WRD_7.SP = VCC -WRD_7.LSR = GND - -comp 45: SLICE_81 (FSLICE) -n4_adj_1 = (n2114*(Din_c_2*~nFWE_c)) -RowA_8.D = MAin_c_8 -RowA_8.CLK = ~nCRAS_c -RowA_8.SP = VCC -RowA_8.LSR = ~Ready -n2114 = (Din_c_7*(~Din_c_4*(~Din_c_1*Din_c_0))) -RowA_9.D = MAin_c_9 -RowA_9.CLK = ~nCRAS_c -RowA_9.SP = VCC -RowA_9.LSR = ~Ready - -comp 46: SLICE_82 (FSLICE) -n2166 = (Bank_6*(MAin_c_2*(Bank_5*Bank_0))) -RowA_0.D = MAin_c_0 -RowA_0.CLK = ~nCRAS_c -RowA_0.SP = VCC -RowA_0.LSR = ~Ready -n26 = (~MAin_c_6+(~n2154+(~n2166+Bank_2))) -RowA_1.D = MAin_c_1 -RowA_1.CLK = ~nCRAS_c -RowA_1.SP = VCC -RowA_1.LSR = ~Ready - -comp 47: SLICE_83 (FSLICE) -n2245 = (InitReady*(Ready_N_272*(~RASr2*nRowColSel_N_32))) -CmdUFMCLK.D = Din_c_1 -CmdUFMCLK.CLK = ~PHI2_c -CmdUFMCLK.SP = PHI2_N_114_enable_7 -CmdUFMCLK.LSR = GND -Ready_N_268 = (n2245+Ready) -CmdUFMCS.D = Din_c_2 -CmdUFMCS.CLK = ~PHI2_c -CmdUFMCS.SP = PHI2_N_114_enable_7 -CmdUFMCS.LSR = GND - -comp 48: SLICE_84 (FSLICE) -nRowColSel_N_28 = ((~FWEr+CASr3)+CBR) -nRCAS_N_161.D = nRCS_N_135 -nRCAS_N_161.CLK = RCLK_c -nRCAS_N_161.SP = RCLK_c_enable_23 -nRCAS_N_161.LSR = GND -n1 = (~CASr3*(CASr2*(FWEr*~CBR))) -n703.D = nRWE_N_173 -n703.CLK = RCLK_c -n703.SP = RCLK_c_enable_23 -n703.LSR = GND - -comp 49: SLICE_85 (FSLICE) -n12 = (((~FS_4+FS_9)+FS_8)+FS_7) -PHI2r3.D = PHI2r2 -PHI2r3.CLK = RCLK_c -PHI2r3.SP = VCC -PHI2r3.LSR = GND -n2103 = (~FS_9*(FS_7*~FS_8)+FS_9*(FS_5*(~FS_7*~FS_8))) -PHI2r.D = PHI2_c -PHI2r.CLK = RCLK_c -PHI2r.SP = VCC -PHI2r.LSR = GND - -comp 50: SLICE_86 (FSLICE) -n2291 = (~InitReady*(~n2300*~FS_11)) -RowA_6.D = MAin_c_6 -RowA_6.CLK = ~nCRAS_c -RowA_6.SP = VCC -RowA_6.LSR = ~Ready -LEDEN_N_88 = (~InitReady*(~FS_10*(~n2300*~FS_11))) -RowA_7.D = MAin_c_7 -RowA_7.CLK = ~nCRAS_c -RowA_7.SP = VCC -RowA_7.LSR = ~Ready - -comp 51: SLICE_87 (FSLICE) -n2122 = (~Din_c_5*(Din_c_6*~Din_c_3)) -Ready_N_272.D = n699 -Ready_N_272.CLK = RCLK_c -Ready_N_272.SP = RCLK_c_enable_23 -Ready_N_272.LSR = GND -n2108 = (Din_c_3*(Din_c_5*~Din_c_6)) -n711.D = nRCAS_N_161 -n711.CLK = RCLK_c -n711.SP = RCLK_c_enable_23 -n711.LSR = GND - -comp 52: SLICE_88 (FSLICE) -RDQMH_c = (~nRowColSel+MAin_c_9) -CmdUFMSDI.D = Din_c_0 -CmdUFMSDI.CLK = ~PHI2_c -CmdUFMSDI.SP = PHI2_N_114_enable_7 -CmdUFMSDI.LSR = GND -RA_c_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9) - -comp 53: SLICE_89 (FSLICE) -n2290 = (nFWE_c+n1285) -LEDEN.D = ~UFMSDO_c -LEDEN.CLK = RCLK_c -LEDEN.SP = RCLK_c_enable_25 -LEDEN.LSR = GND -PHI2_N_114_enable_1 = (MAin_c_1*(~n1285*~nFWE_c)) - -comp 54: SLICE_90 (FSLICE) -PHI2_N_114_enable_6 = (Din_c_4*(XOR8MEG_N_112*(~Din_c_7*~Din_c_6))) -n700.D = n701 -n700.CLK = RCLK_c -n700.SP = RCLK_c_enable_23 -n700.LSR = GND -PHI2_N_114_enable_2 = (XOR8MEG_N_112*(~Din_c_5*(~Din_c_4*~n2385))) -n699.D = n700 -n699.CLK = RCLK_c -n699.SP = RCLK_c_enable_23 -n699.LSR = GND - -comp 55: SLICE_91 (FSLICE) -n2248 = (~InitReady+(nRCAS_N_161+nRCS_N_135)) -CBR.D = ~nCCAS_c -CBR.CLK = ~nCRAS_c -CBR.SP = VCC -CBR.LSR = GND -n2292 = (~RASr2+(~InitReady+(~nRowColSel_N_35+nRCS_N_135))) -FWEr.D = ~nFWE_c -FWEr.CLK = ~nCRAS_c -FWEr.SP = VCC -FWEr.LSR = GND - -comp 56: SLICE_92 (FSLICE) -RDQML_c = (~nRowColSel+~MAin_c_9) -RowA_4.D = MAin_c_4 -RowA_4.CLK = ~nCRAS_c -RowA_4.SP = VCC -RowA_4.LSR = ~Ready -RA_c_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0) -RowA_5.D = MAin_c_5 -RowA_5.CLK = ~nCRAS_c -RowA_5.SP = VCC -RowA_5.LSR = ~Ready - -comp 57: SLICE_93 (FSLICE) -n12_adj_2 = (FS_12*(FS_13*(FS_16*FS_14))) -RASr2.D = RASr -RASr2.CLK = RCLK_c -RASr2.SP = VCC -RASr2.LSR = GND -n2293 = (~FS_11+((FS_16+n10)+FS_17)) -RASr3.D = RASr2 -RASr3.CLK = RCLK_c -RASr3.SP = VCC -RASr3.LSR = GND - -comp 58: SLICE_94 (FSLICE) -RA_c_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1) -Bank_0.D = Din_c_0 -Bank_0.CLK = PHI2_c -Bank_0.SP = VCC -Bank_0.LSR = GND -RA_c_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3) -Bank_1.D = Din_c_1 -Bank_1.CLK = PHI2_c -Bank_1.SP = VCC -Bank_1.LSR = GND - -comp 59: SLICE_95 (FSLICE) -RA_c_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8) -Bank_6.D = Din_c_6 -Bank_6.CLK = PHI2_c -Bank_6.SP = VCC -Bank_6.LSR = GND -RA_c_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2) -Bank_7.D = Din_c_7 -Bank_7.CLK = PHI2_c -Bank_7.SP = VCC -Bank_7.LSR = GND - -comp 60: SLICE_96 (FSLICE) -n2299 = (~Ready+nRowColSel_N_35) -XOR8MEG.D = Din_c_0 -XOR8MEG.CLK = ~PHI2_c -XOR8MEG.SP = PHI2_N_114_enable_2 -XOR8MEG.LSR = GND -n2297 = (~nRowColSel_N_35+nRCS_N_135) - -comp 61: SLICE_97 (FSLICE) -RA_c_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7) -Bank_4.D = Din_c_4 -Bank_4.CLK = PHI2_c -Bank_4.SP = VCC -Bank_4.LSR = GND -n2170 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7))) -Bank_5.D = Din_c_5 -Bank_5.CLK = PHI2_c -Bank_5.SP = VCC -Bank_5.LSR = GND - -comp 62: SLICE_98 (FSLICE) -RA_c_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6) -Bank_2.D = Din_c_2 -Bank_2.CLK = PHI2_c -Bank_2.SP = VCC -Bank_2.LSR = GND -RA_c_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5) -Bank_3.D = Din_c_3 -Bank_3.CLK = PHI2_c -Bank_3.SP = VCC -Bank_3.LSR = GND - -comp 63: SLICE_99 (FSLICE) -n2164 = (nRCAS_N_161+nRWE_N_173) -RBA_c_0.D = CROW_c_0 -RBA_c_0.CLK = ~nCRAS_c -RBA_c_0.SP = VCC -RBA_c_0.LSR = ~Ready -n18 = (nRowColSel_N_34*~nRowColSel_N_35) -RBA_c_1.D = CROW_c_1 -RBA_c_1.CLK = ~nCRAS_c -RBA_c_1.SP = VCC -RBA_c_1.LSR = ~Ready - -comp 64: SLICE_100 (FSLICE) -n11_adj_3 = (~CASr2+nRowColSel_N_33) -WRD_4.D = Din_c_4 -WRD_4.CLK = ~nCCAS_c -WRD_4.SP = VCC -WRD_4.LSR = GND -n2304 = (FWEr+CBR) -WRD_5.D = Din_c_5 -WRD_5.CLK = ~nCCAS_c -WRD_5.SP = VCC -WRD_5.LSR = GND diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd deleted file mode 100644 index ea7b083f50e6de0377ea862e7ae988bd2b157371..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 154201 zcmeFa37nl(kv4uq$evDs1Va**hK6)Pg7m$;CkE5$?m(N)LMLG{VjCf11R6mYbPx>U z?kFAxCgNPe0gAAghjH086j-sDBir~zk9|OTrMzwz#H{EEOfBfwC z_dEC2ty5>KQ&p$V@}4_y-eZqVsC?$~(!|olfv$CxlQ)&NEj;+c6G{^&b`X0&9@|N**4G;>)t#Cn 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16daf53..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t +++ /dev/null @@ -1,9 +0,0 @@ --w --l 5 --i 6 --n 1 --t 1 --s 1 --c 0 --e 0 --exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t.tmp0 b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t.tmp0 deleted file mode 100644 index eb789dd..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t.tmp0 +++ /dev/null @@ -1,9 +0,0 @@ --w --l 5 --i 6 --n 1 --t 1 --s 1 --c 0 --e 0 --exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t deleted file mode 100644 index e625c68..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t +++ /dev/null @@ -1,5 +0,0 @@ --rem --distrce --log "RAM2GS_LCMXO256C_impl1.log" --o "RAM2GS_LCMXO256C_impl1.csv" --pr "RAM2GS_LCMXO256C_impl1.prf" diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad deleted file mode 100644 index 0445323..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad +++ /dev/null @@ -1,271 +0,0 @@ -PAD Specification File -*************************** - -PART TYPE: LCMXO256C -Performance Grade: 3 -PACKAGE: TQFP100 -Package Status: Final Version 1.19 - -Mon Aug 16 21:32:33 2021 - -Pinout by Port Name: -+-----------+----------+--------------+------+----------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | Properties | -+-----------+----------+--------------+------+----------------------------------+ -| CROW[0] | 32/1 | LVTTL33_IN | PB2C | SLEW:FAST | -| CROW[1] | 34/1 | LVTTL33_IN | PB2D | SLEW:FAST | -| Din[0] | 21/1 | LVTTL33_IN | PL8A | SLEW:FAST | -| Din[1] | 15/1 | LVTTL33_IN | PL6A | SLEW:FAST | -| Din[2] | 14/1 | LVTTL33_IN | PL5D | SLEW:FAST | -| Din[3] | 16/1 | LVTTL33_IN | PL6B | SLEW:FAST | -| Din[4] | 18/1 | LVTTL33_IN | PL7B | SLEW:FAST | -| Din[5] | 17/1 | LVTTL33_IN | PL7A | SLEW:FAST | -| Din[6] | 20/1 | LVTTL33_IN | PL7D | SLEW:FAST | -| Din[7] | 19/1 | LVTTL33_IN | PL7C | SLEW:FAST | -| Dout[0] | 1/1 | LVTTL33_OUT | PL2A | DRIVE:4mA SLEW:SLOW | -| Dout[1] | 7/1 | LVTTL33_OUT | PL4A | DRIVE:4mA SLEW:SLOW | -| Dout[2] | 8/1 | LVTTL33_OUT | PL4B | DRIVE:4mA SLEW:SLOW | -| Dout[3] | 6/1 | LVTTL33_OUT | PL3D | DRIVE:4mA SLEW:SLOW | -| Dout[4] | 4/1 | LVTTL33_OUT | PL3B | DRIVE:4mA SLEW:SLOW | -| Dout[5] | 5/1 | LVTTL33_OUT | PL3C | DRIVE:4mA SLEW:SLOW | -| Dout[6] | 2/1 | LVTTL33_OUT | PL2B | DRIVE:4mA SLEW:SLOW | -| Dout[7] | 3/1 | LVTTL33_OUT | PL3A | DRIVE:4mA SLEW:SLOW | -| LED | 57/0 | LVTTL33_OUT | PR7B | DRIVE:16mA SLEW:SLOW | -| MAin[0] | 23/1 | LVTTL33_IN | PL9A | SLEW:FAST | -| MAin[1] | 38/1 | LVTTL33_IN | PB3C | SLEW:FAST | -| MAin[2] | 37/1 | LVTTL33_IN | PB3B | SLEW:FAST | -| MAin[3] | 47/1 | LVTTL33_IN | PB5A | SLEW:FAST | -| MAin[4] | 46/1 | LVTTL33_IN | PB4D | SLEW:FAST | -| MAin[5] | 45/1 | LVTTL33_IN | PB4C | SLEW:FAST | -| MAin[6] | 49/1 | LVTTL33_IN | PB5C | SLEW:FAST | -| MAin[7] | 44/1 | LVTTL33_IN | PB4B | SLEW:FAST | -| MAin[8] | 50/1 | LVTTL33_IN | PB5D | SLEW:FAST | -| MAin[9] | 51/0 | LVTTL33_IN | PR9B | SLEW:FAST | -| PHI2 | 39/1 | LVTTL33_IN | PB3D | SLEW:FAST | -| RA[0] | 98/0 | LVTTL33_OUT | PT2C | DRIVE:4mA SLEW:SLOW | -| RA[10] | 87/0 | LVTTL33_OUT | PT3D | DRIVE:4mA SLEW:SLOW | -| RA[11] | 79/0 | LVTTL33_OUT | PT5A | DRIVE:4mA SLEW:SLOW | -| RA[1] | 89/0 | LVTTL33_OUT | PT3C | DRIVE:4mA SLEW:SLOW | -| RA[2] | 94/0 | LVTTL33_OUT | PT3A | DRIVE:4mA SLEW:SLOW | -| RA[3] | 97/0 | LVTTL33_OUT | PT2D | DRIVE:4mA SLEW:SLOW | -| RA[4] | 99/0 | LVTTL33_OUT | PT2B | DRIVE:4mA SLEW:SLOW | -| RA[5] | 95/0 | LVTTL33_OUT | PT2F | DRIVE:4mA SLEW:SLOW | -| RA[6] | 91/0 | LVTTL33_OUT | PT3B | DRIVE:4mA SLEW:SLOW | -| RA[7] | 100/0 | LVTTL33_OUT | PT2A | DRIVE:4mA SLEW:SLOW | -| RA[8] | 96/0 | LVTTL33_OUT | PT2E | DRIVE:4mA SLEW:SLOW | -| RA[9] | 85/0 | LVTTL33_OUT | PT4B | DRIVE:4mA SLEW:SLOW | -| RBA[0] | 63/0 | LVTTL33_OUT | PR5D | DRIVE:4mA SLEW:SLOW | -| RBA[1] | 83/0 | LVTTL33_OUT | PT4C | DRIVE:4mA SLEW:SLOW | -| RCKE | 82/0 | LVTTL33_OUT | PT4D | DRIVE:4mA SLEW:SLOW | -| RCLK | 86/0 | LVTTL33_IN | PT4A | SLEW:FAST | -| RDQMH | 76/0 | LVTTL33_OUT | PR2A | DRIVE:4mA SLEW:SLOW | -| RDQML | 61/0 | LVTTL33_OUT | PR6A | DRIVE:4mA SLEW:SLOW | -| RD[0] | 64/0 | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[1] | 65/0 | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[2] | 66/0 | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[3] | 67/0 | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[4] | 68/0 | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[5] | 69/0 | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[6] | 70/0 | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| RD[7] | 71/0 | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER | -| UFMCLK | 58/0 | LVTTL33_OUT | PR7A | DRIVE:4mA SLEW:SLOW | -| UFMSDI | 56/0 | LVTTL33_OUT | PR7C | DRIVE:4mA SLEW:SLOW | -| UFMSDO | 55/0 | LVTTL33_IN | PR7D | SLEW:FAST PULL:KEEPER | -| nCCAS | 27/1 | LVTTL33_IN | PL9B | SLEW:FAST | -| nCRAS | 43/1 | LVTTL33_IN | PB4A | SLEW:FAST | -| nFWE | 22/1 | LVTTL33_IN | PL8B | SLEW:FAST | -| nRCAS | 78/0 | LVTTL33_OUT | PT5B | DRIVE:4mA SLEW:SLOW | -| nRCS | 77/0 | LVTTL33_OUT | PT5C | DRIVE:4mA SLEW:SLOW | -| nRRAS | 73/0 | LVTTL33_OUT | PR2B | DRIVE:4mA SLEW:SLOW | -| nRWE | 72/0 | LVTTL33_OUT | PR3A | DRIVE:4mA SLEW:SLOW | -| nUFMCS | 53/0 | LVTTL33_OUT | PR8B | DRIVE:4mA SLEW:SLOW | -+-----------+----------+--------------+------+----------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 3.3V | -| 1 | 3.3V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+---------------------+------------+--------------+------+---------------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | -+----------+---------------------+------------+--------------+------+---------------+ -| 1/1 | Dout[0] | LOCATED | LVTTL33_OUT | PL2A | | -| 2/1 | Dout[6] | LOCATED | LVTTL33_OUT | PL2B | | -| 3/1 | Dout[7] | LOCATED | LVTTL33_OUT | PL3A | | -| 4/1 | Dout[4] | LOCATED | LVTTL33_OUT | PL3B | | -| 5/1 | Dout[5] | LOCATED | LVTTL33_OUT | PL3C | | -| 6/1 | Dout[3] | LOCATED | LVTTL33_OUT | PL3D | | -| 7/1 | Dout[1] | LOCATED | LVTTL33_OUT | PL4A | | -| 8/1 | Dout[2] | LOCATED | LVTTL33_OUT | PL4B | | -| 9/1 | unused, PULL:UP | | | PL5A | | -| 11/1 | unused, PULL:UP | | | PL5B | | -| 13/1 | unused, PULL:UP | | | PL5C | | -| 14/1 | Din[2] | LOCATED | LVTTL33_IN | PL5D | GSR_PADN | -| 15/1 | Din[1] | LOCATED | LVTTL33_IN | PL6A | | -| 16/1 | Din[3] | LOCATED | LVTTL33_IN | PL6B | TSALLPAD | -| 17/1 | Din[5] | LOCATED | LVTTL33_IN | PL7A | | -| 18/1 | Din[4] | LOCATED | LVTTL33_IN | PL7B | | -| 19/1 | Din[7] | LOCATED | LVTTL33_IN | PL7C | | -| 20/1 | Din[6] | LOCATED | LVTTL33_IN | PL7D | | -| 21/1 | Din[0] | LOCATED | LVTTL33_IN | PL8A | | -| 22/1 | nFWE | LOCATED | LVTTL33_IN | PL8B | | -| 23/1 | MAin[0] | LOCATED | LVTTL33_IN | PL9A | | -| 27/1 | nCCAS | LOCATED | LVTTL33_IN | PL9B | | -| 29/1 | unused, PULL:UP | | | PB2A | | -| 30/1 | unused, PULL:UP | | | PB2B | | -| 32/1 | CROW[0] | LOCATED | LVTTL33_IN | PB2C | | -| 34/1 | CROW[1] | LOCATED | LVTTL33_IN | PB2D | | -| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 | -| 37/1 | MAin[2] | LOCATED | LVTTL33_IN | PB3B | | -| 38/1 | MAin[1] | LOCATED | LVTTL33_IN | PB3C | PCLKT1_0 | -| 39/1 | PHI2 | LOCATED | LVTTL33_IN | PB3D | | -| 43/1 | nCRAS | LOCATED | LVTTL33_IN | PB4A | | -| 44/1 | MAin[7] | LOCATED | LVTTL33_IN | PB4B | | -| 45/1 | MAin[5] | LOCATED | LVTTL33_IN | PB4C | | -| 46/1 | MAin[4] | LOCATED | LVTTL33_IN | PB4D | | -| 47/1 | MAin[3] | LOCATED | LVTTL33_IN | PB5A | | -| 49/1 | MAin[6] | LOCATED | LVTTL33_IN | PB5C | | -| 50/1 | MAin[8] | LOCATED | LVTTL33_IN | PB5D | | -| 51/0 | MAin[9] | LOCATED | LVTTL33_IN | PR9B | | -| 52/0 | unused, PULL:UP | | | PR9A | | -| 53/0 | nUFMCS | LOCATED | LVTTL33_OUT | PR8B | | -| 54/0 | unused, PULL:UP | | | PR8A | | -| 55/0 | UFMSDO | LOCATED | LVTTL33_IN | PR7D | | -| 56/0 | UFMSDI | LOCATED | LVTTL33_OUT | PR7C | | -| 57/0 | LED | LOCATED | LVTTL33_OUT | PR7B | | -| 58/0 | UFMCLK | LOCATED | LVTTL33_OUT | PR7A | | -| 59/0 | unused, PULL:UP | | | PR6B | | -| 61/0 | RDQML | LOCATED | LVTTL33_OUT | PR6A | | -| 63/0 | RBA[0] | LOCATED | LVTTL33_OUT | PR5D | | -| 64/0 | RD[0] | LOCATED | LVTTL33_BIDI | PR5C | | -| 65/0 | RD[1] | LOCATED | LVTTL33_BIDI | PR5B | | -| 66/0 | RD[2] | LOCATED | LVTTL33_BIDI | PR5A | | -| 67/0 | RD[3] | LOCATED | LVTTL33_BIDI | PR4B | | -| 68/0 | RD[4] | LOCATED | LVTTL33_BIDI | PR4A | | -| 69/0 | RD[5] | LOCATED | LVTTL33_BIDI | PR3D | | -| 70/0 | RD[6] | LOCATED | LVTTL33_BIDI | PR3C | | -| 71/0 | RD[7] | LOCATED | LVTTL33_BIDI | PR3B | | -| 72/0 | nRWE | LOCATED | LVTTL33_OUT | PR3A | | -| 73/0 | nRRAS | LOCATED | LVTTL33_OUT | PR2B | | -| 76/0 | RDQMH | LOCATED | LVTTL33_OUT | PR2A | | -| 77/0 | nRCS | LOCATED | LVTTL33_OUT | PT5C | | -| 78/0 | nRCAS | LOCATED | LVTTL33_OUT | PT5B | | -| 79/0 | RA[11] | LOCATED | LVTTL33_OUT | PT5A | | -| 80/0 | unused, PULL:UP | | | PT4F | | -| 81/0 | unused, PULL:UP | | | PT4E | | -| 82/0 | RCKE | LOCATED | LVTTL33_OUT | PT4D | | -| 83/0 | RBA[1] | LOCATED | LVTTL33_OUT | PT4C | | -| 85/0 | RA[9] | LOCATED | LVTTL33_OUT | PT4B | PCLKT0_1 | -| 86/0 | RCLK | LOCATED | LVTTL33_IN | PT4A | PCLKT0_0 | -| 87/0 | RA[10] | LOCATED | LVTTL33_OUT | PT3D | | -| 89/0 | RA[1] | LOCATED | LVTTL33_OUT | PT3C | | -| 91/0 | RA[6] | LOCATED | LVTTL33_OUT | PT3B | | -| 94/0 | RA[2] | LOCATED | LVTTL33_OUT | PT3A | | -| 95/0 | RA[5] | LOCATED | LVTTL33_OUT | PT2F | | -| 96/0 | RA[8] | LOCATED | LVTTL33_OUT | PT2E | | -| 97/0 | RA[3] | LOCATED | LVTTL33_OUT | PT2D | | -| 98/0 | RA[0] | LOCATED | LVTTL33_OUT | PT2C | | -| 99/0 | RA[4] | LOCATED | LVTTL33_OUT | PT2B | | -| 100/0 | RA[7] | LOCATED | LVTTL33_OUT | PT2A | | -| PB5B/0 | unused, PULL:UP | | | PB5B | | -| PT5D/0 | unused, PULL:UP | | | PT5D | | -| TCK/1 | | | | TCK | TCK | -| TDI/1 | | | | TDI | TDI | -| TDO/1 | | | | TDO | TDO | -| TMS/1 | | | | TMS | TMS | -+----------+---------------------+------------+--------------+------+---------------+ - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "CROW[0]" SITE "32"; -LOCATE COMP "CROW[1]" SITE "34"; -LOCATE COMP "Din[0]" SITE "21"; -LOCATE COMP "Din[1]" SITE "15"; -LOCATE COMP "Din[2]" SITE "14"; -LOCATE COMP "Din[3]" SITE "16"; -LOCATE COMP "Din[4]" SITE "18"; -LOCATE COMP "Din[5]" SITE "17"; -LOCATE COMP "Din[6]" SITE "20"; -LOCATE COMP "Din[7]" SITE "19"; -LOCATE COMP "Dout[0]" SITE "1"; -LOCATE COMP "Dout[1]" SITE "7"; -LOCATE COMP "Dout[2]" SITE "8"; -LOCATE COMP "Dout[3]" SITE "6"; -LOCATE COMP "Dout[4]" SITE "4"; -LOCATE COMP "Dout[5]" SITE "5"; -LOCATE COMP "Dout[6]" SITE "2"; -LOCATE COMP "Dout[7]" SITE "3"; -LOCATE COMP "LED" SITE "57"; -LOCATE COMP "MAin[0]" SITE "23"; -LOCATE COMP "MAin[1]" SITE "38"; -LOCATE COMP "MAin[2]" SITE "37"; -LOCATE COMP "MAin[3]" SITE "47"; -LOCATE COMP "MAin[4]" SITE "46"; -LOCATE COMP "MAin[5]" SITE "45"; -LOCATE COMP "MAin[6]" SITE "49"; -LOCATE COMP "MAin[7]" SITE "44"; -LOCATE COMP "MAin[8]" SITE "50"; -LOCATE COMP "MAin[9]" SITE "51"; -LOCATE COMP "PHI2" SITE "39"; -LOCATE COMP "RA[0]" SITE "98"; -LOCATE COMP "RA[10]" SITE "87"; -LOCATE COMP "RA[11]" SITE "79"; -LOCATE COMP "RA[1]" SITE "89"; -LOCATE COMP "RA[2]" SITE "94"; -LOCATE COMP "RA[3]" SITE "97"; -LOCATE COMP "RA[4]" SITE "99"; -LOCATE COMP "RA[5]" SITE "95"; -LOCATE COMP "RA[6]" SITE "91"; -LOCATE COMP "RA[7]" SITE "100"; -LOCATE COMP "RA[8]" SITE "96"; -LOCATE COMP "RA[9]" SITE "85"; -LOCATE COMP "RBA[0]" SITE "63"; -LOCATE COMP "RBA[1]" SITE "83"; -LOCATE COMP "RCKE" SITE "82"; -LOCATE COMP "RCLK" SITE "86"; -LOCATE COMP "RDQMH" SITE "76"; -LOCATE COMP "RDQML" SITE "61"; -LOCATE COMP "RD[0]" SITE "64"; -LOCATE COMP "RD[1]" SITE "65"; -LOCATE COMP "RD[2]" SITE "66"; -LOCATE COMP "RD[3]" SITE "67"; -LOCATE COMP "RD[4]" SITE "68"; -LOCATE COMP "RD[5]" SITE "69"; -LOCATE COMP "RD[6]" SITE "70"; -LOCATE COMP "RD[7]" SITE "71"; -LOCATE COMP "UFMCLK" SITE "58"; -LOCATE COMP "UFMSDI" SITE "56"; -LOCATE COMP "UFMSDO" SITE "55"; -LOCATE COMP "nCCAS" SITE "27"; -LOCATE COMP "nCRAS" SITE "43"; -LOCATE COMP "nFWE" SITE "22"; -LOCATE COMP "nRCAS" SITE "78"; -LOCATE COMP "nRCS" SITE "77"; -LOCATE COMP "nRRAS" SITE "73"; -LOCATE COMP "nRWE" SITE "72"; -LOCATE COMP "nUFMCS" SITE "53"; - - - - - -PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Mon Aug 16 21:32:33 2021 - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par deleted file mode 100644 index 6275f58..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par +++ /dev/null @@ -1,239 +0,0 @@ -PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Mon Aug 16 21:32:27 2021 - -C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t -RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir -RAM2GS_LCMXO256C_impl1.prf -gui -msgset -C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml - - -Preference file: RAM2GS_LCMXO256C_impl1.prf. - -Level/ Number Worst Timing Worst Timing Run NCD -Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ----------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 2.023 0 0.339 0 07 Completed - -* : Design saved. - -Total (real) run time for 1-seed: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" -Mon Aug 16 21:32:27 2021 - -PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. -Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf -Preference file: RAM2GS_LCMXO256C_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 - -Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO256C -Package: TQFP100 -Performance: 3 -Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.19. -Performance Hardware Data Status: Version 1.124. -License checked out. - - -Ignore Preference Error(s): True -Device utilization summary: - - PIO (prelim) 67/79 84% used - 67/78 85% bonded - SLICE 65/128 50% used - - - -Number of Signals: 252 -Number of Connections: 618 - -Pin Constraint Summary: - 67 out of 67 pins locked (100% locked). - -The following 4 signals are selected to use the primary clock routing resources: - RCLK_c (driver: RCLK, clk load #: 39) - PHI2_c (driver: PHI2, clk load #: 13) - nCCAS_c (driver: nCCAS, clk load #: 4) - nCRAS_c (driver: nCRAS, clk load #: 7) - -No signal is selected as secondary clock. - -No signal is selected as Global Set/Reset. -Starting Placer Phase 0. -........ -Finished Placer Phase 0. REAL time: 0 secs - -Starting Placer Phase 1. -............... -Placer score = 586066. -Finished Placer Phase 1. REAL time: 6 secs - -Starting Placer Phase 2. -. -Placer score = 584668 -Finished Placer Phase 2. REAL time: 6 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 1 out of 4 (25%) - General PIO: 3 out of 80 (3%) - -Global Clocks: - PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39 - PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 - PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4 - PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7 - - PRIMARY : 4 out of 4 (100%) - SECONDARY: 0 out of 4 (0%) - ---------------- End of Clock Report --------------- - - -I/O Usage Summary (final): - 67 out of 79 (84.8%) PIO sites used. - 67 out of 78 (85.9%) bonded PIO sites used. - Number of PIO comps: 67; differential: 0. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+------------+------------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | -+----------+----------------+------------+------------+------------+ -| 0 | 36 / 41 ( 87%) | 3.3V | - | - | -| 1 | 31 / 37 ( 83%) | 3.3V | - | - | -+----------+----------------+------------+------------+------------+ - -Total placer CPU time: 6 secs - -Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. - -0 connections routed; 618 unrouted. -Starting router resource preassignment -WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. -WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. -WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. - -Completed router resource preassignment. Real time: 6 secs - -Start NBR router at 21:32:33 08/16/21 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at 21:32:33 08/16/21 - -Start NBR section for initial routing at 21:32:33 08/16/21 -Level 1, iteration 1 -0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs -Level 2, iteration 1 -0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.084ns/0.000ns; real time: 6 secs -Level 3, iteration 1 -0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.038ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at 21:32:33 08/16/21 -Level 1, iteration 1 -0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs -Level 4, iteration 1 -8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs -Level 4, iteration 2 -4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs -Level 4, iteration 3 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs - -Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21 - -Start NBR section for re-routing at 21:32:33 08/16/21 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack: 2.023ns/0.000ns; real time: 6 secs - -Start NBR section for post-routing at 21:32:33 08/16/21 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 0 (0.00%) - Estimated worst slack : 2.023ns - Timing score : 0 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - -Total CPU time 6 secs -Total REAL time: 7 secs -Completely routed. -End of route. 618 routed (100.00%); 0 unrouted. - -Hold time timing score: 0, hold timing errors: 0 - -Timing score: 0 - -Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. - - -All signals are completely routed. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = 2.023 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Worst slack> = 0.339 -PAR_SUMMARY::Timing score> = 0.000 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 6 secs -Total REAL time to completion: 7 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf deleted file mode 100644 index 4d03744..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf +++ /dev/null @@ -1,165 +0,0 @@ -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:32:26 2021 - -SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; -LOCATE COMP "RD[7]" SITE "71" ; -LOCATE COMP "RD[6]" SITE "70" ; -LOCATE COMP "RD[5]" SITE "69" ; -LOCATE COMP "RD[4]" SITE "68" ; -LOCATE COMP "RD[3]" SITE "67" ; -LOCATE COMP "RD[2]" SITE "66" ; -LOCATE COMP "RD[1]" SITE "65" ; -LOCATE COMP "RD[0]" SITE "64" ; -LOCATE COMP "Dout[7]" SITE "3" ; -LOCATE COMP "Dout[6]" SITE "2" ; -LOCATE COMP "Dout[5]" SITE "5" ; -LOCATE COMP "Dout[4]" SITE "4" ; -LOCATE COMP "Dout[3]" SITE "6" ; -LOCATE COMP "Dout[2]" SITE "8" ; -LOCATE COMP "Dout[1]" SITE "7" ; -LOCATE COMP "Dout[0]" SITE "1" ; -LOCATE COMP "LED" SITE "57" ; -LOCATE COMP "RBA[1]" SITE "83" ; -LOCATE COMP "RBA[0]" SITE "63" ; -LOCATE COMP "RA[11]" SITE "79" ; -LOCATE COMP "RA[10]" SITE "87" ; -LOCATE COMP "RA[9]" SITE "85" ; -LOCATE COMP "RA[8]" SITE "96" ; -LOCATE COMP "RA[7]" SITE "100" ; -LOCATE COMP "RA[6]" SITE "91" ; -LOCATE COMP "RA[5]" SITE "95" ; -LOCATE COMP "RA[4]" SITE "99" ; -LOCATE COMP "RA[3]" SITE "97" ; -LOCATE COMP "RA[2]" SITE "94" ; -LOCATE COMP "RA[1]" SITE "89" ; -LOCATE COMP "RA[0]" SITE "98" ; -LOCATE COMP "nRCS" SITE "77" ; -LOCATE COMP "RCKE" SITE "82" ; -LOCATE COMP "nRWE" SITE "72" ; -LOCATE COMP "nRRAS" SITE "73" ; -LOCATE COMP "nRCAS" SITE "78" ; -LOCATE COMP "RDQMH" SITE "76" ; -LOCATE COMP "RDQML" SITE "61" ; -LOCATE COMP "nUFMCS" SITE "53" ; -LOCATE COMP "UFMCLK" SITE "58" ; -LOCATE COMP "UFMSDI" SITE "56" ; -LOCATE COMP "PHI2" SITE "39" ; -LOCATE COMP "MAin[9]" SITE "51" ; -LOCATE COMP "MAin[8]" SITE "50" ; -LOCATE COMP "MAin[7]" SITE "44" ; -LOCATE COMP "MAin[6]" SITE "49" ; -LOCATE COMP "MAin[5]" SITE "45" ; -LOCATE COMP "MAin[4]" SITE "46" ; -LOCATE COMP "MAin[3]" SITE "47" ; -LOCATE COMP "MAin[2]" SITE "37" ; -LOCATE COMP "MAin[1]" SITE "38" ; -LOCATE COMP "MAin[0]" SITE "23" ; -LOCATE COMP "CROW[1]" SITE "34" ; -LOCATE COMP "CROW[0]" SITE "32" ; -LOCATE COMP "Din[7]" SITE "19" ; -LOCATE COMP "Din[6]" SITE "20" ; -LOCATE COMP "Din[5]" SITE "17" ; -LOCATE COMP "Din[4]" SITE "18" ; -LOCATE COMP "Din[3]" SITE "16" ; -LOCATE COMP "Din[2]" SITE "14" ; -LOCATE COMP "Din[1]" SITE "15" ; -LOCATE COMP "Din[0]" SITE "21" ; -LOCATE COMP "nCCAS" SITE "27" ; -LOCATE COMP "nCRAS" SITE "43" ; -LOCATE COMP "nFWE" SITE "22" ; -LOCATE COMP "RCLK" SITE "86" ; -LOCATE COMP "UFMSDO" SITE "55" ; -PERIOD NET "PHI2_c" 350.000000 ns ; -USE PRIMARY NET "RCLK_c" ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -USE PRIMARY NET "PHI2_c" ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -USE PRIMARY NET "nCCAS_c" ; -PERIOD NET "RCLK_c" 16.000000 ns ; -USE PRIMARY NET "nCRAS_c" ; -SCHEMATIC END ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; -OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; -OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; -OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; -OUTPUT PORT "nRWE" LOAD 10.000000 pF ; -OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; -OUTPUT PORT "nRCS" LOAD 10.000000 pF ; -OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; -OUTPUT PORT "RDQML" LOAD 10.000000 pF ; -OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; -OUTPUT PORT "RCKE" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "LED" LOAD 25.000000 pF ; -OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; -VOLTAGE 3.300 V; -VCCIO_DERATE BANK 0 PERCENT -5; -VCCIO_DERATE PERCENT -5; -VCCIO_DERATE BANK 1 PERCENT -5; -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; -COMMERCIAL ; diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt deleted file mode 100644 index 916dbc3..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt +++ /dev/null @@ -1,10 +0,0 @@ --v -10 - - - - --gt --sethld --sp 3 --sphld m diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b deleted file mode 100644 index aa05f83..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b +++ /dev/null @@ -1,2 +0,0 @@ - --g ES:No diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 deleted file mode 100644 index f728d52..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 +++ /dev/null @@ -1,2507 +0,0 @@ - -Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO256C -Package: TQFP100 -Performance: 3 -Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.19. -Performance Hardware Data Status: Version 1.124. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 -Mon Aug 16 21:32:27 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf -Design file: ram2gs_lcmxo256c_impl1_map.ncd -Preference file: ram2gs_lcmxo256c_impl1.prf -Device,speed: LCMXO256C,3 -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - - - -================================================================================ -Preference: PERIOD NET "PHI2_c" 350.000000 ns ; - 113 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i7 (from PHI2_c +) - Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) - - Delay: 12.873ns (21.6% logic, 78.4% route), 7 logic levels. - - Constraint Details: - - 12.873ns physical path delay SLICE_95 to SLICE_19 meets - 175.000ns delay constraint less - 0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns - - Physical Path Details: - - Data path SLICE_95 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_95.CLK to SLICE_95.Q1 SLICE_95 (from PHI2_c) -ROUTE 1 e 1.441 SLICE_95.Q1 to SLICE_67.A1 Bank_7 -CTOF_DEL --- 0.371 SLICE_67.A1 to SLICE_67.F1 SLICE_67 -ROUTE 1 e 1.441 SLICE_67.F1 to SLICE_82.C1 n2154 -CTOF_DEL --- 0.371 SLICE_82.C1 to SLICE_82.F1 SLICE_82 -ROUTE 1 e 1.441 SLICE_82.F1 to SLICE_76.B1 n26 -CTOF_DEL --- 0.371 SLICE_76.B1 to SLICE_76.F1 SLICE_76 -ROUTE 4 e 1.441 SLICE_76.F1 to SLICE_89.B0 n1285 -CTOF_DEL --- 0.371 SLICE_89.B0 to SLICE_89.F0 SLICE_89 -ROUTE 3 e 1.441 SLICE_89.F0 to SLICE_18.D1 n2290 -CTOF_DEL --- 0.371 SLICE_18.D1 to SLICE_18.F1 SLICE_18 -ROUTE 3 e 1.441 SLICE_18.F1 to SLICE_90.C0 XOR8MEG_N_112 -CTOF_DEL --- 0.371 SLICE_90.C0 to SLICE_90.F0 SLICE_90 -ROUTE 2 e 1.441 SLICE_90.F0 to SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c) - -------- - 12.873 (21.6% logic, 78.4% route), 7 logic levels. - -Report: 26.276ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 348.000ns - The internal maximum frequency of the following component is 500.000 MHz - - Logical Details: Cell type Pin name Component name - - Destination: FSLICE CLK SLICE_76 - - Delay: 2.000ns -- based on Minimum Pulse Width - -Report: 2.000ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 348.000ns - The internal maximum frequency of the following component is 500.000 MHz - - Logical Details: Cell type Pin name Component name - - Destination: FSLICE CLK SLICE_77 - - Delay: 2.000ns -- based on Minimum Pulse Width - -Report: 2.000ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "RCLK_c" 16.000000 ns ; - 395 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 5.575ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_577__i14 (from RCLK_c +) - Destination: FF Data in n8MEGEN_391 (to RCLK_c +) - - Delay: 10.181ns (23.7% logic, 76.3% route), 6 logic levels. - - Constraint Details: - - 10.181ns physical path delay SLICE_7 to SLICE_56 meets - 16.000ns delay constraint less - 0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns - - Physical Path Details: - - Data path SLICE_7 to SLICE_56: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_7.CLK to SLICE_7.Q0 SLICE_7 (from RCLK_c) -ROUTE 3 e 1.441 SLICE_7.Q0 to SLICE_78.A0 FS_14 -CTOF_DEL --- 0.371 SLICE_78.A0 to SLICE_78.F0 SLICE_78 -ROUTE 3 e 1.441 SLICE_78.F0 to SLICE_73.B1 n10 -CTOF_DEL --- 0.371 SLICE_73.B1 to SLICE_73.F1 SLICE_73 -ROUTE 4 e 0.561 SLICE_73.F1 to SLICE_73.B0 n2300 -CTOF_DEL --- 0.371 SLICE_73.B0 to SLICE_73.F0 SLICE_73 -ROUTE 1 e 1.441 SLICE_73.F0 to SLICE_75.C0 n11 -CTOF_DEL --- 0.371 SLICE_75.C0 to SLICE_75.F0 SLICE_75 -ROUTE 2 e 1.441 SLICE_75.F0 to SLICE_33.D1 n2119 -CTOF_DEL --- 0.371 SLICE_33.D1 to SLICE_33.F1 SLICE_33 -ROUTE 1 e 1.441 SLICE_33.F1 to SLICE_56.CE RCLK_c_enable_7 (to RCLK_c) - -------- - 10.181 (23.7% logic, 76.3% route), 6 logic levels. - -Report: 10.425ns is the minimum period for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.359ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA10_373 (from RCLK_c +) - Destination: Port Pad RA[10] - - Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_55 and - 5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets - 12.500ns offset RCLK to RA[10] by 4.359ns - - Physical Path Details: - - Clock path RCLK to SLICE_55: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_55.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_55 to RA[10]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_55.CLK to SLICE_55.Q0 SLICE_55 (from RCLK_c) -ROUTE 1 e 1.441 SLICE_55.Q0 to 87.PADDO n980 -DOPAD_DEL --- 3.636 87.PADDO to 87.PAD RA[10] - -------- - 5.637 (74.4% logic, 25.6% route), 2 logic levels. - -Report: 8.141ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.547ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[9] - - Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets - 12.500ns offset RCLK to RA[9] by 2.547ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RA[9]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_88.C1 nRowColSel -CTOF_DEL --- 0.371 SLICE_88.C1 to SLICE_88.F1 SLICE_88 -ROUTE 1 e 1.441 SLICE_88.F1 to 85.PADDO RA_c_9 -DOPAD_DEL --- 3.636 85.PADDO to 85.PAD RA[9] - -------- - 7.449 (61.3% logic, 38.7% route), 3 logic levels. - -Report: 9.953ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.547ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[8] - - Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets - 12.500ns offset RCLK to RA[8] by 2.547ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RA[8]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_95.C0 nRowColSel -CTOF_DEL --- 0.371 SLICE_95.C0 to SLICE_95.F0 SLICE_95 -ROUTE 1 e 1.441 SLICE_95.F0 to 96.PADDO RA_c_8 -DOPAD_DEL --- 3.636 96.PADDO to 96.PAD RA[8] - -------- - 7.449 (61.3% logic, 38.7% route), 3 logic levels. - -Report: 9.953ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.547ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[7] - - Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets - 12.500ns offset RCLK to RA[7] by 2.547ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RA[7]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_97.C0 nRowColSel -CTOF_DEL --- 0.371 SLICE_97.C0 to SLICE_97.F0 SLICE_97 -ROUTE 1 e 1.441 SLICE_97.F0 to 100.PADDO RA_c_7 -DOPAD_DEL --- 3.636 100.PADDO to 100.PAD RA[7] - -------- - 7.449 (61.3% logic, 38.7% route), 3 logic levels. - -Report: 9.953ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.547ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[6] - - Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets - 12.500ns offset RCLK to RA[6] by 2.547ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RA[6]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_98.C0 nRowColSel -CTOF_DEL --- 0.371 SLICE_98.C0 to SLICE_98.F0 SLICE_98 -ROUTE 1 e 1.441 SLICE_98.F0 to 91.PADDO RA_c_6 -DOPAD_DEL --- 3.636 91.PADDO to 91.PAD RA[6] - -------- - 7.449 (61.3% logic, 38.7% route), 3 logic levels. - -Report: 9.953ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.547ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[5] - - Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets - 12.500ns offset RCLK to RA[5] by 2.547ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RA[5]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_98.C1 nRowColSel -CTOF_DEL --- 0.371 SLICE_98.C1 to SLICE_98.F1 SLICE_98 -ROUTE 1 e 1.441 SLICE_98.F1 to 95.PADDO RA_c_5 -DOPAD_DEL --- 3.636 95.PADDO to 95.PAD RA[5] - -------- - 7.449 (61.3% logic, 38.7% route), 3 logic levels. - -Report: 9.953ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.427ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[4] - - Data Path Delay: 6.569ns (69.5% logic, 30.5% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets - 12.500ns offset RCLK to RA[4] by 3.427ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RA[4]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.561 SLICE_64.Q0 to SLICE_64.C1 nRowColSel -CTOF_DEL --- 0.371 SLICE_64.C1 to SLICE_64.F1 SLICE_64 -ROUTE 1 e 1.441 SLICE_64.F1 to 99.PADDO RA_c_4 -DOPAD_DEL --- 3.636 99.PADDO to 99.PAD RA[4] - -------- - 6.569 (69.5% logic, 30.5% route), 3 logic levels. - -Report: 9.073ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.547ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[3] - - Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets - 12.500ns offset RCLK to RA[3] by 2.547ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RA[3]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_94.C1 nRowColSel -CTOF_DEL --- 0.371 SLICE_94.C1 to SLICE_94.F1 SLICE_94 -ROUTE 1 e 1.441 SLICE_94.F1 to 97.PADDO RA_c_3 -DOPAD_DEL --- 3.636 97.PADDO to 97.PAD RA[3] - -------- - 7.449 (61.3% logic, 38.7% route), 3 logic levels. - -Report: 9.953ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.547ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[2] - - Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets - 12.500ns offset RCLK to RA[2] by 2.547ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RA[2]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_95.C1 nRowColSel -CTOF_DEL --- 0.371 SLICE_95.C1 to SLICE_95.F1 SLICE_95 -ROUTE 1 e 1.441 SLICE_95.F1 to 94.PADDO RA_c_2 -DOPAD_DEL --- 3.636 94.PADDO to 94.PAD RA[2] - -------- - 7.449 (61.3% logic, 38.7% route), 3 logic levels. - -Report: 9.953ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.547ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[1] - - Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets - 12.500ns offset RCLK to RA[1] by 2.547ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RA[1]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_94.C0 nRowColSel -CTOF_DEL --- 0.371 SLICE_94.C0 to SLICE_94.F0 SLICE_94 -ROUTE 1 e 1.441 SLICE_94.F0 to 89.PADDO RA_c_1 -DOPAD_DEL --- 3.636 89.PADDO to 89.PAD RA[1] - -------- - 7.449 (61.3% logic, 38.7% route), 3 logic levels. - -Report: 9.953ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.547ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[0] - - Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets - 12.500ns offset RCLK to RA[0] by 2.547ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RA[0]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_92.C1 nRowColSel -CTOF_DEL --- 0.371 SLICE_92.C1 to SLICE_92.F1 SLICE_92 -ROUTE 1 e 1.441 SLICE_92.F1 to 98.PADDO RA_c_0 -DOPAD_DEL --- 3.636 98.PADDO to 98.PAD RA[0] - -------- - 7.449 (61.3% logic, 38.7% route), 3 logic levels. - -Report: 9.953ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.359ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCS_369 (from RCLK_c +) - Destination: Port Pad nRCS - - Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_60 and - 5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets - 12.500ns offset RCLK to nRCS by 4.359ns - - Physical Path Details: - - Clock path RCLK to SLICE_60: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_60.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_60 to nRCS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c) -ROUTE 1 e 1.441 SLICE_60.Q0 to 77.PADDO nRCS_c -DOPAD_DEL --- 3.636 77.PADDO to 77.PAD nRCS - -------- - 5.637 (74.4% logic, 25.6% route), 2 logic levels. - -Report: 8.141ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.359ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RCKE_368 (from RCLK_c +) - Destination: Port Pad RCKE - - Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_34 and - 5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets - 12.500ns offset RCLK to RCKE by 4.359ns - - Physical Path Details: - - Clock path RCLK to SLICE_34: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_34.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_34 to RCKE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from RCLK_c) -ROUTE 4 e 1.441 SLICE_34.Q0 to 82.PADDO RCKE_c -DOPAD_DEL --- 3.636 82.PADDO to 82.PAD RCKE - -------- - 5.637 (74.4% logic, 25.6% route), 2 logic levels. - -Report: 8.141ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.359ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRWE_372 (from RCLK_c +) - Destination: Port Pad nRWE - - Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_63 and - 5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets - 12.500ns offset RCLK to nRWE by 4.359ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_63.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_63 to nRWE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 1 e 1.441 SLICE_63.Q0 to 72.PADDO nRWE_c -DOPAD_DEL --- 3.636 72.PADDO to 72.PAD nRWE - -------- - 5.637 (74.4% logic, 25.6% route), 2 logic levels. - -Report: 8.141ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.359ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRRAS_370 (from RCLK_c +) - Destination: Port Pad nRRAS - - Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_61 and - 5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets - 12.500ns offset RCLK to nRRAS by 4.359ns - - Physical Path Details: - - Clock path RCLK to SLICE_61: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_61.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_61 to nRRAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from RCLK_c) -ROUTE 2 e 1.441 SLICE_61.Q0 to 73.PADDO nRRAS_c -DOPAD_DEL --- 3.636 73.PADDO to 73.PAD nRRAS - -------- - 5.637 (74.4% logic, 25.6% route), 2 logic levels. - -Report: 8.141ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 4.359ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCAS_371 (from RCLK_c +) - Destination: Port Pad nRCAS - - Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_58 and - 5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets - 12.500ns offset RCLK to nRCAS by 4.359ns - - Physical Path Details: - - Clock path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_58.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_58 to nRCAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_58.CLK to SLICE_58.Q0 SLICE_58 (from RCLK_c) -ROUTE 1 e 1.441 SLICE_58.Q0 to 78.PADDO nRCAS_c -DOPAD_DEL --- 3.636 78.PADDO to 78.PAD nRCAS - -------- - 5.637 (74.4% logic, 25.6% route), 2 logic levels. - -Report: 8.141ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.547ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RDQMH - - Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets - 12.500ns offset RCLK to RDQMH by 2.547ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RDQMH: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_88.B0 nRowColSel -CTOF_DEL --- 0.371 SLICE_88.B0 to SLICE_88.F0 SLICE_88 -ROUTE 1 e 1.441 SLICE_88.F0 to 76.PADDO RDQMH_c -DOPAD_DEL --- 3.636 76.PADDO to 76.PAD RDQMH - -------- - 7.449 (61.3% logic, 38.7% route), 3 logic levels. - -Report: 9.953ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.547ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RDQML - - Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels. - - Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels. - - Constraint Details: - 2.504ns delay RCLK to SLICE_64 and - 7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets - 12.500ns offset RCLK to RDQML by 2.547ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 2.504 (42.5% logic, 57.5% route), 1 logic levels. - - Data path SLICE_64 to RDQML: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_92.B0 nRowColSel -CTOF_DEL --- 0.371 SLICE_92.B0 to SLICE_92.F0 SLICE_92 -ROUTE 1 e 1.441 SLICE_92.F0 to 61.PADDO RDQML_c -DOPAD_DEL --- 3.636 61.PADDO to 61.PAD RDQML - -------- - 7.449 (61.3% logic, 38.7% route), 3 logic levels. - -Report: 9.953ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 26.276 ns| 7 - | | | -PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 - | | | -PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 - | | | -PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 10.425 ns| 6 - | | | -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 - | | | -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.073 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 - | | | -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 - | | | -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2 - | | | -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 - | | | -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3 - | | | -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 4 clocks: - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; - - Data transfers from: - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Setup): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 -Mon Aug 16 21:32:27 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf -Design file: ram2gs_lcmxo256c_impl1_map.ncd -Preference file: ram2gs_lcmxo256c_impl1.prf -Device,speed: LCMXO256C,M -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - - - -================================================================================ -Preference: PERIOD NET "PHI2_c" 350.000000 ns ; - 113 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.485ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ADSubmitted_380 (from PHI2_c -) - Destination: FF Data in ADSubmitted_380 (to PHI2_c -) - - Delay: 0.462ns (56.7% logic, 43.3% route), 2 logic levels. - - Constraint Details: - - 0.462ns physical path delay SLICE_9 to SLICE_9 meets - -0.023ns DIN_HLD and - 0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns - - Physical Path Details: - - Data path SLICE_9 to SLICE_9: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.170 SLICE_9.CLK to SLICE_9.Q0 SLICE_9 (from PHI2_c) -ROUTE 2 e 0.199 SLICE_9.Q0 to SLICE_9.C0 ADSubmitted -CTOF_DEL --- 0.092 SLICE_9.C0 to SLICE_9.F0 SLICE_9 -ROUTE 1 e 0.001 SLICE_9.F0 to SLICE_9.DI0 n1361 (to PHI2_c) - -------- - 0.462 (56.7% logic, 43.3% route), 2 logic levels. - - -================================================================================ -Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: PERIOD NET "RCLK_c" 16.000000 ns ; - 395 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.377ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i11 (from RCLK_c +) - Destination: FF Data in IS_FSM__i12 (to RCLK_c +) - - Delay: 0.356ns (44.1% logic, 55.9% route), 1 logic levels. - - Constraint Details: - - 0.356ns physical path delay SLICE_72 to SLICE_72 meets - -0.021ns M_HLD and - 0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns - - Physical Path Details: - - Data path SLICE_72 to SLICE_72: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_72.CLK to SLICE_72.Q0 SLICE_72 (from RCLK_c) -ROUTE 1 e 0.199 SLICE_72.Q0 to SLICE_72.M1 n702 (to RCLK_c) - -------- - 0.356 (44.1% logic, 55.9% route), 1 logic levels. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.559ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA10_373 (from RCLK_c +) - Destination: Port Pad RA[10] - - Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_55 and - 1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets - 0.000ns hold offset RCLK to RA[10] by 2.559ns - - Physical Path Details: - - Clock path RCLK to SLICE_55: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_55.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_55 to RA[10]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_55.CLK to SLICE_55.Q0 SLICE_55 (from RCLK_c) -ROUTE 1 e 0.515 SLICE_55.Q0 to 87.PADDO n980 -DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10] - -------- - 1.780 (71.1% logic, 28.9% route), 2 logic levels. - -Report: 2.559ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[9] - - Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets - 0.000ns hold offset RCLK to RA[9] by 3.166ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RA[9]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_88.C1 nRowColSel -CTOF_DEL --- 0.092 SLICE_88.C1 to SLICE_88.F1 SLICE_88 -ROUTE 1 e 0.515 SLICE_88.F1 to 85.PADDO RA_c_9 -DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9] - -------- - 2.387 (56.8% logic, 43.2% route), 3 logic levels. - -Report: 3.166ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[8] - - Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets - 0.000ns hold offset RCLK to RA[8] by 3.166ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RA[8]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_95.C0 nRowColSel -CTOF_DEL --- 0.092 SLICE_95.C0 to SLICE_95.F0 SLICE_95 -ROUTE 1 e 0.515 SLICE_95.F0 to 96.PADDO RA_c_8 -DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8] - -------- - 2.387 (56.8% logic, 43.2% route), 3 logic levels. - -Report: 3.166ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[7] - - Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets - 0.000ns hold offset RCLK to RA[7] by 3.166ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RA[7]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_97.C0 nRowColSel -CTOF_DEL --- 0.092 SLICE_97.C0 to SLICE_97.F0 SLICE_97 -ROUTE 1 e 0.515 SLICE_97.F0 to 100.PADDO RA_c_7 -DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7] - -------- - 2.387 (56.8% logic, 43.2% route), 3 logic levels. - -Report: 3.166ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[6] - - Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets - 0.000ns hold offset RCLK to RA[6] by 3.166ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RA[6]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_98.C0 nRowColSel -CTOF_DEL --- 0.092 SLICE_98.C0 to SLICE_98.F0 SLICE_98 -ROUTE 1 e 0.515 SLICE_98.F0 to 91.PADDO RA_c_6 -DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6] - -------- - 2.387 (56.8% logic, 43.2% route), 3 logic levels. - -Report: 3.166ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[5] - - Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets - 0.000ns hold offset RCLK to RA[5] by 3.166ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RA[5]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_98.C1 nRowColSel -CTOF_DEL --- 0.092 SLICE_98.C1 to SLICE_98.F1 SLICE_98 -ROUTE 1 e 0.515 SLICE_98.F1 to 95.PADDO RA_c_5 -DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5] - -------- - 2.387 (56.8% logic, 43.2% route), 3 logic levels. - -Report: 3.166ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.850ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[4] - - Data Path Delay: 2.071ns (65.5% logic, 34.5% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets - 0.000ns hold offset RCLK to RA[4] by 2.850ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RA[4]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.199 SLICE_64.Q0 to SLICE_64.C1 nRowColSel -CTOF_DEL --- 0.092 SLICE_64.C1 to SLICE_64.F1 SLICE_64 -ROUTE 1 e 0.515 SLICE_64.F1 to 99.PADDO RA_c_4 -DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4] - -------- - 2.071 (65.5% logic, 34.5% route), 3 logic levels. - -Report: 2.850ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[3] - - Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets - 0.000ns hold offset RCLK to RA[3] by 3.166ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RA[3]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_94.C1 nRowColSel -CTOF_DEL --- 0.092 SLICE_94.C1 to SLICE_94.F1 SLICE_94 -ROUTE 1 e 0.515 SLICE_94.F1 to 97.PADDO RA_c_3 -DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3] - -------- - 2.387 (56.8% logic, 43.2% route), 3 logic levels. - -Report: 3.166ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[2] - - Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets - 0.000ns hold offset RCLK to RA[2] by 3.166ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RA[2]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_95.C1 nRowColSel -CTOF_DEL --- 0.092 SLICE_95.C1 to SLICE_95.F1 SLICE_95 -ROUTE 1 e 0.515 SLICE_95.F1 to 94.PADDO RA_c_2 -DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2] - -------- - 2.387 (56.8% logic, 43.2% route), 3 logic levels. - -Report: 3.166ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[1] - - Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets - 0.000ns hold offset RCLK to RA[1] by 3.166ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RA[1]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_94.C0 nRowColSel -CTOF_DEL --- 0.092 SLICE_94.C0 to SLICE_94.F0 SLICE_94 -ROUTE 1 e 0.515 SLICE_94.F0 to 89.PADDO RA_c_1 -DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1] - -------- - 2.387 (56.8% logic, 43.2% route), 3 logic levels. - -Report: 3.166ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[0] - - Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets - 0.000ns hold offset RCLK to RA[0] by 3.166ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RA[0]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_92.C1 nRowColSel -CTOF_DEL --- 0.092 SLICE_92.C1 to SLICE_92.F1 SLICE_92 -ROUTE 1 e 0.515 SLICE_92.F1 to 98.PADDO RA_c_0 -DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0] - -------- - 2.387 (56.8% logic, 43.2% route), 3 logic levels. - -Report: 3.166ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.559ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCS_369 (from RCLK_c +) - Destination: Port Pad nRCS - - Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_60 and - 1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets - 0.000ns hold offset RCLK to nRCS by 2.559ns - - Physical Path Details: - - Clock path RCLK to SLICE_60: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_60.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_60 to nRCS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c) -ROUTE 1 e 0.515 SLICE_60.Q0 to 77.PADDO nRCS_c -DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS - -------- - 1.780 (71.1% logic, 28.9% route), 2 logic levels. - -Report: 2.559ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.559ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RCKE_368 (from RCLK_c +) - Destination: Port Pad RCKE - - Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_34 and - 1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets - 0.000ns hold offset RCLK to RCKE by 2.559ns - - Physical Path Details: - - Clock path RCLK to SLICE_34: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_34.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_34 to RCKE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from RCLK_c) -ROUTE 4 e 0.515 SLICE_34.Q0 to 82.PADDO RCKE_c -DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE - -------- - 1.780 (71.1% logic, 28.9% route), 2 logic levels. - -Report: 2.559ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.559ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRWE_372 (from RCLK_c +) - Destination: Port Pad nRWE - - Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_63 and - 1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets - 0.000ns hold offset RCLK to nRWE by 2.559ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_63.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_63 to nRWE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c) -ROUTE 1 e 0.515 SLICE_63.Q0 to 72.PADDO nRWE_c -DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE - -------- - 1.780 (71.1% logic, 28.9% route), 2 logic levels. - -Report: 2.559ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.559ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRRAS_370 (from RCLK_c +) - Destination: Port Pad nRRAS - - Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_61 and - 1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets - 0.000ns hold offset RCLK to nRRAS by 2.559ns - - Physical Path Details: - - Clock path RCLK to SLICE_61: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_61.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_61 to nRRAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from RCLK_c) -ROUTE 2 e 0.515 SLICE_61.Q0 to 73.PADDO nRRAS_c -DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS - -------- - 1.780 (71.1% logic, 28.9% route), 2 logic levels. - -Report: 2.559ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.559ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCAS_371 (from RCLK_c +) - Destination: Port Pad nRCAS - - Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_58 and - 1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets - 0.000ns hold offset RCLK to nRCAS by 2.559ns - - Physical Path Details: - - Clock path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_58.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_58 to nRCAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_58.CLK to SLICE_58.Q0 SLICE_58 (from RCLK_c) -ROUTE 1 e 0.515 SLICE_58.Q0 to 78.PADDO nRCAS_c -DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS - -------- - 1.780 (71.1% logic, 28.9% route), 2 logic levels. - -Report: 2.559ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RDQMH - - Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets - 0.000ns hold offset RCLK to RDQMH by 3.166ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RDQMH: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_88.B0 nRowColSel -CTOF_DEL --- 0.092 SLICE_88.B0 to SLICE_88.F0 SLICE_88 -ROUTE 1 e 0.515 SLICE_88.F0 to 76.PADDO RDQMH_c -DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH - -------- - 2.387 (56.8% logic, 43.2% route), 3 logic levels. - -Report: 3.166ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.166ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RDQML - - Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels. - - Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels. - - Constraint Details: - 0.779ns delay RCLK to SLICE_64 and - 2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets - 0.000ns hold offset RCLK to RDQML by 3.166ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c - -------- - 0.779 (33.9% logic, 66.1% route), 1 logic levels. - - Data path SLICE_64 to RDQML: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_92.B0 nRowColSel -CTOF_DEL --- 0.092 SLICE_92.B0 to SLICE_92.F0 SLICE_92 -ROUTE 1 e 0.515 SLICE_92.F0 to 61.PADDO RDQML_c -DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML - -------- - 2.387 (56.8% logic, 43.2% route), 3 logic levels. - -Report: 3.166ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2 - | | | -PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0 - | | | -PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0 - | | | -PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1 - | | | -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 - | | | -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.850 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 - | | | -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 - | | | -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2 - | | | -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 - | | | -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3 - | | | -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 4 clocks: - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; - - Data transfers from: - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 0 (setup), 0 (hold) -Score: 0 (setup), 0 (hold) -Cumulative negative slack: 0 (0+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr deleted file mode 100644 index b0d4521..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr +++ /dev/null @@ -1,4355 +0,0 @@ - -Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd. -Design name: RAM2GS -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO256C -Package: TQFP100 -Performance: 3 -Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.19. -Performance Hardware Data Status: Version 1.124. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 -Mon Aug 16 21:32:34 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -Design file: ram2gs_lcmxo256c_impl1.ncd -Preference file: ram2gs_lcmxo256c_impl1.prf -Device,speed: LCMXO256C,3 -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - - - -================================================================================ -Preference: PERIOD NET "PHI2_c" 350.000000 ns ; - 113 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 161.925ns (weighted slack = 323.850ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i0 (from PHI2_c +) - Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) - FF CmdUFMCLK_386 - - Delay: 12.810ns (21.7% logic, 78.3% route), 7 logic levels. - - Constraint Details: - - 12.810ns physical path delay SLICE_94 to SLICE_83 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 174.735ns) by 161.925ns - - Physical Path Details: - - Data path SLICE_94 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) -ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 -CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 -ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 -CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 -ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 -CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 -ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 -CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 -ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 -CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 -ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 -ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) - -------- - 12.810 (21.7% logic, 78.3% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_94: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.080ns (weighted slack = 324.160ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) - FF CmdUFMCLK_386 - - Delay: 12.655ns (22.0% logic, 78.0% route), 7 logic levels. - - Constraint Details: - - 12.655ns physical path delay SLICE_95 to SLICE_83 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 174.735ns) by 162.080ns - - Physical Path Details: - - Data path SLICE_95 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c) -ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6 -CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82 -ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 -CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 -ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 -CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 -ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 -CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 -ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 -CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 -ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 -ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) - -------- - 12.655 (22.0% logic, 78.0% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_95: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.409ns (weighted slack = 324.818ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i0 (from PHI2_c +) - Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) - - Delay: 12.326ns (22.6% logic, 77.4% route), 7 logic levels. - - Constraint Details: - - 12.326ns physical path delay SLICE_94 to SLICE_19 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 174.735ns) by 162.409ns - - Physical Path Details: - - Data path SLICE_94 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) -ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 -CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 -ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 -CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 -ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 -CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 -ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 -CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 -ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 -CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 -ROUTE 3 1.504 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.371 R4C4D.A0 to R4C4D.F0 SLICE_90 -ROUTE 2 1.550 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c) - -------- - 12.326 (22.6% logic, 77.4% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_94: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R5C5A.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.416ns (weighted slack = 324.832ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i0 (from PHI2_c +) - Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -) - - Delay: 12.319ns (22.6% logic, 77.4% route), 7 logic levels. - - Constraint Details: - - 12.319ns physical path delay SLICE_94 to SLICE_88 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 174.735ns) by 162.416ns - - Physical Path Details: - - Data path SLICE_94 to SLICE_88: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) -ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 -CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 -ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 -CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 -ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 -CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 -ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 -CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 -ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 -CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 -ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 -ROUTE 2 1.543 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c) - -------- - 12.319 (22.6% logic, 77.4% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_94: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_88: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R2C4A.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.564ns (weighted slack = 325.128ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) - - Delay: 12.171ns (22.9% logic, 77.1% route), 7 logic levels. - - Constraint Details: - - 12.171ns physical path delay SLICE_95 to SLICE_19 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 174.735ns) by 162.564ns - - Physical Path Details: - - Data path SLICE_95 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c) -ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6 -CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82 -ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 -CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 -ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 -CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 -ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 -CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 -ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 -CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 -ROUTE 3 1.504 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.371 R4C4D.A0 to R4C4D.F0 SLICE_90 -ROUTE 2 1.550 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c) - -------- - 12.171 (22.9% logic, 77.1% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_95: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R5C5A.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.571ns (weighted slack = 325.142ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i6 (from PHI2_c +) - Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -) - - Delay: 12.164ns (22.9% logic, 77.1% route), 7 logic levels. - - Constraint Details: - - 12.164ns physical path delay SLICE_95 to SLICE_88 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 174.735ns) by 162.571ns - - Physical Path Details: - - Data path SLICE_95 to SLICE_88: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c) -ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6 -CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82 -ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 -CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 -ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 -CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 -ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 -CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 -ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 -CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 -ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 -ROUTE 2 1.543 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c) - -------- - 12.164 (22.9% logic, 77.1% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_95: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_88: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R2C4A.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.606ns (weighted slack = 325.212ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i7 (from PHI2_c +) - Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) - FF CmdUFMCLK_386 - - Delay: 12.129ns (23.0% logic, 77.0% route), 7 logic levels. - - Constraint Details: - - 12.129ns physical path delay SLICE_95 to SLICE_83 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 174.735ns) by 162.606ns - - Physical Path Details: - - Data path SLICE_95 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q1 SLICE_95 (from PHI2_c) -ROUTE 1 1.155 R2C2C.Q1 to R5C2B.D1 Bank_7 -CTOF_DEL --- 0.371 R5C2B.D1 to R5C2B.F1 SLICE_67 -ROUTE 1 0.304 R5C2B.F1 to R5C2C.D1 n2154 -CTOF_DEL --- 0.371 R5C2C.D1 to R5C2C.F1 SLICE_82 -ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 -CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 -ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 -CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 -ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 -CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 -ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 -ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) - -------- - 12.129 (23.0% logic, 77.0% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_95: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.635ns (weighted slack = 325.270ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i1 (from PHI2_c +) - Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) - FF CmdUFMCLK_386 - - Delay: 12.100ns (20.0% logic, 80.0% route), 6 logic levels. - - Constraint Details: - - 12.100ns physical path delay SLICE_94 to SLICE_83 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 174.735ns) by 162.635ns - - Physical Path Details: - - Data path SLICE_94 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q1 SLICE_94 (from PHI2_c) -ROUTE 1 1.905 R2C3B.Q1 to R6C2B.C1 Bank_1 -CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_97 -ROUTE 1 1.444 R6C2B.F1 to R5C5B.C1 n2170 -CTOF_DEL --- 0.371 R5C5B.C1 to R5C5B.F1 SLICE_76 -ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 -CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 -ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 -CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 -ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 -ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) - -------- - 12.100 (20.0% logic, 80.0% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_94: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.868ns (weighted slack = 325.736ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i5 (from PHI2_c +) - Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) - FF CmdUFMCLK_386 - - Delay: 11.867ns (23.5% logic, 76.5% route), 7 logic levels. - - Constraint Details: - - 11.867ns physical path delay SLICE_97 to SLICE_83 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 174.735ns) by 162.868ns - - Physical Path Details: - - Data path SLICE_97 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R6C2B.CLK to R6C2B.Q1 SLICE_97 (from PHI2_c) -ROUTE 1 0.700 R6C2B.Q1 to R5C2C.D0 Bank_5 -CTOF_DEL --- 0.371 R5C2C.D0 to R5C2C.F0 SLICE_82 -ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 -CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 -ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 -CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 -ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 -CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 -ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 -CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 -ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72 -ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) - -------- - 11.867 (23.5% logic, 76.5% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_97: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R6C2B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 162.886ns (weighted slack = 325.772ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i0 (from PHI2_c +) - Destination: FF Data in XOR8MEG_381 (to PHI2_c -) - - Delay: 11.849ns (23.5% logic, 76.5% route), 7 logic levels. - - Constraint Details: - - 11.849ns physical path delay SLICE_94 to SLICE_96 meets - 175.000ns delay constraint less - 0.000ns skew and - 0.265ns CE_SET requirement (totaling 174.735ns) by 162.886ns - - Physical Path Details: - - Data path SLICE_94 to SLICE_96: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c) -ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0 -CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82 -ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166 -CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82 -ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26 -CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76 -ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285 -CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89 -ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290 -CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18 -ROUTE 3 1.504 R5C3C.F1 to R4C4D.A1 XOR8MEG_N_112 -CTOF_DEL --- 0.371 R4C4D.A1 to R4C4D.F1 SLICE_90 -ROUTE 1 1.073 R4C4D.F1 to R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c) - -------- - 11.849 (23.5% logic, 76.5% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_94: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_96: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 3.911 39.PADDI to R3C4B.CLK PHI2_c - -------- - 3.911 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 26.150ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 348.000ns - The internal maximum frequency of the following component is 500.000 MHz - - Logical Details: Cell type Pin name Component name - - Destination: FSLICE CLK SLICE_76 - - Delay: 2.000ns -- based on Minimum Pulse Width - -Report: 2.000ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 348.000ns - The internal maximum frequency of the following component is 500.000 MHz - - Logical Details: Cell type Pin name Component name - - Destination: FSLICE CLK SLICE_77 - - Delay: 2.000ns -- based on Minimum Pulse Width - -Report: 2.000ns is the minimum period for this preference. - - -================================================================================ -Preference: PERIOD NET "RCLK_c" 16.000000 ns ; - 395 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 7.566ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_577__i15 (from RCLK_c +) - Destination: FF Data in LEDEN_392 (to RCLK_c +) - - Delay: 8.190ns (29.5% logic, 70.5% route), 6 logic levels. - - Constraint Details: - - 8.190ns physical path delay SLICE_7 to SLICE_89 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.566ns - - Physical Path Details: - - Data path SLICE_7 to SLICE_89: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) -ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 -CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 -ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 -ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 -CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 -ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 -CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 -ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 -CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 -ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) - -------- - 8.190 (29.5% logic, 70.5% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_7: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_89: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.590ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_577__i15 (from RCLK_c +) - Destination: FF Data in n8MEGEN_391 (to RCLK_c +) - - Delay: 8.166ns (29.6% logic, 70.4% route), 6 logic levels. - - Constraint Details: - - 8.166ns physical path delay SLICE_7 to SLICE_56 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.590ns - - Physical Path Details: - - Data path SLICE_7 to SLICE_56: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) -ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 -CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 -ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 -ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 -CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 -ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 -CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 -ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 -CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 -ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) - -------- - 8.166 (29.6% logic, 70.4% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_7: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_56: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 7.984ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_577__i13 (from RCLK_c +) - Destination: FF Data in LEDEN_392 (to RCLK_c +) - - Delay: 7.772ns (31.1% logic, 68.9% route), 6 logic levels. - - Constraint Details: - - 7.772ns physical path delay SLICE_8 to SLICE_89 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 7.984ns - - Physical Path Details: - - Data path SLICE_8 to SLICE_89: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q1 SLICE_8 (from RCLK_c) -ROUTE 3 1.511 R8C4C.Q1 to R7C5C.A0 FS_13 -CTOF_DEL --- 0.371 R7C5C.A0 to R7C5C.F0 SLICE_78 -ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 -ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 -CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 -ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 -CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 -ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 -CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 -ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) - -------- - 7.772 (31.1% logic, 68.9% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_8: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_89: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.008ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_577__i13 (from RCLK_c +) - Destination: FF Data in n8MEGEN_391 (to RCLK_c +) - - Delay: 7.748ns (31.2% logic, 68.8% route), 6 logic levels. - - Constraint Details: - - 7.748ns physical path delay SLICE_8 to SLICE_56 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.008ns - - Physical Path Details: - - Data path SLICE_8 to SLICE_56: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q1 SLICE_8 (from RCLK_c) -ROUTE 3 1.511 R8C4C.Q1 to R7C5C.A0 FS_13 -CTOF_DEL --- 0.371 R7C5C.A0 to R7C5C.F0 SLICE_78 -ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 -ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 -CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 -ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 -CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 -ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 -CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 -ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) - -------- - 7.748 (31.2% logic, 68.8% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_8: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_56: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.123ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_577__i12 (from RCLK_c +) - Destination: FF Data in LEDEN_392 (to RCLK_c +) - - Delay: 7.633ns (31.6% logic, 68.4% route), 6 logic levels. - - Constraint Details: - - 7.633ns physical path delay SLICE_8 to SLICE_89 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.123ns - - Physical Path Details: - - Data path SLICE_8 to SLICE_89: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q0 SLICE_8 (from RCLK_c) -ROUTE 3 1.372 R8C4C.Q0 to R7C5C.C0 FS_12 -CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_78 -ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 -ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 -CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 -ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 -CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 -ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 -CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 -ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) - -------- - 7.633 (31.6% logic, 68.4% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_8: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_89: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.147ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_577__i12 (from RCLK_c +) - Destination: FF Data in n8MEGEN_391 (to RCLK_c +) - - Delay: 7.609ns (31.7% logic, 68.3% route), 6 logic levels. - - Constraint Details: - - 7.609ns physical path delay SLICE_8 to SLICE_56 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.147ns - - Physical Path Details: - - Data path SLICE_8 to SLICE_56: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q0 SLICE_8 (from RCLK_c) -ROUTE 3 1.372 R8C4C.Q0 to R7C5C.C0 FS_12 -CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_78 -ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 -ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 -CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 -ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 -CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 -ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 -CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 -ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) - -------- - 7.609 (31.7% logic, 68.3% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_8: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_56: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.262ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_577__i15 (from RCLK_c +) - Destination: FF Data in UFMCLK_389 (to RCLK_c +) - - Delay: 7.112ns (23.5% logic, 76.5% route), 4 logic levels. - - Constraint Details: - - 7.112ns physical path delay SLICE_7 to SLICE_42 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns - - Physical Path Details: - - Data path SLICE_7 to SLICE_42: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) -ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 -CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 -ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 -ROUTE 4 0.915 R7C4A.F1 to R6C4A.C0 n2300 -CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_86 -ROUTE 2 1.538 R6C4A.F0 to R7C5A.LSR n2291 (to RCLK_c) - -------- - 7.112 (23.5% logic, 76.5% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_7: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_42: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R7C5A.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.262ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_577__i15 (from RCLK_c +) - Destination: FF Data in UFMSDI_390 (to RCLK_c +) - - Delay: 7.112ns (23.5% logic, 76.5% route), 4 logic levels. - - Constraint Details: - - 7.112ns physical path delay SLICE_7 to SLICE_43 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns - - Physical Path Details: - - Data path SLICE_7 to SLICE_43: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c) -ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15 -CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78 -ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 -ROUTE 4 0.915 R7C4A.F1 to R6C4A.C0 n2300 -CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_86 -ROUTE 2 1.538 R6C4A.F0 to R7C5B.LSR n2291 (to RCLK_c) - -------- - 7.112 (23.5% logic, 76.5% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_7: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_43: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R7C5B.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.316ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_577__i14 (from RCLK_c +) - Destination: FF Data in LEDEN_392 (to RCLK_c +) - - Delay: 7.440ns (32.5% logic, 67.5% route), 6 logic levels. - - Constraint Details: - - 7.440ns physical path delay SLICE_7 to SLICE_89 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.316ns - - Physical Path Details: - - Data path SLICE_7 to SLICE_89: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q0 SLICE_7 (from RCLK_c) -ROUTE 3 1.179 R8C4D.Q0 to R7C5C.D0 FS_14 -CTOF_DEL --- 0.371 R7C5C.D0 to R7C5C.F0 SLICE_78 -ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 -ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 -CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 -ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 -CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 -ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119 -CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75 -ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c) - -------- - 7.440 (32.5% logic, 67.5% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_7: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_89: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 8.340ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS_577__i14 (from RCLK_c +) - Destination: FF Data in n8MEGEN_391 (to RCLK_c +) - - Delay: 7.416ns (32.6% logic, 67.4% route), 6 logic levels. - - Constraint Details: - - 7.416ns physical path delay SLICE_7 to SLICE_56 meets - 16.000ns delay constraint less - 0.000ns skew and - 0.244ns CE_SET requirement (totaling 15.756ns) by 8.340ns - - Physical Path Details: - - Data path SLICE_7 to SLICE_56: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q0 SLICE_7 (from RCLK_c) -ROUTE 3 1.179 R8C4D.Q0 to R7C5C.D0 FS_14 -CTOF_DEL --- 0.371 R7C5C.D0 to R7C5C.F0 SLICE_78 -ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10 -CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73 -ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300 -CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73 -ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11 -CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75 -ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119 -CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33 -ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c) - -------- - 7.416 (32.6% logic, 67.4% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_7: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_56: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c - -------- - 1.353 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 8.434ns is the minimum period for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.904ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA10_373 (from RCLK_c +) - Destination: Port Pad RA[10] - - Data Path Delay: 6.180ns (67.9% logic, 32.1% route), 2 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_55 and - 6.180ns delay SLICE_55 to RA[10] (totaling 8.596ns) meets - 12.500ns offset RCLK to RA[10] by 3.904ns - - Physical Path Details: - - Clock path RCLK to SLICE_55: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C4B.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_55 to RA[10]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C4B.CLK to R2C4B.Q0 SLICE_55 (from RCLK_c) -ROUTE 1 1.984 R2C4B.Q0 to 87.PADDO n980 -DOPAD_DEL --- 3.636 87.PADDO to 87.PAD RA[10] - -------- - 6.180 (67.9% logic, 32.1% route), 2 logic levels. - -Report: 8.596ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.734ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[9] - - Data Path Delay: 6.350ns (71.9% logic, 28.1% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 6.350ns delay SLICE_64 to RA[9] (totaling 8.766ns) meets - 12.500ns offset RCLK to RA[9] by 3.734ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RA[9]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.966 R2C2A.Q0 to R2C4A.C1 nRowColSel -CTOF_DEL --- 0.371 R2C4A.C1 to R2C4A.F1 SLICE_88 -ROUTE 1 0.817 R2C4A.F1 to 85.PADDO RA_c_9 -DOPAD_DEL --- 3.636 85.PADDO to 85.PAD RA[9] - -------- - 6.350 (71.9% logic, 28.1% route), 3 logic levels. - -Report: 8.766ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.604ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[8] - - Data Path Delay: 6.480ns (70.5% logic, 29.5% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 6.480ns delay SLICE_64 to RA[8] (totaling 8.896ns) meets - 12.500ns offset RCLK to RA[8] by 3.604ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RA[8]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 1.096 R2C2A.Q0 to R2C2C.B0 nRowColSel -CTOF_DEL --- 0.371 R2C2C.B0 to R2C2C.F0 SLICE_95 -ROUTE 1 0.817 R2C2C.F0 to 96.PADDO RA_c_8 -DOPAD_DEL --- 3.636 96.PADDO to 96.PAD RA[8] - -------- - 6.480 (70.5% logic, 29.5% route), 3 logic levels. - -Report: 8.896ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.245ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[7] - - Data Path Delay: 7.839ns (58.3% logic, 41.7% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 7.839ns delay SLICE_64 to RA[7] (totaling 10.255ns) meets - 12.500ns offset RCLK to RA[7] by 2.245ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RA[7]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 1.234 R2C2A.Q0 to R6C2B.D0 nRowColSel -CTOF_DEL --- 0.371 R6C2B.D0 to R6C2B.F0 SLICE_97 -ROUTE 1 2.038 R6C2B.F0 to 100.PADDO RA_c_7 -DOPAD_DEL --- 3.636 100.PADDO to 100.PAD RA[7] - -------- - 7.839 (58.3% logic, 41.7% route), 3 logic levels. - -Report: 10.255ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.499ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[6] - - Data Path Delay: 7.585ns (60.2% logic, 39.8% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 7.585ns delay SLICE_64 to RA[6] (totaling 10.001ns) meets - 12.500ns offset RCLK to RA[6] by 2.499ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RA[6]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.966 R2C2A.Q0 to R3C2A.C0 nRowColSel -CTOF_DEL --- 0.371 R3C2A.C0 to R3C2A.F0 SLICE_98 -ROUTE 1 2.052 R3C2A.F0 to 91.PADDO RA_c_6 -DOPAD_DEL --- 3.636 91.PADDO to 91.PAD RA[6] - -------- - 7.585 (60.2% logic, 39.8% route), 3 logic levels. - -Report: 10.001ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.891ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[5] - - Data Path Delay: 7.193ns (63.5% logic, 36.5% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 7.193ns delay SLICE_64 to RA[5] (totaling 9.609ns) meets - 12.500ns offset RCLK to RA[5] by 2.891ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RA[5]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.966 R2C2A.Q0 to R3C2A.C1 nRowColSel -CTOF_DEL --- 0.371 R3C2A.C1 to R3C2A.F1 SLICE_98 -ROUTE 1 1.660 R3C2A.F1 to 95.PADDO RA_c_5 -DOPAD_DEL --- 3.636 95.PADDO to 95.PAD RA[5] - -------- - 7.193 (63.5% logic, 36.5% route), 3 logic levels. - -Report: 9.609ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.996ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[4] - - Data Path Delay: 6.088ns (75.0% logic, 25.0% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 6.088ns delay SLICE_64 to RA[4] (totaling 8.504ns) meets - 12.500ns offset RCLK to RA[4] by 3.996ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RA[4]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.704 R2C2A.Q0 to R2C2A.D1 nRowColSel -CTOF_DEL --- 0.371 R2C2A.D1 to R2C2A.F1 SLICE_64 -ROUTE 1 0.817 R2C2A.F1 to 99.PADDO RA_c_4 -DOPAD_DEL --- 3.636 99.PADDO to 99.PAD RA[4] - -------- - 6.088 (75.0% logic, 25.0% route), 3 logic levels. - -Report: 8.504ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.567ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[3] - - Data Path Delay: 7.517ns (60.8% logic, 39.2% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 7.517ns delay SLICE_64 to RA[3] (totaling 9.933ns) meets - 12.500ns offset RCLK to RA[3] by 2.567ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RA[3]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.966 R2C2A.Q0 to R2C3B.C1 nRowColSel -CTOF_DEL --- 0.371 R2C3B.C1 to R2C3B.F1 SLICE_94 -ROUTE 1 1.984 R2C3B.F1 to 97.PADDO RA_c_3 -DOPAD_DEL --- 3.636 97.PADDO to 97.PAD RA[3] - -------- - 7.517 (60.8% logic, 39.2% route), 3 logic levels. - -Report: 9.933ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.438ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[2] - - Data Path Delay: 7.646ns (59.7% logic, 40.3% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 7.646ns delay SLICE_64 to RA[2] (totaling 10.062ns) meets - 12.500ns offset RCLK to RA[2] by 2.438ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RA[2]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 1.096 R2C2A.Q0 to R2C2C.B1 nRowColSel -CTOF_DEL --- 0.371 R2C2C.B1 to R2C2C.F1 SLICE_95 -ROUTE 1 1.983 R2C2C.F1 to 94.PADDO RA_c_2 -DOPAD_DEL --- 3.636 94.PADDO to 94.PAD RA[2] - -------- - 7.646 (59.7% logic, 40.3% route), 3 logic levels. - -Report: 10.062ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.734ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[1] - - Data Path Delay: 6.350ns (71.9% logic, 28.1% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 6.350ns delay SLICE_64 to RA[1] (totaling 8.766ns) meets - 12.500ns offset RCLK to RA[1] by 3.734ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RA[1]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.966 R2C2A.Q0 to R2C3B.C0 nRowColSel -CTOF_DEL --- 0.371 R2C3B.C0 to R2C3B.F0 SLICE_94 -ROUTE 1 0.817 R2C3B.F0 to 89.PADDO RA_c_1 -DOPAD_DEL --- 3.636 89.PADDO to 89.PAD RA[1] - -------- - 6.350 (71.9% logic, 28.1% route), 3 logic levels. - -Report: 8.766ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.826ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[0] - - Data Path Delay: 7.258ns (62.9% logic, 37.1% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 7.258ns delay SLICE_64 to RA[0] (totaling 9.674ns) meets - 12.500ns offset RCLK to RA[0] by 2.826ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RA[0]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 1.165 R2C2A.Q0 to R3C2B.B1 nRowColSel -CTOF_DEL --- 0.371 R3C2B.B1 to R3C2B.F1 SLICE_92 -ROUTE 1 1.526 R3C2B.F1 to 98.PADDO RA_c_0 -DOPAD_DEL --- 3.636 98.PADDO to 98.PAD RA[0] - -------- - 7.258 (62.9% logic, 37.1% route), 3 logic levels. - -Report: 9.674ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 5.071ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCS_369 (from RCLK_c +) - Destination: Port Pad nRCS - - Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_60 and - 5.013ns delay SLICE_60 to nRCS (totaling 7.429ns) meets - 12.500ns offset RCLK to nRCS by 5.071ns - - Physical Path Details: - - Clock path RCLK to SLICE_60: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C5B.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_60 to nRCS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C5B.CLK to R2C5B.Q0 SLICE_60 (from RCLK_c) -ROUTE 1 0.817 R2C5B.Q0 to 77.PADDO nRCS_c -DOPAD_DEL --- 3.636 77.PADDO to 77.PAD nRCS - -------- - 5.013 (83.7% logic, 16.3% route), 2 logic levels. - -Report: 7.429ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.420ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RCKE_368 (from RCLK_c +) - Destination: Port Pad RCKE - - Data Path Delay: 6.664ns (63.0% logic, 37.0% route), 2 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_34 and - 6.664ns delay SLICE_34 to RCKE (totaling 9.080ns) meets - 12.500ns offset RCLK to RCKE by 3.420ns - - Physical Path Details: - - Clock path RCLK to SLICE_34: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R5C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_34 to RCKE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R5C2A.CLK to R5C2A.Q0 SLICE_34 (from RCLK_c) -ROUTE 4 2.468 R5C2A.Q0 to 82.PADDO RCKE_c -DOPAD_DEL --- 3.636 82.PADDO to 82.PAD RCKE - -------- - 6.664 (63.0% logic, 37.0% route), 2 logic levels. - -Report: 9.080ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 5.071ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRWE_372 (from RCLK_c +) - Destination: Port Pad nRWE - - Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_63 and - 5.013ns delay SLICE_63 to nRWE (totaling 7.429ns) meets - 12.500ns offset RCLK to nRWE by 5.071ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R3C5B.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_63 to nRWE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R3C5B.CLK to R3C5B.Q0 SLICE_63 (from RCLK_c) -ROUTE 1 0.817 R3C5B.Q0 to 72.PADDO nRWE_c -DOPAD_DEL --- 3.636 72.PADDO to 72.PAD nRWE - -------- - 5.013 (83.7% logic, 16.3% route), 2 logic levels. - -Report: 7.429ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.885ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRRAS_370 (from RCLK_c +) - Destination: Port Pad nRRAS - - Data Path Delay: 6.199ns (67.7% logic, 32.3% route), 2 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_61 and - 6.199ns delay SLICE_61 to nRRAS (totaling 8.615ns) meets - 12.500ns offset RCLK to nRRAS by 3.885ns - - Physical Path Details: - - Clock path RCLK to SLICE_61: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R4C5A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_61 to nRRAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R4C5A.CLK to R4C5A.Q0 SLICE_61 (from RCLK_c) -ROUTE 2 2.003 R4C5A.Q0 to 73.PADDO nRRAS_c -DOPAD_DEL --- 3.636 73.PADDO to 73.PAD nRRAS - -------- - 6.199 (67.7% logic, 32.3% route), 2 logic levels. - -Report: 8.615ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.905ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCAS_371 (from RCLK_c +) - Destination: Port Pad nRCAS - - Data Path Delay: 6.179ns (67.9% logic, 32.1% route), 2 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_58 and - 6.179ns delay SLICE_58 to nRCAS (totaling 8.595ns) meets - 12.500ns offset RCLK to nRCAS by 3.905ns - - Physical Path Details: - - Clock path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C4C.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_58 to nRCAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_58 (from RCLK_c) -ROUTE 1 1.983 R2C4C.Q0 to 78.PADDO nRCAS_c -DOPAD_DEL --- 3.636 78.PADDO to 78.PAD nRCAS - -------- - 6.179 (67.9% logic, 32.1% route), 2 logic levels. - -Report: 8.595ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 3.025ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RDQMH - - Data Path Delay: 7.059ns (64.7% logic, 35.3% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 7.059ns delay SLICE_64 to RDQMH (totaling 9.475ns) meets - 12.500ns offset RCLK to RDQMH by 3.025ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RDQMH: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.966 R2C2A.Q0 to R2C4A.C0 nRowColSel -CTOF_DEL --- 0.371 R2C4A.C0 to R2C4A.F0 SLICE_88 -ROUTE 1 1.526 R2C4A.F0 to 76.PADDO RDQMH_c -DOPAD_DEL --- 3.636 76.PADDO to 76.PAD RDQMH - -------- - 7.059 (64.7% logic, 35.3% route), 3 logic levels. - -Report: 9.475ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.023ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RDQML - - Data Path Delay: 8.061ns (56.7% logic, 43.3% route), 3 logic levels. - - Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels. - - Constraint Details: - 2.416ns delay RCLK to SLICE_64 and - 8.061ns delay SLICE_64 to RDQML (totaling 10.477ns) meets - 12.500ns offset RCLK to RDQML by 2.023ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK -ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c - -------- - 2.416 (44.0% logic, 56.0% route), 1 logic levels. - - Data path SLICE_64 to RDQML: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.954 R2C2A.Q0 to R3C2B.C0 nRowColSel -CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_92 -ROUTE 1 2.540 R3C2B.F0 to 61.PADDO RDQML_c -DOPAD_DEL --- 3.636 61.PADDO to 61.PAD RDQML - -------- - 8.061 (56.7% logic, 43.3% route), 3 logic levels. - -Report: 10.477ns is the minimum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 26.150 ns| 7 - | | | -PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 - | | | -PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0 - | | | -PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 8.434 ns| 6 - | | | -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.596 ns| 2 - | | | -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.766 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.896 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 10.255 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 10.001 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.609 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.504 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.933 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 10.062 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.766 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.674 ns| 3 - | | | -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 7.429 ns| 2 - | | | -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.080 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 7.429 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.615 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 8.595 ns| 2 - | | | -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 9.475 ns| 3 - | | | -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | -CLKPORT "RCLK" ; | 12.500 ns| 10.477 ns| 3 - | | | -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 4 clocks: - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; - - Data transfers from: - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Setup): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 -Mon Aug 16 21:32:34 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -Design file: ram2gs_lcmxo256c_impl1.ncd -Preference file: ram2gs_lcmxo256c_impl1.prf -Device,speed: LCMXO256C,m -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - -Derating parameters -------------------- -Voltage: 3.300 V - - - -================================================================================ -Preference: PERIOD NET "PHI2_c" 350.000000 ns ; - 113 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.444ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ADSubmitted_380 (from PHI2_c -) - Destination: FF Data in ADSubmitted_380 (to PHI2_c -) - - Delay: 0.421ns (62.2% logic, 37.8% route), 2 logic levels. - - Constraint Details: - - 0.421ns physical path delay SLICE_9 to SLICE_9 meets - -0.023ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.023ns) by 0.444ns - - Physical Path Details: - - Data path SLICE_9 to SLICE_9: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.170 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c) -ROUTE 2 0.159 R5C3A.Q0 to R5C3A.D0 ADSubmitted -CTOF_DEL --- 0.092 R5C3A.D0 to R5C3A.F0 SLICE_9 -ROUTE 1 0.000 R5C3A.F0 to R5C3A.DI0 n1361 (to PHI2_c) - -------- - 0.421 (62.2% logic, 37.8% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_9: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_9: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.186ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_378 (from PHI2_c -) - Destination: FF Data in Cmdn8MEGEN_383 (to PHI2_c -) - - Delay: 1.157ns (30.6% logic, 69.4% route), 3 logic levels. - - Constraint Details: - - 1.157ns physical path delay SLICE_18 to SLICE_23 meets - -0.029ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.029ns) by 1.186ns - - Physical Path Details: - - Data path SLICE_18 to SLICE_23: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) -ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable -CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 -ROUTE 3 0.383 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.092 R4C4D.A0 to R4C4D.F0 SLICE_90 -ROUTE 2 0.167 R4C4D.F0 to R4C4C.CE PHI2_N_114_enable_6 (to PHI2_c) - -------- - 1.157 (30.6% logic, 69.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_23: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R4C4C.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.193ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q C1Submitted_379 (from PHI2_c -) - Destination: FF Data in CmdEnable_378 (to PHI2_c -) - - Delay: 1.164ns (38.3% logic, 61.7% route), 4 logic levels. - - Constraint Details: - - 1.164ns physical path delay SLICE_14 to SLICE_18 meets - -0.029ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.029ns) by 1.193ns - - Physical Path Details: - - Data path SLICE_14 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.170 R6C3B.CLK to R6C3B.Q0 SLICE_14 (from PHI2_c) -ROUTE 1 0.253 R6C3B.Q0 to R6C3B.B1 C1Submitted -CTOF_DEL --- 0.092 R6C3B.B1 to R6C3B.F1 SLICE_14 -ROUTE 1 0.075 R6C3B.F1 to R6C3C.D1 n2098 -CTOF_DEL --- 0.092 R6C3C.D1 to R6C3C.F1 SLICE_77 -ROUTE 1 0.123 R6C3C.F1 to R6C3C.C0 n2286 -CTOF_DEL --- 0.092 R6C3C.C0 to R6C3C.F0 SLICE_77 -ROUTE 1 0.267 R6C3C.F0 to R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c) - -------- - 1.164 (38.3% logic, 61.7% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_14: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R6C3B.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.280ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ADSubmitted_380 (from PHI2_c -) - Destination: FF Data in CmdEnable_378 (to PHI2_c -) - - Delay: 1.251ns (35.7% logic, 64.3% route), 4 logic levels. - - Constraint Details: - - 1.251ns physical path delay SLICE_9 to SLICE_18 meets - -0.029ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.029ns) by 1.280ns - - Physical Path Details: - - Data path SLICE_9 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.170 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c) -ROUTE 2 0.159 R5C3A.Q0 to R5C3A.D1 ADSubmitted -CTOF_DEL --- 0.092 R5C3A.D1 to R5C3A.F1 SLICE_9 -ROUTE 1 0.256 R5C3A.F1 to R6C3C.A1 n2080 -CTOF_DEL --- 0.092 R6C3C.A1 to R6C3C.F1 SLICE_77 -ROUTE 1 0.123 R6C3C.F1 to R6C3C.C0 n2286 -CTOF_DEL --- 0.092 R6C3C.C0 to R6C3C.F0 SLICE_77 -ROUTE 1 0.267 R6C3C.F0 to R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c) - -------- - 1.251 (35.7% logic, 64.3% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_9: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.286ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_378 (from PHI2_c -) - Destination: FF Data in XOR8MEG_381 (to PHI2_c -) - - Delay: 1.257ns (28.2% logic, 71.8% route), 3 logic levels. - - Constraint Details: - - 1.257ns physical path delay SLICE_18 to SLICE_96 meets - -0.029ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.029ns) by 1.286ns - - Physical Path Details: - - Data path SLICE_18 to SLICE_96: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) -ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable -CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 -ROUTE 3 0.383 R5C3C.F1 to R4C4D.A1 XOR8MEG_N_112 -CTOF_DEL --- 0.092 R4C4D.A1 to R4C4D.F1 SLICE_90 -ROUTE 1 0.267 R4C4D.F1 to R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c) - -------- - 1.257 (28.2% logic, 71.8% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_96: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R3C4B.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.400ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_378 (from PHI2_c -) - Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -) - - Delay: 1.371ns (25.8% logic, 74.2% route), 3 logic levels. - - Constraint Details: - - 1.371ns physical path delay SLICE_18 to SLICE_88 meets - -0.029ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.029ns) by 1.400ns - - Physical Path Details: - - Data path SLICE_18 to SLICE_88: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) -ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable -CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 -ROUTE 3 0.383 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.092 R4C4A.A0 to R4C4A.F0 SLICE_72 -ROUTE 2 0.381 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c) - -------- - 1.371 (25.8% logic, 74.2% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_88: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R2C4A.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.414ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_378 (from PHI2_c -) - Destination: FF Data in CmdSubmitted_384 (to PHI2_c -) - - Delay: 1.385ns (25.6% logic, 74.4% route), 3 logic levels. - - Constraint Details: - - 1.385ns physical path delay SLICE_18 to SLICE_19 meets - -0.029ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.029ns) by 1.414ns - - Physical Path Details: - - Data path SLICE_18 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) -ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable -CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 -ROUTE 3 0.383 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.092 R4C4D.A0 to R4C4D.F0 SLICE_90 -ROUTE 2 0.395 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c) - -------- - 1.385 (25.6% logic, 74.4% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_19: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C5A.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 1.537ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdEnable_378 (from PHI2_c -) - Destination: FF Data in CmdUFMCS_385 (to PHI2_c -) - FF CmdUFMCLK_386 - - Delay: 1.508ns (23.5% logic, 76.5% route), 3 logic levels. - - Constraint Details: - - 1.508ns physical path delay SLICE_18 to SLICE_83 meets - -0.029ns CE_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.029ns) by 1.537ns - - Physical Path Details: - - Data path SLICE_18 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c) -ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable -CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18 -ROUTE 3 0.383 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112 -CTOF_DEL --- 0.092 R4C4A.A0 to R4C4A.F0 SLICE_72 -ROUTE 2 0.518 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c) - -------- - 1.508 (23.5% logic, 76.5% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_83: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R5C4B.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 175.681ns (weighted slack = 351.362ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q XOR8MEG_381 (from PHI2_c -) - Destination: FF Data in RA11_358 (to PHI2_c +) - - Delay: 0.670ns (39.1% logic, 60.9% route), 2 logic levels. - - Constraint Details: - - 0.670ns physical path delay SLICE_96 to SLICE_31 meets - -0.011ns DIN_HLD and - -175.000ns delay constraint less - 0.000ns skew requirement (totaling -175.011ns) by 175.681ns - - Physical Path Details: - - Data path SLICE_96 to SLICE_31: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.170 R3C4B.CLK to R3C4B.Q0 SLICE_96 (from PHI2_c) -ROUTE 1 0.408 R3C4B.Q0 to R2C5A.D0 XOR8MEG -CTOF_DEL --- 0.092 R2C5A.D0 to R2C5A.F0 SLICE_31 -ROUTE 1 0.000 R2C5A.F0 to R2C5A.DI0 RA11_N_180 (to PHI2_c) - -------- - 0.670 (39.1% logic, 60.9% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_96: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R3C4B.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_31: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R2C5A.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 176.485ns (weighted slack = 352.970ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q Bank_i3 (from PHI2_c +) - Destination: FF Data in C1Submitted_379 (to PHI2_c -) - - Delay: 1.456ns (23.4% logic, 76.6% route), 3 logic levels. - - Constraint Details: - - 1.456ns physical path delay SLICE_98 to SLICE_14 meets - -0.029ns CE_HLD and - -175.000ns delay constraint less - 0.000ns skew requirement (totaling -175.029ns) by 176.485ns - - Physical Path Details: - - Data path SLICE_98 to SLICE_14: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R3C2A.CLK to R3C2A.Q1 SLICE_98 (from PHI2_c) -ROUTE 1 0.495 R3C2A.Q1 to R5C5B.A1 Bank_3 -CTOF_DEL --- 0.092 R5C5B.A1 to R5C5B.F1 SLICE_76 -ROUTE 4 0.459 R5C5B.F1 to R6C3A.D1 n1285 -CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 SLICE_89 -ROUTE 1 0.161 R6C3A.F1 to R6C3B.CE PHI2_N_114_enable_1 (to PHI2_c) - -------- - 1.456 (23.4% logic, 76.6% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path PHI2 to SLICE_98: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R3C2A.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path PHI2 to SLICE_14: - - Name Fanout Delay (ns) Site Resource -ROUTE 14 1.196 39.PADDI to R6C3B.CLK PHI2_c - -------- - 1.196 (0.0% logic, 100.0% route), 0 logic levels. - - -================================================================================ -Preference: PERIOD NET "nCCAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: PERIOD NET "nCRAS_c" 350.000000 ns ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: PERIOD NET "RCLK_c" 16.000000 ns ; - 395 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.339ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i11 (from RCLK_c +) - Destination: FF Data in IS_FSM__i12 (to RCLK_c +) - - Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. - - Constraint Details: - - 0.318ns physical path delay SLICE_72 to SLICE_72 meets - -0.021ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.021ns) by 0.339ns - - Physical Path Details: - - Data path SLICE_72 to SLICE_72: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R4C4A.CLK to R4C4A.Q0 SLICE_72 (from RCLK_c) -ROUTE 1 0.161 R4C4A.Q0 to R4C4A.M1 n702 (to RCLK_c) - -------- - 0.318 (49.4% logic, 50.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_72: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_72: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.339ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i12 (from RCLK_c +) - Destination: FF Data in IS_FSM__i13 (to RCLK_c +) - - Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. - - Constraint Details: - - 0.318ns physical path delay SLICE_72 to SLICE_90 meets - -0.021ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.021ns) by 0.339ns - - Physical Path Details: - - Data path SLICE_72 to SLICE_90: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R4C4A.CLK to R4C4A.Q1 SLICE_72 (from RCLK_c) -ROUTE 1 0.161 R4C4A.Q1 to R4C4D.M0 n701 (to RCLK_c) - -------- - 0.318 (49.4% logic, 50.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_72: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_90: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.339ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i7 (from RCLK_c +) - Destination: FF Data in IS_FSM__i8 (to RCLK_c +) - - Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. - - Constraint Details: - - 0.318ns physical path delay SLICE_73 to SLICE_73 meets - -0.021ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.021ns) by 0.339ns - - Physical Path Details: - - Data path SLICE_73 to SLICE_73: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R7C4A.CLK to R7C4A.Q0 SLICE_73 (from RCLK_c) -ROUTE 1 0.161 R7C4A.Q0 to R7C4A.M1 n706 (to RCLK_c) - -------- - 0.318 (49.4% logic, 50.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_73: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_73: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.339ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i3 (from RCLK_c +) - Destination: FF Data in IS_FSM__i4 (to RCLK_c +) - - Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. - - Constraint Details: - - 0.318ns physical path delay SLICE_74 to SLICE_74 meets - -0.021ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.021ns) by 0.339ns - - Physical Path Details: - - Data path SLICE_74 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R5C3B.CLK to R5C3B.Q0 SLICE_74 (from RCLK_c) -ROUTE 1 0.161 R5C3B.Q0 to R5C3B.M1 n710 (to RCLK_c) - -------- - 0.318 (49.4% logic, 50.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_74: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_74: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.339ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i6 (from RCLK_c +) - Destination: FF Data in IS_FSM__i7 (to RCLK_c +) - - Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. - - Constraint Details: - - 0.318ns physical path delay SLICE_75 to SLICE_73 meets - -0.021ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.021ns) by 0.339ns - - Physical Path Details: - - Data path SLICE_75 to SLICE_73: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R7C4B.CLK to R7C4B.Q1 SLICE_75 (from RCLK_c) -ROUTE 1 0.161 R7C4B.Q1 to R7C4A.M0 n707 (to RCLK_c) - -------- - 0.318 (49.4% logic, 50.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_75: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_73: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.339ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i5 (from RCLK_c +) - Destination: FF Data in IS_FSM__i6 (to RCLK_c +) - - Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. - - Constraint Details: - - 0.318ns physical path delay SLICE_75 to SLICE_75 meets - -0.021ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.021ns) by 0.339ns - - Physical Path Details: - - Data path SLICE_75 to SLICE_75: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R7C4B.CLK to R7C4B.Q0 SLICE_75 (from RCLK_c) -ROUTE 1 0.161 R7C4B.Q0 to R7C4B.M1 n708 (to RCLK_c) - -------- - 0.318 (49.4% logic, 50.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_75: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_75: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.339ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i10 (from RCLK_c +) - Destination: FF Data in IS_FSM__i11 (to RCLK_c +) - - Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. - - Constraint Details: - - 0.318ns physical path delay SLICE_84 to SLICE_72 meets - -0.021ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.021ns) by 0.339ns - - Physical Path Details: - - Data path SLICE_84 to SLICE_72: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R4C4B.CLK to R4C4B.Q1 SLICE_84 (from RCLK_c) -ROUTE 1 0.161 R4C4B.Q1 to R4C4A.M0 n703 (to RCLK_c) - -------- - 0.318 (49.4% logic, 50.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_84: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R4C4B.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_72: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.339ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i2 (from RCLK_c +) - Destination: FF Data in IS_FSM__i3 (to RCLK_c +) - - Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. - - Constraint Details: - - 0.318ns physical path delay SLICE_87 to SLICE_74 meets - -0.021ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.021ns) by 0.339ns - - Physical Path Details: - - Data path SLICE_87 to SLICE_74: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R5C3D.CLK to R5C3D.Q1 SLICE_87 (from RCLK_c) -ROUTE 1 0.161 R5C3D.Q1 to R5C3B.M0 n711 (to RCLK_c) - -------- - 0.318 (49.4% logic, 50.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_87: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R5C3D.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_74: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.339ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q IS_FSM__i13 (from RCLK_c +) - Destination: FF Data in IS_FSM__i14 (to RCLK_c +) - - Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels. - - Constraint Details: - - 0.318ns physical path delay SLICE_90 to SLICE_90 meets - -0.021ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.021ns) by 0.339ns - - Physical Path Details: - - Data path SLICE_90 to SLICE_90: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R4C4D.CLK to R4C4D.Q0 SLICE_90 (from RCLK_c) -ROUTE 1 0.161 R4C4D.Q0 to R4C4D.M1 n700 (to RCLK_c) - -------- - 0.318 (49.4% logic, 50.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_90: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_90: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.345ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RASr2_353 (from RCLK_c +) - Destination: FF Data in RASr3_354 (to RCLK_c +) - - Delay: 0.324ns (48.5% logic, 51.5% route), 1 logic levels. - - Constraint Details: - - 0.324ns physical path delay SLICE_93 to SLICE_93 meets - -0.021ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.021ns) by 0.345ns - - Physical Path Details: - - Data path SLICE_93 to SLICE_93: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R7C5D.CLK to R7C5D.Q0 SLICE_93 (from RCLK_c) -ROUTE 16 0.167 R7C5D.Q0 to R7C5D.M1 RASr2 (to RCLK_c) - -------- - 0.324 (48.5% logic, 51.5% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path RCLK to SLICE_93: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R7C5D.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path RCLK to SLICE_93: - - Name Fanout Delay (ns) Site Resource -ROUTE 39 0.413 86.PADDI to R7C5D.CLK RCLK_c - -------- - 0.413 (0.0% logic, 100.0% route), 0 logic levels. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.220ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA10_373 (from RCLK_c +) - Destination: Port Pad RA[10] - - Data Path Delay: 1.733ns (73.0% logic, 27.0% route), 2 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_55 and - 1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets - 0.000ns hold offset RCLK to RA[10] by 2.220ns - - Physical Path Details: - - Clock path RCLK to SLICE_55: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C4B.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_55 to RA[10]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C4B.CLK to R2C4B.Q0 SLICE_55 (from RCLK_c) -ROUTE 1 0.468 R2C4B.Q0 to 87.PADDO n980 -DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10] - -------- - 1.733 (73.0% logic, 27.0% route), 2 logic levels. - -Report: 2.220ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.284ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[9] - - Data Path Delay: 1.797ns (75.5% logic, 24.5% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 1.797ns delay SLICE_64 to RA[9] (totaling 2.284ns) meets - 0.000ns hold offset RCLK to RA[9] by 2.284ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RA[9]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.243 R2C2A.Q0 to R2C4A.C1 nRowColSel -CTOF_DEL --- 0.092 R2C4A.C1 to R2C4A.F1 SLICE_88 -ROUTE 1 0.197 R2C4A.F1 to 85.PADDO RA_c_9 -DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9] - -------- - 1.797 (75.5% logic, 24.5% route), 3 logic levels. - -Report: 2.284ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.316ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[8] - - Data Path Delay: 1.829ns (74.2% logic, 25.8% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 1.829ns delay SLICE_64 to RA[8] (totaling 2.316ns) meets - 0.000ns hold offset RCLK to RA[8] by 2.316ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RA[8]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.275 R2C2A.Q0 to R2C2C.B0 nRowColSel -CTOF_DEL --- 0.092 R2C2C.B0 to R2C2C.F0 SLICE_95 -ROUTE 1 0.197 R2C2C.F0 to 96.PADDO RA_c_8 -DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8] - -------- - 1.829 (74.2% logic, 25.8% route), 3 logic levels. - -Report: 2.316ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.652ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[7] - - Data Path Delay: 2.165ns (62.7% logic, 37.3% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 2.165ns delay SLICE_64 to RA[7] (totaling 2.652ns) meets - 0.000ns hold offset RCLK to RA[7] by 2.652ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RA[7]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.319 R2C2A.Q0 to R6C2B.D0 nRowColSel -CTOF_DEL --- 0.092 R6C2B.D0 to R6C2B.F0 SLICE_97 -ROUTE 1 0.489 R6C2B.F0 to 100.PADDO RA_c_7 -DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7] - -------- - 2.165 (62.7% logic, 37.3% route), 3 logic levels. - -Report: 2.652ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.579ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[6] - - Data Path Delay: 2.092ns (64.9% logic, 35.1% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 2.092ns delay SLICE_64 to RA[6] (totaling 2.579ns) meets - 0.000ns hold offset RCLK to RA[6] by 2.579ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RA[6]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.243 R2C2A.Q0 to R3C2A.C0 nRowColSel -CTOF_DEL --- 0.092 R3C2A.C0 to R3C2A.F0 SLICE_98 -ROUTE 1 0.492 R3C2A.F0 to 91.PADDO RA_c_6 -DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6] - -------- - 2.092 (64.9% logic, 35.1% route), 3 logic levels. - -Report: 2.579ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.481ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[5] - - Data Path Delay: 1.994ns (68.1% logic, 31.9% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 1.994ns delay SLICE_64 to RA[5] (totaling 2.481ns) meets - 0.000ns hold offset RCLK to RA[5] by 2.481ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RA[5]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.243 R2C2A.Q0 to R3C2A.C1 nRowColSel -CTOF_DEL --- 0.092 R3C2A.C1 to R3C2A.F1 SLICE_98 -ROUTE 1 0.394 R3C2A.F1 to 95.PADDO RA_c_5 -DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5] - -------- - 1.994 (68.1% logic, 31.9% route), 3 logic levels. - -Report: 2.481ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.219ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[4] - - Data Path Delay: 1.732ns (78.3% logic, 21.7% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 1.732ns delay SLICE_64 to RA[4] (totaling 2.219ns) meets - 0.000ns hold offset RCLK to RA[4] by 2.219ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RA[4]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.178 R2C2A.Q0 to R2C2A.D1 nRowColSel -CTOF_DEL --- 0.092 R2C2A.D1 to R2C2A.F1 SLICE_64 -ROUTE 1 0.197 R2C2A.F1 to 99.PADDO RA_c_4 -DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4] - -------- - 1.732 (78.3% logic, 21.7% route), 3 logic levels. - -Report: 2.219ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.555ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[3] - - Data Path Delay: 2.068ns (65.6% logic, 34.4% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 2.068ns delay SLICE_64 to RA[3] (totaling 2.555ns) meets - 0.000ns hold offset RCLK to RA[3] by 2.555ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RA[3]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.243 R2C2A.Q0 to R2C3B.C1 nRowColSel -CTOF_DEL --- 0.092 R2C3B.C1 to R2C3B.F1 SLICE_94 -ROUTE 1 0.468 R2C3B.F1 to 97.PADDO RA_c_3 -DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3] - -------- - 2.068 (65.6% logic, 34.4% route), 3 logic levels. - -Report: 2.555ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.599ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[2] - - Data Path Delay: 2.112ns (64.3% logic, 35.7% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 2.112ns delay SLICE_64 to RA[2] (totaling 2.599ns) meets - 0.000ns hold offset RCLK to RA[2] by 2.599ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RA[2]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.275 R2C2A.Q0 to R2C2C.B1 nRowColSel -CTOF_DEL --- 0.092 R2C2C.B1 to R2C2C.F1 SLICE_95 -ROUTE 1 0.480 R2C2C.F1 to 94.PADDO RA_c_2 -DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2] - -------- - 2.112 (64.3% logic, 35.7% route), 3 logic levels. - -Report: 2.599ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.284ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[1] - - Data Path Delay: 1.797ns (75.5% logic, 24.5% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 1.797ns delay SLICE_64 to RA[1] (totaling 2.284ns) meets - 0.000ns hold offset RCLK to RA[1] by 2.284ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RA[1]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.243 R2C2A.Q0 to R2C3B.C0 nRowColSel -CTOF_DEL --- 0.092 R2C3B.C0 to R2C3B.F0 SLICE_94 -ROUTE 1 0.197 R2C3B.F0 to 89.PADDO RA_c_1 -DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1] - -------- - 1.797 (75.5% logic, 24.5% route), 3 logic levels. - -Report: 2.284ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.492ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RA[0] - - Data Path Delay: 2.005ns (67.7% logic, 32.3% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 2.005ns delay SLICE_64 to RA[0] (totaling 2.492ns) meets - 0.000ns hold offset RCLK to RA[0] by 2.492ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RA[0]: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.292 R2C2A.Q0 to R3C2B.B1 nRowColSel -CTOF_DEL --- 0.092 R3C2B.B1 to R3C2B.F1 SLICE_92 -ROUTE 1 0.356 R3C2B.F1 to 98.PADDO RA_c_0 -DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0] - -------- - 2.005 (67.7% logic, 32.3% route), 3 logic levels. - -Report: 2.492ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.949ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCS_369 (from RCLK_c +) - Destination: Port Pad nRCS - - Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_60 and - 1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets - 0.000ns hold offset RCLK to nRCS by 1.949ns - - Physical Path Details: - - Clock path RCLK to SLICE_60: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C5B.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_60 to nRCS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C5B.CLK to R2C5B.Q0 SLICE_60 (from RCLK_c) -ROUTE 1 0.197 R2C5B.Q0 to 77.PADDO nRCS_c -DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS - -------- - 1.462 (86.5% logic, 13.5% route), 2 logic levels. - -Report: 1.949ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.363ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RCKE_368 (from RCLK_c +) - Destination: Port Pad RCKE - - Data Path Delay: 1.876ns (67.4% logic, 32.6% route), 2 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_34 and - 1.876ns delay SLICE_34 to RCKE (totaling 2.363ns) meets - 0.000ns hold offset RCLK to RCKE by 2.363ns - - Physical Path Details: - - Clock path RCLK to SLICE_34: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R5C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_34 to RCKE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R5C2A.CLK to R5C2A.Q0 SLICE_34 (from RCLK_c) -ROUTE 4 0.611 R5C2A.Q0 to 82.PADDO RCKE_c -DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE - -------- - 1.876 (67.4% logic, 32.6% route), 2 logic levels. - -Report: 2.363ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.949ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRWE_372 (from RCLK_c +) - Destination: Port Pad nRWE - - Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_63 and - 1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets - 0.000ns hold offset RCLK to nRWE by 1.949ns - - Physical Path Details: - - Clock path RCLK to SLICE_63: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R3C5B.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_63 to nRWE: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R3C5B.CLK to R3C5B.Q0 SLICE_63 (from RCLK_c) -ROUTE 1 0.197 R3C5B.Q0 to 72.PADDO nRWE_c -DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE - -------- - 1.462 (86.5% logic, 13.5% route), 2 logic levels. - -Report: 1.949ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.236ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRRAS_370 (from RCLK_c +) - Destination: Port Pad nRRAS - - Data Path Delay: 1.749ns (72.3% logic, 27.7% route), 2 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_61 and - 1.749ns delay SLICE_61 to nRRAS (totaling 2.236ns) meets - 0.000ns hold offset RCLK to nRRAS by 2.236ns - - Physical Path Details: - - Clock path RCLK to SLICE_61: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R4C5A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_61 to nRRAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R4C5A.CLK to R4C5A.Q0 SLICE_61 (from RCLK_c) -ROUTE 2 0.484 R4C5A.Q0 to 73.PADDO nRRAS_c -DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS - -------- - 1.749 (72.3% logic, 27.7% route), 2 logic levels. - -Report: 2.236ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.232ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRCAS_371 (from RCLK_c +) - Destination: Port Pad nRCAS - - Data Path Delay: 1.745ns (72.5% logic, 27.5% route), 2 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_58 and - 1.745ns delay SLICE_58 to nRCAS (totaling 2.232ns) meets - 0.000ns hold offset RCLK to nRCAS by 2.232ns - - Physical Path Details: - - Clock path RCLK to SLICE_58: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C4C.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_58 to nRCAS: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C4C.CLK to R2C4C.Q0 SLICE_58 (from RCLK_c) -ROUTE 1 0.480 R2C4C.Q0 to 78.PADDO nRCAS_c -DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS - -------- - 1.745 (72.5% logic, 27.5% route), 2 logic levels. - -Report: 2.232ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.443ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RDQMH - - Data Path Delay: 1.956ns (69.4% logic, 30.6% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 1.956ns delay SLICE_64 to RDQMH (totaling 2.443ns) meets - 0.000ns hold offset RCLK to RDQMH by 2.443ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RDQMH: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.243 R2C2A.Q0 to R2C4A.C0 nRowColSel -CTOF_DEL --- 0.092 R2C4A.C0 to R2C4A.F0 SLICE_88 -ROUTE 1 0.356 R2C4A.F0 to 76.PADDO RDQMH_c -DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH - -------- - 1.956 (69.4% logic, 30.6% route), 3 logic levels. - -Report: 2.443ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; - 1 item scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 2.713ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q nRowColSel_375 (from RCLK_c +) - Destination: Port Pad RDQML - - Data Path Delay: 2.226ns (61.0% logic, 39.0% route), 3 logic levels. - - Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - 0.487ns delay RCLK to SLICE_64 and - 2.226ns delay SLICE_64 to RDQML (totaling 2.713ns) meets - 0.000ns hold offset RCLK to RDQML by 2.713ns - - Physical Path Details: - - Clock path RCLK to SLICE_64: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK -ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c - -------- - 0.487 (54.2% logic, 45.8% route), 1 logic levels. - - Data path SLICE_64 to RDQML: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c) -ROUTE 13 0.238 R2C2A.Q0 to R3C2B.C0 nRowColSel -CTOF_DEL --- 0.092 R3C2B.C0 to R3C2B.F0 SLICE_92 -ROUTE 1 0.631 R3C2B.F0 to 61.PADDO RDQML_c -DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML - -------- - 2.226 (61.0% logic, 39.0% route), 3 logic levels. - -Report: 2.713ns is the maximum offset for this preference. - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2 - | | | -PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0 - | | | -PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0 - | | | -PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1 - | | | -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | | -ns CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.220 ns| 2 - | | | -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.284 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.316 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.652 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.579 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.481 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.219 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.555 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.599 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.284 ns| 3 - | | | -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.492 ns| 3 - | | | -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2 - | | | -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.363 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.236 ns| 2 - | | | -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.232 ns| 2 - | | | -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.443 ns| 3 - | | | -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | | -CLKPORT "RCLK" ; | 0.000 ns| 2.713 ns| 3 - | | | -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | | -CLKPORT "RCLK" ; | -| -| 0 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 4 clocks: - -Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 - No transfer within this clock domain is found - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 - No transfer within this clock domain is found - -Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39 - Covered under: PERIOD NET "RCLK_c" 16.000000 ns ; - - Data transfers from: - Clock Domain: nCRAS_c Source: nCRAS.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - Clock Domain: PHI2_c Source: PHI2.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - -Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 - Covered under: PERIOD NET "PHI2_c" 350.000000 ns ; - - Data transfers from: - Clock Domain: RCLK_c Source: RCLK.PAD - Not reported because source and destination domains are unrelated. - To report these transfers please refer to preference CLKSKEWDIFF to define - external clock skew between clock ports. - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 0 (setup), 0 (hold) -Score: 0 (setup), 0 (hold) -Cumulative negative slack: 0 (0+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html deleted file mode 100644 index 0fd44c9..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html +++ /dev/null @@ -1,111 +0,0 @@ - -Bitgen Report - - - - - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html deleted file mode 100644 index 61370c6..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html +++ /dev/null @@ -1,202 +0,0 @@ - -I/O Timing Report - - -
I/O Timing Report
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 4
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-// Design: RAM2GS
-// Package: TQFP100
-// ncd File: ram2gs_lcmxo256c_impl1.ncd
-// Version: Diamond (64-bit) 3.12.0.240.2
-// Written on Mon Aug 16 21:32:34 2021
-// M: Minimum Performance Grade
-// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 5, 4, 3):
-
-// Input Setup and Hold Times
-
-Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-CROW[0] nCRAS F     0.215      3       1.805     3
-CROW[1] nCRAS F    -0.050      M       2.105     3
-Din[0]  PHI2  F     5.083      3       2.097     3
-Din[0]  nCCAS F    -0.020      M       2.133     3
-Din[1]  PHI2  F     3.519      3       2.454     3
-Din[1]  nCCAS F    -0.146      M       2.462     3
-Din[2]  PHI2  F     4.416      3       2.660     3
-Din[2]  nCCAS F     0.272      3       1.853     3
-Din[3]  PHI2  F     5.627      3       2.084     3
-Din[3]  nCCAS F    -0.024      M       2.144     3
-Din[4]  PHI2  F     4.808      3       2.117     3
-Din[4]  nCCAS F     0.350      3       1.766     3
-Din[5]  PHI2  F     5.446      3       2.212     3
-Din[5]  nCCAS F     0.435      3       1.708     3
-Din[6]  PHI2  F     5.339      3       1.487     3
-Din[6]  nCCAS F    -0.140      M       2.452     3
-Din[7]  PHI2  F     4.546      3       1.555     3
-Din[7]  nCCAS F    -0.016      M       2.122     3
-MAin[0] PHI2  F     4.027      3       0.711     3
-MAin[0] nCRAS F     1.132      3       0.987     3
-MAin[1] PHI2  F     4.032      3       1.734     3
-MAin[1] nCRAS F     0.704      3       1.373     3
-MAin[2] PHI2  F    10.358      3      -0.773     M
-MAin[2] nCRAS F    -0.202      M       2.529     3
-MAin[3] PHI2  F    10.442      3      -0.829     M
-MAin[3] nCRAS F     0.186      3       1.819     3
-MAin[4] PHI2  F    10.311      3      -0.765     M
-MAin[4] nCRAS F     0.569      3       1.506     3
-MAin[5] PHI2  F     7.007      3       0.178     3
-MAin[5] nCRAS F     0.186      3       1.819     3
-MAin[6] PHI2  F     9.786      3      -0.641     M
-MAin[6] nCRAS F     0.177      3       1.829     3
-MAin[7] PHI2  F    10.008      3      -0.718     M
-MAin[7] nCRAS F    -0.092      M       2.222     3
-MAin[8] nCRAS F    -0.202      M       2.532     3
-MAin[9] nCRAS F     0.228      3       1.797     3
-PHI2    RCLK  R     5.091      3      -0.759     M
-UFMSDO  RCLK  R     2.219      3      -0.104     M
-nCCAS   RCLK  R     3.820      3      -0.611     M
-nCCAS   nCRAS F     1.538      3       0.708     3
-nCRAS   RCLK  R     4.749      3      -0.670     M
-nFWE    PHI2  F     5.301      3       1.647     3
-nFWE    nCRAS F     1.049      3       1.128     3
-
-
-// Clock to Output Delay
-
-Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-LED    RCLK  R    11.669         3        3.051          M
-RA[0]  RCLK  R     9.674         3        2.492          M
-RA[0]  nCRAS F    12.127         3        3.067          M
-RA[10] RCLK  R     8.596         3        2.220          M
-RA[11] PHI2  R     9.987         3        2.559          M
-RA[1]  RCLK  R     8.766         3        2.284          M
-RA[1]  nCRAS F    11.652         3        2.982          M
-RA[2]  RCLK  R    10.062         3        2.599          M
-RA[2]  nCRAS F    12.947         3        3.306          M
-RA[3]  RCLK  R     9.933         3        2.555          M
-RA[3]  nCRAS F    12.783         3        3.240          M
-RA[4]  RCLK  R     8.504         3        2.219          M
-RA[4]  nCRAS F    11.513         3        2.948          M
-RA[5]  RCLK  R     9.609         3        2.481          M
-RA[5]  nCRAS F    11.870         3        3.010          M
-RA[6]  RCLK  R    10.001         3        2.579          M
-RA[6]  nCRAS F    12.947         3        3.292          M
-RA[7]  RCLK  R    10.255         3        2.652          M
-RA[7]  nCRAS F    12.177         3        3.089          M
-RA[8]  RCLK  R     8.896         3        2.316          M
-RA[8]  nCRAS F    11.417         3        2.920          M
-RA[9]  RCLK  R     8.766         3        2.284          M
-RA[9]  nCRAS F    11.617         3        2.957          M
-RBA[0] nCRAS F     9.698         3        2.483          M
-RBA[1] nCRAS F    11.425         3        2.916          M
-RCKE   RCLK  R     9.080         3        2.363          M
-RDQMH  RCLK  R     9.475         3        2.443          M
-RDQML  RCLK  R    10.477         3        2.713          M
-RD[0]  nCCAS F    11.252         3        2.942          M
-RD[1]  nCCAS F    11.963         3        3.100          M
-RD[2]  nCCAS F    12.880         3        3.336          M
-RD[3]  nCCAS F    12.422         3        3.224          M
-RD[4]  nCCAS F    11.252         3        2.942          M
-RD[5]  nCCAS F    12.423         3        3.212          M
-RD[6]  nCCAS F    12.979         3        3.375          M
-RD[7]  nCCAS F    12.914         3        3.350          M
-UFMCLK RCLK  R     8.007         3        2.126          M
-UFMSDI RCLK  R     8.007         3        2.126          M
-nRCAS  RCLK  R     8.595         3        2.232          M
-nRCS   RCLK  R     7.429         3        1.949          M
-nRRAS  RCLK  R     8.615         3        2.236          M
-nRWE   RCLK  R     7.429         3        1.949          M
-nUFMCS RCLK  R     9.193         3        2.413          M
-WARNING: you must also run trce with hold speed: 3
-WARNING: you must also run trce with setup speed: M
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- - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj deleted file mode 100644 index a0fe340..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj +++ /dev/null @@ -1,41 +0,0 @@ --a "MachXO" --d LCMXO256C --t TQFP100 --s 3 --frequency 200 --optimization_goal Balanced --bram_utilization 100 --ramstyle Auto --romstyle auto --dsp_utilization 100 --use_dsp 1 --use_carry_chain 1 --carry_chain_length 0 --force_gsr Auto --resource_sharing 1 --propagate_constants 1 --remove_duplicate_regs 1 --mux_style Auto --max_fanout 1000 --fsm_encoding_style Auto --twr_paths 3 --fix_gated_clocks 1 --loop_limit 1950 - - - --use_io_insertion 1 --resolve_mixed_drivers 0 --use_io_reg auto - - --lpf 1 --p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C" --ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v" --top RAM2GS - - --p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C" - --ngd "RAM2GS_LCMXO256C_impl1.ngd" - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd deleted file mode 100644 index c70636c..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd +++ /dev/null @@ -1,13 +0,0 @@ -[ActiveSupport MAP] -Device = LCMXO256C; -Package = TQFP100; -Performance = 3; -LUTS_avail = 256; -LUTS_used = 129; -FF_avail = 256; -FF_used = 102; -INPUT_LVTTL33 = 26; -OUTPUT_LVTTL33 = 33; -BIDI_LVTTL33 = 8; -IO_avail = 78; -IO_used = 67; diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam deleted file mode 100644 index 816529f..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam +++ /dev/null @@ -1,108 +0,0 @@ -[ START MERGED ] -nCRAS_N_9 nCRAS_c -nCCAS_N_3 nCCAS_c -n2307 Ready -n2306 nFWE_c -PHI2_N_114 PHI2_c -n2302 nRowColSel_N_35 -nRWE_N_172 nRWE_N_173 -UFMSDO_N_74 UFMSDO_c -n1377 nRowColSel_N_34 -RASr2_N_63 RASr2 -[ END MERGED ] -[ START CLIPPED ] -GND_net -VCC_net -FS_577_add_4_14/CO0 -FS_577_add_4_16/CO0 -FS_577_add_4_12/CO0 -FS_577_add_4_2/CO0 -FS_577_add_4_4/CO0 -FS_577_add_4_6/CO0 -FS_577_add_4_18/CO1 -FS_577_add_4_18/CO0 -FS_577_add_4_8/CO0 -FS_577_add_4_10/CO0 -[ END CLIPPED ] -[ START DESIGN PREFS ] -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:32:26 2021 - -SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; -LOCATE COMP "RD[7]" SITE "71" ; -LOCATE COMP "RD[6]" SITE "70" ; -LOCATE COMP "RD[5]" SITE "69" ; -LOCATE COMP "RD[4]" SITE "68" ; -LOCATE COMP "RD[3]" SITE "67" ; -LOCATE COMP "RD[2]" SITE "66" ; -LOCATE COMP "RD[1]" SITE "65" ; -LOCATE COMP "RD[0]" SITE "64" ; -LOCATE COMP "Dout[7]" SITE "3" ; -LOCATE COMP "Dout[6]" SITE "2" ; -LOCATE COMP "Dout[5]" SITE "5" ; -LOCATE COMP "Dout[4]" SITE "4" ; -LOCATE COMP "Dout[3]" SITE "6" ; -LOCATE COMP "Dout[2]" SITE "8" ; -LOCATE COMP "Dout[1]" SITE "7" ; -LOCATE COMP "Dout[0]" SITE "1" ; -LOCATE COMP "LED" SITE "57" ; -LOCATE COMP "RBA[1]" SITE "83" ; -LOCATE COMP "RBA[0]" SITE "63" ; -LOCATE COMP "RA[11]" SITE "79" ; -LOCATE COMP "RA[10]" SITE "87" ; -LOCATE COMP "RA[9]" SITE "85" ; -LOCATE COMP "RA[8]" SITE "96" ; -LOCATE COMP "RA[7]" SITE "100" ; -LOCATE COMP "RA[6]" SITE "91" ; -LOCATE COMP "RA[5]" SITE "95" ; -LOCATE COMP "RA[4]" SITE "99" ; -LOCATE COMP "RA[3]" SITE "97" ; -LOCATE COMP "RA[2]" SITE "94" ; -LOCATE COMP "RA[1]" SITE "89" ; -LOCATE COMP "RA[0]" SITE "98" ; -LOCATE COMP "nRCS" SITE "77" ; -LOCATE COMP "RCKE" SITE "82" ; -LOCATE COMP "nRWE" SITE "72" ; -LOCATE COMP "nRRAS" SITE "73" ; -LOCATE COMP "nRCAS" SITE "78" ; -LOCATE COMP "RDQMH" SITE "76" ; -LOCATE COMP "RDQML" SITE "61" ; -LOCATE COMP "nUFMCS" SITE "53" ; -LOCATE COMP "UFMCLK" SITE "58" ; -LOCATE COMP "UFMSDI" SITE "56" ; -LOCATE COMP "PHI2" SITE "39" ; -LOCATE COMP "MAin[9]" SITE "51" ; -LOCATE COMP "MAin[8]" SITE "50" ; -LOCATE COMP "MAin[7]" SITE "44" ; -LOCATE COMP "MAin[6]" SITE "49" ; -LOCATE COMP "MAin[5]" SITE "45" ; -LOCATE COMP "MAin[4]" SITE "46" ; -LOCATE COMP "MAin[3]" SITE "47" ; -LOCATE COMP "MAin[2]" SITE "37" ; -LOCATE COMP "MAin[1]" SITE "38" ; -LOCATE COMP "MAin[0]" SITE "23" ; -LOCATE COMP "CROW[1]" SITE "34" ; -LOCATE COMP "CROW[0]" SITE "32" ; -LOCATE COMP "Din[7]" SITE "19" ; -LOCATE COMP "Din[6]" SITE "20" ; -LOCATE COMP "Din[5]" SITE "17" ; -LOCATE COMP "Din[4]" SITE "18" ; -LOCATE COMP "Din[3]" SITE "16" ; -LOCATE COMP "Din[2]" SITE "14" ; -LOCATE COMP "Din[1]" SITE "15" ; -LOCATE COMP "Din[0]" SITE "21" ; -LOCATE COMP "nCCAS" SITE "27" ; -LOCATE COMP "nCRAS" SITE "43" ; -LOCATE COMP "nFWE" SITE "22" ; -LOCATE COMP "RCLK" SITE "86" ; -LOCATE COMP "UFMSDO" SITE "55" ; -PERIOD NET "PHI2_c" 350.000000 ns ; -USE PRIMARY NET "RCLK_c" ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -USE PRIMARY NET "PHI2_c" ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -USE PRIMARY NET "nCCAS_c" ; -PERIOD NET "RCLK_c" 16.000000 ns ; -USE PRIMARY NET "nCRAS_c" ; -SCHEMATIC END ; -[ END DESIGN PREFS ] diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr deleted file mode 100644 index 5a900d5..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr +++ /dev/null @@ -1,10 +0,0 @@ ---------------------------------------------------- -Report for cell RAM2GS - Instance path: RAM2GS - Cell usage: - cell count Res Usage(%) - SLIC 65.00 100.0 - LUT4 111.00 100.0 - IOBUF 67 100.0 - PFUREG 102 100.0 - RIPPLE 9 100.0 diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd deleted file mode 100644 index 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-            Lattice Mapping Report File for Design Module 'RAM2GS'
-
-
-
-Design Information
-
-Command line:   map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial
-     RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
-     RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf C:/Users/Dog
-     /Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.
-     lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_L
-     CMXO256C.lpf -c 0 -gui -msgset
-     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml 
-Target Vendor:  LATTICE
-Target Device:  LCMXO256CTQFP100
-Target Performance:   3
-Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.0.240.2
-Mapped on:  08/16/21  21:32:26
-
-
-Design Summary
-   Number of PFU registers:   102 out of   256 (40%)
-   Number of SLICEs:        65 out of   128 (51%)
-      SLICEs as Logic/ROM:     65 out of   128 (51%)
-      SLICEs as RAM:            0 out of    64 (0%)
-      SLICEs as Carry:          9 out of   128 (7%)
-   Number of LUT4s:        129 out of   256 (50%)
-      Number used as logic LUTs:        111
-      Number used as distributed RAM:     0
-      Number used as ripple logic:       18
-      Number used as shift registers:     0
-   Number of external PIOs: 67 out of 78 (86%)
-   Number of GSRs:  0 out of 1 (0%)
-   JTAG used :      No
-   Readback used :  No
-   Oscillator used :  No
-   Startup used :   No
-   Number of TSALL: 0 out of 1 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
-     distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and
-     ripple logic.
-   Number of clocks:  4
-     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
-     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
-     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
-     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
-   Number of Clock Enables:  13
-     Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
-     Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
-     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
-     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
-     Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
-     Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
-     Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
-     Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
-
-     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
-     Net Ready_N_268: 1 loads, 1 LSLICEs
-   Number of LSRs:  9
-     Net RASr2: 1 loads, 1 LSLICEs
-     Net C1Submitted_N_225: 2 loads, 2 LSLICEs
-     Net n2299: 1 loads, 1 LSLICEs
-     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
-     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
-     Net LEDEN_N_88: 1 loads, 1 LSLICEs
-     Net n2291: 2 loads, 2 LSLICEs
-     Net Ready: 7 loads, 7 LSLICEs
-     Net nRWE_N_173: 1 loads, 1 LSLICEs
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net Ready: 19 loads
-     Net InitReady: 17 loads
-     Net RASr2: 16 loads
-     Net nRowColSel_N_35: 14 loads
-     Net nRowColSel: 13 loads
-     Net Din_c_6: 9 loads
-     Net MAin_c_1: 9 loads
-     Net Din_c_5: 8 loads
-     Net FS_11: 8 loads
-     Net MAin_c_0: 8 loads
-
-
-
-
-   Number of warnings:  0
-   Number of errors:    0
-     
-
-
-
-
-Design Errors/Warnings
-
-   No errors or warnings present.
-
-
-
-IO (PIO) Attributes
-
-+---------------------+-----------+-----------+------------+------------+
-| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
-|                     |           |  IO_TYPE  | Register   |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[7]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[6]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[5]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[4]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[3]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[2]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-| RD[1]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[0]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[7]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[6]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[5]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[4]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[3]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[2]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[1]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[0]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| LED                 | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RBA[1]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RBA[0]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[11]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[10]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[9]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[8]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[7]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[6]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[5]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[4]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[3]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[2]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[1]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[0]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRCS                | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RCKE                | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRWE                | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-| nRRAS               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRCAS               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RDQMH               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RDQML               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nUFMCS              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMCLK              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMSDI              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| PHI2                | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[9]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[8]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[7]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[6]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[5]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[4]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[3]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[2]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[1]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[0]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| CROW[1]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| CROW[0]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[7]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[6]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[5]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[4]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[3]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[2]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[1]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[0]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-| nCCAS               | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nCRAS               | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nFWE                | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RCLK                | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMSDO              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-
-
-Removed logic
-
-Block i2 undriven or does not drive anything - clipped.
-Block GSR_INST undriven or does not drive anything - clipped.
-Signal PHI2_N_114 was merged into signal PHI2_c
-Signal nCRAS_N_9 was merged into signal nCRAS_c
-Signal nCCAS_N_3 was merged into signal nCCAS_c
-Signal n2302 was merged into signal nRowColSel_N_35
-Signal nRWE_N_172 was merged into signal nRWE_N_173
-Signal n2307 was merged into signal Ready
-Signal RASr2_N_63 was merged into signal RASr2
-Signal n1377 was merged into signal nRowColSel_N_34
-Signal n2306 was merged into signal nFWE_c
-Signal UFMSDO_N_74 was merged into signal UFMSDO_c
-Signal GND_net undriven or does not drive anything - clipped.
-Signal VCC_net undriven or does not drive anything - clipped.
-Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
-Block i1962 was optimized away.
-Block i1961 was optimized away.
-Block i1963 was optimized away.
-Block i1070_1_lut_rep_25 was optimized away.
-Block nRWE_I_49_1_lut was optimized away.
-Block i604_1_lut_rep_30 was optimized away.
-Block RASr2_I_0_1_lut was optimized away.
-Block i1069_1_lut was optimized away.
-Block i1_1_lut_rep_29 was optimized away.
-Block UFMSDO_I_0_1_lut was optimized away.
-Block i1 was optimized away.
-
-
-
-Run Time and Memory Usage
--------------------------
-
-   Total CPU Time: 0 secs  
-   Total REAL Time: 0 secs  
-   Peak Memory Usage: 29 MB
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-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-     Copyright (c) 1995 AT&T Corp.   All rights reserved.
-     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-     Copyright (c) 2001 Agere Systems   All rights reserved.
-     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
-     reserved.
-
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- - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html deleted file mode 100644 index 911c6d4..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html +++ /dev/null @@ -1,336 +0,0 @@ - -PAD Specification File - - -
PAD Specification File
-***************************
-
-PART TYPE:        LCMXO256C
-Performance Grade:      3
-PACKAGE:          TQFP100
-Package Status:                     Final          Version 1.19
-
-Mon Aug 16 21:32:33 2021
-
-Pinout by Port Name:
-+-----------+----------+--------------+------+----------------------------------+
-| Port Name | Pin/Bank | Buffer Type  | Site | Properties                       |
-+-----------+----------+--------------+------+----------------------------------+
-| CROW[0]   | 32/1     | LVTTL33_IN   | PB2C | SLEW:FAST                        |
-| CROW[1]   | 34/1     | LVTTL33_IN   | PB2D | SLEW:FAST                        |
-| Din[0]    | 21/1     | LVTTL33_IN   | PL8A | SLEW:FAST                        |
-| Din[1]    | 15/1     | LVTTL33_IN   | PL6A | SLEW:FAST                        |
-| Din[2]    | 14/1     | LVTTL33_IN   | PL5D | SLEW:FAST                        |
-| Din[3]    | 16/1     | LVTTL33_IN   | PL6B | SLEW:FAST                        |
-| Din[4]    | 18/1     | LVTTL33_IN   | PL7B | SLEW:FAST                        |
-| Din[5]    | 17/1     | LVTTL33_IN   | PL7A | SLEW:FAST                        |
-| Din[6]    | 20/1     | LVTTL33_IN   | PL7D | SLEW:FAST                        |
-| Din[7]    | 19/1     | LVTTL33_IN   | PL7C | SLEW:FAST                        |
-| Dout[0]   | 1/1      | LVTTL33_OUT  | PL2A | DRIVE:4mA SLEW:SLOW              |
-| Dout[1]   | 7/1      | LVTTL33_OUT  | PL4A | DRIVE:4mA SLEW:SLOW              |
-| Dout[2]   | 8/1      | LVTTL33_OUT  | PL4B | DRIVE:4mA SLEW:SLOW              |
-| Dout[3]   | 6/1      | LVTTL33_OUT  | PL3D | DRIVE:4mA SLEW:SLOW              |
-| Dout[4]   | 4/1      | LVTTL33_OUT  | PL3B | DRIVE:4mA SLEW:SLOW              |
-| Dout[5]   | 5/1      | LVTTL33_OUT  | PL3C | DRIVE:4mA SLEW:SLOW              |
-| Dout[6]   | 2/1      | LVTTL33_OUT  | PL2B | DRIVE:4mA SLEW:SLOW              |
-| Dout[7]   | 3/1      | LVTTL33_OUT  | PL3A | DRIVE:4mA SLEW:SLOW              |
-| LED       | 57/0     | LVTTL33_OUT  | PR7B | DRIVE:16mA SLEW:SLOW             |
-| MAin[0]   | 23/1     | LVTTL33_IN   | PL9A | SLEW:FAST                        |
-| MAin[1]   | 38/1     | LVTTL33_IN   | PB3C | SLEW:FAST                        |
-| MAin[2]   | 37/1     | LVTTL33_IN   | PB3B | SLEW:FAST                        |
-| MAin[3]   | 47/1     | LVTTL33_IN   | PB5A | SLEW:FAST                        |
-| MAin[4]   | 46/1     | LVTTL33_IN   | PB4D | SLEW:FAST                        |
-| MAin[5]   | 45/1     | LVTTL33_IN   | PB4C | SLEW:FAST                        |
-| MAin[6]   | 49/1     | LVTTL33_IN   | PB5C | SLEW:FAST                        |
-| MAin[7]   | 44/1     | LVTTL33_IN   | PB4B | SLEW:FAST                        |
-| MAin[8]   | 50/1     | LVTTL33_IN   | PB5D | SLEW:FAST                        |
-| MAin[9]   | 51/0     | LVTTL33_IN   | PR9B | SLEW:FAST                        |
-| PHI2      | 39/1     | LVTTL33_IN   | PB3D | SLEW:FAST                        |
-| RA[0]     | 98/0     | LVTTL33_OUT  | PT2C | DRIVE:4mA SLEW:SLOW              |
-| RA[10]    | 87/0     | LVTTL33_OUT  | PT3D | DRIVE:4mA SLEW:SLOW              |
-| RA[11]    | 79/0     | LVTTL33_OUT  | PT5A | DRIVE:4mA SLEW:SLOW              |
-| RA[1]     | 89/0     | LVTTL33_OUT  | PT3C | DRIVE:4mA SLEW:SLOW              |
-| RA[2]     | 94/0     | LVTTL33_OUT  | PT3A | DRIVE:4mA SLEW:SLOW              |
-| RA[3]     | 97/0     | LVTTL33_OUT  | PT2D | DRIVE:4mA SLEW:SLOW              |
-| RA[4]     | 99/0     | LVTTL33_OUT  | PT2B | DRIVE:4mA SLEW:SLOW              |
-| RA[5]     | 95/0     | LVTTL33_OUT  | PT2F | DRIVE:4mA SLEW:SLOW              |
-| RA[6]     | 91/0     | LVTTL33_OUT  | PT3B | DRIVE:4mA SLEW:SLOW              |
-| RA[7]     | 100/0    | LVTTL33_OUT  | PT2A | DRIVE:4mA SLEW:SLOW              |
-| RA[8]     | 96/0     | LVTTL33_OUT  | PT2E | DRIVE:4mA SLEW:SLOW              |
-| RA[9]     | 85/0     | LVTTL33_OUT  | PT4B | DRIVE:4mA SLEW:SLOW              |
-| RBA[0]    | 63/0     | LVTTL33_OUT  | PR5D | DRIVE:4mA SLEW:SLOW              |
-| RBA[1]    | 83/0     | LVTTL33_OUT  | PT4C | DRIVE:4mA SLEW:SLOW              |
-| RCKE      | 82/0     | LVTTL33_OUT  | PT4D | DRIVE:4mA SLEW:SLOW              |
-| RCLK      | 86/0     | LVTTL33_IN   | PT4A | SLEW:FAST                        |
-| RDQMH     | 76/0     | LVTTL33_OUT  | PR2A | DRIVE:4mA SLEW:SLOW              |
-| RDQML     | 61/0     | LVTTL33_OUT  | PR6A | DRIVE:4mA SLEW:SLOW              |
-| RD[0]     | 64/0     | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[1]     | 65/0     | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[2]     | 66/0     | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[3]     | 67/0     | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[4]     | 68/0     | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[5]     | 69/0     | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[6]     | 70/0     | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[7]     | 71/0     | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| UFMCLK    | 58/0     | LVTTL33_OUT  | PR7A | DRIVE:4mA SLEW:SLOW              |
-| UFMSDI    | 56/0     | LVTTL33_OUT  | PR7C | DRIVE:4mA SLEW:SLOW              |
-| UFMSDO    | 55/0     | LVTTL33_IN   | PR7D | SLEW:FAST PULL:KEEPER            |
-| nCCAS     | 27/1     | LVTTL33_IN   | PL9B | SLEW:FAST                        |
-| nCRAS     | 43/1     | LVTTL33_IN   | PB4A | SLEW:FAST                        |
-| nFWE      | 22/1     | LVTTL33_IN   | PL8B | SLEW:FAST                        |
-| nRCAS     | 78/0     | LVTTL33_OUT  | PT5B | DRIVE:4mA SLEW:SLOW              |
-| nRCS      | 77/0     | LVTTL33_OUT  | PT5C | DRIVE:4mA SLEW:SLOW              |
-| nRRAS     | 73/0     | LVTTL33_OUT  | PR2B | DRIVE:4mA SLEW:SLOW              |
-| nRWE      | 72/0     | LVTTL33_OUT  | PR3A | DRIVE:4mA SLEW:SLOW              |
-| nUFMCS    | 53/0     | LVTTL33_OUT  | PR8B | DRIVE:4mA SLEW:SLOW              |
-+-----------+----------+--------------+------+----------------------------------+
-
-Vccio by Bank:
-+------+-------+
-| Bank | Vccio |
-+------+-------+
-| 0    | 3.3V  |
-| 1    | 3.3V  |
-+------+-------+
-
-
-Vref by Bank:
-+------+-----+-----------------+---------+
-| Vref | Pin | Bank # / Vref # | Load(s) |
-+------+-----+-----------------+---------+
-+------+-----+-----------------+---------+
-
-Pinout by Pin Number:
-+----------+---------------------+------------+--------------+------+---------------+
-| Pin/Bank | Pin Info            | Preference | Buffer Type  | Site | Dual Function |
-+----------+---------------------+------------+--------------+------+---------------+
-| 1/1      | Dout[0]             | LOCATED    | LVTTL33_OUT  | PL2A |               |
-| 2/1      | Dout[6]             | LOCATED    | LVTTL33_OUT  | PL2B |               |
-| 3/1      | Dout[7]             | LOCATED    | LVTTL33_OUT  | PL3A |               |
-| 4/1      | Dout[4]             | LOCATED    | LVTTL33_OUT  | PL3B |               |
-| 5/1      | Dout[5]             | LOCATED    | LVTTL33_OUT  | PL3C |               |
-| 6/1      | Dout[3]             | LOCATED    | LVTTL33_OUT  | PL3D |               |
-| 7/1      | Dout[1]             | LOCATED    | LVTTL33_OUT  | PL4A |               |
-| 8/1      | Dout[2]             | LOCATED    | LVTTL33_OUT  | PL4B |               |
-| 9/1      |     unused, PULL:UP |            |              | PL5A |               |
-| 11/1     |     unused, PULL:UP |            |              | PL5B |               |
-| 13/1     |     unused, PULL:UP |            |              | PL5C |               |
-| 14/1     | Din[2]              | LOCATED    | LVTTL33_IN   | PL5D | GSR_PADN      |
-| 15/1     | Din[1]              | LOCATED    | LVTTL33_IN   | PL6A |               |
-| 16/1     | Din[3]              | LOCATED    | LVTTL33_IN   | PL6B | TSALLPAD      |
-| 17/1     | Din[5]              | LOCATED    | LVTTL33_IN   | PL7A |               |
-| 18/1     | Din[4]              | LOCATED    | LVTTL33_IN   | PL7B |               |
-| 19/1     | Din[7]              | LOCATED    | LVTTL33_IN   | PL7C |               |
-| 20/1     | Din[6]              | LOCATED    | LVTTL33_IN   | PL7D |               |
-| 21/1     | Din[0]              | LOCATED    | LVTTL33_IN   | PL8A |               |
-| 22/1     | nFWE                | LOCATED    | LVTTL33_IN   | PL8B |               |
-| 23/1     | MAin[0]             | LOCATED    | LVTTL33_IN   | PL9A |               |
-| 27/1     | nCCAS               | LOCATED    | LVTTL33_IN   | PL9B |               |
-| 29/1     |     unused, PULL:UP |            |              | PB2A |               |
-| 30/1     |     unused, PULL:UP |            |              | PB2B |               |
-| 32/1     | CROW[0]             | LOCATED    | LVTTL33_IN   | PB2C |               |
-| 34/1     | CROW[1]             | LOCATED    | LVTTL33_IN   | PB2D |               |
-| 36/1     |     unused, PULL:UP |            |              | PB3A | PCLKT1_1      |
-| 37/1     | MAin[2]             | LOCATED    | LVTTL33_IN   | PB3B |               |
-| 38/1     | MAin[1]             | LOCATED    | LVTTL33_IN   | PB3C | PCLKT1_0      |
-| 39/1     | PHI2                | LOCATED    | LVTTL33_IN   | PB3D |               |
-| 43/1     | nCRAS               | LOCATED    | LVTTL33_IN   | PB4A |               |
-| 44/1     | MAin[7]             | LOCATED    | LVTTL33_IN   | PB4B |               |
-| 45/1     | MAin[5]             | LOCATED    | LVTTL33_IN   | PB4C |               |
-| 46/1     | MAin[4]             | LOCATED    | LVTTL33_IN   | PB4D |               |
-| 47/1     | MAin[3]             | LOCATED    | LVTTL33_IN   | PB5A |               |
-| 49/1     | MAin[6]             | LOCATED    | LVTTL33_IN   | PB5C |               |
-| 50/1     | MAin[8]             | LOCATED    | LVTTL33_IN   | PB5D |               |
-| 51/0     | MAin[9]             | LOCATED    | LVTTL33_IN   | PR9B |               |
-| 52/0     |     unused, PULL:UP |            |              | PR9A |               |
-| 53/0     | nUFMCS              | LOCATED    | LVTTL33_OUT  | PR8B |               |
-| 54/0     |     unused, PULL:UP |            |              | PR8A |               |
-| 55/0     | UFMSDO              | LOCATED    | LVTTL33_IN   | PR7D |               |
-| 56/0     | UFMSDI              | LOCATED    | LVTTL33_OUT  | PR7C |               |
-| 57/0     | LED                 | LOCATED    | LVTTL33_OUT  | PR7B |               |
-| 58/0     | UFMCLK              | LOCATED    | LVTTL33_OUT  | PR7A |               |
-| 59/0     |     unused, PULL:UP |            |              | PR6B |               |
-| 61/0     | RDQML               | LOCATED    | LVTTL33_OUT  | PR6A |               |
-| 63/0     | RBA[0]              | LOCATED    | LVTTL33_OUT  | PR5D |               |
-| 64/0     | RD[0]               | LOCATED    | LVTTL33_BIDI | PR5C |               |
-| 65/0     | RD[1]               | LOCATED    | LVTTL33_BIDI | PR5B |               |
-| 66/0     | RD[2]               | LOCATED    | LVTTL33_BIDI | PR5A |               |
-| 67/0     | RD[3]               | LOCATED    | LVTTL33_BIDI | PR4B |               |
-| 68/0     | RD[4]               | LOCATED    | LVTTL33_BIDI | PR4A |               |
-| 69/0     | RD[5]               | LOCATED    | LVTTL33_BIDI | PR3D |               |
-| 70/0     | RD[6]               | LOCATED    | LVTTL33_BIDI | PR3C |               |
-| 71/0     | RD[7]               | LOCATED    | LVTTL33_BIDI | PR3B |               |
-| 72/0     | nRWE                | LOCATED    | LVTTL33_OUT  | PR3A |               |
-| 73/0     | nRRAS               | LOCATED    | LVTTL33_OUT  | PR2B |               |
-| 76/0     | RDQMH               | LOCATED    | LVTTL33_OUT  | PR2A |               |
-| 77/0     | nRCS                | LOCATED    | LVTTL33_OUT  | PT5C |               |
-| 78/0     | nRCAS               | LOCATED    | LVTTL33_OUT  | PT5B |               |
-| 79/0     | RA[11]              | LOCATED    | LVTTL33_OUT  | PT5A |               |
-| 80/0     |     unused, PULL:UP |            |              | PT4F |               |
-| 81/0     |     unused, PULL:UP |            |              | PT4E |               |
-| 82/0     | RCKE                | LOCATED    | LVTTL33_OUT  | PT4D |               |
-| 83/0     | RBA[1]              | LOCATED    | LVTTL33_OUT  | PT4C |               |
-| 85/0     | RA[9]               | LOCATED    | LVTTL33_OUT  | PT4B | PCLKT0_1      |
-| 86/0     | RCLK                | LOCATED    | LVTTL33_IN   | PT4A | PCLKT0_0      |
-| 87/0     | RA[10]              | LOCATED    | LVTTL33_OUT  | PT3D |               |
-| 89/0     | RA[1]               | LOCATED    | LVTTL33_OUT  | PT3C |               |
-| 91/0     | RA[6]               | LOCATED    | LVTTL33_OUT  | PT3B |               |
-| 94/0     | RA[2]               | LOCATED    | LVTTL33_OUT  | PT3A |               |
-| 95/0     | RA[5]               | LOCATED    | LVTTL33_OUT  | PT2F |               |
-| 96/0     | RA[8]               | LOCATED    | LVTTL33_OUT  | PT2E |               |
-| 97/0     | RA[3]               | LOCATED    | LVTTL33_OUT  | PT2D |               |
-| 98/0     | RA[0]               | LOCATED    | LVTTL33_OUT  | PT2C |               |
-| 99/0     | RA[4]               | LOCATED    | LVTTL33_OUT  | PT2B |               |
-| 100/0    | RA[7]               | LOCATED    | LVTTL33_OUT  | PT2A |               |
-| PB5B/0   |     unused, PULL:UP |            |              | PB5B |               |
-| PT5D/0   |     unused, PULL:UP |            |              | PT5D |               |
-| TCK/1    |                     |            |              | TCK  | TCK           |
-| TDI/1    |                     |            |              | TDI  | TDI           |
-| TDO/1    |                     |            |              | TDO  | TDO           |
-| TMS/1    |                     |            |              | TMS  | TMS           |
-+----------+---------------------+------------+--------------+------+---------------+
-
-
-List of All Pins' Locate Preferences Based on Final Placement After PAR 
-to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
-
-LOCATE  COMP  "CROW[0]"  SITE  "32";
-LOCATE  COMP  "CROW[1]"  SITE  "34";
-LOCATE  COMP  "Din[0]"  SITE  "21";
-LOCATE  COMP  "Din[1]"  SITE  "15";
-LOCATE  COMP  "Din[2]"  SITE  "14";
-LOCATE  COMP  "Din[3]"  SITE  "16";
-LOCATE  COMP  "Din[4]"  SITE  "18";
-LOCATE  COMP  "Din[5]"  SITE  "17";
-LOCATE  COMP  "Din[6]"  SITE  "20";
-LOCATE  COMP  "Din[7]"  SITE  "19";
-LOCATE  COMP  "Dout[0]"  SITE  "1";
-LOCATE  COMP  "Dout[1]"  SITE  "7";
-LOCATE  COMP  "Dout[2]"  SITE  "8";
-LOCATE  COMP  "Dout[3]"  SITE  "6";
-LOCATE  COMP  "Dout[4]"  SITE  "4";
-LOCATE  COMP  "Dout[5]"  SITE  "5";
-LOCATE  COMP  "Dout[6]"  SITE  "2";
-LOCATE  COMP  "Dout[7]"  SITE  "3";
-LOCATE  COMP  "LED"  SITE  "57";
-LOCATE  COMP  "MAin[0]"  SITE  "23";
-LOCATE  COMP  "MAin[1]"  SITE  "38";
-LOCATE  COMP  "MAin[2]"  SITE  "37";
-LOCATE  COMP  "MAin[3]"  SITE  "47";
-LOCATE  COMP  "MAin[4]"  SITE  "46";
-LOCATE  COMP  "MAin[5]"  SITE  "45";
-LOCATE  COMP  "MAin[6]"  SITE  "49";
-LOCATE  COMP  "MAin[7]"  SITE  "44";
-LOCATE  COMP  "MAin[8]"  SITE  "50";
-LOCATE  COMP  "MAin[9]"  SITE  "51";
-LOCATE  COMP  "PHI2"  SITE  "39";
-LOCATE  COMP  "RA[0]"  SITE  "98";
-LOCATE  COMP  "RA[10]"  SITE  "87";
-LOCATE  COMP  "RA[11]"  SITE  "79";
-LOCATE  COMP  "RA[1]"  SITE  "89";
-LOCATE  COMP  "RA[2]"  SITE  "94";
-LOCATE  COMP  "RA[3]"  SITE  "97";
-LOCATE  COMP  "RA[4]"  SITE  "99";
-LOCATE  COMP  "RA[5]"  SITE  "95";
-LOCATE  COMP  "RA[6]"  SITE  "91";
-LOCATE  COMP  "RA[7]"  SITE  "100";
-LOCATE  COMP  "RA[8]"  SITE  "96";
-LOCATE  COMP  "RA[9]"  SITE  "85";
-LOCATE  COMP  "RBA[0]"  SITE  "63";
-LOCATE  COMP  "RBA[1]"  SITE  "83";
-LOCATE  COMP  "RCKE"  SITE  "82";
-LOCATE  COMP  "RCLK"  SITE  "86";
-LOCATE  COMP  "RDQMH"  SITE  "76";
-LOCATE  COMP  "RDQML"  SITE  "61";
-LOCATE  COMP  "RD[0]"  SITE  "64";
-LOCATE  COMP  "RD[1]"  SITE  "65";
-LOCATE  COMP  "RD[2]"  SITE  "66";
-LOCATE  COMP  "RD[3]"  SITE  "67";
-LOCATE  COMP  "RD[4]"  SITE  "68";
-LOCATE  COMP  "RD[5]"  SITE  "69";
-LOCATE  COMP  "RD[6]"  SITE  "70";
-LOCATE  COMP  "RD[7]"  SITE  "71";
-LOCATE  COMP  "UFMCLK"  SITE  "58";
-LOCATE  COMP  "UFMSDI"  SITE  "56";
-LOCATE  COMP  "UFMSDO"  SITE  "55";
-LOCATE  COMP  "nCCAS"  SITE  "27";
-LOCATE  COMP  "nCRAS"  SITE  "43";
-LOCATE  COMP  "nFWE"  SITE  "22";
-LOCATE  COMP  "nRCAS"  SITE  "78";
-LOCATE  COMP  "nRCS"  SITE  "77";
-LOCATE  COMP  "nRRAS"  SITE  "73";
-LOCATE  COMP  "nRWE"  SITE  "72";
-LOCATE  COMP  "nUFMCS"  SITE  "53";
-
-
-
-
-
-PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Mon Aug 16 21:32:33 2021
-
-
-
-
-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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-

-

-

-
- - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html deleted file mode 100644 index ce22106..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html +++ /dev/null @@ -1,307 +0,0 @@ - -Place & Route Report - - -
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Mon Aug 16 21:32:27 2021
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
-RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
-RAM2GS_LCMXO256C_impl1.prf -gui -msgset
-C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
-
-
-Preference file: RAM2GS_LCMXO256C_impl1.prf.
-
-Cost Table Summary
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            2.023        0            0.339        0            07           Completed
-* : Design saved.
-
-Total (real) run time for 1-seed: 7 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
-Mon Aug 16 21:32:27 2021
-
-
-Best Par Run
-PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
-Preference file: RAM2GS_LCMXO256C_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-
-Device utilization summary:
-
-   PIO (prelim)      67/79           84% used
-                     67/78           85% bonded
-   SLICE             65/128          50% used
-
-
-
-Number of Signals: 252
-Number of Connections: 618
-
-Pin Constraint Summary:
-   67 out of 67 pins locked (100% locked).
-
-The following 4 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 39)
-    PHI2_c (driver: PHI2, clk load #: 13)
-    nCCAS_c (driver: nCCAS, clk load #: 4)
-    nCRAS_c (driver: nCRAS, clk load #: 7)
-
-No signal is selected as secondary clock.
-
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-........
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-...............
-Placer score = 586066.
-Finished Placer Phase 1.  REAL time: 6 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  584668
-Finished Placer Phase 2.  REAL time: 6 secs 
-
-
-
-Clock Report
-
-Global Clock Resources:
-  CLK_PIN    : 1 out of 4 (25%)
-  General PIO: 3 out of 80 (3%)
-
-Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13
-  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4
-  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7
-
-  PRIMARY  : 4 out of 4 (100%)
-  SECONDARY: 0 out of 4 (0%)
-
-
-
-
-I/O Usage Summary (final):
-   67 out of 79 (84.8%) PIO sites used.
-   67 out of 78 (85.9%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+------------+------------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
-+----------+----------------+------------+------------+------------+
-| 0        | 36 / 41 ( 87%) | 3.3V       | -          | -          |
-| 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
-+----------+----------------+------------+------------+------------+
-
-Total placer CPU time: 6 secs 
-
-Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
-
-0 connections routed; 618 unrouted.
-Starting router resource preassignment
-WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
-WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
-WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
-
-Completed router resource preassignment. Real time: 6 secs 
-
-Start NBR router at 21:32:33 08/16/21
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 21:32:33 08/16/21
-
-Start NBR section for initial routing at 21:32:33 08/16/21
-Level 1, iteration 1
-0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 2.038ns/0.000ns; real time: 6 secs 
-Level 4, iteration 1
-23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 21:32:33 08/16/21
-Level 1, iteration 1
-0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
-Level 4, iteration 1
-8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
-Level 4, iteration 2
-4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
-Level 4, iteration 3
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21
-
-Start NBR section for re-routing at 21:32:33 08/16/21
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs 
-
-Start NBR section for post-routing at 21:32:33 08/16/21
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack<setup> : 2.023ns
-  Timing score<setup> : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-Total CPU time 6 secs 
-Total REAL time: 7 secs 
-Completely routed.
-End of route.  618 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack<setup/<ns>> = 2.023
-PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
-PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.339
-PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 6 secs 
-Total REAL time to completion: 7 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
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- - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html deleted file mode 100644 index bb33f8f..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html +++ /dev/null @@ -1,83 +0,0 @@ - -Project Summary - - -

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RAM2GS_LCMXO256C project summary
Module Name:RAM2GS_LCMXO256CSynthesis:Lattice LSE
Implementation Name:impl1Strategy Name:Strategy1
Last Process:JEDEC FileState:Passed
Target Device:LCMXO256C-3T100CDevice Family:MachXO
Device Type:LCMXO256CPackage Type:TQFP100
Performance grade:3Operating conditions:COM
Logic preference file:RAM2GS_LCMXO256C.lpf
Physical Preference file:impl1/RAM2GS_LCMXO256C_impl1.prf
Product Version:3.12.0.240.2Patch Version:
Updated:2021/08/16 21:36:29
Implementation Location:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1
Project File:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf

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- - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html deleted file mode 100644 index 01aa986..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html +++ /dev/null @@ -1,2740 +0,0 @@ - -Lattice Map TRACE Report - - -
Map TRACE Report
-
-Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:32:27 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
-Design file:     ram2gs_lcmxo256c_impl1_map.ncd
-Preference file: ram2gs_lcmxo256c_impl1.prf
-Device,speed:    LCMXO256C,3
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:              12.873ns  (21.6% logic, 78.4% route), 7 logic levels.
-
- Constraint Details:
-
-     12.873ns physical path delay SLICE_95 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_95.CLK to    SLICE_95.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1   e 1.441    SLICE_95.Q1 to    SLICE_67.A1 Bank_7
-CTOF_DEL    ---     0.371    SLICE_67.A1 to    SLICE_67.F1 SLICE_67
-ROUTE         1   e 1.441    SLICE_67.F1 to    SLICE_82.C1 n2154
-CTOF_DEL    ---     0.371    SLICE_82.C1 to    SLICE_82.F1 SLICE_82
-ROUTE         1   e 1.441    SLICE_82.F1 to    SLICE_76.B1 n26
-CTOF_DEL    ---     0.371    SLICE_76.B1 to    SLICE_76.F1 SLICE_76
-ROUTE         4   e 1.441    SLICE_76.F1 to    SLICE_89.B0 n1285
-CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
-ROUTE         3   e 1.441    SLICE_89.F0 to    SLICE_18.D1 n2290
-CTOF_DEL    ---     0.371    SLICE_18.D1 to    SLICE_18.F1 SLICE_18
-ROUTE         3   e 1.441    SLICE_18.F1 to    SLICE_90.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371    SLICE_90.C0 to    SLICE_90.F0 SLICE_90
-ROUTE         2   e 1.441    SLICE_90.F0 to    SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   12.873   (21.6% logic, 78.4% route), 7 logic levels.
-
-Report:   26.276ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_76
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_77
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 5.575ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
-
-   Delay:              10.181ns  (23.7% logic, 76.3% route), 6 logic levels.
-
- Constraint Details:
-
-     10.181ns physical path delay SLICE_7 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560    SLICE_7.CLK to     SLICE_7.Q0 SLICE_7 (from RCLK_c)
-ROUTE         3   e 1.441     SLICE_7.Q0 to    SLICE_78.A0 FS_14
-CTOF_DEL    ---     0.371    SLICE_78.A0 to    SLICE_78.F0 SLICE_78
-ROUTE         3   e 1.441    SLICE_78.F0 to    SLICE_73.B1 n10
-CTOF_DEL    ---     0.371    SLICE_73.B1 to    SLICE_73.F1 SLICE_73
-ROUTE         4   e 0.561    SLICE_73.F1 to    SLICE_73.B0 n2300
-CTOF_DEL    ---     0.371    SLICE_73.B0 to    SLICE_73.F0 SLICE_73
-ROUTE         1   e 1.441    SLICE_73.F0 to    SLICE_75.C0 n11
-CTOF_DEL    ---     0.371    SLICE_75.C0 to    SLICE_75.F0 SLICE_75
-ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_33.D1 n2119
-CTOF_DEL    ---     0.371    SLICE_33.D1 to    SLICE_33.F1 SLICE_33
-ROUTE         1   e 1.441    SLICE_33.F1 to    SLICE_56.CE RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                   10.181   (23.7% logic, 76.3% route), 6 logic levels.
-
-Report:   10.425ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_55 and
-      5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets
-     12.500ns offset RCLK to RA[10] by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_55.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_55.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[9] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
-ROUTE         1   e 1.441    SLICE_88.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[8] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
-ROUTE         1   e 1.441    SLICE_95.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[7] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
-ROUTE         1   e 1.441    SLICE_97.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[6] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
-ROUTE         1   e 1.441    SLICE_98.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[5] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
-ROUTE         1   e 1.441    SLICE_98.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.427ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     6.569ns  (69.5% logic, 30.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets
-     12.500ns offset RCLK to RA[4] by 3.427ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.561    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
-ROUTE         1   e 1.441    SLICE_64.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
-                  --------
-                    6.569   (69.5% logic, 30.5% route), 3 logic levels.
-
-Report:    9.073ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[3] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
-ROUTE         1   e 1.441    SLICE_94.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[2] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
-ROUTE         1   e 1.441    SLICE_95.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[1] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
-ROUTE         1   e 1.441    SLICE_94.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[0] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
-ROUTE         1   e 1.441    SLICE_92.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_60 and
-      5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRCS by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_60.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_60.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_34 and
-      5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets
-     12.500ns offset RCLK to RCKE by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_34.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4   e 1.441    SLICE_34.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_63 and
-      5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRWE by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_63.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_61 and
-      5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRRAS by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_61.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2   e 1.441    SLICE_61.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_58 and
-      5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRCAS by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_58.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_58.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets
-     12.500ns offset RCLK to RDQMH by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
-ROUTE         1   e 1.441    SLICE_88.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets
-     12.500ns offset RCLK to RDQML by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
-ROUTE         1   e 1.441    SLICE_92.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.276 ns|   7  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    10.425 ns|   6  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.073 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:32:27 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
-Design file:     ram2gs_lcmxo256c_impl1_map.ncd
-Preference file: ram2gs_lcmxo256c_impl1.prf
-Device,speed:    LCMXO256C,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.485ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
-
-   Delay:               0.462ns  (56.7% logic, 43.3% route), 2 logic levels.
-
- Constraint Details:
-
-      0.462ns physical path delay SLICE_9 to SLICE_9 meets
-     -0.023ns DIN_HLD and
-      0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170    SLICE_9.CLK to     SLICE_9.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2   e 0.199     SLICE_9.Q0 to     SLICE_9.C0 ADSubmitted
-CTOF_DEL    ---     0.092     SLICE_9.C0 to     SLICE_9.F0 SLICE_9
-ROUTE         1   e 0.001     SLICE_9.F0 to    SLICE_9.DI0 n1361 (to PHI2_c)
-                  --------
-                    0.462   (56.7% logic, 43.3% route), 2 logic levels.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.377ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
-
-   Delay:               0.356ns  (44.1% logic, 55.9% route), 1 logic levels.
-
- Constraint Details:
-
-      0.356ns physical path delay SLICE_72 to SLICE_72 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns
-
- Physical Path Details:
-
-      Data path SLICE_72 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_72.CLK to    SLICE_72.Q0 SLICE_72 (from RCLK_c)
-ROUTE         1   e 0.199    SLICE_72.Q0 to    SLICE_72.M1 n702 (to RCLK_c)
-                  --------
-                    0.356   (44.1% logic, 55.9% route), 1 logic levels.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_55 and
-      1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to RA[10] by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_55.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_55.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[9] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
-ROUTE         1   e 0.515    SLICE_88.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[8] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
-ROUTE         1   e 0.515    SLICE_95.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[7] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
-ROUTE         1   e 0.515    SLICE_97.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[6] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
-ROUTE         1   e 0.515    SLICE_98.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[5] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
-ROUTE         1   e 0.515    SLICE_98.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.850ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     2.071ns  (65.5% logic, 34.5% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets
-      0.000ns hold offset RCLK to RA[4] by 2.850ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.199    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
-ROUTE         1   e 0.515    SLICE_64.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
-                  --------
-                    2.071   (65.5% logic, 34.5% route), 3 logic levels.
-
-Report:    2.850ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[3] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
-ROUTE         1   e 0.515    SLICE_94.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[2] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
-ROUTE         1   e 0.515    SLICE_95.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[1] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
-ROUTE         1   e 0.515    SLICE_94.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[0] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
-ROUTE         1   e 0.515    SLICE_92.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_60 and
-      1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRCS by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_60.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_60.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_34 and
-      1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to RCKE by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_34.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4   e 0.515    SLICE_34.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_63 and
-      1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRWE by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_63.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_61 and
-      1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRRAS by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_61.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2   e 0.515    SLICE_61.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_58 and
-      1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRCAS by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_58.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_58.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RDQMH by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
-ROUTE         1   e 0.515    SLICE_88.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RDQML by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
-ROUTE         1   e 0.515    SLICE_92.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.850 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
-
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-
    - - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html deleted file mode 100644 index bdfe34c..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html +++ /dev/null @@ -1,4588 +0,0 @@ - -Lattice TRACE Report - - -
    Place & Route TRACE Report
-
-Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:32:34 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
-Design file:     ram2gs_lcmxo256c_impl1.ncd
-Preference file: ram2gs_lcmxo256c_impl1.prf
-Device,speed:    LCMXO256C,3
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 161.925ns (weighted slack = 323.850ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i0  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:              12.810ns  (21.7% logic, 78.3% route), 7 logic levels.
-
- Constraint Details:
-
-     12.810ns physical path delay SLICE_94 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.925ns
-
- Physical Path Details:
-
-      Data path SLICE_94 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
-ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
-CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
-ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
-CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
-ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
-CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
-ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
-CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
-ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
-CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
-ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
-ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   12.810   (21.7% logic, 78.3% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.080ns (weighted slack = 324.160ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:              12.655ns  (22.0% logic, 78.0% route), 7 logic levels.
-
- Constraint Details:
-
-     12.655ns physical path delay SLICE_95 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.080ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_95 (from PHI2_c)
-ROUTE         1     1.488       R2C2C.Q0 to       R5C2C.A0 Bank_6
-CTOF_DEL    ---     0.371       R5C2C.A0 to       R5C2C.F0 SLICE_82
-ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
-CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
-ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
-CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
-ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
-CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
-ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
-CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
-ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
-ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   12.655   (22.0% logic, 78.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.409ns (weighted slack = 324.818ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i0  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:              12.326ns  (22.6% logic, 77.4% route), 7 logic levels.
-
- Constraint Details:
-
-     12.326ns physical path delay SLICE_94 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.409ns
-
- Physical Path Details:
-
-      Data path SLICE_94 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
-ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
-CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
-ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
-CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
-ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
-CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
-ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
-CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
-ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
-CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
-ROUTE         3     1.504       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C4D.A0 to       R4C4D.F0 SLICE_90
-ROUTE         2     1.550       R4C4D.F0 to       R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   12.326   (22.6% logic, 77.4% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.416ns (weighted slack = 324.832ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i0  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:              12.319ns  (22.6% logic, 77.4% route), 7 logic levels.
-
- Constraint Details:
-
-     12.319ns physical path delay SLICE_94 to SLICE_88 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.416ns
-
- Physical Path Details:
-
-      Data path SLICE_94 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
-ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
-CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
-ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
-CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
-ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
-CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
-ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
-CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
-ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
-CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
-ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
-ROUTE         2     1.543       R4C4A.F0 to       R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   12.319   (22.6% logic, 77.4% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R2C4A.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.564ns (weighted slack = 325.128ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:              12.171ns  (22.9% logic, 77.1% route), 7 logic levels.
-
- Constraint Details:
-
-     12.171ns physical path delay SLICE_95 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.564ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_95 (from PHI2_c)
-ROUTE         1     1.488       R2C2C.Q0 to       R5C2C.A0 Bank_6
-CTOF_DEL    ---     0.371       R5C2C.A0 to       R5C2C.F0 SLICE_82
-ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
-CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
-ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
-CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
-ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
-CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
-ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
-CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
-ROUTE         3     1.504       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C4D.A0 to       R4C4D.F0 SLICE_90
-ROUTE         2     1.550       R4C4D.F0 to       R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   12.171   (22.9% logic, 77.1% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.571ns (weighted slack = 325.142ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:              12.164ns  (22.9% logic, 77.1% route), 7 logic levels.
-
- Constraint Details:
-
-     12.164ns physical path delay SLICE_95 to SLICE_88 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.571ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_95 (from PHI2_c)
-ROUTE         1     1.488       R2C2C.Q0 to       R5C2C.A0 Bank_6
-CTOF_DEL    ---     0.371       R5C2C.A0 to       R5C2C.F0 SLICE_82
-ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
-CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
-ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
-CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
-ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
-CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
-ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
-CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
-ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
-ROUTE         2     1.543       R4C4A.F0 to       R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   12.164   (22.9% logic, 77.1% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R2C4A.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.606ns (weighted slack = 325.212ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:              12.129ns  (23.0% logic, 77.0% route), 7 logic levels.
-
- Constraint Details:
-
-     12.129ns physical path delay SLICE_95 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.606ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     1.155       R2C2C.Q1 to       R5C2B.D1 Bank_7
-CTOF_DEL    ---     0.371       R5C2B.D1 to       R5C2B.F1 SLICE_67
-ROUTE         1     0.304       R5C2B.F1 to       R5C2C.D1 n2154
-CTOF_DEL    ---     0.371       R5C2C.D1 to       R5C2C.F1 SLICE_82
-ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
-CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
-ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
-CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
-ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
-CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
-ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
-ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   12.129   (23.0% logic, 77.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R2C2C.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.635ns (weighted slack = 325.270ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i1  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:              12.100ns  (20.0% logic, 80.0% route), 6 logic levels.
-
- Constraint Details:
-
-     12.100ns physical path delay SLICE_94 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.635ns
-
- Physical Path Details:
-
-      Data path SLICE_94 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q1 SLICE_94 (from PHI2_c)
-ROUTE         1     1.905       R2C3B.Q1 to       R6C2B.C1 Bank_1
-CTOF_DEL    ---     0.371       R6C2B.C1 to       R6C2B.F1 SLICE_97
-ROUTE         1     1.444       R6C2B.F1 to       R5C5B.C1 n2170
-CTOF_DEL    ---     0.371       R5C5B.C1 to       R5C5B.F1 SLICE_76
-ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
-CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
-ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
-CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
-ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
-ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   12.100   (20.0% logic, 80.0% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.868ns (weighted slack = 325.736ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:              11.867ns  (23.5% logic, 76.5% route), 7 logic levels.
-
- Constraint Details:
-
-     11.867ns physical path delay SLICE_97 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.868ns
-
- Physical Path Details:
-
-      Data path SLICE_97 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R6C2B.CLK to       R6C2B.Q1 SLICE_97 (from PHI2_c)
-ROUTE         1     0.700       R6C2B.Q1 to       R5C2C.D0 Bank_5
-CTOF_DEL    ---     0.371       R5C2C.D0 to       R5C2C.F0 SLICE_82
-ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
-CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
-ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
-CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
-ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
-CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
-ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
-CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
-ROUTE         3     1.504       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C4A.A0 to       R4C4A.F0 SLICE_72
-ROUTE         2     2.034       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   11.867   (23.5% logic, 76.5% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R6C2B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R5C4B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.886ns (weighted slack = 325.772ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i0  (from PHI2_c +)
-   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
-
-   Delay:              11.849ns  (23.5% logic, 76.5% route), 7 logic levels.
-
- Constraint Details:
-
-     11.849ns physical path delay SLICE_94 to SLICE_96 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.886ns
-
- Physical Path Details:
-
-      Data path SLICE_94 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C3B.CLK to       R2C3B.Q0 SLICE_94 (from PHI2_c)
-ROUTE         1     1.643       R2C3B.Q0 to       R5C2C.B0 Bank_0
-CTOF_DEL    ---     0.371       R5C2C.B0 to       R5C2C.F0 SLICE_82
-ROUTE         1     0.497       R5C2C.F0 to       R5C2C.C1 n2166
-CTOF_DEL    ---     0.371       R5C2C.C1 to       R5C2C.F1 SLICE_82
-ROUTE         1     1.548       R5C2C.F1 to       R5C5B.B1 n26
-CTOF_DEL    ---     0.371       R5C5B.B1 to       R5C5B.F1 SLICE_76
-ROUTE         4     1.750       R5C5B.F1 to       R6C3A.D0 n1285
-CTOF_DEL    ---     0.371       R6C3A.D0 to       R6C3A.F0 SLICE_89
-ROUTE         3     1.048       R6C3A.F0 to       R5C3C.A1 n2290
-CTOF_DEL    ---     0.371       R5C3C.A1 to       R5C3C.F1 SLICE_18
-ROUTE         3     1.504       R5C3C.F1 to       R4C4D.A1 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C4D.A1 to       R4C4D.F1 SLICE_90
-ROUTE         1     1.073       R4C4D.F1 to       R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c)
-                  --------
-                   11.849   (23.5% logic, 76.5% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R2C3B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.911       39.PADDI to      R3C4B.CLK PHI2_c
-                  --------
-                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   26.150ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_76
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_77
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 7.566ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               8.190ns  (29.5% logic, 70.5% route), 6 logic levels.
-
- Constraint Details:
-
-      8.190ns physical path delay SLICE_7 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.566ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
-ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
-CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
-ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
-CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
-ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
-CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
-ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
-CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
-ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
-CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
-ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.190   (29.5% logic, 70.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.590ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
-
-   Delay:               8.166ns  (29.6% logic, 70.4% route), 6 logic levels.
-
- Constraint Details:
-
-      8.166ns physical path delay SLICE_7 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.590ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
-ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
-CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
-ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
-CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
-ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
-CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
-ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
-CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
-ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
-CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
-ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    8.166   (29.6% logic, 70.4% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.984ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               7.772ns  (31.1% logic, 68.9% route), 6 logic levels.
-
- Constraint Details:
-
-      7.772ns physical path delay SLICE_8 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.984ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
-ROUTE         3     1.511       R8C4C.Q1 to       R7C5C.A0 FS_13
-CTOF_DEL    ---     0.371       R7C5C.A0 to       R7C5C.F0 SLICE_78
-ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
-CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
-ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
-CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
-ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
-CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
-ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
-CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
-ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    7.772   (31.1% logic, 68.9% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 8.008ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
-
-   Delay:               7.748ns  (31.2% logic, 68.8% route), 6 logic levels.
-
- Constraint Details:
-
-      7.748ns physical path delay SLICE_8 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 8.008ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
-ROUTE         3     1.511       R8C4C.Q1 to       R7C5C.A0 FS_13
-CTOF_DEL    ---     0.371       R7C5C.A0 to       R7C5C.F0 SLICE_78
-ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
-CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
-ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
-CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
-ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
-CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
-ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
-CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
-ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    7.748   (31.2% logic, 68.8% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 8.123ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               7.633ns  (31.6% logic, 68.4% route), 6 logic levels.
-
- Constraint Details:
-
-      7.633ns physical path delay SLICE_8 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 8.123ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q0 SLICE_8 (from RCLK_c)
-ROUTE         3     1.372       R8C4C.Q0 to       R7C5C.C0 FS_12
-CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_78
-ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
-CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
-ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
-CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
-ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
-CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
-ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
-CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
-ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    7.633   (31.6% logic, 68.4% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 8.147ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
-
-   Delay:               7.609ns  (31.7% logic, 68.3% route), 6 logic levels.
-
- Constraint Details:
-
-      7.609ns physical path delay SLICE_8 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 8.147ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q0 SLICE_8 (from RCLK_c)
-ROUTE         3     1.372       R8C4C.Q0 to       R7C5C.C0 FS_12
-CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_78
-ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
-CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
-ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
-CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
-ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
-CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
-ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
-CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
-ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    7.609   (31.7% logic, 68.3% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R8C4C.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 8.262ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
-   Destination:    FF         Data in        UFMCLK_389  (to RCLK_c +)
-
-   Delay:               7.112ns  (23.5% logic, 76.5% route), 4 logic levels.
-
- Constraint Details:
-
-      7.112ns physical path delay SLICE_7 to SLICE_42 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_42:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
-ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
-CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
-ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
-CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
-ROUTE         4     0.915       R7C4A.F1 to       R6C4A.C0 n2300
-CTOF_DEL    ---     0.371       R6C4A.C0 to       R6C4A.F0 SLICE_86
-ROUTE         2     1.538       R6C4A.F0 to      R7C5A.LSR n2291 (to RCLK_c)
-                  --------
-                    7.112   (23.5% logic, 76.5% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_42:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R7C5A.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 8.262ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
-   Destination:    FF         Data in        UFMSDI_390  (to RCLK_c +)
-
-   Delay:               7.112ns  (23.5% logic, 76.5% route), 4 logic levels.
-
- Constraint Details:
-
-      7.112ns physical path delay SLICE_7 to SLICE_43 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
-ROUTE         3     1.929       R8C4D.Q1 to       R7C5C.B0 FS_15
-CTOF_DEL    ---     0.371       R7C5C.B0 to       R7C5C.F0 SLICE_78
-ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
-CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
-ROUTE         4     0.915       R7C4A.F1 to       R6C4A.C0 n2300
-CTOF_DEL    ---     0.371       R6C4A.C0 to       R6C4A.F0 SLICE_86
-ROUTE         2     1.538       R6C4A.F0 to      R7C5B.LSR n2291 (to RCLK_c)
-                  --------
-                    7.112   (23.5% logic, 76.5% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_43:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R7C5B.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 8.316ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               7.440ns  (32.5% logic, 67.5% route), 6 logic levels.
-
- Constraint Details:
-
-      7.440ns physical path delay SLICE_7 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 8.316ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
-ROUTE         3     1.179       R8C4D.Q0 to       R7C5C.D0 FS_14
-CTOF_DEL    ---     0.371       R7C5C.D0 to       R7C5C.F0 SLICE_78
-ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
-CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
-ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
-CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
-ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
-CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
-ROUTE         2     0.513       R7C4B.F0 to       R7C4B.C1 n2119
-CTOF_DEL    ---     0.371       R7C4B.C1 to       R7C4B.F1 SLICE_75
-ROUTE         1     1.260       R7C4B.F1 to       R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    7.440   (32.5% logic, 67.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R6C3A.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 8.340ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
-
-   Delay:               7.416ns  (32.6% logic, 67.4% route), 6 logic levels.
-
- Constraint Details:
-
-      7.416ns physical path delay SLICE_7 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 8.340ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
-ROUTE         3     1.179       R8C4D.Q0 to       R7C5C.D0 FS_14
-CTOF_DEL    ---     0.371       R7C5C.D0 to       R7C5C.F0 SLICE_78
-ROUTE         3     1.057       R7C5C.F0 to       R7C4A.A1 n10
-CTOF_DEL    ---     0.371       R7C4A.A1 to       R7C4A.F1 SLICE_73
-ROUTE         4     0.712       R7C4A.F1 to       R7C4A.B0 n2300
-CTOF_DEL    ---     0.371       R7C4A.B0 to       R7C4A.F0 SLICE_73
-ROUTE         1     0.304       R7C4A.F0 to       R7C4B.D0 n11
-CTOF_DEL    ---     0.371       R7C4B.D0 to       R7C4B.F0 SLICE_75
-ROUTE         2     1.102       R7C4B.F0 to       R6C4C.B1 n2119
-CTOF_DEL    ---     0.371       R6C4C.B1 to       R6C4C.F1 SLICE_33
-ROUTE         1     0.647       R6C4C.F1 to       R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    7.416   (32.6% logic, 67.4% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R8C4D.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to      R6C4B.CLK RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:    8.434ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.904ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     6.180ns  (67.9% logic, 32.1% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_55 and
-      6.180ns delay SLICE_55 to RA[10] (totaling 8.596ns) meets
-     12.500ns offset RCLK to RA[10] by 3.904ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C4B.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     1.984       R2C4B.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
-                  --------
-                    6.180   (67.9% logic, 32.1% route), 2 logic levels.
-
-Report:    8.596ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.734ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     6.350ns  (71.9% logic, 28.1% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      6.350ns delay SLICE_64 to RA[9] (totaling 8.766ns) meets
-     12.500ns offset RCLK to RA[9] by 3.734ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.966       R2C2A.Q0 to       R2C4A.C1 nRowColSel
-CTOF_DEL    ---     0.371       R2C4A.C1 to       R2C4A.F1 SLICE_88
-ROUTE         1     0.817       R2C4A.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
-                  --------
-                    6.350   (71.9% logic, 28.1% route), 3 logic levels.
-
-Report:    8.766ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.604ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     6.480ns  (70.5% logic, 29.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      6.480ns delay SLICE_64 to RA[8] (totaling 8.896ns) meets
-     12.500ns offset RCLK to RA[8] by 3.604ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.096       R2C2A.Q0 to       R2C2C.B0 nRowColSel
-CTOF_DEL    ---     0.371       R2C2C.B0 to       R2C2C.F0 SLICE_95
-ROUTE         1     0.817       R2C2C.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
-                  --------
-                    6.480   (70.5% logic, 29.5% route), 3 logic levels.
-
-Report:    8.896ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.245ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     7.839ns  (58.3% logic, 41.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.839ns delay SLICE_64 to RA[7] (totaling 10.255ns) meets
-     12.500ns offset RCLK to RA[7] by 2.245ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.234       R2C2A.Q0 to       R6C2B.D0 nRowColSel
-CTOF_DEL    ---     0.371       R6C2B.D0 to       R6C2B.F0 SLICE_97
-ROUTE         1     2.038       R6C2B.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
-                  --------
-                    7.839   (58.3% logic, 41.7% route), 3 logic levels.
-
-Report:   10.255ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.499ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     7.585ns  (60.2% logic, 39.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.585ns delay SLICE_64 to RA[6] (totaling 10.001ns) meets
-     12.500ns offset RCLK to RA[6] by 2.499ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.966       R2C2A.Q0 to       R3C2A.C0 nRowColSel
-CTOF_DEL    ---     0.371       R3C2A.C0 to       R3C2A.F0 SLICE_98
-ROUTE         1     2.052       R3C2A.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
-                  --------
-                    7.585   (60.2% logic, 39.8% route), 3 logic levels.
-
-Report:   10.001ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.891ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     7.193ns  (63.5% logic, 36.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.193ns delay SLICE_64 to RA[5] (totaling 9.609ns) meets
-     12.500ns offset RCLK to RA[5] by 2.891ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.966       R2C2A.Q0 to       R3C2A.C1 nRowColSel
-CTOF_DEL    ---     0.371       R3C2A.C1 to       R3C2A.F1 SLICE_98
-ROUTE         1     1.660       R3C2A.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
-                  --------
-                    7.193   (63.5% logic, 36.5% route), 3 logic levels.
-
-Report:    9.609ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.996ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     6.088ns  (75.0% logic, 25.0% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      6.088ns delay SLICE_64 to RA[4] (totaling 8.504ns) meets
-     12.500ns offset RCLK to RA[4] by 3.996ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.704       R2C2A.Q0 to       R2C2A.D1 nRowColSel
-CTOF_DEL    ---     0.371       R2C2A.D1 to       R2C2A.F1 SLICE_64
-ROUTE         1     0.817       R2C2A.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
-                  --------
-                    6.088   (75.0% logic, 25.0% route), 3 logic levels.
-
-Report:    8.504ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.567ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     7.517ns  (60.8% logic, 39.2% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.517ns delay SLICE_64 to RA[3] (totaling 9.933ns) meets
-     12.500ns offset RCLK to RA[3] by 2.567ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.966       R2C2A.Q0 to       R2C3B.C1 nRowColSel
-CTOF_DEL    ---     0.371       R2C3B.C1 to       R2C3B.F1 SLICE_94
-ROUTE         1     1.984       R2C3B.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
-                  --------
-                    7.517   (60.8% logic, 39.2% route), 3 logic levels.
-
-Report:    9.933ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.438ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     7.646ns  (59.7% logic, 40.3% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.646ns delay SLICE_64 to RA[2] (totaling 10.062ns) meets
-     12.500ns offset RCLK to RA[2] by 2.438ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.096       R2C2A.Q0 to       R2C2C.B1 nRowColSel
-CTOF_DEL    ---     0.371       R2C2C.B1 to       R2C2C.F1 SLICE_95
-ROUTE         1     1.983       R2C2C.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
-                  --------
-                    7.646   (59.7% logic, 40.3% route), 3 logic levels.
-
-Report:   10.062ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.734ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     6.350ns  (71.9% logic, 28.1% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      6.350ns delay SLICE_64 to RA[1] (totaling 8.766ns) meets
-     12.500ns offset RCLK to RA[1] by 3.734ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.966       R2C2A.Q0 to       R2C3B.C0 nRowColSel
-CTOF_DEL    ---     0.371       R2C3B.C0 to       R2C3B.F0 SLICE_94
-ROUTE         1     0.817       R2C3B.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
-                  --------
-                    6.350   (71.9% logic, 28.1% route), 3 logic levels.
-
-Report:    8.766ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.826ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     7.258ns  (62.9% logic, 37.1% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.258ns delay SLICE_64 to RA[0] (totaling 9.674ns) meets
-     12.500ns offset RCLK to RA[0] by 2.826ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.165       R2C2A.Q0 to       R3C2B.B1 nRowColSel
-CTOF_DEL    ---     0.371       R3C2B.B1 to       R3C2B.F1 SLICE_92
-ROUTE         1     1.526       R3C2B.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
-                  --------
-                    7.258   (62.9% logic, 37.1% route), 3 logic levels.
-
-Report:    9.674ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 5.071ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_60 and
-      5.013ns delay SLICE_60 to nRCS (totaling 7.429ns) meets
-     12.500ns offset RCLK to nRCS by 5.071ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C5B.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.817       R2C5B.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.429ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.420ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     6.664ns  (63.0% logic, 37.0% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_34 and
-      6.664ns delay SLICE_34 to RCKE (totaling 9.080ns) meets
-     12.500ns offset RCLK to RCKE by 3.420ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R5C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C2A.CLK to       R5C2A.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     2.468       R5C2A.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
-                  --------
-                    6.664   (63.0% logic, 37.0% route), 2 logic levels.
-
-Report:    9.080ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 5.071ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_63 and
-      5.013ns delay SLICE_63 to nRWE (totaling 7.429ns) meets
-     12.500ns offset RCLK to nRWE by 5.071ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R3C5B.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     0.817       R3C5B.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.429ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.885ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     6.199ns  (67.7% logic, 32.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_61 and
-      6.199ns delay SLICE_61 to nRRAS (totaling 8.615ns) meets
-     12.500ns offset RCLK to nRRAS by 3.885ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R4C5A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R4C5A.CLK to       R4C5A.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     2.003       R4C5A.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
-                  --------
-                    6.199   (67.7% logic, 32.3% route), 2 logic levels.
-
-Report:    8.615ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.905ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     6.179ns  (67.9% logic, 32.1% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_58 and
-      6.179ns delay SLICE_58 to nRCAS (totaling 8.595ns) meets
-     12.500ns offset RCLK to nRCAS by 3.905ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C4C.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     1.983       R2C4C.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
-                  --------
-                    6.179   (67.9% logic, 32.1% route), 2 logic levels.
-
-Report:    8.595ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.025ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     7.059ns  (64.7% logic, 35.3% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.059ns delay SLICE_64 to RDQMH (totaling 9.475ns) meets
-     12.500ns offset RCLK to RDQMH by 3.025ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.966       R2C2A.Q0 to       R2C4A.C0 nRowColSel
-CTOF_DEL    ---     0.371       R2C4A.C0 to       R2C4A.F0 SLICE_88
-ROUTE         1     1.526       R2C4A.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
-                  --------
-                    7.059   (64.7% logic, 35.3% route), 3 logic levels.
-
-Report:    9.475ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.023ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     8.061ns  (56.7% logic, 43.3% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      8.061ns delay SLICE_64 to RDQML (totaling 10.477ns) meets
-     12.500ns offset RCLK to RDQML by 2.023ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.954       R2C2A.Q0 to       R3C2B.C0 nRowColSel
-CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_92
-ROUTE         1     2.540       R3C2B.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
-                  --------
-                    8.061   (56.7% logic, 43.3% route), 3 logic levels.
-
-Report:   10.477ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.150 ns|   7  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     8.434 ns|   6  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.596 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.766 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.896 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.255 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.001 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.609 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.504 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.933 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.062 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.766 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.674 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     7.429 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.080 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     7.429 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.615 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.595 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.475 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.477 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:32:34 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
-Design file:     ram2gs_lcmxo256c_impl1.ncd
-Preference file: ram2gs_lcmxo256c_impl1.prf
-Device,speed:    LCMXO256C,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.444ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
-
-   Delay:               0.421ns  (62.2% logic, 37.8% route), 2 logic levels.
-
- Constraint Details:
-
-      0.421ns physical path delay SLICE_9 to SLICE_9 meets
-     -0.023ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.023ns) by 0.444ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C3A.CLK to       R5C3A.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.159       R5C3A.Q0 to       R5C3A.D0 ADSubmitted
-CTOF_DEL    ---     0.092       R5C3A.D0 to       R5C3A.F0 SLICE_9
-ROUTE         1     0.000       R5C3A.F0 to      R5C3A.DI0 n1361 (to PHI2_c)
-                  --------
-                    0.421   (62.2% logic, 37.8% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C3A.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C3A.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.186ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
-
-   Delay:               1.157ns  (30.6% logic, 69.4% route), 3 logic levels.
-
- Constraint Details:
-
-      1.157ns physical path delay SLICE_18 to SLICE_23 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.186ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
-CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
-ROUTE         3     0.383       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R4C4D.A0 to       R4C4D.F0 SLICE_90
-ROUTE         2     0.167       R4C4D.F0 to       R4C4C.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                    1.157   (30.6% logic, 69.4% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R4C4C.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.193ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted_379  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
-
-   Delay:               1.164ns  (38.3% logic, 61.7% route), 4 logic levels.
-
- Constraint Details:
-
-      1.164ns physical path delay SLICE_14 to SLICE_18 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.193ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R6C3B.CLK to       R6C3B.Q0 SLICE_14 (from PHI2_c)
-ROUTE         1     0.253       R6C3B.Q0 to       R6C3B.B1 C1Submitted
-CTOF_DEL    ---     0.092       R6C3B.B1 to       R6C3B.F1 SLICE_14
-ROUTE         1     0.075       R6C3B.F1 to       R6C3C.D1 n2098
-CTOF_DEL    ---     0.092       R6C3C.D1 to       R6C3C.F1 SLICE_77
-ROUTE         1     0.123       R6C3C.F1 to       R6C3C.C0 n2286
-CTOF_DEL    ---     0.092       R6C3C.C0 to       R6C3C.F0 SLICE_77
-ROUTE         1     0.267       R6C3C.F0 to       R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c)
-                  --------
-                    1.164   (38.3% logic, 61.7% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R6C3B.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.280ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
-
-   Delay:               1.251ns  (35.7% logic, 64.3% route), 4 logic levels.
-
- Constraint Details:
-
-      1.251ns physical path delay SLICE_9 to SLICE_18 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.280ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C3A.CLK to       R5C3A.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.159       R5C3A.Q0 to       R5C3A.D1 ADSubmitted
-CTOF_DEL    ---     0.092       R5C3A.D1 to       R5C3A.F1 SLICE_9
-ROUTE         1     0.256       R5C3A.F1 to       R6C3C.A1 n2080
-CTOF_DEL    ---     0.092       R6C3C.A1 to       R6C3C.F1 SLICE_77
-ROUTE         1     0.123       R6C3C.F1 to       R6C3C.C0 n2286
-CTOF_DEL    ---     0.092       R6C3C.C0 to       R6C3C.F0 SLICE_77
-ROUTE         1     0.267       R6C3C.F0 to       R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c)
-                  --------
-                    1.251   (35.7% logic, 64.3% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C3A.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.286ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
-
-   Delay:               1.257ns  (28.2% logic, 71.8% route), 3 logic levels.
-
- Constraint Details:
-
-      1.257ns physical path delay SLICE_18 to SLICE_96 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.286ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
-CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
-ROUTE         3     0.383       R5C3C.F1 to       R4C4D.A1 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R4C4D.A1 to       R4C4D.F1 SLICE_90
-ROUTE         1     0.267       R4C4D.F1 to       R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c)
-                  --------
-                    1.257   (28.2% logic, 71.8% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R3C4B.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.400ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:               1.371ns  (25.8% logic, 74.2% route), 3 logic levels.
-
- Constraint Details:
-
-      1.371ns physical path delay SLICE_18 to SLICE_88 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.400ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
-CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
-ROUTE         3     0.383       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R4C4A.A0 to       R4C4A.F0 SLICE_72
-ROUTE         2     0.381       R4C4A.F0 to       R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                    1.371   (25.8% logic, 74.2% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R2C4A.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.414ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:               1.385ns  (25.6% logic, 74.4% route), 3 logic levels.
-
- Constraint Details:
-
-      1.385ns physical path delay SLICE_18 to SLICE_19 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.414ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
-CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
-ROUTE         3     0.383       R5C3C.F1 to       R4C4D.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R4C4D.A0 to       R4C4D.F0 SLICE_90
-ROUTE         2     0.395       R4C4D.F0 to       R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                    1.385   (25.6% logic, 74.4% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.537ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:               1.508ns  (23.5% logic, 76.5% route), 3 logic levels.
-
- Constraint Details:
-
-      1.508ns physical path delay SLICE_18 to SLICE_83 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.537ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C3C.CLK to       R5C3C.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.253       R5C3C.Q0 to       R5C3C.B1 CmdEnable
-CTOF_DEL    ---     0.092       R5C3C.B1 to       R5C3C.F1 SLICE_18
-ROUTE         3     0.383       R5C3C.F1 to       R4C4A.A0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R4C4A.A0 to       R4C4A.F0 SLICE_72
-ROUTE         2     0.518       R4C4A.F0 to       R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                    1.508   (23.5% logic, 76.5% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C3C.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R5C4B.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 175.681ns (weighted slack = 351.362ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              XOR8MEG_381  (from PHI2_c -)
-   Destination:    FF         Data in        RA11_358  (to PHI2_c +)
-
-   Delay:               0.670ns  (39.1% logic, 60.9% route), 2 logic levels.
-
- Constraint Details:
-
-      0.670ns physical path delay SLICE_96 to SLICE_31 meets
-     -0.011ns DIN_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.011ns) by 175.681ns
-
- Physical Path Details:
-
-      Data path SLICE_96 to SLICE_31:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R3C4B.CLK to       R3C4B.Q0 SLICE_96 (from PHI2_c)
-ROUTE         1     0.408       R3C4B.Q0 to       R2C5A.D0 XOR8MEG
-CTOF_DEL    ---     0.092       R2C5A.D0 to       R2C5A.F0 SLICE_31
-ROUTE         1     0.000       R2C5A.F0 to      R2C5A.DI0 RA11_N_180 (to PHI2_c)
-                  --------
-                    0.670   (39.1% logic, 60.9% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R3C4B.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_31:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R2C5A.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 176.485ns (weighted slack = 352.970ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i3  (from PHI2_c +)
-   Destination:    FF         Data in        C1Submitted_379  (to PHI2_c -)
-
-   Delay:               1.456ns  (23.4% logic, 76.6% route), 3 logic levels.
-
- Constraint Details:
-
-      1.456ns physical path delay SLICE_98 to SLICE_14 meets
-     -0.029ns CE_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.029ns) by 176.485ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R3C2A.CLK to       R3C2A.Q1 SLICE_98 (from PHI2_c)
-ROUTE         1     0.495       R3C2A.Q1 to       R5C5B.A1 Bank_3
-CTOF_DEL    ---     0.092       R5C5B.A1 to       R5C5B.F1 SLICE_76
-ROUTE         4     0.459       R5C5B.F1 to       R6C3A.D1 n1285
-CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_89
-ROUTE         1     0.161       R6C3A.F1 to       R6C3B.CE PHI2_N_114_enable_1 (to PHI2_c)
-                  --------
-                    1.456   (23.4% logic, 76.6% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R3C2A.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.196       39.PADDI to      R6C3B.CLK PHI2_c
-                  --------
-                    1.196   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_72 to SLICE_72 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_72 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R4C4A.CLK to       R4C4A.Q0 SLICE_72 (from RCLK_c)
-ROUTE         1     0.161       R4C4A.Q0 to       R4C4A.M1 n702 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_72 to SLICE_90 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_72 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R4C4A.CLK to       R4C4A.Q1 SLICE_72 (from RCLK_c)
-ROUTE         1     0.161       R4C4A.Q1 to       R4C4D.M0 n701 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R4C4D.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i7  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i8  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_73 to SLICE_73 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_73 to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C4A.CLK to       R7C4A.Q0 SLICE_73 (from RCLK_c)
-ROUTE         1     0.161       R7C4A.Q0 to       R7C4A.M1 n706 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R7C4A.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R7C4A.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_74 to SLICE_74 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_74 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C3B.CLK to       R5C3B.Q0 SLICE_74 (from RCLK_c)
-ROUTE         1     0.161       R5C3B.Q0 to       R5C3B.M1 n710 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R5C3B.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R5C3B.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_75 to SLICE_73 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_75 to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C4B.CLK to       R7C4B.Q1 SLICE_75 (from RCLK_c)
-ROUTE         1     0.161       R7C4B.Q1 to       R7C4A.M0 n707 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R7C4B.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R7C4A.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i5  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i6  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_75 to SLICE_75 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_75 to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C4B.CLK to       R7C4B.Q0 SLICE_75 (from RCLK_c)
-ROUTE         1     0.161       R7C4B.Q0 to       R7C4B.M1 n708 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R7C4B.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R7C4B.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_84 to SLICE_72 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_84 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R4C4B.CLK to       R4C4B.Q1 SLICE_84 (from RCLK_c)
-ROUTE         1     0.161       R4C4B.Q1 to       R4C4A.M0 n703 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R4C4B.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R4C4A.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_87 to SLICE_74 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_87 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C3D.CLK to       R5C3D.Q1 SLICE_87 (from RCLK_c)
-ROUTE         1     0.161       R5C3D.Q1 to       R5C3B.M0 n711 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_87:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R5C3D.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R5C3B.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i13  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i14  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_90 to SLICE_90 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_90 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R4C4D.CLK to       R4C4D.Q0 SLICE_90 (from RCLK_c)
-ROUTE         1     0.161       R4C4D.Q0 to       R4C4D.M1 n700 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R4C4D.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R4C4D.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.345ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RASr2_353  (from RCLK_c +)
-   Destination:    FF         Data in        RASr3_354  (to RCLK_c +)
-
-   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.324ns physical path delay SLICE_93 to SLICE_93 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
-
- Physical Path Details:
-
-      Data path SLICE_93 to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C5D.CLK to       R7C5D.Q0 SLICE_93 (from RCLK_c)
-ROUTE        16     0.167       R7C5D.Q0 to       R7C5D.M1 RASr2 (to RCLK_c)
-                  --------
-                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R7C5D.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to      R7C5D.CLK RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.220ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     1.733ns  (73.0% logic, 27.0% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_55 and
-      1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets
-      0.000ns hold offset RCLK to RA[10] by 2.220ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C4B.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     0.468       R2C4B.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
-                  --------
-                    1.733   (73.0% logic, 27.0% route), 2 logic levels.
-
-Report:    2.220ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.284ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     1.797ns  (75.5% logic, 24.5% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      1.797ns delay SLICE_64 to RA[9] (totaling 2.284ns) meets
-      0.000ns hold offset RCLK to RA[9] by 2.284ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.243       R2C2A.Q0 to       R2C4A.C1 nRowColSel
-CTOF_DEL    ---     0.092       R2C4A.C1 to       R2C4A.F1 SLICE_88
-ROUTE         1     0.197       R2C4A.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
-                  --------
-                    1.797   (75.5% logic, 24.5% route), 3 logic levels.
-
-Report:    2.284ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.316ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     1.829ns  (74.2% logic, 25.8% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      1.829ns delay SLICE_64 to RA[8] (totaling 2.316ns) meets
-      0.000ns hold offset RCLK to RA[8] by 2.316ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.275       R2C2A.Q0 to       R2C2C.B0 nRowColSel
-CTOF_DEL    ---     0.092       R2C2C.B0 to       R2C2C.F0 SLICE_95
-ROUTE         1     0.197       R2C2C.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
-                  --------
-                    1.829   (74.2% logic, 25.8% route), 3 logic levels.
-
-Report:    2.316ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.652ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.165ns delay SLICE_64 to RA[7] (totaling 2.652ns) meets
-      0.000ns hold offset RCLK to RA[7] by 2.652ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.319       R2C2A.Q0 to       R6C2B.D0 nRowColSel
-CTOF_DEL    ---     0.092       R6C2B.D0 to       R6C2B.F0 SLICE_97
-ROUTE         1     0.489       R6C2B.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
-                  --------
-                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
-
-Report:    2.652ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.579ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     2.092ns  (64.9% logic, 35.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.092ns delay SLICE_64 to RA[6] (totaling 2.579ns) meets
-      0.000ns hold offset RCLK to RA[6] by 2.579ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.243       R2C2A.Q0 to       R3C2A.C0 nRowColSel
-CTOF_DEL    ---     0.092       R3C2A.C0 to       R3C2A.F0 SLICE_98
-ROUTE         1     0.492       R3C2A.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
-                  --------
-                    2.092   (64.9% logic, 35.1% route), 3 logic levels.
-
-Report:    2.579ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.481ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     1.994ns  (68.1% logic, 31.9% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      1.994ns delay SLICE_64 to RA[5] (totaling 2.481ns) meets
-      0.000ns hold offset RCLK to RA[5] by 2.481ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.243       R2C2A.Q0 to       R3C2A.C1 nRowColSel
-CTOF_DEL    ---     0.092       R3C2A.C1 to       R3C2A.F1 SLICE_98
-ROUTE         1     0.394       R3C2A.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
-                  --------
-                    1.994   (68.1% logic, 31.9% route), 3 logic levels.
-
-Report:    2.481ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.219ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     1.732ns  (78.3% logic, 21.7% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      1.732ns delay SLICE_64 to RA[4] (totaling 2.219ns) meets
-      0.000ns hold offset RCLK to RA[4] by 2.219ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.178       R2C2A.Q0 to       R2C2A.D1 nRowColSel
-CTOF_DEL    ---     0.092       R2C2A.D1 to       R2C2A.F1 SLICE_64
-ROUTE         1     0.197       R2C2A.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
-                  --------
-                    1.732   (78.3% logic, 21.7% route), 3 logic levels.
-
-Report:    2.219ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.555ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     2.068ns  (65.6% logic, 34.4% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.068ns delay SLICE_64 to RA[3] (totaling 2.555ns) meets
-      0.000ns hold offset RCLK to RA[3] by 2.555ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.243       R2C2A.Q0 to       R2C3B.C1 nRowColSel
-CTOF_DEL    ---     0.092       R2C3B.C1 to       R2C3B.F1 SLICE_94
-ROUTE         1     0.468       R2C3B.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
-                  --------
-                    2.068   (65.6% logic, 34.4% route), 3 logic levels.
-
-Report:    2.555ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.599ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     2.112ns  (64.3% logic, 35.7% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.112ns delay SLICE_64 to RA[2] (totaling 2.599ns) meets
-      0.000ns hold offset RCLK to RA[2] by 2.599ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.275       R2C2A.Q0 to       R2C2C.B1 nRowColSel
-CTOF_DEL    ---     0.092       R2C2C.B1 to       R2C2C.F1 SLICE_95
-ROUTE         1     0.480       R2C2C.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
-                  --------
-                    2.112   (64.3% logic, 35.7% route), 3 logic levels.
-
-Report:    2.599ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.284ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     1.797ns  (75.5% logic, 24.5% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      1.797ns delay SLICE_64 to RA[1] (totaling 2.284ns) meets
-      0.000ns hold offset RCLK to RA[1] by 2.284ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.243       R2C2A.Q0 to       R2C3B.C0 nRowColSel
-CTOF_DEL    ---     0.092       R2C3B.C0 to       R2C3B.F0 SLICE_94
-ROUTE         1     0.197       R2C3B.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
-                  --------
-                    1.797   (75.5% logic, 24.5% route), 3 logic levels.
-
-Report:    2.284ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.492ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     2.005ns  (67.7% logic, 32.3% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.005ns delay SLICE_64 to RA[0] (totaling 2.492ns) meets
-      0.000ns hold offset RCLK to RA[0] by 2.492ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.292       R2C2A.Q0 to       R3C2B.B1 nRowColSel
-CTOF_DEL    ---     0.092       R3C2B.B1 to       R3C2B.F1 SLICE_92
-ROUTE         1     0.356       R3C2B.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
-                  --------
-                    2.005   (67.7% logic, 32.3% route), 3 logic levels.
-
-Report:    2.492ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_60 and
-      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to nRCS by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C5B.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.197       R2C5B.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.363ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     1.876ns  (67.4% logic, 32.6% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_34 and
-      1.876ns delay SLICE_34 to RCKE (totaling 2.363ns) meets
-      0.000ns hold offset RCLK to RCKE by 2.363ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C2A.CLK to       R5C2A.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     0.611       R5C2A.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
-                  --------
-                    1.876   (67.4% logic, 32.6% route), 2 logic levels.
-
-Report:    2.363ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_63 and
-      1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to nRWE by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R3C5B.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     0.197       R3C5B.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.236ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     1.749ns  (72.3% logic, 27.7% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_61 and
-      1.749ns delay SLICE_61 to nRRAS (totaling 2.236ns) meets
-      0.000ns hold offset RCLK to nRRAS by 2.236ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R4C5A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R4C5A.CLK to       R4C5A.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     0.484       R4C5A.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
-                  --------
-                    1.749   (72.3% logic, 27.7% route), 2 logic levels.
-
-Report:    2.236ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.232ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     1.745ns  (72.5% logic, 27.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_58 and
-      1.745ns delay SLICE_58 to nRCAS (totaling 2.232ns) meets
-      0.000ns hold offset RCLK to nRCAS by 2.232ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C4C.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C4C.CLK to       R2C4C.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     0.480       R2C4C.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
-                  --------
-                    1.745   (72.5% logic, 27.5% route), 2 logic levels.
-
-Report:    2.232ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.443ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     1.956ns  (69.4% logic, 30.6% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      1.956ns delay SLICE_64 to RDQMH (totaling 2.443ns) meets
-      0.000ns hold offset RCLK to RDQMH by 2.443ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.243       R2C2A.Q0 to       R2C4A.C0 nRowColSel
-CTOF_DEL    ---     0.092       R2C4A.C0 to       R2C4A.F0 SLICE_88
-ROUTE         1     0.356       R2C4A.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
-                  --------
-                    1.956   (69.4% logic, 30.6% route), 3 logic levels.
-
-Report:    2.443ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.713ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     2.226ns  (61.0% logic, 39.0% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.226ns delay SLICE_64 to RDQML (totaling 2.713ns) meets
-      0.000ns hold offset RCLK to RDQML by 2.713ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C2A.CLK to       R2C2A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.238       R2C2A.Q0 to       R3C2B.C0 nRowColSel
-CTOF_DEL    ---     0.092       R3C2B.C0 to       R3C2B.F0 SLICE_92
-ROUTE         1     0.631       R3C2B.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
-                  --------
-                    2.226   (61.0% logic, 39.0% route), 3 logic levels.
-
-Report:    2.713ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.220 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.284 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.316 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.579 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.481 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.219 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.555 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.599 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.284 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.492 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.363 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.236 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.232 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.443 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.713 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
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    - - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_drc.log b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_drc.log deleted file mode 100644 index 946f96e..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_drc.log +++ /dev/null @@ -1,15 +0,0 @@ -Results of NGD DRC are available in RAM2GS_drc.log. -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... - - -Running DRC... - -DRC complete with no errors or warnings - -Design Results: - 304 blocks expanded -completed the first expansion -All blocks are expanded and NGD expansion is successful. -Writing NGD file RAM2GS_LCMXO256C_impl1.ngd. diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_lse.twr b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_lse.twr deleted file mode 100644 index 83d5ab2..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_lse.twr +++ /dev/null @@ -1,311 +0,0 @@ --------------------------------------------------------------------------------- -Lattice Synthesis Timing Report, Version -Mon Aug 16 21:32:26 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Design: RAM2GS -Constraint file: -Report level: verbose report, limited to 3 items per constraint --------------------------------------------------------------------------------- - - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] - 122 items scored, 121 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path violates requirements by 10.378ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK Bank_i5 (from PHI2_c +) - Destination: FD1P3AX SP CmdUFMCS_385 (to PHI2_c -) - - Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels. - - Constraint Details: - - 12.614ns data_path Bank_i5 to CmdUFMCS_385 violates - 2.500ns delay constraint less - 0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns - - Path Details: Bank_i5 to CmdUFMCS_385 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c) -Route 1 e 1.220 Bank[5] -LUT4 --- 0.390 B to Z i1856_4_lut -Route 1 e 1.220 n2166 -LUT4 --- 0.390 B to Z i12_4_lut -Route 1 e 1.220 n26 -LUT4 --- 0.390 B to Z i13_4_lut -Route 4 e 1.552 n1285 -LUT4 --- 0.390 B to Z i1830_2_lut_rep_13 -Route 3 e 1.483 n2290 -LUT4 --- 0.390 D to Z i3_4_lut -Route 3 e 1.483 XOR8MEG_N_112 -LUT4 --- 0.390 A to Z i2_3_lut_4_lut -Route 3 e 1.483 PHI2_N_114_enable_7 - -------- - 12.614 (23.4% logic, 76.6% route), 7 logic levels. - - -Error: The following path violates requirements by 10.378ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK Bank_i5 (from PHI2_c +) - Destination: FD1P3AX SP CmdUFMSDI_387 (to PHI2_c -) - - Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels. - - Constraint Details: - - 12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates - 2.500ns delay constraint less - 0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns - - Path Details: Bank_i5 to CmdUFMSDI_387 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c) -Route 1 e 1.220 Bank[5] -LUT4 --- 0.390 B to Z i1856_4_lut -Route 1 e 1.220 n2166 -LUT4 --- 0.390 B to Z i12_4_lut -Route 1 e 1.220 n26 -LUT4 --- 0.390 B to Z i13_4_lut -Route 4 e 1.552 n1285 -LUT4 --- 0.390 B to Z i1830_2_lut_rep_13 -Route 3 e 1.483 n2290 -LUT4 --- 0.390 D to Z i3_4_lut -Route 3 e 1.483 XOR8MEG_N_112 -LUT4 --- 0.390 A to Z i2_3_lut_4_lut -Route 3 e 1.483 PHI2_N_114_enable_7 - -------- - 12.614 (23.4% logic, 76.6% route), 7 logic levels. - - -Error: The following path violates requirements by 10.378ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK Bank_i5 (from PHI2_c +) - Destination: FD1P3AX SP CmdUFMCLK_386 (to PHI2_c -) - - Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels. - - Constraint Details: - - 12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates - 2.500ns delay constraint less - 0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns - - Path Details: Bank_i5 to CmdUFMCLK_386 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c) -Route 1 e 1.220 Bank[5] -LUT4 --- 0.390 B to Z i1856_4_lut -Route 1 e 1.220 n2166 -LUT4 --- 0.390 B to Z i12_4_lut -Route 1 e 1.220 n26 -LUT4 --- 0.390 B to Z i13_4_lut -Route 4 e 1.552 n1285 -LUT4 --- 0.390 B to Z i1830_2_lut_rep_13 -Route 3 e 1.483 n2290 -LUT4 --- 0.390 D to Z i3_4_lut -Route 3 e 1.483 XOR8MEG_N_112 -LUT4 --- 0.390 A to Z i2_3_lut_4_lut -Route 3 e 1.483 PHI2_N_114_enable_7 - -------- - 12.614 (23.4% logic, 76.6% route), 7 logic levels. - -Warning: 12.878 ns is the maximum delay for this constraint. - - - -================================================================================ -Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] - 369 items scored, 244 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path violates requirements by 6.291ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK FS_577__i12 (from RCLK_c +) - Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +) - - Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels. - - Constraint Details: - - 11.027ns data_path FS_577__i12 to LEDEN_392 violates - 5.000ns delay constraint less - 0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns - - Path Details: FS_577__i12 to LEDEN_392 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c) -Route 3 e 1.603 FS[12] -LUT4 --- 0.390 C to Z i4_4_lut -Route 3 e 1.483 n10 -LUT4 --- 0.390 B to Z i5_3_lut_rep_23 -Route 4 e 1.552 n2300 -LUT4 --- 0.390 B to Z i4_3_lut_4_lut -Route 1 e 1.220 n11 -LUT4 --- 0.390 C to Z i2_4_lut_adj_4 -Route 2 e 1.386 n2119 -LUT4 --- 0.390 C to Z i2_3_lut_3_lut -Route 1 e 1.220 RCLK_c_enable_25 - -------- - 11.027 (23.2% logic, 76.8% route), 6 logic levels. - - -Error: The following path violates requirements by 6.291ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK FS_577__i12 (from RCLK_c +) - Destination: FD1P3AX SP n8MEGEN_391 (to RCLK_c +) - - Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels. - - Constraint Details: - - 11.027ns data_path FS_577__i12 to n8MEGEN_391 violates - 5.000ns delay constraint less - 0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns - - Path Details: FS_577__i12 to n8MEGEN_391 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c) -Route 3 e 1.603 FS[12] -LUT4 --- 0.390 C to Z i4_4_lut -Route 3 e 1.483 n10 -LUT4 --- 0.390 B to Z i5_3_lut_rep_23 -Route 4 e 1.552 n2300 -LUT4 --- 0.390 B to Z i4_3_lut_4_lut -Route 1 e 1.220 n11 -LUT4 --- 0.390 C to Z i2_4_lut_adj_4 -Route 2 e 1.386 n2119 -LUT4 --- 0.390 D to Z i1248_4_lut -Route 1 e 1.220 RCLK_c_enable_7 - -------- - 11.027 (23.2% logic, 76.8% route), 6 logic levels. - - -Error: The following path violates requirements by 6.291ns - - Logical Details: Cell type Pin type Cell name (clock net +/-) - - Source: FD1S3AX CK FS_577__i13 (from RCLK_c +) - Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +) - - Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels. - - Constraint Details: - - 11.027ns data_path FS_577__i13 to LEDEN_392 violates - 5.000ns delay constraint less - 0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns - - Path Details: FS_577__i13 to LEDEN_392 - - Name Fanout Delay (ns) Pins Resource(Cell.Net) -L_CO --- 0.613 CK to Q FS_577__i13 (from RCLK_c) -Route 3 e 1.603 FS[13] -LUT4 --- 0.390 B to Z i4_4_lut -Route 3 e 1.483 n10 -LUT4 --- 0.390 B to Z i5_3_lut_rep_23 -Route 4 e 1.552 n2300 -LUT4 --- 0.390 B to Z i4_3_lut_4_lut -Route 1 e 1.220 n11 -LUT4 --- 0.390 C to Z i2_4_lut_adj_4 -Route 2 e 1.386 n2119 -LUT4 --- 0.390 C to Z i2_3_lut_3_lut -Route 1 e 1.220 RCLK_c_enable_25 - -------- - 11.027 (23.2% logic, 76.8% route), 6 logic levels. - -Warning: 11.291 ns is the maximum delay for this constraint. - - -Timing Report Summary --------------- --------------------------------------------------------------------------------- -Constraint | Constraint| Actual|Levels --------------------------------------------------------------------------------- - | | | -create_clock -period 5.000000 -name | | | -clk3 [get_nets nCCAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk2 [get_nets nCRAS_c] | -| -| 0 - | | | -create_clock -period 5.000000 -name | | | -clk1 [get_nets PHI2_c] | 5.000 ns| 25.756 ns| 7 * - | | | -create_clock -period 5.000000 -name | | | -clk0 [get_nets RCLK_c] | 5.000 ns| 11.291 ns| 6 * - | | | --------------------------------------------------------------------------------- - - -2 constraints not met. - --------------------------------------------------------------------------------- -Critical Nets | Loads| Errors| % of total --------------------------------------------------------------------------------- -n1285 | 4| 112| 30.68% - | | | -n26 | 1| 70| 19.18% - | | | -RCLK_c_enable_23 | 16| 64| 17.53% - | | | -n2290 | 3| 64| 17.53% - | | | -XOR8MEG_N_112 | 3| 54| 14.79% - | | | -n2119 | 2| 48| 13.15% - | | | -n2166 | 1| 42| 11.51% - | | | --------------------------------------------------------------------------------- - - -Timing summary: ---------------- - -Timing errors: 365 Score: 2309745 - -Constraints cover 495 paths, 177 nets, and 464 connections (66.5% coverage) - - -Peak memory: 52502528 bytes, TRCE: 1482752 bytes, DLYMAN: 163840 bytes -CPU_TIME_REPORT: 0 secs diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html deleted file mode 100644 index 82208e7..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html +++ /dev/null @@ -1,376 +0,0 @@ - -Lattice Synthesis Timing Report - - -
    Lattice Synthesis Timing Report
---------------------------------------------------------------------------------
-Lattice Synthesis Timing Report, Version  
-Mon Aug 16 21:32:26 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Design:     RAM2GS
-Constraint file:  
-Report level:    verbose report, limited to 3 items per constraint
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
-            122 items scored, 121 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 10.378ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdUFMCS_385  (to PHI2_c -)
-
-   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
-      2.500ns delay constraint less
-      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
-
- Path Details: Bank_i5 to CmdUFMCS_385
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
-Route         1   e 1.220                                  Bank[5]
-LUT4        ---     0.390              B to Z              i1856_4_lut
-Route         1   e 1.220                                  n2166
-LUT4        ---     0.390              B to Z              i12_4_lut
-Route         1   e 1.220                                  n26
-LUT4        ---     0.390              B to Z              i13_4_lut
-Route         4   e 1.552                                  n1285
-LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
-Route         3   e 1.483                                  n2290
-LUT4        ---     0.390              D to Z              i3_4_lut
-Route         3   e 1.483                                  XOR8MEG_N_112
-LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
-Route         3   e 1.483                                  PHI2_N_114_enable_7
-                  --------
-                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
-
-
-Error:  The following path violates requirements by 10.378ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
-      2.500ns delay constraint less
-      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
-
- Path Details: Bank_i5 to CmdUFMSDI_387
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
-Route         1   e 1.220                                  Bank[5]
-LUT4        ---     0.390              B to Z              i1856_4_lut
-Route         1   e 1.220                                  n2166
-LUT4        ---     0.390              B to Z              i12_4_lut
-Route         1   e 1.220                                  n26
-LUT4        ---     0.390              B to Z              i13_4_lut
-Route         4   e 1.552                                  n1285
-LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
-Route         3   e 1.483                                  n2290
-LUT4        ---     0.390              D to Z              i3_4_lut
-Route         3   e 1.483                                  XOR8MEG_N_112
-LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
-Route         3   e 1.483                                  PHI2_N_114_enable_7
-                  --------
-                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
-
-
-Error:  The following path violates requirements by 10.378ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdUFMCLK_386  (to PHI2_c -)
-
-   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
-      2.500ns delay constraint less
-      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
-
- Path Details: Bank_i5 to CmdUFMCLK_386
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
-Route         1   e 1.220                                  Bank[5]
-LUT4        ---     0.390              B to Z              i1856_4_lut
-Route         1   e 1.220                                  n2166
-LUT4        ---     0.390              B to Z              i12_4_lut
-Route         1   e 1.220                                  n26
-LUT4        ---     0.390              B to Z              i13_4_lut
-Route         4   e 1.552                                  n1285
-LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
-Route         3   e 1.483                                  n2290
-LUT4        ---     0.390              D to Z              i3_4_lut
-Route         3   e 1.483                                  XOR8MEG_N_112
-LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
-Route         3   e 1.483                                  PHI2_N_114_enable_7
-                  --------
-                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
-
-Warning: 12.878 ns is the maximum delay for this constraint.
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
-            369 items scored, 244 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 6.291ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
-   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
-
-   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.027ns data_path FS_577__i12 to LEDEN_392 violates
-      5.000ns delay constraint less
-      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
-
- Path Details: FS_577__i12 to LEDEN_392
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
-Route         3   e 1.603                                  FS[12]
-LUT4        ---     0.390              C to Z              i4_4_lut
-Route         3   e 1.483                                  n10
-LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
-Route         4   e 1.552                                  n2300
-LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
-Route         1   e 1.220                                  n11
-LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
-Route         2   e 1.386                                  n2119
-LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
-Route         1   e 1.220                                  RCLK_c_enable_25
-                  --------
-                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 6.291ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
-   Destination:    FD1P3AX    SP             n8MEGEN_391  (to RCLK_c +)
-
-   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
-      5.000ns delay constraint less
-      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
-
- Path Details: FS_577__i12 to n8MEGEN_391
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
-Route         3   e 1.603                                  FS[12]
-LUT4        ---     0.390              C to Z              i4_4_lut
-Route         3   e 1.483                                  n10
-LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
-Route         4   e 1.552                                  n2300
-LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
-Route         1   e 1.220                                  n11
-LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
-Route         2   e 1.386                                  n2119
-LUT4        ---     0.390              D to Z              i1248_4_lut
-Route         1   e 1.220                                  RCLK_c_enable_7
-                  --------
-                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 6.291ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_577__i13  (from RCLK_c +)
-   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
-
-   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.027ns data_path FS_577__i13 to LEDEN_392 violates
-      5.000ns delay constraint less
-      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
-
- Path Details: FS_577__i13 to LEDEN_392
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              FS_577__i13 (from RCLK_c)
-Route         3   e 1.603                                  FS[13]
-LUT4        ---     0.390              B to Z              i4_4_lut
-Route         3   e 1.483                                  n10
-LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
-Route         4   e 1.552                                  n2300
-LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
-Route         1   e 1.220                                  n11
-LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
-Route         2   e 1.386                                  n2119
-LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
-Route         1   e 1.220                                  RCLK_c_enable_25
-                  --------
-                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
-
-Warning: 11.291 ns is the maximum delay for this constraint.
-
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |     5.000 ns|    25.756 ns|     7 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |     5.000 ns|    11.291 ns|     6 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
---------------------------------------------------------------------------------
-Critical Nets                           |   Loads|  Errors| % of total
---------------------------------------------------------------------------------
-n1285                                   |       4|     112|     30.68%
-                                        |        |        |
-n26                                     |       1|      70|     19.18%
-                                        |        |        |
-RCLK_c_enable_23                        |      16|      64|     17.53%
-                                        |        |        |
-n2290                                   |       3|      64|     17.53%
-                                        |        |        |
-XOR8MEG_N_112                           |       3|      54|     14.79%
-                                        |        |        |
-n2119                                   |       2|      48|     13.15%
-                                        |        |        |
-n2166                                   |       1|      42|     11.51%
-                                        |        |        |
---------------------------------------------------------------------------------
-
-
-Timing summary:
----------------
-
-Timing errors: 365  Score: 2309745
-
-Constraints cover  495 paths, 177 nets, and 464 connections (66.5% coverage)
-
-
-Peak memory: 52502528 bytes, TRCE: 1482752 bytes, DLYMAN: 163840 bytes
-CPU_TIME_REPORT: 0 secs 
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    - - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_prim.v b/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_prim.v deleted file mode 100644 index d942735..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_prim.v +++ /dev/null @@ -1,789 +0,0 @@ -// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.0.240.2 -// Netlist written on Mon Aug 16 21:32:26 2021 -// -// Verilog Description of module RAM2GS -// - -module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, - LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, - nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1[8:14]) - input PHI2; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) - input [9:0]MAin; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) - input [1:0]CROW; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18]) - input [7:0]Din; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) - output [7:0]Dout; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) - input nCCAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) - input nCRAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) - input nFWE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12]) - output LED; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12]) - output [1:0]RBA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) - output [11:0]RA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - inout [7:0]RD; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) - output nRCS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17]) - input RCLK; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12]) - output RCKE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17]) - output nRWE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49]) - output nRRAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28]) - output nRCAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39]) - output RDQMH; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21]) - output RDQML; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14]) - output nUFMCS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19]) - output UFMCLK; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19]) - output UFMSDI; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19]) - input UFMSDO; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14]) - - wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) - wire nCCAS_c /* synthesis is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) - wire nCRAS_c /* synthesis is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) - wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12]) - wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) - wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) - wire PHI2_N_114 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(38[6:13]) - - wire GND_net, VCC_net, LEDEN, PHI2r, PHI2r2, PHI2r3, RASr, - RASr2, RASr3, CASr, CASr2, CASr3, FWEr, CBR, Din_c_7, - Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0, - n2131, n33, PHI2_N_114_enable_2, n1; - wire [7:0]Bank; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(31[12:16]) - - wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, - MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, - nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, - nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, n980; - wire [9:0]RowA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(51[12:16]) - - wire RA_c_9, RA_c_8, RA_c_7, RA_c_6, RA_c_5, RA_c_4, RA_c_3, - RA_c_2, RA_c_1, RA_c_0, RDQML_c, RDQMH_c; - wire [7:0]WRD; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(59[12:15]) - - wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, - CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, - CmdUFMCS, InitReady, Ready; - wire [17:0]FS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(86[13:15]) - - wire LED_N_90, RA11_N_180, n2164, n1895, n2294, n4, PHI2_N_114_enable_6, - n1881, RASr2_N_63, RCKE_N_128, nRowColSel_N_35, nRWE_N_178, - RCKEEN_N_126, nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, - nRowColSel_N_28, n1880, n4_adj_1, n2286, RCKEEN_N_117, nRWE_N_174, - RCKEEN_N_116, nRCS_N_135, nRCAS_N_161, nRWE_N_173, nRWE_N_172, - n1377, Ready_N_272, n2287, n26, Ready_N_268, nRCS_N_132, - nRCAS_N_157, nRWE_N_167, RCKEEN_N_115, n2290, n2289, n1361, - n1369, ADSubmitted_N_234, CmdEnable_N_236, C1Submitted_N_225, - XOR8MEG_N_112, n2098, PHI2_N_114_enable_1, n2248, Cmdn8MEGEN_N_248, - RCLK_c_enable_7, n2244, n2117, LEDEN_N_88, RCLK_c_enable_6, - UFMSDO_N_74, n2243, RCLK_c_enable_24, n8MEGEN_N_94, UFMCLK_N_212, - UFMSDI_N_219, n2242, n2114, n2080, PHI2_N_114_enable_7, n12, - n699, n700, n701, n702, n703, n705, n706, n707, n708, - n709, n710, n711, n11, n2076, n2119, n1368, n12_adj_2, - n1878, PHI2_N_114_enable_8, n2308, n2291, n2307, n11_adj_3, - n973, n1135, n78, n79, n80, n81, n82, n83, n84, n85, - n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, - n1348, n50, n1877, RCLK_c_enable_23, n1876, n1875, n2293, - n2306, RCLK_c_enable_4, n2170, RCLK_c_enable_25, RCLK_c_enable_3, - n2128, n2103, n2304, n2386, n1879, n1874, n2310, n974, - n975, n962, n976, n2168, n977, n2245, n978, n2122, n979, - Dout_c, n2166, n2302, n2108, n2301, n2387, n1285, n2300, - n1628, n1627, n2299, n18, n2385, n2309, n2298, n2292, - n2297, n2154, n10, n2296, n2295; - - VHI i2 (.Z(VCC_net)); - INV i1963 (.A(nCCAS_c), .Z(nCCAS_N_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) - FD1S3AX PHI2r2_350 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) - defparam PHI2r2_350.GSR = "ENABLED"; - ORCALUT4 i2_3_lut_4_lut (.A(XOR8MEG_N_112), .B(n2298), .C(n2296), - .D(Din_c_5), .Z(PHI2_N_114_enable_7)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; - defparam i2_3_lut_4_lut.init = 16'h0800; - ORCALUT4 i1_2_lut_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), .Z(n4)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) - defparam i1_2_lut_3_lut.init = 16'hfdfd; - FD1S3AX PHI2r3_351 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) - defparam PHI2r3_351.GSR = "ENABLED"; - FD1S3AX RASr_352 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) - defparam RASr_352.GSR = "ENABLED"; - FD1S3AX RASr2_353 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) - defparam RASr2_353.GSR = "ENABLED"; - FD1S3AX RASr3_354 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) - defparam RASr3_354.GSR = "ENABLED"; - FD1S3AX CASr_355 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) - defparam CASr_355.GSR = "ENABLED"; - FD1S3AX CASr2_356 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) - defparam CASr2_356.GSR = "ENABLED"; - FD1S3AX CASr3_357 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) - defparam CASr3_357.GSR = "ENABLED"; - FD1S3IX RA11_358 (.D(RA11_N_180), .CK(PHI2_c), .CD(n2307), .Q(RA_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) - defparam RA11_358.GSR = "ENABLED"; - FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RowA_i0.GSR = "ENABLED"; - FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) - defparam WRD_i0.GSR = "ENABLED"; - FD1S3AX FWEr_362 (.D(n2306), .CK(nCRAS_N_9), .Q(FWEr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam FWEr_362.GSR = "ENABLED"; - FD1S3AX CBR_363 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam CBR_363.GSR = "ENABLED"; - FD1S3IX ADSubmitted_380 (.D(n1361), .CK(PHI2_N_114), .CD(C1Submitted_N_225), - .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) - defparam ADSubmitted_380.GSR = "ENABLED"; - ORCALUT4 MAin_9__I_0_400_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), - .Z(RA_c_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) - defparam MAin_9__I_0_400_i5_3_lut.init = 16'hcaca; - ORCALUT4 i1_2_lut (.A(FS[10]), .B(n2076), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A (B)) */ ; - defparam i1_2_lut.init = 16'h8888; - CCU2 FS_577_add_4_10 (.A0(FS[8]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[9]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1877), - .COUT1(n1878), .S0(n87), .S1(n86)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577_add_4_10.INIT0 = 16'hfaaa; - defparam FS_577_add_4_10.INIT1 = 16'hfaaa; - defparam FS_577_add_4_10.INJECT1_0 = "NO"; - defparam FS_577_add_4_10.INJECT1_1 = "NO"; - FD1S3AX RCKE_368 (.D(RCKE_N_128), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(141[9] 144[5]) - defparam RCKE_368.GSR = "ENABLED"; - FD1P3AY nRCS_369 (.D(nRCS_N_132), .SP(RCLK_c_enable_4), .CK(RCLK_c), - .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam nRCS_369.GSR = "ENABLED"; - FD1S3IX nRowColSel_375 (.D(n1368), .CK(RCLK_c), .CD(n2299), .Q(nRowColSel)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam nRowColSel_375.GSR = "ENABLED"; - ORCALUT4 n1_bdd_4_lut (.A(n1), .B(n1627), .C(nRWE_N_178), .D(nRowColSel_N_35), - .Z(nRWE_N_174)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; - defparam n1_bdd_4_lut.init = 16'hf0dd; - ORCALUT4 i2_3_lut_rep_31 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), - .Z(n2308)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; - defparam i2_3_lut_rep_31.init = 16'h0808; - ORCALUT4 i1_2_lut_2_lut_4_lut (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), - .D(InitReady), .Z(RCLK_c_enable_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ; - defparam i1_2_lut_2_lut_4_lut.init = 16'h08ff; - CCU2 FS_577_add_4_8 (.A0(FS[6]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[7]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1876), - .COUT1(n1877), .S0(n89), .S1(n88)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577_add_4_8.INIT0 = 16'hfaaa; - defparam FS_577_add_4_8.INIT1 = 16'hfaaa; - defparam FS_577_add_4_8.INJECT1_0 = "NO"; - defparam FS_577_add_4_8.INJECT1_1 = "NO"; - ORCALUT4 i1_4_lut (.A(nRowColSel_N_34), .B(n1), .C(n2304), .D(nRowColSel_N_33), - .Z(n2117)) /* synthesis lut_function=(!(A+(B (C (D))+!B (C+!(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) - defparam i1_4_lut.init = 16'h0544; - ORCALUT4 i3_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n2290), - .Z(XOR8MEG_N_112)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; - defparam i3_4_lut.init = 16'h0040; - ORCALUT4 i4_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[6]), .D(n2168), - .Z(n11)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) - defparam i4_3_lut_4_lut.init = 16'hfdff; - FD1S3IX S_FSM_i2 (.D(n1135), .CK(RCLK_c), .CD(n2302), .Q(nRowColSel_N_34)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam S_FSM_i2.GSR = "ENABLED"; - ORCALUT4 i1_4_lut_adj_1 (.A(nRowColSel), .B(n1627), .C(nRowColSel_N_28), - .D(nRowColSel_N_32), .Z(n1368)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B+!(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i1_4_lut_adj_1.init = 16'hcfee; - FD1S3AY nRRAS_370 (.D(n33), .CK(RCLK_c), .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam nRRAS_370.GSR = "ENABLED"; - ORCALUT4 i1055_3_lut_4_lut (.A(MAin_c_1), .B(n2290), .C(ADSubmitted), - .D(ADSubmitted_N_234), .Z(n1361)) /* synthesis lut_function=(A (B (C+(D))+!B (D))+!A (C+(D))) */ ; - defparam i1055_3_lut_4_lut.init = 16'hffd0; - ORCALUT4 i2_3_lut (.A(FWEr), .B(CASr3), .C(CBR), .Z(nRowColSel_N_28)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(230[16:37]) - defparam i2_3_lut.init = 16'hfdfd; - BB Dout_pad_7__688 (.I(WRD[7]), .T(n962), .B(RD[7]), .O(n973)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) - FD1P3AY nRCAS_371 (.D(nRCAS_N_157), .SP(RCLK_c_enable_4), .CK(RCLK_c), - .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam nRCAS_371.GSR = "ENABLED"; - FD1P3AY nRWE_372 (.D(nRWE_N_167), .SP(RCLK_c_enable_3), .CK(RCLK_c), - .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam nRWE_372.GSR = "ENABLED"; - FD1S3JX RA10_373 (.D(n2128), .CK(RCLK_c), .PD(nRWE_N_172), .Q(n980)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam RA10_373.GSR = "ENABLED"; - FD1P3AX RCKEEN_374 (.D(RCKEEN_N_115), .SP(RCLK_c_enable_4), .CK(RCLK_c), - .Q(RCKEEN)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam RCKEEN_374.GSR = "ENABLED"; - ORCALUT4 i2_4_lut (.A(n2122), .B(n2295), .C(Din_c_2), .D(n2131), - .Z(C1Submitted_N_225)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; - defparam i2_4_lut.init = 16'h0008; - FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RBA__i1.GSR = "ENABLED"; - ORCALUT4 Din_7__I_0_442_i6_2_lut_rep_32 (.A(Din_c_6), .B(Din_c_7), .Z(n2385)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) - defparam Din_7__I_0_442_i6_2_lut_rep_32.init = 16'heeee; - ORCALUT4 i1248_4_lut (.A(FS[5]), .B(n2308), .C(InitReady), .D(n2119), - .Z(RCLK_c_enable_7)) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) - defparam i1248_4_lut.init = 16'hc5c0; - ORCALUT4 i2_3_lut_4_lut_adj_2 (.A(nRowColSel_N_32), .B(n2299), .C(nRowColSel_N_34), - .D(nRowColSel_N_33), .Z(RCLK_c_enable_4)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i2_3_lut_4_lut_adj_2.init = 16'hfffe; - ORCALUT4 i1437_4_lut (.A(UFMSDO_c), .B(Cmdn8MEGEN), .C(FS[10]), .D(n4), - .Z(n8MEGEN_N_94)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) - defparam i1437_4_lut.init = 16'hcc5c; - FD1P3AX IS_FSM__i0 (.D(Ready_N_272), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(nRCS_N_135)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i0.GSR = "ENABLED"; - ORCALUT4 i1_2_lut_adj_3 (.A(RASr2), .B(RCKE_c), .Z(nRWE_N_178)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) - defparam i1_2_lut_adj_3.init = 16'hbbbb; - ORCALUT4 i2_4_lut_adj_4 (.A(n2294), .B(FS[10]), .C(n11), .D(n12), - .Z(n2119)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) - defparam i2_4_lut_adj_4.init = 16'h0008; - FD1P3JX C1Submitted_379 (.D(n2386), .SP(PHI2_N_114_enable_1), .PD(C1Submitted_N_225), - .CK(PHI2_N_114), .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) - defparam C1Submitted_379.GSR = "ENABLED"; - FD1S3JX nUFMCS_388 (.D(n1348), .CK(RCLK_c), .PD(LEDEN_N_88), .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) - defparam nUFMCS_388.GSR = "ENABLED"; - ORCALUT4 m1_lut (.Z(n2387)) /* synthesis lut_function=1, syn_instantiated=1 */ ; - defparam m1_lut.init = 16'hffff; - ORCALUT4 i2_4_lut_adj_5 (.A(n2108), .B(MAin_c_1), .C(C1Submitted), - .D(MAin_c_0), .Z(n2098)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; - defparam i2_4_lut_adj_5.init = 16'h0800; - ORCALUT4 i5_4_lut (.A(FS[9]), .B(FS[4]), .C(FS[8]), .D(FS[7]), .Z(n12)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ; - defparam i5_4_lut.init = 16'hfffb; - FD1S3AX FS_577__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i0.GSR = "ENABLED"; - ORCALUT4 i2_3_lut_adj_6 (.A(n2122), .B(ADSubmitted), .C(MAin_c_0), - .Z(n2080)) /* synthesis lut_function=(!((B+(C))+!A)) */ ; - defparam i2_3_lut_adj_6.init = 16'h0202; - ORCALUT4 i1419_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(58[17:46]) - defparam i1419_2_lut.init = 16'hbbbb; - ORCALUT4 n50_bdd_4_lut_1911 (.A(n50), .B(RASr2), .C(RCKE_c), .D(nRowColSel_N_35), - .Z(n2242)) /* synthesis lut_function=(!(A (B (D)+!B (C (D)))+!A (B+(C+!(D))))) */ ; - defparam n50_bdd_4_lut_1911.init = 16'h03aa; - ORCALUT4 i1893_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; - defparam i1893_2_lut.init = 16'h7777; - FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) - defparam Bank_i0.GSR = "ENABLED"; - ORCALUT4 i1858_4_lut (.A(FS[1]), .B(FS[0]), .C(FS[2]), .D(FS[3]), - .Z(n2168)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i1858_4_lut.init = 16'h8000; - ORCALUT4 i1_2_lut_3_lut_adj_7 (.A(MAin_c_1), .B(n1285), .C(MAin_c_0), - .Z(n2131)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31]) - defparam i1_2_lut_3_lut_adj_7.init = 16'hfdfd; - ORCALUT4 i22_4_lut (.A(FS[4]), .B(CmdUFMCLK), .C(InitReady), .D(n2076), - .Z(UFMCLK_N_212)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) - defparam i22_4_lut.init = 16'hc0ca; - ORCALUT4 i5_4_lut_adj_8 (.A(FS[14]), .B(FS[16]), .C(FS[13]), .D(FS[12]), - .Z(n12_adj_2)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i5_4_lut_adj_8.init = 16'h8000; - ORCALUT4 i1889_4_lut_then_4_lut (.A(n2117), .B(RCKE_c), .C(RASr2), - .D(nRowColSel_N_35), .Z(n2310)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A (B (D)+!B (C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) - defparam i1889_4_lut_then_4_lut.init = 16'h0355; - ORCALUT4 i1889_4_lut_else_4_lut (.A(InitReady), .B(nRCS_N_135), .C(RASr2), - .D(nRowColSel_N_35), .Z(n2309)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) - defparam i1889_4_lut_else_4_lut.init = 16'hdfff; - CCU2 FS_577_add_4_18 (.A0(FS[16]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[17]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1881), - .S0(n79), .S1(n78)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577_add_4_18.INIT0 = 16'hfaaa; - defparam FS_577_add_4_18.INIT1 = 16'hfaaa; - defparam FS_577_add_4_18.INJECT1_0 = "NO"; - defparam FS_577_add_4_18.INJECT1_1 = "NO"; - ORCALUT4 UFMSDO_I_0_1_lut (.A(UFMSDO_c), .Z(UFMSDO_N_74)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(378[53:60]) - defparam UFMSDO_I_0_1_lut.init = 16'h5555; - FD1S3IX S_FSM_i3 (.D(n1135), .CK(RCLK_c), .CD(n1377), .Q(nRowColSel_N_33)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam S_FSM_i3.GSR = "ENABLED"; - ORCALUT4 i1897_2_lut_rep_14_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), - .Z(n2291)) /* synthesis lut_function=(!(A+(B+(C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) - defparam i1897_2_lut_rep_14_3_lut.init = 16'h0101; - ORCALUT4 i1878_2_lut_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[10]), - .D(InitReady), .Z(LEDEN_N_88)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) - defparam i1878_2_lut_3_lut_4_lut.init = 16'h0001; - ORCALUT4 i1884_4_lut (.A(MAin_c_0), .B(n2290), .C(n2286), .D(MAin_c_1), - .Z(PHI2_N_114_enable_8)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ; - defparam i1884_4_lut.init = 16'h0302; - FD1S3AX PHI2r_349 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5]) - defparam PHI2r_349.GSR = "ENABLED"; - ORCALUT4 i2_3_lut_rep_21_4_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), - .D(Din_c_4), .Z(n2298)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) - defparam i2_3_lut_rep_21_4_lut.init = 16'hfffe; - ORCALUT4 i1830_2_lut_rep_13 (.A(nFWE_c), .B(n1285), .Z(n2290)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1830_2_lut_rep_13.init = 16'heeee; - PFUMX i1912 (.BLUT(n2243), .ALUT(n2242), .C0(Ready), .Z(n2244)); - FD1S3AX S_FSM_i1 (.D(RASr2_N_63), .CK(RCLK_c), .Q(nRowColSel_N_35)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam S_FSM_i1.GSR = "ENABLED"; - ORCALUT4 i1886_2_lut (.A(nRowColSel_N_32), .B(RASr2), .Z(n1135)) /* synthesis lut_function=(!(A+!(B))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i1886_2_lut.init = 16'h4444; - ORCALUT4 n50_bdd_4_lut (.A(n50), .B(InitReady), .C(RASr2), .D(nRowColSel_N_35), - .Z(n2243)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C)))) */ ; - defparam n50_bdd_4_lut.init = 16'h3fbf; - ORCALUT4 i1034_2_lut (.A(ADSubmitted_N_234), .B(C1Submitted_N_225), - .Z(CmdEnable_N_236)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1034_2_lut.init = 16'heeee; - ORCALUT4 i2_3_lut_4_lut_adj_9 (.A(Din_c_6), .B(Din_c_7), .C(XOR8MEG_N_112), - .D(Din_c_4), .Z(PHI2_N_114_enable_6)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) - defparam i2_3_lut_4_lut_adj_9.init = 16'h1000; - ORCALUT4 i1832_2_lut_rep_19_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), - .Z(n2296)) /* synthesis lut_function=(A+(B+!(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31]) - defparam i1832_2_lut_rep_19_3_lut.init = 16'hefef; - FD1S3IX S_FSM_i4 (.D(n1628), .CK(RCLK_c), .CD(RASr2_N_63), .Q(nRowColSel_N_32)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam S_FSM_i4.GSR = "ENABLED"; - ORCALUT4 i1424_2_lut_rep_27 (.A(FWEr), .B(CBR), .Z(n2304)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1424_2_lut_rep_27.init = 16'heeee; - ORCALUT4 i2_3_lut_adj_10 (.A(Din_c_3), .B(Din_c_6), .C(Din_c_5), .Z(n2122)) /* synthesis lut_function=(!(A+((C)+!B))) */ ; - defparam i2_3_lut_adj_10.init = 16'h0404; - ORCALUT4 i1429_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(RCKEEN_N_126)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; - defparam i1429_2_lut_3_lut.init = 16'h1f1f; - ORCALUT4 i4_4_lut (.A(FS[14]), .B(FS[13]), .C(FS[12]), .D(FS[15]), - .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) - defparam i4_4_lut.init = 16'hfffe; - ORCALUT4 i5_3_lut_rep_23 (.A(FS[16]), .B(n10), .C(FS[17]), .Z(n2300)) /* synthesis lut_function=(A+(B+(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) - defparam i5_3_lut_rep_23.init = 16'hfefe; - ORCALUT4 i1_4_lut_adj_11 (.A(n2244), .B(n2297), .C(n18), .D(Ready), - .Z(n33)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) - defparam i1_4_lut_adj_11.init = 16'hfaee; - ORCALUT4 i1_2_lut_rep_16_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), - .Z(n2293)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) - defparam i1_2_lut_rep_16_4_lut.init = 16'hfeff; - ORCALUT4 i3_4_lut_adj_12 (.A(CBR), .B(FWEr), .C(CASr2), .D(CASr3), - .Z(n1)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; - defparam i3_4_lut_adj_12.init = 16'h0040; - ORCALUT4 i1_2_lut_adj_13 (.A(nRowColSel_N_34), .B(nRowColSel_N_33), - .Z(n1627)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i1_2_lut_adj_13.init = 16'heeee; - ORCALUT4 i1420_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n962)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1420_2_lut.init = 16'heeee; - ORCALUT4 i1_1_lut_rep_29 (.A(nFWE_c), .Z(n2306)) /* synthesis lut_function=(!(A)) */ ; - defparam i1_1_lut_rep_29.init = 16'h5555; - ORCALUT4 Cmdn8MEGEN_I_84_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_5), - .D(n2296), .Z(Cmdn8MEGEN_N_248)) /* synthesis lut_function=(A (B (C+(D)))+!A (B+!(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(316[13] 322[7]) - defparam Cmdn8MEGEN_I_84_4_lut.init = 16'hccc5; - ORCALUT4 i1069_1_lut (.A(nRowColSel_N_34), .Z(n1377)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i1069_1_lut.init = 16'h5555; - ORCALUT4 n2080_bdd_4_lut (.A(n2080), .B(n2098), .C(Din_c_2), .D(n2114), - .Z(n2286)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ; - defparam n2080_bdd_4_lut.init = 16'hca00; - ORCALUT4 RASr2_I_0_1_lut (.A(RASr2), .Z(RASr2_N_63)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[40:46]) - defparam RASr2_I_0_1_lut.init = 16'h5555; - ORCALUT4 i847_2_lut_4_lut (.A(n2385), .B(Din_c_4), .C(Din_c_5), .D(XOR8MEG_N_112), - .Z(PHI2_N_114_enable_2)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(310[8:22]) - defparam i847_2_lut_4_lut.init = 16'h0100; - ORCALUT4 i1_4_lut_adj_14 (.A(n2108), .B(MAin_c_0), .C(n4_adj_1), .D(n2289), - .Z(ADSubmitted_N_234)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24]) - defparam i1_4_lut_adj_14.init = 16'h0080; - ORCALUT4 i1_2_lut_adj_15 (.A(nRowColSel_N_33), .B(CASr2), .Z(n11_adj_3)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(48[6:16]) - defparam i1_2_lut_adj_15.init = 16'hbbbb; - FD1S3AX FS_577__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i17.GSR = "ENABLED"; - ORCALUT4 i1_2_lut_3_lut_3_lut (.A(nFWE_c), .B(Din_c_2), .C(n2114), - .Z(n4_adj_1)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; - defparam i1_2_lut_3_lut_3_lut.init = 16'h4040; - FD1S3AX FS_577__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i16.GSR = "ENABLED"; - FD1S3AX FS_577__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i15.GSR = "ENABLED"; - ORCALUT4 nRWE_I_0_428_4_lut (.A(n2164), .B(nRWE_N_174), .C(Ready), - .D(n2292), .Z(nRWE_N_167)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(232[12] 284[6]) - defparam nRWE_I_0_428_4_lut.init = 16'hcfc5; - ORCALUT4 i1257_3_lut (.A(n1895), .B(CmdUFMSDI), .C(InitReady), .Z(UFMSDI_N_219)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) - defparam i1257_3_lut.init = 16'hcaca; - ORCALUT4 RCKE_I_0_423_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), - .Z(RCKE_N_128)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[11:55]) - defparam RCKE_I_0_423_4_lut.init = 16'hcfc8; - FD1P3AX InitReady_367 (.D(n2387), .SP(RCLK_c_enable_6), .CK(RCLK_c), - .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(134[9] 138[5]) - defparam InitReady_367.GSR = "ENABLED"; - ORCALUT4 i1_2_lut_adj_16 (.A(nRowColSel_N_32), .B(nRowColSel_N_33), - .Z(n1628)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i1_2_lut_adj_16.init = 16'heeee; - ORCALUT4 i1854_2_lut (.A(nRCAS_N_161), .B(nRWE_N_173), .Z(n2164)) /* synthesis lut_function=(A+(B)) */ ; - defparam i1854_2_lut.init = 16'heeee; - ORCALUT4 i1_2_lut_rep_17_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), - .Z(n2294)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37]) - defparam i1_2_lut_rep_17_4_lut.init = 16'hfffe; - ORCALUT4 i1881_2_lut_rep_24 (.A(RASr2), .B(InitReady), .Z(n2301)) /* synthesis lut_function=(!(A (B))) */ ; - defparam i1881_2_lut_rep_24.init = 16'h7777; - GSR GSR_INST (.GSR(VCC_net)); - ORCALUT4 i1_2_lut_rep_18_2_lut (.A(nFWE_c), .B(n2114), .Z(n2295)) /* synthesis lut_function=(!(A+!(B))) */ ; - defparam i1_2_lut_rep_18_2_lut.init = 16'h4444; - FD1S3AX FS_577__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i14.GSR = "ENABLED"; - ORCALUT4 i2_3_lut_3_lut (.A(InitReady), .B(FS[5]), .C(n2119), .Z(RCLK_c_enable_25)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(384[16:26]) - defparam i2_3_lut_3_lut.init = 16'h4040; - ORCALUT4 i2_3_lut_adj_17 (.A(Din_c_6), .B(Din_c_5), .C(Din_c_3), .Z(n2108)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24]) - defparam i2_3_lut_adj_17.init = 16'h4040; - ORCALUT4 i2_4_lut_adj_18 (.A(FS[6]), .B(n2293), .C(n2103), .D(FS[10]), - .Z(n1895)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam i2_4_lut_adj_18.init = 16'h0020; - ORCALUT4 i1_4_lut_adj_19 (.A(FS[8]), .B(FS[7]), .C(FS[5]), .D(FS[9]), - .Z(n2103)) /* synthesis lut_function=(!(A+(B (D)+!B !(C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(339[4] 372[11]) - defparam i1_4_lut_adj_19.init = 16'h1044; - FD1P3AX XOR8MEG_381 (.D(Din_c_0), .SP(PHI2_N_114_enable_2), .CK(PHI2_N_114), - .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) - defparam XOR8MEG_381.GSR = "ENABLED"; - FD1P3AX n8MEGEN_391 (.D(n8MEGEN_N_94), .SP(RCLK_c_enable_7), .CK(RCLK_c), - .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) - defparam n8MEGEN_391.GSR = "ENABLED"; - FD1P3AX Ready_377 (.D(n2387), .SP(Ready_N_268), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam Ready_377.GSR = "ENABLED"; - ORCALUT4 MAin_9__I_0_400_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), - .Z(RA_c_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) - defparam MAin_9__I_0_400_i2_3_lut.init = 16'hcaca; - FD1P3AX CmdUFMCLK_386 (.D(Din_c_1), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), - .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) - defparam CmdUFMCLK_386.GSR = "ENABLED"; - FD1P3AX CmdUFMSDI_387 (.D(Din_c_0), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), - .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) - defparam CmdUFMSDI_387.GSR = "ENABLED"; - FD1P3AX Cmdn8MEGEN_383 (.D(Cmdn8MEGEN_N_248), .SP(PHI2_N_114_enable_6), - .CK(PHI2_N_114), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) - defparam Cmdn8MEGEN_383.GSR = "ENABLED"; - FD1P3AX CmdSubmitted_384 (.D(n2387), .SP(PHI2_N_114_enable_6), .CK(PHI2_N_114), - .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) - defparam CmdSubmitted_384.GSR = "ENABLED"; - CCU2 FS_577_add_4_6 (.A0(FS[4]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[5]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1875), - .COUT1(n1876), .S0(n91), .S1(n90)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577_add_4_6.INIT0 = 16'hfaaa; - defparam FS_577_add_4_6.INIT1 = 16'hfaaa; - defparam FS_577_add_4_6.INJECT1_0 = "NO"; - defparam FS_577_add_4_6.INJECT1_1 = "NO"; - FD1P3AX CmdUFMCS_385 (.D(Din_c_2), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), - .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) - defparam CmdUFMCS_385.GSR = "ENABLED"; - FD1S3AX FS_577__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i13.GSR = "ENABLED"; - ORCALUT4 i1875_2_lut (.A(nCRAS_c), .B(LEDEN), .Z(LED_N_90)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(13[15:34]) - defparam i1875_2_lut.init = 16'hbbbb; - FD1S3AX FS_577__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i12.GSR = "ENABLED"; - PFUMX RCKEEN_I_0_419 (.BLUT(RCKEEN_N_117), .ALUT(RCKEEN_N_126), .C0(nRowColSel_N_35), - .Z(RCKEEN_N_116)); - ORCALUT4 i1856_4_lut (.A(Bank[0]), .B(Bank[5]), .C(MAin_c_2), .D(Bank[6]), - .Z(n2166)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i1856_4_lut.init = 16'h8000; - FD1S3AX FS_577__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i11.GSR = "ENABLED"; - ORCALUT4 i1844_2_lut (.A(Bank[7]), .B(MAin_c_4), .Z(n2154)) /* synthesis lut_function=(A (B)) */ ; - defparam i1844_2_lut.init = 16'h8888; - ORCALUT4 RA11_I_53_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_180)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(99[22:51]) - defparam RA11_I_53_3_lut.init = 16'hc6c6; - ORCALUT4 Ready_bdd_3_lut_1922 (.A(nRCAS_N_161), .B(nRCS_N_135), .C(InitReady), - .Z(n2248)) /* synthesis lut_function=(A+(B+!(C))) */ ; - defparam Ready_bdd_3_lut_1922.init = 16'hefef; - FD1P3IX UFMSDI_390 (.D(UFMSDI_N_219), .SP(RCLK_c_enable_24), .CD(n2291), - .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) - defparam UFMSDI_390.GSR = "ENABLED"; - ORCALUT4 MAin_9__I_0_400_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), - .Z(RA_c_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) - defparam MAin_9__I_0_400_i10_3_lut.init = 16'hcaca; - ORCALUT4 i604_1_lut_rep_30 (.A(Ready), .Z(n2307)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam i604_1_lut_rep_30.init = 16'h5555; - FD1S3AX FS_577__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i10.GSR = "ENABLED"; - FD1S3AX FS_577__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i9.GSR = "ENABLED"; - FD1S3AX FS_577__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i8.GSR = "ENABLED"; - FD1S3AX FS_577__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i7.GSR = "ENABLED"; - FD1S3AX FS_577__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i6.GSR = "ENABLED"; - FD1S3AX FS_577__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i5.GSR = "ENABLED"; - FD1S3AX FS_577__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i4.GSR = "ENABLED"; - FD1S3AX FS_577__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i3.GSR = "ENABLED"; - FD1S3AX FS_577__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i2.GSR = "ENABLED"; - FD1S3AX FS_577__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577__i1.GSR = "ENABLED"; - FD1P3AX IS_FSM__i15 (.D(n699), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(Ready_N_272)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i15.GSR = "ENABLED"; - FD1P3AX IS_FSM__i14 (.D(n700), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n699)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i14.GSR = "ENABLED"; - FD1P3AX IS_FSM__i13 (.D(n701), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n700)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i13.GSR = "ENABLED"; - FD1P3AX IS_FSM__i12 (.D(n702), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n701)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i12.GSR = "ENABLED"; - FD1P3AX IS_FSM__i11 (.D(n703), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n702)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i11.GSR = "ENABLED"; - FD1P3AX IS_FSM__i10 (.D(nRWE_N_173), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n703)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i10.GSR = "ENABLED"; - FD1P3AX IS_FSM__i9 (.D(n705), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(nRWE_N_173)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i9.GSR = "ENABLED"; - FD1P3AX IS_FSM__i8 (.D(n706), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n705)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i8.GSR = "ENABLED"; - FD1P3AX IS_FSM__i7 (.D(n707), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n706)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i7.GSR = "ENABLED"; - FD1P3AX IS_FSM__i6 (.D(n708), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n707)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i6.GSR = "ENABLED"; - FD1P3AX IS_FSM__i5 (.D(n709), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n708)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i5.GSR = "ENABLED"; - FD1P3AX IS_FSM__i4 (.D(n710), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n709)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i4.GSR = "ENABLED"; - FD1P3AX IS_FSM__i3 (.D(n711), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n710)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i3.GSR = "ENABLED"; - FD1P3AX IS_FSM__i2 (.D(nRCAS_N_161), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(n711)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i2.GSR = "ENABLED"; - FD1P3AX IS_FSM__i1 (.D(nRCS_N_135), .SP(RCLK_c_enable_23), .CK(RCLK_c), - .Q(nRCAS_N_161)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15]) - defparam IS_FSM__i1.GSR = "ENABLED"; - FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RBA__i2.GSR = "ENABLED"; - FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) - defparam WRD_i7.GSR = "ENABLED"; - FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) - defparam WRD_i6.GSR = "ENABLED"; - FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) - defparam WRD_i5.GSR = "ENABLED"; - FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) - defparam WRD_i4.GSR = "ENABLED"; - FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) - defparam WRD_i3.GSR = "ENABLED"; - FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) - defparam WRD_i2.GSR = "ENABLED"; - FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5]) - defparam WRD_i1.GSR = "ENABLED"; - FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[9])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RowA_i9.GSR = "ENABLED"; - FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[8])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RowA_i8.GSR = "ENABLED"; - FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RowA_i7.GSR = "ENABLED"; - FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RowA_i6.GSR = "ENABLED"; - FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RowA_i5.GSR = "ENABLED"; - FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RowA_i4.GSR = "ENABLED"; - FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RowA_i3.GSR = "ENABLED"; - FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RowA_i2.GSR = "ENABLED"; - FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5]) - defparam RowA_i1.GSR = "ENABLED"; - FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) - defparam Bank_i7.GSR = "ENABLED"; - ORCALUT4 i1_2_lut_rep_12 (.A(MAin_c_1), .B(n1285), .Z(n2289)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31]) - defparam i1_2_lut_rep_12.init = 16'hdddd; - ORCALUT4 i1_2_lut_rep_15_3_lut_4_lut_4_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), - .C(InitReady), .D(RASr2), .Z(n2292)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i1_2_lut_rep_15_3_lut_4_lut_4_lut.init = 16'hdfff; - ORCALUT4 i1_2_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_35), .C(RASr2), - .D(InitReady), .Z(RCLK_c_enable_23)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam i1_2_lut_4_lut_4_lut.init = 16'h4000; - FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) - defparam Bank_i6.GSR = "ENABLED"; - FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) - defparam Bank_i5.GSR = "ENABLED"; - FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) - defparam Bank_i4.GSR = "ENABLED"; - FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) - defparam Bank_i3.GSR = "ENABLED"; - FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) - defparam Bank_i2.GSR = "ENABLED"; - FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5]) - defparam Bank_i1.GSR = "ENABLED"; - BB Dout_pad_6__689 (.I(WRD[6]), .T(n962), .B(RD[6]), .O(n974)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) - BB Dout_pad_5__690 (.I(WRD[5]), .T(n962), .B(RD[5]), .O(n975)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) - BB Dout_pad_4__691 (.I(WRD[4]), .T(n962), .B(RD[4]), .O(n976)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) - BB Dout_pad_3__692 (.I(WRD[3]), .T(n962), .B(RD[3]), .O(n977)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) - BB Dout_pad_2__693 (.I(WRD[2]), .T(n962), .B(RD[2]), .O(n978)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) - BB Dout_pad_1__694 (.I(WRD[1]), .T(n962), .B(RD[1]), .O(n979)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) - ORCALUT4 nRWE_I_49_1_lut (.A(nRWE_N_173), .Z(nRWE_N_172)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(255[14] 262[8]) - defparam nRWE_I_49_1_lut.init = 16'h5555; - BB Dout_pad_0__695 (.I(WRD[0]), .T(n962), .B(RD[0]), .O(Dout_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16]) - OB Dout_pad_7 (.I(n973), .O(Dout[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) - OB Dout_pad_6 (.I(n974), .O(Dout[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) - OB Dout_pad_5 (.I(n975), .O(Dout[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) - OB Dout_pad_4 (.I(n976), .O(Dout[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) - OB Dout_pad_3 (.I(n977), .O(Dout[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) - OB Dout_pad_2 (.I(n978), .O(Dout[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) - OB Dout_pad_1 (.I(n979), .O(Dout[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) - OB Dout_pad_0 (.I(Dout_c), .O(Dout[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19]) - OB LED_pad (.I(LED_N_90), .O(LED)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12]) - OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) - OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22]) - OB RA_pad_11 (.I(RA_c), .O(RA[11])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB RA_pad_10 (.I(n980), .O(RA[10])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB RA_pad_9 (.I(RA_c_9), .O(RA[9])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB RA_pad_8 (.I(RA_c_8), .O(RA[8])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB RA_pad_7 (.I(RA_c_7), .O(RA[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB RA_pad_6 (.I(RA_c_6), .O(RA[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB RA_pad_5 (.I(RA_c_5), .O(RA[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB RA_pad_4 (.I(RA_c_4), .O(RA[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB RA_pad_3 (.I(RA_c_3), .O(RA[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB RA_pad_2 (.I(RA_c_2), .O(RA[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB RA_pad_1 (.I(RA_c_1), .O(RA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB RA_pad_0 (.I(RA_c_0), .O(RA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18]) - OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17]) - OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17]) - OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49]) - OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28]) - OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39]) - OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21]) - OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14]) - OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19]) - OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19]) - OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19]) - IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) - IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) - IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) - IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) - IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) - IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) - IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) - IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) - IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) - IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) - IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18]) - IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18]) - IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18]) - IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) - IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) - IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) - IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) - IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) - IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) - IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) - IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17]) - IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13]) - IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) - IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12]) - IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12]) - IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14]) - ORCALUT4 MAin_9__I_0_400_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), - .Z(RA_c_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) - defparam MAin_9__I_0_400_i9_3_lut.init = 16'hcaca; - CCU2 FS_577_add_4_4 (.A0(FS[2]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[3]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1874), - .COUT1(n1875), .S0(n93), .S1(n92)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577_add_4_4.INIT0 = 16'hfaaa; - defparam FS_577_add_4_4.INIT1 = 16'hfaaa; - defparam FS_577_add_4_4.INJECT1_0 = "NO"; - defparam FS_577_add_4_4.INJECT1_1 = "NO"; - ORCALUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_32), - .C(n1627), .D(nRowColSel_N_35), .Z(RCLK_c_enable_3)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'hfffd; - FD1P3IX UFMCLK_389 (.D(UFMCLK_N_212), .SP(RCLK_c_enable_24), .CD(n2291), - .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) - defparam UFMCLK_389.GSR = "ENABLED"; - ORCALUT4 i2_2_lut_rep_22_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2299)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5]) - defparam i2_2_lut_rep_22_2_lut.init = 16'hdddd; - ORCALUT4 i2_3_lut_4_lut_adj_20 (.A(n2297), .B(n2301), .C(nRCAS_N_161), - .D(Ready), .Z(n2128)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i2_3_lut_4_lut_adj_20.init = 16'hfffe; - ORCALUT4 i2_3_lut_adj_21 (.A(nRowColSel_N_33), .B(nRRAS_c), .C(nRowColSel_N_32), - .Z(n50)) /* synthesis lut_function=(A+(B+(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i2_3_lut_adj_21.init = 16'hfefe; - ORCALUT4 MAin_9__I_0_400_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), - .Z(RA_c_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) - defparam MAin_9__I_0_400_i8_3_lut.init = 16'hcaca; - ORCALUT4 Ready_bdd_4_lut (.A(Ready), .B(n2117), .C(n2287), .D(nRowColSel_N_35), - .Z(nRCAS_N_157)) /* synthesis lut_function=(A (B (C (D))+!B (C+!(D)))+!A (C+!(D))) */ ; - defparam Ready_bdd_4_lut.init = 16'hf077; - ORCALUT4 i1366_3_lut (.A(InitReady), .B(RCKEEN_N_116), .C(Ready), - .Z(RCKEEN_N_115)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11]) - defparam i1366_3_lut.init = 16'hcaca; - ORCALUT4 i6_4_lut (.A(FS[15]), .B(n12_adj_2), .C(FS[11]), .D(FS[17]), - .Z(n2076)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i6_4_lut.init = 16'h8000; - ORCALUT4 i1_4_lut_4_lut (.A(CBR), .B(n11_adj_3), .C(FWEr), .D(nRowColSel_N_34), - .Z(RCKEEN_N_117)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(214[26:30]) - defparam i1_4_lut_4_lut.init = 16'h5540; - ORCALUT4 i1_2_lut_rep_11_3_lut (.A(nFWE_c), .B(n1285), .C(MAin_c_1), - .Z(PHI2_N_114_enable_1)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; - defparam i1_2_lut_rep_11_3_lut.init = 16'h1010; - CCU2 FS_577_add_4_2 (.A0(FS[0]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[1]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(GND_net), - .COUT1(n1874), .S0(n95), .S1(n94)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577_add_4_2.INIT0 = 16'h0555; - defparam FS_577_add_4_2.INIT1 = 16'hfaaa; - defparam FS_577_add_4_2.INJECT1_0 = "NO"; - defparam FS_577_add_4_2.INJECT1_1 = "NO"; - ORCALUT4 i3_4_lut_adj_22 (.A(Din_c_0), .B(Din_c_1), .C(Din_c_4), .D(Din_c_7), - .Z(n2114)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; - defparam i3_4_lut_adj_22.init = 16'h0200; - ORCALUT4 Ready_bdd_4_lut_1960 (.A(nRowColSel_N_32), .B(RASr2), .C(Ready_N_272), - .D(InitReady), .Z(n2245)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; - defparam Ready_bdd_4_lut_1960.init = 16'h2000; - ORCALUT4 n2245_bdd_2_lut (.A(n2245), .B(Ready), .Z(Ready_N_268)) /* synthesis lut_function=(A+(B)) */ ; - defparam n2245_bdd_2_lut.init = 16'heeee; - ORCALUT4 n2248_bdd_4_lut_4_lut (.A(CBR), .B(RASr2), .C(Ready), .D(n2248), - .Z(n2287)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A !((C+(D))+!B))) */ ; - defparam n2248_bdd_4_lut_4_lut.init = 16'h7f73; - FD1P3AX LEDEN_392 (.D(UFMSDO_N_74), .SP(RCLK_c_enable_25), .CK(RCLK_c), - .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) - defparam LEDEN_392.GSR = "ENABLED"; - ORCALUT4 MAin_9__I_0_400_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), - .Z(RA_c_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) - defparam MAin_9__I_0_400_i7_3_lut.init = 16'hcaca; - ORCALUT4 MAin_9__I_0_400_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), - .Z(RA_c_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) - defparam MAin_9__I_0_400_i6_3_lut.init = 16'hcaca; - CCU2 FS_577_add_4_12 (.A0(FS[10]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[11]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1878), - .COUT1(n1879), .S0(n85), .S1(n84)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577_add_4_12.INIT0 = 16'hfaaa; - defparam FS_577_add_4_12.INIT1 = 16'hfaaa; - defparam FS_577_add_4_12.INJECT1_0 = "NO"; - defparam FS_577_add_4_12.INJECT1_1 = "NO"; - FD1P3AX CmdEnable_378 (.D(CmdEnable_N_236), .SP(PHI2_N_114_enable_8), - .CK(PHI2_N_114), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5]) - defparam CmdEnable_378.GSR = "ENABLED"; - CCU2 FS_577_add_4_16 (.A0(FS[14]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[15]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1880), - .COUT1(n1881), .S0(n81), .S1(n80)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577_add_4_16.INIT0 = 16'hfaaa; - defparam FS_577_add_4_16.INIT1 = 16'hfaaa; - defparam FS_577_add_4_16.INJECT1_0 = "NO"; - defparam FS_577_add_4_16.INJECT1_1 = "NO"; - CCU2 FS_577_add_4_14 (.A0(FS[12]), .B0(GND_net), .C0(GND_net), .D0(GND_net), - .A1(FS[13]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1879), - .COUT1(n1880), .S0(n83), .S1(n82)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13]) - defparam FS_577_add_4_14.INIT0 = 16'hfaaa; - defparam FS_577_add_4_14.INIT1 = 16'hfaaa; - defparam FS_577_add_4_14.INJECT1_0 = "NO"; - defparam FS_577_add_4_14.INJECT1_1 = "NO"; - ORCALUT4 MAin_9__I_0_400_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), - .Z(RA_c_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) - defparam MAin_9__I_0_400_i3_3_lut.init = 16'hcaca; - ORCALUT4 i1485_3_lut (.A(n2076), .B(n1369), .C(InitReady), .Z(n1348)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15]) - defparam i1485_3_lut.init = 16'hcaca; - ORCALUT4 i1_2_lut_2_lut (.A(nRowColSel_N_35), .B(nRowColSel_N_34), .Z(n18)) /* synthesis lut_function=(!(A+!(B))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i1_2_lut_2_lut.init = 16'h4444; - ORCALUT4 i1_2_lut_rep_20_2_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), - .Z(n2297)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i1_2_lut_rep_20_2_lut.init = 16'hdddd; - ORCALUT4 i1062_3_lut (.A(nUFMCS_c), .B(CmdUFMCS), .C(n2308), .Z(n1369)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5]) - defparam i1062_3_lut.init = 16'h3a3a; - ORCALUT4 MAin_9__I_0_400_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), - .Z(RA_c_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) - defparam MAin_9__I_0_400_i4_3_lut.init = 16'hcaca; - ORCALUT4 MAin_9__I_0_400_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), - .Z(RA_c_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54]) - defparam MAin_9__I_0_400_i1_3_lut.init = 16'hcaca; - INV i1961 (.A(nCRAS_c), .Z(nCRAS_N_9)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20]) - INV i1962 (.A(PHI2_c), .Z(PHI2_N_114)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12]) - VLO i1 (.Z(GND_net)); - TSALL TSALL_INST (.TSALL(GND_net)); - ORCALUT4 i1070_1_lut_rep_25 (.A(nRowColSel_N_35), .Z(n2302)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16]) - defparam i1070_1_lut_rep_25.init = 16'h5555; - PUR PUR_INST (.PUR(VCC_net)); - defparam PUR_INST.RST_PULSE = 1; - ORCALUT4 i13_4_lut (.A(Bank[3]), .B(n26), .C(n2170), .D(MAin_c_5), - .Z(n1285)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; - defparam i13_4_lut.init = 16'hdfff; - ORCALUT4 i12_4_lut (.A(Bank[2]), .B(n2166), .C(n2154), .D(MAin_c_6), - .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; - defparam i12_4_lut.init = 16'hbfff; - ORCALUT4 i1860_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), - .Z(n2170)) /* synthesis lut_function=(A (B (C (D)))) */ ; - defparam i1860_4_lut.init = 16'h8000; - ORCALUT4 m0_lut (.Z(n2386)) /* synthesis lut_function=0, syn_instantiated=1 */ ; - defparam m0_lut.init = 16'h0000; - PFUMX i1934 (.BLUT(n2309), .ALUT(n2310), .C0(Ready), .Z(nRCS_N_132)); - -endmodule -// -// Verilog Description of module TSALL -// module not written out since it is a black-box. -// - -// -// Verilog Description of module PUR -// module not written out since it is a black-box. -// - diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf b/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf deleted file mode 100644 index 420deec..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf +++ /dev/null @@ -1,89 +0,0 @@ -PERIOD NET "PHI2_c" 350.000000 ns ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -PERIOD NET "RCLK_c" 15.000000 ns ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; -OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; -OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; -OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; -OUTPUT PORT "nRWE" LOAD 10.000000 pF ; -OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; -OUTPUT PORT "nRCS" LOAD 10.000000 pF ; -OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; -OUTPUT PORT "RDQML" LOAD 10.000000 pF ; -OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; -OUTPUT PORT "RCKE" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "LED" LOAD 25.000000 pF ; -OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; -VOLTAGE 3.300 V; -VCCIO_DERATE BANK 0 PERCENT -5; -VCCIO_DERATE PERCENT -5; -VCCIO_DERATE BANK 1 PERCENT -5; -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; -COMMERCIAL ; \ No newline at end of file diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp b/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp deleted file mode 100644 index fc768e6..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp +++ /dev/null @@ -1,155 +0,0 @@ -VOLTAGE 3.300 V; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "LED" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ; -IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ; -IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ; -IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ; -PERIOD NET "PHI2_c" 350.000000 ns ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -PERIOD NET "RCLK_c" 15.000000 ns ; -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; -OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; -OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; -OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; -OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; -OUTPUT PORT "nRWE" LOAD 10.000000 pF ; -OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; -OUTPUT PORT "nRCS" LOAD 10.000000 pF ; -OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; -OUTPUT PORT "RDQML" LOAD 10.000000 pF ; -OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; -OUTPUT PORT "RCKE" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "LED" LOAD 25.000000 pF ; -OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; -VCCIO_DERATE BANK 0 PERCENT -5; -VCCIO_DERATE PERCENT -5; -VCCIO_DERATE BANK 1 PERCENT -5; diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp0 b/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp0 deleted file mode 100644 index f59c75e..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp0 +++ /dev/null @@ -1,88 +0,0 @@ -PERIOD NET "PHI2_c" 350.000000 ns ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -PERIOD NET "RCLK_c" 15.000000 ns ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; -OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; -OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; -OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; -OUTPUT PORT "nRWE" LOAD 10.000000 pF ; -OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; -OUTPUT PORT "nRCS" LOAD 10.000000 pF ; -OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; -OUTPUT PORT "RDQML" LOAD 10.000000 pF ; -OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; -OUTPUT PORT "RCKE" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "LED" LOAD 25.000000 pF ; -OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; -VOLTAGE 3.300 V; -VCCIO_DERATE BANK 0 PERCENT -5; -VCCIO_DERATE PERCENT -5; -VCCIO_DERATE BANK 1 PERCENT -5; -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp2 b/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp2 deleted file mode 100644 index fc768e6..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf.prf_cdmp2 +++ /dev/null @@ -1,155 +0,0 @@ -VOLTAGE 3.300 V; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "LED" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ; -IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ; -IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ; -IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ; -IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ; -PERIOD NET "PHI2_c" 350.000000 ns ; -PERIOD NET "nCCAS_c" 350.000000 ns ; -PERIOD NET "nCRAS_c" 350.000000 ns ; -PERIOD NET "RCLK_c" 15.000000 ns ; -CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; -CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; -OUTPUT PORT "RD[7]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[0]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[1]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[2]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[3]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[4]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[5]" LOAD 20.000000 pF ; -OUTPUT PORT "RD[6]" LOAD 20.000000 pF ; -OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ; -OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ; -OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ; -OUTPUT PORT "nRWE" LOAD 10.000000 pF ; -OUTPUT PORT "nRCAS" LOAD 10.000000 pF ; -OUTPUT PORT "nRCS" LOAD 10.000000 pF ; -OUTPUT PORT "nRRAS" LOAD 10.000000 pF ; -OUTPUT PORT "RDQML" LOAD 10.000000 pF ; -OUTPUT PORT "RDQMH" LOAD 10.000000 pF ; -OUTPUT PORT "RCKE" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[11]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[10]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[9]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[8]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[7]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[6]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[5]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[4]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[3]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[2]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[1]" LOAD 10.000000 pF ; -OUTPUT PORT "RA[0]" LOAD 10.000000 pF ; -OUTPUT PORT "LED" LOAD 25.000000 pF ; -OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ; -OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ; -VCCIO_DERATE BANK 0 PERCENT -5; -VCCIO_DERATE PERCENT -5; -VCCIO_DERATE BANK 1 PERCENT -5; diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf_hold.html b/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf_hold.html deleted file mode 100644 index 14546c8..0000000 --- a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf_hold.html +++ /dev/null @@ -1,2080 +0,0 @@ - - - - - - - -
    
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 20:23:38 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Design file:     RAM2GS
-Device,speed:    LCMXO256C,M
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            10 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
- 
-
-Passed: The following path meets requirements by 0.540ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted_375  (to PHI2_c -)
-
-   Delay:               0.517ns  (50.7% logic, 49.3% route), 2 logic levels.
-
- Constraint Details:
-
-      0.517ns physical path delay SLICE_9 to SLICE_9 meets
-     -0.023ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.023ns) by 0.540ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R6C3C.CLK to       R6C3C.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.255       R6C3C.Q0 to R6C3C.B0       ADSubmitted
-CTOF_DEL    ---     0.092       R6C3C.B0 to       R6C3C.F0 SLICE_9
-ROUTE         1     0.000       R6C3C.F0 to R6C3C.DI0      n1355 (to PHI2_c)
-                  --------
-                    0.517   (50.7% logic, 49.3% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C3C.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C3C.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.089ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
-                   FF                        CmdUFMCLK_380
-
-   Delay:               1.060ns  (33.4% logic, 66.6% route), 3 logic levels.
-
- Constraint Details:
-
-      1.060ns physical path delay SLICE_18 to SLICE_83 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.089ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
-CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
-ROUTE         3     0.354       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R4C5A.C1 to       R4C5A.F1 SLICE_73
-ROUTE         2     0.178       R4C5A.F1 to R5C5D.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                    1.060   (33.4% logic, 66.6% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R5C5D.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.165ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
-   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
-
-   Delay:               1.136ns  (31.2% logic, 68.8% route), 3 logic levels.
-
- Constraint Details:
-
-      1.136ns physical path delay SLICE_18 to SLICE_19 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.165ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
-CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
-ROUTE         3     0.181       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R6C3A.B0 to       R6C3A.F0 SLICE_76
-ROUTE         2     0.427       R6C3A.F0 to R7C4D.CE       PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                    1.136   (31.2% logic, 68.8% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R7C4D.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.212ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
-
-   Delay:               1.183ns  (29.9% logic, 70.1% route), 3 logic levels.
-
- Constraint Details:
-
-      1.183ns physical path delay SLICE_18 to SLICE_77 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.212ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
-CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
-ROUTE         3     0.354       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R4C5A.C1 to       R4C5A.F1 SLICE_73
-ROUTE         2     0.301       R4C5A.F1 to R7C5C.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                    1.183   (29.9% logic, 70.1% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R7C5C.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.247ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
-   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
-
-   Delay:               1.218ns  (29.1% logic, 70.9% route), 3 logic levels.
-
- Constraint Details:
-
-      1.218ns physical path delay SLICE_18 to SLICE_94 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.247ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
-CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
-ROUTE         3     0.266       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R7C3C.A0 to       R7C3C.F0 SLICE_97
-ROUTE         1     0.424       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
-                  --------
-                    1.218   (29.1% logic, 70.9% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R8C5C.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.288ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
-   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
-
-   Delay:               1.259ns  (28.1% logic, 71.9% route), 3 logic levels.
-
- Constraint Details:
-
-      1.259ns physical path delay SLICE_18 to SLICE_23 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.288ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R6C4D.CLK to       R6C4D.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.174       R6C4D.Q0 to R6C3A.D1       CmdEnable
-CTOF_DEL    ---     0.092       R6C3A.D1 to       R6C3A.F1 SLICE_76
-ROUTE         3     0.181       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R6C3A.B0 to       R6C3A.F0 SLICE_76
-ROUTE         2     0.550       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                    1.259   (28.1% logic, 71.9% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R7C3A.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.392ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted_374  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
-
-   Delay:               1.363ns  (37.1% logic, 62.9% route), 4 logic levels.
-
- Constraint Details:
-
-      1.363ns physical path delay SLICE_14 to SLICE_18 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.392ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R6C4C.CLK to       R6C4C.Q0 SLICE_14 (from PHI2_c)
-ROUTE         1     0.256       R6C4C.Q0 to R6C3D.A1       C1Submitted
-CTOOFX_DEL  ---     0.151       R6C3D.A1 to     R6C3D.OFX0 i26/SLICE_70
-ROUTE         1     0.269     R6C3D.OFX0 to R6C4A.B1       n13
-CTOF_DEL    ---     0.092       R6C4A.B1 to       R6C4A.F1 SLICE_80
-ROUTE         1     0.172       R6C4A.F1 to R6C4A.B0       n6
-CTOF_DEL    ---     0.092       R6C4A.B0 to       R6C4A.F0 SLICE_80
-ROUTE         1     0.161       R6C4A.F0 to R6C4D.CE       PHI2_N_114_enable_8 (to PHI2_c)
-                  --------
-                    1.363   (37.1% logic, 62.9% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C4C.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.395ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
-
-   Delay:               1.366ns  (37.3% logic, 62.7% route), 4 logic levels.
-
- Constraint Details:
-
-      1.366ns physical path delay SLICE_9 to SLICE_18 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.395ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R6C3C.CLK to       R6C3C.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.255       R6C3C.Q0 to R6C3D.B0       ADSubmitted
-CTOOFX_DEL  ---     0.155       R6C3D.B0 to     R6C3D.OFX0 i26/SLICE_70
-ROUTE         1     0.269     R6C3D.OFX0 to R6C4A.B1       n13
-CTOF_DEL    ---     0.092       R6C4A.B1 to       R6C4A.F1 SLICE_80
-ROUTE         1     0.172       R6C4A.F1 to R6C4A.B0       n6
-CTOF_DEL    ---     0.092       R6C4A.B0 to       R6C4A.F0 SLICE_80
-ROUTE         1     0.161       R6C4A.F0 to R6C4D.CE       PHI2_N_114_enable_8 (to PHI2_c)
-                  --------
-                    1.366   (37.3% logic, 62.7% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C3C.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C4D.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 175.744ns (weighted slack = 351.488ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              XOR8MEG_376  (from PHI2_c -)
-   Destination:    FF         Data in        RA11_353  (to PHI2_c +)
-
-   Delay:               0.733ns  (35.7% logic, 64.3% route), 2 logic levels.
-
- Constraint Details:
-
-      0.733ns physical path delay SLICE_94 to SLICE_31 meets
-     -0.011ns DIN_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.011ns) by 175.744ns
-
- Physical Path Details:
-
-      Data path SLICE_94 to SLICE_31:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R8C5C.CLK to       R8C5C.Q0 SLICE_94 (from PHI2_c)
-ROUTE         1     0.471       R8C5C.Q0 to R2C5A.C0       XOR8MEG
-CTOF_DEL    ---     0.092       R2C5A.C0 to       R2C5A.F0 SLICE_31
-ROUTE         1     0.000       R2C5A.F0 to R2C5A.DI0      RA11_N_180 (to PHI2_c)
-                  --------
-                    0.733   (35.7% logic, 64.3% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R8C5C.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_31:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R2C5A.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 176.433ns (weighted slack = 352.866ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i3  (from PHI2_c +)
-   Destination:    FF         Data in        C1Submitted_374  (to PHI2_c -)
-
-   Delay:               1.404ns  (24.3% logic, 75.7% route), 3 logic levels.
-
- Constraint Details:
-
-      1.404ns physical path delay SLICE_92 to SLICE_14 meets
-     -0.029ns CE_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.029ns) by 176.433ns
-
- Physical Path Details:
-
-      Data path SLICE_92 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C3B.CLK to       R2C3B.Q1 SLICE_92 (from PHI2_c)
-ROUTE         1     0.502       R2C3B.Q1 to R5C4B.A1       Bank_3
-CTOF_DEL    ---     0.092       R5C4B.A1 to       R5C4B.F1 SLICE_74
-ROUTE         5     0.137       R5C4B.F1 to R5C4B.C0       n1279
-CTOF_DEL    ---     0.092       R5C4B.C0 to       R5C4B.F0 SLICE_74
-ROUTE         1     0.424       R5C4B.F0 to R6C4C.CE       PHI2_N_114_enable_1 (to PHI2_c)
-                  --------
-                    1.404   (24.3% logic, 75.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_92:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R2C3B.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.200       39.PADDI to R6C4C.CLK      PHI2_c
-                  --------
-                    1.200   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 15.000000 ns  ;
-            10 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_101 to SLICE_101 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_101 to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C4C.CLK to       R5C4C.Q0 SLICE_101 (from RCLK_c)
-ROUTE         1     0.161       R5C4C.Q0 to R5C4C.M1       n705 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R5C4C.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R5C4C.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_81 to SLICE_81 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_81 to SLICE_81:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R4C4C.CLK to       R4C4C.Q0 SLICE_81 (from RCLK_c)
-ROUTE         1     0.161       R4C4C.Q0 to R4C4C.M1       n703 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_81:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R4C4C.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_81:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R4C4C.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_84 to SLICE_84 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_84 to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C4D.CLK to       R5C4D.Q0 SLICE_84 (from RCLK_c)
-ROUTE         1     0.161       R5C4D.Q0 to R5C4D.M1       n695 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R5C4D.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R5C4D.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_95 to SLICE_95 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R6C2A.CLK to       R6C2A.Q0 SLICE_95 (from RCLK_c)
-ROUTE         1     0.161       R6C2A.Q0 to R6C2A.M1       n699 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R6C2A.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R6C2A.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_96 to SLICE_84 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_96 to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C4A.CLK to       R5C4A.Q1 SLICE_96 (from RCLK_c)
-ROUTE         1     0.161       R5C4A.Q1 to R5C4D.M0       n696 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R5C4A.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R5C4D.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_96 to SLICE_96 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_96 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C4A.CLK to       R5C4A.Q0 SLICE_96 (from RCLK_c)
-ROUTE         1     0.161       R5C4A.Q0 to R5C4A.M1       n697 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R5C4A.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R5C4A.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              PHI2r_344  (from RCLK_c +)
-   Destination:    FF         Data in        PHI2r2_345  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_97 to SLICE_88 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_97 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C3C.CLK to       R7C3C.Q1 SLICE_97 (from RCLK_c)
-ROUTE         1     0.161       R7C3C.Q1 to R7C3B.M1       PHI2r (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R7C3C.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R7C3B.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_99 to SLICE_99 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_99 to SLICE_99:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R3C5C.CLK to       R3C5C.Q0 SLICE_99 (from RCLK_c)
-ROUTE         1     0.161       R3C5C.Q0 to R3C5C.M1       n693 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_99:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R3C5C.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_99:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R3C5C.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.345ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              PHI2r2_345  (from RCLK_c +)
-   Destination:    FF         Data in        PHI2r3_346  (to RCLK_c +)
-
-   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.324ns physical path delay SLICE_88 to SLICE_97 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
-
- Physical Path Details:
-
-      Data path SLICE_88 to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C3B.CLK to       R7C3B.Q1 SLICE_88 (from RCLK_c)
-ROUTE         3     0.167       R7C3B.Q1 to R7C3C.M0       PHI2r2 (to RCLK_c)
-                  --------
-                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R7C3B.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R7C3C.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.345ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i15  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i0  (to RCLK_c +)
-
-   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.324ns physical path delay SLICE_99 to SLICE_87 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
-
- Physical Path Details:
-
-      Data path SLICE_99 to SLICE_87:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R3C5C.CLK to       R3C5C.Q1 SLICE_99 (from RCLK_c)
-ROUTE         2     0.167       R3C5C.Q1 to R3C5A.M0       Ready_N_272 (to RCLK_c)
-                  --------
-                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_99:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R3C5C.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_87:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.413       86.PADDI to R3C5A.CLK      RCLK_c
-                  --------
-                    0.413   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.220ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_368  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     1.733ns  (73.0% logic, 27.0% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_55 and
-      1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets
-      0.000ns hold offset RCLK to RA[10] by 2.220ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C4B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     0.468       R2C4B.Q0 to 87.PADDO       n974
-DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
-                  --------
-                    1.733   (73.0% logic, 27.0% route), 2 logic levels.
-
-Report:    2.220ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.805ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     2.318ns  (58.5% logic, 41.5% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.318ns delay SLICE_64 to RA[9] (totaling 2.805ns) meets
-      0.000ns hold offset RCLK to RA[9] by 2.805ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.469       R7C2B.Q0 to R3C5A.D1       nRowColSel
-CTOF_DEL    ---     0.092       R3C5A.D1 to       R3C5A.F1 SLICE_87
-ROUTE         1     0.492       R3C5A.F1 to 85.PADDO       RA_c_9
-DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
-                  --------
-                    2.318   (58.5% logic, 41.5% route), 3 logic levels.
-
-Report:    2.805ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.476ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     1.989ns  (68.2% logic, 31.8% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      1.989ns delay SLICE_64 to RA[8] (totaling 2.476ns) meets
-      0.000ns hold offset RCLK to RA[8] by 2.476ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.435       R7C2B.Q0 to R2C2C.D0       nRowColSel
-CTOF_DEL    ---     0.092       R2C2C.D0 to       R2C2C.F0 SLICE_98
-ROUTE         1     0.197       R2C2C.F0 to 96.PADDO       RA_c_8
-DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
-                  --------
-                    1.989   (68.2% logic, 31.8% route), 3 logic levels.
-
-Report:    2.476ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.460ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     1.973ns  (68.8% logic, 31.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      1.973ns delay SLICE_64 to RA[7] (totaling 2.460ns) meets
-      0.000ns hold offset RCLK to RA[7] by 2.460ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.222       R7C2B.Q0 to R7C2B.C1       nRowColSel
-CTOF_DEL    ---     0.092       R7C2B.C1 to       R7C2B.F1 SLICE_64
-ROUTE         1     0.394       R7C2B.F1 to 100.PADDO      RA_c_7
-DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
-                  --------
-                    1.973   (68.8% logic, 31.2% route), 3 logic levels.
-
-Report:    2.460ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.759ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     2.272ns  (59.7% logic, 40.3% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.272ns delay SLICE_64 to RA[6] (totaling 2.759ns) meets
-      0.000ns hold offset RCLK to RA[6] by 2.759ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.435       R7C2B.Q0 to R2C2C.D1       nRowColSel
-CTOF_DEL    ---     0.092       R2C2C.D1 to       R2C2C.F1 SLICE_98
-ROUTE         1     0.480       R2C2C.F1 to 91.PADDO       RA_c_6
-DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
-                  --------
-                    2.272   (59.7% logic, 40.3% route), 3 logic levels.
-
-Report:    2.759ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.516ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     2.029ns  (66.9% logic, 33.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.029ns delay SLICE_64 to RA[5] (totaling 2.516ns) meets
-      0.000ns hold offset RCLK to RA[5] by 2.516ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.278       R7C2B.Q0 to R6C2A.A1       nRowColSel
-CTOF_DEL    ---     0.092       R6C2A.A1 to       R6C2A.F1 SLICE_95
-ROUTE         1     0.394       R6C2A.F1 to 95.PADDO       RA_c_5
-DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
-                  --------
-                    2.029   (66.9% logic, 33.1% route), 3 logic levels.
-
-Report:    2.516ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.635ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     2.148ns  (63.2% logic, 36.8% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.148ns delay SLICE_64 to RA[4] (totaling 2.635ns) meets
-      0.000ns hold offset RCLK to RA[4] by 2.635ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.435       R7C2B.Q0 to R2C2B.D1       nRowColSel
-CTOF_DEL    ---     0.092       R2C2B.D1 to       R2C2B.F1 SLICE_93
-ROUTE         1     0.356       R2C2B.F1 to 99.PADDO       RA_c_4
-DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
-                  --------
-                    2.148   (63.2% logic, 36.8% route), 3 logic levels.
-
-Report:    2.635ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.758ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     2.271ns  (59.8% logic, 40.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.271ns delay SLICE_64 to RA[3] (totaling 2.758ns) meets
-      0.000ns hold offset RCLK to RA[3] by 2.758ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.446       R7C2B.Q0 to R2C3B.D1       nRowColSel
-CTOF_DEL    ---     0.092       R2C3B.D1 to       R2C3B.F1 SLICE_92
-ROUTE         1     0.468       R2C3B.F1 to 97.PADDO       RA_c_3
-DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
-                  --------
-                    2.271   (59.8% logic, 40.2% route), 3 logic levels.
-
-Report:    2.758ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.487ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     2.000ns  (67.8% logic, 32.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.000ns delay SLICE_64 to RA[2] (totaling 2.487ns) meets
-      0.000ns hold offset RCLK to RA[2] by 2.487ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.446       R7C2B.Q0 to R2C3A.D0       nRowColSel
-CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_90
-ROUTE         1     0.197       R2C3A.F0 to 94.PADDO       RA_c_2
-DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
-                  --------
-                    2.000   (67.8% logic, 32.1% route), 3 logic levels.
-
-Report:    2.487ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.487ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     2.000ns  (67.8% logic, 32.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.000ns delay SLICE_64 to RA[1] (totaling 2.487ns) meets
-      0.000ns hold offset RCLK to RA[1] by 2.487ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.446       R7C2B.Q0 to R2C3B.D0       nRowColSel
-CTOF_DEL    ---     0.092       R2C3B.D0 to       R2C3B.F0 SLICE_92
-ROUTE         1     0.197       R2C3B.F0 to 89.PADDO       RA_c_1
-DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
-                  --------
-                    2.000   (67.8% logic, 32.1% route), 3 logic levels.
-
-Report:    2.487ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.476ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     1.989ns  (68.2% logic, 31.8% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      1.989ns delay SLICE_64 to RA[0] (totaling 2.476ns) meets
-      0.000ns hold offset RCLK to RA[0] by 2.476ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.435       R7C2B.Q0 to R2C2B.D0       nRowColSel
-CTOF_DEL    ---     0.092       R2C2B.D0 to       R2C2B.F0 SLICE_93
-ROUTE         1     0.197       R2C2B.F0 to 98.PADDO       RA_c_0
-DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
-                  --------
-                    1.989   (68.2% logic, 31.8% route), 3 logic levels.
-
-Report:    2.476ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_364  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_60 and
-      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to nRCS by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C5B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.197       R2C5B.Q0 to 77.PADDO       nRCS_c
-DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.252ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_363  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     1.765ns  (71.7% logic, 28.3% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_34 and
-      1.765ns delay SLICE_34 to RCKE (totaling 2.252ns) meets
-      0.000ns hold offset RCLK to RCKE by 2.252ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R6C5B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R6C5B.CLK to       R6C5B.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     0.500       R6C5B.Q0 to 82.PADDO       RCKE_c
-DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
-                  --------
-                    1.765   (71.7% logic, 28.3% route), 2 logic levels.
-
-Report:    2.252ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_367  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_63 and
-      1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to nRWE by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R3C5B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     0.197       R3C5B.Q0 to 72.PADDO       nRWE_c
-DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.111ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     1.624ns  (77.9% logic, 22.1% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_61 and
-      1.624ns delay SLICE_61 to nRRAS (totaling 2.111ns) meets
-      0.000ns hold offset RCLK to nRRAS by 2.111ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C4C.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C4C.CLK to       R2C4C.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     0.359       R2C4C.Q0 to 73.PADDO       nRRAS_c
-DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
-                  --------
-                    1.624   (77.9% logic, 22.1% route), 2 logic levels.
-
-Report:    2.111ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.220ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     1.733ns  (73.0% logic, 27.0% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_58 and
-      1.733ns delay SLICE_58 to nRCAS (totaling 2.220ns) meets
-      0.000ns hold offset RCLK to nRCAS by 2.220ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C4A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C4A.CLK to       R2C4A.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     0.468       R2C4A.Q0 to 78.PADDO       nRCAS_c
-DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
-                  --------
-                    1.733   (73.0% logic, 27.0% route), 2 logic levels.
-
-Report:    2.220ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.510ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     2.023ns  (67.1% logic, 32.9% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.023ns delay SLICE_64 to RDQMH (totaling 2.510ns) meets
-      0.000ns hold offset RCLK to RDQMH by 2.510ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.469       R7C2B.Q0 to R3C5A.D0       nRowColSel
-CTOF_DEL    ---     0.092       R3C5A.D0 to       R3C5A.F0 SLICE_87
-ROUTE         1     0.197       R3C5A.F0 to 76.PADDO       RDQMH_c
-DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
-                  --------
-                    2.023   (67.1% logic, 32.9% route), 3 logic levels.
-
-Report:    2.510ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.602ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     2.115ns  (64.2% logic, 35.8% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.115ns delay SLICE_64 to RDQML (totaling 2.602ns) meets
-      0.000ns hold offset RCLK to RDQML by 2.602ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.278       R7C2B.Q0 to R6C2A.A0       nRowColSel
-CTOF_DEL    ---     0.092       R6C2A.A0 to       R6C2A.F0 SLICE_95
-ROUTE         1     0.480       R6C2A.F0 to 61.PADDO       RDQML_c
-DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
-                  --------
-                    2.115   (64.2% logic, 35.8% route), 3 logic levels.
-
-Report:    2.602ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 15.000000 ns  ;     |            -|            -|   1  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.220 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.805 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.476 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.460 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.759 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.516 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.635 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.758 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.487 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.487 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.476 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.252 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.111 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.220 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.510 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.602 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 15.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 520 paths, 6 nets, and 436 connections (70.89% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf_setup.html b/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf_setup.html
deleted file mode 100644
index 267300a..0000000
--- a/CPLD-old/LCMXO/LCMXO256C/impl1/Untitled.tpf_setup.html
+++ /dev/null
@@ -1,3314 +0,0 @@
-
-
-
-
-
-
-
-
    
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 20:23:38 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Design file:     RAM2GS
-Device,speed:    LCMXO256C,3
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            10 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
- 
-
-Passed: The following path meets requirements by 162.969ns (weighted slack = 325.938ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i0  (from PHI2_c +)
-   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
-
-   Delay:              11.766ns  (23.7% logic, 76.3% route), 7 logic levels.
-
- Constraint Details:
-
-     11.766ns physical path delay SLICE_93 to SLICE_23 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.969ns
-
- Physical Path Details:
-
-      Data path SLICE_93 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
-ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
-CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
-ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
-CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
-ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
-CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
-ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
-CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
-ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
-CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
-ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
-ROUTE         2     2.130       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   11.766   (23.7% logic, 76.3% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R7C3A.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 163.029ns (weighted slack = 326.058ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
-
-   Delay:              11.706ns  (23.8% logic, 76.2% route), 7 logic levels.
-
- Constraint Details:
-
-     11.706ns physical path delay SLICE_98 to SLICE_23 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 163.029ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
-ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
-CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
-ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
-CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
-ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
-CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
-ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
-CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
-ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
-CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
-ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
-ROUTE         2     2.130       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   11.706   (23.8% logic, 76.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R7C3A.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 163.113ns (weighted slack = 326.226ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i0  (from PHI2_c +)
-   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
-
-   Delay:              11.622ns  (24.0% logic, 76.0% route), 7 logic levels.
-
- Constraint Details:
-
-     11.622ns physical path delay SLICE_93 to SLICE_94 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 163.113ns
-
- Physical Path Details:
-
-      Data path SLICE_93 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
-ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
-CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
-ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
-CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
-ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
-CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
-ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
-CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
-ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
-CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
-ROUTE         3     1.057       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R7C3C.A0 to       R7C3C.F0 SLICE_97
-ROUTE         1     1.656       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
-                  --------
-                   11.622   (24.0% logic, 76.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R8C5C.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 163.173ns (weighted slack = 326.346ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
-
-   Delay:              11.562ns  (24.1% logic, 75.9% route), 7 logic levels.
-
- Constraint Details:
-
-     11.562ns physical path delay SLICE_98 to SLICE_94 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 163.173ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
-ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
-CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
-ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
-CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
-ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
-CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
-ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
-CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
-ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
-CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
-ROUTE         3     1.057       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R7C3C.A0 to       R7C3C.F0 SLICE_97
-ROUTE         1     1.656       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
-                  --------
-                   11.562   (24.1% logic, 75.9% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R8C5C.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 163.236ns (weighted slack = 326.472ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
-
-   Delay:              11.499ns  (24.2% logic, 75.8% route), 7 logic levels.
-
- Constraint Details:
-
-     11.499ns physical path delay SLICE_90 to SLICE_23 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 163.236ns
-
- Physical Path Details:
-
-      Data path SLICE_90 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C3A.CLK to       R2C3A.Q1 SLICE_90 (from PHI2_c)
-ROUTE         1     0.819       R2C3A.Q1 to R2C3A.C1       Bank_5
-CTOF_DEL    ---     0.371       R2C3A.C1 to       R2C3A.F1 SLICE_90
-ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
-CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
-ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
-CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
-ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
-CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
-ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
-CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
-ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
-ROUTE         2     2.130       R6C3A.F0 to R7C3A.CE       PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   11.499   (24.2% logic, 75.8% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R2C3A.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R7C3A.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 163.277ns (weighted slack = 326.554ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i0  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
-
-   Delay:              11.458ns  (24.3% logic, 75.7% route), 7 logic levels.
-
- Constraint Details:
-
-     11.458ns physical path delay SLICE_93 to SLICE_77 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 163.277ns
-
- Physical Path Details:
-
-      Data path SLICE_93 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
-ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
-CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
-ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
-CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
-ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
-CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
-ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
-CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
-ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
-CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
-ROUTE         3     1.379       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C5A.C1 to       R4C5A.F1 SLICE_73
-ROUTE         2     1.170       R4C5A.F1 to R7C5C.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   11.458   (24.3% logic, 75.7% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R7C5C.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 163.337ns (weighted slack = 326.674ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
-
-   Delay:              11.398ns  (24.4% logic, 75.6% route), 7 logic levels.
-
- Constraint Details:
-
-     11.398ns physical path delay SLICE_98 to SLICE_77 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 163.337ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
-ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
-CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
-ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
-CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
-ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
-CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
-ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
-CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
-ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
-CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
-ROUTE         3     1.379       R6C3A.F1 to R4C5A.C1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R4C5A.C1 to       R4C5A.F1 SLICE_73
-ROUTE         2     1.170       R4C5A.F1 to R7C5C.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   11.398   (24.4% logic, 75.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R7C5C.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 163.380ns (weighted slack = 326.760ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
-
-   Delay:              11.355ns  (24.5% logic, 75.5% route), 7 logic levels.
-
- Constraint Details:
-
-     11.355ns physical path delay SLICE_90 to SLICE_94 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 163.380ns
-
- Physical Path Details:
-
-      Data path SLICE_90 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C3A.CLK to       R2C3A.Q1 SLICE_90 (from PHI2_c)
-ROUTE         1     0.819       R2C3A.Q1 to R2C3A.C1       Bank_5
-CTOF_DEL    ---     0.371       R2C3A.C1 to       R2C3A.F1 SLICE_90
-ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
-CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
-ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
-CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
-ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
-CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
-ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
-CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
-ROUTE         3     1.057       R6C3A.F1 to R7C3C.A0       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R7C3C.A0 to       R7C3C.F0 SLICE_97
-ROUTE         1     1.656       R7C3C.F0 to R8C5C.CE       PHI2_N_114_enable_2 (to PHI2_c)
-                  --------
-                   11.355   (24.5% logic, 75.5% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R2C3A.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R8C5C.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 163.430ns (weighted slack = 326.860ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i0  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
-
-   Delay:              11.305ns  (24.6% logic, 75.4% route), 7 logic levels.
-
- Constraint Details:
-
-     11.305ns physical path delay SLICE_93 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 163.430ns
-
- Physical Path Details:
-
-      Data path SLICE_93 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_93 (from PHI2_c)
-ROUTE         1     1.086       R2C2B.Q0 to R2C3A.B1       Bank_0
-CTOF_DEL    ---     0.371       R2C3A.B1 to       R2C3A.F1 SLICE_90
-ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
-CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
-ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
-CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
-ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
-CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
-ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
-CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
-ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
-ROUTE         2     1.669       R6C3A.F0 to R7C4D.CE       PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   11.305   (24.6% logic, 75.4% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R2C2B.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R7C4D.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 163.490ns (weighted slack = 326.980ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
-
-   Delay:              11.245ns  (24.8% logic, 75.2% route), 7 logic levels.
-
- Constraint Details:
-
-     11.245ns physical path delay SLICE_98 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 163.490ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_98 (from PHI2_c)
-ROUTE         1     1.026       R2C2C.Q0 to R2C3A.A1       Bank_6
-CTOF_DEL    ---     0.371       R2C3A.A1 to       R2C3A.F1 SLICE_90
-ROUTE         1     1.643       R2C3A.F1 to R5C4D.B1       n2160
-CTOF_DEL    ---     0.371       R5C4D.B1 to       R5C4D.F1 SLICE_84
-ROUTE         1     0.819       R5C4D.F1 to R5C4B.C1       n26
-CTOF_DEL    ---     0.371       R5C4B.C1 to       R5C4B.F1 SLICE_74
-ROUTE         5     1.601       R5C4B.F1 to R6C3C.B1       n1279
-CTOF_DEL    ---     0.371       R6C3C.B1 to       R6C3C.F1 SLICE_9
-ROUTE         2     0.974       R6C3C.F1 to R6C3A.A1       n2288
-CTOF_DEL    ---     0.371       R6C3A.A1 to       R6C3A.F1 SLICE_76
-ROUTE         3     0.727       R6C3A.F1 to R6C3A.B0       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R6C3A.B0 to       R6C3A.F0 SLICE_76
-ROUTE         2     1.669       R6C3A.F0 to R7C4D.CE       PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   11.245   (24.8% logic, 75.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R2C2C.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.924       39.PADDI to R7C4D.CLK      PHI2_c
-                  --------
-                    3.924   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   24.062ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_73
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_74
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 15.000000 ns  ;
-            10 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
- 
-
-Passed: The following path meets requirements by 6.275ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
-
-   Delay:               8.481ns  (28.5% logic, 71.5% route), 6 logic levels.
-
- Constraint Details:
-
-      8.481ns physical path delay SLICE_7 to SLICE_85 meets
-     15.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 14.756ns) by 6.275ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
-ROUTE         3     1.466       R8C4D.Q0 to R8C5D.B1       FS_14
-CTOF_DEL    ---     0.371       R8C5D.B1 to       R8C5D.F1 SLICE_78
-ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
-CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
-ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
-CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
-ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
-CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
-ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
-CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
-ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.481   (28.5% logic, 71.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 6.434ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
-
-   Delay:               8.322ns  (29.0% logic, 71.0% route), 6 logic levels.
-
- Constraint Details:
-
-      8.322ns physical path delay SLICE_7 to SLICE_56 meets
-     15.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 14.756ns) by 6.434ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q0 SLICE_7 (from RCLK_c)
-ROUTE         3     1.466       R8C4D.Q0 to R8C5D.B1       FS_14
-CTOF_DEL    ---     0.371       R8C5D.B1 to       R8C5D.F1 SLICE_78
-ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
-CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
-ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
-CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
-ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
-CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
-ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
-CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
-ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    8.322   (29.0% logic, 71.0% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 6.474ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
-
-   Delay:               8.282ns  (29.2% logic, 70.8% route), 6 logic levels.
-
- Constraint Details:
-
-      8.282ns physical path delay SLICE_7 to SLICE_85 meets
-     15.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 14.756ns) by 6.474ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
-ROUTE         3     1.267       R8C4D.Q1 to R8C5D.C1       FS_15
-CTOF_DEL    ---     0.371       R8C5D.C1 to       R8C5D.F1 SLICE_78
-ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
-CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
-ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
-CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
-ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
-CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
-ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
-CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
-ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.282   (29.2% logic, 70.8% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 6.633ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
-
-   Delay:               8.123ns  (29.7% logic, 70.3% route), 6 logic levels.
-
- Constraint Details:
-
-      8.123ns physical path delay SLICE_7 to SLICE_56 meets
-     15.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 14.756ns) by 6.633ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4D.CLK to       R8C4D.Q1 SLICE_7 (from RCLK_c)
-ROUTE         3     1.267       R8C4D.Q1 to R8C5D.C1       FS_15
-CTOF_DEL    ---     0.371       R8C5D.C1 to       R8C5D.F1 SLICE_78
-ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
-CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
-ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
-CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
-ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
-CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
-ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
-CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
-ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    8.123   (29.7% logic, 70.3% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R8C4D.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 6.693ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
-
-   Delay:               8.063ns  (30.0% logic, 70.0% route), 6 logic levels.
-
- Constraint Details:
-
-      8.063ns physical path delay SLICE_8 to SLICE_85 meets
-     15.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 14.756ns) by 6.693ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
-ROUTE         3     1.048       R8C4C.Q1 to R8C5D.A1       FS_13
-CTOF_DEL    ---     0.371       R8C5D.A1 to       R8C5D.F1 SLICE_78
-ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
-CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
-ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
-CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
-ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
-CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
-ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
-CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
-ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.063   (30.0% logic, 70.0% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R8C4C.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 6.852ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
-
-   Delay:               7.904ns  (30.6% logic, 69.4% route), 6 logic levels.
-
- Constraint Details:
-
-      7.904ns physical path delay SLICE_8 to SLICE_56 meets
-     15.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 14.756ns) by 6.852ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q1 SLICE_8 (from RCLK_c)
-ROUTE         3     1.048       R8C4C.Q1 to R8C5D.A1       FS_13
-CTOF_DEL    ---     0.371       R8C5D.A1 to       R8C5D.F1 SLICE_78
-ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
-CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
-ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
-CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
-ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
-CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
-ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
-CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
-ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    7.904   (30.6% logic, 69.4% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R8C4C.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 6.891ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i2  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
-
-   Delay:               7.865ns  (26.0% logic, 74.0% route), 5 logic levels.
-
- Constraint Details:
-
-      7.865ns physical path delay SLICE_4 to SLICE_85 meets
-     15.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 14.756ns) by 6.891ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C3B.CLK to       R8C3B.Q0 SLICE_4 (from RCLK_c)
-ROUTE         2     1.563       R8C3B.Q0 to R7C4C.B1       FS_2
-CTOF_DEL    ---     0.371       R7C4C.B1 to       R7C4C.F1 SLICE_68
-ROUTE         1     1.487       R7C4C.F1 to R9C5A.A0       n2164
-CTOF_DEL    ---     0.371       R9C5A.A0 to       R9C5A.F0 SLICE_75
-ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
-CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
-ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
-CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
-ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    7.865   (26.0% logic, 74.0% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R8C3B.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 6.951ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i1  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
-
-   Delay:               7.805ns  (26.2% logic, 73.8% route), 5 logic levels.
-
- Constraint Details:
-
-      7.805ns physical path delay SLICE_5 to SLICE_85 meets
-     15.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 14.756ns) by 6.951ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C3A.CLK to       R8C3A.Q1 SLICE_5 (from RCLK_c)
-ROUTE         2     1.503       R8C3A.Q1 to R7C4C.A1       FS_1
-CTOF_DEL    ---     0.371       R7C4C.A1 to       R7C4C.F1 SLICE_68
-ROUTE         1     1.487       R7C4C.F1 to R9C5A.A0       n2164
-CTOF_DEL    ---     0.371       R9C5A.A0 to       R9C5A.F0 SLICE_75
-ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
-CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
-ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
-CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
-ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    7.805   (26.2% logic, 73.8% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R8C3A.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 7.017ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i12  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
-
-   Delay:               7.739ns  (31.2% logic, 68.8% route), 6 logic levels.
-
- Constraint Details:
-
-      7.739ns physical path delay SLICE_8 to SLICE_85 meets
-     15.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 14.756ns) by 7.017ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C4C.CLK to       R8C4C.Q0 SLICE_8 (from RCLK_c)
-ROUTE         3     0.724       R8C4C.Q0 to R8C5D.D1       FS_12
-CTOF_DEL    ---     0.371       R8C5D.D1 to       R8C5D.F1 SLICE_78
-ROUTE         3     1.117       R8C5D.F1 to R9C5A.B1       n10
-CTOF_DEL    ---     0.371       R9C5A.B1 to       R9C5A.F1 SLICE_75
-ROUTE         4     0.712       R9C5A.F1 to R9C5A.B0       n2298
-CTOF_DEL    ---     0.371       R9C5A.B0 to       R9C5A.F0 SLICE_75
-ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
-CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
-ROUTE         2     1.042       R7C5C.F1 to R5C5A.A1       n2111
-CTOF_DEL    ---     0.371       R5C5A.A1 to       R5C5A.F1 SLICE_100
-ROUTE         1     0.703       R5C5A.F1 to R7C5D.CE       RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    7.739   (31.2% logic, 68.8% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R8C4C.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R7C5D.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 7.050ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i2  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
-
-   Delay:               7.706ns  (26.5% logic, 73.5% route), 5 logic levels.
-
- Constraint Details:
-
-      7.706ns physical path delay SLICE_4 to SLICE_56 meets
-     15.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 14.756ns) by 7.050ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C3B.CLK to       R8C3B.Q0 SLICE_4 (from RCLK_c)
-ROUTE         2     1.563       R8C3B.Q0 to R7C4C.B1       FS_2
-CTOF_DEL    ---     0.371       R7C4C.B1 to       R7C4C.F1 SLICE_68
-ROUTE         1     1.487       R7C4C.F1 to R9C5A.A0       n2164
-CTOF_DEL    ---     0.371       R9C5A.A0 to       R9C5A.F0 SLICE_75
-ROUTE         1     1.026       R9C5A.F0 to R7C5C.A1       n11
-CTOF_DEL    ---     0.371       R7C5C.A1 to       R7C5C.F1 SLICE_77
-ROUTE         2     0.513       R7C5C.F1 to R7C5C.C0       n2111
-CTOF_DEL    ---     0.371       R7C5C.C0 to       R7C5C.F0 SLICE_77
-ROUTE         1     1.073       R7C5C.F0 to R7C4B.CE       RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    7.706   (26.5% logic, 73.5% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R8C3B.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.353       86.PADDI to R7C4B.CLK      RCLK_c
-                  --------
-                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:    8.725ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.904ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_368  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     6.180ns  (67.9% logic, 32.1% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_55 and
-      6.180ns delay SLICE_55 to RA[10] (totaling 8.596ns) meets
-     12.500ns offset RCLK to RA[10] by 3.904ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R2C4B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     1.984       R2C4B.Q0 to 87.PADDO       n974
-DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
-                  --------
-                    6.180   (67.9% logic, 32.1% route), 2 logic levels.
-
-Report:    8.596ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 7.280ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_368  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     5.683ns  (73.0% logic, 27.0% route), 2 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_55 and
-      5.683ns delay SLICE_55 to RA[10] (totaling 7.280ns) meets
-      0.000ns hold offset RCLK to RA[10] by 7.280ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R2C4B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C4B.CLK to       R2C4B.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     1.532       R2C4B.Q0 to 87.PADDO       n974
-DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
-                  --------
-                    5.683   (73.0% logic, 27.0% route), 2 logic levels.
-
-Report:    7.280ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.684ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     8.400ns  (54.4% logic, 45.6% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      8.400ns delay SLICE_64 to RA[9] (totaling 10.816ns) meets
-     12.500ns offset RCLK to RA[9] by 1.684ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.781       R7C2B.Q0 to R3C5A.D1       nRowColSel
-CTOF_DEL    ---     0.371       R3C5A.D1 to       R3C5A.F1 SLICE_87
-ROUTE         1     2.052       R3C5A.F1 to 85.PADDO       RA_c_9
-DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
-                  --------
-                    8.400   (54.4% logic, 45.6% route), 3 logic levels.
-
-Report:   10.816ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 9.193ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     7.596ns  (58.6% logic, 41.4% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      7.596ns delay SLICE_64 to RA[9] (totaling 9.193ns) meets
-      0.000ns hold offset RCLK to RA[9] by 9.193ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.534       R7C2B.Q0 to R3C5A.D1       nRowColSel
-CTOF_DEL    ---     0.301       R3C5A.D1 to       R3C5A.F1 SLICE_87
-ROUTE         1     1.610       R3C5A.F1 to 85.PADDO       RA_c_9
-DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
-                  --------
-                    7.596   (58.6% logic, 41.4% route), 3 logic levels.
-
-Report:    9.193ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.988ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     7.096ns  (64.4% logic, 35.6% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.096ns delay SLICE_64 to RA[8] (totaling 9.512ns) meets
-     12.500ns offset RCLK to RA[8] by 2.988ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.712       R7C2B.Q0 to R2C2C.D0       nRowColSel
-CTOF_DEL    ---     0.371       R2C2C.D0 to       R2C2C.F0 SLICE_98
-ROUTE         1     0.817       R2C2C.F0 to 96.PADDO       RA_c_8
-DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
-                  --------
-                    7.096   (64.4% logic, 35.6% route), 3 logic levels.
-
-Report:    9.512ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.119ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     6.522ns  (68.3% logic, 31.7% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      6.522ns delay SLICE_64 to RA[8] (totaling 8.119ns) meets
-      0.000ns hold offset RCLK to RA[8] by 8.119ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.424       R7C2B.Q0 to R2C2C.D0       nRowColSel
-CTOF_DEL    ---     0.301       R2C2C.D0 to       R2C2C.F0 SLICE_98
-ROUTE         1     0.646       R2C2C.F0 to 96.PADDO       RA_c_8
-DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
-                  --------
-                    6.522   (68.3% logic, 31.7% route), 3 logic levels.
-
-Report:    8.119ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.977ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     7.107ns  (64.3% logic, 35.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.107ns delay SLICE_64 to RA[7] (totaling 9.523ns) meets
-     12.500ns offset RCLK to RA[7] by 2.977ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.880       R7C2B.Q0 to R7C2B.C1       nRowColSel
-CTOF_DEL    ---     0.371       R7C2B.C1 to       R7C2B.F1 SLICE_64
-ROUTE         1     1.660       R7C2B.F1 to 100.PADDO      RA_c_7
-DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
-                  --------
-                    7.107   (64.3% logic, 35.7% route), 3 logic levels.
-
-Report:    9.523ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.063ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     6.466ns  (68.9% logic, 31.1% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      6.466ns delay SLICE_64 to RA[7] (totaling 8.063ns) meets
-      0.000ns hold offset RCLK to RA[7] by 8.063ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.726       R7C2B.Q0 to R7C2B.C1       nRowColSel
-CTOF_DEL    ---     0.301       R7C2B.C1 to       R7C2B.F1 SLICE_64
-ROUTE         1     1.288       R7C2B.F1 to 100.PADDO      RA_c_7
-DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
-                  --------
-                    6.466   (68.9% logic, 31.1% route), 3 logic levels.
-
-Report:    8.063ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.822ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     8.262ns  (55.3% logic, 44.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      8.262ns delay SLICE_64 to RA[6] (totaling 10.678ns) meets
-     12.500ns offset RCLK to RA[6] by 1.822ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.712       R7C2B.Q0 to R2C2C.D1       nRowColSel
-CTOF_DEL    ---     0.371       R2C2C.D1 to       R2C2C.F1 SLICE_98
-ROUTE         1     1.983       R2C2C.F1 to 91.PADDO       RA_c_6
-DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
-                  --------
-                    8.262   (55.3% logic, 44.7% route), 3 logic levels.
-
-Report:   10.678ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 9.044ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     7.447ns  (59.8% logic, 40.2% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      7.447ns delay SLICE_64 to RA[6] (totaling 9.044ns) meets
-      0.000ns hold offset RCLK to RA[6] by 9.044ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.424       R7C2B.Q0 to R2C2C.D1       nRowColSel
-CTOF_DEL    ---     0.301       R2C2C.D1 to       R2C2C.F1 SLICE_98
-ROUTE         1     1.571       R2C2C.F1 to 91.PADDO       RA_c_6
-DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
-                  --------
-                    7.447   (59.8% logic, 40.2% route), 3 logic levels.
-
-Report:    9.044ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.738ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     7.346ns  (62.2% logic, 37.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.346ns delay SLICE_64 to RA[5] (totaling 9.762ns) meets
-     12.500ns offset RCLK to RA[5] by 2.738ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.119       R7C2B.Q0 to R6C2A.A1       nRowColSel
-CTOF_DEL    ---     0.371       R6C2A.A1 to       R6C2A.F1 SLICE_95
-ROUTE         1     1.660       R6C2A.F1 to 95.PADDO       RA_c_5
-DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
-                  --------
-                    7.346   (62.2% logic, 37.8% route), 3 logic levels.
-
-Report:    9.762ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.252ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     6.655ns  (66.9% logic, 33.1% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      6.655ns delay SLICE_64 to RA[5] (totaling 8.252ns) meets
-      0.000ns hold offset RCLK to RA[5] by 8.252ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.915       R7C2B.Q0 to R6C2A.A1       nRowColSel
-CTOF_DEL    ---     0.301       R6C2A.A1 to       R6C2A.F1 SLICE_95
-ROUTE         1     1.288       R6C2A.F1 to 95.PADDO       RA_c_5
-DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
-                  --------
-                    6.655   (66.9% logic, 33.1% route), 3 logic levels.
-
-Report:    8.252ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.279ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     7.805ns  (58.5% logic, 41.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.805ns delay SLICE_64 to RA[4] (totaling 10.221ns) meets
-     12.500ns offset RCLK to RA[4] by 2.279ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.712       R7C2B.Q0 to R2C2B.D1       nRowColSel
-CTOF_DEL    ---     0.371       R2C2B.D1 to       R2C2B.F1 SLICE_93
-ROUTE         1     1.526       R2C2B.F1 to 99.PADDO       RA_c_4
-DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
-                  --------
-                    7.805   (58.5% logic, 41.5% route), 3 logic levels.
-
-Report:   10.221ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.638ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     7.041ns  (63.2% logic, 36.8% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      7.041ns delay SLICE_64 to RA[4] (totaling 8.638ns) meets
-      0.000ns hold offset RCLK to RA[4] by 8.638ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.424       R7C2B.Q0 to R2C2B.D1       nRowColSel
-CTOF_DEL    ---     0.301       R2C2B.D1 to       R2C2B.F1 SLICE_93
-ROUTE         1     1.165       R2C2B.F1 to 99.PADDO       RA_c_4
-DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
-                  --------
-                    7.041   (63.2% logic, 36.8% route), 3 logic levels.
-
-Report:    8.638ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.800ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     8.284ns  (55.1% logic, 44.9% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      8.284ns delay SLICE_64 to RA[3] (totaling 10.700ns) meets
-     12.500ns offset RCLK to RA[3] by 1.800ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.733       R7C2B.Q0 to R2C3B.D1       nRowColSel
-CTOF_DEL    ---     0.371       R2C3B.D1 to       R2C3B.F1 SLICE_92
-ROUTE         1     1.984       R2C3B.F1 to 97.PADDO       RA_c_3
-DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
-                  --------
-                    8.284   (55.1% logic, 44.9% route), 3 logic levels.
-
-Report:   10.700ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 9.042ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     7.445ns  (59.8% logic, 40.2% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      7.445ns delay SLICE_64 to RA[3] (totaling 9.042ns) meets
-      0.000ns hold offset RCLK to RA[3] by 9.042ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.461       R7C2B.Q0 to R2C3B.D1       nRowColSel
-CTOF_DEL    ---     0.301       R2C3B.D1 to       R2C3B.F1 SLICE_92
-ROUTE         1     1.532       R2C3B.F1 to 97.PADDO       RA_c_3
-DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
-                  --------
-                    7.445   (59.8% logic, 40.2% route), 3 logic levels.
-
-Report:    9.042ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.967ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     7.117ns  (64.2% logic, 35.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.117ns delay SLICE_64 to RA[2] (totaling 9.533ns) meets
-     12.500ns offset RCLK to RA[2] by 2.967ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.733       R7C2B.Q0 to R2C3A.D0       nRowColSel
-CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_90
-ROUTE         1     0.817       R2C3A.F0 to 94.PADDO       RA_c_2
-DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
-                  --------
-                    7.117   (64.2% logic, 35.8% route), 3 logic levels.
-
-Report:    9.533ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.156ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     6.559ns  (67.9% logic, 32.1% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      6.559ns delay SLICE_64 to RA[2] (totaling 8.156ns) meets
-      0.000ns hold offset RCLK to RA[2] by 8.156ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.461       R7C2B.Q0 to R2C3A.D0       nRowColSel
-CTOF_DEL    ---     0.301       R2C3A.D0 to       R2C3A.F0 SLICE_90
-ROUTE         1     0.646       R2C3A.F0 to 94.PADDO       RA_c_2
-DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
-                  --------
-                    6.559   (67.9% logic, 32.1% route), 3 logic levels.
-
-Report:    8.156ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.967ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     7.117ns  (64.2% logic, 35.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.117ns delay SLICE_64 to RA[1] (totaling 9.533ns) meets
-     12.500ns offset RCLK to RA[1] by 2.967ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.733       R7C2B.Q0 to R2C3B.D0       nRowColSel
-CTOF_DEL    ---     0.371       R2C3B.D0 to       R2C3B.F0 SLICE_92
-ROUTE         1     0.817       R2C3B.F0 to 89.PADDO       RA_c_1
-DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
-                  --------
-                    7.117   (64.2% logic, 35.8% route), 3 logic levels.
-
-Report:    9.533ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.156ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     6.559ns  (67.9% logic, 32.1% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      6.559ns delay SLICE_64 to RA[1] (totaling 8.156ns) meets
-      0.000ns hold offset RCLK to RA[1] by 8.156ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.461       R7C2B.Q0 to R2C3B.D0       nRowColSel
-CTOF_DEL    ---     0.301       R2C3B.D0 to       R2C3B.F0 SLICE_92
-ROUTE         1     0.646       R2C3B.F0 to 89.PADDO       RA_c_1
-DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
-                  --------
-                    6.559   (67.9% logic, 32.1% route), 3 logic levels.
-
-Report:    8.156ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.988ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     7.096ns  (64.4% logic, 35.6% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.096ns delay SLICE_64 to RA[0] (totaling 9.512ns) meets
-     12.500ns offset RCLK to RA[0] by 2.988ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.712       R7C2B.Q0 to R2C2B.D0       nRowColSel
-CTOF_DEL    ---     0.371       R2C2B.D0 to       R2C2B.F0 SLICE_93
-ROUTE         1     0.817       R2C2B.F0 to 98.PADDO       RA_c_0
-DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
-                  --------
-                    7.096   (64.4% logic, 35.6% route), 3 logic levels.
-
-Report:    9.512ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.119ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     6.522ns  (68.3% logic, 31.7% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      6.522ns delay SLICE_64 to RA[0] (totaling 8.119ns) meets
-      0.000ns hold offset RCLK to RA[0] by 8.119ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.424       R7C2B.Q0 to R2C2B.D0       nRowColSel
-CTOF_DEL    ---     0.301       R2C2B.D0 to       R2C2B.F0 SLICE_93
-ROUTE         1     0.646       R2C2B.F0 to 98.PADDO       RA_c_0
-DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
-                  --------
-                    6.522   (68.3% logic, 31.7% route), 3 logic levels.
-
-Report:    8.119ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 5.071ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_364  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_60 and
-      5.013ns delay SLICE_60 to nRCS (totaling 7.429ns) meets
-     12.500ns offset RCLK to nRCS by 5.071ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R2C5B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.817       R2C5B.Q0 to 77.PADDO       nRCS_c
-DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.429ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 6.394ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_364  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_60 and
-      4.797ns delay SLICE_60 to nRCS (totaling 6.394ns) meets
-      0.000ns hold offset RCLK to nRCS by 6.394ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R2C5B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C5B.CLK to       R2C5B.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.646       R2C5B.Q0 to 77.PADDO       nRCS_c
-DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
-                  --------
-                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    6.394ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.806ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_363  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     6.278ns  (66.8% logic, 33.2% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_34 and
-      6.278ns delay SLICE_34 to RCKE (totaling 8.694ns) meets
-     12.500ns offset RCLK to RCKE by 3.806ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R6C5B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R6C5B.CLK to       R6C5B.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     2.082       R6C5B.Q0 to 82.PADDO       RCKE_c
-DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
-                  --------
-                    6.278   (66.8% logic, 33.2% route), 2 logic levels.
-
-Report:    8.694ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 7.385ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_363  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     5.788ns  (71.7% logic, 28.3% route), 2 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_34 and
-      5.788ns delay SLICE_34 to RCKE (totaling 7.385ns) meets
-      0.000ns hold offset RCLK to RCKE by 7.385ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R6C5B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R6C5B.CLK to       R6C5B.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     1.637       R6C5B.Q0 to 82.PADDO       RCKE_c
-DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
-                  --------
-                    5.788   (71.7% logic, 28.3% route), 2 logic levels.
-
-Report:    7.385ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 5.071ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_367  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_63 and
-      5.013ns delay SLICE_63 to nRWE (totaling 7.429ns) meets
-     12.500ns offset RCLK to nRWE by 5.071ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R3C5B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     0.817       R3C5B.Q0 to 72.PADDO       nRWE_c
-DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.429ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 6.394ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_367  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_63 and
-      4.797ns delay SLICE_63 to nRWE (totaling 6.394ns) meets
-      0.000ns hold offset RCLK to nRWE by 6.394ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R3C5B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R3C5B.CLK to       R3C5B.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     0.646       R3C5B.Q0 to 72.PADDO       nRWE_c
-DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
-                  --------
-                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    6.394ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.360ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     5.724ns  (73.3% logic, 26.7% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_61 and
-      5.724ns delay SLICE_61 to nRRAS (totaling 8.140ns) meets
-     12.500ns offset RCLK to nRRAS by 4.360ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R2C4C.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     1.528       R2C4C.Q0 to 73.PADDO       nRRAS_c
-DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
-                  --------
-                    5.724   (73.3% logic, 26.7% route), 2 logic levels.
-
-Report:    8.140ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 6.920ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     5.323ns  (78.0% logic, 22.0% route), 2 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_61 and
-      5.323ns delay SLICE_61 to nRRAS (totaling 6.920ns) meets
-      0.000ns hold offset RCLK to nRRAS by 6.920ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R2C4C.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C4C.CLK to       R2C4C.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     1.172       R2C4C.Q0 to 73.PADDO       nRRAS_c
-DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
-                  --------
-                    5.323   (78.0% logic, 22.0% route), 2 logic levels.
-
-Report:    6.920ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.904ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     6.180ns  (67.9% logic, 32.1% route), 2 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_58 and
-      6.180ns delay SLICE_58 to nRCAS (totaling 8.596ns) meets
-     12.500ns offset RCLK to nRCAS by 3.904ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R2C4A.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C4A.CLK to       R2C4A.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     1.984       R2C4A.Q0 to 78.PADDO       nRCAS_c
-DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
-                  --------
-                    6.180   (67.9% logic, 32.1% route), 2 logic levels.
-
-Report:    8.596ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 7.280ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     5.683ns  (73.0% logic, 27.0% route), 2 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_58 and
-      5.683ns delay SLICE_58 to nRCAS (totaling 7.280ns) meets
-      0.000ns hold offset RCLK to nRCAS by 7.280ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R2C4A.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C4A.CLK to       R2C4A.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     1.532       R2C4A.Q0 to 78.PADDO       nRCAS_c
-DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
-                  --------
-                    5.683   (73.0% logic, 27.0% route), 2 logic levels.
-
-Report:    7.280ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.919ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     7.165ns  (63.7% logic, 36.3% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.165ns delay SLICE_64 to RDQMH (totaling 9.581ns) meets
-     12.500ns offset RCLK to RDQMH by 2.919ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.781       R7C2B.Q0 to R3C5A.D0       nRowColSel
-CTOF_DEL    ---     0.371       R3C5A.D0 to       R3C5A.F0 SLICE_87
-ROUTE         1     0.817       R3C5A.F0 to 76.PADDO       RDQMH_c
-DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
-                  --------
-                    7.165   (63.7% logic, 36.3% route), 3 logic levels.
-
-Report:    9.581ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.229ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     6.632ns  (67.1% logic, 32.9% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      6.632ns delay SLICE_64 to RDQMH (totaling 8.229ns) meets
-      0.000ns hold offset RCLK to RDQMH by 8.229ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.534       R7C2B.Q0 to R3C5A.D0       nRowColSel
-CTOF_DEL    ---     0.301       R3C5A.D0 to       R3C5A.F0 SLICE_87
-ROUTE         1     0.646       R3C5A.F0 to 76.PADDO       RDQMH_c
-DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
-                  --------
-                    6.632   (67.1% logic, 32.9% route), 3 logic levels.
-
-Report:    8.229ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.415ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     7.669ns  (59.6% logic, 40.4% route), 3 logic levels.
-
-   Clock Path Delay:    2.416ns  (44.0% logic, 56.0% route), 1 logic levels.
-
- Constraint Details:
-      2.416ns delay RCLK to SLICE_64 and
-      7.669ns delay SLICE_64 to RDQML (totaling 10.085ns) meets
-     12.500ns offset RCLK to RDQML by 2.415ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.353       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    2.416   (44.0% logic, 56.0% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.119       R7C2B.Q0 to R6C2A.A0       nRowColSel
-CTOF_DEL    ---     0.371       R6C2A.A0 to       R6C2A.F0 SLICE_95
-ROUTE         1     1.983       R6C2A.F0 to 61.PADDO       RDQML_c
-DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
-                  --------
-                    7.669   (59.6% logic, 40.4% route), 3 logic levels.
-
-Report:   10.085ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.535ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     6.938ns  (64.2% logic, 35.8% route), 3 logic levels.
-
-   Clock Path Delay:    1.597ns  (54.3% logic, 45.7% route), 1 logic levels.
-
- Constraint Details:
-      1.597ns delay RCLK to SLICE_64 and
-      6.938ns delay SLICE_64 to RDQML (totaling 8.535ns) meets
-      0.000ns hold offset RCLK to RDQML by 8.535ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.730       86.PADDI to R7C2B.CLK      RCLK_c
-                  --------
-                    1.597   (54.3% logic, 45.7% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R7C2B.CLK to       R7C2B.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.915       R7C2B.Q0 to R6C2A.A0       nRowColSel
-CTOF_DEL    ---     0.301       R6C2A.A0 to       R6C2A.F0 SLICE_95
-ROUTE         1     1.571       R6C2A.F0 to 61.PADDO       RDQML_c
-DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
-                  --------
-                    6.938   (64.2% logic, 35.8% route), 3 logic levels.
-
-Report:    8.535ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    24.062 ns|   7  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 15.000000 ns  ;     |    15.000 ns|     8.725 ns|   6  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.596 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.280 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.816 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.193 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.512 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.119 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.523 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.063 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.678 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.044 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.762 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.252 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.221 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.638 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.700 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.042 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.533 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.156 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.533 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.156 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.512 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.119 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.429 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.394 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.694 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.385 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.429 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.394 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.140 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.920 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.596 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.280 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.581 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.229 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.085 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.535 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 15.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 538 paths, 6 nets, and 436 connections (70.89% coverage)
-
diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/automake.log b/CPLD-old/LCMXO/LCMXO256C/impl1/automake.log
deleted file mode 100644
index e197df1..0000000
--- a/CPLD-old/LCMXO/LCMXO256C/impl1/automake.log
+++ /dev/null
@@ -1,528 +0,0 @@
-
-ibisgen "RAM2GS_LCMXO256C_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo.ibs"   
-IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
-
-Mon Aug 16 21:36:25 2021
-
-Comp: CROW[0]
- Site: 32
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: CROW[1]
- Site: 34
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[0]
- Site: 21
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[1]
- Site: 15
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[2]
- Site: 14
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[3]
- Site: 16
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[4]
- Site: 18
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[5]
- Site: 17
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[6]
- Site: 20
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[7]
- Site: 19
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Dout[0]
- Site: 1
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[1]
- Site: 7
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[2]
- Site: 8
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[3]
- Site: 6
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[4]
- Site: 4
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[5]
- Site: 5
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[6]
- Site: 2
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[7]
- Site: 3
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: LED
- Site: 57
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=16mA 
- SLEW=SLOW 
------------------------
-Comp: MAin[0]
- Site: 23
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[1]
- Site: 38
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[2]
- Site: 37
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[3]
- Site: 47
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[4]
- Site: 46
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[5]
- Site: 45
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[6]
- Site: 49
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[7]
- Site: 44
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[8]
- Site: 50
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[9]
- Site: 51
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: PHI2
- Site: 39
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: RA[0]
- Site: 98
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[10]
- Site: 87
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[11]
- Site: 79
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[1]
- Site: 89
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[2]
- Site: 94
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[3]
- Site: 97
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[4]
- Site: 99
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[5]
- Site: 95
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[6]
- Site: 91
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[7]
- Site: 100
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[8]
- Site: 96
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[9]
- Site: 85
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RBA[0]
- Site: 63
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RBA[1]
- Site: 83
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RCKE
- Site: 82
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RCLK
- Site: 86
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: RDQMH
- Site: 76
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RDQML
- Site: 61
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RD[0]
- Site: 64
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[1]
- Site: 65
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[2]
- Site: 66
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[3]
- Site: 67
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[4]
- Site: 68
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[5]
- Site: 69
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[6]
- Site: 70
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[7]
- Site: 71
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: UFMCLK
- Site: 58
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: UFMSDI
- Site: 56
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: UFMSDO
- Site: 55
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: nCCAS
- Site: 27
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: nCRAS
- Site: 43
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: nFWE
- Site: 22
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: nRCAS
- Site: 78
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRCS
- Site: 77
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRRAS
- Site: 73
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRWE
- Site: 72
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nUFMCS
- Site: 53
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Created design models.
-
-
-Generating: C:\Users\Dog\Documents\GitHub\RAM2GS\CPLD\LCMXO\LCMXO256C\impl1\IBIS\RAM2GS_LCMXO256C_im~.ibs
-
-
-    
-
-tmcheck -par "RAM2GS_LCMXO256C_impl1.par" 
-
-bitgen -w "RAM2GS_LCMXO256C_impl1.ncd" -f "RAM2GS_LCMXO256C_impl1.t2b" "RAM2GS_LCMXO256C_impl1.prf"
-
-
-BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-
-Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
-
-Preference Summary:
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                             ES  |                           No**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
-Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 44 MB
-
-ddtcmd -dev LCMXO256C-XXT100 -if "RAM2GS_LCMXO256C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO256C_impl1.jed"  -comment "RAM2GS_LCMXO256C_impl1.alt" 
-Lattice Diamond Deployment Tool 3.12 Command Line
-
-Loading Programmer Device Database...
-
-Generating JED.....
-Device Name: LCMXO256C-XXT100
-Reading Input File: RAM2GS_LCMXO256C_impl1.bit
-Output File: RAM2GS_LCMXO256C_impl1.jed
-Comment file RAM2GS_LCMXO256C_impl1.alt.
-Generating JEDEC.....
-File RAM2GS_LCMXO256C_impl1.jed generated successfully.
-Lattice Diamond Deployment Tool has exited successfully.
-
diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html b/CPLD-old/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html
deleted file mode 100644
index 0b86833..0000000
--- a/CPLD-old/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html
+++ /dev/null
@@ -1,9 +0,0 @@
-         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/hdla_gen_hierarchy.html'.
-Starting: parse design source files
-(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
-(VERI-1482) Analyzing Verilog file 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v'
-INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
-INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,1-397,10) (VERI-9000) elaborating module 'RAM2GS'
-Done: design load finished with (0) errors, and (0) warnings
-
-
    
\ No newline at end of file
diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior b/CPLD-old/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
deleted file mode 100644
index 68dddcc..0000000
--- a/CPLD-old/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
+++ /dev/null
@@ -1,137 +0,0 @@
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 4
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-// Design: RAM2GS
-// Package: TQFP100
-// ncd File: ram2gs_lcmxo256c_impl1.ncd
-// Version: Diamond (64-bit) 3.12.0.240.2
-// Written on Mon Aug 16 21:32:34 2021
-// M: Minimum Performance Grade
-// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 5, 4, 3):
-
-// Input Setup and Hold Times
-
-Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-CROW[0] nCRAS F     0.215      3       1.805     3
-CROW[1] nCRAS F    -0.050      M       2.105     3
-Din[0]  PHI2  F     5.083      3       2.097     3
-Din[0]  nCCAS F    -0.020      M       2.133     3
-Din[1]  PHI2  F     3.519      3       2.454     3
-Din[1]  nCCAS F    -0.146      M       2.462     3
-Din[2]  PHI2  F     4.416      3       2.660     3
-Din[2]  nCCAS F     0.272      3       1.853     3
-Din[3]  PHI2  F     5.627      3       2.084     3
-Din[3]  nCCAS F    -0.024      M       2.144     3
-Din[4]  PHI2  F     4.808      3       2.117     3
-Din[4]  nCCAS F     0.350      3       1.766     3
-Din[5]  PHI2  F     5.446      3       2.212     3
-Din[5]  nCCAS F     0.435      3       1.708     3
-Din[6]  PHI2  F     5.339      3       1.487     3
-Din[6]  nCCAS F    -0.140      M       2.452     3
-Din[7]  PHI2  F     4.546      3       1.555     3
-Din[7]  nCCAS F    -0.016      M       2.122     3
-MAin[0] PHI2  F     4.027      3       0.711     3
-MAin[0] nCRAS F     1.132      3       0.987     3
-MAin[1] PHI2  F     4.032      3       1.734     3
-MAin[1] nCRAS F     0.704      3       1.373     3
-MAin[2] PHI2  F    10.358      3      -0.773     M
-MAin[2] nCRAS F    -0.202      M       2.529     3
-MAin[3] PHI2  F    10.442      3      -0.829     M
-MAin[3] nCRAS F     0.186      3       1.819     3
-MAin[4] PHI2  F    10.311      3      -0.765     M
-MAin[4] nCRAS F     0.569      3       1.506     3
-MAin[5] PHI2  F     7.007      3       0.178     3
-MAin[5] nCRAS F     0.186      3       1.819     3
-MAin[6] PHI2  F     9.786      3      -0.641     M
-MAin[6] nCRAS F     0.177      3       1.829     3
-MAin[7] PHI2  F    10.008      3      -0.718     M
-MAin[7] nCRAS F    -0.092      M       2.222     3
-MAin[8] nCRAS F    -0.202      M       2.532     3
-MAin[9] nCRAS F     0.228      3       1.797     3
-PHI2    RCLK  R     5.091      3      -0.759     M
-UFMSDO  RCLK  R     2.219      3      -0.104     M
-nCCAS   RCLK  R     3.820      3      -0.611     M
-nCCAS   nCRAS F     1.538      3       0.708     3
-nCRAS   RCLK  R     4.749      3      -0.670     M
-nFWE    PHI2  F     5.301      3       1.647     3
-nFWE    nCRAS F     1.049      3       1.128     3
-
-
-// Clock to Output Delay
-
-Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-LED    RCLK  R    11.669         3        3.051          M
-RA[0]  RCLK  R     9.674         3        2.492          M
-RA[0]  nCRAS F    12.127         3        3.067          M
-RA[10] RCLK  R     8.596         3        2.220          M
-RA[11] PHI2  R     9.987         3        2.559          M
-RA[1]  RCLK  R     8.766         3        2.284          M
-RA[1]  nCRAS F    11.652         3        2.982          M
-RA[2]  RCLK  R    10.062         3        2.599          M
-RA[2]  nCRAS F    12.947         3        3.306          M
-RA[3]  RCLK  R     9.933         3        2.555          M
-RA[3]  nCRAS F    12.783         3        3.240          M
-RA[4]  RCLK  R     8.504         3        2.219          M
-RA[4]  nCRAS F    11.513         3        2.948          M
-RA[5]  RCLK  R     9.609         3        2.481          M
-RA[5]  nCRAS F    11.870         3        3.010          M
-RA[6]  RCLK  R    10.001         3        2.579          M
-RA[6]  nCRAS F    12.947         3        3.292          M
-RA[7]  RCLK  R    10.255         3        2.652          M
-RA[7]  nCRAS F    12.177         3        3.089          M
-RA[8]  RCLK  R     8.896         3        2.316          M
-RA[8]  nCRAS F    11.417         3        2.920          M
-RA[9]  RCLK  R     8.766         3        2.284          M
-RA[9]  nCRAS F    11.617         3        2.957          M
-RBA[0] nCRAS F     9.698         3        2.483          M
-RBA[1] nCRAS F    11.425         3        2.916          M
-RCKE   RCLK  R     9.080         3        2.363          M
-RDQMH  RCLK  R     9.475         3        2.443          M
-RDQML  RCLK  R    10.477         3        2.713          M
-RD[0]  nCCAS F    11.252         3        2.942          M
-RD[1]  nCCAS F    11.963         3        3.100          M
-RD[2]  nCCAS F    12.880         3        3.336          M
-RD[3]  nCCAS F    12.422         3        3.224          M
-RD[4]  nCCAS F    11.252         3        2.942          M
-RD[5]  nCCAS F    12.423         3        3.212          M
-RD[6]  nCCAS F    12.979         3        3.375          M
-RD[7]  nCCAS F    12.914         3        3.350          M
-UFMCLK RCLK  R     8.007         3        2.126          M
-UFMSDI RCLK  R     8.007         3        2.126          M
-nRCAS  RCLK  R     8.595         3        2.232          M
-nRCS   RCLK  R     7.429         3        1.949          M
-nRRAS  RCLK  R     8.615         3        2.236          M
-nRWE   RCLK  R     7.429         3        1.949          M
-nUFMCS RCLK  R     9.193         3        2.413          M
-WARNING: you must also run trce with hold speed: 3
-WARNING: you must also run trce with setup speed: M
diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd b/CPLD-old/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd
deleted file mode 100644
index 7b7fee7..0000000
--- a/CPLD-old/LCMXO/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd
+++ /dev/null
@@ -1,91 +0,0 @@
-[ActiveSupport TRCE]
-; Setup Analysis
-Period_0 = 26.150 ns (350.000 ns);
-Period_1 = 2.000 ns (350.000 ns);
-Period_2 = 2.000 ns (350.000 ns);
-Period_3 = 8.434 ns (16.000 ns);
-Tco_4 = - (-);
-Tco_5 = - (-);
-Tco_6 = - (-);
-Tco_7 = - (-);
-Tco_8 = - (-);
-Tco_9 = - (-);
-Tco_10 = - (-);
-Tco_11 = - (-);
-Tco_12 = - (-);
-Tco_13 = - (-);
-Tco_14 = - (-);
-Tco_15 = - (-);
-Tco_16 = 8.596 ns (12.500 ns);
-Tco_17 = 8.766 ns (12.500 ns);
-Tco_18 = 8.896 ns (12.500 ns);
-Tco_19 = 10.255 ns (12.500 ns);
-Tco_20 = 10.001 ns (12.500 ns);
-Tco_21 = 9.609 ns (12.500 ns);
-Tco_22 = 8.504 ns (12.500 ns);
-Tco_23 = 9.933 ns (12.500 ns);
-Tco_24 = 10.062 ns (12.500 ns);
-Tco_25 = 8.766 ns (12.500 ns);
-Tco_26 = 9.674 ns (12.500 ns);
-Tco_27 = 7.429 ns (12.500 ns);
-Tco_28 = 9.080 ns (12.500 ns);
-Tco_29 = 7.429 ns (12.500 ns);
-Tco_30 = 8.615 ns (12.500 ns);
-Tco_31 = 8.595 ns (12.500 ns);
-Tco_32 = 9.475 ns (12.500 ns);
-Tco_33 = 10.477 ns (12.500 ns);
-Tco_34 = - (-);
-Tco_35 = - (-);
-Tco_36 = - (-);
-Tco_37 = - (-);
-Tco_38 = - (-);
-Tco_39 = - (-);
-Tco_40 = - (-);
-Failed = 0 (Total 41);
-Clock_ports = 4;
-Clock_nets = 4;
-; Hold Analysis
-Period_0 = - (-);
-Period_1 = - (-);
-Period_2 = - (-);
-Period_3 = - (-);
-Tco_4 = - (-);
-Tco_5 = - (-);
-Tco_6 = - (-);
-Tco_7 = - (-);
-Tco_8 = - (-);
-Tco_9 = - (-);
-Tco_10 = - (-);
-Tco_11 = - (-);
-Tco_12 = - (-);
-Tco_13 = - (-);
-Tco_14 = - (-);
-Tco_15 = - (-);
-Tco_16 = 2.220 ns (0.000 ns);
-Tco_17 = 2.284 ns (0.000 ns);
-Tco_18 = 2.316 ns (0.000 ns);
-Tco_19 = 2.652 ns (0.000 ns);
-Tco_20 = 2.579 ns (0.000 ns);
-Tco_21 = 2.481 ns (0.000 ns);
-Tco_22 = 2.219 ns (0.000 ns);
-Tco_23 = 2.555 ns (0.000 ns);
-Tco_24 = 2.599 ns (0.000 ns);
-Tco_25 = 2.284 ns (0.000 ns);
-Tco_26 = 2.492 ns (0.000 ns);
-Tco_27 = 1.949 ns (0.000 ns);
-Tco_28 = 2.363 ns (0.000 ns);
-Tco_29 = 1.949 ns (0.000 ns);
-Tco_30 = 2.236 ns (0.000 ns);
-Tco_31 = 2.232 ns (0.000 ns);
-Tco_32 = 2.443 ns (0.000 ns);
-Tco_33 = 2.713 ns (0.000 ns);
-Tco_34 = - (-);
-Tco_35 = - (-);
-Tco_36 = - (-);
-Tco_37 = - (-);
-Tco_38 = - (-);
-Tco_39 = - (-);
-Tco_40 = - (-);
-Failed = 0 (Total 41);
-Clock_ports = 4;
-Clock_nets = 4;
diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/synthesis.log b/CPLD-old/LCMXO/LCMXO256C/impl1/synthesis.log
deleted file mode 100644
index 70a7a9b..0000000
--- a/CPLD-old/LCMXO/LCMXO256C/impl1/synthesis.log
+++ /dev/null
@@ -1,239 +0,0 @@
-synthesis:  version Diamond (64-bit) 3.12.0.240.2
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Mon Aug 16 21:32:25 2021
-
-
-Command Line:  synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml 
-
-Synthesis options:
-The -a option is MachXO.
-The -s option is 3.
-The -t option is TQFP100.
-The -d option is LCMXO256C.
-Using package TQFP100.
-Using performance grade 3.
-                                                          
-
-##########################################################
-
-### Lattice Family : MachXO
-
-### Device  : LCMXO256C
-
-### Package : TQFP100
-
-### Speed   : 3
-
-##########################################################
-
-                                                          
-
-INFO - synthesis: User-Selected Strategy Settings
-Optimization goal = Balanced
-Top-level module name = RAM2GS.
-Target frequency = 200.000000 MHz.
-Maximum fanout = 1000.
-Timing path count = 3
-BRAM utilization = 100.000000 %
-DSP usage = true
-DSP utilization = 100.000000 %
-fsm_encoding_style = auto
-resolve_mixed_drivers = 0
-fix_gated_clocks = 1
-
-Mux style = Auto
-Use Carry Chain = true
-carry_chain_length = 0
-Loop Limit = 1950.
-Use IO Insertion = TRUE
-Use IO Reg = AUTO
-
-Resource Sharing = TRUE
-Propagate Constants = TRUE
-Remove Duplicate Registers = TRUE
-force_gsr = auto
-ROM style = auto
-RAM style = auto
-The -comp option is FALSE.
-The -syn option is FALSE.
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
--p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1 (searchpath added)
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
-Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
-NGD file = RAM2GS_LCMXO256C_impl1.ngd
--sdc option: SDC file input not used.
--lpf option: Output file option is ON.
-Hardtimer checking is enabled (default). The -dt option is not used.
-The -r option is OFF. [ Remove LOC Properties is OFF. ]
-Technology check ok...
-
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
-Compile design.
-Compile Design Begin
-Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
-Top module name (Verilog): RAM2GS
-INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Top-level module name = RAM2GS.
-INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 0000 -> 0000000000000001
-
- 0001 -> 0000000000000010
-
- 0010 -> 0000000000000100
-
- 0011 -> 0000000000001000
-
- 0100 -> 0000000000010000
-
- 0101 -> 0000000000100000
-
- 0110 -> 0000000001000000
-
- 0111 -> 0000000010000000
-
- 1000 -> 0000000100000000
-
- 1001 -> 0000001000000000
-
- 1010 -> 0000010000000000
-
- 1011 -> 0000100000000000
-
- 1100 -> 0001000000000000
-
- 1101 -> 0010000000000000
-
- 1110 -> 0100000000000000
-
- 1111 -> 1000000000000000
-
-INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 00 -> 0001
-
- 01 -> 0010
-
- 10 -> 0100
-
- 11 -> 1000
-
-
-
-
-GSR will not be inferred because no asynchronous signal was found in the netlist.
-WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
-Applying 200.000000 MHz constraint to all clocks
-
-WARNING - synthesis: No user .sdc file.
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
-
-################### Begin Area Report (RAM2GS)######################
-Number of register bits => 102 of 490 (20 % )
-BB => 8
-CCU2 => 9
-FD1P3AX => 28
-FD1P3AY => 3
-FD1P3IX => 2
-FD1P3JX => 1
-FD1S3AX => 47
-FD1S3AY => 1
-FD1S3IX => 16
-FD1S3JX => 4
-GSR => 1
-IB => 26
-INV => 3
-OB => 33
-ORCALUT4 => 116
-PFUMX => 3
-################### End Area Report ##################
-
-################### Begin BlackBox Report ######################
-TSALL => 1
-################### End BlackBox Report ##################
-
-################### Begin Clock Report ######################
-Clock Nets
-Number of Clocks: 4
-  Net : RCLK_c, loads : 62
-  Net : PHI2_c, loads : 11
-  Net : nCCAS_c, loads : 2
-  Net : nCRAS_c, loads : 2
-Clock Enable Nets
-Number of Clock Enables: 13
-Top 10 highest fanout Clock Enables:
-  Net : RCLK_c_enable_23, loads : 16
-  Net : RCLK_c_enable_4, loads : 3
-  Net : PHI2_N_114_enable_7, loads : 3
-  Net : RCLK_c_enable_24, loads : 2
-  Net : PHI2_N_114_enable_6, loads : 2
-  Net : RCLK_c_enable_7, loads : 1
-  Net : RCLK_c_enable_6, loads : 1
-  Net : RCLK_c_enable_3, loads : 1
-  Net : PHI2_N_114_enable_2, loads : 1
-  Net : PHI2_N_114_enable_1, loads : 1
-Highest fanout non-clock nets
-Top 10 highest fanout non-clock nets:
-  Net : InitReady, loads : 17
-  Net : RCLK_c_enable_23, loads : 16
-  Net : RASr2, loads : 15
-  Net : nCRAS_N_9, loads : 15
-  Net : nRowColSel_N_35, loads : 14
-  Net : nRowColSel, loads : 13
-  Net : Ready, loads : 13
-  Net : n2307, loads : 13
-  Net : nCCAS_N_3, loads : 10
-  Net : Din_c_6, loads : 9
-################### End Clock Report ##################
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |  200.000 MHz|   38.826 MHz|     7 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
-
-Peak Memory Usage: 50.406  MB
-
---------------------------------------------------------------
-Elapsed CPU time for LSE flow : 0.530  secs
---------------------------------------------------------------
diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/synthesis_lse.html b/CPLD-old/LCMXO/LCMXO256C/impl1/synthesis_lse.html
deleted file mode 100644
index 8faa0b2..0000000
--- a/CPLD-old/LCMXO/LCMXO256C/impl1/synthesis_lse.html
+++ /dev/null
@@ -1,304 +0,0 @@
-
-Synthesis and Ngdbuild Report
-
-
-
    Synthesis and Ngdbuild  Report
-synthesis:  version Diamond (64-bit) 3.12.0.240.2
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Mon Aug 16 21:32:25 2021
-
-
-Command Line:  synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml 
-
-Synthesis options:
-The -a option is MachXO.
-The -s option is 3.
-The -t option is TQFP100.
-The -d option is LCMXO256C.
-Using package TQFP100.
-Using performance grade 3.
-                                                          
-
-##########################################################
-
-### Lattice Family : MachXO
-
-### Device  : LCMXO256C
-
-### Package : TQFP100
-
-### Speed   : 3
-
-##########################################################
-
-                                                          
-
-INFO - synthesis: User-Selected Strategy Settings
-Optimization goal = Balanced
-Top-level module name = RAM2GS.
-Target frequency = 200.000000 MHz.
-Maximum fanout = 1000.
-Timing path count = 3
-BRAM utilization = 100.000000 %
-DSP usage = true
-DSP utilization = 100.000000 %
-fsm_encoding_style = auto
-resolve_mixed_drivers = 0
-fix_gated_clocks = 1
-
-Mux style = Auto
-Use Carry Chain = true
-carry_chain_length = 0
-Loop Limit = 1950.
-Use IO Insertion = TRUE
-Use IO Reg = AUTO
-
-Resource Sharing = TRUE
-Propagate Constants = TRUE
-Remove Duplicate Registers = TRUE
-force_gsr = auto
-ROM style = auto
-RAM style = auto
-The -comp option is FALSE.
-The -syn option is FALSE.
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
--p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1 (searchpath added)
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
-Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
-NGD file = RAM2GS_LCMXO256C_impl1.ngd
--sdc option: SDC file input not used.
--lpf option: Output file option is ON.
-Hardtimer checking is enabled (default). The -dt option is not used.
-The -r option is OFF. [ Remove LOC Properties is OFF. ]
-Technology check ok...
-
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
-Compile design.
-Compile Design Begin
-Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
-Top module name (Verilog): RAM2GS
-INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Top-level module name = RAM2GS.
-INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 0000 -> 0000000000000001
-
- 0001 -> 0000000000000010
-
- 0010 -> 0000000000000100
-
- 0011 -> 0000000000001000
-
- 0100 -> 0000000000010000
-
- 0101 -> 0000000000100000
-
- 0110 -> 0000000001000000
-
- 0111 -> 0000000010000000
-
- 1000 -> 0000000100000000
-
- 1001 -> 0000001000000000
-
- 1010 -> 0000010000000000
-
- 1011 -> 0000100000000000
-
- 1100 -> 0001000000000000
-
- 1101 -> 0010000000000000
-
- 1110 -> 0100000000000000
-
- 1111 -> 1000000000000000
-
-INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 00 -> 0001
-
- 01 -> 0010
-
- 10 -> 0100
-
- 11 -> 1000
-
-
-
-
-GSR will not be inferred because no asynchronous signal was found in the netlist.
-WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
-Applying 200.000000 MHz constraint to all clocks
-
-WARNING - synthesis: No user .sdc file.
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
-
-################### Begin Area Report (RAM2GS)######################
-Number of register bits => 102 of 490 (20 % )
-BB => 8
-CCU2 => 9
-FD1P3AX => 28
-FD1P3AY => 3
-FD1P3IX => 2
-FD1P3JX => 1
-FD1S3AX => 47
-FD1S3AY => 1
-FD1S3IX => 16
-FD1S3JX => 4
-GSR => 1
-IB => 26
-INV => 3
-OB => 33
-ORCALUT4 => 116
-PFUMX => 3
-################### End Area Report ##################
-
-################### Begin BlackBox Report ######################
-TSALL => 1
-################### End BlackBox Report ##################
-
-################### Begin Clock Report ######################
-Clock Nets
-Number of Clocks: 4
-  Net : RCLK_c, loads : 62
-  Net : PHI2_c, loads : 11
-  Net : nCCAS_c, loads : 2
-  Net : nCRAS_c, loads : 2
-Clock Enable Nets
-Number of Clock Enables: 13
-Top 10 highest fanout Clock Enables:
-  Net : RCLK_c_enable_23, loads : 16
-  Net : RCLK_c_enable_4, loads : 3
-  Net : PHI2_N_114_enable_7, loads : 3
-  Net : RCLK_c_enable_24, loads : 2
-  Net : PHI2_N_114_enable_6, loads : 2
-  Net : RCLK_c_enable_7, loads : 1
-  Net : RCLK_c_enable_6, loads : 1
-  Net : RCLK_c_enable_3, loads : 1
-  Net : PHI2_N_114_enable_2, loads : 1
-  Net : PHI2_N_114_enable_1, loads : 1
-Highest fanout non-clock nets
-Top 10 highest fanout non-clock nets:
-  Net : InitReady, loads : 17
-  Net : RCLK_c_enable_23, loads : 16
-  Net : RASr2, loads : 15
-  Net : nCRAS_N_9, loads : 15
-  Net : nRowColSel_N_35, loads : 14
-  Net : nRowColSel, loads : 13
-  Net : Ready, loads : 13
-  Net : n2307, loads : 13
-  Net : nCCAS_N_3, loads : 10
-  Net : Din_c_6, loads : 9
-################### End Clock Report ##################
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
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-clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
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diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/xxx_lse_cp_file_list b/CPLD-old/LCMXO/LCMXO256C/impl1/xxx_lse_cp_file_list
deleted file mode 100644
index 29f9161..0000000
--- a/CPLD-old/LCMXO/LCMXO256C/impl1/xxx_lse_cp_file_list
+++ /dev/null
@@ -1,252 +0,0 @@
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diff --git a/CPLD-old/LCMXO/LCMXO256C/impl1/xxx_lse_sign_file b/CPLD-old/LCMXO/LCMXO256C/impl1/xxx_lse_sign_file
deleted file mode 100644
index 47217b1..0000000
--- a/CPLD-old/LCMXO/LCMXO256C/impl1/xxx_lse_sign_file
+++ /dev/null
@@ -1,252 +0,0 @@
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diff --git a/CPLD-old/LCMXO/LCMXO640C/.setting.ini b/CPLD-old/LCMXO/LCMXO640C/.setting.ini
deleted file mode 100644
index c145fb8..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/.setting.ini
+++ /dev/null
@@ -1,4 +0,0 @@
-[General]
-Export.auto_tasks=IBIS, Bitgen
-Map.auto_tasks=MapEqu, MapTrace
-PAR.auto_tasks=PARTrace, IOTiming
diff --git a/CPLD-old/LCMXO/LCMXO640C/.spread_sheet.ini b/CPLD-old/LCMXO/LCMXO640C/.spread_sheet.ini
deleted file mode 100644
index 6c511f4..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/.spread_sheet.ini
+++ /dev/null
@@ -1,3 +0,0 @@
-[General]
-COLUMN_POS_INFO_NAME_-1_0=Prioritize
-COLUMN_POS_INFO_NAME_-1_1=PIO Register
diff --git a/CPLD-old/LCMXO/LCMXO640C/.spreadsheet_view.ini b/CPLD-old/LCMXO/LCMXO640C/.spreadsheet_view.ini
deleted file mode 100644
index 54adf6f..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/.spreadsheet_view.ini
+++ /dev/null
@@ -1,65 +0,0 @@
-[General]
-pin_sort_type=0
-pin_sort_ascending=true
-sig_sort_type=0
-sig_sort_ascending=true
-active_Sheet=Port Assignments
-
-[Port%20Assignments]
-Name="166,0"
-Group%20By="84,1"
-Pin="56,2"
-BANK="62,3"
-IO_TYPE="131,4"
-PULLMODE="92,5"
-DRIVE="67,6"
-SLEWRATE="92,7"
-OPENDRAIN="97,8"
-Outload%20%28pF%29="103,9"
-MaxSkew="87,10"
-Clock%20Load%20Only="121,11"
-sort_columns="Name,Ascending"
-
-[Pin%20Assignments]
-Pin="90,0"
-Pad%20Name="89,1"
-Dual%20Function="109,2"
-Polarity="77,3"
-BANK="0,4"
-IO_TYPE="131,5"
-Signal%20Name="113,6"
-Signal%20Type="115,7"
-sort_columns="Pin,Ascending"
-
-[Clock%20Resource]
-Clock%20Type="100,ELLIPSIS"
-Clock%20Name="100,ELLIPSIS"
-Selection="100,ELLIPSIS"
-
-[Global%20Preferences]
-Preference%20Name="222,ELLIPSIS"
-Preference%20Value="236,ELLIPSIS"
-
-[Cell%20Mapping]
-Type="100,ELLIPSIS"
-Name="100,ELLIPSIS"
-Din\Dout="100,ELLIPSIS"
-PIO%20Register="100,ELLIPSIS"
-
-[Route%20Priority]
-Type="100,ELLIPSIS"
-Name="100,ELLIPSIS"
-Prioritize="100,ELLIPSIS"
-
-[Timing%20Preferences]
-Preference%20Name="246,ELLIPSIS"
-Preference%20Value="104,ELLIPSIS"
-Preference%20Unit="98,ELLIPSIS"
-
-[Group]
-Group%20Type\Name="134,ELLIPSIS"
-Value="38,ELLIPSIS"
-
-[Misc%20Preferences]
-Preference%20Name="117,ELLIPSIS"
-Preference%20Value="104,ELLIPSIS"
diff --git a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ccl b/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ccl
deleted file mode 100644
index dcf391b..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ccl
+++ /dev/null
@@ -1 +0,0 @@
-VERSION=20110520
diff --git a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf b/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf
deleted file mode 100644
index c625cb6..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf
+++ /dev/null
@@ -1,14 +0,0 @@
-
-
-    
-    
-        
-        
-            
-        
-        
-            
-        
-    
-    
-
diff --git a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.lpf b/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.lpf
deleted file mode 100644
index 9fa278f..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.lpf
+++ /dev/null
@@ -1,226 +0,0 @@
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-LOCATE COMP "Dout[0]" SITE "1" ;
-LOCATE COMP "Dout[6]" SITE "2" ;
-LOCATE COMP "Dout[7]" SITE "3" ;
-LOCATE COMP "Dout[4]" SITE "4" ;
-LOCATE COMP "Dout[5]" SITE "5" ;
-LOCATE COMP "Dout[3]" SITE "6" ;
-LOCATE COMP "Dout[1]" SITE "7" ;
-LOCATE COMP "Dout[2]" SITE "8" ;
-LOCATE COMP "Din[2]" SITE "14" ;
-LOCATE COMP "Din[1]" SITE "15" ;
-LOCATE COMP "Din[3]" SITE "16" ;
-LOCATE COMP "Din[5]" SITE "17" ;
-LOCATE COMP "Din[4]" SITE "18" ;
-LOCATE COMP "Din[7]" SITE "19" ;
-LOCATE COMP "Din[6]" SITE "20" ;
-LOCATE COMP "Din[0]" SITE "21" ;
-LOCATE COMP "LED" SITE "57" ;
-LOCATE COMP "RA[0]" SITE "98" ;
-LOCATE COMP "RA[1]" SITE "89" ;
-LOCATE COMP "RA[2]" SITE "94" ;
-LOCATE COMP "RA[3]" SITE "97" ;
-LOCATE COMP "RA[4]" SITE "99" ;
-LOCATE COMP "RA[5]" SITE "95" ;
-LOCATE COMP "RA[6]" SITE "91" ;
-LOCATE COMP "RA[7]" SITE "100" ;
-LOCATE COMP "RA[8]" SITE "96" ;
-LOCATE COMP "RA[9]" SITE "85" ;
-LOCATE COMP "RA[10]" SITE "87" ;
-LOCATE COMP "RA[11]" SITE "79" ;
-LOCATE COMP "RBA[1]" SITE "83" ;
-LOCATE COMP "RBA[0]" SITE "63" ;
-LOCATE COMP "RCKE" SITE "82" ;
-LOCATE COMP "RDQMH" SITE "76" ;
-LOCATE COMP "RDQML" SITE "61" ;
-LOCATE COMP "UFMCLK" SITE "58" ;
-LOCATE COMP "UFMSDI" SITE "56" ;
-LOCATE COMP "nUFMCS" SITE "53" ;
-LOCATE COMP "nRCAS" SITE "78" ;
-LOCATE COMP "nRCS" SITE "77" ;
-LOCATE COMP "nRRAS" SITE "73" ;
-LOCATE COMP "nRWE" SITE "72" ;
-LOCATE COMP "RD[0]" SITE "64" ;
-LOCATE COMP "RD[1]" SITE "65" ;
-LOCATE COMP "RD[2]" SITE "66" ;
-LOCATE COMP "RD[3]" SITE "67" ;
-LOCATE COMP "RD[4]" SITE "68" ;
-LOCATE COMP "RD[5]" SITE "69" ;
-LOCATE COMP "RD[6]" SITE "70" ;
-LOCATE COMP "RD[7]" SITE "71" ;
-LOCATE COMP "PHI2" SITE "39" ;
-LOCATE COMP "RCLK" SITE "86" ;
-LOCATE COMP "nCCAS" SITE "27" ;
-LOCATE COMP "nCRAS" SITE "43" ;
-LOCATE COMP "CROW[0]" SITE "32" ;
-LOCATE COMP "CROW[1]" SITE "34" ;
-LOCATE COMP "UFMSDO" SITE "55" ;
-LOCATE COMP "nFWE" SITE "22" ;
-LOCATE COMP "MAin[0]" SITE "23" ;
-LOCATE COMP "MAin[1]" SITE "38" ;
-LOCATE COMP "MAin[2]" SITE "37" ;
-LOCATE COMP "MAin[3]" SITE "47" ;
-LOCATE COMP "MAin[4]" SITE "46" ;
-LOCATE COMP "MAin[5]" SITE "45" ;
-LOCATE COMP "MAin[6]" SITE "49" ;
-LOCATE COMP "MAin[7]" SITE "44" ;
-LOCATE COMP "MAin[8]" SITE "50" ;
-LOCATE COMP "MAin[9]" SITE "51" ;
-IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVTTL33 ;
-IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ;
-IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ;
-IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
-IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
-IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
-OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
-OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
-OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "LED" LOAD 25.000000 pF ;
-OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
-USE PRIMARY NET "PHI2_c" ;
-USE PRIMARY NET "RCLK_c" ;
-VOLTAGE 3.300 V;
-VCCIO_DERATE BANK 0 PERCENT -5; 
-VCCIO_DERATE PERCENT -5; 
-VCCIO_DERATE BANK 1 PERCENT -5; 
-PERIOD NET "PHI2_c" 350.000000 ns  ;
-PERIOD NET "nCCAS_c" 350.000000 ns  ;
-PERIOD NET "nCRAS_c" 350.000000 ns  ;
-PERIOD NET "RCLK_c" 16.000000 ns  ;
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-USE PRIMARY NET "nCCAS_c" ;
-USE PRIMARY NET "nCRAS_c" ;
diff --git a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C1.sty b/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C1.sty
deleted file mode 100644
index feec63c..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C1.sty
+++ /dev/null
@@ -1,205 +0,0 @@
-
-
-
-    
-    
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diff --git a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcl.html b/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcl.html
deleted file mode 100644
index c0aa950..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcl.html
+++ /dev/null
@@ -1,75 +0,0 @@
-
-Lattice TCL Log
-
-
-
    pn210816203903
-#Start recording tcl command: 8/16/2021 20:34:20
-#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
-prj_project new -name "RAM2GS_LCMXO640C" -impl "impl1" -dev LCMXO640C-3T100C -synthesis "lse"
-prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
-prj_project save
-prj_src add -exclude "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
-prj_run Export -impl impl1 -forceAll
-prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
-prj_run Export -impl impl1 -forceAll
-#Stop recording: 8/16/2021 20:39:03
-
-
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diff --git a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816203903.tcr b/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816203903.tcr
deleted file mode 100644
index aada37a..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816203903.tcr
+++ /dev/null
@@ -1,10 +0,0 @@
-#Start recording tcl command: 8/16/2021 20:34:20
-#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
-prj_project new -name "RAM2GS_LCMXO640C" -impl "impl1" -dev LCMXO640C-3T100C -synthesis "lse"
-prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
-prj_project save
-prj_src add -exclude "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
-prj_run Export -impl impl1 -forceAll
-prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
-prj_run Export -impl impl1 -forceAll
-#Stop recording: 8/16/2021 20:39:03
diff --git a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816214112.tcr b/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816214112.tcr
deleted file mode 100644
index 3c252b4..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn210816214112.tcr
+++ /dev/null
@@ -1,6 +0,0 @@
-#Start recording tcl command: 8/16/2021 21:33:25
-#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
-prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf"
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceOne
-#Stop recording: 8/16/2021 21:41:12
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/.build_status b/CPLD-old/LCMXO/LCMXO640C/impl1/.build_status
deleted file mode 100644
index 45432b8..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/.build_status
+++ /dev/null
@@ -1,46 +0,0 @@
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diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb b/CPLD-old/LCMXO/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb
deleted file mode 100644
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deleted file mode 100644
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z7tf5rwKoOiiUwTWtfSMYrh(Lhm67UJ=VDaiM07u#;w{WDG0$9{x>_`2_Vl*PMKe~`
zq~SY<+2PmDPH{XXsRm4ob8Q+`B~CZ`Hm|1i$Y{)W@tvcJI0c6Y*H+>Hhd4pQ*%fnU
zpLxU)N6hFs1(mTKA?3mho2^sdoJbPdaYr{Nid7BC+Y%Yr7`!o2X+&e=GTw2GW@9JB
zj5+z#-s4yHE?mBB<;lG`53kv@Z0$Re4eMwuaO<^cVPCk!lq
S>jO?xXeHip?: 1.302ns/0.000ns; real time: 5 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 523(84.63%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.256ns/0.000ns; real time: 5 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 511(82.69%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.228ns/0.000ns; real time: 5 secs 
-Level 4, iteration 1
-16(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 21:33:37 08/16/21
-Level 1, iteration 1
-0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 1
-5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 2
-2(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 3
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 21:33:37 08/16/21
-
-Start NBR section for re-routing at 21:33:37 08/16/21
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for post-routing at 21:33:37 08/16/21
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 1.213ns
-  Timing score : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-Total CPU time 6 secs 
-Total REAL time: 6 secs 
-Completely routed.
-End of route.  618 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 1.213
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.339
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 6 secs 
-Total REAL time to completion: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd
deleted file mode 100644
index 878d798..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd
+++ /dev/null
@@ -1,45 +0,0 @@
-[ActiveSupport PAR]
-; Global primary clocks
-GLOBAL_PRIMARY_USED = 4;
-; Global primary clock #0
-GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
-GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
-GLOBAL_PRIMARY_0_LOADNUM = 39;
-; Global primary clock #1
-GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
-GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
-GLOBAL_PRIMARY_1_LOADNUM = 13;
-; Global primary clock #2
-GLOBAL_PRIMARY_2_SIGNALNAME = nCCAS_c;
-GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
-GLOBAL_PRIMARY_2_LOADNUM = 4;
-; Global primary clock #3
-GLOBAL_PRIMARY_3_SIGNALNAME = nCRAS_c;
-GLOBAL_PRIMARY_3_DRIVERTYPE = PIO;
-GLOBAL_PRIMARY_3_LOADNUM = 7;
-; # of global secondary clocks
-GLOBAL_SECONDARY_USED = 0;
-; I/O Bank 0 Usage
-BANK_0_USED = 18;
-BANK_0_AVAIL = 18;
-BANK_0_VCCIO = 3.3V;
-BANK_0_VREF1 = NA;
-BANK_0_VREF2 = NA;
-; I/O Bank 1 Usage
-BANK_1_USED = 18;
-BANK_1_AVAIL = 21;
-BANK_1_VCCIO = 3.3V;
-BANK_1_VREF1 = NA;
-BANK_1_VREF2 = NA;
-; I/O Bank 2 Usage
-BANK_2_USED = 13;
-BANK_2_AVAIL = 14;
-BANK_2_VCCIO = NA;
-BANK_2_VREF1 = NA;
-BANK_2_VREF2 = NA;
-; I/O Bank 3 Usage
-BANK_3_USED = 18;
-BANK_3_AVAIL = 21;
-BANK_3_VCCIO = 3.3V;
-BANK_3_VREF1 = NA;
-BANK_3_VREF2 = NA;
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
deleted file mode 100644
index 8bf94bf..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
+++ /dev/null
@@ -1,28 +0,0 @@
-PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Mon Aug 16 21:33:31 2021
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
-RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
-RAM2GS_LCMXO640C_impl1.prf -gui -msgset
-C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
-
-
-Preference file: RAM2GS_LCMXO640C_impl1.prf.
-
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            1.213        0            0.339        0            06           Completed
-
-* : Design saved.
-
-Total (real) run time for 1-seed: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc
deleted file mode 100644
index ec074a2..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc
+++ /dev/null
@@ -1 +0,0 @@
-DRC detected 0 errors and 0 warnings.
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
deleted file mode 100644
index 149b5cf..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
+++ /dev/null
@@ -1,1745 +0,0 @@
-
-*
-NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12*
-NOTE Version:         Diamond (64-bit) 3.12.0.240.2*
-NOTE Readback:       Off*
-NOTE Security:      Off*
-NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
-NOTE All Rights Reserved *
-NOTE DATE CREATED: Mon Aug 16 21:36:33 2021 *
-NOTE DESIGN NAME: RAM2GS *
-NOTE DEVICE NAME: LCMXO640C-3TQFP100 *
-NOTE PIN ASSIGNMENTS *
-NOTE PINS RD[7] : 71 : inout *
-NOTE PINS RD[6] : 70 : inout *
-NOTE PINS RD[5] : 69 : inout *
-NOTE PINS RD[4] : 68 : inout *
-NOTE PINS RD[3] : 67 : inout *
-NOTE PINS RD[2] : 66 : inout *
-NOTE PINS RD[1] : 65 : inout *
-NOTE PINS RD[0] : 64 : inout *
-NOTE PINS Dout[7] : 3 : out *
-NOTE PINS Dout[6] : 2 : out *
-NOTE PINS Dout[5] : 5 : out *
-NOTE PINS Dout[4] : 4 : out *
-NOTE PINS Dout[3] : 6 : out *
-NOTE PINS Dout[2] : 8 : out *
-NOTE PINS Dout[1] : 7 : out *
-NOTE PINS Dout[0] : 1 : out *
-NOTE PINS LED : 57 : out *
-NOTE PINS RBA[1] : 83 : out *
-NOTE PINS RBA[0] : 63 : out *
-NOTE PINS RA[11] : 79 : out *
-NOTE PINS RA[10] : 87 : out *
-NOTE PINS RA[9] : 85 : out *
-NOTE PINS RA[8] : 96 : out *
-NOTE PINS RA[7] : 100 : out *
-NOTE PINS RA[6] : 91 : out *
-NOTE PINS RA[5] : 95 : out *
-NOTE PINS RA[4] : 99 : out *
-NOTE PINS RA[3] : 97 : out *
-NOTE PINS RA[2] : 94 : out *
-NOTE PINS RA[1] : 89 : out *
-NOTE PINS RA[0] : 98 : out *
-NOTE PINS nRCS : 77 : out *
-NOTE PINS RCKE : 82 : out *
-NOTE PINS nRWE : 72 : out *
-NOTE PINS nRRAS : 73 : out *
-NOTE PINS nRCAS : 78 : out *
-NOTE PINS RDQMH : 76 : out *
-NOTE PINS RDQML : 61 : out *
-NOTE PINS nUFMCS : 53 : out *
-NOTE PINS UFMCLK : 58 : out *
-NOTE PINS UFMSDI : 56 : out *
-NOTE PINS PHI2 : 39 : in *
-NOTE PINS MAin[9] : 51 : in *
-NOTE PINS MAin[8] : 50 : in *
-NOTE PINS MAin[7] : 44 : in *
-NOTE PINS MAin[6] : 49 : in *
-NOTE PINS MAin[5] : 45 : in *
-NOTE PINS MAin[4] : 46 : in *
-NOTE PINS MAin[3] : 47 : in *
-NOTE PINS MAin[2] : 37 : in *
-NOTE PINS MAin[1] : 38 : in *
-NOTE PINS MAin[0] : 23 : in *
-NOTE PINS CROW[1] : 34 : in *
-NOTE PINS CROW[0] : 32 : in *
-NOTE PINS Din[7] : 19 : in *
-NOTE PINS Din[6] : 20 : in *
-NOTE PINS Din[5] : 17 : in *
-NOTE PINS Din[4] : 18 : in *
-NOTE PINS Din[3] : 16 : in *
-NOTE PINS Din[2] : 14 : in *
-NOTE PINS Din[1] : 15 : in *
-NOTE PINS Din[0] : 21 : in *
-NOTE PINS nCCAS : 27 : in *
-NOTE PINS nCRAS : 43 : in *
-NOTE PINS nFWE : 22 : in *
-NOTE PINS RCLK : 86 : in *
-NOTE PINS UFMSDO : 55 : in *
-NOTE CONFIGURATION MODE: NONE *
-NOTE COMPRESSION: off *
-
-
-QF130036*
-G0*
-F0*
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-46DE
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log
deleted file mode 100644
index d0353b8..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log
+++ /dev/null
@@ -1,4 +0,0 @@
----- MParTrce Tool Log File ----
-
-==== Par Standard Out ====
-==== End of Par Standard Out ====
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf
deleted file mode 100644
index 2743d95..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf
+++ /dev/null
@@ -1,4 +0,0 @@
-#BLOCK ASYNCPATHS;
-#BLOCK RESETPATHS;
-
-#FREQUENCY 200.000000 MHz;
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata
deleted file mode 100644
index f0b54bc..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata
+++ /dev/null
@@ -1,5981 +0,0 @@
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diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
deleted file mode 100644
index 279152d..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
+++ /dev/null
@@ -1,402 +0,0 @@
-
-            Lattice Mapping Report File for Design Module 'RAM2GS'
-
-
-Design Information
-------------------
-
-Command line:   map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial
-     RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr
-     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf C:/Users/Dog
-     /Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.
-     lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_L
-     CMXO640C.lpf -c 0 -gui -msgset
-     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
-Target Vendor:  LATTICE
-Target Device:  LCMXO640CTQFP100
-Target Performance:   3
-Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.0.240.2
-Mapped on:  08/16/21  21:33:30
-
-Design Summary
---------------
-
-   Number of PFU registers:   102 out of   640 (16%)
-   Number of SLICEs:        65 out of   320 (20%)
-      SLICEs as Logic/ROM:     65 out of   320 (20%)
-      SLICEs as RAM:            0 out of   192 (0%)
-      SLICEs as Carry:          9 out of   320 (3%)
-   Number of LUT4s:        129 out of   640 (20%)
-      Number used as logic LUTs:        111
-      Number used as distributed RAM:     0
-      Number used as ripple logic:       18
-      Number used as shift registers:     0
-   Number of external PIOs: 67 out of 74 (91%)
-   Number of GSRs:  0 out of 1 (0%)
-   JTAG used :      No
-   Readback used :  No
-   Oscillator used :  No
-   Startup used :   No
-   Number of TSALL: 0 out of 1 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
-     distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and
-     ripple logic.
-   Number of clocks:  4
-     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
-     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
-     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
-     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
-   Number of Clock Enables:  13
-     Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
-     Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
-     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
-     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
-     Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
-     Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
-     Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
-     Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
-
-                                    Page 1
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/21  21:33:30
-
-Design Summary (cont)
----------------------
-     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
-     Net Ready_N_268: 1 loads, 1 LSLICEs
-   Number of LSRs:  9
-     Net RASr2: 1 loads, 1 LSLICEs
-     Net C1Submitted_N_225: 2 loads, 2 LSLICEs
-     Net n2299: 1 loads, 1 LSLICEs
-     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
-     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
-     Net LEDEN_N_88: 1 loads, 1 LSLICEs
-     Net n2291: 2 loads, 2 LSLICEs
-     Net Ready: 7 loads, 7 LSLICEs
-     Net nRWE_N_173: 1 loads, 1 LSLICEs
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net Ready: 19 loads
-     Net InitReady: 17 loads
-     Net RASr2: 16 loads
-     Net nRowColSel_N_35: 14 loads
-     Net nRowColSel: 13 loads
-     Net Din_c_6: 9 loads
-     Net MAin_c_1: 9 loads
-     Net Din_c_5: 8 loads
-     Net FS_11: 8 loads
-     Net MAin_c_0: 8 loads
-
-
-
-
-   Number of warnings:  0
-   Number of errors:    0
-     
-
-Design Errors/Warnings
-----------------------
-
-   No errors or warnings present.
-
-IO (PIO) Attributes
--------------------
-
-+---------------------+-----------+-----------+------------+------------+
-| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
-|                     |           |  IO_TYPE  | Register   |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[7]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[6]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[5]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[4]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[3]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[2]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-                                    Page 2
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/21  21:33:30
-
-IO (PIO) Attributes (cont)
---------------------------
-| RD[1]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[0]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[7]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[6]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[5]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[4]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[3]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[2]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[1]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[0]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| LED                 | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RBA[1]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RBA[0]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[11]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[10]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[9]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[8]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[7]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[6]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[5]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[4]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[3]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[2]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[1]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[0]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRCS                | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RCKE                | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRWE                | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-                                    Page 3
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/21  21:33:30
-
-IO (PIO) Attributes (cont)
---------------------------
-| nRRAS               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRCAS               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RDQMH               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RDQML               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nUFMCS              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMCLK              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMSDI              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| PHI2                | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[9]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[8]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[7]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[6]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[5]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[4]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[3]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[2]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[1]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[0]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| CROW[1]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| CROW[0]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[7]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[6]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[5]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[4]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[3]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[2]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[1]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[0]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-                                    Page 4
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/21  21:33:30
-
-IO (PIO) Attributes (cont)
---------------------------
-| nCCAS               | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nCRAS               | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nFWE                | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RCLK                | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMSDO              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-Removed logic
--------------
-
-Block i2 undriven or does not drive anything - clipped.
-Block GSR_INST undriven or does not drive anything - clipped.
-Signal PHI2_N_114 was merged into signal PHI2_c
-Signal nCRAS_N_9 was merged into signal nCRAS_c
-Signal nCCAS_N_3 was merged into signal nCCAS_c
-Signal n2302 was merged into signal nRowColSel_N_35
-Signal nRWE_N_172 was merged into signal nRWE_N_173
-Signal n2307 was merged into signal Ready
-Signal RASr2_N_63 was merged into signal RASr2
-Signal n1377 was merged into signal nRowColSel_N_34
-Signal n2306 was merged into signal nFWE_c
-Signal UFMSDO_N_74 was merged into signal UFMSDO_c
-Signal GND_net undriven or does not drive anything - clipped.
-Signal VCC_net undriven or does not drive anything - clipped.
-Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
-Block i1962 was optimized away.
-Block i1961 was optimized away.
-Block i1963 was optimized away.
-Block i1070_1_lut_rep_25 was optimized away.
-Block nRWE_I_49_1_lut was optimized away.
-Block i604_1_lut_rep_30 was optimized away.
-Block RASr2_I_0_1_lut was optimized away.
-Block i1069_1_lut was optimized away.
-Block i1_1_lut_rep_29 was optimized away.
-Block UFMSDO_I_0_1_lut was optimized away.
-Block i1 was optimized away.
-
-Run Time and Memory Usage
--------------------------
-
-   Total CPU Time: 0 secs  
-   Total REAL Time: 0 secs  
-   Peak Memory Usage: 30 MB
-
-                                    Page 5
-
-
-
-
-Design:  RAM2GS                                        Date:  08/16/21  21:33:30
-
-Run Time and Memory Usage (cont)
---------------------------------
-        
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
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-
-
-
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-
-
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-                                    Page 6
-
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-     Copyright (c) 1995 AT&T Corp.   All rights reserved.
-     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-     Copyright (c) 2001 Agere Systems   All rights reserved.
-     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
-     reserved.
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt
deleted file mode 100644
index 2d70ad1..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt
+++ /dev/null
@@ -1,9 +0,0 @@
--v
-1
-
-
--gt
-
-
--mapchkpnt 0
--sethld
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e
deleted file mode 100644
index c5da0e1..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e
+++ /dev/null
@@ -1,574 +0,0 @@
-
-comp 0: SLICE_0 (FSLICE)
-
-comp 1: SLICE_1 (FSLICE)
-
-comp 2: SLICE_2 (FSLICE)
-
-comp 3: SLICE_3 (FSLICE)
-
-comp 4: SLICE_4 (FSLICE)
-
-comp 5: SLICE_5 (FSLICE)
-
-comp 6: SLICE_6 (FSLICE)
-
-comp 7: SLICE_7 (FSLICE)
-
-comp 8: SLICE_8 (FSLICE)
-
-comp 9: SLICE_9 (FSLICE)
-n1361 = ((ADSubmitted*(~MAin_c_1+n2290))+ADSubmitted_N_234)
-ADSubmitted.D = n1361
-ADSubmitted.CLK = ~PHI2_c
-ADSubmitted.SP = VCC
-ADSubmitted.LSR = C1Submitted_N_225
-n2080 = (~MAin_c_0*(~ADSubmitted*n2122))
-
-comp 10: SLICE_14 (FSLICE)
-n2386 = GND
-C1Submitted.D = n2386
-C1Submitted.CLK = ~PHI2_c
-C1Submitted.SP = PHI2_N_114_enable_1
-C1Submitted.LSR = C1Submitted_N_225
-n2098 = (MAin_c_0*(~C1Submitted*(MAin_c_1*n2108)))
-
-comp 11: SLICE_18 (FSLICE)
-CmdEnable_N_236 = (ADSubmitted_N_234+C1Submitted_N_225)
-CmdEnable.D = CmdEnable_N_236
-CmdEnable.CLK = ~PHI2_c
-CmdEnable.SP = PHI2_N_114_enable_8
-CmdEnable.LSR = GND
-XOR8MEG_N_112 = (~n2290*(CmdEnable*(MAin_c_0*~MAin_c_1)))
-
-comp 12: SLICE_19 (FSLICE)
-n2387\000/BUF1 = VCC
-CmdSubmitted.D = n2387\000/BUF1
-CmdSubmitted.CLK = ~PHI2_c
-CmdSubmitted.SP = PHI2_N_114_enable_6
-CmdSubmitted.LSR = GND
-n2308 = (~PHI2r2*(CmdSubmitted*PHI2r3))
-
-comp 13: SLICE_23 (FSLICE)
-Cmdn8MEGEN_N_248 = (~n2296*(~Din_c_5*~Din_c_0+Din_c_5*n8MEGEN)+n2296*n8MEGEN)
-Cmdn8MEGEN.D = Cmdn8MEGEN_N_248
-Cmdn8MEGEN.CLK = ~PHI2_c
-Cmdn8MEGEN.SP = PHI2_N_114_enable_6
-Cmdn8MEGEN.LSR = GND
-n2296 = (~Din_c_4+(Din_c_6+Din_c_7))
-
-comp 14: SLICE_25 (FSLICE)
-n2387 = VCC
-InitReady.D = n2387
-InitReady.CLK = RCLK_c
-InitReady.SP = RCLK_c_enable_6
-InitReady.LSR = GND
-RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3)))
-
-comp 15: SLICE_31 (FSLICE)
-RA11_N_180 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG)
-RA_c.D = RA11_N_180
-RA_c.CLK = PHI2_c
-RA_c.SP = VCC
-RA_c.LSR = ~Ready
-n2385 = (Din_c_6+Din_c_7)
-
-comp 16: SLICE_33 (FSLICE)
-RCKEEN_N_115 = (~Ready*InitReady+Ready*RCKEEN_N_116)
-RCKEEN.D = RCKEEN_N_115
-RCKEEN.CLK = RCLK_c
-RCKEEN.SP = RCLK_c_enable_4
-RCKEEN.LSR = GND
-RCLK_c_enable_7 = (~n2119*(InitReady*n2308)+n2119*(~InitReady*~FS_5+InitReady*n2308))
-
-comp 17: SLICE_34 (FSLICE)
-RCKE_N_128 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN))
-RCKE_c.D = RCKE_N_128
-RCKE_c.CLK = RCLK_c
-RCKE_c.SP = VCC
-RCKE_c.LSR = GND
-nRWE_N_178 = (~RCKE_c+RASr2)
-CASr2.D = CASr
-CASr2.CLK = RCLK_c
-CASr2.SP = VCC
-CASr2.LSR = GND
-
-comp 18: SLICE_35 (FSLICE)
-n2387\001/BUF1 = VCC
-Ready.D = n2387\001/BUF1
-Ready.CLK = RCLK_c
-Ready.SP = Ready_N_268
-Ready.LSR = GND
-RCLK_c_enable_23 = (InitReady*(RASr2*(nRowColSel_N_35*~Ready)))
-
-comp 19: SLICE_42 (FSLICE)
-UFMCLK_N_212 = (~n2076*(~InitReady*FS_4+InitReady*CmdUFMCLK)+n2076*(InitReady*CmdUFMCLK))
-UFMCLK_c.D = UFMCLK_N_212
-UFMCLK_c.CLK = RCLK_c
-UFMCLK_c.SP = RCLK_c_enable_24
-UFMCLK_c.LSR = n2291
-RCLK_c_enable_6 = (n2076*FS_10)
-
-comp 20: SLICE_43 (FSLICE)
-UFMSDI_N_219 = (~InitReady*n1895+InitReady*CmdUFMSDI)
-UFMSDI_c.D = UFMSDI_N_219
-UFMSDI_c.CLK = RCLK_c
-UFMSDI_c.SP = RCLK_c_enable_24
-UFMSDI_c.LSR = n2291
-n1895 = (~FS_10*(n2103*(~n2293*FS_6)))
-
-comp 21: SLICE_55 (FSLICE)
-n2128 = (((n2297+n2301)+nRCAS_N_161)+Ready)
-n980.D = n2128
-n980.CLK = RCLK_c
-n980.SP = VCC
-n980.LSR = ~nRWE_N_173
-n2301 = (~InitReady+~RASr2)
-
-comp 22: SLICE_56 (FSLICE)
-n8MEGEN_N_94 = (~n4*(~FS_10*Cmdn8MEGEN+FS_10*~UFMSDO_c)+n4*Cmdn8MEGEN)
-n8MEGEN.D = n8MEGEN_N_94
-n8MEGEN.CLK = RCLK_c
-n8MEGEN.SP = RCLK_c_enable_7
-n8MEGEN.LSR = GND
-n4 = ((~FS_11+n2300)+InitReady)
-
-comp 23: SLICE_58 (FSLICE)
-nRCAS_N_157 = (~nRowColSel_N_35*(~n2117+~Ready)+nRowColSel_N_35*n2287)
-nRCAS_c.D = nRCAS_N_157
-nRCAS_c.CLK = RCLK_c
-nRCAS_c.SP = RCLK_c_enable_4
-nRCAS_c.LSR = GND
-n2287 = (~n2248*(~Ready*~RASr2+Ready*(~RASr2+~CBR))+n2248*(~Ready+(~RASr2+~CBR)))
-
-comp 24: SLICE_60 (FSLICE)
-nRCS_N_132 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~n2117*~nRowColSel_N_35))*Ready)+((~InitReady+nRCS_N_135+~RASr2+~nRowColSel_N_35)*~Ready)
-nRCS_c.D = nRCS_N_132
-nRCS_c.CLK = RCLK_c
-nRCS_c.SP = RCLK_c_enable_4
-nRCS_c.LSR = GND
-
-comp 25: SLICE_61 (FSLICE)
-n33 = (~Ready*(n2244+n2297)+Ready*(n2244+n18))
-nRRAS_c.D = n33
-nRRAS_c.CLK = RCLK_c
-nRRAS_c.SP = VCC
-nRRAS_c.LSR = GND
-n50 = ((nRowColSel_N_33+nRRAS_c)+nRowColSel_N_32)
-RASr.D = ~nCRAS_c
-RASr.CLK = RCLK_c
-RASr.SP = VCC
-RASr.LSR = GND
-
-comp 26: SLICE_62 (FSLICE)
-n1369 = (~n2308*nUFMCS_c+n2308*~CmdUFMCS)
-nRWE_N_173.D = n705
-nRWE_N_173.CLK = RCLK_c
-nRWE_N_173.SP = RCLK_c_enable_23
-nRWE_N_173.LSR = GND
-nRCS_N_135.D = Ready_N_272
-nRCS_N_135.CLK = RCLK_c
-nRCS_N_135.SP = RCLK_c_enable_23
-nRCS_N_135.LSR = GND
-
-comp 27: SLICE_63 (FSLICE)
-nRWE_N_167 = (~n2292*(~Ready*~n2164+Ready*nRWE_N_174)+n2292*(~Ready+nRWE_N_174))
-nRWE_c.D = nRWE_N_167
-nRWE_c.CLK = RCLK_c
-nRWE_c.SP = RCLK_c_enable_3
-nRWE_c.LSR = GND
-nRWE_N_174 = (~nRowColSel_N_35*(~n1+n1627)+nRowColSel_N_35*nRWE_N_178)
-
-comp 28: SLICE_64 (FSLICE)
-n1368 = (~nRowColSel_N_32*(nRowColSel+n1627)+nRowColSel_N_32*(~nRowColSel_N_28+n1627))
-nRowColSel.D = n1368
-nRowColSel.CLK = RCLK_c
-nRowColSel.SP = VCC
-nRowColSel.LSR = n2299
-RA_c_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4)
-
-comp 29: SLICE_65 (FSLICE)
-n1628 = (nRowColSel_N_32+nRowColSel_N_33)
-nRowColSel_N_32.D = n1628
-nRowColSel_N_32.CLK = RCLK_c
-nRowColSel_N_32.SP = VCC
-nRowColSel_N_32.LSR = ~RASr2
-RCLK_c_enable_4 = (((nRowColSel_N_32+n2299)+nRowColSel_N_34)+nRowColSel_N_33)
-
-comp 30: SLICE_66 (FSLICE)
-n1135 = (RASr2*~nRowColSel_N_32)
-nRowColSel_N_33.D = n1135
-nRowColSel_N_33.CLK = RCLK_c
-nRowColSel_N_33.SP = VCC
-nRowColSel_N_33.LSR = ~nRowColSel_N_34
-n2117 = (~nRowColSel_N_33*(n1*~nRowColSel_N_34)+nRowColSel_N_33*(~n2304*~nRowColSel_N_34))
-
-comp 31: SLICE_67 (FSLICE)
-LED_N_90 = (~LEDEN+nCRAS_c)
-nRowColSel_N_34.D = n1135
-nRowColSel_N_34.CLK = RCLK_c
-nRowColSel_N_34.SP = VCC
-nRowColSel_N_34.LSR = ~nRowColSel_N_35
-n2154 = (MAin_c_4*Bank_7)
-
-comp 32: SLICE_68 (FSLICE)
-n2168 = (FS_3*(FS_2*(FS_0*FS_1)))
-nRowColSel_N_35.D = ~RASr2
-nRowColSel_N_35.CLK = RCLK_c
-nRowColSel_N_35.SP = VCC
-nRowColSel_N_35.LSR = GND
-n962 = (nCCAS_c+nFWE_c)
-CASr3.D = CASr2
-CASr3.CLK = RCLK_c
-CASr3.SP = VCC
-CASr3.LSR = GND
-
-comp 33: SLICE_69 (FSLICE)
-n1348 = (~InitReady*n2076+InitReady*n1369)
-nUFMCS_c.D = n1348
-nUFMCS_c.CLK = RCLK_c
-nUFMCS_c.SP = VCC
-nUFMCS_c.LSR = LEDEN_N_88
-n2076 = (FS_17*(FS_11*(n12_adj_2*FS_15)))
-
-comp 34: i1912/SLICE_70 (FSLICE)
-n2244 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~nRowColSel_N_35*n50))*Ready)+(((~nRowColSel_N_35*n50)+~InitReady+~RASr2)*~Ready)
-
-comp 35: RCKEEN_I_0_419/SLICE_71 (FSLICE)
-RCKEEN_N_116 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11_adj_3*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35)
-
-comp 36: SLICE_72 (FSLICE)
-PHI2_N_114_enable_7 = (Din_c_5*(~n2296*(n2298*XOR8MEG_N_112)))
-n702.D = n703
-n702.CLK = RCLK_c
-n702.SP = RCLK_c_enable_23
-n702.LSR = GND
-n2298 = (((Din_c_6+Din_c_7)+Din_c_5)+Din_c_4)
-n701.D = n702
-n701.CLK = RCLK_c
-n701.SP = RCLK_c_enable_23
-n701.LSR = GND
-
-comp 37: SLICE_73 (FSLICE)
-n11 = (~n2168+((~FS_11+n2300)+FS_6))
-n706.D = n707
-n706.CLK = RCLK_c
-n706.SP = RCLK_c_enable_23
-n706.LSR = GND
-n2300 = ((FS_16+n10)+FS_17)
-n705.D = n706
-n705.CLK = RCLK_c
-n705.SP = RCLK_c_enable_23
-n705.LSR = GND
-
-comp 38: SLICE_74 (FSLICE)
-C1Submitted_N_225 = (~n2131*(~Din_c_2*(n2295*n2122)))
-n710.D = n711
-n710.CLK = RCLK_c
-n710.SP = RCLK_c_enable_23
-n710.LSR = GND
-n2295 = (n2114*~nFWE_c)
-n709.D = n710
-n709.CLK = RCLK_c
-n709.SP = RCLK_c_enable_23
-n709.LSR = GND
-
-comp 39: SLICE_75 (FSLICE)
-n2119 = (~n12*(~n11*(FS_10*n2294)))
-n708.D = n709
-n708.CLK = RCLK_c
-n708.SP = RCLK_c_enable_23
-n708.LSR = GND
-RCLK_c_enable_25 = (n2119*(FS_5*~InitReady))
-n707.D = n708
-n707.CLK = RCLK_c
-n707.SP = RCLK_c_enable_23
-n707.LSR = GND
-
-comp 40: SLICE_76 (FSLICE)
-n2131 = ((~MAin_c_1+n1285)+MAin_c_0)
-WRD_0.D = Din_c_0
-WRD_0.CLK = ~nCCAS_c
-WRD_0.SP = VCC
-WRD_0.LSR = GND
-n1285 = (~MAin_c_5+(~n2170+(~Bank_3+n26)))
-WRD_1.D = Din_c_1
-WRD_1.CLK = ~nCCAS_c
-WRD_1.SP = VCC
-WRD_1.LSR = GND
-
-comp 41: SLICE_77 (FSLICE)
-PHI2_N_114_enable_8 = (~MAin_c_1*(~n2286*(~n2290*MAin_c_0))+MAin_c_1*(~n2286*~n2290))
-RowA_2.D = MAin_c_2
-RowA_2.CLK = ~nCRAS_c
-RowA_2.SP = VCC
-RowA_2.LSR = ~Ready
-n2286 = (n2114*(~Din_c_2*n2080+Din_c_2*n2098))
-RowA_3.D = MAin_c_3
-RowA_3.CLK = ~nCRAS_c
-RowA_3.SP = VCC
-RowA_3.LSR = ~Ready
-
-comp 42: SLICE_78 (FSLICE)
-n10 = (((FS_14+FS_13)+FS_12)+FS_15)
-CASr.D = ~nCCAS_c
-CASr.CLK = RCLK_c
-CASr.SP = VCC
-CASr.LSR = GND
-n2294 = (((FS_16+n10)+FS_17)+FS_11)
-PHI2r2.D = PHI2r
-PHI2r2.CLK = RCLK_c
-PHI2r2.SP = VCC
-PHI2r2.LSR = GND
-
-comp 43: SLICE_79 (FSLICE)
-n1627 = (nRowColSel_N_34+nRowColSel_N_33)
-WRD_2.D = Din_c_2
-WRD_2.CLK = ~nCCAS_c
-WRD_2.SP = VCC
-WRD_2.LSR = GND
-RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1627)+nRowColSel_N_35)
-WRD_3.D = Din_c_3
-WRD_3.CLK = ~nCCAS_c
-WRD_3.SP = VCC
-WRD_3.LSR = GND
-
-comp 44: SLICE_80 (FSLICE)
-ADSubmitted_N_234 = (~n2289*(n4_adj_1*(MAin_c_0*n2108)))
-WRD_6.D = Din_c_6
-WRD_6.CLK = ~nCCAS_c
-WRD_6.SP = VCC
-WRD_6.LSR = GND
-n2289 = (~MAin_c_1+n1285)
-WRD_7.D = Din_c_7
-WRD_7.CLK = ~nCCAS_c
-WRD_7.SP = VCC
-WRD_7.LSR = GND
-
-comp 45: SLICE_81 (FSLICE)
-n4_adj_1 = (n2114*(Din_c_2*~nFWE_c))
-RowA_8.D = MAin_c_8
-RowA_8.CLK = ~nCRAS_c
-RowA_8.SP = VCC
-RowA_8.LSR = ~Ready
-n2114 = (Din_c_7*(~Din_c_4*(~Din_c_1*Din_c_0)))
-RowA_9.D = MAin_c_9
-RowA_9.CLK = ~nCRAS_c
-RowA_9.SP = VCC
-RowA_9.LSR = ~Ready
-
-comp 46: SLICE_82 (FSLICE)
-n2166 = (Bank_6*(MAin_c_2*(Bank_5*Bank_0)))
-RowA_0.D = MAin_c_0
-RowA_0.CLK = ~nCRAS_c
-RowA_0.SP = VCC
-RowA_0.LSR = ~Ready
-n26 = (~MAin_c_6+(~n2154+(~n2166+Bank_2)))
-RowA_1.D = MAin_c_1
-RowA_1.CLK = ~nCRAS_c
-RowA_1.SP = VCC
-RowA_1.LSR = ~Ready
-
-comp 47: SLICE_83 (FSLICE)
-n2245 = (InitReady*(Ready_N_272*(~RASr2*nRowColSel_N_32)))
-CmdUFMCLK.D = Din_c_1
-CmdUFMCLK.CLK = ~PHI2_c
-CmdUFMCLK.SP = PHI2_N_114_enable_7
-CmdUFMCLK.LSR = GND
-Ready_N_268 = (n2245+Ready)
-CmdUFMCS.D = Din_c_2
-CmdUFMCS.CLK = ~PHI2_c
-CmdUFMCS.SP = PHI2_N_114_enable_7
-CmdUFMCS.LSR = GND
-
-comp 48: SLICE_84 (FSLICE)
-nRowColSel_N_28 = ((~FWEr+CASr3)+CBR)
-nRCAS_N_161.D = nRCS_N_135
-nRCAS_N_161.CLK = RCLK_c
-nRCAS_N_161.SP = RCLK_c_enable_23
-nRCAS_N_161.LSR = GND
-n1 = (~CASr3*(CASr2*(FWEr*~CBR)))
-n703.D = nRWE_N_173
-n703.CLK = RCLK_c
-n703.SP = RCLK_c_enable_23
-n703.LSR = GND
-
-comp 49: SLICE_85 (FSLICE)
-n12 = (((~FS_4+FS_9)+FS_8)+FS_7)
-PHI2r3.D = PHI2r2
-PHI2r3.CLK = RCLK_c
-PHI2r3.SP = VCC
-PHI2r3.LSR = GND
-n2103 = (~FS_9*(FS_7*~FS_8)+FS_9*(FS_5*(~FS_7*~FS_8)))
-PHI2r.D = PHI2_c
-PHI2r.CLK = RCLK_c
-PHI2r.SP = VCC
-PHI2r.LSR = GND
-
-comp 50: SLICE_86 (FSLICE)
-n2291 = (~InitReady*(~n2300*~FS_11))
-RowA_6.D = MAin_c_6
-RowA_6.CLK = ~nCRAS_c
-RowA_6.SP = VCC
-RowA_6.LSR = ~Ready
-LEDEN_N_88 = (~InitReady*(~FS_10*(~n2300*~FS_11)))
-RowA_7.D = MAin_c_7
-RowA_7.CLK = ~nCRAS_c
-RowA_7.SP = VCC
-RowA_7.LSR = ~Ready
-
-comp 51: SLICE_87 (FSLICE)
-n2122 = (~Din_c_5*(Din_c_6*~Din_c_3))
-Ready_N_272.D = n699
-Ready_N_272.CLK = RCLK_c
-Ready_N_272.SP = RCLK_c_enable_23
-Ready_N_272.LSR = GND
-n2108 = (Din_c_3*(Din_c_5*~Din_c_6))
-n711.D = nRCAS_N_161
-n711.CLK = RCLK_c
-n711.SP = RCLK_c_enable_23
-n711.LSR = GND
-
-comp 52: SLICE_88 (FSLICE)
-RDQMH_c = (~nRowColSel+MAin_c_9)
-CmdUFMSDI.D = Din_c_0
-CmdUFMSDI.CLK = ~PHI2_c
-CmdUFMSDI.SP = PHI2_N_114_enable_7
-CmdUFMSDI.LSR = GND
-RA_c_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9)
-
-comp 53: SLICE_89 (FSLICE)
-n2290 = (nFWE_c+n1285)
-LEDEN.D = ~UFMSDO_c
-LEDEN.CLK = RCLK_c
-LEDEN.SP = RCLK_c_enable_25
-LEDEN.LSR = GND
-PHI2_N_114_enable_1 = (MAin_c_1*(~n1285*~nFWE_c))
-
-comp 54: SLICE_90 (FSLICE)
-PHI2_N_114_enable_6 = (Din_c_4*(XOR8MEG_N_112*(~Din_c_7*~Din_c_6)))
-n700.D = n701
-n700.CLK = RCLK_c
-n700.SP = RCLK_c_enable_23
-n700.LSR = GND
-PHI2_N_114_enable_2 = (XOR8MEG_N_112*(~Din_c_5*(~Din_c_4*~n2385)))
-n699.D = n700
-n699.CLK = RCLK_c
-n699.SP = RCLK_c_enable_23
-n699.LSR = GND
-
-comp 55: SLICE_91 (FSLICE)
-n2248 = (~InitReady+(nRCAS_N_161+nRCS_N_135))
-CBR.D = ~nCCAS_c
-CBR.CLK = ~nCRAS_c
-CBR.SP = VCC
-CBR.LSR = GND
-n2292 = (~RASr2+(~InitReady+(~nRowColSel_N_35+nRCS_N_135)))
-FWEr.D = ~nFWE_c
-FWEr.CLK = ~nCRAS_c
-FWEr.SP = VCC
-FWEr.LSR = GND
-
-comp 56: SLICE_92 (FSLICE)
-RDQML_c = (~nRowColSel+~MAin_c_9)
-RowA_4.D = MAin_c_4
-RowA_4.CLK = ~nCRAS_c
-RowA_4.SP = VCC
-RowA_4.LSR = ~Ready
-RA_c_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0)
-RowA_5.D = MAin_c_5
-RowA_5.CLK = ~nCRAS_c
-RowA_5.SP = VCC
-RowA_5.LSR = ~Ready
-
-comp 57: SLICE_93 (FSLICE)
-n12_adj_2 = (FS_12*(FS_13*(FS_16*FS_14)))
-RASr2.D = RASr
-RASr2.CLK = RCLK_c
-RASr2.SP = VCC
-RASr2.LSR = GND
-n2293 = (~FS_11+((FS_16+n10)+FS_17))
-RASr3.D = RASr2
-RASr3.CLK = RCLK_c
-RASr3.SP = VCC
-RASr3.LSR = GND
-
-comp 58: SLICE_94 (FSLICE)
-RA_c_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1)
-Bank_0.D = Din_c_0
-Bank_0.CLK = PHI2_c
-Bank_0.SP = VCC
-Bank_0.LSR = GND
-RA_c_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3)
-Bank_1.D = Din_c_1
-Bank_1.CLK = PHI2_c
-Bank_1.SP = VCC
-Bank_1.LSR = GND
-
-comp 59: SLICE_95 (FSLICE)
-RA_c_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8)
-Bank_6.D = Din_c_6
-Bank_6.CLK = PHI2_c
-Bank_6.SP = VCC
-Bank_6.LSR = GND
-RA_c_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2)
-Bank_7.D = Din_c_7
-Bank_7.CLK = PHI2_c
-Bank_7.SP = VCC
-Bank_7.LSR = GND
-
-comp 60: SLICE_96 (FSLICE)
-n2299 = (~Ready+nRowColSel_N_35)
-XOR8MEG.D = Din_c_0
-XOR8MEG.CLK = ~PHI2_c
-XOR8MEG.SP = PHI2_N_114_enable_2
-XOR8MEG.LSR = GND
-n2297 = (~nRowColSel_N_35+nRCS_N_135)
-
-comp 61: SLICE_97 (FSLICE)
-RA_c_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7)
-Bank_4.D = Din_c_4
-Bank_4.CLK = PHI2_c
-Bank_4.SP = VCC
-Bank_4.LSR = GND
-n2170 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7)))
-Bank_5.D = Din_c_5
-Bank_5.CLK = PHI2_c
-Bank_5.SP = VCC
-Bank_5.LSR = GND
-
-comp 62: SLICE_98 (FSLICE)
-RA_c_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6)
-Bank_2.D = Din_c_2
-Bank_2.CLK = PHI2_c
-Bank_2.SP = VCC
-Bank_2.LSR = GND
-RA_c_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5)
-Bank_3.D = Din_c_3
-Bank_3.CLK = PHI2_c
-Bank_3.SP = VCC
-Bank_3.LSR = GND
-
-comp 63: SLICE_99 (FSLICE)
-n2164 = (nRCAS_N_161+nRWE_N_173)
-RBA_c_0.D = CROW_c_0
-RBA_c_0.CLK = ~nCRAS_c
-RBA_c_0.SP = VCC
-RBA_c_0.LSR = ~Ready
-n18 = (nRowColSel_N_34*~nRowColSel_N_35)
-RBA_c_1.D = CROW_c_1
-RBA_c_1.CLK = ~nCRAS_c
-RBA_c_1.SP = VCC
-RBA_c_1.LSR = ~Ready
-
-comp 64: SLICE_100 (FSLICE)
-n11_adj_3 = (~CASr2+nRowColSel_N_33)
-WRD_4.D = Din_c_4
-WRD_4.CLK = ~nCCAS_c
-WRD_4.SP = VCC
-WRD_4.LSR = GND
-n2304 = (FWEr+CBR)
-WRD_5.D = Din_c_5
-WRD_5.CLK = ~nCCAS_c
-WRD_5.SP = VCC
-WRD_5.LSR = GND
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd
deleted file mode 100644
index fa3d1271d2b8a91aaa5c3455186366cb54bf9687..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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zW?WJGkdNUD7UlU$Y6%qOV~a#%F-|_FE(Ni&lp6oAV~h9@u~g4qSBtNumO)VvSJcjv
zB`{7pbrsgB<~~!@TEFlH%qK!
zsjT0gC*%qSwV3F;4Cgy+oJPjnud<6IZk~#|!vU9j})sR&Ii#
zFs|qV(O54E#LCUoxZaH`TI}*Me5rOi$PgDj4L`TTe~O_MYlmwKCWoKQ>&=AA&M%gag!Zaw7{-ilo3U@Ls1Y{KSC_xcEM1Hguc$6VF?XTS{!>zC7T|ITwq18xM^
z((s($7S{pXn6N{94Y%yR=v}}~0B1BjaqSuWwX;Fk!J&pn=LXLQ+!U~@;W4A8oej7d
z;Dm-}UD69~-bpkktgolx=_?1@fLjpOQyZO{b7%9dfLjuFpf)-+_r|(U0B!}?R83Od
zA33)YaBISPmF!$mf8PKz-<9L8lLfly&CX-gmo)u
zxJjKEmjG@DIID27&WeS70JjHhXn6d*PJH+2Kv>tDhBFP%-2=EIVV!i#$tN8F@5Coe
z!c5(A{OA2{1KbI)W|Qg_7~lg4>!?|#nyx&3I^fQLEtMp7^zO4;
z0PaFq2VcWOuIRBCa96+?4WHcMs4~Z3Aj69`|7!8Y&nPm?g3cOeN?X{
zj{!aqu%3J3JA;M;?nzi1J$K!w7V*u{3$UKs={j*1;DZQjt>-?%>XirF8?cs}b{e&K
z5a2$9wF=e4q30}_^(J5ou&d#-+KlDLPG7(Y4KMiY)FR-632W(T__S4nz5sj(VNLYj
zqplkAAmDz0^(Jk<95W7Zf5I-*M<4yknH&!w>_q)hE*diZJHP`8J4qXzoPOin4S)v`
zHbYC2T7E?fzC#QqY^&a+<;ps30S_VUHDBdUjTzEoDBz)lU7+KZ!zc1Px`z?A$ks+r
zs=KH^;6n*J%h2$MdDG#Yz{GIE=ITvO7&7#Fz#|Bom(xbKT-$zMz&11~X!zK6&3(X!
z5jHI*PD4LL^2Lwp`YZ
zA#8;y;8^$+L$aeGbw;pb2y+6VjwS3gSEzA>O)dyE9;RQ2M24{0c_EJ@Y-UEN;|V*(
z5^4frr{{#4NZ2I#-4h^7DA**ZwS_tn+#I1M6LxA=s40Ym8xaBkYB&P>Trjb3&a@*g9XR#e_W{3UvV}
zAreand(IScDPe1Ep_UQ$tRvKN!q#MkT0z(|IiW5jY_%^`mawNop)LX?MB-w?o-&2}
z2VqazLR~`G6OK@q683mjsFj30mJ{kS!XEX7x}30lDAYee36Z#hu>Y7sUP;&^woq3Q
z_OK(=)r38i73vzo{+$!*TEZUmh4Kh{AQb94P(mcGC+vPx$QuZ|&lc)N!tQm1x{0uV
zWrez#uzPYsRS@G*BI|#coE7YBY-H{XO
zF2Zj2g~}0D84ATf36WSu*lnhecN2E2Ez~`P-Qo!KFTyIaLfuQ)%{ig&BkU$$sQU@K
zF%;?nP(magBOmFfY`bgoU0^ZxQy9E7aSB?am1G4q+c#LcL4a
zCx%elK^260kFZYzp>`1VSzf633ESfdwUe;VU7`AYOJ!4gbA|eputG+t&j|b85^4`&KNv!N4yqv37li#72=ygl
zKjnq`im;zOp}r>U7gwln2>WkFsBa1T)e`DE!v1FnRRC2G>U+X|3xxWCuwq`Q9|^1S
zg!+lF-(8`8ChU)lP`?oNrzO;X$*P1Q)UTilLj8}dN(MsxMpmWrLKVp>;t5qnR#8`|
z-^r?dGD7`9R@JeD`jf0m8(bw5pbA1I$*Q`6P${yiUS23dR@L`}qGVMASEzl+s)iY%
z>X229ETPh5#4baqx@5!$lGP(4cFJ+}$%yw|@!bYw#12oWhGfKhd7&DCvW03)M!ahX
z)r5?ACnuBv$`Yz68S%C+R5LQ-P1&V6C{wT&WW+YvuO%4~6a;HUM!YU-Tc`HOV8KFiIuZ}O&
z5yVU9ggTOVb+bYpMZ9{BP@{=g-xg{N@fw&yjU`?~E)vP3L4`scL%c@5P{$IlaZadl
z#A}ijYCQ1_N2m<(n%Y7gN4#dHP{$LmITwlK1W=(+6N%Tt7wQD!waf`MiFmEDLY+vw
z){anDeO9PbiPymq${}7y
zTd0?5gFkaz!SDWRXymyfj3zFWY86dnJNq
S: 1.302ns/0.000ns; real time: 5 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 523(84.63%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.256ns/0.000ns; real time: 5 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 511(82.69%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.228ns/0.000ns; real time: 5 secs 
-Level 4, iteration 1
-16(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 21:33:37 08/16/21
-Level 1, iteration 1
-0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 1
-5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 2
-2(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 3
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 21:33:37 08/16/21
-
-Start NBR section for re-routing at 21:33:37 08/16/21
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack: 1.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for post-routing at 21:33:37 08/16/21
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack : 1.213ns
-  Timing score : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-Total CPU time 6 secs 
-Total REAL time: 6 secs 
-Completely routed.
-End of route.  618 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack> = 1.213
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Worst  slack> = 0.339
-PAR_SUMMARY::Timing score> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 6 secs 
-Total REAL time to completion: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
deleted file mode 100644
index 8dceb1f..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
+++ /dev/null
@@ -1,165 +0,0 @@
-SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:33:30 2021
-
-SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
-LOCATE COMP "RD[7]" SITE "71" ;
-LOCATE COMP "RD[6]" SITE "70" ;
-LOCATE COMP "RD[5]" SITE "69" ;
-LOCATE COMP "RD[4]" SITE "68" ;
-LOCATE COMP "RD[3]" SITE "67" ;
-LOCATE COMP "RD[2]" SITE "66" ;
-LOCATE COMP "RD[1]" SITE "65" ;
-LOCATE COMP "RD[0]" SITE "64" ;
-LOCATE COMP "Dout[7]" SITE "3" ;
-LOCATE COMP "Dout[6]" SITE "2" ;
-LOCATE COMP "Dout[5]" SITE "5" ;
-LOCATE COMP "Dout[4]" SITE "4" ;
-LOCATE COMP "Dout[3]" SITE "6" ;
-LOCATE COMP "Dout[2]" SITE "8" ;
-LOCATE COMP "Dout[1]" SITE "7" ;
-LOCATE COMP "Dout[0]" SITE "1" ;
-LOCATE COMP "LED" SITE "57" ;
-LOCATE COMP "RBA[1]" SITE "83" ;
-LOCATE COMP "RBA[0]" SITE "63" ;
-LOCATE COMP "RA[11]" SITE "79" ;
-LOCATE COMP "RA[10]" SITE "87" ;
-LOCATE COMP "RA[9]" SITE "85" ;
-LOCATE COMP "RA[8]" SITE "96" ;
-LOCATE COMP "RA[7]" SITE "100" ;
-LOCATE COMP "RA[6]" SITE "91" ;
-LOCATE COMP "RA[5]" SITE "95" ;
-LOCATE COMP "RA[4]" SITE "99" ;
-LOCATE COMP "RA[3]" SITE "97" ;
-LOCATE COMP "RA[2]" SITE "94" ;
-LOCATE COMP "RA[1]" SITE "89" ;
-LOCATE COMP "RA[0]" SITE "98" ;
-LOCATE COMP "nRCS" SITE "77" ;
-LOCATE COMP "RCKE" SITE "82" ;
-LOCATE COMP "nRWE" SITE "72" ;
-LOCATE COMP "nRRAS" SITE "73" ;
-LOCATE COMP "nRCAS" SITE "78" ;
-LOCATE COMP "RDQMH" SITE "76" ;
-LOCATE COMP "RDQML" SITE "61" ;
-LOCATE COMP "nUFMCS" SITE "53" ;
-LOCATE COMP "UFMCLK" SITE "58" ;
-LOCATE COMP "UFMSDI" SITE "56" ;
-LOCATE COMP "PHI2" SITE "39" ;
-LOCATE COMP "MAin[9]" SITE "51" ;
-LOCATE COMP "MAin[8]" SITE "50" ;
-LOCATE COMP "MAin[7]" SITE "44" ;
-LOCATE COMP "MAin[6]" SITE "49" ;
-LOCATE COMP "MAin[5]" SITE "45" ;
-LOCATE COMP "MAin[4]" SITE "46" ;
-LOCATE COMP "MAin[3]" SITE "47" ;
-LOCATE COMP "MAin[2]" SITE "37" ;
-LOCATE COMP "MAin[1]" SITE "38" ;
-LOCATE COMP "MAin[0]" SITE "23" ;
-LOCATE COMP "CROW[1]" SITE "34" ;
-LOCATE COMP "CROW[0]" SITE "32" ;
-LOCATE COMP "Din[7]" SITE "19" ;
-LOCATE COMP "Din[6]" SITE "20" ;
-LOCATE COMP "Din[5]" SITE "17" ;
-LOCATE COMP "Din[4]" SITE "18" ;
-LOCATE COMP "Din[3]" SITE "16" ;
-LOCATE COMP "Din[2]" SITE "14" ;
-LOCATE COMP "Din[1]" SITE "15" ;
-LOCATE COMP "Din[0]" SITE "21" ;
-LOCATE COMP "nCCAS" SITE "27" ;
-LOCATE COMP "nCRAS" SITE "43" ;
-LOCATE COMP "nFWE" SITE "22" ;
-LOCATE COMP "RCLK" SITE "86" ;
-LOCATE COMP "UFMSDO" SITE "55" ;
-PERIOD NET "PHI2_c" 350.000000 ns  ;
-USE PRIMARY NET "RCLK_c" ;
-PERIOD NET "nCCAS_c" 350.000000 ns  ;
-USE PRIMARY NET "PHI2_c" ;
-PERIOD NET "nCRAS_c" 350.000000 ns  ;
-USE PRIMARY NET "nCCAS_c" ;
-PERIOD NET "RCLK_c" 16.000000 ns  ;
-USE PRIMARY NET "nCRAS_c" ;
-SCHEMATIC END ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
-OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
-OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "LED" LOAD 25.000000 pF ;
-OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
-VOLTAGE 3.300 V;
-VCCIO_DERATE BANK 0 PERCENT -5; 
-VCCIO_DERATE PERCENT -5; 
-VCCIO_DERATE BANK 1 PERCENT -5; 
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-COMMERCIAL ;
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt
deleted file mode 100644
index 916dbc3..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt
+++ /dev/null
@@ -1,10 +0,0 @@
--v
-10
-
-
-
-
--gt
--sethld
--sp 3
--sphld m
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b
deleted file mode 100644
index aa05f83..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b
+++ /dev/null
@@ -1,2 +0,0 @@
-
--g ES:No
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
deleted file mode 100644
index 21ca4c4..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
+++ /dev/null
@@ -1,2507 +0,0 @@
-
-Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:33:31 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1_map.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,3
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:              12.873ns  (21.6% logic, 78.4% route), 7 logic levels.
-
- Constraint Details:
-
-     12.873ns physical path delay SLICE_95 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_95.CLK to    SLICE_95.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1   e 1.441    SLICE_95.Q1 to    SLICE_67.A1 Bank_7
-CTOF_DEL    ---     0.371    SLICE_67.A1 to    SLICE_67.F1 SLICE_67
-ROUTE         1   e 1.441    SLICE_67.F1 to    SLICE_82.C1 n2154
-CTOF_DEL    ---     0.371    SLICE_82.C1 to    SLICE_82.F1 SLICE_82
-ROUTE         1   e 1.441    SLICE_82.F1 to    SLICE_76.B1 n26
-CTOF_DEL    ---     0.371    SLICE_76.B1 to    SLICE_76.F1 SLICE_76
-ROUTE         4   e 1.441    SLICE_76.F1 to    SLICE_89.B0 n1285
-CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
-ROUTE         3   e 1.441    SLICE_89.F0 to    SLICE_18.D1 n2290
-CTOF_DEL    ---     0.371    SLICE_18.D1 to    SLICE_18.F1 SLICE_18
-ROUTE         3   e 1.441    SLICE_18.F1 to    SLICE_90.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371    SLICE_90.C0 to    SLICE_90.F0 SLICE_90
-ROUTE         2   e 1.441    SLICE_90.F0 to    SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   12.873   (21.6% logic, 78.4% route), 7 logic levels.
-
-Report:   26.276ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_76
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_77
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 5.575ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
-
-   Delay:              10.181ns  (23.7% logic, 76.3% route), 6 logic levels.
-
- Constraint Details:
-
-     10.181ns physical path delay SLICE_7 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560    SLICE_7.CLK to     SLICE_7.Q0 SLICE_7 (from RCLK_c)
-ROUTE         3   e 1.441     SLICE_7.Q0 to    SLICE_78.A0 FS_14
-CTOF_DEL    ---     0.371    SLICE_78.A0 to    SLICE_78.F0 SLICE_78
-ROUTE         3   e 1.441    SLICE_78.F0 to    SLICE_73.B1 n10
-CTOF_DEL    ---     0.371    SLICE_73.B1 to    SLICE_73.F1 SLICE_73
-ROUTE         4   e 0.561    SLICE_73.F1 to    SLICE_73.B0 n2300
-CTOF_DEL    ---     0.371    SLICE_73.B0 to    SLICE_73.F0 SLICE_73
-ROUTE         1   e 1.441    SLICE_73.F0 to    SLICE_75.C0 n11
-CTOF_DEL    ---     0.371    SLICE_75.C0 to    SLICE_75.F0 SLICE_75
-ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_33.D1 n2119
-CTOF_DEL    ---     0.371    SLICE_33.D1 to    SLICE_33.F1 SLICE_33
-ROUTE         1   e 1.441    SLICE_33.F1 to    SLICE_56.CE RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                   10.181   (23.7% logic, 76.3% route), 6 logic levels.
-
-Report:   10.425ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_55 and
-      5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets
-     12.500ns offset RCLK to RA[10] by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_55.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_55.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[9] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
-ROUTE         1   e 1.441    SLICE_88.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[8] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
-ROUTE         1   e 1.441    SLICE_95.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[7] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
-ROUTE         1   e 1.441    SLICE_97.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[6] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
-ROUTE         1   e 1.441    SLICE_98.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[5] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
-ROUTE         1   e 1.441    SLICE_98.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.427ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     6.569ns  (69.5% logic, 30.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets
-     12.500ns offset RCLK to RA[4] by 3.427ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.561    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
-ROUTE         1   e 1.441    SLICE_64.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
-                  --------
-                    6.569   (69.5% logic, 30.5% route), 3 logic levels.
-
-Report:    9.073ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[3] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
-ROUTE         1   e 1.441    SLICE_94.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[2] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
-ROUTE         1   e 1.441    SLICE_95.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[1] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
-ROUTE         1   e 1.441    SLICE_94.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[0] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
-ROUTE         1   e 1.441    SLICE_92.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_60 and
-      5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRCS by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_60.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_60.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_34 and
-      5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets
-     12.500ns offset RCLK to RCKE by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_34.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4   e 1.441    SLICE_34.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_63 and
-      5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRWE by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_63.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_61 and
-      5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRRAS by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_61.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2   e 1.441    SLICE_61.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_58 and
-      5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRCAS by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_58.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_58.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets
-     12.500ns offset RCLK to RDQMH by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
-ROUTE         1   e 1.441    SLICE_88.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets
-     12.500ns offset RCLK to RDQML by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
-ROUTE         1   e 1.441    SLICE_92.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.276 ns|   7  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    10.425 ns|   6  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.073 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:33:31 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1_map.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.485ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
-
-   Delay:               0.462ns  (56.7% logic, 43.3% route), 2 logic levels.
-
- Constraint Details:
-
-      0.462ns physical path delay SLICE_9 to SLICE_9 meets
-     -0.023ns DIN_HLD and
-      0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170    SLICE_9.CLK to     SLICE_9.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2   e 0.199     SLICE_9.Q0 to     SLICE_9.C0 ADSubmitted
-CTOF_DEL    ---     0.092     SLICE_9.C0 to     SLICE_9.F0 SLICE_9
-ROUTE         1   e 0.001     SLICE_9.F0 to    SLICE_9.DI0 n1361 (to PHI2_c)
-                  --------
-                    0.462   (56.7% logic, 43.3% route), 2 logic levels.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.377ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
-
-   Delay:               0.356ns  (44.1% logic, 55.9% route), 1 logic levels.
-
- Constraint Details:
-
-      0.356ns physical path delay SLICE_72 to SLICE_72 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns
-
- Physical Path Details:
-
-      Data path SLICE_72 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_72.CLK to    SLICE_72.Q0 SLICE_72 (from RCLK_c)
-ROUTE         1   e 0.199    SLICE_72.Q0 to    SLICE_72.M1 n702 (to RCLK_c)
-                  --------
-                    0.356   (44.1% logic, 55.9% route), 1 logic levels.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_55 and
-      1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to RA[10] by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_55.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_55.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[9] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
-ROUTE         1   e 0.515    SLICE_88.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[8] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
-ROUTE         1   e 0.515    SLICE_95.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[7] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
-ROUTE         1   e 0.515    SLICE_97.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[6] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
-ROUTE         1   e 0.515    SLICE_98.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[5] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
-ROUTE         1   e 0.515    SLICE_98.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.850ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     2.071ns  (65.5% logic, 34.5% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets
-      0.000ns hold offset RCLK to RA[4] by 2.850ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.199    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
-ROUTE         1   e 0.515    SLICE_64.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
-                  --------
-                    2.071   (65.5% logic, 34.5% route), 3 logic levels.
-
-Report:    2.850ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[3] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
-ROUTE         1   e 0.515    SLICE_94.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[2] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
-ROUTE         1   e 0.515    SLICE_95.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[1] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
-ROUTE         1   e 0.515    SLICE_94.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[0] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
-ROUTE         1   e 0.515    SLICE_92.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_60 and
-      1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRCS by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_60.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_60.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_34 and
-      1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to RCKE by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_34.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4   e 0.515    SLICE_34.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_63 and
-      1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRWE by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_63.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_61 and
-      1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRRAS by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_61.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2   e 0.515    SLICE_61.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_58 and
-      1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRCAS by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_58.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_58.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RDQMH by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
-ROUTE         1   e 0.515    SLICE_88.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RDQML by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
-ROUTE         1   e 0.515    SLICE_92.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.850 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
deleted file mode 100644
index 546895c..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
+++ /dev/null
@@ -1,4338 +0,0 @@
-
-Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:33:37 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,3
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 161.362ns (weighted slack = 322.724ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:              13.373ns  (20.8% logic, 79.2% route), 7 logic levels.
-
- Constraint Details:
-
-     13.373ns physical path delay SLICE_95 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.362ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
-ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   13.373   (20.8% logic, 79.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
-
- Constraint Details:
-
-     13.241ns physical path delay SLICE_95 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
-
- Constraint Details:
-
-     13.241ns physical path delay SLICE_95 to SLICE_88 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.945ns (weighted slack = 323.890ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
-
-   Delay:              12.790ns  (21.8% logic, 78.2% route), 7 logic levels.
-
- Constraint Details:
-
-     12.790ns physical path delay SLICE_95 to SLICE_23 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.945ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
-ROUTE         2     1.089       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   12.790   (21.8% logic, 78.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R6C7B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.961ns (weighted slack = 323.922ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
-
-   Delay:              12.774ns  (21.8% logic, 78.2% route), 7 logic levels.
-
- Constraint Details:
-
-     12.774ns physical path delay SLICE_95 to SLICE_96 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.961ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7C.C1 to       R5C7C.F1 SLICE_90
-ROUTE         1     1.073       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
-                  --------
-                   12.774   (21.8% logic, 78.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R5C8B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
-
-   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
-
- Constraint Details:
-
-     12.703ns physical path delay SLICE_95 to SLICE_18 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
-CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
-ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
-CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
-ROUTE         2     2.112       R6C9A.F0 to       R5C5A.B0 ADSubmitted_N_234
-CTOF_DEL    ---     0.371       R5C5A.B0 to       R5C5A.F0 SLICE_18
-ROUTE         1     0.000       R5C5A.F0 to      R5C5A.DI0 CmdEnable_N_236 (to PHI2_c)
-                  --------
-                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
-
-   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
-
- Constraint Details:
-
-     12.703ns physical path delay SLICE_95 to SLICE_9 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
-CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
-ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
-CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
-ROUTE         2     2.112       R6C9A.F0 to       R5C5B.B0 ADSubmitted_N_234
-CTOF_DEL    ---     0.371       R5C5B.B0 to       R5C5B.F0 SLICE_9
-ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
-                  --------
-                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R5C5B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.710ns (weighted slack = 325.420ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:              12.025ns  (23.2% logic, 76.8% route), 7 logic levels.
-
- Constraint Details:
-
-     12.025ns physical path delay SLICE_97 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.710ns
-
- Physical Path Details:
-
-      Data path SLICE_97 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
-ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
-CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
-ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
-CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
-ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   12.025   (23.2% logic, 76.8% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     11.893ns physical path delay SLICE_97 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
-
- Physical Path Details:
-
-      Data path SLICE_97 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
-ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
-CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
-ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
-CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     11.893ns physical path delay SLICE_97 to SLICE_88 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
-
- Physical Path Details:
-
-      Data path SLICE_97 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
-ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
-CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
-ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
-CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   27.276ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_76
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_77
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 6.557ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               9.262ns  (20.9% logic, 79.1% route), 4 logic levels.
-
- Constraint Details:
-
-      9.262ns physical path delay SLICE_65 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.557ns
-
- Physical Path Details:
-
-      Data path SLICE_65 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
-ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
-CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
-CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    9.262   (20.9% logic, 79.1% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_65:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.573ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               9.246ns  (20.7% logic, 79.3% route), 4 logic levels.
-
- Constraint Details:
-
-      9.246ns physical path delay SLICE_65 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.573ns
-
- Physical Path Details:
-
-      Data path SLICE_65 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
-ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
-CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
-CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    9.246   (20.7% logic, 79.3% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_65:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.866ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               8.890ns  (27.2% logic, 72.8% route), 6 logic levels.
-
- Constraint Details:
-
-      8.890ns physical path delay SLICE_7 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 6.866ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q1 SLICE_7 (from RCLK_c)
-ROUTE         3     1.466      R10C7D.Q1 to      R10C8D.B0 FS_15
-CTOF_DEL    ---     0.371      R10C8D.B0 to      R10C8D.F0 SLICE_78
-ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
-CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
-ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
-CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
-ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
-CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
-ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
-CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
-ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.890   (27.2% logic, 72.8% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.963ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               8.856ns  (21.8% logic, 78.2% route), 4 logic levels.
-
- Constraint Details:
-
-      8.856ns physical path delay SLICE_66 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.963ns
-
- Physical Path Details:
-
-      Data path SLICE_66 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
-ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
-CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
-CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    8.856   (21.8% logic, 78.2% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_66:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.979ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               8.840ns  (21.7% logic, 78.3% route), 4 logic levels.
-
- Constraint Details:
-
-      8.840ns physical path delay SLICE_66 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.979ns
-
- Physical Path Details:
-
-      Data path SLICE_66 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
-ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
-CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
-CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    8.840   (21.7% logic, 78.3% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_66:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.065ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               8.691ns  (27.8% logic, 72.2% route), 6 logic levels.
-
- Constraint Details:
-
-      8.691ns physical path delay SLICE_7 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.065ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q0 SLICE_7 (from RCLK_c)
-ROUTE         3     1.267      R10C7D.Q0 to      R10C8D.C0 FS_14
-CTOF_DEL    ---     0.371      R10C8D.C0 to      R10C8D.F0 SLICE_78
-ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
-CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
-ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
-CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
-ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
-CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
-ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
-CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
-ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.691   (27.8% logic, 72.2% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.284ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               8.472ns  (28.5% logic, 71.5% route), 6 logic levels.
-
- Constraint Details:
-
-      8.472ns physical path delay SLICE_8 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.284ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q1 SLICE_8 (from RCLK_c)
-ROUTE         3     1.048      R10C7C.Q1 to      R10C8D.A0 FS_13
-CTOF_DEL    ---     0.371      R10C8D.A0 to      R10C8D.F0 SLICE_78
-ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
-CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
-ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
-CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
-ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
-CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
-ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
-CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
-ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.472   (28.5% logic, 71.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.601ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               8.155ns  (29.6% logic, 70.4% route), 6 logic levels.
-
- Constraint Details:
-
-      8.155ns physical path delay SLICE_8 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.601ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q0 SLICE_8 (from RCLK_c)
-ROUTE         3     0.731      R10C7C.Q0 to      R10C8D.D0 FS_12
-CTOF_DEL    ---     0.371      R10C8D.D0 to      R10C8D.F0 SLICE_78
-ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
-CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
-ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
-CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
-ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
-CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
-ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
-CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
-ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.155   (29.6% logic, 70.4% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.732ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               8.087ns  (23.9% logic, 76.1% route), 4 logic levels.
-
- Constraint Details:
-
-      8.087ns physical path delay SLICE_61 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.732ns
-
- Physical Path Details:
-
-      Data path SLICE_61 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
-CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
-CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    8.087   (23.9% logic, 76.1% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.748ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               8.071ns  (23.8% logic, 76.2% route), 4 logic levels.
-
- Constraint Details:
-
-      8.071ns physical path delay SLICE_61 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.748ns
-
- Physical Path Details:
-
-      Data path SLICE_61 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
-CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
-CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    8.071   (23.8% logic, 76.2% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:    9.443ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_55 and
-      5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
-     12.500ns offset RCLK to RA[10] by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R2C5A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     0.817       R2C5A.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.088ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     7.924ns  (57.6% logic, 42.4% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.924ns delay SLICE_64 to RA[9] (totaling 10.412ns) meets
-     12.500ns offset RCLK to RA[9] by 2.088ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D1 nRowColSel
-CTOF_DEL    ---     0.371       R4C9A.D1 to       R4C9A.F1 SLICE_88
-ROUTE         1     2.564       R4C9A.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
-                  --------
-                    7.924   (57.6% logic, 42.4% route), 3 logic levels.
-
-Report:   10.412ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.035ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     7.977ns  (57.3% logic, 42.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.977ns delay SLICE_64 to RA[8] (totaling 10.465ns) meets
-     12.500ns offset RCLK to RA[8] by 2.035ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D0 nRowColSel
-CTOF_DEL    ---     0.371       R3C2B.D0 to       R3C2B.F0 SLICE_95
-ROUTE         1     1.660       R3C2B.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
-                  --------
-                    7.977   (57.3% logic, 42.7% route), 3 logic levels.
-
-Report:   10.465ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.583ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     7.429ns  (61.5% logic, 38.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.429ns delay SLICE_64 to RA[7] (totaling 9.917ns) meets
-     12.500ns offset RCLK to RA[7] by 2.583ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     2.045       R5C9A.Q0 to       R2C2A.C0 nRowColSel
-CTOF_DEL    ---     0.371       R2C2A.C0 to       R2C2A.F0 SLICE_97
-ROUTE         1     0.817       R2C2A.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
-                  --------
-                    7.429   (61.5% logic, 38.5% route), 3 logic levels.
-
-Report:    9.917ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.846ns delay SLICE_64 to RA[6] (totaling 10.334ns) meets
-     12.500ns offset RCLK to RA[6] by 2.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D0 nRowColSel
-CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_98
-ROUTE         1     1.526       R2C3A.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
-                  --------
-                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
-
-Report:   10.334ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.846ns delay SLICE_64 to RA[5] (totaling 10.334ns) meets
-     12.500ns offset RCLK to RA[5] by 2.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D1 nRowColSel
-CTOF_DEL    ---     0.371       R2C3A.D1 to       R2C3A.F1 SLICE_98
-ROUTE         1     1.526       R2C3A.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
-                  --------
-                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
-
-Report:   10.334ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.742ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     8.270ns  (55.2% logic, 44.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.270ns delay SLICE_64 to RA[4] (totaling 10.758ns) meets
-     12.500ns offset RCLK to RA[4] by 1.742ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.702       R5C9A.Q0 to       R5C9A.D1 nRowColSel
-CTOF_DEL    ---     0.371       R5C9A.D1 to       R5C9A.F1 SLICE_64
-ROUTE         1     3.001       R5C9A.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
-                  --------
-                    8.270   (55.2% logic, 44.8% route), 3 logic levels.
-
-Report:   10.758ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.725ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     8.287ns  (55.1% logic, 44.9% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.287ns delay SLICE_64 to RA[3] (totaling 10.775ns) meets
-     12.500ns offset RCLK to RA[3] by 1.725ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     2.198       R5C9A.Q0 to       R2C2C.D1 nRowColSel
-CTOF_DEL    ---     0.371       R2C2C.D1 to       R2C2C.F1 SLICE_94
-ROUTE         1     1.522       R2C2C.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
-                  --------
-                    8.287   (55.1% logic, 44.9% route), 3 logic levels.
-
-Report:   10.775ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.643ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     8.369ns  (54.6% logic, 45.4% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.369ns delay SLICE_64 to RA[2] (totaling 10.857ns) meets
-     12.500ns offset RCLK to RA[2] by 1.643ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D1 nRowColSel
-CTOF_DEL    ---     0.371       R3C2B.D1 to       R3C2B.F1 SLICE_95
-ROUTE         1     2.052       R3C2B.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
-                  --------
-                    8.369   (54.6% logic, 45.4% route), 3 logic levels.
-
-Report:   10.857ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.417ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     8.595ns  (53.1% logic, 46.9% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.595ns delay SLICE_64 to RA[1] (totaling 11.083ns) meets
-     12.500ns offset RCLK to RA[1] by 1.417ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     2.045       R5C9A.Q0 to       R2C2C.C0 nRowColSel
-CTOF_DEL    ---     0.371       R2C2C.C0 to       R2C2C.F0 SLICE_94
-ROUTE         1     1.983       R2C2C.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
-                  --------
-                    8.595   (53.1% logic, 46.9% route), 3 logic levels.
-
-Report:   11.083ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.213ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     8.799ns  (51.9% logic, 48.1% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.799ns delay SLICE_64 to RA[0] (totaling 11.287ns) meets
-     12.500ns offset RCLK to RA[0] by 1.213ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D1 nRowColSel
-CTOF_DEL    ---     0.371       R8C9C.D1 to       R8C9C.F1 SLICE_92
-ROUTE         1     2.987       R8C9C.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
-                  --------
-                    8.799   (51.9% logic, 48.1% route), 3 logic levels.
-
-Report:   11.287ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_60 and
-      5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
-     12.500ns offset RCLK to nRCS by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R2C9C.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.817       R2C9C.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_34 and
-      5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
-     12.500ns offset RCLK to RCKE by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R2C7C.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     0.817       R2C7C.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     6.653ns  (63.1% logic, 36.9% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_63 and
-      6.653ns delay SLICE_63 to nRWE (totaling 9.141ns) meets
-     12.500ns offset RCLK to nRWE by 3.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to     R10C9C.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     2.457      R10C9C.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
-                  --------
-                    6.653   (63.1% logic, 36.9% route), 2 logic levels.
-
-Report:    9.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.325ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     6.687ns  (62.7% logic, 37.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_61 and
-      6.687ns delay SLICE_61 to nRRAS (totaling 9.175ns) meets
-     12.500ns offset RCLK to nRRAS by 3.325ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     2.491       R3C2A.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
-                  --------
-                    6.687   (62.7% logic, 37.3% route), 2 logic levels.
-
-Report:    9.175ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_58 and
-      5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
-     12.500ns offset RCLK to nRCAS by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R2C9B.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     0.817       R2C9B.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.669ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     7.343ns  (62.2% logic, 37.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.343ns delay SLICE_64 to RDQMH (totaling 9.831ns) meets
-     12.500ns offset RCLK to RDQMH by 2.669ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D0 nRowColSel
-CTOF_DEL    ---     0.371       R4C9A.D0 to       R4C9A.F0 SLICE_88
-ROUTE         1     1.983       R4C9A.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
-                  --------
-                    7.343   (62.2% logic, 37.8% route), 3 logic levels.
-
-Report:    9.831ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.383ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     6.629ns  (68.9% logic, 31.1% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      6.629ns delay SLICE_64 to RDQML (totaling 9.117ns) meets
-     12.500ns offset RCLK to RDQML by 3.383ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D0 nRowColSel
-CTOF_DEL    ---     0.371       R8C9C.D0 to       R8C9C.F0 SLICE_92
-ROUTE         1     0.817       R8C9C.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
-                  --------
-                    6.629   (68.9% logic, 31.1% route), 3 logic levels.
-
-Report:    9.117ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    27.276 ns|   7  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     9.443 ns|   4  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.412 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.465 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.917 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.758 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.775 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.857 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    11.083 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    11.287 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.175 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.831 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.117 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:33:37 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.447ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
-
-   Delay:               0.424ns  (61.8% logic, 38.2% route), 2 logic levels.
-
- Constraint Details:
-
-      0.424ns physical path delay SLICE_9 to SLICE_9 meets
-     -0.023ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.023ns) by 0.447ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.162       R5C5B.Q0 to       R5C5B.A0 ADSubmitted
-CTOF_DEL    ---     0.092       R5C5B.A0 to       R5C5B.F0 SLICE_9
-ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
-                  --------
-                    0.424   (61.8% logic, 38.2% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.113ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
-
-   Delay:               1.084ns  (32.7% logic, 67.3% route), 3 logic levels.
-
- Constraint Details:
-
-      1.084ns physical path delay SLICE_18 to SLICE_96 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.113ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
-CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C7C.C1 to       R5C7C.F1 SLICE_90
-ROUTE         1     0.267       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
-                  --------
-                    1.084   (32.7% logic, 67.3% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.118ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
-
-   Delay:               1.089ns  (32.5% logic, 67.5% route), 3 logic levels.
-
- Constraint Details:
-
-      1.089ns physical path delay SLICE_18 to SLICE_23 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.118ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
-CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
-ROUTE         2     0.272       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                    1.089   (32.5% logic, 67.5% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R6C7B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.238ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
-
- Constraint Details:
-
-      1.209ns physical path delay SLICE_18 to SLICE_83 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
-CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     0.392       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R7C8B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.238ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
-
- Constraint Details:
-
-      1.209ns physical path delay SLICE_18 to SLICE_88 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
-CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     0.392       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R4C9A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.270ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
-
-   Delay:               1.241ns  (35.9% logic, 64.1% route), 4 logic levels.
-
- Constraint Details:
-
-      1.241ns physical path delay SLICE_9 to SLICE_18 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.270ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.258       R5C5B.Q0 to       R5C5B.B1 ADSubmitted
-CTOF_DEL    ---     0.092       R5C5B.B1 to       R5C5B.F1 SLICE_9
-ROUTE         1     0.123       R5C5B.F1 to       R5C5D.C1 n2080
-CTOF_DEL    ---     0.092       R5C5D.C1 to       R5C5D.F1 SLICE_77
-ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
-CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
-ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
-                  --------
-                    1.241   (35.9% logic, 64.1% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.276ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:               1.247ns  (28.4% logic, 71.6% route), 3 logic levels.
-
- Constraint Details:
-
-      1.247ns physical path delay SLICE_18 to SLICE_19 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.276ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
-CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
-ROUTE         2     0.430       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                    1.247   (28.4% logic, 71.6% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R9C8B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.299ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted_379  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
-
-   Delay:               1.270ns  (35.1% logic, 64.9% route), 4 logic levels.
-
- Constraint Details:
-
-      1.270ns physical path delay SLICE_14 to SLICE_18 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.299ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5C.CLK to       R5C5C.Q0 SLICE_14 (from PHI2_c)
-ROUTE         1     0.238       R5C5C.Q0 to       R5C5C.A1 C1Submitted
-CTOF_DEL    ---     0.092       R5C5C.A1 to       R5C5C.F1 SLICE_14
-ROUTE         1     0.172       R5C5C.F1 to       R5C5D.B1 n2098
-CTOF_DEL    ---     0.092       R5C5D.B1 to       R5C5D.F1 SLICE_77
-ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
-CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
-ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
-                  --------
-                    1.270   (35.1% logic, 64.9% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 175.790ns (weighted slack = 351.580ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              XOR8MEG_381  (from PHI2_c -)
-   Destination:    FF         Data in        RA11_358  (to PHI2_c +)
-
-   Delay:               0.779ns  (33.6% logic, 66.4% route), 2 logic levels.
-
- Constraint Details:
-
-      0.779ns physical path delay SLICE_96 to SLICE_31 meets
-     -0.011ns DIN_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.011ns) by 175.790ns
-
- Physical Path Details:
-
-      Data path SLICE_96 to SLICE_31:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C8B.CLK to       R5C8B.Q0 SLICE_96 (from PHI2_c)
-ROUTE         1     0.517       R5C8B.Q0 to       R2C9A.B0 XOR8MEG
-CTOF_DEL    ---     0.092       R2C9A.B0 to       R2C9A.F0 SLICE_31
-ROUTE         1     0.000       R2C9A.F0 to      R2C9A.DI0 RA11_N_180 (to PHI2_c)
-                  --------
-                    0.779   (33.6% logic, 66.4% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_31:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R2C9A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 176.484ns (weighted slack = 352.968ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i3  (from PHI2_c +)
-   Destination:    FF         Data in        C1Submitted_379  (to PHI2_c -)
-
-   Delay:               1.455ns  (23.4% logic, 76.6% route), 3 logic levels.
-
- Constraint Details:
-
-      1.455ns physical path delay SLICE_98 to SLICE_14 meets
-     -0.029ns CE_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.029ns) by 176.484ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C3A.CLK to       R2C3A.Q1 SLICE_98 (from PHI2_c)
-ROUTE         1     0.382       R2C3A.Q1 to       R4C2A.B1 Bank_3
-CTOF_DEL    ---     0.092       R4C2A.B1 to       R4C2A.F1 SLICE_76
-ROUTE         4     0.556       R4C2A.F1 to       R5C6A.B1 n1285
-CTOF_DEL    ---     0.092       R5C6A.B1 to       R5C6A.F1 SLICE_89
-ROUTE         1     0.176       R5C6A.F1 to       R5C5C.CE PHI2_N_114_enable_1 (to PHI2_c)
-                  --------
-                    1.455   (23.4% logic, 76.6% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R2C3A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_72 to SLICE_72 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_72 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q0 SLICE_72 (from RCLK_c)
-ROUTE         1     0.161       R5C7A.Q0 to       R5C7A.M1 n702 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_72 to SLICE_90 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_72 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q1 SLICE_72 (from RCLK_c)
-ROUTE         1     0.161       R5C7A.Q1 to       R5C7C.M0 n701 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i7  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i8  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_73 to SLICE_73 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_73 to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R9C8A.CLK to       R9C8A.Q0 SLICE_73 (from RCLK_c)
-ROUTE         1     0.161       R9C8A.Q0 to       R9C8A.M1 n706 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_74 to SLICE_74 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_74 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C6C.CLK to       R5C6C.Q0 SLICE_74 (from RCLK_c)
-ROUTE         1     0.161       R5C6C.Q0 to       R5C6C.M1 n710 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_75 to SLICE_73 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_75 to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q1 SLICE_75 (from RCLK_c)
-ROUTE         1     0.161       R9C8D.Q1 to       R9C8A.M0 n707 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i5  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i6  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_75 to SLICE_75 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_75 to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q0 SLICE_75 (from RCLK_c)
-ROUTE         1     0.161       R9C8D.Q0 to       R9C8D.M1 n708 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              PHI2r_349  (from RCLK_c +)
-   Destination:    FF         Data in        PHI2r2_350  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_85 to SLICE_78 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_85 to SLICE_78:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157     R10C8C.CLK to      R10C8C.Q1 SLICE_85 (from RCLK_c)
-ROUTE         1     0.161      R10C8C.Q1 to      R10C8D.M1 PHI2r (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_78:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_87 to SLICE_74 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_87 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C6B.CLK to       R5C6B.Q1 SLICE_87 (from RCLK_c)
-ROUTE         1     0.161       R5C6B.Q1 to       R5C6C.M0 n711 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_87:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C6B.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i13  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i14  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_90 to SLICE_90 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_90 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C7C.CLK to       R5C7C.Q0 SLICE_90 (from RCLK_c)
-ROUTE         1     0.161       R5C7C.Q0 to       R5C7C.M1 n700 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.345ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              PHI2r2_350  (from RCLK_c +)
-   Destination:    FF         Data in        PHI2r3_351  (to RCLK_c +)
-
-   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.324ns physical path delay SLICE_78 to SLICE_85 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
-
- Physical Path Details:
-
-      Data path SLICE_78 to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157     R10C8D.CLK to      R10C8D.Q1 SLICE_78 (from RCLK_c)
-ROUTE         3     0.167      R10C8D.Q1 to      R10C8C.M0 PHI2r2 (to RCLK_c)
-                  --------
-                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_78:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_55 and
-      1.462ns delay SLICE_55 to RA[10] (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to RA[10] by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C5A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     0.197       R2C5A.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.668ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     2.181ns  (62.2% logic, 37.8% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.181ns delay SLICE_64 to RA[9] (totaling 2.668ns) meets
-      0.000ns hold offset RCLK to RA[9] by 2.668ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D1 nRowColSel
-CTOF_DEL    ---     0.092       R4C9A.D1 to       R4C9A.F1 SLICE_88
-ROUTE         1     0.625       R4C9A.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
-                  --------
-                    2.181   (62.2% logic, 37.8% route), 3 logic levels.
-
-Report:    2.668ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.689ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     2.202ns  (61.6% logic, 38.4% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.202ns delay SLICE_64 to RA[8] (totaling 2.689ns) meets
-      0.000ns hold offset RCLK to RA[8] by 2.689ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D0 nRowColSel
-CTOF_DEL    ---     0.092       R3C2B.D0 to       R3C2B.F0 SLICE_95
-ROUTE         1     0.394       R3C2B.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
-                  --------
-                    2.202   (61.6% logic, 38.4% route), 3 logic levels.
-
-Report:    2.689ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.572ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     2.085ns  (65.1% logic, 34.9% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.085ns delay SLICE_64 to RA[7] (totaling 2.572ns) meets
-      0.000ns hold offset RCLK to RA[7] by 2.572ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.531       R5C9A.Q0 to       R2C2A.C0 nRowColSel
-CTOF_DEL    ---     0.092       R2C2A.C0 to       R2C2A.F0 SLICE_97
-ROUTE         1     0.197       R2C2A.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
-                  --------
-                    2.085   (65.1% logic, 34.9% route), 3 logic levels.
-
-Report:    2.572ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.652ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.165ns delay SLICE_64 to RA[6] (totaling 2.652ns) meets
-      0.000ns hold offset RCLK to RA[6] by 2.652ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D0 nRowColSel
-CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_98
-ROUTE         1     0.356       R2C3A.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
-                  --------
-                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
-
-Report:    2.652ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.652ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.165ns delay SLICE_64 to RA[5] (totaling 2.652ns) meets
-      0.000ns hold offset RCLK to RA[5] by 2.652ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D1 nRowColSel
-CTOF_DEL    ---     0.092       R2C3A.D1 to       R2C3A.F1 SLICE_98
-ROUTE         1     0.356       R2C3A.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
-                  --------
-                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
-
-Report:    2.652ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.776ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     2.289ns  (59.3% logic, 40.7% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.289ns delay SLICE_64 to RA[4] (totaling 2.776ns) meets
-      0.000ns hold offset RCLK to RA[4] by 2.776ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.178       R5C9A.Q0 to       R5C9A.D1 nRowColSel
-CTOF_DEL    ---     0.092       R5C9A.D1 to       R5C9A.F1 SLICE_64
-ROUTE         1     0.754       R5C9A.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
-                  --------
-                    2.289   (59.3% logic, 40.7% route), 3 logic levels.
-
-Report:    2.776ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.772ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     2.285ns  (59.4% logic, 40.6% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.285ns delay SLICE_64 to RA[3] (totaling 2.772ns) meets
-      0.000ns hold offset RCLK to RA[3] by 2.772ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.571       R5C9A.Q0 to       R2C2C.D1 nRowColSel
-CTOF_DEL    ---     0.092       R2C2C.D1 to       R2C2C.F1 SLICE_94
-ROUTE         1     0.357       R2C2C.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
-                  --------
-                    2.285   (59.4% logic, 40.6% route), 3 logic levels.
-
-Report:    2.772ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.787ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     2.300ns  (59.0% logic, 41.0% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.300ns delay SLICE_64 to RA[2] (totaling 2.787ns) meets
-      0.000ns hold offset RCLK to RA[2] by 2.787ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D1 nRowColSel
-CTOF_DEL    ---     0.092       R3C2B.D1 to       R3C2B.F1 SLICE_95
-ROUTE         1     0.492       R3C2B.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
-                  --------
-                    2.300   (59.0% logic, 41.0% route), 3 logic levels.
-
-Report:    2.787ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.855ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     2.368ns  (57.3% logic, 42.7% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.368ns delay SLICE_64 to RA[1] (totaling 2.855ns) meets
-      0.000ns hold offset RCLK to RA[1] by 2.855ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.531       R5C9A.Q0 to       R2C2C.C0 nRowColSel
-CTOF_DEL    ---     0.092       R2C2C.C0 to       R2C2C.F0 SLICE_94
-ROUTE         1     0.480       R2C2C.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
-                  --------
-                    2.368   (57.3% logic, 42.7% route), 3 logic levels.
-
-Report:    2.855ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.893ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     2.406ns  (56.4% logic, 43.6% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.406ns delay SLICE_64 to RA[0] (totaling 2.893ns) meets
-      0.000ns hold offset RCLK to RA[0] by 2.893ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D1 nRowColSel
-CTOF_DEL    ---     0.092       R8C9C.D1 to       R8C9C.F1 SLICE_92
-ROUTE         1     0.739       R8C9C.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
-                  --------
-                    2.406   (56.4% logic, 43.6% route), 3 logic levels.
-
-Report:    2.893ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_60 and
-      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to nRCS by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C9C.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.197       R2C9C.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_34 and
-      1.462ns delay SLICE_34 to RCKE (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to RCKE by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C7C.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     0.197       R2C7C.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.356ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     1.869ns  (67.7% logic, 32.3% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_63 and
-      1.869ns delay SLICE_63 to nRWE (totaling 2.356ns) meets
-      0.000ns hold offset RCLK to nRWE by 2.356ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to     R10C9C.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     0.604      R10C9C.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
-                  --------
-                    1.869   (67.7% logic, 32.3% route), 2 logic levels.
-
-Report:    2.356ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.363ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     1.876ns  (67.4% logic, 32.6% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_61 and
-      1.876ns delay SLICE_61 to nRRAS (totaling 2.363ns) meets
-      0.000ns hold offset RCLK to nRRAS by 2.363ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     0.611       R3C2A.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
-                  --------
-                    1.876   (67.4% logic, 32.6% route), 2 logic levels.
-
-Report:    2.363ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_58 and
-      1.462ns delay SLICE_58 to nRCAS (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to nRCAS by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C9B.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     0.197       R2C9B.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.523ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     2.036ns  (66.7% logic, 33.3% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.036ns delay SLICE_64 to RDQMH (totaling 2.523ns) meets
-      0.000ns hold offset RCLK to RDQMH by 2.523ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D0 nRowColSel
-CTOF_DEL    ---     0.092       R4C9A.D0 to       R4C9A.F0 SLICE_88
-ROUTE         1     0.480       R4C9A.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
-                  --------
-                    2.036   (66.7% logic, 33.3% route), 3 logic levels.
-
-Report:    2.523ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.351ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     1.864ns  (72.8% logic, 27.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      1.864ns delay SLICE_64 to RDQML (totaling 2.351ns) meets
-      0.000ns hold offset RCLK to RDQML by 2.351ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D0 nRowColSel
-CTOF_DEL    ---     0.092       R8C9C.D0 to       R8C9C.F0 SLICE_92
-ROUTE         1     0.197       R8C9C.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
-                  --------
-                    1.864   (72.8% logic, 27.2% route), 3 logic levels.
-
-Report:    2.351ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.668 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.689 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.572 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.776 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.772 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.787 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.855 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.893 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.356 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.363 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.523 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.351 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
deleted file mode 100644
index b9ec128..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
+++ /dev/null
@@ -1,111 +0,0 @@
-
-Bitgen Report
-
-
-
-
-
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html
deleted file mode 100644
index 4d7032d..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html
+++ /dev/null
@@ -1,202 +0,0 @@
-
-I/O Timing Report
-
-
-
    I/O Timing Report
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 4
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-// Design: RAM2GS
-// Package: TQFP100
-// ncd File: ram2gs_lcmxo640c_impl1.ncd
-// Version: Diamond (64-bit) 3.12.0.240.2
-// Written on Mon Aug 16 21:33:38 2021
-// M: Minimum Performance Grade
-// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 5, 4, 3):
-
-// Input Setup and Hold Times
-
-Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-CROW[0] nCRAS F     0.474      3       1.625     3
-CROW[1] nCRAS F     0.104      3       1.925     3
-Din[0]  PHI2  F     6.682      3       1.613     3
-Din[0]  nCCAS F    -0.028      M       2.082     3
-Din[1]  PHI2  F     6.886      3       2.631     3
-Din[1]  nCCAS F    -0.025      M       2.074     3
-Din[2]  PHI2  F     5.426      3       1.921     3
-Din[2]  nCCAS F     1.175      3       1.003     3
-Din[3]  PHI2  F     5.699      3       1.852     3
-Din[3]  nCCAS F     0.331      3       1.707     3
-Din[4]  PHI2  F     6.556      3       1.438     3
-Din[4]  nCCAS F     0.706      3       1.406     3
-Din[5]  PHI2  F     6.281      3       1.959     3
-Din[5]  nCCAS F     0.246      3       1.807     3
-Din[6]  PHI2  F     5.585      3       1.441     3
-Din[6]  nCCAS F     0.799      3       1.341     3
-Din[7]  PHI2  F     7.980      3       1.725     3
-Din[7]  nCCAS F     0.333      3       1.707     3
-MAin[0] PHI2  F     4.994      3       1.265     3
-MAin[0] nCRAS F     0.662      3       1.471     3
-MAin[1] PHI2  F     6.056      3       1.867     3
-MAin[1] nCRAS F     1.180      3       0.990     3
-MAin[2] PHI2  F    10.634      3      -1.183     M
-MAin[2] nCRAS F    -0.218      M       2.631     3
-MAin[3] PHI2  F    10.902      3      -1.260     M
-MAin[3] nCRAS F     0.208      3       1.826     3
-MAin[4] PHI2  F    10.204      3      -1.072     M
-MAin[4] nCRAS F    -0.218      M       2.628     3
-MAin[5] PHI2  F     7.043      3      -0.270     M
-MAin[5] nCRAS F     0.123      3       1.925     3
-MAin[6] PHI2  F     9.465      3      -0.885     M
-MAin[6] nCRAS F     0.584      3       1.522     3
-MAin[7] PHI2  F     9.683      3      -0.938     M
-MAin[7] nCRAS F    -0.218      M       2.628     3
-MAin[8] nCRAS F     0.316      3       1.758     3
-MAin[9] nCRAS F    -0.058      M       2.185     3
-PHI2    RCLK  R     1.456      3       0.038     3
-UFMSDO  RCLK  R     2.953      3      -0.147     M
-nCCAS   RCLK  R     2.435      3      -0.244     M
-nCCAS   nCRAS F     0.156      3       1.902     3
-nCRAS   RCLK  R     5.307      3      -0.787     M
-nFWE    PHI2  F     5.614      3       1.072     3
-nFWE    nCRAS F    -0.101      M       2.317     3
-
-
-// Clock to Output Delay
-
-Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-LED    RCLK  R    11.635         3        3.019          M
-RA[0]  RCLK  R    11.287         3        2.893          M
-RA[0]  nCRAS F    15.323         3        3.902          M
-RA[10] RCLK  R     7.501         3        1.949          M
-RA[11] PHI2  R     9.747         3        2.487          M
-RA[1]  RCLK  R    11.083         3        2.855          M
-RA[1]  nCRAS F    12.034         3        3.047          M
-RA[2]  RCLK  R    10.857         3        2.787          M
-RA[2]  nCRAS F    13.411         3        3.403          M
-RA[3]  RCLK  R    10.775         3        2.772          M
-RA[3]  nCRAS F    12.977         3        3.296          M
-RA[4]  RCLK  R    10.758         3        2.776          M
-RA[4]  nCRAS F    14.192         3        3.619          M
-RA[5]  RCLK  R    10.334         3        2.652          M
-RA[5]  nCRAS F    13.484         3        3.424          M
-RA[6]  RCLK  R    10.334         3        2.652          M
-RA[6]  nCRAS F    12.972         3        3.291          M
-RA[7]  RCLK  R     9.917         3        2.572          M
-RA[7]  nCRAS F    12.327         3        3.147          M
-RA[8]  RCLK  R    10.465         3        2.689          M
-RA[8]  nCRAS F    12.559         3        3.170          M
-RA[9]  RCLK  R    10.412         3        2.668          M
-RA[9]  nCRAS F    14.019         3        3.564          M
-RBA[0] nCRAS F    11.063         3        2.809          M
-RBA[1] nCRAS F    11.902         3        3.028          M
-RCKE   RCLK  R     7.501         3        1.949          M
-RDQMH  RCLK  R     9.831         3        2.523          M
-RDQML  RCLK  R     9.117         3        2.351          M
-RD[0]  nCCAS F    12.575         3        3.249          M
-RD[1]  nCCAS F    13.016         3        3.365          M
-RD[2]  nCCAS F    11.602         3        2.993          M
-RD[3]  nCCAS F    10.893         3        2.834          M
-RD[4]  nCCAS F    12.063         3        3.116          M
-RD[5]  nCCAS F    12.555         3        3.242          M
-RD[6]  nCCAS F    12.537         3        3.240          M
-RD[7]  nCCAS F    12.524         3        3.239          M
-UFMCLK RCLK  R     8.079         3        2.126          M
-UFMSDI RCLK  R     8.079         3        2.126          M
-nRCAS  RCLK  R     7.501         3        1.949          M
-nRCS   RCLK  R     7.501         3        1.949          M
-nRRAS  RCLK  R     9.175         3        2.363          M
-nRWE   RCLK  R     9.141         3        2.356          M
-nUFMCS RCLK  R     8.804         3        2.290          M
-WARNING: you must also run trce with hold speed: 3
-WARNING: you must also run trce with setup speed: M
-
-
-
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
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-
    
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-
    
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-
    
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-
    
-
    
-
    
-
    
-
    
-
    
-
    
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-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
-
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj
deleted file mode 100644
index f265fc9..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj
+++ /dev/null
@@ -1,41 +0,0 @@
--a "MachXO"
--d LCMXO640C
--t TQFP100
--s 3
--frequency 200
--optimization_goal Balanced
--bram_utilization 100
--ramstyle Auto
--romstyle auto
--dsp_utilization 100
--use_dsp 1
--use_carry_chain 1
--carry_chain_length 0
--force_gsr Auto
--resource_sharing 1
--propagate_constants 1
--remove_duplicate_regs 1
--mux_style Auto
--max_fanout 1000
--fsm_encoding_style Auto
--twr_paths 3
--fix_gated_clocks 1
--loop_limit 1950
-
-
-
--use_io_insertion 1
--resolve_mixed_drivers 0
--use_io_reg auto
-
-
--lpf 1
--p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C"
--ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
--top RAM2GS
-
-
--p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C"
-
--ngd "RAM2GS_LCMXO640C_impl1.ngd"
-
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd
deleted file mode 100644
index a946767..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd
+++ /dev/null
@@ -1,13 +0,0 @@
-[ActiveSupport MAP]
-Device = LCMXO640C;
-Package = TQFP100;
-Performance = 3;
-LUTS_avail = 640;
-LUTS_used = 129;
-FF_avail = 640;
-FF_used = 102;
-INPUT_LVTTL33 = 26;
-OUTPUT_LVTTL33 = 33;
-BIDI_LVTTL33 = 8;
-IO_avail = 74;
-IO_used = 67;
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam
deleted file mode 100644
index 4787547..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam
+++ /dev/null
@@ -1,108 +0,0 @@
-[ START MERGED ]
-nCRAS_N_9 nCRAS_c
-nCCAS_N_3 nCCAS_c
-n2307 Ready
-n2306 nFWE_c
-PHI2_N_114 PHI2_c
-n2302 nRowColSel_N_35
-nRWE_N_172 nRWE_N_173
-UFMSDO_N_74 UFMSDO_c
-n1377 nRowColSel_N_34
-RASr2_N_63 RASr2
-[ END MERGED ]
-[ START CLIPPED ]
-GND_net
-VCC_net
-FS_577_add_4_14/CO0
-FS_577_add_4_16/CO0
-FS_577_add_4_12/CO0
-FS_577_add_4_2/CO0
-FS_577_add_4_4/CO0
-FS_577_add_4_6/CO0
-FS_577_add_4_18/CO1
-FS_577_add_4_18/CO0
-FS_577_add_4_8/CO0
-FS_577_add_4_10/CO0
-[ END CLIPPED ]
-[ START DESIGN PREFS ]
-SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:33:30 2021
-
-SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
-LOCATE COMP "RD[7]" SITE "71" ;
-LOCATE COMP "RD[6]" SITE "70" ;
-LOCATE COMP "RD[5]" SITE "69" ;
-LOCATE COMP "RD[4]" SITE "68" ;
-LOCATE COMP "RD[3]" SITE "67" ;
-LOCATE COMP "RD[2]" SITE "66" ;
-LOCATE COMP "RD[1]" SITE "65" ;
-LOCATE COMP "RD[0]" SITE "64" ;
-LOCATE COMP "Dout[7]" SITE "3" ;
-LOCATE COMP "Dout[6]" SITE "2" ;
-LOCATE COMP "Dout[5]" SITE "5" ;
-LOCATE COMP "Dout[4]" SITE "4" ;
-LOCATE COMP "Dout[3]" SITE "6" ;
-LOCATE COMP "Dout[2]" SITE "8" ;
-LOCATE COMP "Dout[1]" SITE "7" ;
-LOCATE COMP "Dout[0]" SITE "1" ;
-LOCATE COMP "LED" SITE "57" ;
-LOCATE COMP "RBA[1]" SITE "83" ;
-LOCATE COMP "RBA[0]" SITE "63" ;
-LOCATE COMP "RA[11]" SITE "79" ;
-LOCATE COMP "RA[10]" SITE "87" ;
-LOCATE COMP "RA[9]" SITE "85" ;
-LOCATE COMP "RA[8]" SITE "96" ;
-LOCATE COMP "RA[7]" SITE "100" ;
-LOCATE COMP "RA[6]" SITE "91" ;
-LOCATE COMP "RA[5]" SITE "95" ;
-LOCATE COMP "RA[4]" SITE "99" ;
-LOCATE COMP "RA[3]" SITE "97" ;
-LOCATE COMP "RA[2]" SITE "94" ;
-LOCATE COMP "RA[1]" SITE "89" ;
-LOCATE COMP "RA[0]" SITE "98" ;
-LOCATE COMP "nRCS" SITE "77" ;
-LOCATE COMP "RCKE" SITE "82" ;
-LOCATE COMP "nRWE" SITE "72" ;
-LOCATE COMP "nRRAS" SITE "73" ;
-LOCATE COMP "nRCAS" SITE "78" ;
-LOCATE COMP "RDQMH" SITE "76" ;
-LOCATE COMP "RDQML" SITE "61" ;
-LOCATE COMP "nUFMCS" SITE "53" ;
-LOCATE COMP "UFMCLK" SITE "58" ;
-LOCATE COMP "UFMSDI" SITE "56" ;
-LOCATE COMP "PHI2" SITE "39" ;
-LOCATE COMP "MAin[9]" SITE "51" ;
-LOCATE COMP "MAin[8]" SITE "50" ;
-LOCATE COMP "MAin[7]" SITE "44" ;
-LOCATE COMP "MAin[6]" SITE "49" ;
-LOCATE COMP "MAin[5]" SITE "45" ;
-LOCATE COMP "MAin[4]" SITE "46" ;
-LOCATE COMP "MAin[3]" SITE "47" ;
-LOCATE COMP "MAin[2]" SITE "37" ;
-LOCATE COMP "MAin[1]" SITE "38" ;
-LOCATE COMP "MAin[0]" SITE "23" ;
-LOCATE COMP "CROW[1]" SITE "34" ;
-LOCATE COMP "CROW[0]" SITE "32" ;
-LOCATE COMP "Din[7]" SITE "19" ;
-LOCATE COMP "Din[6]" SITE "20" ;
-LOCATE COMP "Din[5]" SITE "17" ;
-LOCATE COMP "Din[4]" SITE "18" ;
-LOCATE COMP "Din[3]" SITE "16" ;
-LOCATE COMP "Din[2]" SITE "14" ;
-LOCATE COMP "Din[1]" SITE "15" ;
-LOCATE COMP "Din[0]" SITE "21" ;
-LOCATE COMP "nCCAS" SITE "27" ;
-LOCATE COMP "nCRAS" SITE "43" ;
-LOCATE COMP "nFWE" SITE "22" ;
-LOCATE COMP "RCLK" SITE "86" ;
-LOCATE COMP "UFMSDO" SITE "55" ;
-PERIOD NET "PHI2_c" 350.000000 ns  ;
-USE PRIMARY NET "RCLK_c" ;
-PERIOD NET "nCCAS_c" 350.000000 ns  ;
-USE PRIMARY NET "PHI2_c" ;
-PERIOD NET "nCRAS_c" 350.000000 ns  ;
-USE PRIMARY NET "nCCAS_c" ;
-PERIOD NET "RCLK_c" 16.000000 ns  ;
-USE PRIMARY NET "nCRAS_c" ;
-SCHEMATIC END ;
-[ END DESIGN PREFS ]
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr
deleted file mode 100644
index 5a900d5..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr
+++ /dev/null
@@ -1,10 +0,0 @@
----------------------------------------------------
-Report for cell RAM2GS
-   Instance path: RAM2GS
-                     Cell usage:
-                                  cell	      count    Res Usage(%)
-                                  SLIC	      65.00        100.0
-                                  LUT4	     111.00        100.0
-                                 IOBUF	         67        100.0
-                                PFUREG	        102        100.0
-                                RIPPLE	          9        100.0
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd
deleted file mode 100644
index f4f2deb380a22c1d20baf60d9a638727b58154a0..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html
deleted file mode 100644
index cee33ff..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html
+++ /dev/null
@@ -1,425 +0,0 @@
-
-Project Summary
-
-
-
    
-            Lattice Mapping Report File for Design Module 'RAM2GS'
-
-
-
-Design Information
-
-Command line:   map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial
-     RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr
-     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf C:/Users/Dog
-     /Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.
-     lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_L
-     CMXO640C.lpf -c 0 -gui -msgset
-     C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
-Target Vendor:  LATTICE
-Target Device:  LCMXO640CTQFP100
-Target Performance:   3
-Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.0.240.2
-Mapped on:  08/16/21  21:33:30
-
-
-Design Summary
-   Number of PFU registers:   102 out of   640 (16%)
-   Number of SLICEs:        65 out of   320 (20%)
-      SLICEs as Logic/ROM:     65 out of   320 (20%)
-      SLICEs as RAM:            0 out of   192 (0%)
-      SLICEs as Carry:          9 out of   320 (3%)
-   Number of LUT4s:        129 out of   640 (20%)
-      Number used as logic LUTs:        111
-      Number used as distributed RAM:     0
-      Number used as ripple logic:       18
-      Number used as shift registers:     0
-   Number of external PIOs: 67 out of 74 (91%)
-   Number of GSRs:  0 out of 1 (0%)
-   JTAG used :      No
-   Readback used :  No
-   Oscillator used :  No
-   Startup used :   No
-   Number of TSALL: 0 out of 1 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
-     distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and
-     ripple logic.
-   Number of clocks:  4
-     Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
-     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
-     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
-     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
-   Number of Clock Enables:  13
-     Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
-     Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
-     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
-     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
-     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
-     Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
-     Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
-     Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
-     Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
-
-     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
-     Net Ready_N_268: 1 loads, 1 LSLICEs
-   Number of LSRs:  9
-     Net RASr2: 1 loads, 1 LSLICEs
-     Net C1Submitted_N_225: 2 loads, 2 LSLICEs
-     Net n2299: 1 loads, 1 LSLICEs
-     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
-     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
-     Net LEDEN_N_88: 1 loads, 1 LSLICEs
-     Net n2291: 2 loads, 2 LSLICEs
-     Net Ready: 7 loads, 7 LSLICEs
-     Net nRWE_N_173: 1 loads, 1 LSLICEs
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net Ready: 19 loads
-     Net InitReady: 17 loads
-     Net RASr2: 16 loads
-     Net nRowColSel_N_35: 14 loads
-     Net nRowColSel: 13 loads
-     Net Din_c_6: 9 loads
-     Net MAin_c_1: 9 loads
-     Net Din_c_5: 8 loads
-     Net FS_11: 8 loads
-     Net MAin_c_0: 8 loads
-
-
-
-
-   Number of warnings:  0
-   Number of errors:    0
-     
-
-
-
-
-Design Errors/Warnings
-
-   No errors or warnings present.
-
-
-
-IO (PIO) Attributes
-
-+---------------------+-----------+-----------+------------+------------+
-| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
-|                     |           |  IO_TYPE  | Register   |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[7]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[6]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[5]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[4]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[3]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[2]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-| RD[1]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RD[0]               | BIDIR     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[7]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[6]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[5]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[4]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[3]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[2]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[1]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Dout[0]             | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| LED                 | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RBA[1]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RBA[0]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[11]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[10]              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[9]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[8]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[7]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[6]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[5]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[4]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[3]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[2]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[1]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RA[0]               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRCS                | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RCKE                | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRWE                | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-| nRRAS               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nRCAS               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RDQMH               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RDQML               | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nUFMCS              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMCLK              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMSDI              | OUTPUT    | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| PHI2                | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[9]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[8]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[7]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[6]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[5]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[4]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[3]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[2]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[1]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| MAin[0]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| CROW[1]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| CROW[0]             | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[7]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[6]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[5]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[4]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[3]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[2]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[1]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| Din[0]              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-| nCCAS               | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nCRAS               | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| nFWE                | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| RCLK                | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-| UFMSDO              | INPUT     | LVTTL33   |            |            |
-+---------------------+-----------+-----------+------------+------------+
-
-
-
-Removed logic
-
-Block i2 undriven or does not drive anything - clipped.
-Block GSR_INST undriven or does not drive anything - clipped.
-Signal PHI2_N_114 was merged into signal PHI2_c
-Signal nCRAS_N_9 was merged into signal nCRAS_c
-Signal nCCAS_N_3 was merged into signal nCCAS_c
-Signal n2302 was merged into signal nRowColSel_N_35
-Signal nRWE_N_172 was merged into signal nRWE_N_173
-Signal n2307 was merged into signal Ready
-Signal RASr2_N_63 was merged into signal RASr2
-Signal n1377 was merged into signal nRowColSel_N_34
-Signal n2306 was merged into signal nFWE_c
-Signal UFMSDO_N_74 was merged into signal UFMSDO_c
-Signal GND_net undriven or does not drive anything - clipped.
-Signal VCC_net undriven or does not drive anything - clipped.
-Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
-Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
-Block i1962 was optimized away.
-Block i1961 was optimized away.
-Block i1963 was optimized away.
-Block i1070_1_lut_rep_25 was optimized away.
-Block nRWE_I_49_1_lut was optimized away.
-Block i604_1_lut_rep_30 was optimized away.
-Block RASr2_I_0_1_lut was optimized away.
-Block i1069_1_lut was optimized away.
-Block i1_1_lut_rep_29 was optimized away.
-Block UFMSDO_I_0_1_lut was optimized away.
-Block i1 was optimized away.
-
-
-
-Run Time and Memory Usage
--------------------------
-
-   Total CPU Time: 0 secs  
-   Total REAL Time: 0 secs  
-   Peak Memory Usage: 30 MB
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-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-     Copyright (c) 1995 AT&T Corp.   All rights reserved.
-     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-     Copyright (c) 2001 Agere Systems   All rights reserved.
-     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
-     reserved.
-
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diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
deleted file mode 100644
index ab78925..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
+++ /dev/null
@@ -1,418 +0,0 @@
-
-PAD Specification File
-
-
-
    PAD Specification File
-***************************
-
-PART TYPE:        LCMXO640C
-Performance Grade:      3
-PACKAGE:          TQFP100
-Package Status:                     Final          Version 1.17
-
-Mon Aug 16 21:33:36 2021
-
-Pinout by Port Name:
-+-----------+----------+--------------+-------+----------------------------------+
-| Port Name | Pin/Bank | Buffer Type  | Site  | Properties                       |
-+-----------+----------+--------------+-------+----------------------------------+
-| CROW[0]   | 32/2     | LVTTL33_IN   | PB4C  | SLEW:FAST                        |
-| CROW[1]   | 34/2     | LVTTL33_IN   | PB4E  | SLEW:FAST                        |
-| Din[0]    | 21/3     | LVTTL33_IN   | PL10C | SLEW:FAST                        |
-| Din[1]    | 15/3     | LVTTL33_IN   | PL7B  | SLEW:FAST                        |
-| Din[2]    | 14/3     | LVTTL33_IN   | PL5B  | SLEW:FAST                        |
-| Din[3]    | 16/3     | LVTTL33_IN   | PL8C  | SLEW:FAST                        |
-| Din[4]    | 18/3     | LVTTL33_IN   | PL9A  | SLEW:FAST                        |
-| Din[5]    | 17/3     | LVTTL33_IN   | PL8D  | SLEW:FAST                        |
-| Din[6]    | 20/3     | LVTTL33_IN   | PL10A | SLEW:FAST                        |
-| Din[7]    | 19/3     | LVTTL33_IN   | PL9C  | SLEW:FAST                        |
-| Dout[0]   | 1/3      | LVTTL33_OUT  | PL2A  | DRIVE:4mA SLEW:SLOW              |
-| Dout[1]   | 7/3      | LVTTL33_OUT  | PL3C  | DRIVE:4mA SLEW:SLOW              |
-| Dout[2]   | 8/3      | LVTTL33_OUT  | PL3D  | DRIVE:4mA SLEW:SLOW              |
-| Dout[3]   | 6/3      | LVTTL33_OUT  | PL3B  | DRIVE:4mA SLEW:SLOW              |
-| Dout[4]   | 4/3      | LVTTL33_OUT  | PL2D  | DRIVE:4mA SLEW:SLOW              |
-| Dout[5]   | 5/3      | LVTTL33_OUT  | PL3A  | DRIVE:4mA SLEW:SLOW              |
-| Dout[6]   | 2/3      | LVTTL33_OUT  | PL2C  | DRIVE:4mA SLEW:SLOW              |
-| Dout[7]   | 3/3      | LVTTL33_OUT  | PL2B  | DRIVE:4mA SLEW:SLOW              |
-| LED       | 57/1     | LVTTL33_OUT  | PR10B | DRIVE:16mA SLEW:SLOW             |
-| MAin[0]   | 23/3     | LVTTL33_IN   | PL11C | SLEW:FAST                        |
-| MAin[1]   | 38/2     | LVTTL33_IN   | PB6B  | SLEW:FAST                        |
-| MAin[2]   | 37/2     | LVTTL33_IN   | PB5D  | SLEW:FAST                        |
-| MAin[3]   | 47/2     | LVTTL33_IN   | PB9C  | SLEW:FAST                        |
-| MAin[4]   | 46/2     | LVTTL33_IN   | PB9A  | SLEW:FAST                        |
-| MAin[5]   | 45/2     | LVTTL33_IN   | PB8D  | SLEW:FAST                        |
-| MAin[6]   | 49/2     | LVTTL33_IN   | PB9D  | SLEW:FAST                        |
-| MAin[7]   | 44/2     | LVTTL33_IN   | PB8C  | SLEW:FAST                        |
-| MAin[8]   | 50/2     | LVTTL33_IN   | PB9F  | SLEW:FAST                        |
-| MAin[9]   | 51/1     | LVTTL33_IN   | PR11D | SLEW:FAST                        |
-| PHI2      | 39/2     | LVTTL33_IN   | PB6C  | SLEW:FAST                        |
-| RA[0]     | 98/0     | LVTTL33_OUT  | PT2B  | DRIVE:4mA SLEW:SLOW              |
-| RA[10]    | 87/0     | LVTTL33_OUT  | PT5A  | DRIVE:4mA SLEW:SLOW              |
-| RA[11]    | 79/0     | LVTTL33_OUT  | PT9A  | DRIVE:4mA SLEW:SLOW              |
-| RA[1]     | 89/0     | LVTTL33_OUT  | PT4F  | DRIVE:4mA SLEW:SLOW              |
-| RA[2]     | 94/0     | LVTTL33_OUT  | PT3B  | DRIVE:4mA SLEW:SLOW              |
-| RA[3]     | 97/0     | LVTTL33_OUT  | PT2E  | DRIVE:4mA SLEW:SLOW              |
-| RA[4]     | 99/0     | LVTTL33_OUT  | PT2C  | DRIVE:4mA SLEW:SLOW              |
-| RA[5]     | 95/0     | LVTTL33_OUT  | PT3A  | DRIVE:4mA SLEW:SLOW              |
-| RA[6]     | 91/0     | LVTTL33_OUT  | PT3F  | DRIVE:4mA SLEW:SLOW              |
-| RA[7]     | 100/0    | LVTTL33_OUT  | PT2A  | DRIVE:4mA SLEW:SLOW              |
-| RA[8]     | 96/0     | LVTTL33_OUT  | PT2F  | DRIVE:4mA SLEW:SLOW              |
-| RA[9]     | 85/0     | LVTTL33_OUT  | PT6B  | DRIVE:4mA SLEW:SLOW              |
-| RBA[0]    | 63/1     | LVTTL33_OUT  | PR7B  | DRIVE:4mA SLEW:SLOW              |
-| RBA[1]    | 83/0     | LVTTL33_OUT  | PT7A  | DRIVE:4mA SLEW:SLOW              |
-| RCKE      | 82/0     | LVTTL33_OUT  | PT7E  | DRIVE:4mA SLEW:SLOW              |
-| RCLK      | 86/0     | LVTTL33_IN   | PT5B  | SLEW:FAST                        |
-| RDQMH     | 76/0     | LVTTL33_OUT  | PT9F  | DRIVE:4mA SLEW:SLOW              |
-| RDQML     | 61/1     | LVTTL33_OUT  | PR9B  | DRIVE:4mA SLEW:SLOW              |
-| RD[0]     | 64/1     | LVTTL33_BIDI | PR6C  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[1]     | 65/1     | LVTTL33_BIDI | PR6B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[2]     | 66/1     | LVTTL33_BIDI | PR5D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[3]     | 67/1     | LVTTL33_BIDI | PR5B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[4]     | 68/1     | LVTTL33_BIDI | PR4D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[5]     | 69/1     | LVTTL33_BIDI | PR4B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[6]     | 70/1     | LVTTL33_BIDI | PR3D  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| RD[7]     | 71/1     | LVTTL33_BIDI | PR3B  | DRIVE:4mA SLEW:SLOW PULL:KEEPER  |
-| UFMCLK    | 58/1     | LVTTL33_OUT  | PR10A | DRIVE:4mA SLEW:SLOW              |
-| UFMSDI    | 56/1     | LVTTL33_OUT  | PR10C | DRIVE:4mA SLEW:SLOW              |
-| UFMSDO    | 55/1     | LVTTL33_IN   | PR10D | SLEW:FAST PULL:KEEPER            |
-| nCCAS     | 27/2     | LVTTL33_IN   | PB2C  | SLEW:FAST                        |
-| nCRAS     | 43/2     | LVTTL33_IN   | PB8B  | SLEW:FAST                        |
-| nFWE      | 22/3     | LVTTL33_IN   | PL11A | SLEW:FAST                        |
-| nRCAS     | 78/0     | LVTTL33_OUT  | PT9C  | DRIVE:4mA SLEW:SLOW              |
-| nRCS      | 77/0     | LVTTL33_OUT  | PT9E  | DRIVE:4mA SLEW:SLOW              |
-| nRRAS     | 73/1     | LVTTL33_OUT  | PR2B  | DRIVE:4mA SLEW:SLOW              |
-| nRWE      | 72/1     | LVTTL33_OUT  | PR2D  | DRIVE:4mA SLEW:SLOW              |
-| nUFMCS    | 53/1     | LVTTL33_OUT  | PR11C | DRIVE:4mA SLEW:SLOW              |
-+-----------+----------+--------------+-------+----------------------------------+
-
-Vccio by Bank:
-+------+-------+
-| Bank | Vccio |
-+------+-------+
-| 0    | 3.3V  |
-| 1    | 3.3V  |
-| 2    |       |
-| 3    | 3.3V  |
-+------+-------+
-
-
-Vref by Bank:
-+------+-----+-----------------+---------+
-| Vref | Pin | Bank # / Vref # | Load(s) |
-+------+-----+-----------------+---------+
-+------+-----+-----------------+---------+
-
-Pinout by Pin Number:
-+----------+---------------------+------------+--------------+-------+---------------+
-| Pin/Bank | Pin Info            | Preference | Buffer Type  | Site  | Dual Function |
-+----------+---------------------+------------+--------------+-------+---------------+
-| 1/3      | Dout[0]             | LOCATED    | LVTTL33_OUT  | PL2A  |               |
-| 2/3      | Dout[6]             | LOCATED    | LVTTL33_OUT  | PL2C  |               |
-| 3/3      | Dout[7]             | LOCATED    | LVTTL33_OUT  | PL2B  |               |
-| 4/3      | Dout[4]             | LOCATED    | LVTTL33_OUT  | PL2D  |               |
-| 5/3      | Dout[5]             | LOCATED    | LVTTL33_OUT  | PL3A  |               |
-| 6/3      | Dout[3]             | LOCATED    | LVTTL33_OUT  | PL3B  |               |
-| 7/3      | Dout[1]             | LOCATED    | LVTTL33_OUT  | PL3C  |               |
-| 8/3      | Dout[2]             | LOCATED    | LVTTL33_OUT  | PL3D  |               |
-| 9/3      |     unused, PULL:UP |            |              | PL4A  |               |
-| 11/3     |     unused, PULL:UP |            |              | PL4C  |               |
-| 13/3     |     unused, PULL:UP |            |              | PL4D  |               |
-| 14/3     | Din[2]              | LOCATED    | LVTTL33_IN   | PL5B  | GSR_PADN      |
-| 15/3     | Din[1]              | LOCATED    | LVTTL33_IN   | PL7B  |               |
-| 16/3     | Din[3]              | LOCATED    | LVTTL33_IN   | PL8C  | TSALLPAD      |
-| 17/3     | Din[5]              | LOCATED    | LVTTL33_IN   | PL8D  |               |
-| 18/3     | Din[4]              | LOCATED    | LVTTL33_IN   | PL9A  |               |
-| 19/3     | Din[7]              | LOCATED    | LVTTL33_IN   | PL9C  |               |
-| 20/3     | Din[6]              | LOCATED    | LVTTL33_IN   | PL10A |               |
-| 21/3     | Din[0]              | LOCATED    | LVTTL33_IN   | PL10C |               |
-| 22/3     | nFWE                | LOCATED    | LVTTL33_IN   | PL11A |               |
-| 23/3     | MAin[0]             | LOCATED    | LVTTL33_IN   | PL11C |               |
-| 27/2     | nCCAS               | LOCATED    | LVTTL33_IN   | PB2C  |               |
-| 32/2     | CROW[0]             | LOCATED    | LVTTL33_IN   | PB4C  |               |
-| 34/2     | CROW[1]             | LOCATED    | LVTTL33_IN   | PB4E  |               |
-| 36/2     |     unused, PULL:UP |            |              | PB5B  | PCLKT2_1      |
-| 37/2     | MAin[2]             | LOCATED    | LVTTL33_IN   | PB5D  |               |
-| 38/2     | MAin[1]             | LOCATED    | LVTTL33_IN   | PB6B  | PCLKT2_0      |
-| 39/2     | PHI2                | LOCATED    | LVTTL33_IN   | PB6C  |               |
-| 43/2     | nCRAS               | LOCATED    | LVTTL33_IN   | PB8B  |               |
-| 44/2     | MAin[7]             | LOCATED    | LVTTL33_IN   | PB8C  |               |
-| 45/2     | MAin[5]             | LOCATED    | LVTTL33_IN   | PB8D  |               |
-| 46/2     | MAin[4]             | LOCATED    | LVTTL33_IN   | PB9A  |               |
-| 47/2     | MAin[3]             | LOCATED    | LVTTL33_IN   | PB9C  |               |
-| 49/2     | MAin[6]             | LOCATED    | LVTTL33_IN   | PB9D  |               |
-| 50/2     | MAin[8]             | LOCATED    | LVTTL33_IN   | PB9F  |               |
-| 51/1     | MAin[9]             | LOCATED    | LVTTL33_IN   | PR11D |               |
-| 52/1     |     unused, PULL:UP |            |              | PR11B |               |
-| 53/1     | nUFMCS              | LOCATED    | LVTTL33_OUT  | PR11C |               |
-| 54/1     |     unused, PULL:UP |            |              | PR11A |               |
-| 55/1     | UFMSDO              | LOCATED    | LVTTL33_IN   | PR10D |               |
-| 56/1     | UFMSDI              | LOCATED    | LVTTL33_OUT  | PR10C |               |
-| 57/1     | LED                 | LOCATED    | LVTTL33_OUT  | PR10B |               |
-| 58/1     | UFMCLK              | LOCATED    | LVTTL33_OUT  | PR10A |               |
-| 59/1     |     unused, PULL:UP |            |              | PR9D  |               |
-| 61/1     | RDQML               | LOCATED    | LVTTL33_OUT  | PR9B  |               |
-| 63/1     | RBA[0]              | LOCATED    | LVTTL33_OUT  | PR7B  |               |
-| 64/1     | RD[0]               | LOCATED    | LVTTL33_BIDI | PR6C  |               |
-| 65/1     | RD[1]               | LOCATED    | LVTTL33_BIDI | PR6B  |               |
-| 66/1     | RD[2]               | LOCATED    | LVTTL33_BIDI | PR5D  |               |
-| 67/1     | RD[3]               | LOCATED    | LVTTL33_BIDI | PR5B  |               |
-| 68/1     | RD[4]               | LOCATED    | LVTTL33_BIDI | PR4D  |               |
-| 69/1     | RD[5]               | LOCATED    | LVTTL33_BIDI | PR4B  |               |
-| 70/1     | RD[6]               | LOCATED    | LVTTL33_BIDI | PR3D  |               |
-| 71/1     | RD[7]               | LOCATED    | LVTTL33_BIDI | PR3B  |               |
-| 72/1     | nRWE                | LOCATED    | LVTTL33_OUT  | PR2D  |               |
-| 73/1     | nRRAS               | LOCATED    | LVTTL33_OUT  | PR2B  |               |
-| 76/0     | RDQMH               | LOCATED    | LVTTL33_OUT  | PT9F  |               |
-| 77/0     | nRCS                | LOCATED    | LVTTL33_OUT  | PT9E  |               |
-| 78/0     | nRCAS               | LOCATED    | LVTTL33_OUT  | PT9C  |               |
-| 79/0     | RA[11]              | LOCATED    | LVTTL33_OUT  | PT9A  |               |
-| 82/0     | RCKE                | LOCATED    | LVTTL33_OUT  | PT7E  | D7            |
-| 83/0     | RBA[1]              | LOCATED    | LVTTL33_OUT  | PT7A  | D6            |
-| 85/0     | RA[9]               | LOCATED    | LVTTL33_OUT  | PT6B  | PCLKT0_1      |
-| 86/0     | RCLK                | LOCATED    | LVTTL33_IN   | PT5B  | PCLKT0_0      |
-| 87/0     | RA[10]              | LOCATED    | LVTTL33_OUT  | PT5A  |               |
-| 89/0     | RA[1]               | LOCATED    | LVTTL33_OUT  | PT4F  |               |
-| 91/0     | RA[6]               | LOCATED    | LVTTL33_OUT  | PT3F  | D3            |
-| 94/0     | RA[2]               | LOCATED    | LVTTL33_OUT  | PT3B  |               |
-| 95/0     | RA[5]               | LOCATED    | LVTTL33_OUT  | PT3A  |               |
-| 96/0     | RA[8]               | LOCATED    | LVTTL33_OUT  | PT2F  | D2            |
-| 97/0     | RA[3]               | LOCATED    | LVTTL33_OUT  | PT2E  |               |
-| 98/0     | RA[0]               | LOCATED    | LVTTL33_OUT  | PT2B  | D1            |
-| 99/0     | RA[4]               | LOCATED    | LVTTL33_OUT  | PT2C  |               |
-| 100/0    | RA[7]               | LOCATED    | LVTTL33_OUT  | PT2A  |               |
-| PB2A/2   |     unused, PULL:UP |            |              | PB2A  |               |
-| PB2B/2   |     unused, PULL:UP |            |              | PB2B  |               |
-| PB2D/2   |     unused, PULL:UP |            |              | PB2D  |               |
-| PB3A/2   |     unused, PULL:UP |            |              | PB3A  |               |
-| PB3B/2   |     unused, PULL:UP |            |              | PB3B  |               |
-| PB3C/2   |     unused, PULL:UP |            |              | PB3C  |               |
-| PB3D/2   |     unused, PULL:UP |            |              | PB3D  |               |
-| PB4A/2   |     unused, PULL:UP |            |              | PB4A  |               |
-| PB4B/2   |     unused, PULL:UP |            |              | PB4B  |               |
-| PB4D/2   |     unused, PULL:UP |            |              | PB4D  |               |
-| PB4F/2   |     unused, PULL:UP |            |              | PB4F  |               |
-| PB5A/2   |     unused, PULL:UP |            |              | PB5A  |               |
-| PB5C/2   |     unused, PULL:UP |            |              | PB5C  |               |
-| PB6A/2   |     unused, PULL:UP |            |              | PB6A  |               |
-| PB6D/2   |     unused, PULL:UP |            |              | PB6D  |               |
-| PB7A/2   |     unused, PULL:UP |            |              | PB7A  |               |
-| PB7B/2   |     unused, PULL:UP |            |              | PB7B  |               |
-| PB7C/2   |     unused, PULL:UP |            |              | PB7C  |               |
-| PB7D/2   |     unused, PULL:UP |            |              | PB7D  |               |
-| PB7E/2   |     unused, PULL:UP |            |              | PB7E  |               |
-| PB7F/2   |     unused, PULL:UP |            |              | PB7F  |               |
-| PB8A/2   |     unused, PULL:UP |            |              | PB8A  |               |
-| PB9B/2   |     unused, PULL:UP |            |              | PB9B  |               |
-| PB9E/0   |     unused, PULL:UP |            |              | PB9E  |               |
-| PL4B/3   |     unused, PULL:UP |            |              | PL4B  |               |
-| PL5A/3   |     unused, PULL:UP |            |              | PL5A  |               |
-| PL5C/3   |     unused, PULL:UP |            |              | PL5C  |               |
-| PL5D/3   |     unused, PULL:UP |            |              | PL5D  |               |
-| PL6A/3   |     unused, PULL:UP |            |              | PL6A  |               |
-| PL6B/3   |     unused, PULL:UP |            |              | PL6B  |               |
-| PL6C/3   |     unused, PULL:UP |            |              | PL6C  |               |
-| PL6D/3   |     unused, PULL:UP |            |              | PL6D  |               |
-| PL7A/3   |     unused, PULL:UP |            |              | PL7A  |               |
-| PL7C/3   |     unused, PULL:UP |            |              | PL7C  |               |
-| PL7D/3   |     unused, PULL:UP |            |              | PL7D  |               |
-| PL8A/3   |     unused, PULL:UP |            |              | PL8A  |               |
-| PL8B/3   |     unused, PULL:UP |            |              | PL8B  |               |
-| PL9B/3   |     unused, PULL:UP |            |              | PL9B  |               |
-| PL9D/3   |     unused, PULL:UP |            |              | PL9D  |               |
-| PL10B/3  |     unused, PULL:UP |            |              | PL10B |               |
-| PL10D/3  |     unused, PULL:UP |            |              | PL10D |               |
-| PL11B/3  |     unused, PULL:UP |            |              | PL11B |               |
-| PL11D/3  |     unused, PULL:UP |            |              | PL11D |               |
-| PR2A/1   |     unused, PULL:UP |            |              | PR2A  |               |
-| PR2C/1   |     unused, PULL:UP |            |              | PR2C  |               |
-| PR3A/1   |     unused, PULL:UP |            |              | PR3A  |               |
-| PR3C/1   |     unused, PULL:UP |            |              | PR3C  |               |
-| PR4A/1   |     unused, PULL:UP |            |              | PR4A  |               |
-| PR4C/1   |     unused, PULL:UP |            |              | PR4C  |               |
-| PR5A/1   |     unused, PULL:UP |            |              | PR5A  |               |
-| PR5C/1   |     unused, PULL:UP |            |              | PR5C  |               |
-| PR6A/1   |     unused, PULL:UP |            |              | PR6A  |               |
-| PR6D/1   |     unused, PULL:UP |            |              | PR6D  |               |
-| PR7A/1   |     unused, PULL:UP |            |              | PR7A  |               |
-| PR7C/1   |     unused, PULL:UP |            |              | PR7C  |               |
-| PR7D/1   |     unused, PULL:UP |            |              | PR7D  |               |
-| PR8A/1   |     unused, PULL:UP |            |              | PR8A  |               |
-| PR8B/1   |     unused, PULL:UP |            |              | PR8B  |               |
-| PR8C/1   |     unused, PULL:UP |            |              | PR8C  |               |
-| PR8D/1   |     unused, PULL:UP |            |              | PR8D  |               |
-| PR9A/1   |     unused, PULL:UP |            |              | PR9A  |               |
-| PR9C/1   |     unused, PULL:UP |            |              | PR9C  |               |
-| PT2D/0   |     unused, PULL:UP |            |              | PT2D  |               |
-| PT3C/0   |     unused, PULL:UP |            |              | PT3C  |               |
-| PT3D/0   |     unused, PULL:UP |            |              | PT3D  |               |
-| PT3E/0   |     unused, PULL:UP |            |              | PT3E  |               |
-| PT4A/0   |     unused, PULL:UP |            |              | PT4A  |               |
-| PT4B/0   |     unused, PULL:UP |            |              | PT4B  |               |
-| PT4C/0   |     unused, PULL:UP |            |              | PT4C  |               |
-| PT4D/0   |     unused, PULL:UP |            |              | PT4D  |               |
-| PT4E/0   |     unused, PULL:UP |            |              | PT4E  |               |
-| PT5C/0   |     unused, PULL:UP |            |              | PT5C  |               |
-| PT5D/0   |     unused, PULL:UP |            |              | PT5D  |               |
-| PT6A/0   |     unused, PULL:UP |            |              | PT6A  |               |
-| PT6C/0   |     unused, PULL:UP |            |              | PT6C  |               |
-| PT6D/0   |     unused, PULL:UP |            |              | PT6D  |               |
-| PT7B/0   |     unused, PULL:UP |            |              | PT7B  |               |
-| PT7C/0   |     unused, PULL:UP |            |              | PT7C  |               |
-| PT7D/0   |     unused, PULL:UP |            |              | PT7D  |               |
-| PT7F/0   |     unused, PULL:UP |            |              | PT7F  |               |
-| PT8A/0   |     unused, PULL:UP |            |              | PT8A  |               |
-| PT8B/0   |     unused, PULL:UP |            |              | PT8B  |               |
-| PT8C/0   |     unused, PULL:UP |            |              | PT8C  |               |
-| PT8D/0   |     unused, PULL:UP |            |              | PT8D  |               |
-| PT9B/0   |     unused, PULL:UP |            |              | PT9B  |               |
-| PT9D/0   |     unused, PULL:UP |            |              | PT9D  |               |
-| TCK/2    |                     |            |              | TCK   | TCK           |
-| TDI/2    |                     |            |              | TDI   | TDID0         |
-| TDO/2    |                     |            |              | TDO   | TDO           |
-| TMS/2    |                     |            |              | TMS   | TMS           |
-+----------+---------------------+------------+--------------+-------+---------------+
-
-
-List of All Pins' Locate Preferences Based on Final Placement After PAR 
-to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
-
-LOCATE  COMP  "CROW[0]"  SITE  "32";
-LOCATE  COMP  "CROW[1]"  SITE  "34";
-LOCATE  COMP  "Din[0]"  SITE  "21";
-LOCATE  COMP  "Din[1]"  SITE  "15";
-LOCATE  COMP  "Din[2]"  SITE  "14";
-LOCATE  COMP  "Din[3]"  SITE  "16";
-LOCATE  COMP  "Din[4]"  SITE  "18";
-LOCATE  COMP  "Din[5]"  SITE  "17";
-LOCATE  COMP  "Din[6]"  SITE  "20";
-LOCATE  COMP  "Din[7]"  SITE  "19";
-LOCATE  COMP  "Dout[0]"  SITE  "1";
-LOCATE  COMP  "Dout[1]"  SITE  "7";
-LOCATE  COMP  "Dout[2]"  SITE  "8";
-LOCATE  COMP  "Dout[3]"  SITE  "6";
-LOCATE  COMP  "Dout[4]"  SITE  "4";
-LOCATE  COMP  "Dout[5]"  SITE  "5";
-LOCATE  COMP  "Dout[6]"  SITE  "2";
-LOCATE  COMP  "Dout[7]"  SITE  "3";
-LOCATE  COMP  "LED"  SITE  "57";
-LOCATE  COMP  "MAin[0]"  SITE  "23";
-LOCATE  COMP  "MAin[1]"  SITE  "38";
-LOCATE  COMP  "MAin[2]"  SITE  "37";
-LOCATE  COMP  "MAin[3]"  SITE  "47";
-LOCATE  COMP  "MAin[4]"  SITE  "46";
-LOCATE  COMP  "MAin[5]"  SITE  "45";
-LOCATE  COMP  "MAin[6]"  SITE  "49";
-LOCATE  COMP  "MAin[7]"  SITE  "44";
-LOCATE  COMP  "MAin[8]"  SITE  "50";
-LOCATE  COMP  "MAin[9]"  SITE  "51";
-LOCATE  COMP  "PHI2"  SITE  "39";
-LOCATE  COMP  "RA[0]"  SITE  "98";
-LOCATE  COMP  "RA[10]"  SITE  "87";
-LOCATE  COMP  "RA[11]"  SITE  "79";
-LOCATE  COMP  "RA[1]"  SITE  "89";
-LOCATE  COMP  "RA[2]"  SITE  "94";
-LOCATE  COMP  "RA[3]"  SITE  "97";
-LOCATE  COMP  "RA[4]"  SITE  "99";
-LOCATE  COMP  "RA[5]"  SITE  "95";
-LOCATE  COMP  "RA[6]"  SITE  "91";
-LOCATE  COMP  "RA[7]"  SITE  "100";
-LOCATE  COMP  "RA[8]"  SITE  "96";
-LOCATE  COMP  "RA[9]"  SITE  "85";
-LOCATE  COMP  "RBA[0]"  SITE  "63";
-LOCATE  COMP  "RBA[1]"  SITE  "83";
-LOCATE  COMP  "RCKE"  SITE  "82";
-LOCATE  COMP  "RCLK"  SITE  "86";
-LOCATE  COMP  "RDQMH"  SITE  "76";
-LOCATE  COMP  "RDQML"  SITE  "61";
-LOCATE  COMP  "RD[0]"  SITE  "64";
-LOCATE  COMP  "RD[1]"  SITE  "65";
-LOCATE  COMP  "RD[2]"  SITE  "66";
-LOCATE  COMP  "RD[3]"  SITE  "67";
-LOCATE  COMP  "RD[4]"  SITE  "68";
-LOCATE  COMP  "RD[5]"  SITE  "69";
-LOCATE  COMP  "RD[6]"  SITE  "70";
-LOCATE  COMP  "RD[7]"  SITE  "71";
-LOCATE  COMP  "UFMCLK"  SITE  "58";
-LOCATE  COMP  "UFMSDI"  SITE  "56";
-LOCATE  COMP  "UFMSDO"  SITE  "55";
-LOCATE  COMP  "nCCAS"  SITE  "27";
-LOCATE  COMP  "nCRAS"  SITE  "43";
-LOCATE  COMP  "nFWE"  SITE  "22";
-LOCATE  COMP  "nRCAS"  SITE  "78";
-LOCATE  COMP  "nRCS"  SITE  "77";
-LOCATE  COMP  "nRRAS"  SITE  "73";
-LOCATE  COMP  "nRWE"  SITE  "72";
-LOCATE  COMP  "nUFMCS"  SITE  "53";
-
-
-
-
-
-PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Mon Aug 16 21:33:36 2021
-
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diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
deleted file mode 100644
index ec4ec76..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
+++ /dev/null
@@ -1,315 +0,0 @@
-
-Place & Route Report
-
-
-
    PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Mon Aug 16 21:33:31 2021
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
-RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
-RAM2GS_LCMXO640C_impl1.prf -gui -msgset
-C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
-
-
-Preference file: RAM2GS_LCMXO640C_impl1.prf.
-
-Cost Table Summary
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            1.213        0            0.339        0            06           Completed
-* : Design saved.
-
-Total (real) run time for 1-seed: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
-Mon Aug 16 21:33:31 2021
-
-
-Best Par Run
-PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
-Preference file: RAM2GS_LCMXO640C_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-
-Device utilization summary:
-
-   PIO (prelim)      67/159          42% used
-                     67/74           90% bonded
-   SLICE             65/320          20% used
-
-
-
-Number of Signals: 252
-Number of Connections: 618
-
-Pin Constraint Summary:
-   67 out of 67 pins locked (100% locked).
-
-The following 4 signals are selected to use the primary clock routing resources:
-    RCLK_c (driver: RCLK, clk load #: 39)
-    PHI2_c (driver: PHI2, clk load #: 13)
-    nCCAS_c (driver: nCCAS, clk load #: 4)
-    nCRAS_c (driver: nCRAS, clk load #: 7)
-
-No signal is selected as secondary clock.
-
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-.......
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-...............
-Placer score = 1105164.
-Finished Placer Phase 1.  REAL time: 5 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  1103986
-Finished Placer Phase 2.  REAL time: 5 secs 
-
-
-
-Clock Report
-
-Global Clock Resources:
-  CLK_PIN    : 1 out of 4 (25%)
-  General PIO: 3 out of 160 (1%)
-
-Global Clocks:
-  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 39
-  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13
-  PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PB2C)", clk load = 4
-  PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7
-
-  PRIMARY  : 4 out of 4 (100%)
-  SECONDARY: 0 out of 4 (0%)
-
-
-
-
-I/O Usage Summary (final):
-   67 out of 159 (42.1%) PIO sites used.
-   67 out of 74 (90.5%) bonded PIO sites used.
-   Number of PIO comps: 67; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+------------+------------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
-+----------+----------------+------------+------------+------------+
-| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
-| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
-| 2        | 13 / 14 ( 92%) | -          | -          | -          |
-| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
-+----------+----------------+------------+------------+------------+
-
-Total placer CPU time: 5 secs 
-
-Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
-
-0 connections routed; 618 unrouted.
-Starting router resource preassignment
-WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
-WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
-WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
-
-Completed router resource preassignment. Real time: 5 secs 
-
-Start NBR router at 21:33:36 08/16/21
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 21:33:36 08/16/21
-
-Start NBR section for initial routing at 21:33:36 08/16/21
-Level 1, iteration 1
-0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.302ns/0.000ns; real time: 5 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 523(84.63%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.256ns/0.000ns; real time: 5 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 511(82.69%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.228ns/0.000ns; real time: 5 secs 
-Level 4, iteration 1
-16(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 21:33:37 08/16/21
-Level 1, iteration 1
-0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
-Level 2, iteration 1
-0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
-Level 3, iteration 1
-0(0.00%) conflict; 16(2.59%) untouched conns; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 1
-5(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 2
-2(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
-Level 4, iteration 3
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 21:33:37 08/16/21
-
-Start NBR section for re-routing at 21:33:37 08/16/21
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 1.213ns/0.000ns; real time: 6 secs 
-
-Start NBR section for post-routing at 21:33:37 08/16/21
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack<setup> : 1.213ns
-  Timing score<setup> : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-Total CPU time 6 secs 
-Total REAL time: 6 secs 
-Completely routed.
-End of route.  618 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack<setup/<ns>> = 1.213
-PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
-PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.339
-PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 6 secs 
-Total REAL time to completion: 6 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
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diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
deleted file mode 100644
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--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
+++ /dev/null
@@ -1,83 +0,0 @@
-
-Project Summary
-
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    RAM2GS_LCMXO640C project summary
    Module Name:RAM2GS_LCMXO640CSynthesis:Lattice LSE
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO640C-3T100CDevice Family:MachXO
    Device Type:LCMXO640CPackage Type:TQFP100
    Performance grade:3Operating conditions:COM
    Logic preference file:RAM2GS_LCMXO640C.lpf
    Physical Preference file:impl1/RAM2GS_LCMXO640C_impl1.prf
    Product Version:3.12.0.240.2Patch Version:
    Updated:2021/08/16 21:36:37
    Implementation Location:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1
    Project File:C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf
    
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diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
deleted file mode 100644
index bdf2b16..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
+++ /dev/null
@@ -1,2740 +0,0 @@
-
-Lattice Map TRACE Report
-
-
-
    Map TRACE Report
-
-Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:33:31 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1_map.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,3
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:              12.873ns  (21.6% logic, 78.4% route), 7 logic levels.
-
- Constraint Details:
-
-     12.873ns physical path delay SLICE_95 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_95.CLK to    SLICE_95.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1   e 1.441    SLICE_95.Q1 to    SLICE_67.A1 Bank_7
-CTOF_DEL    ---     0.371    SLICE_67.A1 to    SLICE_67.F1 SLICE_67
-ROUTE         1   e 1.441    SLICE_67.F1 to    SLICE_82.C1 n2154
-CTOF_DEL    ---     0.371    SLICE_82.C1 to    SLICE_82.F1 SLICE_82
-ROUTE         1   e 1.441    SLICE_82.F1 to    SLICE_76.B1 n26
-CTOF_DEL    ---     0.371    SLICE_76.B1 to    SLICE_76.F1 SLICE_76
-ROUTE         4   e 1.441    SLICE_76.F1 to    SLICE_89.B0 n1285
-CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
-ROUTE         3   e 1.441    SLICE_89.F0 to    SLICE_18.D1 n2290
-CTOF_DEL    ---     0.371    SLICE_18.D1 to    SLICE_18.F1 SLICE_18
-ROUTE         3   e 1.441    SLICE_18.F1 to    SLICE_90.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371    SLICE_90.C0 to    SLICE_90.F0 SLICE_90
-ROUTE         2   e 1.441    SLICE_90.F0 to    SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   12.873   (21.6% logic, 78.4% route), 7 logic levels.
-
-Report:   26.276ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_76
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_77
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 5.575ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_391  (to RCLK_c +)
-
-   Delay:              10.181ns  (23.7% logic, 76.3% route), 6 logic levels.
-
- Constraint Details:
-
-     10.181ns physical path delay SLICE_7 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560    SLICE_7.CLK to     SLICE_7.Q0 SLICE_7 (from RCLK_c)
-ROUTE         3   e 1.441     SLICE_7.Q0 to    SLICE_78.A0 FS_14
-CTOF_DEL    ---     0.371    SLICE_78.A0 to    SLICE_78.F0 SLICE_78
-ROUTE         3   e 1.441    SLICE_78.F0 to    SLICE_73.B1 n10
-CTOF_DEL    ---     0.371    SLICE_73.B1 to    SLICE_73.F1 SLICE_73
-ROUTE         4   e 0.561    SLICE_73.F1 to    SLICE_73.B0 n2300
-CTOF_DEL    ---     0.371    SLICE_73.B0 to    SLICE_73.F0 SLICE_73
-ROUTE         1   e 1.441    SLICE_73.F0 to    SLICE_75.C0 n11
-CTOF_DEL    ---     0.371    SLICE_75.C0 to    SLICE_75.F0 SLICE_75
-ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_33.D1 n2119
-CTOF_DEL    ---     0.371    SLICE_33.D1 to    SLICE_33.F1 SLICE_33
-ROUTE         1   e 1.441    SLICE_33.F1 to    SLICE_56.CE RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                   10.181   (23.7% logic, 76.3% route), 6 logic levels.
-
-Report:   10.425ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_55 and
-      5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets
-     12.500ns offset RCLK to RA[10] by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_55.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_55.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[9] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
-ROUTE         1   e 1.441    SLICE_88.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[8] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
-ROUTE         1   e 1.441    SLICE_95.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[7] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
-ROUTE         1   e 1.441    SLICE_97.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[6] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
-ROUTE         1   e 1.441    SLICE_98.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[5] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
-ROUTE         1   e 1.441    SLICE_98.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.427ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     6.569ns  (69.5% logic, 30.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets
-     12.500ns offset RCLK to RA[4] by 3.427ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.561    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
-ROUTE         1   e 1.441    SLICE_64.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
-                  --------
-                    6.569   (69.5% logic, 30.5% route), 3 logic levels.
-
-Report:    9.073ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[3] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
-ROUTE         1   e 1.441    SLICE_94.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[2] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
-ROUTE         1   e 1.441    SLICE_95.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[1] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
-ROUTE         1   e 1.441    SLICE_94.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets
-     12.500ns offset RCLK to RA[0] by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
-ROUTE         1   e 1.441    SLICE_92.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_60 and
-      5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRCS by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_60.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_60.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_34 and
-      5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets
-     12.500ns offset RCLK to RCKE by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_34.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4   e 1.441    SLICE_34.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_63 and
-      5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRWE by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_63.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_61 and
-      5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRRAS by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_61.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2   e 1.441    SLICE_61.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     5.637ns  (74.4% logic, 25.6% route), 2 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_58 and
-      5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets
-     12.500ns offset RCLK to nRCAS by 4.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_58.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1   e 1.441    SLICE_58.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
-                  --------
-                    5.637   (74.4% logic, 25.6% route), 2 logic levels.
-
-Report:    8.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets
-     12.500ns offset RCLK to RDQMH by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
-ROUTE         1   e 1.441    SLICE_88.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.547ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     7.449ns  (61.3% logic, 38.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.504ns  (42.5% logic, 57.5% route), 1 logic levels.
-
- Constraint Details:
-      2.504ns delay RCLK to SLICE_64 and
-      7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets
-     12.500ns offset RCLK to RDQML by 2.547ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 1.441       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    2.504   (42.5% logic, 57.5% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 1.441    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
-CTOF_DEL    ---     0.371    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
-ROUTE         1   e 1.441    SLICE_92.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
-                  --------
-                    7.449   (61.3% logic, 38.7% route), 3 logic levels.
-
-Report:    9.953ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    26.276 ns|   7  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|    10.425 ns|   6  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.073 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     8.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.953 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:33:31 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1_map.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.485ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
-
-   Delay:               0.462ns  (56.7% logic, 43.3% route), 2 logic levels.
-
- Constraint Details:
-
-      0.462ns physical path delay SLICE_9 to SLICE_9 meets
-     -0.023ns DIN_HLD and
-      0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170    SLICE_9.CLK to     SLICE_9.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2   e 0.199     SLICE_9.Q0 to     SLICE_9.C0 ADSubmitted
-CTOF_DEL    ---     0.092     SLICE_9.C0 to     SLICE_9.F0 SLICE_9
-ROUTE         1   e 0.001     SLICE_9.F0 to    SLICE_9.DI0 n1361 (to PHI2_c)
-                  --------
-                    0.462   (56.7% logic, 43.3% route), 2 logic levels.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.377ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
-
-   Delay:               0.356ns  (44.1% logic, 55.9% route), 1 logic levels.
-
- Constraint Details:
-
-      0.356ns physical path delay SLICE_72 to SLICE_72 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns
-
- Physical Path Details:
-
-      Data path SLICE_72 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_72.CLK to    SLICE_72.Q0 SLICE_72 (from RCLK_c)
-ROUTE         1   e 0.199    SLICE_72.Q0 to    SLICE_72.M1 n702 (to RCLK_c)
-                  --------
-                    0.356   (44.1% logic, 55.9% route), 1 logic levels.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_55 and
-      1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to RA[10] by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_55.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_55.CLK to    SLICE_55.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_55.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[9] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
-ROUTE         1   e 0.515    SLICE_88.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[8] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_95.C0 to    SLICE_95.F0 SLICE_95
-ROUTE         1   e 0.515    SLICE_95.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[7] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_97.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_97.C0 to    SLICE_97.F0 SLICE_97
-ROUTE         1   e 0.515    SLICE_97.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[6] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_98.C0 to    SLICE_98.F0 SLICE_98
-ROUTE         1   e 0.515    SLICE_98.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[5] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_98.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_98.C1 to    SLICE_98.F1 SLICE_98
-ROUTE         1   e 0.515    SLICE_98.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.850ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     2.071ns  (65.5% logic, 34.5% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets
-      0.000ns hold offset RCLK to RA[4] by 2.850ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.199    SLICE_64.Q0 to    SLICE_64.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_64.C1 to    SLICE_64.F1 SLICE_64
-ROUTE         1   e 0.515    SLICE_64.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
-                  --------
-                    2.071   (65.5% logic, 34.5% route), 3 logic levels.
-
-Report:    2.850ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[3] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_94.C1 to    SLICE_94.F1 SLICE_94
-ROUTE         1   e 0.515    SLICE_94.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[2] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_95.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_95.C1 to    SLICE_95.F1 SLICE_95
-ROUTE         1   e 0.515    SLICE_95.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[1] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_94.C0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_94.C0 to    SLICE_94.F0 SLICE_94
-ROUTE         1   e 0.515    SLICE_94.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RA[0] by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.C1 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_92.C1 to    SLICE_92.F1 SLICE_92
-ROUTE         1   e 0.515    SLICE_92.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_60 and
-      1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRCS by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_60.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_60.CLK to    SLICE_60.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_60.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_34 and
-      1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to RCKE by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_34.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4   e 0.515    SLICE_34.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_63 and
-      1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRWE by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_63.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_63.CLK to    SLICE_63.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_63.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_61 and
-      1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRRAS by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_61.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_61.CLK to    SLICE_61.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2   e 0.515    SLICE_61.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     1.780ns  (71.1% logic, 28.9% route), 2 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_58 and
-      1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets
-      0.000ns hold offset RCLK to nRCAS by 2.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_58.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_58.CLK to    SLICE_58.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1   e 0.515    SLICE_58.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
-                  --------
-                    1.780   (71.1% logic, 28.9% route), 2 logic levels.
-
-Report:    2.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RDQMH by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_88.B0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_88.B0 to    SLICE_88.F0 SLICE_88
-ROUTE         1   e 0.515    SLICE_88.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     2.387ns  (56.8% logic, 43.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.779ns  (33.9% logic, 66.1% route), 1 logic levels.
-
- Constraint Details:
-      0.779ns delay RCLK to SLICE_64 and
-      2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets
-      0.000ns hold offset RCLK to RDQML by 3.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39   e 0.515       86.PADDI to   SLICE_64.CLK RCLK_c
-                  --------
-                    0.779   (33.9% logic, 66.1% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157   SLICE_64.CLK to    SLICE_64.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13   e 0.515    SLICE_64.Q0 to    SLICE_92.B0 nRowColSel
-CTOF_DEL    ---     0.092    SLICE_92.B0 to    SLICE_92.F0 SLICE_92
-ROUTE         1   e 0.515    SLICE_92.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
-                  --------
-                    2.387   (56.8% logic, 43.2% route), 3 logic levels.
-
-Report:    3.166ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.850 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.559 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     3.166 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
-
-
-
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
-
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
deleted file mode 100644
index 1e50adc..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
+++ /dev/null
@@ -1,4571 +0,0 @@
-
-Lattice TRACE Report
-
-
-
    Place & Route TRACE Report
-
-Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:33:37 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,3
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 161.362ns (weighted slack = 322.724ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:              13.373ns  (20.8% logic, 79.2% route), 7 logic levels.
-
- Constraint Details:
-
-     13.373ns physical path delay SLICE_95 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.362ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
-ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   13.373   (20.8% logic, 79.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
-
- Constraint Details:
-
-     13.241ns physical path delay SLICE_95 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.494ns (weighted slack = 322.988ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:              13.241ns  (21.0% logic, 79.0% route), 7 logic levels.
-
- Constraint Details:
-
-     13.241ns physical path delay SLICE_95 to SLICE_88 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.494ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   13.241   (21.0% logic, 79.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.945ns (weighted slack = 323.890ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
-
-   Delay:              12.790ns  (21.8% logic, 78.2% route), 7 logic levels.
-
- Constraint Details:
-
-     12.790ns physical path delay SLICE_95 to SLICE_23 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.945ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
-ROUTE         2     1.089       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   12.790   (21.8% logic, 78.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R6C7B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 161.961ns (weighted slack = 323.922ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
-
-   Delay:              12.774ns  (21.8% logic, 78.2% route), 7 logic levels.
-
- Constraint Details:
-
-     12.774ns physical path delay SLICE_95 to SLICE_96 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 161.961ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7C.C1 to       R5C7C.F1 SLICE_90
-ROUTE         1     1.073       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
-                  --------
-                   12.774   (21.8% logic, 78.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R5C8B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
-
-   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
-
- Constraint Details:
-
-     12.703ns physical path delay SLICE_95 to SLICE_18 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
-CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
-ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
-CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
-ROUTE         2     2.112       R6C9A.F0 to       R5C5A.B0 ADSubmitted_N_234
-CTOF_DEL    ---     0.371       R5C5A.B0 to       R5C5A.F0 SLICE_18
-ROUTE         1     0.000       R5C5A.F0 to      R5C5A.DI0 CmdEnable_N_236 (to PHI2_c)
-                  --------
-                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.123ns (weighted slack = 324.246ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
-
-   Delay:              12.703ns  (21.9% logic, 78.1% route), 7 logic levels.
-
- Constraint Details:
-
-     12.703ns physical path delay SLICE_95 to SLICE_9 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.174ns DIN_SET requirement (totaling 174.826ns) by 162.123ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2B.CLK to       R3C2B.Q1 SLICE_95 (from PHI2_c)
-ROUTE         1     2.044       R3C2B.Q1 to       R4C9C.A1 Bank_7
-CTOF_DEL    ---     0.371       R4C9C.A1 to       R4C9C.F1 SLICE_67
-ROUTE         1     1.905       R4C9C.F1 to       R3C2C.C1 n2154
-CTOF_DEL    ---     0.371       R3C2C.C1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.134       R4C2A.F1 to       R6C9A.B1 n1285
-CTOF_DEL    ---     0.371       R6C9A.B1 to       R6C9A.F1 SLICE_80
-ROUTE         1     0.696       R6C9A.F1 to       R6C9A.B0 n2289
-CTOF_DEL    ---     0.371       R6C9A.B0 to       R6C9A.F0 SLICE_80
-ROUTE         2     2.112       R6C9A.F0 to       R5C5B.B0 ADSubmitted_N_234
-CTOF_DEL    ---     0.371       R5C5B.B0 to       R5C5B.F0 SLICE_9
-ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
-                  --------
-                   12.703   (21.9% logic, 78.1% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R3C2B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R5C5B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.710ns (weighted slack = 325.420ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:              12.025ns  (23.2% logic, 76.8% route), 7 logic levels.
-
- Constraint Details:
-
-     12.025ns physical path delay SLICE_97 to SLICE_19 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.710ns
-
- Physical Path Details:
-
-      Data path SLICE_97 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
-ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
-CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
-ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
-CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7C.C0 to       R5C7C.F0 SLICE_90
-ROUTE         2     1.672       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                   12.025   (23.2% logic, 76.8% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R9C8B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     11.893ns physical path delay SLICE_97 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
-
- Physical Path Details:
-
-      Data path SLICE_97 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
-ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
-CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
-ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
-CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     1.540       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R7C8B.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 162.842ns (weighted slack = 325.684ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:              11.893ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     11.893ns physical path delay SLICE_97 to SLICE_88 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 162.842ns
-
- Physical Path Details:
-
-      Data path SLICE_97 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_97 (from PHI2_c)
-ROUTE         1     1.643       R2C2A.Q1 to       R3C2C.B0 Bank_5
-CTOF_DEL    ---     0.371       R3C2C.B0 to       R3C2C.F0 SLICE_82
-ROUTE         1     0.958       R3C2C.F0 to       R3C2C.A1 n2166
-CTOF_DEL    ---     0.371       R3C2C.A1 to       R3C2C.F1 SLICE_82
-ROUTE         1     1.026       R3C2C.F1 to       R4C2A.A1 n26
-CTOF_DEL    ---     0.371       R4C2A.A1 to       R4C2A.F1 SLICE_76
-ROUTE         4     2.142       R4C2A.F1 to       R5C6A.B0 n1285
-CTOF_DEL    ---     0.371       R5C6A.B0 to       R5C6A.F0 SLICE_89
-ROUTE         3     0.899       R5C6A.F0 to       R5C5A.C1 n2290
-CTOF_DEL    ---     0.371       R5C5A.C1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.899       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     1.540       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   11.893   (23.4% logic, 76.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_97:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R2C2A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to      R4C9A.CLK PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   27.276ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_76
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_77
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 6.557ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               9.262ns  (20.9% logic, 79.1% route), 4 logic levels.
-
- Constraint Details:
-
-      9.262ns physical path delay SLICE_65 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.557ns
-
- Physical Path Details:
-
-      Data path SLICE_65 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
-ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
-CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
-CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    9.262   (20.9% logic, 79.1% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_65:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.573ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S_FSM_i4  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               9.246ns  (20.7% logic, 79.3% route), 4 logic levels.
-
- Constraint Details:
-
-      9.246ns physical path delay SLICE_65 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.573ns
-
- Physical Path Details:
-
-      Data path SLICE_65 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9C.CLK to       R5C9C.Q0 SLICE_65 (from RCLK_c)
-ROUTE         7     2.149       R5C9C.Q0 to       R3C2A.B1 nRowColSel_N_32
-CTOF_DEL    ---     0.371       R3C2A.B1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
-CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    9.246   (20.7% logic, 79.3% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_65:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C9C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.866ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i15  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               8.890ns  (27.2% logic, 72.8% route), 6 logic levels.
-
- Constraint Details:
-
-      8.890ns physical path delay SLICE_7 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 6.866ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q1 SLICE_7 (from RCLK_c)
-ROUTE         3     1.466      R10C7D.Q1 to      R10C8D.B0 FS_15
-CTOF_DEL    ---     0.371      R10C8D.B0 to      R10C8D.F0 SLICE_78
-ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
-CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
-ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
-CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
-ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
-CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
-ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
-CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
-ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.890   (27.2% logic, 72.8% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.963ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               8.856ns  (21.8% logic, 78.2% route), 4 logic levels.
-
- Constraint Details:
-
-      8.856ns physical path delay SLICE_66 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.963ns
-
- Physical Path Details:
-
-      Data path SLICE_66 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
-ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
-CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
-CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    8.856   (21.8% logic, 78.2% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_66:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 6.979ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S_FSM_i3  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               8.840ns  (21.7% logic, 78.3% route), 4 logic levels.
-
- Constraint Details:
-
-      8.840ns physical path delay SLICE_66 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 6.979ns
-
- Physical Path Details:
-
-      Data path SLICE_66 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9D.CLK to       R5C9D.Q0 SLICE_66 (from RCLK_c)
-ROUTE         6     1.743       R5C9D.Q0 to       R3C2A.D1 nRowColSel_N_33
-CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
-CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    8.840   (21.7% logic, 78.3% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_66:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C9D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.065ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i14  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               8.691ns  (27.8% logic, 72.2% route), 6 logic levels.
-
- Constraint Details:
-
-      8.691ns physical path delay SLICE_7 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.065ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560     R10C7D.CLK to      R10C7D.Q0 SLICE_7 (from RCLK_c)
-ROUTE         3     1.267      R10C7D.Q0 to      R10C8D.C0 FS_14
-CTOF_DEL    ---     0.371      R10C8D.C0 to      R10C8D.F0 SLICE_78
-ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
-CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
-ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
-CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
-ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
-CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
-ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
-CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
-ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.691   (27.8% logic, 72.2% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to     R10C7D.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.284ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i13  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               8.472ns  (28.5% logic, 71.5% route), 6 logic levels.
-
- Constraint Details:
-
-      8.472ns physical path delay SLICE_8 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.284ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q1 SLICE_8 (from RCLK_c)
-ROUTE         3     1.048      R10C7C.Q1 to      R10C8D.A0 FS_13
-CTOF_DEL    ---     0.371      R10C8D.A0 to      R10C8D.F0 SLICE_78
-ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
-CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
-ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
-CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
-ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
-CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
-ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
-CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
-ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.472   (28.5% logic, 71.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.601ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_577__i12  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_392  (to RCLK_c +)
-
-   Delay:               8.155ns  (29.6% logic, 70.4% route), 6 logic levels.
-
- Constraint Details:
-
-      8.155ns physical path delay SLICE_8 to SLICE_89 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.601ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560     R10C7C.CLK to      R10C7C.Q0 SLICE_8 (from RCLK_c)
-ROUTE         3     0.731      R10C7C.Q0 to      R10C8D.D0 FS_12
-CTOF_DEL    ---     0.371      R10C8D.D0 to      R10C8D.F0 SLICE_78
-ROUTE         3     1.117      R10C8D.F0 to       R9C8A.B1 n10
-CTOF_DEL    ---     0.371       R9C8A.B1 to       R9C8A.F1 SLICE_73
-ROUTE         4     0.727       R9C8A.F1 to       R9C8A.B0 n2300
-CTOF_DEL    ---     0.371       R9C8A.B0 to       R9C8A.F0 SLICE_73
-ROUTE         1     0.626       R9C8A.F0 to       R9C8D.D0 n11
-CTOF_DEL    ---     0.371       R9C8D.D0 to       R9C8D.F0 SLICE_75
-ROUTE         2     0.513       R9C8D.F0 to       R9C8D.C1 n2119
-CTOF_DEL    ---     0.371       R9C8D.C1 to       R9C8D.F1 SLICE_75
-ROUTE         1     2.026       R9C8D.F1 to       R5C6A.CE RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.155   (29.6% logic, 70.4% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to     R10C7C.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_89:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R5C6A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.732ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               8.087ns  (23.9% logic, 76.1% route), 4 logic levels.
-
- Constraint Details:
-
-      8.087ns physical path delay SLICE_61 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.732ns
-
- Physical Path Details:
-
-      Data path SLICE_61 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
-CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B0 n50
-CTOOFX_DEL  ---     0.631       R8C9D.B0 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    8.087   (23.9% logic, 76.1% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 7.748ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    FF         Data in        nRRAS_370  (to RCLK_c +)
-
-   Delay:               8.071ns  (23.8% logic, 76.2% route), 4 logic levels.
-
- Constraint Details:
-
-      8.071ns physical path delay SLICE_61 to SLICE_61 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.181ns DIN_SET requirement (totaling 15.819ns) by 7.748ns
-
- Physical Path Details:
-
-      Data path SLICE_61 to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     0.974       R3C2A.Q0 to       R3C2A.A1 nRRAS_c
-CTOF_DEL    ---     0.371       R3C2A.A1 to       R3C2A.F1 SLICE_61
-ROUTE         2     2.624       R3C2A.F1 to       R8C9D.B1 n50
-CTOOFX_DEL  ---     0.615       R8C9D.B1 to     R8C9D.OFX0 i1912/SLICE_70
-ROUTE         1     2.556     R8C9D.OFX0 to       R3C2A.A0 n2244
-CTOF_DEL    ---     0.371       R3C2A.A0 to       R3C2A.F0 SLICE_61
-ROUTE         1     0.000       R3C2A.F0 to      R3C2A.DI0 n33 (to RCLK_c)
-                  --------
-                    8.071   (23.8% logic, 76.2% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:    9.443ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_55 and
-      5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
-     12.500ns offset RCLK to RA[10] by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R2C5A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     0.817       R2C5A.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.088ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     7.924ns  (57.6% logic, 42.4% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.924ns delay SLICE_64 to RA[9] (totaling 10.412ns) meets
-     12.500ns offset RCLK to RA[9] by 2.088ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D1 nRowColSel
-CTOF_DEL    ---     0.371       R4C9A.D1 to       R4C9A.F1 SLICE_88
-ROUTE         1     2.564       R4C9A.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
-                  --------
-                    7.924   (57.6% logic, 42.4% route), 3 logic levels.
-
-Report:   10.412ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.035ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     7.977ns  (57.3% logic, 42.7% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.977ns delay SLICE_64 to RA[8] (totaling 10.465ns) meets
-     12.500ns offset RCLK to RA[8] by 2.035ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D0 nRowColSel
-CTOF_DEL    ---     0.371       R3C2B.D0 to       R3C2B.F0 SLICE_95
-ROUTE         1     1.660       R3C2B.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
-                  --------
-                    7.977   (57.3% logic, 42.7% route), 3 logic levels.
-
-Report:   10.465ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.583ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     7.429ns  (61.5% logic, 38.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.429ns delay SLICE_64 to RA[7] (totaling 9.917ns) meets
-     12.500ns offset RCLK to RA[7] by 2.583ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     2.045       R5C9A.Q0 to       R2C2A.C0 nRowColSel
-CTOF_DEL    ---     0.371       R2C2A.C0 to       R2C2A.F0 SLICE_97
-ROUTE         1     0.817       R2C2A.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
-                  --------
-                    7.429   (61.5% logic, 38.5% route), 3 logic levels.
-
-Report:    9.917ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.846ns delay SLICE_64 to RA[6] (totaling 10.334ns) meets
-     12.500ns offset RCLK to RA[6] by 2.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D0 nRowColSel
-CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_98
-ROUTE         1     1.526       R2C3A.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
-                  --------
-                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
-
-Report:   10.334ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.166ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     7.846ns  (58.2% logic, 41.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.846ns delay SLICE_64 to RA[5] (totaling 10.334ns) meets
-     12.500ns offset RCLK to RA[5] by 2.166ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.753       R5C9A.Q0 to       R2C3A.D1 nRowColSel
-CTOF_DEL    ---     0.371       R2C3A.D1 to       R2C3A.F1 SLICE_98
-ROUTE         1     1.526       R2C3A.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
-                  --------
-                    7.846   (58.2% logic, 41.8% route), 3 logic levels.
-
-Report:   10.334ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.742ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     8.270ns  (55.2% logic, 44.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.270ns delay SLICE_64 to RA[4] (totaling 10.758ns) meets
-     12.500ns offset RCLK to RA[4] by 1.742ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.702       R5C9A.Q0 to       R5C9A.D1 nRowColSel
-CTOF_DEL    ---     0.371       R5C9A.D1 to       R5C9A.F1 SLICE_64
-ROUTE         1     3.001       R5C9A.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
-                  --------
-                    8.270   (55.2% logic, 44.8% route), 3 logic levels.
-
-Report:   10.758ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.725ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     8.287ns  (55.1% logic, 44.9% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.287ns delay SLICE_64 to RA[3] (totaling 10.775ns) meets
-     12.500ns offset RCLK to RA[3] by 1.725ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     2.198       R5C9A.Q0 to       R2C2C.D1 nRowColSel
-CTOF_DEL    ---     0.371       R2C2C.D1 to       R2C2C.F1 SLICE_94
-ROUTE         1     1.522       R2C2C.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
-                  --------
-                    8.287   (55.1% logic, 44.9% route), 3 logic levels.
-
-Report:   10.775ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.643ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     8.369ns  (54.6% logic, 45.4% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.369ns delay SLICE_64 to RA[2] (totaling 10.857ns) meets
-     12.500ns offset RCLK to RA[2] by 1.643ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.750       R5C9A.Q0 to       R3C2B.D1 nRowColSel
-CTOF_DEL    ---     0.371       R3C2B.D1 to       R3C2B.F1 SLICE_95
-ROUTE         1     2.052       R3C2B.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
-                  --------
-                    8.369   (54.6% logic, 45.4% route), 3 logic levels.
-
-Report:   10.857ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.417ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     8.595ns  (53.1% logic, 46.9% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.595ns delay SLICE_64 to RA[1] (totaling 11.083ns) meets
-     12.500ns offset RCLK to RA[1] by 1.417ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     2.045       R5C9A.Q0 to       R2C2C.C0 nRowColSel
-CTOF_DEL    ---     0.371       R2C2C.C0 to       R2C2C.F0 SLICE_94
-ROUTE         1     1.983       R2C2C.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
-                  --------
-                    8.595   (53.1% logic, 46.9% route), 3 logic levels.
-
-Report:   11.083ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.213ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     8.799ns  (51.9% logic, 48.1% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.799ns delay SLICE_64 to RA[0] (totaling 11.287ns) meets
-     12.500ns offset RCLK to RA[0] by 1.213ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D1 nRowColSel
-CTOF_DEL    ---     0.371       R8C9C.D1 to       R8C9C.F1 SLICE_92
-ROUTE         1     2.987       R8C9C.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
-                  --------
-                    8.799   (51.9% logic, 48.1% route), 3 logic levels.
-
-Report:   11.287ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_60 and
-      5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
-     12.500ns offset RCLK to nRCS by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R2C9C.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.817       R2C9C.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_34 and
-      5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
-     12.500ns offset RCLK to RCKE by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R2C7C.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     0.817       R2C7C.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.359ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     6.653ns  (63.1% logic, 36.9% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_63 and
-      6.653ns delay SLICE_63 to nRWE (totaling 9.141ns) meets
-     12.500ns offset RCLK to nRWE by 3.359ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to     R10C9C.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     2.457      R10C9C.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
-                  --------
-                    6.653   (63.1% logic, 36.9% route), 2 logic levels.
-
-Report:    9.141ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.325ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     6.687ns  (62.7% logic, 37.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_61 and
-      6.687ns delay SLICE_61 to nRRAS (totaling 9.175ns) meets
-     12.500ns offset RCLK to nRRAS by 3.325ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     2.491       R3C2A.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
-                  --------
-                    6.687   (62.7% logic, 37.3% route), 2 logic levels.
-
-Report:    9.175ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_58 and
-      5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
-     12.500ns offset RCLK to nRCAS by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R2C9B.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     0.817       R2C9B.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.669ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     7.343ns  (62.2% logic, 37.8% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.343ns delay SLICE_64 to RDQMH (totaling 9.831ns) meets
-     12.500ns offset RCLK to RDQMH by 2.669ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.793       R5C9A.Q0 to       R4C9A.D0 nRowColSel
-CTOF_DEL    ---     0.371       R4C9A.D0 to       R4C9A.F0 SLICE_88
-ROUTE         1     1.983       R4C9A.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
-                  --------
-                    7.343   (62.2% logic, 37.8% route), 3 logic levels.
-
-Report:    9.831ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.383ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     6.629ns  (68.9% logic, 31.1% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      6.629ns delay SLICE_64 to RDQML (totaling 9.117ns) meets
-     12.500ns offset RCLK to RDQML by 3.383ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.245       R5C9A.Q0 to       R8C9C.D0 nRowColSel
-CTOF_DEL    ---     0.371       R8C9C.D0 to       R8C9C.F0 SLICE_92
-ROUTE         1     0.817       R8C9C.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
-                  --------
-                    6.629   (68.9% logic, 31.1% route), 3 logic levels.
-
-Report:    9.117ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    27.276 ns|   7  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     9.443 ns|   4  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.412 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.465 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.917 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.334 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.758 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.775 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    10.857 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    11.083 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|    11.287 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.141 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.175 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.831 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |    12.500 ns|     9.117 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 21:33:37 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
-Design file:     ram2gs_lcmxo640c_impl1.ncd
-Preference file: ram2gs_lcmxo640c_impl1.prf
-Device,speed:    LCMXO640C,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • PERIOD NET "PHI2_c" 350.000000 ns  (0 errors)
    •             113 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCCAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "nCRAS_c" 350.000000 ns  (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • PERIOD NET "RCLK_c" 16.000000 ns  (0 errors)
    •             395 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             1 item scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            113 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.447ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted_380  (to PHI2_c -)
-
-   Delay:               0.424ns  (61.8% logic, 38.2% route), 2 logic levels.
-
- Constraint Details:
-
-      0.424ns physical path delay SLICE_9 to SLICE_9 meets
-     -0.023ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.023ns) by 0.447ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.162       R5C5B.Q0 to       R5C5B.A0 ADSubmitted
-CTOF_DEL    ---     0.092       R5C5B.A0 to       R5C5B.F0 SLICE_9
-ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 n1361 (to PHI2_c)
-                  --------
-                    0.424   (61.8% logic, 38.2% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.113ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        XOR8MEG_381  (to PHI2_c -)
-
-   Delay:               1.084ns  (32.7% logic, 67.3% route), 3 logic levels.
-
- Constraint Details:
-
-      1.084ns physical path delay SLICE_18 to SLICE_96 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.113ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
-CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C1 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C7C.C1 to       R5C7C.F1 SLICE_90
-ROUTE         1     0.267       R5C7C.F1 to       R5C8B.CE PHI2_N_114_enable_2 (to PHI2_c)
-                  --------
-                    1.084   (32.7% logic, 67.3% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.118ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        Cmdn8MEGEN_383  (to PHI2_c -)
-
-   Delay:               1.089ns  (32.5% logic, 67.5% route), 3 logic levels.
-
- Constraint Details:
-
-      1.089ns physical path delay SLICE_18 to SLICE_23 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.118ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
-CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
-ROUTE         2     0.272       R5C7C.F0 to       R6C7B.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                    1.089   (32.5% logic, 67.5% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R6C7B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.238ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMCS_385  (to PHI2_c -)
-                   FF                        CmdUFMCLK_386
-
-   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
-
- Constraint Details:
-
-      1.209ns physical path delay SLICE_18 to SLICE_83 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
-CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     0.392       R5C7A.F0 to       R7C8B.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R7C8B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.238ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:               1.209ns  (29.3% logic, 70.7% route), 3 logic levels.
-
- Constraint Details:
-
-      1.209ns physical path delay SLICE_18 to SLICE_88 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.238ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
-CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.225       R5C5A.F1 to       R5C7A.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C7A.C0 to       R5C7A.F0 SLICE_72
-ROUTE         2     0.392       R5C7A.F0 to       R4C9A.CE PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                    1.209   (29.3% logic, 70.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_88:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R4C9A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.270ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_380  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
-
-   Delay:               1.241ns  (35.9% logic, 64.1% route), 4 logic levels.
-
- Constraint Details:
-
-      1.241ns physical path delay SLICE_9 to SLICE_18 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.270ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5B.CLK to       R5C5B.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.258       R5C5B.Q0 to       R5C5B.B1 ADSubmitted
-CTOF_DEL    ---     0.092       R5C5B.B1 to       R5C5B.F1 SLICE_9
-ROUTE         1     0.123       R5C5B.F1 to       R5C5D.C1 n2080
-CTOF_DEL    ---     0.092       R5C5D.C1 to       R5C5D.F1 SLICE_77
-ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
-CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
-ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
-                  --------
-                    1.241   (35.9% logic, 64.1% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.276ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_378  (from PHI2_c -)
-   Destination:    FF         Data in        CmdSubmitted_384  (to PHI2_c -)
-
-   Delay:               1.247ns  (28.4% logic, 71.6% route), 3 logic levels.
-
- Constraint Details:
-
-      1.247ns physical path delay SLICE_18 to SLICE_19 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.276ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5A.CLK to       R5C5A.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.238       R5C5A.Q0 to       R5C5A.A1 CmdEnable
-CTOF_DEL    ---     0.092       R5C5A.A1 to       R5C5A.F1 SLICE_18
-ROUTE         3     0.225       R5C5A.F1 to       R5C7C.C0 XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C7C.C0 to       R5C7C.F0 SLICE_90
-ROUTE         2     0.430       R5C7C.F0 to       R9C8B.CE PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                    1.247   (28.4% logic, 71.6% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R9C8B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 1.299ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted_379  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_378  (to PHI2_c -)
-
-   Delay:               1.270ns  (35.1% logic, 64.9% route), 4 logic levels.
-
- Constraint Details:
-
-      1.270ns physical path delay SLICE_14 to SLICE_18 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.299ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C5C.CLK to       R5C5C.Q0 SLICE_14 (from PHI2_c)
-ROUTE         1     0.238       R5C5C.Q0 to       R5C5C.A1 C1Submitted
-CTOF_DEL    ---     0.092       R5C5C.A1 to       R5C5C.F1 SLICE_14
-ROUTE         1     0.172       R5C5C.F1 to       R5C5D.B1 n2098
-CTOF_DEL    ---     0.092       R5C5D.B1 to       R5C5D.F1 SLICE_77
-ROUTE         1     0.253       R5C5D.F1 to       R5C5D.B0 n2286
-CTOF_DEL    ---     0.092       R5C5D.B0 to       R5C5D.F0 SLICE_77
-ROUTE         1     0.161       R5C5D.F0 to       R5C5A.CE PHI2_N_114_enable_8 (to PHI2_c)
-                  --------
-                    1.270   (35.1% logic, 64.9% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 175.790ns (weighted slack = 351.580ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              XOR8MEG_381  (from PHI2_c -)
-   Destination:    FF         Data in        RA11_358  (to PHI2_c +)
-
-   Delay:               0.779ns  (33.6% logic, 66.4% route), 2 logic levels.
-
- Constraint Details:
-
-      0.779ns physical path delay SLICE_96 to SLICE_31 meets
-     -0.011ns DIN_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.011ns) by 175.790ns
-
- Physical Path Details:
-
-      Data path SLICE_96 to SLICE_31:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R5C8B.CLK to       R5C8B.Q0 SLICE_96 (from PHI2_c)
-ROUTE         1     0.517       R5C8B.Q0 to       R2C9A.B0 XOR8MEG
-CTOF_DEL    ---     0.092       R2C9A.B0 to       R2C9A.F0 SLICE_31
-ROUTE         1     0.000       R2C9A.F0 to      R2C9A.DI0 RA11_N_180 (to PHI2_c)
-                  --------
-                    0.779   (33.6% logic, 66.4% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C8B.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_31:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R2C9A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 176.484ns (weighted slack = 352.968ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i3  (from PHI2_c +)
-   Destination:    FF         Data in        C1Submitted_379  (to PHI2_c -)
-
-   Delay:               1.455ns  (23.4% logic, 76.6% route), 3 logic levels.
-
- Constraint Details:
-
-      1.455ns physical path delay SLICE_98 to SLICE_14 meets
-     -0.029ns CE_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.029ns) by 176.484ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C3A.CLK to       R2C3A.Q1 SLICE_98 (from PHI2_c)
-ROUTE         1     0.382       R2C3A.Q1 to       R4C2A.B1 Bank_3
-CTOF_DEL    ---     0.092       R4C2A.B1 to       R4C2A.F1 SLICE_76
-ROUTE         4     0.556       R4C2A.F1 to       R5C6A.B1 n1285
-CTOF_DEL    ---     0.092       R5C6A.B1 to       R5C6A.F1 SLICE_89
-ROUTE         1     0.176       R5C6A.F1 to       R5C5C.CE PHI2_N_114_enable_1 (to PHI2_c)
-                  --------
-                    1.455   (23.4% logic, 76.6% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R2C3A.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to      R5C5C.CLK PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            395 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i11  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i12  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_72 to SLICE_72 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_72 to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q0 SLICE_72 (from RCLK_c)
-ROUTE         1     0.161       R5C7A.Q0 to       R5C7A.M1 n702 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_72 to SLICE_90 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_72 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C7A.CLK to       R5C7A.Q1 SLICE_72 (from RCLK_c)
-ROUTE         1     0.161       R5C7A.Q1 to       R5C7C.M0 n701 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_72:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i7  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i8  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_73 to SLICE_73 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_73 to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R9C8A.CLK to       R9C8A.Q0 SLICE_73 (from RCLK_c)
-ROUTE         1     0.161       R9C8A.Q0 to       R9C8A.M1 n706 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_74 to SLICE_74 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_74 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C6C.CLK to       R5C6C.Q0 SLICE_74 (from RCLK_c)
-ROUTE         1     0.161       R5C6C.Q0 to       R5C6C.M1 n710 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_75 to SLICE_73 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_75 to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q1 SLICE_75 (from RCLK_c)
-ROUTE         1     0.161       R9C8D.Q1 to       R9C8A.M0 n707 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_73:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8A.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i5  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i6  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_75 to SLICE_75 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_75 to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R9C8D.CLK to       R9C8D.Q0 SLICE_75 (from RCLK_c)
-ROUTE         1     0.161       R9C8D.Q0 to       R9C8D.M1 n708 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_75:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R9C8D.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              PHI2r_349  (from RCLK_c +)
-   Destination:    FF         Data in        PHI2r2_350  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_85 to SLICE_78 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_85 to SLICE_78:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157     R10C8C.CLK to      R10C8C.Q1 SLICE_85 (from RCLK_c)
-ROUTE         1     0.161      R10C8C.Q1 to      R10C8D.M1 PHI2r (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_78:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_87 to SLICE_74 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_87 to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C6B.CLK to       R5C6B.Q1 SLICE_87 (from RCLK_c)
-ROUTE         1     0.161       R5C6B.Q1 to       R5C6C.M0 n711 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_87:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C6B.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_74:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C6C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.339ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i13  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i14  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_90 to SLICE_90 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_90 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C7C.CLK to       R5C7C.Q0 SLICE_90 (from RCLK_c)
-ROUTE         1     0.161       R5C7C.Q0 to       R5C7C.M1 n700 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to      R5C7C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.345ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              PHI2r2_350  (from RCLK_c +)
-   Destination:    FF         Data in        PHI2r3_351  (to RCLK_c +)
-
-   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.324ns physical path delay SLICE_78 to SLICE_85 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
-
- Physical Path Details:
-
-      Data path SLICE_78 to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157     R10C8D.CLK to      R10C8D.Q1 SLICE_78 (from RCLK_c)
-ROUTE         3     0.167      R10C8D.Q1 to      R10C8C.M0 PHI2r2 (to RCLK_c)
-                  --------
-                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_78:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to     R10C8D.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to     R10C8C.CLK RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_373  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_55 and
-      1.462ns delay SLICE_55 to RA[10] (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to RA[10] by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C5A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     0.197       R2C5A.Q0 to       87.PADDO n980
-DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.668ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     2.181ns  (62.2% logic, 37.8% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.181ns delay SLICE_64 to RA[9] (totaling 2.668ns) meets
-      0.000ns hold offset RCLK to RA[9] by 2.668ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D1 nRowColSel
-CTOF_DEL    ---     0.092       R4C9A.D1 to       R4C9A.F1 SLICE_88
-ROUTE         1     0.625       R4C9A.F1 to       85.PADDO RA_c_9
-DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
-                  --------
-                    2.181   (62.2% logic, 37.8% route), 3 logic levels.
-
-Report:    2.668ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.689ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     2.202ns  (61.6% logic, 38.4% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.202ns delay SLICE_64 to RA[8] (totaling 2.689ns) meets
-      0.000ns hold offset RCLK to RA[8] by 2.689ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D0 nRowColSel
-CTOF_DEL    ---     0.092       R3C2B.D0 to       R3C2B.F0 SLICE_95
-ROUTE         1     0.394       R3C2B.F0 to       96.PADDO RA_c_8
-DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
-                  --------
-                    2.202   (61.6% logic, 38.4% route), 3 logic levels.
-
-Report:    2.689ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.572ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     2.085ns  (65.1% logic, 34.9% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.085ns delay SLICE_64 to RA[7] (totaling 2.572ns) meets
-      0.000ns hold offset RCLK to RA[7] by 2.572ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.531       R5C9A.Q0 to       R2C2A.C0 nRowColSel
-CTOF_DEL    ---     0.092       R2C2A.C0 to       R2C2A.F0 SLICE_97
-ROUTE         1     0.197       R2C2A.F0 to      100.PADDO RA_c_7
-DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
-                  --------
-                    2.085   (65.1% logic, 34.9% route), 3 logic levels.
-
-Report:    2.572ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.652ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.165ns delay SLICE_64 to RA[6] (totaling 2.652ns) meets
-      0.000ns hold offset RCLK to RA[6] by 2.652ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D0 nRowColSel
-CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_98
-ROUTE         1     0.356       R2C3A.F0 to       91.PADDO RA_c_6
-DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
-                  --------
-                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
-
-Report:    2.652ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.652ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     2.165ns  (62.7% logic, 37.3% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.165ns delay SLICE_64 to RA[5] (totaling 2.652ns) meets
-      0.000ns hold offset RCLK to RA[5] by 2.652ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.452       R5C9A.Q0 to       R2C3A.D1 nRowColSel
-CTOF_DEL    ---     0.092       R2C3A.D1 to       R2C3A.F1 SLICE_98
-ROUTE         1     0.356       R2C3A.F1 to       95.PADDO RA_c_5
-DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
-                  --------
-                    2.165   (62.7% logic, 37.3% route), 3 logic levels.
-
-Report:    2.652ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.776ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     2.289ns  (59.3% logic, 40.7% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.289ns delay SLICE_64 to RA[4] (totaling 2.776ns) meets
-      0.000ns hold offset RCLK to RA[4] by 2.776ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.178       R5C9A.Q0 to       R5C9A.D1 nRowColSel
-CTOF_DEL    ---     0.092       R5C9A.D1 to       R5C9A.F1 SLICE_64
-ROUTE         1     0.754       R5C9A.F1 to       99.PADDO RA_c_4
-DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
-                  --------
-                    2.289   (59.3% logic, 40.7% route), 3 logic levels.
-
-Report:    2.776ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.772ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     2.285ns  (59.4% logic, 40.6% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.285ns delay SLICE_64 to RA[3] (totaling 2.772ns) meets
-      0.000ns hold offset RCLK to RA[3] by 2.772ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.571       R5C9A.Q0 to       R2C2C.D1 nRowColSel
-CTOF_DEL    ---     0.092       R2C2C.D1 to       R2C2C.F1 SLICE_94
-ROUTE         1     0.357       R2C2C.F1 to       97.PADDO RA_c_3
-DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
-                  --------
-                    2.285   (59.4% logic, 40.6% route), 3 logic levels.
-
-Report:    2.772ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.787ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     2.300ns  (59.0% logic, 41.0% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.300ns delay SLICE_64 to RA[2] (totaling 2.787ns) meets
-      0.000ns hold offset RCLK to RA[2] by 2.787ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.451       R5C9A.Q0 to       R3C2B.D1 nRowColSel
-CTOF_DEL    ---     0.092       R3C2B.D1 to       R3C2B.F1 SLICE_95
-ROUTE         1     0.492       R3C2B.F1 to       94.PADDO RA_c_2
-DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
-                  --------
-                    2.300   (59.0% logic, 41.0% route), 3 logic levels.
-
-Report:    2.787ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.855ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     2.368ns  (57.3% logic, 42.7% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.368ns delay SLICE_64 to RA[1] (totaling 2.855ns) meets
-      0.000ns hold offset RCLK to RA[1] by 2.855ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.531       R5C9A.Q0 to       R2C2C.C0 nRowColSel
-CTOF_DEL    ---     0.092       R2C2C.C0 to       R2C2C.F0 SLICE_94
-ROUTE         1     0.480       R2C2C.F0 to       89.PADDO RA_c_1
-DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
-                  --------
-                    2.368   (57.3% logic, 42.7% route), 3 logic levels.
-
-Report:    2.855ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.893ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     2.406ns  (56.4% logic, 43.6% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.406ns delay SLICE_64 to RA[0] (totaling 2.893ns) meets
-      0.000ns hold offset RCLK to RA[0] by 2.893ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D1 nRowColSel
-CTOF_DEL    ---     0.092       R8C9C.D1 to       R8C9C.F1 SLICE_92
-ROUTE         1     0.739       R8C9C.F1 to       98.PADDO RA_c_0
-DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
-                  --------
-                    2.406   (56.4% logic, 43.6% route), 3 logic levels.
-
-Report:    2.893ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_369  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_60 and
-      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to nRCS by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C9C.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.197       R2C9C.Q0 to       77.PADDO nRCS_c
-DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_368  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_34 and
-      1.462ns delay SLICE_34 to RCKE (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to RCKE by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C7C.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     0.197       R2C7C.Q0 to       82.PADDO RCKE_c
-DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.356ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_372  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     1.869ns  (67.7% logic, 32.3% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_63 and
-      1.869ns delay SLICE_63 to nRWE (totaling 2.356ns) meets
-      0.000ns hold offset RCLK to nRWE by 2.356ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to     R10C9C.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157     R10C9C.CLK to      R10C9C.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     0.604      R10C9C.Q0 to       72.PADDO nRWE_c
-DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
-                  --------
-                    1.869   (67.7% logic, 32.3% route), 2 logic levels.
-
-Report:    2.356ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.363ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_370  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     1.876ns  (67.4% logic, 32.6% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_61 and
-      1.876ns delay SLICE_61 to nRRAS (totaling 2.363ns) meets
-      0.000ns hold offset RCLK to nRRAS by 2.363ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R3C2A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R3C2A.CLK to       R3C2A.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     0.611       R3C2A.Q0 to       73.PADDO nRRAS_c
-DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
-                  --------
-                    1.876   (67.4% logic, 32.6% route), 2 logic levels.
-
-Report:    2.363ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_371  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_58 and
-      1.462ns delay SLICE_58 to nRCAS (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to nRCAS by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R2C9B.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     0.197       R2C9B.Q0 to       78.PADDO nRCAS_c
-DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.523ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     2.036ns  (66.7% logic, 33.3% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.036ns delay SLICE_64 to RDQMH (totaling 2.523ns) meets
-      0.000ns hold offset RCLK to RDQMH by 2.523ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.199       R5C9A.Q0 to       R4C9A.D0 nRowColSel
-CTOF_DEL    ---     0.092       R4C9A.D0 to       R4C9A.F0 SLICE_88
-ROUTE         1     0.480       R4C9A.F0 to       76.PADDO RDQMH_c
-DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
-                  --------
-                    2.036   (66.7% logic, 33.3% route), 3 logic levels.
-
-Report:    2.523ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.351ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_375  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     1.864ns  (72.8% logic, 27.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      1.864ns delay SLICE_64 to RDQML (totaling 2.351ns) meets
-      0.000ns hold offset RCLK to RDQML by 2.351ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to      R5C9A.CLK RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R5C9A.CLK to       R5C9A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.310       R5C9A.Q0 to       R8C9C.D0 nRowColSel
-CTOF_DEL    ---     0.092       R8C9C.D0 to       R8C9C.F0 SLICE_92
-ROUTE         1     0.197       R8C9C.F0 to       61.PADDO RDQML_c
-DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
-                  --------
-                    1.864   (72.8% logic, 27.2% route), 3 logic levels.
-
-Report:    2.351ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.668 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.689 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.572 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.652 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.776 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.772 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.787 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.855 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.893 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.356 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.363 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.523 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.351 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 526 paths, 6 nets, and 444 connections (71.84% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
-
-
-
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
-
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_drc.log b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_drc.log
deleted file mode 100644
index 7932ec0..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_drc.log
+++ /dev/null
@@ -1,15 +0,0 @@
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-
-
-Running DRC...
-
-DRC complete with no errors or warnings
-
-Design Results:
-    304 blocks expanded
-completed the first expansion
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO640C_impl1.ngd.
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_lse.twr b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_lse.twr
deleted file mode 100644
index 0779fdc..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_lse.twr
+++ /dev/null
@@ -1,311 +0,0 @@
---------------------------------------------------------------------------------
-Lattice Synthesis Timing Report, Version  
-Mon Aug 16 21:33:30 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Design:     RAM2GS
-Constraint file:  
-Report level:    verbose report, limited to 3 items per constraint
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
-            122 items scored, 121 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 10.378ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdUFMCS_385  (to PHI2_c -)
-
-   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
-      2.500ns delay constraint less
-      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
-
- Path Details: Bank_i5 to CmdUFMCS_385
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
-Route         1   e 1.220                                  Bank[5]
-LUT4        ---     0.390              B to Z              i1856_4_lut
-Route         1   e 1.220                                  n2166
-LUT4        ---     0.390              B to Z              i12_4_lut
-Route         1   e 1.220                                  n26
-LUT4        ---     0.390              B to Z              i13_4_lut
-Route         4   e 1.552                                  n1285
-LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
-Route         3   e 1.483                                  n2290
-LUT4        ---     0.390              D to Z              i3_4_lut
-Route         3   e 1.483                                  XOR8MEG_N_112
-LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
-Route         3   e 1.483                                  PHI2_N_114_enable_7
-                  --------
-                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
-
-
-Error:  The following path violates requirements by 10.378ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
-      2.500ns delay constraint less
-      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
-
- Path Details: Bank_i5 to CmdUFMSDI_387
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
-Route         1   e 1.220                                  Bank[5]
-LUT4        ---     0.390              B to Z              i1856_4_lut
-Route         1   e 1.220                                  n2166
-LUT4        ---     0.390              B to Z              i12_4_lut
-Route         1   e 1.220                                  n26
-LUT4        ---     0.390              B to Z              i13_4_lut
-Route         4   e 1.552                                  n1285
-LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
-Route         3   e 1.483                                  n2290
-LUT4        ---     0.390              D to Z              i3_4_lut
-Route         3   e 1.483                                  XOR8MEG_N_112
-LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
-Route         3   e 1.483                                  PHI2_N_114_enable_7
-                  --------
-                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
-
-
-Error:  The following path violates requirements by 10.378ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdUFMCLK_386  (to PHI2_c -)
-
-   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
-      2.500ns delay constraint less
-      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
-
- Path Details: Bank_i5 to CmdUFMCLK_386
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
-Route         1   e 1.220                                  Bank[5]
-LUT4        ---     0.390              B to Z              i1856_4_lut
-Route         1   e 1.220                                  n2166
-LUT4        ---     0.390              B to Z              i12_4_lut
-Route         1   e 1.220                                  n26
-LUT4        ---     0.390              B to Z              i13_4_lut
-Route         4   e 1.552                                  n1285
-LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
-Route         3   e 1.483                                  n2290
-LUT4        ---     0.390              D to Z              i3_4_lut
-Route         3   e 1.483                                  XOR8MEG_N_112
-LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
-Route         3   e 1.483                                  PHI2_N_114_enable_7
-                  --------
-                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
-
-Warning: 12.878 ns is the maximum delay for this constraint.
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
-            369 items scored, 244 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 6.291ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
-   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
-
-   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.027ns data_path FS_577__i12 to LEDEN_392 violates
-      5.000ns delay constraint less
-      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
-
- Path Details: FS_577__i12 to LEDEN_392
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
-Route         3   e 1.603                                  FS[12]
-LUT4        ---     0.390              C to Z              i4_4_lut
-Route         3   e 1.483                                  n10
-LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
-Route         4   e 1.552                                  n2300
-LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
-Route         1   e 1.220                                  n11
-LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
-Route         2   e 1.386                                  n2119
-LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
-Route         1   e 1.220                                  RCLK_c_enable_25
-                  --------
-                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 6.291ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
-   Destination:    FD1P3AX    SP             n8MEGEN_391  (to RCLK_c +)
-
-   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
-      5.000ns delay constraint less
-      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
-
- Path Details: FS_577__i12 to n8MEGEN_391
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
-Route         3   e 1.603                                  FS[12]
-LUT4        ---     0.390              C to Z              i4_4_lut
-Route         3   e 1.483                                  n10
-LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
-Route         4   e 1.552                                  n2300
-LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
-Route         1   e 1.220                                  n11
-LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
-Route         2   e 1.386                                  n2119
-LUT4        ---     0.390              D to Z              i1248_4_lut
-Route         1   e 1.220                                  RCLK_c_enable_7
-                  --------
-                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 6.291ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_577__i13  (from RCLK_c +)
-   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
-
-   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.027ns data_path FS_577__i13 to LEDEN_392 violates
-      5.000ns delay constraint less
-      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
-
- Path Details: FS_577__i13 to LEDEN_392
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              FS_577__i13 (from RCLK_c)
-Route         3   e 1.603                                  FS[13]
-LUT4        ---     0.390              B to Z              i4_4_lut
-Route         3   e 1.483                                  n10
-LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
-Route         4   e 1.552                                  n2300
-LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
-Route         1   e 1.220                                  n11
-LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
-Route         2   e 1.386                                  n2119
-LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
-Route         1   e 1.220                                  RCLK_c_enable_25
-                  --------
-                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
-
-Warning: 11.291 ns is the maximum delay for this constraint.
-
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |     5.000 ns|    25.756 ns|     7 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |     5.000 ns|    11.291 ns|     6 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
---------------------------------------------------------------------------------
-Critical Nets                           |   Loads|  Errors| % of total
---------------------------------------------------------------------------------
-n1285                                   |       4|     112|     30.68%
-                                        |        |        |
-n26                                     |       1|      70|     19.18%
-                                        |        |        |
-RCLK_c_enable_23                        |      16|      64|     17.53%
-                                        |        |        |
-n2290                                   |       3|      64|     17.53%
-                                        |        |        |
-XOR8MEG_N_112                           |       3|      54|     14.79%
-                                        |        |        |
-n2119                                   |       2|      48|     13.15%
-                                        |        |        |
-n2166                                   |       1|      42|     11.51%
-                                        |        |        |
---------------------------------------------------------------------------------
-
-
-Timing summary:
----------------
-
-Timing errors: 365  Score: 2309745
-
-Constraints cover  495 paths, 177 nets, and 464 connections (66.5% coverage)
-
-
-Peak memory: 52920320 bytes, TRCE: 1425408 bytes, DLYMAN: 163840 bytes
-CPU_TIME_REPORT: 0 secs 
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html
deleted file mode 100644
index 93ec74e..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html
+++ /dev/null
@@ -1,376 +0,0 @@
-
-Lattice Synthesis Timing Report
-
-
-
    Lattice Synthesis Timing Report
---------------------------------------------------------------------------------
-Lattice Synthesis Timing Report, Version  
-Mon Aug 16 21:33:30 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Design:     RAM2GS
-Constraint file:  
-Report level:    verbose report, limited to 3 items per constraint
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
-            122 items scored, 121 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 10.378ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdUFMCS_385  (to PHI2_c -)
-
-   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
-      2.500ns delay constraint less
-      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
-
- Path Details: Bank_i5 to CmdUFMCS_385
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
-Route         1   e 1.220                                  Bank[5]
-LUT4        ---     0.390              B to Z              i1856_4_lut
-Route         1   e 1.220                                  n2166
-LUT4        ---     0.390              B to Z              i12_4_lut
-Route         1   e 1.220                                  n26
-LUT4        ---     0.390              B to Z              i13_4_lut
-Route         4   e 1.552                                  n1285
-LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
-Route         3   e 1.483                                  n2290
-LUT4        ---     0.390              D to Z              i3_4_lut
-Route         3   e 1.483                                  XOR8MEG_N_112
-LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
-Route         3   e 1.483                                  PHI2_N_114_enable_7
-                  --------
-                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
-
-
-Error:  The following path violates requirements by 10.378ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdUFMSDI_387  (to PHI2_c -)
-
-   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
-      2.500ns delay constraint less
-      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
-
- Path Details: Bank_i5 to CmdUFMSDI_387
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
-Route         1   e 1.220                                  Bank[5]
-LUT4        ---     0.390              B to Z              i1856_4_lut
-Route         1   e 1.220                                  n2166
-LUT4        ---     0.390              B to Z              i12_4_lut
-Route         1   e 1.220                                  n26
-LUT4        ---     0.390              B to Z              i13_4_lut
-Route         4   e 1.552                                  n1285
-LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
-Route         3   e 1.483                                  n2290
-LUT4        ---     0.390              D to Z              i3_4_lut
-Route         3   e 1.483                                  XOR8MEG_N_112
-LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
-Route         3   e 1.483                                  PHI2_N_114_enable_7
-                  --------
-                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
-
-
-Error:  The following path violates requirements by 10.378ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             Bank_i5  (from PHI2_c +)
-   Destination:    FD1P3AX    SP             CmdUFMCLK_386  (to PHI2_c -)
-
-   Delay:                  12.614ns  (23.4% logic, 76.6% route), 7 logic levels.
-
- Constraint Details:
-
-     12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
-      2.500ns delay constraint less
-      0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
-
- Path Details: Bank_i5 to CmdUFMCLK_386
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              Bank_i5 (from PHI2_c)
-Route         1   e 1.220                                  Bank[5]
-LUT4        ---     0.390              B to Z              i1856_4_lut
-Route         1   e 1.220                                  n2166
-LUT4        ---     0.390              B to Z              i12_4_lut
-Route         1   e 1.220                                  n26
-LUT4        ---     0.390              B to Z              i13_4_lut
-Route         4   e 1.552                                  n1285
-LUT4        ---     0.390              B to Z              i1830_2_lut_rep_13
-Route         3   e 1.483                                  n2290
-LUT4        ---     0.390              D to Z              i3_4_lut
-Route         3   e 1.483                                  XOR8MEG_N_112
-LUT4        ---     0.390              A to Z              i2_3_lut_4_lut
-Route         3   e 1.483                                  PHI2_N_114_enable_7
-                  --------
-                   12.614  (23.4% logic, 76.6% route), 7 logic levels.
-
-Warning: 12.878 ns is the maximum delay for this constraint.
-
-
-
-================================================================================
-Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
-            369 items scored, 244 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error:  The following path violates requirements by 6.291ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
-   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
-
-   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.027ns data_path FS_577__i12 to LEDEN_392 violates
-      5.000ns delay constraint less
-      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
-
- Path Details: FS_577__i12 to LEDEN_392
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
-Route         3   e 1.603                                  FS[12]
-LUT4        ---     0.390              C to Z              i4_4_lut
-Route         3   e 1.483                                  n10
-LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
-Route         4   e 1.552                                  n2300
-LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
-Route         1   e 1.220                                  n11
-LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
-Route         2   e 1.386                                  n2119
-LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
-Route         1   e 1.220                                  RCLK_c_enable_25
-                  --------
-                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 6.291ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_577__i12  (from RCLK_c +)
-   Destination:    FD1P3AX    SP             n8MEGEN_391  (to RCLK_c +)
-
-   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
-      5.000ns delay constraint less
-      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
-
- Path Details: FS_577__i12 to n8MEGEN_391
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              FS_577__i12 (from RCLK_c)
-Route         3   e 1.603                                  FS[12]
-LUT4        ---     0.390              C to Z              i4_4_lut
-Route         3   e 1.483                                  n10
-LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
-Route         4   e 1.552                                  n2300
-LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
-Route         1   e 1.220                                  n11
-LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
-Route         2   e 1.386                                  n2119
-LUT4        ---     0.390              D to Z              i1248_4_lut
-Route         1   e 1.220                                  RCLK_c_enable_7
-                  --------
-                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
-
-
-Error:  The following path violates requirements by 6.291ns
-
- Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
-
-   Source:         FD1S3AX    CK             FS_577__i13  (from RCLK_c +)
-   Destination:    FD1P3AX    SP             LEDEN_392  (to RCLK_c +)
-
-   Delay:                  11.027ns  (23.2% logic, 76.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.027ns data_path FS_577__i13 to LEDEN_392 violates
-      5.000ns delay constraint less
-      0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
-
- Path Details: FS_577__i13 to LEDEN_392
-
-   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
-L_CO        ---     0.613             CK to Q              FS_577__i13 (from RCLK_c)
-Route         3   e 1.603                                  FS[13]
-LUT4        ---     0.390              B to Z              i4_4_lut
-Route         3   e 1.483                                  n10
-LUT4        ---     0.390              B to Z              i5_3_lut_rep_23
-Route         4   e 1.552                                  n2300
-LUT4        ---     0.390              B to Z              i4_3_lut_4_lut
-Route         1   e 1.220                                  n11
-LUT4        ---     0.390              C to Z              i2_4_lut_adj_4
-Route         2   e 1.386                                  n2119
-LUT4        ---     0.390              C to Z              i2_3_lut_3_lut
-Route         1   e 1.220                                  RCLK_c_enable_25
-                  --------
-                   11.027  (23.2% logic, 76.8% route), 6 logic levels.
-
-Warning: 11.291 ns is the maximum delay for this constraint.
-
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |     5.000 ns|    25.756 ns|     7 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |     5.000 ns|    11.291 ns|     6 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
---------------------------------------------------------------------------------
-Critical Nets                           |   Loads|  Errors| % of total
---------------------------------------------------------------------------------
-n1285                                   |       4|     112|     30.68%
-                                        |        |        |
-n26                                     |       1|      70|     19.18%
-                                        |        |        |
-RCLK_c_enable_23                        |      16|      64|     17.53%
-                                        |        |        |
-n2290                                   |       3|      64|     17.53%
-                                        |        |        |
-XOR8MEG_N_112                           |       3|      54|     14.79%
-                                        |        |        |
-n2119                                   |       2|      48|     13.15%
-                                        |        |        |
-n2166                                   |       1|      42|     11.51%
-                                        |        |        |
---------------------------------------------------------------------------------
-
-
-Timing summary:
----------------
-
-Timing errors: 365  Score: 2309745
-
-Constraints cover  495 paths, 177 nets, and 464 connections (66.5% coverage)
-
-
-Peak memory: 52920320 bytes, TRCE: 1425408 bytes, DLYMAN: 163840 bytes
-CPU_TIME_REPORT: 0 secs 
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diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_prim.v b/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_prim.v
deleted file mode 100644
index 9cec3ba..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/RAM2GS_prim.v
+++ /dev/null
@@ -1,789 +0,0 @@
-// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.0.240.2
-// Netlist written on Mon Aug 16 21:33:30 2021
-//
-// Verilog Description of module RAM2GS
-//
-
-module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, 
-            LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, 
-            nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1[8:14])
-    input PHI2;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
-    input [9:0]MAin;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
-    input [1:0]CROW;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
-    input [7:0]Din;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
-    output [7:0]Dout;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
-    input nCCAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
-    input nCRAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
-    input nFWE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12])
-    output LED;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12])
-    output [1:0]RBA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
-    output [11:0]RA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    inout [7:0]RD;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
-    output nRCS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17])
-    input RCLK;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
-    output RCKE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17])
-    output nRWE;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49])
-    output nRRAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28])
-    output nRCAS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39])
-    output RDQMH;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21])
-    output RDQML;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14])
-    output nUFMCS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19])
-    output UFMCLK;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19])
-    output UFMSDI;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19])
-    input UFMSDO;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14])
-    
-    wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
-    wire nCCAS_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
-    wire nCRAS_c /* synthesis is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
-    wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
-    wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
-    wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
-    wire PHI2_N_114 /* synthesis is_inv_clock=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(38[6:13])
-    
-    wire GND_net, VCC_net, LEDEN, PHI2r, PHI2r2, PHI2r3, RASr, 
-        RASr2, RASr3, CASr, CASr2, CASr3, FWEr, CBR, Din_c_7, 
-        Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0, 
-        n2131, n33, PHI2_N_114_enable_2, n1;
-    wire [7:0]Bank;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(31[12:16])
-    
-    wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, 
-        MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, 
-        nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, 
-        nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, n980;
-    wire [9:0]RowA;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(51[12:16])
-    
-    wire RA_c_9, RA_c_8, RA_c_7, RA_c_6, RA_c_5, RA_c_4, RA_c_3, 
-        RA_c_2, RA_c_1, RA_c_0, RDQML_c, RDQMH_c;
-    wire [7:0]WRD;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(59[12:15])
-    
-    wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, 
-        CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, 
-        CmdUFMCS, InitReady, Ready;
-    wire [17:0]FS;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(86[13:15])
-    
-    wire LED_N_90, RA11_N_180, n2164, n1895, n2294, n4, PHI2_N_114_enable_6, 
-        n1881, RASr2_N_63, RCKE_N_128, nRowColSel_N_35, nRWE_N_178, 
-        RCKEEN_N_126, nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, 
-        nRowColSel_N_28, n1880, n4_adj_1, n2286, RCKEEN_N_117, nRWE_N_174, 
-        RCKEEN_N_116, nRCS_N_135, nRCAS_N_161, nRWE_N_173, nRWE_N_172, 
-        n1377, Ready_N_272, n2287, n26, Ready_N_268, nRCS_N_132, 
-        nRCAS_N_157, nRWE_N_167, RCKEEN_N_115, n2290, n2289, n1361, 
-        n1369, ADSubmitted_N_234, CmdEnable_N_236, C1Submitted_N_225, 
-        XOR8MEG_N_112, n2098, PHI2_N_114_enable_1, n2248, Cmdn8MEGEN_N_248, 
-        RCLK_c_enable_7, n2244, n2117, LEDEN_N_88, RCLK_c_enable_6, 
-        UFMSDO_N_74, n2243, RCLK_c_enable_24, n8MEGEN_N_94, UFMCLK_N_212, 
-        UFMSDI_N_219, n2242, n2114, n2080, PHI2_N_114_enable_7, n12, 
-        n699, n700, n701, n702, n703, n705, n706, n707, n708, 
-        n709, n710, n711, n11, n2076, n2119, n1368, n12_adj_2, 
-        n1878, PHI2_N_114_enable_8, n2308, n2291, n2307, n11_adj_3, 
-        n973, n1135, n78, n79, n80, n81, n82, n83, n84, n85, 
-        n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, 
-        n1348, n50, n1877, RCLK_c_enable_23, n1876, n1875, n2293, 
-        n2306, RCLK_c_enable_4, n2170, RCLK_c_enable_25, RCLK_c_enable_3, 
-        n2128, n2103, n2304, n2386, n1879, n1874, n2310, n974, 
-        n975, n962, n976, n2168, n977, n2245, n978, n2122, n979, 
-        Dout_c, n2166, n2302, n2108, n2301, n2387, n1285, n2300, 
-        n1628, n1627, n2299, n18, n2385, n2309, n2298, n2292, 
-        n2297, n2154, n10, n2296, n2295;
-    
-    VHI i2 (.Z(VCC_net));
-    INV i1963 (.A(nCCAS_c), .Z(nCCAS_N_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
-    FD1S3AX PHI2r2_350 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
-    defparam PHI2r2_350.GSR = "ENABLED";
-    ORCALUT4 i2_3_lut_4_lut (.A(XOR8MEG_N_112), .B(n2298), .C(n2296), 
-            .D(Din_c_5), .Z(PHI2_N_114_enable_7)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
-    defparam i2_3_lut_4_lut.init = 16'h0800;
-    ORCALUT4 i1_2_lut_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), .Z(n4)) /* synthesis lut_function=((B+(C))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
-    defparam i1_2_lut_3_lut.init = 16'hfdfd;
-    FD1S3AX PHI2r3_351 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
-    defparam PHI2r3_351.GSR = "ENABLED";
-    FD1S3AX RASr_352 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
-    defparam RASr_352.GSR = "ENABLED";
-    FD1S3AX RASr2_353 (.D(RASr), .CK(RCLK_c), .Q(RASr2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
-    defparam RASr2_353.GSR = "ENABLED";
-    FD1S3AX RASr3_354 (.D(RASr2), .CK(RCLK_c), .Q(RASr3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
-    defparam RASr3_354.GSR = "ENABLED";
-    FD1S3AX CASr_355 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
-    defparam CASr_355.GSR = "ENABLED";
-    FD1S3AX CASr2_356 (.D(CASr), .CK(RCLK_c), .Q(CASr2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
-    defparam CASr2_356.GSR = "ENABLED";
-    FD1S3AX CASr3_357 (.D(CASr2), .CK(RCLK_c), .Q(CASr3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
-    defparam CASr3_357.GSR = "ENABLED";
-    FD1S3IX RA11_358 (.D(RA11_N_180), .CK(PHI2_c), .CD(n2307), .Q(RA_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
-    defparam RA11_358.GSR = "ENABLED";
-    FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RowA_i0.GSR = "ENABLED";
-    FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
-    defparam WRD_i0.GSR = "ENABLED";
-    FD1S3AX FWEr_362 (.D(n2306), .CK(nCRAS_N_9), .Q(FWEr));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam FWEr_362.GSR = "ENABLED";
-    FD1S3AX CBR_363 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam CBR_363.GSR = "ENABLED";
-    FD1S3IX ADSubmitted_380 (.D(n1361), .CK(PHI2_N_114), .CD(C1Submitted_N_225), 
-            .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
-    defparam ADSubmitted_380.GSR = "ENABLED";
-    ORCALUT4 MAin_9__I_0_400_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), 
-            .Z(RA_c_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
-    defparam MAin_9__I_0_400_i5_3_lut.init = 16'hcaca;
-    ORCALUT4 i1_2_lut (.A(FS[10]), .B(n2076), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A (B)) */ ;
-    defparam i1_2_lut.init = 16'h8888;
-    CCU2 FS_577_add_4_10 (.A0(FS[8]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-         .A1(FS[9]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1877), 
-         .COUT1(n1878), .S0(n87), .S1(n86));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577_add_4_10.INIT0 = 16'hfaaa;
-    defparam FS_577_add_4_10.INIT1 = 16'hfaaa;
-    defparam FS_577_add_4_10.INJECT1_0 = "NO";
-    defparam FS_577_add_4_10.INJECT1_1 = "NO";
-    FD1S3AX RCKE_368 (.D(RCKE_N_128), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(141[9] 144[5])
-    defparam RCKE_368.GSR = "ENABLED";
-    FD1P3AY nRCS_369 (.D(nRCS_N_132), .SP(RCLK_c_enable_4), .CK(RCLK_c), 
-            .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam nRCS_369.GSR = "ENABLED";
-    FD1S3IX nRowColSel_375 (.D(n1368), .CK(RCLK_c), .CD(n2299), .Q(nRowColSel));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam nRowColSel_375.GSR = "ENABLED";
-    ORCALUT4 n1_bdd_4_lut (.A(n1), .B(n1627), .C(nRWE_N_178), .D(nRowColSel_N_35), 
-            .Z(nRWE_N_174)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ;
-    defparam n1_bdd_4_lut.init = 16'hf0dd;
-    ORCALUT4 i2_3_lut_rep_31 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), 
-            .Z(n2308)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
-    defparam i2_3_lut_rep_31.init = 16'h0808;
-    ORCALUT4 i1_2_lut_2_lut_4_lut (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), 
-            .D(InitReady), .Z(RCLK_c_enable_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ;
-    defparam i1_2_lut_2_lut_4_lut.init = 16'h08ff;
-    CCU2 FS_577_add_4_8 (.A0(FS[6]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-         .A1(FS[7]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1876), 
-         .COUT1(n1877), .S0(n89), .S1(n88));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577_add_4_8.INIT0 = 16'hfaaa;
-    defparam FS_577_add_4_8.INIT1 = 16'hfaaa;
-    defparam FS_577_add_4_8.INJECT1_0 = "NO";
-    defparam FS_577_add_4_8.INJECT1_1 = "NO";
-    ORCALUT4 i1_4_lut (.A(nRowColSel_N_34), .B(n1), .C(n2304), .D(nRowColSel_N_33), 
-            .Z(n2117)) /* synthesis lut_function=(!(A+(B (C (D))+!B (C+!(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
-    defparam i1_4_lut.init = 16'h0544;
-    ORCALUT4 i3_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n2290), 
-            .Z(XOR8MEG_N_112)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
-    defparam i3_4_lut.init = 16'h0040;
-    ORCALUT4 i4_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[6]), .D(n2168), 
-            .Z(n11)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
-    defparam i4_3_lut_4_lut.init = 16'hfdff;
-    FD1S3IX S_FSM_i2 (.D(n1135), .CK(RCLK_c), .CD(n2302), .Q(nRowColSel_N_34));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam S_FSM_i2.GSR = "ENABLED";
-    ORCALUT4 i1_4_lut_adj_1 (.A(nRowColSel), .B(n1627), .C(nRowColSel_N_28), 
-            .D(nRowColSel_N_32), .Z(n1368)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B+!(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i1_4_lut_adj_1.init = 16'hcfee;
-    FD1S3AY nRRAS_370 (.D(n33), .CK(RCLK_c), .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam nRRAS_370.GSR = "ENABLED";
-    ORCALUT4 i1055_3_lut_4_lut (.A(MAin_c_1), .B(n2290), .C(ADSubmitted), 
-            .D(ADSubmitted_N_234), .Z(n1361)) /* synthesis lut_function=(A (B (C+(D))+!B (D))+!A (C+(D))) */ ;
-    defparam i1055_3_lut_4_lut.init = 16'hffd0;
-    ORCALUT4 i2_3_lut (.A(FWEr), .B(CASr3), .C(CBR), .Z(nRowColSel_N_28)) /* synthesis lut_function=((B+(C))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(230[16:37])
-    defparam i2_3_lut.init = 16'hfdfd;
-    BB Dout_pad_7__688 (.I(WRD[7]), .T(n962), .B(RD[7]), .O(n973));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
-    FD1P3AY nRCAS_371 (.D(nRCAS_N_157), .SP(RCLK_c_enable_4), .CK(RCLK_c), 
-            .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam nRCAS_371.GSR = "ENABLED";
-    FD1P3AY nRWE_372 (.D(nRWE_N_167), .SP(RCLK_c_enable_3), .CK(RCLK_c), 
-            .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam nRWE_372.GSR = "ENABLED";
-    FD1S3JX RA10_373 (.D(n2128), .CK(RCLK_c), .PD(nRWE_N_172), .Q(n980));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam RA10_373.GSR = "ENABLED";
-    FD1P3AX RCKEEN_374 (.D(RCKEEN_N_115), .SP(RCLK_c_enable_4), .CK(RCLK_c), 
-            .Q(RCKEEN));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam RCKEEN_374.GSR = "ENABLED";
-    ORCALUT4 i2_4_lut (.A(n2122), .B(n2295), .C(Din_c_2), .D(n2131), 
-            .Z(C1Submitted_N_225)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
-    defparam i2_4_lut.init = 16'h0008;
-    FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RBA__i1.GSR = "ENABLED";
-    ORCALUT4 Din_7__I_0_442_i6_2_lut_rep_32 (.A(Din_c_6), .B(Din_c_7), .Z(n2385)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
-    defparam Din_7__I_0_442_i6_2_lut_rep_32.init = 16'heeee;
-    ORCALUT4 i1248_4_lut (.A(FS[5]), .B(n2308), .C(InitReady), .D(n2119), 
-            .Z(RCLK_c_enable_7)) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
-    defparam i1248_4_lut.init = 16'hc5c0;
-    ORCALUT4 i2_3_lut_4_lut_adj_2 (.A(nRowColSel_N_32), .B(n2299), .C(nRowColSel_N_34), 
-            .D(nRowColSel_N_33), .Z(RCLK_c_enable_4)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i2_3_lut_4_lut_adj_2.init = 16'hfffe;
-    ORCALUT4 i1437_4_lut (.A(UFMSDO_c), .B(Cmdn8MEGEN), .C(FS[10]), .D(n4), 
-            .Z(n8MEGEN_N_94)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
-    defparam i1437_4_lut.init = 16'hcc5c;
-    FD1P3AX IS_FSM__i0 (.D(Ready_N_272), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(nRCS_N_135));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i0.GSR = "ENABLED";
-    ORCALUT4 i1_2_lut_adj_3 (.A(RASr2), .B(RCKE_c), .Z(nRWE_N_178)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
-    defparam i1_2_lut_adj_3.init = 16'hbbbb;
-    ORCALUT4 i2_4_lut_adj_4 (.A(n2294), .B(FS[10]), .C(n11), .D(n12), 
-            .Z(n2119)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
-    defparam i2_4_lut_adj_4.init = 16'h0008;
-    FD1P3JX C1Submitted_379 (.D(n2386), .SP(PHI2_N_114_enable_1), .PD(C1Submitted_N_225), 
-            .CK(PHI2_N_114), .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
-    defparam C1Submitted_379.GSR = "ENABLED";
-    FD1S3JX nUFMCS_388 (.D(n1348), .CK(RCLK_c), .PD(LEDEN_N_88), .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
-    defparam nUFMCS_388.GSR = "ENABLED";
-    ORCALUT4 m1_lut (.Z(n2387)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
-    defparam m1_lut.init = 16'hffff;
-    ORCALUT4 i2_4_lut_adj_5 (.A(n2108), .B(MAin_c_1), .C(C1Submitted), 
-            .D(MAin_c_0), .Z(n2098)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
-    defparam i2_4_lut_adj_5.init = 16'h0800;
-    ORCALUT4 i5_4_lut (.A(FS[9]), .B(FS[4]), .C(FS[8]), .D(FS[7]), .Z(n12)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;
-    defparam i5_4_lut.init = 16'hfffb;
-    FD1S3AX FS_577__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i0.GSR = "ENABLED";
-    ORCALUT4 i2_3_lut_adj_6 (.A(n2122), .B(ADSubmitted), .C(MAin_c_0), 
-            .Z(n2080)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
-    defparam i2_3_lut_adj_6.init = 16'h0202;
-    ORCALUT4 i1419_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(58[17:46])
-    defparam i1419_2_lut.init = 16'hbbbb;
-    ORCALUT4 n50_bdd_4_lut_1911 (.A(n50), .B(RASr2), .C(RCKE_c), .D(nRowColSel_N_35), 
-            .Z(n2242)) /* synthesis lut_function=(!(A (B (D)+!B (C (D)))+!A (B+(C+!(D))))) */ ;
-    defparam n50_bdd_4_lut_1911.init = 16'h03aa;
-    ORCALUT4 i1893_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ;
-    defparam i1893_2_lut.init = 16'h7777;
-    FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
-    defparam Bank_i0.GSR = "ENABLED";
-    ORCALUT4 i1858_4_lut (.A(FS[1]), .B(FS[0]), .C(FS[2]), .D(FS[3]), 
-            .Z(n2168)) /* synthesis lut_function=(A (B (C (D)))) */ ;
-    defparam i1858_4_lut.init = 16'h8000;
-    ORCALUT4 i1_2_lut_3_lut_adj_7 (.A(MAin_c_1), .B(n1285), .C(MAin_c_0), 
-            .Z(n2131)) /* synthesis lut_function=((B+(C))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31])
-    defparam i1_2_lut_3_lut_adj_7.init = 16'hfdfd;
-    ORCALUT4 i22_4_lut (.A(FS[4]), .B(CmdUFMCLK), .C(InitReady), .D(n2076), 
-            .Z(UFMCLK_N_212)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
-    defparam i22_4_lut.init = 16'hc0ca;
-    ORCALUT4 i5_4_lut_adj_8 (.A(FS[14]), .B(FS[16]), .C(FS[13]), .D(FS[12]), 
-            .Z(n12_adj_2)) /* synthesis lut_function=(A (B (C (D)))) */ ;
-    defparam i5_4_lut_adj_8.init = 16'h8000;
-    ORCALUT4 i1889_4_lut_then_4_lut (.A(n2117), .B(RCKE_c), .C(RASr2), 
-            .D(nRowColSel_N_35), .Z(n2310)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A (B (D)+!B (C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
-    defparam i1889_4_lut_then_4_lut.init = 16'h0355;
-    ORCALUT4 i1889_4_lut_else_4_lut (.A(InitReady), .B(nRCS_N_135), .C(RASr2), 
-            .D(nRowColSel_N_35), .Z(n2309)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
-    defparam i1889_4_lut_else_4_lut.init = 16'hdfff;
-    CCU2 FS_577_add_4_18 (.A0(FS[16]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-         .A1(FS[17]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1881), 
-         .S0(n79), .S1(n78));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577_add_4_18.INIT0 = 16'hfaaa;
-    defparam FS_577_add_4_18.INIT1 = 16'hfaaa;
-    defparam FS_577_add_4_18.INJECT1_0 = "NO";
-    defparam FS_577_add_4_18.INJECT1_1 = "NO";
-    ORCALUT4 UFMSDO_I_0_1_lut (.A(UFMSDO_c), .Z(UFMSDO_N_74)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(378[53:60])
-    defparam UFMSDO_I_0_1_lut.init = 16'h5555;
-    FD1S3IX S_FSM_i3 (.D(n1135), .CK(RCLK_c), .CD(n1377), .Q(nRowColSel_N_33));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam S_FSM_i3.GSR = "ENABLED";
-    ORCALUT4 i1897_2_lut_rep_14_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), 
-            .Z(n2291)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
-    defparam i1897_2_lut_rep_14_3_lut.init = 16'h0101;
-    ORCALUT4 i1878_2_lut_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[10]), 
-            .D(InitReady), .Z(LEDEN_N_88)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
-    defparam i1878_2_lut_3_lut_4_lut.init = 16'h0001;
-    ORCALUT4 i1884_4_lut (.A(MAin_c_0), .B(n2290), .C(n2286), .D(MAin_c_1), 
-            .Z(PHI2_N_114_enable_8)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ;
-    defparam i1884_4_lut.init = 16'h0302;
-    FD1S3AX PHI2r_349 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
-    defparam PHI2r_349.GSR = "ENABLED";
-    ORCALUT4 i2_3_lut_rep_21_4_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), 
-            .D(Din_c_4), .Z(n2298)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
-    defparam i2_3_lut_rep_21_4_lut.init = 16'hfffe;
-    ORCALUT4 i1830_2_lut_rep_13 (.A(nFWE_c), .B(n1285), .Z(n2290)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i1830_2_lut_rep_13.init = 16'heeee;
-    PFUMX i1912 (.BLUT(n2243), .ALUT(n2242), .C0(Ready), .Z(n2244));
-    FD1S3AX S_FSM_i1 (.D(RASr2_N_63), .CK(RCLK_c), .Q(nRowColSel_N_35));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam S_FSM_i1.GSR = "ENABLED";
-    ORCALUT4 i1886_2_lut (.A(nRowColSel_N_32), .B(RASr2), .Z(n1135)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i1886_2_lut.init = 16'h4444;
-    ORCALUT4 n50_bdd_4_lut (.A(n50), .B(InitReady), .C(RASr2), .D(nRowColSel_N_35), 
-            .Z(n2243)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C)))) */ ;
-    defparam n50_bdd_4_lut.init = 16'h3fbf;
-    ORCALUT4 i1034_2_lut (.A(ADSubmitted_N_234), .B(C1Submitted_N_225), 
-            .Z(CmdEnable_N_236)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i1034_2_lut.init = 16'heeee;
-    ORCALUT4 i2_3_lut_4_lut_adj_9 (.A(Din_c_6), .B(Din_c_7), .C(XOR8MEG_N_112), 
-            .D(Din_c_4), .Z(PHI2_N_114_enable_6)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
-    defparam i2_3_lut_4_lut_adj_9.init = 16'h1000;
-    ORCALUT4 i1832_2_lut_rep_19_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), 
-            .Z(n2296)) /* synthesis lut_function=(A+(B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
-    defparam i1832_2_lut_rep_19_3_lut.init = 16'hefef;
-    FD1S3IX S_FSM_i4 (.D(n1628), .CK(RCLK_c), .CD(RASr2_N_63), .Q(nRowColSel_N_32));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam S_FSM_i4.GSR = "ENABLED";
-    ORCALUT4 i1424_2_lut_rep_27 (.A(FWEr), .B(CBR), .Z(n2304)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i1424_2_lut_rep_27.init = 16'heeee;
-    ORCALUT4 i2_3_lut_adj_10 (.A(Din_c_3), .B(Din_c_6), .C(Din_c_5), .Z(n2122)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;
-    defparam i2_3_lut_adj_10.init = 16'h0404;
-    ORCALUT4 i1429_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(RCKEEN_N_126)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ;
-    defparam i1429_2_lut_3_lut.init = 16'h1f1f;
-    ORCALUT4 i4_4_lut (.A(FS[14]), .B(FS[13]), .C(FS[12]), .D(FS[15]), 
-            .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
-    defparam i4_4_lut.init = 16'hfffe;
-    ORCALUT4 i5_3_lut_rep_23 (.A(FS[16]), .B(n10), .C(FS[17]), .Z(n2300)) /* synthesis lut_function=(A+(B+(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
-    defparam i5_3_lut_rep_23.init = 16'hfefe;
-    ORCALUT4 i1_4_lut_adj_11 (.A(n2244), .B(n2297), .C(n18), .D(Ready), 
-            .Z(n33)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
-    defparam i1_4_lut_adj_11.init = 16'hfaee;
-    ORCALUT4 i1_2_lut_rep_16_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), 
-            .Z(n2293)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
-    defparam i1_2_lut_rep_16_4_lut.init = 16'hfeff;
-    ORCALUT4 i3_4_lut_adj_12 (.A(CBR), .B(FWEr), .C(CASr2), .D(CASr3), 
-            .Z(n1)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
-    defparam i3_4_lut_adj_12.init = 16'h0040;
-    ORCALUT4 i1_2_lut_adj_13 (.A(nRowColSel_N_34), .B(nRowColSel_N_33), 
-            .Z(n1627)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i1_2_lut_adj_13.init = 16'heeee;
-    ORCALUT4 i1420_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n962)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i1420_2_lut.init = 16'heeee;
-    ORCALUT4 i1_1_lut_rep_29 (.A(nFWE_c), .Z(n2306)) /* synthesis lut_function=(!(A)) */ ;
-    defparam i1_1_lut_rep_29.init = 16'h5555;
-    ORCALUT4 Cmdn8MEGEN_I_84_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_5), 
-            .D(n2296), .Z(Cmdn8MEGEN_N_248)) /* synthesis lut_function=(A (B (C+(D)))+!A (B+!(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(316[13] 322[7])
-    defparam Cmdn8MEGEN_I_84_4_lut.init = 16'hccc5;
-    ORCALUT4 i1069_1_lut (.A(nRowColSel_N_34), .Z(n1377)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i1069_1_lut.init = 16'h5555;
-    ORCALUT4 n2080_bdd_4_lut (.A(n2080), .B(n2098), .C(Din_c_2), .D(n2114), 
-            .Z(n2286)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
-    defparam n2080_bdd_4_lut.init = 16'hca00;
-    ORCALUT4 RASr2_I_0_1_lut (.A(RASr2), .Z(RASr2_N_63)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[40:46])
-    defparam RASr2_I_0_1_lut.init = 16'h5555;
-    ORCALUT4 i847_2_lut_4_lut (.A(n2385), .B(Din_c_4), .C(Din_c_5), .D(XOR8MEG_N_112), 
-            .Z(PHI2_N_114_enable_2)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(310[8:22])
-    defparam i847_2_lut_4_lut.init = 16'h0100;
-    ORCALUT4 i1_4_lut_adj_14 (.A(n2108), .B(MAin_c_0), .C(n4_adj_1), .D(n2289), 
-            .Z(ADSubmitted_N_234)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24])
-    defparam i1_4_lut_adj_14.init = 16'h0080;
-    ORCALUT4 i1_2_lut_adj_15 (.A(nRowColSel_N_33), .B(CASr2), .Z(n11_adj_3)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(48[6:16])
-    defparam i1_2_lut_adj_15.init = 16'hbbbb;
-    FD1S3AX FS_577__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i17.GSR = "ENABLED";
-    ORCALUT4 i1_2_lut_3_lut_3_lut (.A(nFWE_c), .B(Din_c_2), .C(n2114), 
-            .Z(n4_adj_1)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
-    defparam i1_2_lut_3_lut_3_lut.init = 16'h4040;
-    FD1S3AX FS_577__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i16.GSR = "ENABLED";
-    FD1S3AX FS_577__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i15.GSR = "ENABLED";
-    ORCALUT4 nRWE_I_0_428_4_lut (.A(n2164), .B(nRWE_N_174), .C(Ready), 
-            .D(n2292), .Z(nRWE_N_167)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(232[12] 284[6])
-    defparam nRWE_I_0_428_4_lut.init = 16'hcfc5;
-    ORCALUT4 i1257_3_lut (.A(n1895), .B(CmdUFMSDI), .C(InitReady), .Z(UFMSDI_N_219)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
-    defparam i1257_3_lut.init = 16'hcaca;
-    ORCALUT4 RCKE_I_0_423_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), 
-            .Z(RCKE_N_128)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[11:55])
-    defparam RCKE_I_0_423_4_lut.init = 16'hcfc8;
-    FD1P3AX InitReady_367 (.D(n2387), .SP(RCLK_c_enable_6), .CK(RCLK_c), 
-            .Q(InitReady)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(134[9] 138[5])
-    defparam InitReady_367.GSR = "ENABLED";
-    ORCALUT4 i1_2_lut_adj_16 (.A(nRowColSel_N_32), .B(nRowColSel_N_33), 
-            .Z(n1628)) /* synthesis lut_function=(A+(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i1_2_lut_adj_16.init = 16'heeee;
-    ORCALUT4 i1854_2_lut (.A(nRCAS_N_161), .B(nRWE_N_173), .Z(n2164)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam i1854_2_lut.init = 16'heeee;
-    ORCALUT4 i1_2_lut_rep_17_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]), 
-            .Z(n2294)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
-    defparam i1_2_lut_rep_17_4_lut.init = 16'hfffe;
-    ORCALUT4 i1881_2_lut_rep_24 (.A(RASr2), .B(InitReady), .Z(n2301)) /* synthesis lut_function=(!(A (B))) */ ;
-    defparam i1881_2_lut_rep_24.init = 16'h7777;
-    GSR GSR_INST (.GSR(VCC_net));
-    ORCALUT4 i1_2_lut_rep_18_2_lut (.A(nFWE_c), .B(n2114), .Z(n2295)) /* synthesis lut_function=(!(A+!(B))) */ ;
-    defparam i1_2_lut_rep_18_2_lut.init = 16'h4444;
-    FD1S3AX FS_577__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i14.GSR = "ENABLED";
-    ORCALUT4 i2_3_lut_3_lut (.A(InitReady), .B(FS[5]), .C(n2119), .Z(RCLK_c_enable_25)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(384[16:26])
-    defparam i2_3_lut_3_lut.init = 16'h4040;
-    ORCALUT4 i2_3_lut_adj_17 (.A(Din_c_6), .B(Din_c_5), .C(Din_c_3), .Z(n2108)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24])
-    defparam i2_3_lut_adj_17.init = 16'h4040;
-    ORCALUT4 i2_4_lut_adj_18 (.A(FS[6]), .B(n2293), .C(n2103), .D(FS[10]), 
-            .Z(n1895)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam i2_4_lut_adj_18.init = 16'h0020;
-    ORCALUT4 i1_4_lut_adj_19 (.A(FS[8]), .B(FS[7]), .C(FS[5]), .D(FS[9]), 
-            .Z(n2103)) /* synthesis lut_function=(!(A+(B (D)+!B !(C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(339[4] 372[11])
-    defparam i1_4_lut_adj_19.init = 16'h1044;
-    FD1P3AX XOR8MEG_381 (.D(Din_c_0), .SP(PHI2_N_114_enable_2), .CK(PHI2_N_114), 
-            .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
-    defparam XOR8MEG_381.GSR = "ENABLED";
-    FD1P3AX n8MEGEN_391 (.D(n8MEGEN_N_94), .SP(RCLK_c_enable_7), .CK(RCLK_c), 
-            .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
-    defparam n8MEGEN_391.GSR = "ENABLED";
-    FD1P3AX Ready_377 (.D(n2387), .SP(Ready_N_268), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam Ready_377.GSR = "ENABLED";
-    ORCALUT4 MAin_9__I_0_400_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), 
-            .Z(RA_c_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
-    defparam MAin_9__I_0_400_i2_3_lut.init = 16'hcaca;
-    FD1P3AX CmdUFMCLK_386 (.D(Din_c_1), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), 
-            .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
-    defparam CmdUFMCLK_386.GSR = "ENABLED";
-    FD1P3AX CmdUFMSDI_387 (.D(Din_c_0), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), 
-            .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
-    defparam CmdUFMSDI_387.GSR = "ENABLED";
-    FD1P3AX Cmdn8MEGEN_383 (.D(Cmdn8MEGEN_N_248), .SP(PHI2_N_114_enable_6), 
-            .CK(PHI2_N_114), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
-    defparam Cmdn8MEGEN_383.GSR = "ENABLED";
-    FD1P3AX CmdSubmitted_384 (.D(n2387), .SP(PHI2_N_114_enable_6), .CK(PHI2_N_114), 
-            .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
-    defparam CmdSubmitted_384.GSR = "ENABLED";
-    CCU2 FS_577_add_4_6 (.A0(FS[4]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-         .A1(FS[5]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1875), 
-         .COUT1(n1876), .S0(n91), .S1(n90));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577_add_4_6.INIT0 = 16'hfaaa;
-    defparam FS_577_add_4_6.INIT1 = 16'hfaaa;
-    defparam FS_577_add_4_6.INJECT1_0 = "NO";
-    defparam FS_577_add_4_6.INJECT1_1 = "NO";
-    FD1P3AX CmdUFMCS_385 (.D(Din_c_2), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114), 
-            .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
-    defparam CmdUFMCS_385.GSR = "ENABLED";
-    FD1S3AX FS_577__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i13.GSR = "ENABLED";
-    ORCALUT4 i1875_2_lut (.A(nCRAS_c), .B(LEDEN), .Z(LED_N_90)) /* synthesis lut_function=(A+!(B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(13[15:34])
-    defparam i1875_2_lut.init = 16'hbbbb;
-    FD1S3AX FS_577__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i12.GSR = "ENABLED";
-    PFUMX RCKEEN_I_0_419 (.BLUT(RCKEEN_N_117), .ALUT(RCKEEN_N_126), .C0(nRowColSel_N_35), 
-          .Z(RCKEEN_N_116));
-    ORCALUT4 i1856_4_lut (.A(Bank[0]), .B(Bank[5]), .C(MAin_c_2), .D(Bank[6]), 
-            .Z(n2166)) /* synthesis lut_function=(A (B (C (D)))) */ ;
-    defparam i1856_4_lut.init = 16'h8000;
-    FD1S3AX FS_577__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i11.GSR = "ENABLED";
-    ORCALUT4 i1844_2_lut (.A(Bank[7]), .B(MAin_c_4), .Z(n2154)) /* synthesis lut_function=(A (B)) */ ;
-    defparam i1844_2_lut.init = 16'h8888;
-    ORCALUT4 RA11_I_53_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_180)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(99[22:51])
-    defparam RA11_I_53_3_lut.init = 16'hc6c6;
-    ORCALUT4 Ready_bdd_3_lut_1922 (.A(nRCAS_N_161), .B(nRCS_N_135), .C(InitReady), 
-            .Z(n2248)) /* synthesis lut_function=(A+(B+!(C))) */ ;
-    defparam Ready_bdd_3_lut_1922.init = 16'hefef;
-    FD1P3IX UFMSDI_390 (.D(UFMSDI_N_219), .SP(RCLK_c_enable_24), .CD(n2291), 
-            .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
-    defparam UFMSDI_390.GSR = "ENABLED";
-    ORCALUT4 MAin_9__I_0_400_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), 
-            .Z(RA_c_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
-    defparam MAin_9__I_0_400_i10_3_lut.init = 16'hcaca;
-    ORCALUT4 i604_1_lut_rep_30 (.A(Ready), .Z(n2307)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam i604_1_lut_rep_30.init = 16'h5555;
-    FD1S3AX FS_577__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i10.GSR = "ENABLED";
-    FD1S3AX FS_577__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i9.GSR = "ENABLED";
-    FD1S3AX FS_577__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i8.GSR = "ENABLED";
-    FD1S3AX FS_577__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i7.GSR = "ENABLED";
-    FD1S3AX FS_577__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i6.GSR = "ENABLED";
-    FD1S3AX FS_577__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i5.GSR = "ENABLED";
-    FD1S3AX FS_577__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i4.GSR = "ENABLED";
-    FD1S3AX FS_577__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i3.GSR = "ENABLED";
-    FD1S3AX FS_577__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i2.GSR = "ENABLED";
-    FD1S3AX FS_577__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577__i1.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i15 (.D(n699), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(Ready_N_272));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i15.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i14 (.D(n700), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n699));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i14.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i13 (.D(n701), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n700));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i13.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i12 (.D(n702), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n701));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i12.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i11 (.D(n703), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n702));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i11.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i10 (.D(nRWE_N_173), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n703));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i10.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i9 (.D(n705), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(nRWE_N_173));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i9.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i8 (.D(n706), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n705));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i8.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i7 (.D(n707), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n706));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i7.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i6 (.D(n708), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n707));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i6.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i5 (.D(n709), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n708));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i5.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i4 (.D(n710), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n709));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i4.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i3 (.D(n711), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n710));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i3.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i2 (.D(nRCAS_N_161), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(n711));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i2.GSR = "ENABLED";
-    FD1P3AX IS_FSM__i1 (.D(nRCS_N_135), .SP(RCLK_c_enable_23), .CK(RCLK_c), 
-            .Q(nRCAS_N_161));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
-    defparam IS_FSM__i1.GSR = "ENABLED";
-    FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RBA__i2.GSR = "ENABLED";
-    FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
-    defparam WRD_i7.GSR = "ENABLED";
-    FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
-    defparam WRD_i6.GSR = "ENABLED";
-    FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
-    defparam WRD_i5.GSR = "ENABLED";
-    FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
-    defparam WRD_i4.GSR = "ENABLED";
-    FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
-    defparam WRD_i3.GSR = "ENABLED";
-    FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
-    defparam WRD_i2.GSR = "ENABLED";
-    FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
-    defparam WRD_i1.GSR = "ENABLED";
-    FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[9]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RowA_i9.GSR = "ENABLED";
-    FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[8]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RowA_i8.GSR = "ENABLED";
-    FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RowA_i7.GSR = "ENABLED";
-    FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RowA_i6.GSR = "ENABLED";
-    FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RowA_i5.GSR = "ENABLED";
-    FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RowA_i4.GSR = "ENABLED";
-    FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RowA_i3.GSR = "ENABLED";
-    FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RowA_i2.GSR = "ENABLED";
-    FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
-    defparam RowA_i1.GSR = "ENABLED";
-    FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
-    defparam Bank_i7.GSR = "ENABLED";
-    ORCALUT4 i1_2_lut_rep_12 (.A(MAin_c_1), .B(n1285), .Z(n2289)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31])
-    defparam i1_2_lut_rep_12.init = 16'hdddd;
-    ORCALUT4 i1_2_lut_rep_15_3_lut_4_lut_4_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), 
-            .C(InitReady), .D(RASr2), .Z(n2292)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i1_2_lut_rep_15_3_lut_4_lut_4_lut.init = 16'hdfff;
-    ORCALUT4 i1_2_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_35), .C(RASr2), 
-            .D(InitReady), .Z(RCLK_c_enable_23)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam i1_2_lut_4_lut_4_lut.init = 16'h4000;
-    FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
-    defparam Bank_i6.GSR = "ENABLED";
-    FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
-    defparam Bank_i5.GSR = "ENABLED";
-    FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
-    defparam Bank_i4.GSR = "ENABLED";
-    FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
-    defparam Bank_i3.GSR = "ENABLED";
-    FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
-    defparam Bank_i2.GSR = "ENABLED";
-    FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
-    defparam Bank_i1.GSR = "ENABLED";
-    BB Dout_pad_6__689 (.I(WRD[6]), .T(n962), .B(RD[6]), .O(n974));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
-    BB Dout_pad_5__690 (.I(WRD[5]), .T(n962), .B(RD[5]), .O(n975));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
-    BB Dout_pad_4__691 (.I(WRD[4]), .T(n962), .B(RD[4]), .O(n976));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
-    BB Dout_pad_3__692 (.I(WRD[3]), .T(n962), .B(RD[3]), .O(n977));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
-    BB Dout_pad_2__693 (.I(WRD[2]), .T(n962), .B(RD[2]), .O(n978));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
-    BB Dout_pad_1__694 (.I(WRD[1]), .T(n962), .B(RD[1]), .O(n979));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
-    ORCALUT4 nRWE_I_49_1_lut (.A(nRWE_N_173), .Z(nRWE_N_172)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(255[14] 262[8])
-    defparam nRWE_I_49_1_lut.init = 16'h5555;
-    BB Dout_pad_0__695 (.I(WRD[0]), .T(n962), .B(RD[0]), .O(Dout_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
-    OB Dout_pad_7 (.I(n973), .O(Dout[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
-    OB Dout_pad_6 (.I(n974), .O(Dout[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
-    OB Dout_pad_5 (.I(n975), .O(Dout[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
-    OB Dout_pad_4 (.I(n976), .O(Dout[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
-    OB Dout_pad_3 (.I(n977), .O(Dout[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
-    OB Dout_pad_2 (.I(n978), .O(Dout[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
-    OB Dout_pad_1 (.I(n979), .O(Dout[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
-    OB Dout_pad_0 (.I(Dout_c), .O(Dout[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
-    OB LED_pad (.I(LED_N_90), .O(LED));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12])
-    OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
-    OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
-    OB RA_pad_11 (.I(RA_c), .O(RA[11]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB RA_pad_10 (.I(n980), .O(RA[10]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB RA_pad_9 (.I(RA_c_9), .O(RA[9]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB RA_pad_8 (.I(RA_c_8), .O(RA[8]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB RA_pad_7 (.I(RA_c_7), .O(RA[7]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB RA_pad_6 (.I(RA_c_6), .O(RA[6]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB RA_pad_5 (.I(RA_c_5), .O(RA[5]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB RA_pad_4 (.I(RA_c_4), .O(RA[4]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB RA_pad_3 (.I(RA_c_3), .O(RA[3]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB RA_pad_2 (.I(RA_c_2), .O(RA[2]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB RA_pad_1 (.I(RA_c_1), .O(RA[1]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB RA_pad_0 (.I(RA_c_0), .O(RA[0]));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
-    OB nRCS_pad (.I(nRCS_c), .O(nRCS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17])
-    OB RCKE_pad (.I(RCKE_c), .O(RCKE));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17])
-    OB nRWE_pad (.I(nRWE_c), .O(nRWE));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49])
-    OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28])
-    OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39])
-    OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21])
-    OB RDQML_pad (.I(RDQML_c), .O(RDQML));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14])
-    OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19])
-    OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19])
-    OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19])
-    IB PHI2_pad (.I(PHI2), .O(PHI2_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
-    IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
-    IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
-    IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
-    IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
-    IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
-    IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
-    IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
-    IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
-    IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
-    IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
-    IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
-    IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
-    IB Din_pad_7 (.I(Din[7]), .O(Din_c_7));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
-    IB Din_pad_6 (.I(Din[6]), .O(Din_c_6));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
-    IB Din_pad_5 (.I(Din[5]), .O(Din_c_5));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
-    IB Din_pad_4 (.I(Din[4]), .O(Din_c_4));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
-    IB Din_pad_3 (.I(Din[3]), .O(Din_c_3));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
-    IB Din_pad_2 (.I(Din[2]), .O(Din_c_2));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
-    IB Din_pad_1 (.I(Din[1]), .O(Din_c_1));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
-    IB Din_pad_0 (.I(Din[0]), .O(Din_c_0));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
-    IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
-    IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
-    IB nFWE_pad (.I(nFWE), .O(nFWE_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12])
-    IB RCLK_pad (.I(RCLK), .O(RCLK_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
-    IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14])
-    ORCALUT4 MAin_9__I_0_400_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), 
-            .Z(RA_c_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
-    defparam MAin_9__I_0_400_i9_3_lut.init = 16'hcaca;
-    CCU2 FS_577_add_4_4 (.A0(FS[2]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-         .A1(FS[3]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1874), 
-         .COUT1(n1875), .S0(n93), .S1(n92));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577_add_4_4.INIT0 = 16'hfaaa;
-    defparam FS_577_add_4_4.INIT1 = 16'hfaaa;
-    defparam FS_577_add_4_4.INJECT1_0 = "NO";
-    defparam FS_577_add_4_4.INJECT1_1 = "NO";
-    ORCALUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_32), 
-            .C(n1627), .D(nRowColSel_N_35), .Z(RCLK_c_enable_3)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'hfffd;
-    FD1P3IX UFMCLK_389 (.D(UFMCLK_N_212), .SP(RCLK_c_enable_24), .CD(n2291), 
-            .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
-    defparam UFMCLK_389.GSR = "ENABLED";
-    ORCALUT4 i2_2_lut_rep_22_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2299)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
-    defparam i2_2_lut_rep_22_2_lut.init = 16'hdddd;
-    ORCALUT4 i2_3_lut_4_lut_adj_20 (.A(n2297), .B(n2301), .C(nRCAS_N_161), 
-            .D(Ready), .Z(n2128)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i2_3_lut_4_lut_adj_20.init = 16'hfffe;
-    ORCALUT4 i2_3_lut_adj_21 (.A(nRowColSel_N_33), .B(nRRAS_c), .C(nRowColSel_N_32), 
-            .Z(n50)) /* synthesis lut_function=(A+(B+(C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i2_3_lut_adj_21.init = 16'hfefe;
-    ORCALUT4 MAin_9__I_0_400_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), 
-            .Z(RA_c_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
-    defparam MAin_9__I_0_400_i8_3_lut.init = 16'hcaca;
-    ORCALUT4 Ready_bdd_4_lut (.A(Ready), .B(n2117), .C(n2287), .D(nRowColSel_N_35), 
-            .Z(nRCAS_N_157)) /* synthesis lut_function=(A (B (C (D))+!B (C+!(D)))+!A (C+!(D))) */ ;
-    defparam Ready_bdd_4_lut.init = 16'hf077;
-    ORCALUT4 i1366_3_lut (.A(InitReady), .B(RCKEEN_N_116), .C(Ready), 
-            .Z(RCKEEN_N_115)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
-    defparam i1366_3_lut.init = 16'hcaca;
-    ORCALUT4 i6_4_lut (.A(FS[15]), .B(n12_adj_2), .C(FS[11]), .D(FS[17]), 
-            .Z(n2076)) /* synthesis lut_function=(A (B (C (D)))) */ ;
-    defparam i6_4_lut.init = 16'h8000;
-    ORCALUT4 i1_4_lut_4_lut (.A(CBR), .B(n11_adj_3), .C(FWEr), .D(nRowColSel_N_34), 
-            .Z(RCKEEN_N_117)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(214[26:30])
-    defparam i1_4_lut_4_lut.init = 16'h5540;
-    ORCALUT4 i1_2_lut_rep_11_3_lut (.A(nFWE_c), .B(n1285), .C(MAin_c_1), 
-            .Z(PHI2_N_114_enable_1)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
-    defparam i1_2_lut_rep_11_3_lut.init = 16'h1010;
-    CCU2 FS_577_add_4_2 (.A0(FS[0]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-         .A1(FS[1]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(GND_net), 
-         .COUT1(n1874), .S0(n95), .S1(n94));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577_add_4_2.INIT0 = 16'h0555;
-    defparam FS_577_add_4_2.INIT1 = 16'hfaaa;
-    defparam FS_577_add_4_2.INJECT1_0 = "NO";
-    defparam FS_577_add_4_2.INJECT1_1 = "NO";
-    ORCALUT4 i3_4_lut_adj_22 (.A(Din_c_0), .B(Din_c_1), .C(Din_c_4), .D(Din_c_7), 
-            .Z(n2114)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
-    defparam i3_4_lut_adj_22.init = 16'h0200;
-    ORCALUT4 Ready_bdd_4_lut_1960 (.A(nRowColSel_N_32), .B(RASr2), .C(Ready_N_272), 
-            .D(InitReady), .Z(n2245)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
-    defparam Ready_bdd_4_lut_1960.init = 16'h2000;
-    ORCALUT4 n2245_bdd_2_lut (.A(n2245), .B(Ready), .Z(Ready_N_268)) /* synthesis lut_function=(A+(B)) */ ;
-    defparam n2245_bdd_2_lut.init = 16'heeee;
-    ORCALUT4 n2248_bdd_4_lut_4_lut (.A(CBR), .B(RASr2), .C(Ready), .D(n2248), 
-            .Z(n2287)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A !((C+(D))+!B))) */ ;
-    defparam n2248_bdd_4_lut_4_lut.init = 16'h7f73;
-    FD1P3AX LEDEN_392 (.D(UFMSDO_N_74), .SP(RCLK_c_enable_25), .CK(RCLK_c), 
-            .Q(LEDEN)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
-    defparam LEDEN_392.GSR = "ENABLED";
-    ORCALUT4 MAin_9__I_0_400_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), 
-            .Z(RA_c_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
-    defparam MAin_9__I_0_400_i7_3_lut.init = 16'hcaca;
-    ORCALUT4 MAin_9__I_0_400_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), 
-            .Z(RA_c_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
-    defparam MAin_9__I_0_400_i6_3_lut.init = 16'hcaca;
-    CCU2 FS_577_add_4_12 (.A0(FS[10]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-         .A1(FS[11]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1878), 
-         .COUT1(n1879), .S0(n85), .S1(n84));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577_add_4_12.INIT0 = 16'hfaaa;
-    defparam FS_577_add_4_12.INIT1 = 16'hfaaa;
-    defparam FS_577_add_4_12.INJECT1_0 = "NO";
-    defparam FS_577_add_4_12.INJECT1_1 = "NO";
-    FD1P3AX CmdEnable_378 (.D(CmdEnable_N_236), .SP(PHI2_N_114_enable_8), 
-            .CK(PHI2_N_114), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
-    defparam CmdEnable_378.GSR = "ENABLED";
-    CCU2 FS_577_add_4_16 (.A0(FS[14]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-         .A1(FS[15]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1880), 
-         .COUT1(n1881), .S0(n81), .S1(n80));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577_add_4_16.INIT0 = 16'hfaaa;
-    defparam FS_577_add_4_16.INIT1 = 16'hfaaa;
-    defparam FS_577_add_4_16.INJECT1_0 = "NO";
-    defparam FS_577_add_4_16.INJECT1_1 = "NO";
-    CCU2 FS_577_add_4_14 (.A0(FS[12]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
-         .A1(FS[13]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1879), 
-         .COUT1(n1880), .S0(n83), .S1(n82));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
-    defparam FS_577_add_4_14.INIT0 = 16'hfaaa;
-    defparam FS_577_add_4_14.INIT1 = 16'hfaaa;
-    defparam FS_577_add_4_14.INJECT1_0 = "NO";
-    defparam FS_577_add_4_14.INJECT1_1 = "NO";
-    ORCALUT4 MAin_9__I_0_400_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), 
-            .Z(RA_c_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
-    defparam MAin_9__I_0_400_i3_3_lut.init = 16'hcaca;
-    ORCALUT4 i1485_3_lut (.A(n2076), .B(n1369), .C(InitReady), .Z(n1348)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
-    defparam i1485_3_lut.init = 16'hcaca;
-    ORCALUT4 i1_2_lut_2_lut (.A(nRowColSel_N_35), .B(nRowColSel_N_34), .Z(n18)) /* synthesis lut_function=(!(A+!(B))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i1_2_lut_2_lut.init = 16'h4444;
-    ORCALUT4 i1_2_lut_rep_20_2_lut (.A(nRowColSel_N_35), .B(nRCS_N_135), 
-            .Z(n2297)) /* synthesis lut_function=((B)+!A) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i1_2_lut_rep_20_2_lut.init = 16'hdddd;
-    ORCALUT4 i1062_3_lut (.A(nUFMCS_c), .B(CmdUFMCS), .C(n2308), .Z(n1369)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
-    defparam i1062_3_lut.init = 16'h3a3a;
-    ORCALUT4 MAin_9__I_0_400_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), 
-            .Z(RA_c_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
-    defparam MAin_9__I_0_400_i4_3_lut.init = 16'hcaca;
-    ORCALUT4 MAin_9__I_0_400_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), 
-            .Z(RA_c_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
-    defparam MAin_9__I_0_400_i1_3_lut.init = 16'hcaca;
-    INV i1961 (.A(nCRAS_c), .Z(nCRAS_N_9));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
-    INV i1962 (.A(PHI2_c), .Z(PHI2_N_114));   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
-    VLO i1 (.Z(GND_net));
-    TSALL TSALL_INST (.TSALL(GND_net));
-    ORCALUT4 i1070_1_lut_rep_25 (.A(nRowColSel_N_35), .Z(n2302)) /* synthesis lut_function=(!(A)) */ ;   // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
-    defparam i1070_1_lut_rep_25.init = 16'h5555;
-    PUR PUR_INST (.PUR(VCC_net));
-    defparam PUR_INST.RST_PULSE = 1;
-    ORCALUT4 i13_4_lut (.A(Bank[3]), .B(n26), .C(n2170), .D(MAin_c_5), 
-            .Z(n1285)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;
-    defparam i13_4_lut.init = 16'hdfff;
-    ORCALUT4 i12_4_lut (.A(Bank[2]), .B(n2166), .C(n2154), .D(MAin_c_6), 
-            .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
-    defparam i12_4_lut.init = 16'hbfff;
-    ORCALUT4 i1860_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), 
-            .Z(n2170)) /* synthesis lut_function=(A (B (C (D)))) */ ;
-    defparam i1860_4_lut.init = 16'h8000;
-    ORCALUT4 m0_lut (.Z(n2386)) /* synthesis lut_function=0, syn_instantiated=1 */ ;
-    defparam m0_lut.init = 16'h0000;
-    PFUMX i1934 (.BLUT(n2309), .ALUT(n2310), .C0(Ready), .Z(nRCS_N_132));
-    
-endmodule
-//
-// Verilog Description of module TSALL
-// module not written out since it is a black-box. 
-//
-
-//
-// Verilog Description of module PUR
-// module not written out since it is a black-box. 
-//
-
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf b/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf
deleted file mode 100644
index 15d3b42..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf
+++ /dev/null
@@ -1,89 +0,0 @@
-PERIOD NET "PHI2_c" 350.000000 ns  ;
-PERIOD NET "nCCAS_c" 350.000000 ns  ;
-PERIOD NET "nCRAS_c" 350.000000 ns  ;
-PERIOD NET "RCLK_c" 16.000000 ns  ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
-OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
-OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "LED" LOAD 25.000000 pF ;
-OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
-VOLTAGE 3.300 V;
-VCCIO_DERATE BANK 0 PERCENT -5; 
-VCCIO_DERATE PERCENT -5; 
-VCCIO_DERATE BANK 1 PERCENT -5; 
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-COMMERCIAL ;
\ No newline at end of file
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp b/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp
deleted file mode 100644
index 0f2c679..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp
+++ /dev/null
@@ -1,155 +0,0 @@
-VOLTAGE 3.300 V;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "LED" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ;
-PERIOD NET "PHI2_c" 350.000000 ns  ;
-PERIOD NET "nCCAS_c" 350.000000 ns  ;
-PERIOD NET "nCRAS_c" 350.000000 ns  ;
-PERIOD NET "RCLK_c" 16.000000 ns  ;
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
-OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
-OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "LED" LOAD 25.000000 pF ;
-OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
-VCCIO_DERATE BANK 0 PERCENT -5; 
-VCCIO_DERATE PERCENT -5; 
-VCCIO_DERATE BANK 1 PERCENT -5; 
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp0 b/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp0
deleted file mode 100644
index 3564159..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp0
+++ /dev/null
@@ -1,88 +0,0 @@
-PERIOD NET "PHI2_c" 350.000000 ns  ;
-PERIOD NET "nCCAS_c" 350.000000 ns  ;
-PERIOD NET "nCRAS_c" 350.000000 ns  ;
-PERIOD NET "RCLK_c" 16.000000 ns  ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
-OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
-OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "LED" LOAD 25.000000 pF ;
-OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
-VOLTAGE 3.300 V;
-VCCIO_DERATE BANK 0 PERCENT -5; 
-VCCIO_DERATE PERCENT -5; 
-VCCIO_DERATE BANK 1 PERCENT -5; 
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp2 b/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp2
deleted file mode 100644
index 0f2c679..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf.prf_cdmp2
+++ /dev/null
@@ -1,155 +0,0 @@
-VOLTAGE 3.300 V;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "LED" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ;
-IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ;
-PERIOD NET "PHI2_c" 350.000000 ns  ;
-PERIOD NET "nCCAS_c" 350.000000 ns  ;
-PERIOD NET "nCRAS_c" 350.000000 ns  ;
-PERIOD NET "RCLK_c" 16.000000 ns  ;
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
-OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
-OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
-OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
-OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
-OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
-OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
-OUTPUT PORT "LED" LOAD 25.000000 pF ;
-OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
-OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
-VCCIO_DERATE BANK 0 PERCENT -5; 
-VCCIO_DERATE PERCENT -5; 
-VCCIO_DERATE BANK 1 PERCENT -5; 
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf_hold.html b/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf_hold.html
deleted file mode 100644
index 5e379e0..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf_hold.html
+++ /dev/null
@@ -1,2080 +0,0 @@
-
-
-
-
-
-
-
-
    
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 20:38:58 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Design file:     RAM2GS
-Device,speed:    LCMXO640C,M
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            10 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
- 
-
-Passed: The following path meets requirements by 0.447ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
-   Destination:    FF         Data in        ADSubmitted_375  (to PHI2_c -)
-
-   Delay:               0.424ns  (61.8% logic, 38.2% route), 2 logic levels.
-
- Constraint Details:
-
-      0.424ns physical path delay SLICE_9 to SLICE_9 meets
-     -0.023ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.023ns) by 0.447ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R4C5C.CLK to       R4C5C.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.162       R4C5C.Q0 to R4C5C.A0       ADSubmitted
-CTOF_DEL    ---     0.092       R4C5C.A0 to       R4C5C.F0 SLICE_9
-ROUTE         1     0.000       R4C5C.F0 to R4C5C.DI0      n1355 (to PHI2_c)
-                  --------
-                    0.424   (61.8% logic, 38.2% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C5C.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C5C.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.244ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              C1Submitted_374  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
-
-   Delay:               1.215ns  (41.6% logic, 58.4% route), 4 logic levels.
-
- Constraint Details:
-
-      1.215ns physical path delay SLICE_14 to SLICE_18 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.244ns
-
- Physical Path Details:
-
-      Data path SLICE_14 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R4C5A.CLK to       R4C5A.Q0 SLICE_14 (from PHI2_c)
-ROUTE         1     0.222       R4C5A.Q0 to R4C6C.C1       C1Submitted
-CTOOFX_DEL  ---     0.151       R4C6C.C1 to     R4C6C.OFX0 i26/SLICE_70
-ROUTE         1     0.204     R4C6C.OFX0 to R4C6D.C1       n13
-CTOF_DEL    ---     0.092       R4C6D.C1 to       R4C6D.F1 SLICE_80
-ROUTE         1     0.123       R4C6D.F1 to R4C6D.C0       n6
-CTOF_DEL    ---     0.092       R4C6D.C0 to       R4C6D.F0 SLICE_80
-ROUTE         1     0.161       R4C6D.F0 to R4C6B.CE       PHI2_N_114_enable_8 (to PHI2_c)
-                  --------
-                    1.215   (41.6% logic, 58.4% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C5A.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.249ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
-   Destination:    FF         Data in        CmdSubmitted_378  (to PHI2_c -)
-
-   Delay:               1.220ns  (29.0% logic, 71.0% route), 3 logic levels.
-
- Constraint Details:
-
-      1.220ns physical path delay SLICE_18 to SLICE_19 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.249ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
-CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
-ROUTE         3     0.132       R4C5B.F1 to R4C5B.C0       XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R4C5B.C0 to       R4C5B.F0 SLICE_76
-ROUTE         2     0.463       R4C5B.F0 to R7C7C.CE       PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                    1.220   (29.0% logic, 71.0% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_19:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R7C7C.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.287ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ADSubmitted_375  (from PHI2_c -)
-   Destination:    FF         Data in        CmdEnable_373  (to PHI2_c -)
-
-   Delay:               1.258ns  (40.5% logic, 59.5% route), 4 logic levels.
-
- Constraint Details:
-
-      1.258ns physical path delay SLICE_9 to SLICE_18 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.287ns
-
- Physical Path Details:
-
-      Data path SLICE_9 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R4C5C.CLK to       R4C5C.Q0 SLICE_9 (from PHI2_c)
-ROUTE         2     0.261       R4C5C.Q0 to R4C6C.A0       ADSubmitted
-CTOOFX_DEL  ---     0.155       R4C6C.A0 to     R4C6C.OFX0 i26/SLICE_70
-ROUTE         1     0.204     R4C6C.OFX0 to R4C6D.C1       n13
-CTOF_DEL    ---     0.092       R4C6D.C1 to       R4C6D.F1 SLICE_80
-ROUTE         1     0.123       R4C6D.F1 to R4C6D.C0       n6
-CTOF_DEL    ---     0.092       R4C6D.C0 to       R4C6D.F0 SLICE_80
-ROUTE         1     0.161       R4C6D.F0 to R4C6B.CE       PHI2_N_114_enable_8 (to PHI2_c)
-                  --------
-                    1.258   (40.5% logic, 59.5% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_9:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C5C.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.372ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
-   Destination:    FF         Data in        Cmdn8MEGEN_377  (to PHI2_c -)
-
-   Delay:               1.343ns  (26.4% logic, 73.6% route), 3 logic levels.
-
- Constraint Details:
-
-      1.343ns physical path delay SLICE_18 to SLICE_23 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.372ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
-CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
-ROUTE         3     0.132       R4C5B.F1 to R4C5B.C0       XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R4C5B.C0 to       R4C5B.F0 SLICE_76
-ROUTE         2     0.586       R4C5B.F0 to R6C6A.CE       PHI2_N_114_enable_6 (to PHI2_c)
-                  --------
-                    1.343   (26.4% logic, 73.6% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_23:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R6C6A.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.447ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
-   Destination:    FF         Data in        XOR8MEG_376  (to PHI2_c -)
-
-   Delay:               1.418ns  (25.0% logic, 75.0% route), 3 logic levels.
-
- Constraint Details:
-
-      1.418ns physical path delay SLICE_18 to SLICE_94 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.447ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
-CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
-ROUTE         3     0.383       R4C5B.F1 to R7C6D.C0       XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R7C6D.C0 to       R7C6D.F0 SLICE_97
-ROUTE         1     0.410       R7C6D.F0 to R8C9B.CE       PHI2_N_114_enable_2 (to PHI2_c)
-                  --------
-                    1.418   (25.0% logic, 75.0% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R8C9B.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.656ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
-
-   Delay:               1.627ns  (21.8% logic, 78.2% route), 3 logic levels.
-
- Constraint Details:
-
-      1.627ns physical path delay SLICE_18 to SLICE_77 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.656ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
-CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
-ROUTE         3     0.335       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     0.667       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                    1.627   (21.8% logic, 78.2% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R9C9A.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 1.779ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdEnable_373  (from PHI2_c -)
-   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
-                   FF                        CmdUFMCLK_380
-
-   Delay:               1.750ns  (20.2% logic, 79.8% route), 3 logic levels.
-
- Constraint Details:
-
-      1.750ns physical path delay SLICE_18 to SLICE_83 meets
-     -0.029ns CE_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.029ns) by 1.779ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R4C6B.CLK to       R4C6B.Q0 SLICE_18 (from PHI2_c)
-ROUTE         1     0.271       R4C6B.Q0 to R4C5B.B1       CmdEnable
-CTOF_DEL    ---     0.092       R4C5B.B1 to       R4C5B.F1 SLICE_76
-ROUTE         3     0.335       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.092       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     0.790       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                    1.750   (20.2% logic, 79.8% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C6B.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R5C8B.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 175.792ns (weighted slack = 351.584ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              XOR8MEG_376  (from PHI2_c -)
-   Destination:    FF         Data in        RA11_353  (to PHI2_c +)
-
-   Delay:               0.781ns  (33.5% logic, 66.5% route), 2 logic levels.
-
- Constraint Details:
-
-      0.781ns physical path delay SLICE_94 to SLICE_31 meets
-     -0.011ns DIN_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.011ns) by 175.792ns
-
- Physical Path Details:
-
-      Data path SLICE_94 to SLICE_31:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.170      R8C9B.CLK to       R8C9B.Q0 SLICE_94 (from PHI2_c)
-ROUTE         1     0.519       R8C9B.Q0 to R2C9A.B0       XOR8MEG
-CTOF_DEL    ---     0.092       R2C9A.B0 to       R2C9A.F0 SLICE_31
-ROUTE         1     0.000       R2C9A.F0 to R2C9A.DI0      RA11_N_180 (to PHI2_c)
-                  --------
-                    0.781   (33.5% logic, 66.5% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_94:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R8C9B.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_31:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R2C9A.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 176.113ns (weighted slack = 352.226ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i3  (from PHI2_c +)
-   Destination:    FF         Data in        C1Submitted_374  (to PHI2_c -)
-
-   Delay:               1.084ns  (31.5% logic, 68.5% route), 3 logic levels.
-
- Constraint Details:
-
-      1.084ns physical path delay SLICE_92 to SLICE_14 meets
-     -0.029ns CE_HLD and
-    -175.000ns delay constraint less
-      0.000ns skew requirement (totaling -175.029ns) by 176.113ns
-
- Physical Path Details:
-
-      Data path SLICE_92 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C3A.CLK to       R2C3A.Q1 SLICE_92 (from PHI2_c)
-ROUTE         1     0.344       R2C3A.Q1 to R2C5C.A1       Bank_3
-CTOF_DEL    ---     0.092       R2C5C.A1 to       R2C5C.F1 SLICE_74
-ROUTE         5     0.132       R2C5C.F1 to R2C5C.C0       n1279
-CTOF_DEL    ---     0.092       R2C5C.C0 to       R2C5C.F0 SLICE_74
-ROUTE         1     0.267       R2C5C.F0 to R4C5A.CE       PHI2_N_114_enable_1 (to PHI2_c)
-                  --------
-                    1.084   (31.5% logic, 68.5% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_92:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R2C3A.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_14:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     1.120       39.PADDI to R4C5A.CLK      PHI2_c
-                  --------
-                    1.120   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            10 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_101 to SLICE_101 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_101 to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6C.CLK to       R2C6C.Q0 SLICE_101 (from RCLK_c)
-ROUTE         1     0.161       R2C6C.Q0 to R2C6C.M1       n705 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R2C6C.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R2C6C.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i3  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i4  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_101 to SLICE_81 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_101 to SLICE_81:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6C.CLK to       R2C6C.Q1 SLICE_101 (from RCLK_c)
-ROUTE         1     0.161       R2C6C.Q1 to R2C6B.M0       n704 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_101:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R2C6C.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_81:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R2C6B.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_80 to SLICE_80 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_80 to SLICE_80:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R4C6D.CLK to       R4C6D.Q0 SLICE_80 (from RCLK_c)
-ROUTE         1     0.161       R4C6D.Q0 to R4C6D.M1       n701 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_80:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R4C6D.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_80:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R4C6D.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_81 to SLICE_81 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_81 to SLICE_81:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6B.CLK to       R2C6B.Q0 SLICE_81 (from RCLK_c)
-ROUTE         1     0.161       R2C6B.Q0 to R2C6B.M1       n703 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_81:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R2C6B.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_81:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R2C6B.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_84 to SLICE_84 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_84 to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C5B.CLK to       R2C5B.Q0 SLICE_84 (from RCLK_c)
-ROUTE         1     0.161       R2C5B.Q0 to R2C5B.M1       n695 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R2C5B.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_84:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R2C5B.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_95 to SLICE_95 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_95 to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R8C9C.CLK to       R8C9C.Q0 SLICE_95 (from RCLK_c)
-ROUTE         1     0.161       R8C9C.Q0 to R8C9C.M1       n699 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R8C9C.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_95:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R8C9C.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_96 to SLICE_96 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_96 to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R4C7A.CLK to       R4C7A.Q0 SLICE_96 (from RCLK_c)
-ROUTE         1     0.161       R4C7A.Q0 to R4C7A.M1       n697 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R4C7A.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_96:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R4C7A.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.339ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
-
-   Delay:               0.318ns  (49.4% logic, 50.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.318ns physical path delay SLICE_99 to SLICE_99 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.339ns
-
- Physical Path Details:
-
-      Data path SLICE_99 to SLICE_99:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C7B.CLK to       R2C7B.Q0 SLICE_99 (from RCLK_c)
-ROUTE         1     0.161       R2C7B.Q0 to R2C7B.M1       n693 (to RCLK_c)
-                  --------
-                    0.318   (49.4% logic, 50.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_99:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R2C7B.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_99:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R2C7B.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.345ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RASr2_348  (from RCLK_c +)
-   Destination:    FF         Data in        RASr3_349  (to RCLK_c +)
-
-   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.324ns physical path delay SLICE_61 to SLICE_29 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
-
- Physical Path Details:
-
-      Data path SLICE_61 to SLICE_29:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R4C9B.CLK to       R4C9B.Q1 SLICE_61 (from RCLK_c)
-ROUTE        16     0.167       R4C9B.Q1 to R4C9D.M1       RASr2 (to RCLK_c)
-                  --------
-                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R4C9B.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_29:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R4C9D.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 0.345ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
-   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
-
-   Delay:               0.324ns  (48.5% logic, 51.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.324ns physical path delay SLICE_87 to SLICE_87 meets
-     -0.021ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.021ns) by 0.345ns
-
- Physical Path Details:
-
-      Data path SLICE_87 to SLICE_87:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R6C9A.CLK to       R6C9A.Q0 SLICE_87 (from RCLK_c)
-ROUTE         6     0.167       R6C9A.Q0 to R6C9A.M1       nRCS_N_135 (to RCLK_c)
-                  --------
-                    0.324   (48.5% logic, 51.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_87:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R6C9A.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_87:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     0.435       86.PADDI to R6C9A.CLK      RCLK_c
-                  --------
-                    0.435   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_368  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_55 and
-      1.462ns delay SLICE_55 to RA[10] (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to RA[10] by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C5A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     0.197       R2C5A.Q0 to 87.PADDO       n974
-DOPAD_DEL   ---     1.108       87.PADDO to         87.PAD RA[10]
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.844ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     2.357ns  (57.6% logic, 42.4% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.357ns delay SLICE_64 to RA[9] (totaling 2.844ns) meets
-      0.000ns hold offset RCLK to RA[9] by 2.844ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.473       R2C6A.Q0 to R6C9A.D1       nRowColSel
-CTOF_DEL    ---     0.092       R6C9A.D1 to       R6C9A.F1 SLICE_87
-ROUTE         1     0.527       R6C9A.F1 to 85.PADDO       RA_c_9
-DOPAD_DEL   ---     1.108       85.PADDO to         85.PAD RA[9]
-                  --------
-                    2.357   (57.6% logic, 42.4% route), 3 logic levels.
-
-Report:    2.844ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.575ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     2.088ns  (65.0% logic, 35.0% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.088ns delay SLICE_64 to RA[8] (totaling 2.575ns) meets
-      0.000ns hold offset RCLK to RA[8] by 2.575ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.375       R2C6A.Q0 to R2C2A.C0       nRowColSel
-CTOF_DEL    ---     0.092       R2C2A.C0 to       R2C2A.F0 SLICE_98
-ROUTE         1     0.356       R2C2A.F0 to 96.PADDO       RA_c_8
-DOPAD_DEL   ---     1.108       96.PADDO to         96.PAD RA[8]
-                  --------
-                    2.088   (65.0% logic, 35.0% route), 3 logic levels.
-
-Report:    2.575ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.673ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     2.186ns  (62.1% logic, 37.9% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.186ns delay SLICE_64 to RA[7] (totaling 2.673ns) meets
-      0.000ns hold offset RCLK to RA[7] by 2.673ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.226       R2C6A.Q0 to R2C6A.C1       nRowColSel
-CTOF_DEL    ---     0.092       R2C6A.C1 to       R2C6A.F1 SLICE_64
-ROUTE         1     0.603       R2C6A.F1 to 100.PADDO      RA_c_7
-DOPAD_DEL   ---     1.108      100.PADDO to        100.PAD RA[7]
-                  --------
-                    2.186   (62.1% logic, 37.9% route), 3 logic levels.
-
-Report:    2.673ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.687ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     2.200ns  (61.7% logic, 38.3% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.200ns delay SLICE_64 to RA[6] (totaling 2.687ns) meets
-      0.000ns hold offset RCLK to RA[6] by 2.687ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.375       R2C6A.Q0 to R2C2A.C1       nRowColSel
-CTOF_DEL    ---     0.092       R2C2A.C1 to       R2C2A.F1 SLICE_98
-ROUTE         1     0.468       R2C2A.F1 to 91.PADDO       RA_c_6
-DOPAD_DEL   ---     1.108       91.PADDO to         91.PAD RA[6]
-                  --------
-                    2.200   (61.7% logic, 38.3% route), 3 logic levels.
-
-Report:    2.687ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.915ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     2.428ns  (55.9% logic, 44.1% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.428ns delay SLICE_64 to RA[5] (totaling 2.915ns) meets
-      0.000ns hold offset RCLK to RA[5] by 2.915ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.447       R2C6A.Q0 to R8C9C.D1       nRowColSel
-CTOF_DEL    ---     0.092       R8C9C.D1 to       R8C9C.F1 SLICE_95
-ROUTE         1     0.624       R8C9C.F1 to 95.PADDO       RA_c_5
-DOPAD_DEL   ---     1.108       95.PADDO to         95.PAD RA[5]
-                  --------
-                    2.428   (55.9% logic, 44.1% route), 3 logic levels.
-
-Report:    2.915ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.574ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     2.087ns  (65.0% logic, 35.0% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.087ns delay SLICE_64 to RA[4] (totaling 2.574ns) meets
-      0.000ns hold offset RCLK to RA[4] by 2.574ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.375       R2C6A.Q0 to R2C2C.C1       nRowColSel
-CTOF_DEL    ---     0.092       R2C2C.C1 to       R2C2C.F1 SLICE_93
-ROUTE         1     0.355       R2C2C.F1 to 99.PADDO       RA_c_4
-DOPAD_DEL   ---     1.108       99.PADDO to         99.PAD RA[4]
-                  --------
-                    2.087   (65.0% logic, 35.0% route), 3 logic levels.
-
-Report:    2.574ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.622ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     2.135ns  (63.6% logic, 36.4% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.135ns delay SLICE_64 to RA[3] (totaling 2.622ns) meets
-      0.000ns hold offset RCLK to RA[3] by 2.622ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.310       R2C6A.Q0 to R2C3A.D1       nRowColSel
-CTOF_DEL    ---     0.092       R2C3A.D1 to       R2C3A.F1 SLICE_92
-ROUTE         1     0.468       R2C3A.F1 to 97.PADDO       RA_c_3
-DOPAD_DEL   ---     1.108       97.PADDO to         97.PAD RA[3]
-                  --------
-                    2.135   (63.6% logic, 36.4% route), 3 logic levels.
-
-Report:    2.622ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.698ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     2.211ns  (61.4% logic, 38.6% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.211ns delay SLICE_64 to RA[2] (totaling 2.698ns) meets
-      0.000ns hold offset RCLK to RA[2] by 2.698ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.375       R2C6A.Q0 to R2C2B.C0       nRowColSel
-CTOF_DEL    ---     0.092       R2C2B.C0 to       R2C2B.F0 SLICE_90
-ROUTE         1     0.479       R2C2B.F0 to 94.PADDO       RA_c_2
-DOPAD_DEL   ---     1.108       94.PADDO to         94.PAD RA[2]
-                  --------
-                    2.211   (61.4% logic, 38.6% route), 3 logic levels.
-
-Report:    2.698ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.622ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     2.135ns  (63.6% logic, 36.4% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.135ns delay SLICE_64 to RA[1] (totaling 2.622ns) meets
-      0.000ns hold offset RCLK to RA[1] by 2.622ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.310       R2C6A.Q0 to R2C3A.D0       nRowColSel
-CTOF_DEL    ---     0.092       R2C3A.D0 to       R2C3A.F0 SLICE_92
-ROUTE         1     0.468       R2C3A.F0 to 89.PADDO       RA_c_1
-DOPAD_DEL   ---     1.108       89.PADDO to         89.PAD RA[1]
-                  --------
-                    2.135   (63.6% logic, 36.4% route), 3 logic levels.
-
-Report:    2.622ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.573ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     2.086ns  (65.1% logic, 34.9% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.086ns delay SLICE_64 to RA[0] (totaling 2.573ns) meets
-      0.000ns hold offset RCLK to RA[0] by 2.573ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.375       R2C6A.Q0 to R2C2C.C0       nRowColSel
-CTOF_DEL    ---     0.092       R2C2C.C0 to       R2C2C.F0 SLICE_93
-ROUTE         1     0.354       R2C2C.F0 to 98.PADDO       RA_c_0
-DOPAD_DEL   ---     1.108       98.PADDO to         98.PAD RA[0]
-                  --------
-                    2.086   (65.1% logic, 34.9% route), 3 logic levels.
-
-Report:    2.573ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_364  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_60 and
-      1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to nRCS by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C9C.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.197       R2C9C.Q0 to 77.PADDO       nRCS_c
-DOPAD_DEL   ---     1.108       77.PADDO to         77.PAD nRCS
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_363  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_34 and
-      1.462ns delay SLICE_34 to RCKE (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to RCKE by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C7C.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     0.197       R2C7C.Q0 to 82.PADDO       RCKE_c
-DOPAD_DEL   ---     1.108       82.PADDO to         82.PAD RCKE
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.232ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_367  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     1.745ns  (72.5% logic, 27.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_63 and
-      1.745ns delay SLICE_63 to nRWE (totaling 2.232ns) meets
-      0.000ns hold offset RCLK to nRWE by 2.232ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C7A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C7A.CLK to       R2C7A.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     0.480       R2C7A.Q0 to 72.PADDO       nRWE_c
-DOPAD_DEL   ---     1.108       72.PADDO to         72.PAD nRWE
-                  --------
-                    1.745   (72.5% logic, 27.5% route), 2 logic levels.
-
-Report:    2.232ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.236ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     1.749ns  (72.3% logic, 27.7% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_61 and
-      1.749ns delay SLICE_61 to nRRAS (totaling 2.236ns) meets
-      0.000ns hold offset RCLK to nRRAS by 2.236ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R4C9B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R4C9B.CLK to       R4C9B.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     0.484       R4C9B.Q0 to 73.PADDO       nRRAS_c
-DOPAD_DEL   ---     1.108       73.PADDO to         73.PAD nRRAS
-                  --------
-                    1.749   (72.3% logic, 27.7% route), 2 logic levels.
-
-Report:    2.236ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.949ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     1.462ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_58 and
-      1.462ns delay SLICE_58 to nRCAS (totaling 1.949ns) meets
-      0.000ns hold offset RCLK to nRCAS by 1.949ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C9B.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     0.197       R2C9B.Q0 to 78.PADDO       nRCAS_c
-DOPAD_DEL   ---     1.108       78.PADDO to         78.PAD nRCAS
-                  --------
-                    1.462   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    1.949ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.711ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     2.224ns  (61.0% logic, 39.0% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.224ns delay SLICE_64 to RDQMH (totaling 2.711ns) meets
-      0.000ns hold offset RCLK to RDQMH by 2.711ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.473       R2C6A.Q0 to R6C9A.D0       nRowColSel
-CTOF_DEL    ---     0.092       R6C9A.D0 to       R6C9A.F0 SLICE_87
-ROUTE         1     0.394       R6C9A.F0 to 76.PADDO       RDQMH_c
-DOPAD_DEL   ---     1.108       76.PADDO to         76.PAD RDQMH
-                  --------
-                    2.224   (61.0% logic, 39.0% route), 3 logic levels.
-
-Report:    2.711ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.488ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     2.001ns  (67.8% logic, 32.2% route), 3 logic levels.
-
-   Clock Path Delay:    0.487ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      0.487ns delay RCLK to SLICE_64 and
-      2.001ns delay SLICE_64 to RDQML (totaling 2.488ns) meets
-      0.000ns hold offset RCLK to RDQML by 2.488ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.264         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.223       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    0.487   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.157      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.447       R2C6A.Q0 to R8C9C.D0       nRowColSel
-CTOF_DEL    ---     0.092       R8C9C.D0 to       R8C9C.F0 SLICE_95
-ROUTE         1     0.197       R8C9C.F0 to 61.PADDO       RDQML_c
-DOPAD_DEL   ---     1.108       61.PADDO to         61.PAD RDQML
-                  --------
-                    2.001   (67.8% logic, 32.2% route), 3 logic levels.
-
-Report:    2.488ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |            -|            -|   2  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |            -|            -|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |            -|            -|   1  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ;                     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.844 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.575 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.673 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.687 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.915 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.574 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.622 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.698 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.622 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.573 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.232 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.236 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     1.949 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.711 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |     0.000 ns|     2.488 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ;                        |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 520 paths, 6 nets, and 440 connections (71.54% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf_setup.html b/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf_setup.html
deleted file mode 100644
index 9090020..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/Untitled.tpf_setup.html
+++ /dev/null
@@ -1,3314 +0,0 @@
-
-
-
-
-
-
-
-
    
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
-Mon Aug 16 20:38:58 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Design file:     RAM2GS
-Device,speed:    LCMXO640C,3
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-
-Derating parameters
--------------------
-Voltage:    3.300 V
-
-
-
-================================================================================
-Preference: PERIOD NET "PHI2_c" 350.000000 ns  ;
-            10 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
- 
-
-Passed: The following path meets requirements by 163.925ns (weighted slack = 327.850ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
-                   FF                        CmdUFMCLK_380
-
-   Delay:              10.810ns  (25.8% logic, 74.2% route), 7 logic levels.
-
- Constraint Details:
-
-     10.810ns physical path delay SLICE_98 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 163.925ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_98 (from PHI2_c)
-ROUTE         1     1.018       R2C2A.Q0 to R2C2B.B1       Bank_6
-CTOF_DEL    ---     0.371       R2C2B.B1 to       R2C2B.F1 SLICE_90
-ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
-CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
-ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
-CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
-ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
-CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
-ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
-CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
-ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   10.810   (25.8% logic, 74.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 164.114ns (weighted slack = 328.228ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
-                   FF                        CmdUFMCLK_380
-
-   Delay:              10.621ns  (26.2% logic, 73.8% route), 7 logic levels.
-
- Constraint Details:
-
-     10.621ns physical path delay SLICE_98 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 164.114ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_98 (from PHI2_c)
-ROUTE         1     1.487       R2C2A.Q1 to R2C5B.A0       Bank_7
-CTOF_DEL    ---     0.371       R2C5B.A0 to       R2C5B.F0 SLICE_84
-ROUTE         1     0.497       R2C5B.F0 to R2C5B.C1       n2136
-CTOF_DEL    ---     0.371       R2C5B.C1 to       R2C5B.F1 SLICE_84
-ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
-CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
-ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
-CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
-ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
-CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
-ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   10.621   (26.2% logic, 73.8% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 164.237ns (weighted slack = 328.474ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i4  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
-                   FF                        CmdUFMCLK_380
-
-   Delay:              10.498ns  (23.0% logic, 77.0% route), 6 logic levels.
-
- Constraint Details:
-
-     10.498ns physical path delay SLICE_90 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 164.237ns
-
- Physical Path Details:
-
-      Data path SLICE_90 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_90 (from PHI2_c)
-ROUTE         1     1.643       R2C2B.Q0 to R2C6C.B0       Bank_4
-CTOF_DEL    ---     0.371       R2C6C.B0 to       R2C6C.F0 SLICE_101
-ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
-CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
-ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
-CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
-ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
-CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
-ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   10.498   (23.0% logic, 77.0% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 164.307ns (weighted slack = 328.614ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
-                   FF                        CmdUFMCLK_380
-
-   Delay:              10.428ns  (26.7% logic, 73.3% route), 7 logic levels.
-
- Constraint Details:
-
-     10.428ns physical path delay SLICE_90 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 164.307ns
-
- Physical Path Details:
-
-      Data path SLICE_90 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q1 SLICE_90 (from PHI2_c)
-ROUTE         1     0.636       R2C2B.Q1 to R2C2B.A1       Bank_5
-CTOF_DEL    ---     0.371       R2C2B.A1 to       R2C2B.F1 SLICE_90
-ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
-CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
-ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
-CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
-ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
-CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
-ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
-CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
-ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   10.428   (26.7% logic, 73.3% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 164.317ns (weighted slack = 328.634ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i0  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
-                   FF                        CmdUFMCLK_380
-
-   Delay:              10.418ns  (26.7% logic, 73.3% route), 7 logic levels.
-
- Constraint Details:
-
-     10.418ns physical path delay SLICE_93 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 164.317ns
-
- Physical Path Details:
-
-      Data path SLICE_93 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q0 SLICE_93 (from PHI2_c)
-ROUTE         1     0.626       R2C2C.Q0 to R2C2B.D1       Bank_0
-CTOF_DEL    ---     0.371       R2C2B.D1 to       R2C2B.F1 SLICE_90
-ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
-CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
-ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
-CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
-ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
-CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
-ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
-CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
-ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   10.418   (26.7% logic, 73.3% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R2C2C.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 164.386ns (weighted slack = 328.772ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i6  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
-
-   Delay:              10.349ns  (26.9% logic, 73.1% route), 7 logic levels.
-
- Constraint Details:
-
-     10.349ns physical path delay SLICE_98 to SLICE_77 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 164.386ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_98 (from PHI2_c)
-ROUTE         1     1.018       R2C2A.Q0 to R2C2B.B1       Bank_6
-CTOF_DEL    ---     0.371       R2C2B.B1 to       R2C2B.F1 SLICE_90
-ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
-CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
-ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
-CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
-ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
-CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
-ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
-CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
-ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   10.349   (26.9% logic, 73.1% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 164.575ns (weighted slack = 329.150ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i7  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
-
-   Delay:              10.160ns  (27.4% logic, 72.6% route), 7 logic levels.
-
- Constraint Details:
-
-     10.160ns physical path delay SLICE_98 to SLICE_77 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 164.575ns
-
- Physical Path Details:
-
-      Data path SLICE_98 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_98 (from PHI2_c)
-ROUTE         1     1.487       R2C2A.Q1 to R2C5B.A0       Bank_7
-CTOF_DEL    ---     0.371       R2C5B.A0 to       R2C5B.F0 SLICE_84
-ROUTE         1     0.497       R2C5B.F0 to R2C5B.C1       n2136
-CTOF_DEL    ---     0.371       R2C5B.C1 to       R2C5B.F1 SLICE_84
-ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
-CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
-ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
-CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
-ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
-CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
-ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   10.160   (27.4% logic, 72.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_98:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R2C2A.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 164.629ns (weighted slack = 329.258ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i1  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMCS_379  (to PHI2_c -)
-                   FF                        CmdUFMCLK_380
-
-   Delay:              10.106ns  (23.9% logic, 76.1% route), 6 logic levels.
-
- Constraint Details:
-
-     10.106ns physical path delay SLICE_93 to SLICE_83 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 164.629ns
-
- Physical Path Details:
-
-      Data path SLICE_93 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2C.CLK to       R2C2C.Q1 SLICE_93 (from PHI2_c)
-ROUTE         1     1.251       R2C2C.Q1 to R2C6C.D0       Bank_1
-CTOF_DEL    ---     0.371       R2C6C.D0 to       R2C6C.F0 SLICE_101
-ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
-CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
-ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
-CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
-ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
-CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
-ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     3.021       R5C2A.F1 to R5C8B.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   10.106   (23.9% logic, 76.1% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_93:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R2C2C.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_83:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R5C8B.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 164.698ns (weighted slack = 329.396ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i4  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
-
-   Delay:              10.037ns  (24.1% logic, 75.9% route), 6 logic levels.
-
- Constraint Details:
-
-     10.037ns physical path delay SLICE_90 to SLICE_77 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 164.698ns
-
- Physical Path Details:
-
-      Data path SLICE_90 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q0 SLICE_90 (from PHI2_c)
-ROUTE         1     1.643       R2C2B.Q0 to R2C6C.B0       Bank_4
-CTOF_DEL    ---     0.371       R2C6C.B0 to       R2C6C.F0 SLICE_101
-ROUTE         1     0.893       R2C6C.F0 to R2C5C.C1       n2162
-CTOF_DEL    ---     0.371       R2C5C.C1 to       R2C5C.F1 SLICE_74
-ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
-CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
-ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
-CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
-ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                   10.037   (24.1% logic, 75.9% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 164.768ns (weighted slack = 329.536ns)
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              Bank_i5  (from PHI2_c +)
-   Destination:    FF         Data in        CmdUFMSDI_381  (to PHI2_c -)
-
-   Delay:               9.967ns  (28.0% logic, 72.0% route), 7 logic levels.
-
- Constraint Details:
-
-      9.967ns physical path delay SLICE_90 to SLICE_77 meets
-    175.000ns delay constraint less
-      0.000ns skew and
-      0.265ns CE_SET requirement (totaling 174.735ns) by 164.768ns
-
- Physical Path Details:
-
-      Data path SLICE_90 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C2B.CLK to       R2C2B.Q1 SLICE_90 (from PHI2_c)
-ROUTE         1     0.636       R2C2B.Q1 to R2C2B.A1       Bank_5
-CTOF_DEL    ---     0.371       R2C2B.A1 to       R2C2B.F1 SLICE_90
-ROUTE         1     1.155       R2C2B.F1 to R2C5B.D1       n2160
-CTOF_DEL    ---     0.371       R2C5B.D1 to       R2C5B.F1 SLICE_84
-ROUTE         1     0.304       R2C5B.F1 to R2C5C.D1       n26
-CTOF_DEL    ---     0.371       R2C5C.D1 to       R2C5C.F1 SLICE_74
-ROUTE         5     0.924       R2C5C.F1 to R4C5C.C1       n1279
-CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_9
-ROUTE         2     0.320       R4C5C.F1 to R4C5B.D1       n2288
-CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_76
-ROUTE         3     1.282       R4C5B.F1 to R5C2A.D1       XOR8MEG_N_112
-CTOF_DEL    ---     0.371       R5C2A.D1 to       R5C2A.F1 SLICE_73
-ROUTE         2     2.560       R5C2A.F1 to R9C9A.CE       PHI2_N_114_enable_7 (to PHI2_c)
-                  --------
-                    9.967   (28.0% logic, 72.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path PHI2 to SLICE_90:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R2C2B.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path PHI2 to SLICE_77:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        14     3.671       39.PADDI to R9C9A.CLK      PHI2_c
-                  --------
-                    3.671   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   22.150ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCCAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_73
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "nCRAS_c" 350.000000 ns  ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 348.000ns
-         The internal maximum frequency of the following component is 500.000 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    FSLICE     CLK            SLICE_74
-
-   Delay:               2.000ns -- based on Minimum Pulse Width
-
-Report:    2.000ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: PERIOD NET "RCLK_c" 16.000000 ns  ;
-            10 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
- 
-
-Passed: The following path meets requirements by 7.341ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
-
-   Delay:               8.415ns  (28.7% logic, 71.3% route), 6 logic levels.
-
- Constraint Details:
-
-      8.415ns physical path delay SLICE_7 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.341ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
-ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
-CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
-ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
-CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
-ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
-CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
-ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
-CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
-ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
-CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
-ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    8.415   (28.7% logic, 71.3% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 7.520ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
-
-   Delay:               8.236ns  (29.3% logic, 70.7% route), 6 logic levels.
-
- Constraint Details:
-
-      8.236ns physical path delay SLICE_7 to SLICE_85 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.520ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
-ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
-CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
-ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
-CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
-ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
-CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
-ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
-CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
-ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
-CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
-ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.236   (29.3% logic, 70.7% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 7.549ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
-
-   Delay:               8.207ns  (29.4% logic, 70.6% route), 6 logic levels.
-
- Constraint Details:
-
-      8.207ns physical path delay SLICE_7 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.549ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q0 SLICE_7 (from RCLK_c)
-ROUTE         3     1.267       R8C8D.Q0 to R8C9D.C1       FS_14
-CTOF_DEL    ---     0.371       R8C9D.C1 to       R8C9D.F1 SLICE_78
-ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
-CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
-ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
-CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
-ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
-CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
-ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
-CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
-ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    8.207   (29.4% logic, 70.6% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 7.728ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i14  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
-
-   Delay:               8.028ns  (30.1% logic, 69.9% route), 6 logic levels.
-
- Constraint Details:
-
-      8.028ns physical path delay SLICE_7 to SLICE_85 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.728ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q0 SLICE_7 (from RCLK_c)
-ROUTE         3     1.267       R8C8D.Q0 to R8C9D.C1       FS_14
-CTOF_DEL    ---     0.371       R8C9D.C1 to       R8C9D.F1 SLICE_78
-ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
-CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
-ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
-CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
-ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
-CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
-ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
-CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
-ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    8.028   (30.1% logic, 69.9% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 7.768ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
-
-   Delay:               7.988ns  (30.2% logic, 69.8% route), 6 logic levels.
-
- Constraint Details:
-
-      7.988ns physical path delay SLICE_8 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.768ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q1 SLICE_8 (from RCLK_c)
-ROUTE         3     1.048       R8C8C.Q1 to R8C9D.A1       FS_13
-CTOF_DEL    ---     0.371       R8C9D.A1 to       R8C9D.F1 SLICE_78
-ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
-CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
-ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
-CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
-ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
-CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
-ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
-CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
-ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    7.988   (30.2% logic, 69.8% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 7.947ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i13  (from RCLK_c +)
-   Destination:    FF         Data in        LEDEN_386  (to RCLK_c +)
-
-   Delay:               7.809ns  (30.9% logic, 69.1% route), 6 logic levels.
-
- Constraint Details:
-
-      7.809ns physical path delay SLICE_8 to SLICE_85 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 7.947ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q1 SLICE_8 (from RCLK_c)
-ROUTE         3     1.048       R8C8C.Q1 to R8C9D.A1       FS_13
-CTOF_DEL    ---     0.371       R8C9D.A1 to       R8C9D.F1 SLICE_78
-ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
-CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
-ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
-CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
-ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
-CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
-ROUTE         2     0.903       R9C9A.F1 to R10C9A.C1      n2111
-CTOF_DEL    ---     0.371      R10C9A.C1 to      R10C9A.F1 SLICE_100
-ROUTE         1     0.703      R10C9A.F1 to R9C9D.CE       RCLK_c_enable_25 (to RCLK_c)
-                  --------
-                    7.809   (30.9% logic, 69.1% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_85:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R9C9D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 8.079ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i15  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
-
-   Delay:               7.677ns  (26.6% logic, 73.4% route), 5 logic levels.
-
- Constraint Details:
-
-      7.677ns physical path delay SLICE_7 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 8.079ns
-
- Physical Path Details:
-
-      Data path SLICE_7 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C8D.CLK to       R8C8D.Q1 SLICE_7 (from RCLK_c)
-ROUTE         3     1.475       R8C8D.Q1 to R8C9D.B1       FS_15
-CTOF_DEL    ---     0.371       R8C9D.B1 to       R8C9D.F1 SLICE_78
-ROUTE         3     0.989       R8C9D.F1 to R8C9B.A1       n10
-CTOF_DEL    ---     0.371       R8C9B.A1 to       R8C9B.F1 SLICE_94
-ROUTE         1     1.384       R8C9B.F1 to R9C9A.A1       n2292
-CTOF_DEL    ---     0.371       R9C9A.A1 to       R9C9A.F1 SLICE_77
-ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
-CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
-ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    7.677   (26.6% logic, 73.4% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_7:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R8C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 8.092ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i12  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
-
-   Delay:               7.664ns  (31.5% logic, 68.5% route), 6 logic levels.
-
- Constraint Details:
-
-      7.664ns physical path delay SLICE_8 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 8.092ns
-
- Physical Path Details:
-
-      Data path SLICE_8 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C8C.CLK to       R8C8C.Q0 SLICE_8 (from RCLK_c)
-ROUTE         3     0.724       R8C8C.Q0 to R8C9D.D1       FS_12
-CTOF_DEL    ---     0.371       R8C9D.D1 to       R8C9D.F1 SLICE_78
-ROUTE         3     1.057       R8C9D.F1 to R6C9B.A1       n10
-CTOF_DEL    ---     0.371       R6C9B.A1 to       R6C9B.F1 SLICE_75
-ROUTE         4     0.528       R6C9B.F1 to R6C9B.C0       n2298
-CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_75
-ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
-CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
-ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
-CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
-ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    7.664   (31.5% logic, 68.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_8:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R8C8C.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 8.177ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i1  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
-
-   Delay:               7.579ns  (27.0% logic, 73.0% route), 5 logic levels.
-
- Constraint Details:
-
-      7.579ns physical path delay SLICE_5 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 8.177ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C7A.CLK to       R8C7A.Q1 SLICE_5 (from RCLK_c)
-ROUTE         2     1.108       R8C7A.Q1 to R7C7D.B1       FS_1
-CTOF_DEL    ---     0.371       R7C7D.B1 to       R7C7D.F1 SLICE_68
-ROUTE         1     1.487       R7C7D.F1 to R6C9B.A0       n2164
-CTOF_DEL    ---     0.371       R6C9B.A0 to       R6C9B.F0 SLICE_75
-ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
-CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
-ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
-CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
-ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    7.579   (27.0% logic, 73.0% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R8C7A.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
- 
-
-Passed: The following path meets requirements by 8.243ns
- 
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS_571__i2  (from RCLK_c +)
-   Destination:    FF         Data in        n8MEGEN_385  (to RCLK_c +)
-
-   Delay:               7.513ns  (27.2% logic, 72.8% route), 5 logic levels.
-
- Constraint Details:
-
-      7.513ns physical path delay SLICE_4 to SLICE_56 meets
-     16.000ns delay constraint less
-      0.000ns skew and
-      0.244ns CE_SET requirement (totaling 15.756ns) by 8.243ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R8C7B.CLK to       R8C7B.Q0 SLICE_4 (from RCLK_c)
-ROUTE         2     1.042       R8C7B.Q0 to R7C7D.A1       FS_2
-CTOF_DEL    ---     0.371       R7C7D.A1 to       R7C7D.F1 SLICE_68
-ROUTE         1     1.487       R7C7D.F1 to R6C9B.A0       n2164
-CTOF_DEL    ---     0.371       R6C9B.A0 to       R6C9B.F0 SLICE_75
-ROUTE         1     1.155       R6C9B.F0 to R9C9A.D1       n11
-CTOF_DEL    ---     0.371       R9C9A.D1 to       R9C9A.F1 SLICE_77
-ROUTE         2     0.712       R9C9A.F1 to R9C9A.B0       n2111
-CTOF_DEL    ---     0.371       R9C9A.B0 to       R9C9A.F0 SLICE_77
-ROUTE         1     1.073       R9C9A.F0 to R9C8D.CE       RCLK_c_enable_7 (to RCLK_c)
-                  --------
-                    7.513   (27.2% logic, 72.8% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path RCLK to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R8C7B.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path RCLK to SLICE_56:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        39     1.425       86.PADDI to R9C8D.CLK      RCLK_c
-                  --------
-                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:    8.659ns is the minimum period for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_368  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_55 and
-      5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
-     12.500ns offset RCLK to RA[10] by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C5A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     0.817       R2C5A.Q0 to 87.PADDO       n974
-DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 6.396ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA10_368  (from RCLK_c +)
-   Destination:    Port       Pad            RA[10]
-
-   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_55 and
-      4.797ns delay SLICE_55 to RA[10] (totaling 6.396ns) meets
-      0.000ns hold offset RCLK to RA[10] by 6.396ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C5A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_55 to RA[10]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C5A.CLK to       R2C5A.Q0 SLICE_55 (from RCLK_c)
-ROUTE         1     0.646       R2C5A.Q0 to 87.PADDO       n974
-DOPAD_DEL   ---     3.636       87.PADDO to         87.PAD RA[10]
-                  --------
-                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    6.396ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.477ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     8.535ns  (53.5% logic, 46.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.535ns delay SLICE_64 to RA[9] (totaling 11.023ns) meets
-     12.500ns offset RCLK to RA[9] by 1.477ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.796       R2C6A.Q0 to R6C9A.D1       nRowColSel
-CTOF_DEL    ---     0.371       R6C9A.D1 to       R6C9A.F1 SLICE_87
-ROUTE         1     2.172       R6C9A.F1 to 85.PADDO       RA_c_9
-DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
-                  --------
-                    8.535   (53.5% logic, 46.5% route), 3 logic levels.
-
-Report:   11.023ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 9.323ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[9]
-
-   Data Path Delay:     7.724ns  (57.6% logic, 42.4% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      7.724ns delay SLICE_64 to RA[9] (totaling 9.323ns) meets
-      0.000ns hold offset RCLK to RA[9] by 9.323ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[9]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.549       R2C6A.Q0 to R6C9A.D1       nRowColSel
-CTOF_DEL    ---     0.301       R6C9A.D1 to       R6C9A.F1 SLICE_87
-ROUTE         1     1.723       R6C9A.F1 to 85.PADDO       RA_c_9
-DOPAD_DEL   ---     3.636       85.PADDO to         85.PAD RA[9]
-                  --------
-                    7.724   (57.6% logic, 42.4% route), 3 logic levels.
-
-Report:    9.323ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.460ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     7.552ns  (60.5% logic, 39.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.552ns delay SLICE_64 to RA[8] (totaling 10.040ns) meets
-     12.500ns offset RCLK to RA[8] by 2.460ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.459       R2C6A.Q0 to R2C2A.C0       nRowColSel
-CTOF_DEL    ---     0.371       R2C2A.C0 to       R2C2A.F0 SLICE_98
-ROUTE         1     1.526       R2C2A.F0 to 96.PADDO       RA_c_8
-DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
-                  --------
-                    7.552   (60.5% logic, 39.5% route), 3 logic levels.
-
-Report:   10.040ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.446ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[8]
-
-   Data Path Delay:     6.847ns  (65.0% logic, 35.0% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      6.847ns delay SLICE_64 to RA[8] (totaling 8.446ns) meets
-      0.000ns hold offset RCLK to RA[8] by 8.446ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[8]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.230       R2C6A.Q0 to R2C2A.C0       nRowColSel
-CTOF_DEL    ---     0.301       R2C2A.C0 to       R2C2A.F0 SLICE_98
-ROUTE         1     1.165       R2C2A.F0 to 96.PADDO       RA_c_8
-DOPAD_DEL   ---     3.636       96.PADDO to         96.PAD RA[8]
-                  --------
-                    6.847   (65.0% logic, 35.0% route), 3 logic levels.
-
-Report:    8.446ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.106ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     7.906ns  (57.8% logic, 42.2% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.906ns delay SLICE_64 to RA[7] (totaling 10.394ns) meets
-     12.500ns offset RCLK to RA[7] by 2.106ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.895       R2C6A.Q0 to R2C6A.C1       nRowColSel
-CTOF_DEL    ---     0.371       R2C6A.C1 to       R2C6A.F1 SLICE_64
-ROUTE         1     2.444       R2C6A.F1 to 100.PADDO      RA_c_7
-DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
-                  --------
-                    7.906   (57.8% logic, 42.2% route), 3 logic levels.
-
-Report:   10.394ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.766ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[7]
-
-   Data Path Delay:     7.167ns  (62.1% logic, 37.9% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      7.167ns delay SLICE_64 to RA[7] (totaling 8.766ns) meets
-      0.000ns hold offset RCLK to RA[7] by 8.766ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[7]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     0.741       R2C6A.Q0 to R2C6A.C1       nRowColSel
-CTOF_DEL    ---     0.301       R2C6A.C1 to       R2C6A.F1 SLICE_64
-ROUTE         1     1.974       R2C6A.F1 to 100.PADDO      RA_c_7
-DOPAD_DEL   ---     3.636      100.PADDO to        100.PAD RA[7]
-                  --------
-                    7.167   (62.1% logic, 37.9% route), 3 logic levels.
-
-Report:    8.766ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.002ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     8.010ns  (57.0% logic, 43.0% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.010ns delay SLICE_64 to RA[6] (totaling 10.498ns) meets
-     12.500ns offset RCLK to RA[6] by 2.002ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.459       R2C6A.Q0 to R2C2A.C1       nRowColSel
-CTOF_DEL    ---     0.371       R2C2A.C1 to       R2C2A.F1 SLICE_98
-ROUTE         1     1.984       R2C2A.F1 to 91.PADDO       RA_c_6
-DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
-                  --------
-                    8.010   (57.0% logic, 43.0% route), 3 logic levels.
-
-Report:   10.498ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.813ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[6]
-
-   Data Path Delay:     7.214ns  (61.7% logic, 38.3% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      7.214ns delay SLICE_64 to RA[6] (totaling 8.813ns) meets
-      0.000ns hold offset RCLK to RA[6] by 8.813ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[6]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.230       R2C6A.Q0 to R2C2A.C1       nRowColSel
-CTOF_DEL    ---     0.301       R2C2A.C1 to       R2C2A.F1 SLICE_98
-ROUTE         1     1.532       R2C2A.F1 to 91.PADDO       RA_c_6
-DOPAD_DEL   ---     3.636       91.PADDO to         91.PAD RA[6]
-                  --------
-                    7.214   (61.7% logic, 38.3% route), 3 logic levels.
-
-Report:    8.813ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.141ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     8.871ns  (51.5% logic, 48.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.871ns delay SLICE_64 to RA[5] (totaling 11.359ns) meets
-     12.500ns offset RCLK to RA[5] by 1.141ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.736       R2C6A.Q0 to R8C9C.D1       nRowColSel
-CTOF_DEL    ---     0.371       R8C9C.D1 to       R8C9C.F1 SLICE_95
-ROUTE         1     2.568       R8C9C.F1 to 95.PADDO       RA_c_5
-DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
-                  --------
-                    8.871   (51.5% logic, 48.5% route), 3 logic levels.
-
-Report:   11.359ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 9.559ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[5]
-
-   Data Path Delay:     7.960ns  (55.9% logic, 44.1% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      7.960ns delay SLICE_64 to RA[5] (totaling 9.559ns) meets
-      0.000ns hold offset RCLK to RA[5] by 9.559ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[5]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.466       R2C6A.Q0 to R8C9C.D1       nRowColSel
-CTOF_DEL    ---     0.301       R8C9C.D1 to       R8C9C.F1 SLICE_95
-ROUTE         1     2.042       R8C9C.F1 to 95.PADDO       RA_c_5
-DOPAD_DEL   ---     3.636       95.PADDO to         95.PAD RA[5]
-                  --------
-                    7.960   (55.9% logic, 44.1% route), 3 logic levels.
-
-Report:    9.559ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.458ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     7.554ns  (60.5% logic, 39.5% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.554ns delay SLICE_64 to RA[4] (totaling 10.042ns) meets
-     12.500ns offset RCLK to RA[4] by 2.458ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.459       R2C6A.Q0 to R2C2C.C1       nRowColSel
-CTOF_DEL    ---     0.371       R2C2C.C1 to       R2C2C.F1 SLICE_93
-ROUTE         1     1.528       R2C2C.F1 to 99.PADDO       RA_c_4
-DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
-                  --------
-                    7.554   (60.5% logic, 39.5% route), 3 logic levels.
-
-Report:   10.042ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.445ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[4]
-
-   Data Path Delay:     6.846ns  (65.0% logic, 35.0% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      6.846ns delay SLICE_64 to RA[4] (totaling 8.445ns) meets
-      0.000ns hold offset RCLK to RA[4] by 8.445ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[4]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.230       R2C6A.Q0 to R2C2C.C1       nRowColSel
-CTOF_DEL    ---     0.301       R2C2C.C1 to       R2C2C.F1 SLICE_93
-ROUTE         1     1.164       R2C2C.F1 to 99.PADDO       RA_c_4
-DOPAD_DEL   ---     3.636       99.PADDO to         99.PAD RA[4]
-                  --------
-                    6.846   (65.0% logic, 35.0% route), 3 logic levels.
-
-Report:    8.445ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.216ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     7.796ns  (58.6% logic, 41.4% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.796ns delay SLICE_64 to RA[3] (totaling 10.284ns) meets
-     12.500ns offset RCLK to RA[3] by 2.216ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.245       R2C6A.Q0 to R2C3A.D1       nRowColSel
-CTOF_DEL    ---     0.371       R2C3A.D1 to       R2C3A.F1 SLICE_92
-ROUTE         1     1.984       R2C3A.F1 to 97.PADDO       RA_c_3
-DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
-                  --------
-                    7.796   (58.6% logic, 41.4% route), 3 logic levels.
-
-Report:   10.284ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.599ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[3]
-
-   Data Path Delay:     7.000ns  (63.6% logic, 36.4% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      7.000ns delay SLICE_64 to RA[3] (totaling 8.599ns) meets
-      0.000ns hold offset RCLK to RA[3] by 8.599ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[3]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.016       R2C6A.Q0 to R2C3A.D1       nRowColSel
-CTOF_DEL    ---     0.301       R2C3A.D1 to       R2C3A.F1 SLICE_92
-ROUTE         1     1.532       R2C3A.F1 to 97.PADDO       RA_c_3
-DOPAD_DEL   ---     3.636       97.PADDO to         97.PAD RA[3]
-                  --------
-                    7.000   (63.6% logic, 36.4% route), 3 logic levels.
-
-Report:    8.599ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     8.013ns  (57.0% logic, 43.0% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.013ns delay SLICE_64 to RA[2] (totaling 10.501ns) meets
-     12.500ns offset RCLK to RA[2] by 1.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.459       R2C6A.Q0 to R2C2B.C0       nRowColSel
-CTOF_DEL    ---     0.371       R2C2B.C0 to       R2C2B.F0 SLICE_90
-ROUTE         1     1.987       R2C2B.F0 to 94.PADDO       RA_c_2
-DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
-                  --------
-                    8.013   (57.0% logic, 43.0% route), 3 logic levels.
-
-Report:   10.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.849ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[2]
-
-   Data Path Delay:     7.250ns  (61.4% logic, 38.6% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      7.250ns delay SLICE_64 to RA[2] (totaling 8.849ns) meets
-      0.000ns hold offset RCLK to RA[2] by 8.849ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[2]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.230       R2C6A.Q0 to R2C2B.C0       nRowColSel
-CTOF_DEL    ---     0.301       R2C2B.C0 to       R2C2B.F0 SLICE_90
-ROUTE         1     1.568       R2C2B.F0 to 94.PADDO       RA_c_2
-DOPAD_DEL   ---     3.636       94.PADDO to         94.PAD RA[2]
-                  --------
-                    7.250   (61.4% logic, 38.6% route), 3 logic levels.
-
-Report:    8.849ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.216ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     7.796ns  (58.6% logic, 41.4% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.796ns delay SLICE_64 to RA[1] (totaling 10.284ns) meets
-     12.500ns offset RCLK to RA[1] by 2.216ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.245       R2C6A.Q0 to R2C3A.D0       nRowColSel
-CTOF_DEL    ---     0.371       R2C3A.D0 to       R2C3A.F0 SLICE_92
-ROUTE         1     1.984       R2C3A.F0 to 89.PADDO       RA_c_1
-DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
-                  --------
-                    7.796   (58.6% logic, 41.4% route), 3 logic levels.
-
-Report:   10.284ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.599ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[1]
-
-   Data Path Delay:     7.000ns  (63.6% logic, 36.4% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      7.000ns delay SLICE_64 to RA[1] (totaling 8.599ns) meets
-      0.000ns hold offset RCLK to RA[1] by 8.599ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[1]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.016       R2C6A.Q0 to R2C3A.D0       nRowColSel
-CTOF_DEL    ---     0.301       R2C3A.D0 to       R2C3A.F0 SLICE_92
-ROUTE         1     1.532       R2C3A.F0 to 89.PADDO       RA_c_1
-DOPAD_DEL   ---     3.636       89.PADDO to         89.PAD RA[1]
-                  --------
-                    7.000   (63.6% logic, 36.4% route), 3 logic levels.
-
-Report:    8.599ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.454ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     7.558ns  (60.4% logic, 39.6% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.558ns delay SLICE_64 to RA[0] (totaling 10.046ns) meets
-     12.500ns offset RCLK to RA[0] by 2.454ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.459       R2C6A.Q0 to R2C2C.C0       nRowColSel
-CTOF_DEL    ---     0.371       R2C2C.C0 to       R2C2C.F0 SLICE_93
-ROUTE         1     1.532       R2C2C.F0 to 98.PADDO       RA_c_0
-DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
-                  --------
-                    7.558   (60.4% logic, 39.6% route), 3 logic levels.
-
-Report:   10.046ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.442ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RA[0]
-
-   Data Path Delay:     6.843ns  (65.1% logic, 34.9% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      6.843ns delay SLICE_64 to RA[0] (totaling 8.442ns) meets
-      0.000ns hold offset RCLK to RA[0] by 8.442ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RA[0]:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.230       R2C6A.Q0 to R2C2C.C0       nRowColSel
-CTOF_DEL    ---     0.301       R2C2C.C0 to       R2C2C.F0 SLICE_93
-ROUTE         1     1.161       R2C2C.F0 to 98.PADDO       RA_c_0
-DOPAD_DEL   ---     3.636       98.PADDO to         98.PAD RA[0]
-                  --------
-                    6.843   (65.1% logic, 34.9% route), 3 logic levels.
-
-Report:    8.442ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_364  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_60 and
-      5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
-     12.500ns offset RCLK to nRCS by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C9C.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.817       R2C9C.Q0 to 77.PADDO       nRCS_c
-DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 6.396ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCS_364  (from RCLK_c +)
-   Destination:    Port       Pad            nRCS
-
-   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_60 and
-      4.797ns delay SLICE_60 to nRCS (totaling 6.396ns) meets
-      0.000ns hold offset RCLK to nRCS by 6.396ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_60:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C9C.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_60 to nRCS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C9C.CLK to       R2C9C.Q0 SLICE_60 (from RCLK_c)
-ROUTE         1     0.646       R2C9C.Q0 to 77.PADDO       nRCS_c
-DOPAD_DEL   ---     3.636       77.PADDO to         77.PAD nRCS
-                  --------
-                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    6.396ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_363  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_34 and
-      5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
-     12.500ns offset RCLK to RCKE by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C7C.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     0.817       R2C7C.Q0 to 82.PADDO       RCKE_c
-DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 6.396ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RCKE_363  (from RCLK_c +)
-   Destination:    Port       Pad            RCKE
-
-   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_34 and
-      4.797ns delay SLICE_34 to RCKE (totaling 6.396ns) meets
-      0.000ns hold offset RCLK to RCKE by 6.396ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C7C.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_34 to RCKE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C7C.CLK to       R2C7C.Q0 SLICE_34 (from RCLK_c)
-ROUTE         4     0.646       R2C7C.Q0 to 82.PADDO       RCKE_c
-DOPAD_DEL   ---     3.636       82.PADDO to         82.PAD RCKE
-                  --------
-                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    6.396ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.833ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_367  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     6.179ns  (67.9% logic, 32.1% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_63 and
-      6.179ns delay SLICE_63 to nRWE (totaling 8.667ns) meets
-     12.500ns offset RCLK to nRWE by 3.833ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C7A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C7A.CLK to       R2C7A.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     1.983       R2C7A.Q0 to 72.PADDO       nRWE_c
-DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
-                  --------
-                    6.179   (67.9% logic, 32.1% route), 2 logic levels.
-
-Report:    8.667ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 7.321ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRWE_367  (from RCLK_c +)
-   Destination:    Port       Pad            nRWE
-
-   Data Path Delay:     5.722ns  (72.5% logic, 27.5% route), 2 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_63 and
-      5.722ns delay SLICE_63 to nRWE (totaling 7.321ns) meets
-      0.000ns hold offset RCLK to nRWE by 7.321ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_63:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C7A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_63 to nRWE:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C7A.CLK to       R2C7A.Q0 SLICE_63 (from RCLK_c)
-ROUTE         1     1.571       R2C7A.Q0 to 72.PADDO       nRWE_c
-DOPAD_DEL   ---     3.636       72.PADDO to         72.PAD nRWE
-                  --------
-                    5.722   (72.5% logic, 27.5% route), 2 logic levels.
-
-Report:    7.321ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 3.813ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     6.199ns  (67.7% logic, 32.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_61 and
-      6.199ns delay SLICE_61 to nRRAS (totaling 8.687ns) meets
-     12.500ns offset RCLK to nRRAS by 3.813ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R4C9B.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R4C9B.CLK to       R4C9B.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     2.003       R4C9B.Q0 to 73.PADDO       nRRAS_c
-DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
-                  --------
-                    6.199   (67.7% logic, 32.3% route), 2 logic levels.
-
-Report:    8.687ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 7.334ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRRAS_365  (from RCLK_c +)
-   Destination:    Port       Pad            nRRAS
-
-   Data Path Delay:     5.735ns  (72.4% logic, 27.6% route), 2 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_61 and
-      5.735ns delay SLICE_61 to nRRAS (totaling 7.334ns) meets
-      0.000ns hold offset RCLK to nRRAS by 7.334ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_61:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R4C9B.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_61 to nRRAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R4C9B.CLK to       R4C9B.Q0 SLICE_61 (from RCLK_c)
-ROUTE         2     1.584       R4C9B.Q0 to 73.PADDO       nRRAS_c
-DOPAD_DEL   ---     3.636       73.PADDO to         73.PAD nRRAS
-                  --------
-                    5.735   (72.4% logic, 27.6% route), 2 logic levels.
-
-Report:    7.334ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 4.999ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     5.013ns  (83.7% logic, 16.3% route), 2 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_58 and
-      5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
-     12.500ns offset RCLK to nRCAS by 4.999ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C9B.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     0.817       R2C9B.Q0 to 78.PADDO       nRCAS_c
-DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
-                  --------
-                    5.013   (83.7% logic, 16.3% route), 2 logic levels.
-
-Report:    7.501ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 6.396ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRCAS_366  (from RCLK_c +)
-   Destination:    Port       Pad            nRCAS
-
-   Data Path Delay:     4.797ns  (86.5% logic, 13.5% route), 2 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_58 and
-      4.797ns delay SLICE_58 to nRCAS (totaling 6.396ns) meets
-      0.000ns hold offset RCLK to nRCAS by 6.396ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_58:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C9B.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_58 to nRCAS:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C9B.CLK to       R2C9B.Q0 SLICE_58 (from RCLK_c)
-ROUTE         1     0.646       R2C9B.Q0 to 78.PADDO       nRCAS_c
-DOPAD_DEL   ---     3.636       78.PADDO to         78.PAD nRCAS
-                  --------
-                    4.797   (86.5% logic, 13.5% route), 2 logic levels.
-
-Report:    6.396ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.989ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     8.023ns  (56.9% logic, 43.1% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      8.023ns delay SLICE_64 to RDQMH (totaling 10.511ns) meets
-     12.500ns offset RCLK to RDQMH by 1.989ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.796       R2C6A.Q0 to R6C9A.D0       nRowColSel
-CTOF_DEL    ---     0.371       R6C9A.D0 to       R6C9A.F0 SLICE_87
-ROUTE         1     1.660       R6C9A.F0 to 76.PADDO       RDQMH_c
-DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
-                  --------
-                    8.023   (56.9% logic, 43.1% route), 3 logic levels.
-
-Report:   10.511ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.888ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQMH
-
-   Data Path Delay:     7.289ns  (61.1% logic, 38.9% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      7.289ns delay SLICE_64 to RDQMH (totaling 8.888ns) meets
-      0.000ns hold offset RCLK to RDQMH by 8.888ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQMH:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.549       R2C6A.Q0 to R6C9A.D0       nRowColSel
-CTOF_DEL    ---     0.301       R6C9A.D0 to       R6C9A.F0 SLICE_87
-ROUTE         1     1.288       R6C9A.F0 to 76.PADDO       RDQMH_c
-DOPAD_DEL   ---     3.636       76.PADDO to         76.PAD RDQMH
-                  --------
-                    7.289   (61.1% logic, 38.9% route), 3 logic levels.
-
-Report:    8.888ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 2.892ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     7.120ns  (64.1% logic, 35.9% route), 3 logic levels.
-
-   Clock Path Delay:    2.488ns  (42.7% logic, 57.3% route), 1 logic levels.
-
- Constraint Details:
-      2.488ns delay RCLK to SLICE_64 and
-      7.120ns delay SLICE_64 to RDQML (totaling 9.608ns) meets
-     12.500ns offset RCLK to RDQML by 2.892ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     1.063         86.PAD to       86.PADDI RCLK
-ROUTE        39     1.425       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    2.488   (42.7% logic, 57.3% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.560      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.736       R2C6A.Q0 to R8C9C.D0       nRowColSel
-CTOF_DEL    ---     0.371       R8C9C.D0 to       R8C9C.F0 SLICE_95
-ROUTE         1     0.817       R8C9C.F0 to 61.PADDO       RDQML_c
-DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
-                  --------
-                    7.120   (64.1% logic, 35.9% route), 3 logic levels.
-
-Report:    9.608ns is the minimum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            1 item scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 8.163ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              nRowColSel_370  (from RCLK_c +)
-   Destination:    Port       Pad            RDQML
-
-   Data Path Delay:     6.564ns  (67.8% logic, 32.2% route), 3 logic levels.
-
-   Clock Path Delay:    1.599ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-      1.599ns delay RCLK to SLICE_64 and
-      6.564ns delay SLICE_64 to RDQML (totaling 8.163ns) meets
-      0.000ns hold offset RCLK to RDQML by 8.163ns
-
- Physical Path Details:
-
-      Clock path RCLK to SLICE_64:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.867         86.PAD to       86.PADDI RCLK
-ROUTE        39     0.732       86.PADDI to R2C6A.CLK      RCLK_c
-                  --------
-                    1.599   (54.2% logic, 45.8% route), 1 logic levels.
-
-      Data path SLICE_64 to RDQML:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.515      R2C6A.CLK to       R2C6A.Q0 SLICE_64 (from RCLK_c)
-ROUTE        13     1.466       R2C6A.Q0 to R8C9C.D0       nRowColSel
-CTOF_DEL    ---     0.301       R8C9C.D0 to       R8C9C.F0 SLICE_95
-ROUTE         1     0.646       R8C9C.F0 to 61.PADDO       RDQML_c
-DOPAD_DEL   ---     3.636       61.PADDO to         61.PAD RDQML
-                  --------
-                    6.564   (67.8% logic, 32.2% route), 3 logic levels.
-
-Report:    8.163ns is the maximum offset for this preference.
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-PERIOD NET "PHI2_c" 350.000000 ns  ;    |   350.000 ns|    22.150 ns|   7  
-                                        |             |             |
-PERIOD NET "nCCAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "nCRAS_c" 350.000000 ns  ;   |   350.000 ns|     2.000 ns|   0  
-                                        |             |             |
-PERIOD NET "RCLK_c" 16.000000 ns  ;     |    16.000 ns|     8.659 ns|   6  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[0]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[7]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[6]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[5]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[4]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[3]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[2]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Setup Analysis.     |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "Dout[1]" 12.500000   |             |             |
-ns CLKPORT "RCLK" ; Hold Analysis.      |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    11.023 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.323 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.040 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.446 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.394 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.766 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.498 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.813 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    11.359 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     9.559 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.042 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.445 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.284 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.599 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.501 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.849 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.284 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.599 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.046 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.442 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCS" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RCKE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.667 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRWE" 12.500000 ns   |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.321 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     8.687 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     7.334 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     7.501 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     6.396 ns|   2  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|    10.511 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.888 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |    12.500 ns|     9.608 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RDQML" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |     0.000 ns|     8.163 ns|   3  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Setup Analysis.        |            -|            -|   0  
-                                        |             |             |
-CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns  |             |             |
-CLKPORT "RCLK" ; Hold Analysis.         |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 4 clocks:
-
-Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
-   No transfer within this clock domain is found
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
-   No transfer within this clock domain is found
-
-Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 39
-   Covered under: PERIOD NET "RCLK_c" 16.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: nCRAS_c   Source: nCRAS.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-   Clock Domain: PHI2_c   Source: PHI2.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
-   Covered under: PERIOD NET "PHI2_c" 350.000000 ns  ;
-
-   Data transfers from:
-   Clock Domain: RCLK_c   Source: RCLK.PAD
-      Not reported because source and destination domains are unrelated.
-      To report these transfers please refer to preference CLKSKEWDIFF to define
-      external clock skew between clock ports.
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 538 paths, 6 nets, and 440 connections (71.54% coverage)
-
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/automake.log b/CPLD-old/LCMXO/LCMXO640C/impl1/automake.log
deleted file mode 100644
index 1165506..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/automake.log
+++ /dev/null
@@ -1,528 +0,0 @@
-
-ibisgen "RAM2GS_LCMXO640C_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo.ibs"   
-IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
-
-Mon Aug 16 21:36:33 2021
-
-Comp: CROW[0]
- Site: 32
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: CROW[1]
- Site: 34
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[0]
- Site: 21
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[1]
- Site: 15
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[2]
- Site: 14
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[3]
- Site: 16
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[4]
- Site: 18
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[5]
- Site: 17
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[6]
- Site: 20
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Din[7]
- Site: 19
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: Dout[0]
- Site: 1
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[1]
- Site: 7
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[2]
- Site: 8
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[3]
- Site: 6
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[4]
- Site: 4
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[5]
- Site: 5
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[6]
- Site: 2
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: Dout[7]
- Site: 3
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: LED
- Site: 57
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=16mA 
- SLEW=SLOW 
------------------------
-Comp: MAin[0]
- Site: 23
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[1]
- Site: 38
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[2]
- Site: 37
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[3]
- Site: 47
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[4]
- Site: 46
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[5]
- Site: 45
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[6]
- Site: 49
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[7]
- Site: 44
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[8]
- Site: 50
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: MAin[9]
- Site: 51
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: PHI2
- Site: 39
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: RA[0]
- Site: 98
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[10]
- Site: 87
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[11]
- Site: 79
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[1]
- Site: 89
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[2]
- Site: 94
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[3]
- Site: 97
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[4]
- Site: 99
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[5]
- Site: 95
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[6]
- Site: 91
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[7]
- Site: 100
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[8]
- Site: 96
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RA[9]
- Site: 85
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RBA[0]
- Site: 63
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RBA[1]
- Site: 83
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RCKE
- Site: 82
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RCLK
- Site: 86
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: RDQMH
- Site: 76
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RDQML
- Site: 61
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: RD[0]
- Site: 64
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[1]
- Site: 65
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[2]
- Site: 66
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[3]
- Site: 67
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[4]
- Site: 68
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[5]
- Site: 69
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[6]
- Site: 70
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: RD[7]
- Site: 71
- Type: BIDI
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
- PULL=KEEPER 
------------------------
-Comp: UFMCLK
- Site: 58
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: UFMSDI
- Site: 56
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: UFMSDO
- Site: 55
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
- PULL=KEEPER 
------------------------
-Comp: nCCAS
- Site: 27
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: nCRAS
- Site: 43
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: nFWE
- Site: 22
- Type: IN
- IO_TYPE=LVTTL33 
- SLEW=FAST 
------------------------
-Comp: nRCAS
- Site: 78
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRCS
- Site: 77
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRRAS
- Site: 73
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nRWE
- Site: 72
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Comp: nUFMCS
- Site: 53
- Type: OUT
- IO_TYPE=LVTTL33 
- DRIVE=4mA 
- SLEW=SLOW 
------------------------
-Created design models.
-
-
-Generating: C:\Users\Dog\Documents\GitHub\RAM2GS\CPLD\LCMXO\LCMXO640C\impl1\IBIS\RAM2GS_LCMXO640C_im~.ibs
-
-
-    
-
-tmcheck -par "RAM2GS_LCMXO640C_impl1.par" 
-
-bitgen -w "RAM2GS_LCMXO640C_impl1.ncd" -f "RAM2GS_LCMXO640C_impl1.t2b" "RAM2GS_LCMXO640C_impl1.prf"
-
-
-BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-
-Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
-
-Preference Summary:
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                             ES  |                           No**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
-Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 46 MB
-
-ddtcmd -dev LCMXO640C-XXT100 -if "RAM2GS_LCMXO640C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO640C_impl1.jed"  -comment "RAM2GS_LCMXO640C_impl1.alt" 
-Lattice Diamond Deployment Tool 3.12 Command Line
-
-Loading Programmer Device Database...
-
-Generating JED.....
-Device Name: LCMXO640C-XXT100
-Reading Input File: RAM2GS_LCMXO640C_impl1.bit
-Output File: RAM2GS_LCMXO640C_impl1.jed
-Comment file RAM2GS_LCMXO640C_impl1.alt.
-Generating JEDEC.....
-File RAM2GS_LCMXO640C_impl1.jed generated successfully.
-Lattice Diamond Deployment Tool has exited successfully.
-
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html b/CPLD-old/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html
deleted file mode 100644
index ef94b54..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html
+++ /dev/null
@@ -1,9 +0,0 @@
-         	                                   	                                                	                                                 	                                                  	
    Setting log file to 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1/hdla_gen_hierarchy.html'.
-Starting: parse design source files
-(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
-(VERI-1482) Analyzing Verilog file 'C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v'
-INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
-INFO - C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v(1,1-397,10) (VERI-9000) elaborating module 'RAM2GS'
-Done: design load finished with (0) errors, and (0) warnings
-
-
    
\ No newline at end of file
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior b/CPLD-old/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
deleted file mode 100644
index 4473ca1..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
+++ /dev/null
@@ -1,137 +0,0 @@
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 4
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-// Design: RAM2GS
-// Package: TQFP100
-// ncd File: ram2gs_lcmxo640c_impl1.ncd
-// Version: Diamond (64-bit) 3.12.0.240.2
-// Written on Mon Aug 16 21:33:38 2021
-// M: Minimum Performance Grade
-// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 5, 4, 3):
-
-// Input Setup and Hold Times
-
-Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-CROW[0] nCRAS F     0.474      3       1.625     3
-CROW[1] nCRAS F     0.104      3       1.925     3
-Din[0]  PHI2  F     6.682      3       1.613     3
-Din[0]  nCCAS F    -0.028      M       2.082     3
-Din[1]  PHI2  F     6.886      3       2.631     3
-Din[1]  nCCAS F    -0.025      M       2.074     3
-Din[2]  PHI2  F     5.426      3       1.921     3
-Din[2]  nCCAS F     1.175      3       1.003     3
-Din[3]  PHI2  F     5.699      3       1.852     3
-Din[3]  nCCAS F     0.331      3       1.707     3
-Din[4]  PHI2  F     6.556      3       1.438     3
-Din[4]  nCCAS F     0.706      3       1.406     3
-Din[5]  PHI2  F     6.281      3       1.959     3
-Din[5]  nCCAS F     0.246      3       1.807     3
-Din[6]  PHI2  F     5.585      3       1.441     3
-Din[6]  nCCAS F     0.799      3       1.341     3
-Din[7]  PHI2  F     7.980      3       1.725     3
-Din[7]  nCCAS F     0.333      3       1.707     3
-MAin[0] PHI2  F     4.994      3       1.265     3
-MAin[0] nCRAS F     0.662      3       1.471     3
-MAin[1] PHI2  F     6.056      3       1.867     3
-MAin[1] nCRAS F     1.180      3       0.990     3
-MAin[2] PHI2  F    10.634      3      -1.183     M
-MAin[2] nCRAS F    -0.218      M       2.631     3
-MAin[3] PHI2  F    10.902      3      -1.260     M
-MAin[3] nCRAS F     0.208      3       1.826     3
-MAin[4] PHI2  F    10.204      3      -1.072     M
-MAin[4] nCRAS F    -0.218      M       2.628     3
-MAin[5] PHI2  F     7.043      3      -0.270     M
-MAin[5] nCRAS F     0.123      3       1.925     3
-MAin[6] PHI2  F     9.465      3      -0.885     M
-MAin[6] nCRAS F     0.584      3       1.522     3
-MAin[7] PHI2  F     9.683      3      -0.938     M
-MAin[7] nCRAS F    -0.218      M       2.628     3
-MAin[8] nCRAS F     0.316      3       1.758     3
-MAin[9] nCRAS F    -0.058      M       2.185     3
-PHI2    RCLK  R     1.456      3       0.038     3
-UFMSDO  RCLK  R     2.953      3      -0.147     M
-nCCAS   RCLK  R     2.435      3      -0.244     M
-nCCAS   nCRAS F     0.156      3       1.902     3
-nCRAS   RCLK  R     5.307      3      -0.787     M
-nFWE    PHI2  F     5.614      3       1.072     3
-nFWE    nCRAS F    -0.101      M       2.317     3
-
-
-// Clock to Output Delay
-
-Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-LED    RCLK  R    11.635         3        3.019          M
-RA[0]  RCLK  R    11.287         3        2.893          M
-RA[0]  nCRAS F    15.323         3        3.902          M
-RA[10] RCLK  R     7.501         3        1.949          M
-RA[11] PHI2  R     9.747         3        2.487          M
-RA[1]  RCLK  R    11.083         3        2.855          M
-RA[1]  nCRAS F    12.034         3        3.047          M
-RA[2]  RCLK  R    10.857         3        2.787          M
-RA[2]  nCRAS F    13.411         3        3.403          M
-RA[3]  RCLK  R    10.775         3        2.772          M
-RA[3]  nCRAS F    12.977         3        3.296          M
-RA[4]  RCLK  R    10.758         3        2.776          M
-RA[4]  nCRAS F    14.192         3        3.619          M
-RA[5]  RCLK  R    10.334         3        2.652          M
-RA[5]  nCRAS F    13.484         3        3.424          M
-RA[6]  RCLK  R    10.334         3        2.652          M
-RA[6]  nCRAS F    12.972         3        3.291          M
-RA[7]  RCLK  R     9.917         3        2.572          M
-RA[7]  nCRAS F    12.327         3        3.147          M
-RA[8]  RCLK  R    10.465         3        2.689          M
-RA[8]  nCRAS F    12.559         3        3.170          M
-RA[9]  RCLK  R    10.412         3        2.668          M
-RA[9]  nCRAS F    14.019         3        3.564          M
-RBA[0] nCRAS F    11.063         3        2.809          M
-RBA[1] nCRAS F    11.902         3        3.028          M
-RCKE   RCLK  R     7.501         3        1.949          M
-RDQMH  RCLK  R     9.831         3        2.523          M
-RDQML  RCLK  R     9.117         3        2.351          M
-RD[0]  nCCAS F    12.575         3        3.249          M
-RD[1]  nCCAS F    13.016         3        3.365          M
-RD[2]  nCCAS F    11.602         3        2.993          M
-RD[3]  nCCAS F    10.893         3        2.834          M
-RD[4]  nCCAS F    12.063         3        3.116          M
-RD[5]  nCCAS F    12.555         3        3.242          M
-RD[6]  nCCAS F    12.537         3        3.240          M
-RD[7]  nCCAS F    12.524         3        3.239          M
-UFMCLK RCLK  R     8.079         3        2.126          M
-UFMSDI RCLK  R     8.079         3        2.126          M
-nRCAS  RCLK  R     7.501         3        1.949          M
-nRCS   RCLK  R     7.501         3        1.949          M
-nRRAS  RCLK  R     9.175         3        2.363          M
-nRWE   RCLK  R     9.141         3        2.356          M
-nUFMCS RCLK  R     8.804         3        2.290          M
-WARNING: you must also run trce with hold speed: 3
-WARNING: you must also run trce with setup speed: M
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd b/CPLD-old/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd
deleted file mode 100644
index 735293f..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd
+++ /dev/null
@@ -1,91 +0,0 @@
-[ActiveSupport TRCE]
-; Setup Analysis
-Period_0 = 27.276 ns (350.000 ns);
-Period_1 = 2.000 ns (350.000 ns);
-Period_2 = 2.000 ns (350.000 ns);
-Period_3 = 9.443 ns (16.000 ns);
-Tco_4 = - (-);
-Tco_5 = - (-);
-Tco_6 = - (-);
-Tco_7 = - (-);
-Tco_8 = - (-);
-Tco_9 = - (-);
-Tco_10 = - (-);
-Tco_11 = - (-);
-Tco_12 = - (-);
-Tco_13 = - (-);
-Tco_14 = - (-);
-Tco_15 = - (-);
-Tco_16 = 7.501 ns (12.500 ns);
-Tco_17 = 10.412 ns (12.500 ns);
-Tco_18 = 10.465 ns (12.500 ns);
-Tco_19 = 9.917 ns (12.500 ns);
-Tco_20 = 10.334 ns (12.500 ns);
-Tco_21 = 10.334 ns (12.500 ns);
-Tco_22 = 10.758 ns (12.500 ns);
-Tco_23 = 10.775 ns (12.500 ns);
-Tco_24 = 10.857 ns (12.500 ns);
-Tco_25 = 11.083 ns (12.500 ns);
-Tco_26 = 11.287 ns (12.500 ns);
-Tco_27 = 7.501 ns (12.500 ns);
-Tco_28 = 7.501 ns (12.500 ns);
-Tco_29 = 9.141 ns (12.500 ns);
-Tco_30 = 9.175 ns (12.500 ns);
-Tco_31 = 7.501 ns (12.500 ns);
-Tco_32 = 9.831 ns (12.500 ns);
-Tco_33 = 9.117 ns (12.500 ns);
-Tco_34 = - (-);
-Tco_35 = - (-);
-Tco_36 = - (-);
-Tco_37 = - (-);
-Tco_38 = - (-);
-Tco_39 = - (-);
-Tco_40 = - (-);
-Failed = 0 (Total 41);
-Clock_ports = 4;
-Clock_nets = 4;
-; Hold Analysis
-Period_0 = - (-);
-Period_1 = - (-);
-Period_2 = - (-);
-Period_3 = - (-);
-Tco_4 = - (-);
-Tco_5 = - (-);
-Tco_6 = - (-);
-Tco_7 = - (-);
-Tco_8 = - (-);
-Tco_9 = - (-);
-Tco_10 = - (-);
-Tco_11 = - (-);
-Tco_12 = - (-);
-Tco_13 = - (-);
-Tco_14 = - (-);
-Tco_15 = - (-);
-Tco_16 = 1.949 ns (0.000 ns);
-Tco_17 = 2.668 ns (0.000 ns);
-Tco_18 = 2.689 ns (0.000 ns);
-Tco_19 = 2.572 ns (0.000 ns);
-Tco_20 = 2.652 ns (0.000 ns);
-Tco_21 = 2.652 ns (0.000 ns);
-Tco_22 = 2.776 ns (0.000 ns);
-Tco_23 = 2.772 ns (0.000 ns);
-Tco_24 = 2.787 ns (0.000 ns);
-Tco_25 = 2.855 ns (0.000 ns);
-Tco_26 = 2.893 ns (0.000 ns);
-Tco_27 = 1.949 ns (0.000 ns);
-Tco_28 = 1.949 ns (0.000 ns);
-Tco_29 = 2.356 ns (0.000 ns);
-Tco_30 = 2.363 ns (0.000 ns);
-Tco_31 = 1.949 ns (0.000 ns);
-Tco_32 = 2.523 ns (0.000 ns);
-Tco_33 = 2.351 ns (0.000 ns);
-Tco_34 = - (-);
-Tco_35 = - (-);
-Tco_36 = - (-);
-Tco_37 = - (-);
-Tco_38 = - (-);
-Tco_39 = - (-);
-Tco_40 = - (-);
-Failed = 0 (Total 41);
-Clock_ports = 4;
-Clock_nets = 4;
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/synthesis.log b/CPLD-old/LCMXO/LCMXO640C/impl1/synthesis.log
deleted file mode 100644
index f808002..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/synthesis.log
+++ /dev/null
@@ -1,239 +0,0 @@
-synthesis:  version Diamond (64-bit) 3.12.0.240.2
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Mon Aug 16 21:33:29 2021
-
-
-Command Line:  synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
-
-Synthesis options:
-The -a option is MachXO.
-The -s option is 3.
-The -t option is TQFP100.
-The -d option is LCMXO640C.
-Using package TQFP100.
-Using performance grade 3.
-                                                          
-
-##########################################################
-
-### Lattice Family : MachXO
-
-### Device  : LCMXO640C
-
-### Package : TQFP100
-
-### Speed   : 3
-
-##########################################################
-
-                                                          
-
-INFO - synthesis: User-Selected Strategy Settings
-Optimization goal = Balanced
-Top-level module name = RAM2GS.
-Target frequency = 200.000000 MHz.
-Maximum fanout = 1000.
-Timing path count = 3
-BRAM utilization = 100.000000 %
-DSP usage = true
-DSP utilization = 100.000000 %
-fsm_encoding_style = auto
-resolve_mixed_drivers = 0
-fix_gated_clocks = 1
-
-Mux style = Auto
-Use Carry Chain = true
-carry_chain_length = 0
-Loop Limit = 1950.
-Use IO Insertion = TRUE
-Use IO Reg = AUTO
-
-Resource Sharing = TRUE
-Propagate Constants = TRUE
-Remove Duplicate Registers = TRUE
-force_gsr = auto
-ROM style = auto
-RAM style = auto
-The -comp option is FALSE.
-The -syn option is FALSE.
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
--p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1 (searchpath added)
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
-Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
-NGD file = RAM2GS_LCMXO640C_impl1.ngd
--sdc option: SDC file input not used.
--lpf option: Output file option is ON.
-Hardtimer checking is enabled (default). The -dt option is not used.
-The -r option is OFF. [ Remove LOC Properties is OFF. ]
-Technology check ok...
-
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
-Compile design.
-Compile Design Begin
-Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
-Top module name (Verilog): RAM2GS
-INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Top-level module name = RAM2GS.
-INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 0000 -> 0000000000000001
-
- 0001 -> 0000000000000010
-
- 0010 -> 0000000000000100
-
- 0011 -> 0000000000001000
-
- 0100 -> 0000000000010000
-
- 0101 -> 0000000000100000
-
- 0110 -> 0000000001000000
-
- 0111 -> 0000000010000000
-
- 1000 -> 0000000100000000
-
- 1001 -> 0000001000000000
-
- 1010 -> 0000010000000000
-
- 1011 -> 0000100000000000
-
- 1100 -> 0001000000000000
-
- 1101 -> 0010000000000000
-
- 1110 -> 0100000000000000
-
- 1111 -> 1000000000000000
-
-INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 00 -> 0001
-
- 01 -> 0010
-
- 10 -> 0100
-
- 11 -> 1000
-
-
-
-
-GSR will not be inferred because no asynchronous signal was found in the netlist.
-WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
-Applying 200.000000 MHz constraint to all clocks
-
-WARNING - synthesis: No user .sdc file.
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO640C_impl1.ngd.
-
-################### Begin Area Report (RAM2GS)######################
-Number of register bits => 102 of 862 (11 % )
-BB => 8
-CCU2 => 9
-FD1P3AX => 28
-FD1P3AY => 3
-FD1P3IX => 2
-FD1P3JX => 1
-FD1S3AX => 47
-FD1S3AY => 1
-FD1S3IX => 16
-FD1S3JX => 4
-GSR => 1
-IB => 26
-INV => 3
-OB => 33
-ORCALUT4 => 116
-PFUMX => 3
-################### End Area Report ##################
-
-################### Begin BlackBox Report ######################
-TSALL => 1
-################### End BlackBox Report ##################
-
-################### Begin Clock Report ######################
-Clock Nets
-Number of Clocks: 4
-  Net : RCLK_c, loads : 62
-  Net : PHI2_c, loads : 11
-  Net : nCCAS_c, loads : 2
-  Net : nCRAS_c, loads : 2
-Clock Enable Nets
-Number of Clock Enables: 13
-Top 10 highest fanout Clock Enables:
-  Net : RCLK_c_enable_23, loads : 16
-  Net : RCLK_c_enable_4, loads : 3
-  Net : PHI2_N_114_enable_7, loads : 3
-  Net : RCLK_c_enable_24, loads : 2
-  Net : PHI2_N_114_enable_6, loads : 2
-  Net : RCLK_c_enable_7, loads : 1
-  Net : RCLK_c_enable_6, loads : 1
-  Net : RCLK_c_enable_3, loads : 1
-  Net : PHI2_N_114_enable_2, loads : 1
-  Net : PHI2_N_114_enable_1, loads : 1
-Highest fanout non-clock nets
-Top 10 highest fanout non-clock nets:
-  Net : InitReady, loads : 17
-  Net : RCLK_c_enable_23, loads : 16
-  Net : RASr2, loads : 15
-  Net : nCRAS_N_9, loads : 15
-  Net : nRowColSel_N_35, loads : 14
-  Net : nRowColSel, loads : 13
-  Net : Ready, loads : 13
-  Net : n2307, loads : 13
-  Net : nCCAS_N_3, loads : 10
-  Net : Din_c_6, loads : 9
-################### End Clock Report ##################
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |  200.000 MHz|   38.826 MHz|     7 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
-
-Peak Memory Usage: 50.699  MB
-
---------------------------------------------------------------
-Elapsed CPU time for LSE flow : 0.515  secs
---------------------------------------------------------------
diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/synthesis_lse.html b/CPLD-old/LCMXO/LCMXO640C/impl1/synthesis_lse.html
deleted file mode 100644
index 23a4fc7..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/synthesis_lse.html
+++ /dev/null
@@ -1,304 +0,0 @@
-
-Synthesis and Ngdbuild Report
-
-
-
    Synthesis and Ngdbuild  Report
-synthesis:  version Diamond (64-bit) 3.12.0.240.2
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Mon Aug 16 21:33:29 2021
-
-
-Command Line:  synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml 
-
-Synthesis options:
-The -a option is MachXO.
-The -s option is 3.
-The -t option is TQFP100.
-The -d option is LCMXO640C.
-Using package TQFP100.
-Using performance grade 3.
-                                                          
-
-##########################################################
-
-### Lattice Family : MachXO
-
-### Device  : LCMXO640C
-
-### Package : TQFP100
-
-### Speed   : 3
-
-##########################################################
-
-                                                          
-
-INFO - synthesis: User-Selected Strategy Settings
-Optimization goal = Balanced
-Top-level module name = RAM2GS.
-Target frequency = 200.000000 MHz.
-Maximum fanout = 1000.
-Timing path count = 3
-BRAM utilization = 100.000000 %
-DSP usage = true
-DSP utilization = 100.000000 %
-fsm_encoding_style = auto
-resolve_mixed_drivers = 0
-fix_gated_clocks = 1
-
-Mux style = Auto
-Use Carry Chain = true
-carry_chain_length = 0
-Loop Limit = 1950.
-Use IO Insertion = TRUE
-Use IO Reg = AUTO
-
-Resource Sharing = TRUE
-Propagate Constants = TRUE
-Remove Duplicate Registers = TRUE
-force_gsr = auto
-ROM style = auto
-RAM style = auto
-The -comp option is FALSE.
-The -syn option is FALSE.
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
--p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/impl1 (searchpath added)
--p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C (searchpath added)
-Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
-NGD file = RAM2GS_LCMXO640C_impl1.ngd
--sdc option: SDC file input not used.
--lpf option: Output file option is ON.
-Hardtimer checking is enabled (default). The -dt option is not used.
-The -r option is OFF. [ Remove LOC Properties is OFF. ]
-Technology check ok...
-
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
-Compile design.
-Compile Design Begin
-Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
-Top module name (Verilog): RAM2GS
-INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
-WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Top-level module name = RAM2GS.
-INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 0000 -> 0000000000000001
-
- 0001 -> 0000000000000010
-
- 0010 -> 0000000000000100
-
- 0011 -> 0000000000001000
-
- 0100 -> 0000000000010000
-
- 0101 -> 0000000000100000
-
- 0110 -> 0000000001000000
-
- 0111 -> 0000000010000000
-
- 1000 -> 0000000100000000
-
- 1001 -> 0000001000000000
-
- 1010 -> 0000010000000000
-
- 1011 -> 0000100000000000
-
- 1100 -> 0001000000000000
-
- 1101 -> 0010000000000000
-
- 1110 -> 0100000000000000
-
- 1111 -> 1000000000000000
-
-INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
-original encoding -> new encoding (one-hot encoding)
-
- 00 -> 0001
-
- 01 -> 0010
-
- 10 -> 0100
-
- 11 -> 1000
-
-
-
-
-GSR will not be inferred because no asynchronous signal was found in the netlist.
-WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
-Applying 200.000000 MHz constraint to all clocks
-
-WARNING - synthesis: No user .sdc file.
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO640C_impl1.ngd.
-
-################### Begin Area Report (RAM2GS)######################
-Number of register bits => 102 of 862 (11 % )
-BB => 8
-CCU2 => 9
-FD1P3AX => 28
-FD1P3AY => 3
-FD1P3IX => 2
-FD1P3JX => 1
-FD1S3AX => 47
-FD1S3AY => 1
-FD1S3IX => 16
-FD1S3JX => 4
-GSR => 1
-IB => 26
-INV => 3
-OB => 33
-ORCALUT4 => 116
-PFUMX => 3
-################### End Area Report ##################
-
-################### Begin BlackBox Report ######################
-TSALL => 1
-################### End BlackBox Report ##################
-
-################### Begin Clock Report ######################
-Clock Nets
-Number of Clocks: 4
-  Net : RCLK_c, loads : 62
-  Net : PHI2_c, loads : 11
-  Net : nCCAS_c, loads : 2
-  Net : nCRAS_c, loads : 2
-Clock Enable Nets
-Number of Clock Enables: 13
-Top 10 highest fanout Clock Enables:
-  Net : RCLK_c_enable_23, loads : 16
-  Net : RCLK_c_enable_4, loads : 3
-  Net : PHI2_N_114_enable_7, loads : 3
-  Net : RCLK_c_enable_24, loads : 2
-  Net : PHI2_N_114_enable_6, loads : 2
-  Net : RCLK_c_enable_7, loads : 1
-  Net : RCLK_c_enable_6, loads : 1
-  Net : RCLK_c_enable_3, loads : 1
-  Net : PHI2_N_114_enable_2, loads : 1
-  Net : PHI2_N_114_enable_1, loads : 1
-Highest fanout non-clock nets
-Top 10 highest fanout non-clock nets:
-  Net : InitReady, loads : 17
-  Net : RCLK_c_enable_23, loads : 16
-  Net : RASr2, loads : 15
-  Net : nCRAS_N_9, loads : 15
-  Net : nRowColSel_N_35, loads : 14
-  Net : nRowColSel, loads : 13
-  Net : Ready, loads : 13
-  Net : n2307, loads : 13
-  Net : nCCAS_N_3, loads : 10
-  Net : Din_c_6, loads : 9
-################### End Clock Report ##################
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |  200.000 MHz|   38.826 MHz|     7 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |  200.000 MHz|   88.566 MHz|     6 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
-
-Peak Memory Usage: 50.699  MB
-
---------------------------------------------------------------
-Elapsed CPU time for LSE flow : 0.515  secs
---------------------------------------------------------------
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diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/xxx_lse_cp_file_list b/CPLD-old/LCMXO/LCMXO640C/impl1/xxx_lse_cp_file_list
deleted file mode 100644
index 29f9161..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/xxx_lse_cp_file_list
+++ /dev/null
@@ -1,252 +0,0 @@
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diff --git a/CPLD-old/LCMXO/LCMXO640C/impl1/xxx_lse_sign_file b/CPLD-old/LCMXO/LCMXO640C/impl1/xxx_lse_sign_file
deleted file mode 100644
index 47217b1..0000000
--- a/CPLD-old/LCMXO/LCMXO640C/impl1/xxx_lse_sign_file
+++ /dev/null
@@ -1,252 +0,0 @@
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diff --git a/CPLD-old/LCMXO/RAM2GS-LCMXO.v b/CPLD-old/LCMXO/RAM2GS-LCMXO.v
deleted file mode 100644
index fce50cf..0000000
--- a/CPLD-old/LCMXO/RAM2GS-LCMXO.v
+++ /dev/null
@@ -1,403 +0,0 @@
-module RAM2GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE, LED,
-			  RBA, RA, RD, nRCS, RCLK, RCKE,
-			  nRWE, nRRAS, nRCAS, RDQMH, RDQML,
-			  nUFMCS, UFMCLK, UFMSDI, UFMSDO);
-
-	/* 65816 Phase 2 Clock */
-	input PHI2;
-
-	/* Activity LED */
-	reg LEDEN = 0;
-	output LED;
-	assign LED = ~(~nCRAS &&  LEDEN);
-
-	/* Async. DRAM Control Inputs */
-	input nCCAS, nCRAS;
-
-	/* Synchronized PHI2 and DRAM signals */
-	reg PHI2r, PHI2r2, PHI2r3;
-	reg RASr, RASr2, RASr3;
-	reg CASr, CASr2, CASr3;
-	reg FWEr;
-	reg CBR;
-
-	/* 65816 Data */
-	input [7:0] Din;
-	output [7:0] Dout;
-	assign Dout[7:0] = RD[7:0];
-
-	/* Latched 65816 Bank Address */
-	reg [7:0] Bank;
-
-	/* Async. DRAM Address Bus */
-	input [1:0] CROW;
-	input [9:0] MAin;
-	input nFWE;
-	reg n8MEGEN = 0;
-	reg XOR8MEG = 0;
-	
-	/* SDRAM Clock */
-	input RCLK;
-	
-	/* SDRAM */
-	reg RCKEEN;
-	output reg RCKE = 0;
-	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
-	output reg [1:0] RBA;
-	reg nRowColSel;
-	reg RA11;
-	reg RA10;
-	reg [9:0] RowA;
-	output [11:0] RA;
-	assign RA[11] = RA11;
-	assign RA[10] = RA10;
-	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML, RDQMH;
-	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
-	reg [7:0] WRD;
-	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
-
-	/* UFM Interface */
-	output reg nUFMCS = 1;
-	output reg UFMCLK = 0;
-	output reg UFMSDI = 0;
-	input UFMSDO;
-
-	/* UFM Command Interface */
-	reg C1Submitted = 0;
-	reg ADSubmitted = 0;
-	reg CmdEnable = 0;
-	reg CmdSubmitted = 0;
-	reg CmdLEDEN = 0;
-	reg Cmdn8MEGEN = 0;
-	reg CmdUFMCLK = 0;
-	reg CmdUFMSDI = 0;
-	reg CmdUFMCS = 0;
-	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
-	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
-	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
-	
-	/* State Counters */
-	reg InitReady = 0; // 1 if ready for init sequence
-	reg Ready = 0; // 1 if done with init sequence
-	reg [1:0] S = 0; // post-RAS State counter
-	reg [17:0] FS = 0; // Fast init state counter
-	reg [3:0] IS = 0; // Init state counter
-	reg WriteDone;
-	
-	/* Synchronize PHI2, RAS, CAS */
-	always @(posedge RCLK) begin
-		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
-		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
-		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
-	end
-	
-	/* Latch 65816 bank when PHI2 rises */
-	always @(posedge PHI2) begin
-		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
-		else RA11 <= 1'b0; // Reserved in mode register
-		Bank[7:0] <= Din[7:0]; // Latch bank
-	end
-	
-	/* Latch bank address, row address, WE, and CAS when RAS falls */
-	always @(negedge nCRAS) begin
-		if (Ready) begin
-			RBA[1:0] <= CROW[1:0];
-			RowA[9:0] <= MAin[9:0];
-		end else begin
-			RBA[1:0] <= 2'b00;		// Reserved in mode register
-			RowA[9] <= 1'b1;		// "1" for single write mode
-			RowA[8] <= 1'b0;		// Reserved
-			RowA[7] <= 1'b0;		// "0" for not test mode
-			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
-			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
-			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
-		end
-		FWEr <= ~nFWE;
-		CBR <= ~nCCAS;
-	end
-
-	/* Latch write data when CAS falls */
-	always @(negedge nCCAS) begin
-		WRD[7:0] <= Din[7:0];
-	end
-
-	/* State counter from RAS */
-	always @(posedge RCLK) begin
-		if (~RASr2) S <= 0;
-		else if (S==2'h3) S <= 2'h3;
-		else S <= S+1;
-	end
-	/* Init state counter */
-	always @(posedge RCLK) begin
-		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
-		FS <= FS+1;
-		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
-	end
-
-	/* SDRAM CKE */
-	always @(posedge RCLK) begin
-		// Only 1 LUT4 allowed for this function!
-		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
-	end
-
-	/* SDRAM command */
-	always @(posedge RCLK) begin
-		if (Ready) begin
-			if (S==0) begin
-				if (RASr2) begin
-					if (CBR) begin
-						// AREF
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b0;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // RA10 is don't care
-					end else begin
-						// ACT
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b1;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // Bank RA10 consistently "1"
-					end
-					// Enable clock only for reads
-					RCKEEN <= ~CBR & ~FWEr;
-				end else if (RCKE) begin
-					// PCall
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-					RCKEEN <= 1'b1;
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-					RCKEEN <= 1'b1;
-				end
-				nRowColSel <= 1'b0; // Select registered row addres
-			end else if (S==1) begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR; // Disable clock if refresh cycle
-			end else if (S==2) begin
-				if (~FWEr & ~CBR) begin
-					// RD
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
-			end else if (S==3) begin
-				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
-					// WR
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= ~(~FWEr | CASr3 | CBR);
-				RCKEEN <= ~(~FWEr | CASr2 | CBR);
-			end
-		end else if (InitReady) begin
-			if (S==0 & RASr2) begin
-				if (IS==0) begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end else if (IS==1) begin
-					// PC all
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-				end else if (IS==9) begin
-					// Load mode register
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b0; // Reserved in mode register
-				end else begin
-					// AREF
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				IS <= IS+1;
-			end else begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-			end
-			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b1;
-		end else begin
-			// NOP
-			nRCS <= 1'b1;
-			nRRAS <= 1'b1;
-			nRCAS <= 1'b1;
-			nRWE <= 1'b1;
-			RA10 <= 1'b1; // RA10 is don't care
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b0;
-		end
-	end
-	
-	/* Submit command when PHI2 falls */
-	always @(negedge PHI2) begin
-		// Magic number check
-		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
-			if (ADSubmitted) begin
-				CmdEnable <= 1'b1;
-			end
-			C1Submitted <= 1'b1;
-			ADSubmitted <= 1'b0;
-		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
-			if (C1Submitted) begin
-				CmdEnable <= 1'b1;
-			end
-			ADSubmitted <= 1'b1;
-			C1Submitted <= 1'b0;
-		end else if (C1WR | ADWR) begin // wrong magic number submitted
-			CmdEnable <= 1'b0;
-			C1Submitted <= 1'b0;
-			ADSubmitted <= 1'b0;
-		end else if (CMDWR) CmdEnable <= 1'b0;
-
-		// Submit command
-		if (CMDWR & CmdEnable) begin
-			if (Din[7:4]==4'h0) begin
-				XOR8MEG <= Din[0];
-			end else if (Din[7:4]==4'h1) begin
-				CmdLEDEN <= ~Din[1];
-				Cmdn8MEGEN <= ~Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h3 && ~Din[3]) begin
-				CmdLEDEN <= LEDEN;
-				Cmdn8MEGEN <= n8MEGEN;
-				CmdUFMCS <= Din[2];
-				CmdUFMCLK <= Din[1];
-				CmdUFMSDI <= Din[0];
-				CmdSubmitted <= 1'b1;
-			end
-		end
-	end
-
-	/* UFM Control */
-	always @(posedge RCLK) begin
-		if (~InitReady && FS[17:10]==8'h00) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h01) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h02) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			case (FS[9:5]) // Shift out read data command (0x03)
-				5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
-				5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
-				5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
-				5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
-				5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
-				5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
-				5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
-				5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
-				5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
-				5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
-				5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
-				5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
-				5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
-				5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
-				5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
-				5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
-				5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
-				5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
-				5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
-				5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
-				5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
-				5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
-				5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
-				5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
-				5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
-				5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
-				5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
-				5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
-				5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
-				5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
-				5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
-				5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h03) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			UFMSDI <= 1'b0;
-			// Latch n8MEGEN and LEDEN
-			if (FS[9:5]==5'h00 && FS[4:0]==5'h1F) n8MEGEN <= ~UFMSDO;
-			if (FS[9:5]==5'h01 && FS[4:0]==5'h1F) LEDEN <= ~UFMSDO;
-		end else if (~InitReady && FS[17:10]==8'h04) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h05) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= FS[4];
-			UFMSDI <= 1'b0;
-		end else if (~InitReady) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
-			// Set user command signals after PHI2 falls
-			// CmdnLEDEN, Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
-			LEDEN <= CmdLEDEN;
-			n8MEGEN <= Cmdn8MEGEN;
-			nUFMCS <= ~CmdUFMCS;
-			UFMCLK <= CmdUFMCLK;
-			UFMSDI <= CmdUFMSDI;
-		end
-	end
-endmodule
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/.run_manager.ini b/CPLD-old/LCMXO2/LCMXO2-640HC/.run_manager.ini
deleted file mode 100644
index 8c0aa7b..0000000
--- a/CPLD-old/LCMXO2/LCMXO2-640HC/.run_manager.ini
+++ /dev/null
@@ -1,9 +0,0 @@
-[Runmanager]
-Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
-windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
-headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
-
-[impl1%3CStrategy1%3E]
-isChecked=false
-isHidden=false
-isExpanded=false
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/.vdbs/dbStat.txt b/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/.vdbs/dbStat.txt
deleted file mode 100644
index 0a575a4..0000000
--- a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/.vdbs/dbStat.txt
+++ /dev/null
@@ -1 +0,0 @@
-RAM2GS_rtl.vdb
diff --git a/CPLD-old/MAX/MAXII/RAM2GS-MAXII.qpf b/CPLD-old/MAX/MAXII/RAM2GS-MAXII.qpf
deleted file mode 100644
index 74f038f..0000000
--- a/CPLD-old/MAX/MAXII/RAM2GS-MAXII.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-# Date created = 18:32:31  August 16, 2021
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.0"
-DATE = "18:32:31  August 16, 2021"
-
-# Revisions
-
-PROJECT_REVISION = "RAM2GS"
diff --git a/CPLD-old/MAX/MAXII/RAM2GS.qsf b/CPLD-old/MAX/MAXII/RAM2GS.qsf
deleted file mode 100644
index 5aa99ad..0000000
--- a/CPLD-old/MAX/MAXII/RAM2GS.qsf
+++ /dev/null
@@ -1,212 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
-# Date created = 21:16:34  March 08, 2020
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		RAM4GS_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "MAX II"
-set_global_assignment -name DEVICE EPM240T100C5
-set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34  MARCH 08, 2020"
-set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-set_global_assignment -name SMART_RECOMPILE OFF
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
-set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON
-set_global_assignment -name SAFE_STATE_MACHINE ON
-
-
-
-set_location_assignment PIN_12 -to RCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK
-
-set_location_assignment PIN_52 -to PHI2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI2
-
-set_location_assignment PIN_67 -to nCRAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCRAS
-
-set_location_assignment PIN_53 -to nCCAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCCAS
-
-set_location_assignment PIN_48 -to nFWE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nFWE
-
-set_location_assignment PIN_49 -to MAin[0]
-set_location_assignment PIN_51 -to MAin[1]
-set_location_assignment PIN_50 -to MAin[2]
-set_location_assignment PIN_71 -to MAin[3]
-set_location_assignment PIN_70 -to MAin[4]
-set_location_assignment PIN_69 -to MAin[5]
-set_location_assignment PIN_72 -to MAin[6]
-set_location_assignment PIN_68 -to MAin[7]
-set_location_assignment PIN_73 -to MAin[8]
-set_location_assignment PIN_74 -to MAin[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MAin
-
-set_location_assignment PIN_54 -to CROW[0]
-set_location_assignment PIN_55 -to CROW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CROW
-
-set_location_assignment PIN_35 -to Din[2]
-set_location_assignment PIN_36 -to Din[1]
-set_location_assignment PIN_37 -to Din[3]
-set_location_assignment PIN_38 -to Din[5]
-set_location_assignment PIN_39 -to Din[4]
-set_location_assignment PIN_40 -to Din[7]
-set_location_assignment PIN_41 -to Din[6]
-set_location_assignment PIN_42 -to Din[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
-
-set_location_assignment PIN_33 -to Dout[0]
-set_location_assignment PIN_57 -to Dout[1]
-set_location_assignment PIN_56 -to Dout[2]
-set_location_assignment PIN_47 -to Dout[3]
-set_location_assignment PIN_44 -to Dout[4]
-set_location_assignment PIN_28 -to Dout[5]
-set_location_assignment PIN_34 -to Dout[6]
-set_location_assignment PIN_43 -to Dout[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
-
-set_location_assignment PIN_8 -to RCKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCKE
-
-set_location_assignment PIN_3 -to nRCS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCS
-
-set_location_assignment PIN_100 -to nRWE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
-
-set_location_assignment PIN_6 -to nRRAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRRAS
-
-set_location_assignment PIN_4 -to nRCAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCAS
-
-set_location_assignment PIN_5 -to RBA[0]
-set_location_assignment PIN_14 -to RBA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RBA
-
-set_location_assignment PIN_18 -to RA[0]
-set_location_assignment PIN_20 -to RA[1]
-set_location_assignment PIN_30 -to RA[2]
-set_location_assignment PIN_27 -to RA[3]
-set_location_assignment PIN_26 -to RA[4]
-set_location_assignment PIN_29 -to RA[5]
-set_location_assignment PIN_21 -to RA[6]
-set_location_assignment PIN_19 -to RA[7]
-set_location_assignment PIN_17 -to RA[8]
-set_location_assignment PIN_15 -to RA[9]
-set_location_assignment PIN_16 -to RA[10]
-set_location_assignment PIN_7 -to RA[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
-
-set_location_assignment PIN_2 -to RDQMH
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQMH
-
-set_location_assignment PIN_98 -to RDQML
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQML
-
-set_location_assignment PIN_96 -to RD[0]
-set_location_assignment PIN_90 -to RD[1]
-set_location_assignment PIN_89 -to RD[2]
-set_location_assignment PIN_99 -to RD[3]
-set_location_assignment PIN_92 -to RD[4]
-set_location_assignment PIN_91 -to RD[5]
-set_location_assignment PIN_95 -to RD[6]
-set_location_assignment PIN_97 -to RD[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
-
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS
-set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to MAin
-set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to CROW
-set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to Din
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to Dout
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to Dout
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCKE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RCKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRWE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRRAS
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRRAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCAS
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RBA
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RBA
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RBA
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RA
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RA
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQMH
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQMH
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQML
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
-set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
-set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v"
-set_global_assignment -name MIF_FILE "../RAM2GS-MAX.mif"
-set_global_assignment -name QIP_FILE UFM.qip
\ No newline at end of file
diff --git a/CPLD-old/MAX/MAXII/RAM2GS.qws b/CPLD-old/MAX/MAXII/RAM2GS.qws
deleted file mode 100644
index 4620ebd54aa138f6cfdb41c02b9004f436262c7c..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 818
zcmc(dyG{a85QcwH5=tv83kqY12^Wdtr4sR0U}8WMJG1PrN)VU8q9(={@YQT=eFq;w
z#cxiQh8PoVJSTJJ_Me@9=InM}leM60c^WF#x$YEcpe|mYn6D5}3W-(MmP$G$6M`6G
z?}EKdw6BqRWNtuO?m!)^L!xcGrfND;g=h<}u46U0T_RS~*;KxeM2osjYB%(t4XvuG
zb#$Oj&H~!UuVSsR1C_Bn&cJ2MSQW(61>4gaJOcPV{#P$H#MBeV7}19vQl>@l4P!Qu
zEIRw1I4Gr&C8ib9MXa25m}tz7m~>7j=!n;A)8W9N8na9%Yfk%I4QbsVzPjIm95pWF
zd8ZC9di9q|_FobRmX0M>O2=i-MiX*5Vrq^f6>TIcQr%E;>(O90%pM8?<*El
YuP@K;LsrABOp`7$6Ay-;Cg!L01?`7}%m4rY

diff --git a/CPLD-old/MAX/MAXII/UFM.qip b/CPLD-old/MAX/MAXII/UFM.qip
deleted file mode 100644
index e2d8458..0000000
--- a/CPLD-old/MAX/MAXII/UFM.qip
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE"
-set_global_assignment -name IP_TOOL_VERSION "13.0"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"]
diff --git a/CPLD-old/MAX/MAXII/UFM.v b/CPLD-old/MAX/MAXII/UFM.v
deleted file mode 100644
index f58dd72..0000000
--- a/CPLD-old/MAX/MAXII/UFM.v
+++ /dev/null
@@ -1,268 +0,0 @@
-// megafunction wizard: %ALTUFM_NONE%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: ALTUFM_NONE 
-
-// ============================================================
-// File Name: UFM.v
-// Megafunction Name(s):
-// 			ALTUFM_NONE
-//
-// Simulation Library Files(s):
-// 			maxii
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2013 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
-//Subscription Agreement, Altera MegaCore Function License 
-//Agreement, or other applicable license agreement, including, 
-//without limitation, that your use is for the sole purpose of 
-//programming logic devices manufactured by Altera and sold by 
-//Altera or its authorized distributors.  Please refer to the 
-//applicable agreement for further details.
-
-
-//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM2GS-MAX.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
-//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
-// synthesis VERILOG_INPUT_VERSION VERILOG_2001
-// altera message_off 10463
-
-
-//synthesis_resources = maxii_ufm 1 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  UFM_altufm_none_imr
-	( 
-	arclk,
-	ardin,
-	arshft,
-	busy,
-	drclk,
-	drdin,
-	drdout,
-	drshft,
-	erase,
-	osc,
-	oscena,
-	program,
-	rtpbusy) ;
-	input   arclk;
-	input   ardin;
-	input   arshft;
-	output   busy;
-	input   drclk;
-	input   drdin;
-	output   drdout;
-	input   drshft;
-	input   erase;
-	output   osc;
-	input   oscena;
-	input   program;
-	output   rtpbusy;
-
-	wire  wire_maxii_ufm_block1_bgpbusy;
-	wire  wire_maxii_ufm_block1_busy;
-	wire  wire_maxii_ufm_block1_drdout;
-	wire  wire_maxii_ufm_block1_osc;
-	wire  ufm_arclk;
-	wire  ufm_ardin;
-	wire  ufm_arshft;
-	wire  ufm_bgpbusy;
-	wire  ufm_busy;
-	wire  ufm_drclk;
-	wire  ufm_drdin;
-	wire  ufm_drdout;
-	wire  ufm_drshft;
-	wire  ufm_erase;
-	wire  ufm_osc;
-	wire  ufm_oscena;
-	wire  ufm_program;
-
-	maxii_ufm   maxii_ufm_block1
-	( 
-	.arclk(ufm_arclk),
-	.ardin(ufm_ardin),
-	.arshft(ufm_arshft),
-	.bgpbusy(wire_maxii_ufm_block1_bgpbusy),
-	.busy(wire_maxii_ufm_block1_busy),
-	.drclk(ufm_drclk),
-	.drdin(ufm_drdin),
-	.drdout(wire_maxii_ufm_block1_drdout),
-	.drshft(ufm_drshft),
-	.erase(ufm_erase),
-	.osc(wire_maxii_ufm_block1_osc),
-	.oscena(ufm_oscena),
-	.program(ufm_program)
-	// synopsys translate_off
-	,
-	.ctrl_bgpbusy(1'b0),
-	.devclrn(1'b1),
-	.devpor(1'b1),
-	.sbdin(1'b0),
-	.sbdout()
-	// synopsys translate_on
-	);
-	defparam
-		maxii_ufm_block1.address_width = 9,
-		maxii_ufm_block1.erase_time = 500000000,
-		maxii_ufm_block1.init_file = "RAM2GS-MAX.mif",
-		maxii_ufm_block1.mem1 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
-		maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
-		maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
-		maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
-		maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
-		maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
-		maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
-		maxii_ufm_block1.mem2 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem3 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem4 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem5 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem6 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem7 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem8 = 512'hFFFF7FFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
-		maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
-		maxii_ufm_block1.osc_sim_setting = 180000,
-		maxii_ufm_block1.program_time = 1600000,
-		maxii_ufm_block1.lpm_type = "maxii_ufm";
-	assign
-		busy = ufm_busy,
-		drdout = ufm_drdout,
-		osc = ufm_osc,
-		rtpbusy = ufm_bgpbusy,
-		ufm_arclk = arclk,
-		ufm_ardin = ardin,
-		ufm_arshft = arshft,
-		ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy,
-		ufm_busy = wire_maxii_ufm_block1_busy,
-		ufm_drclk = drclk,
-		ufm_drdin = drdin,
-		ufm_drdout = wire_maxii_ufm_block1_drdout,
-		ufm_drshft = drshft,
-		ufm_erase = erase,
-		ufm_osc = wire_maxii_ufm_block1_osc,
-		ufm_oscena = oscena,
-		ufm_program = program;
-endmodule //UFM_altufm_none_imr
-//VALID FILE
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module UFM (
-	arclk,
-	ardin,
-	arshft,
-	drclk,
-	drdin,
-	drshft,
-	erase,
-	oscena,
-	program,
-	busy,
-	drdout,
-	osc,
-	rtpbusy);
-
-	input	  arclk;
-	input	  ardin;
-	input	  arshft;
-	input	  drclk;
-	input	  drdin;
-	input	  drshft;
-	input	  erase;
-	input	  oscena;
-	input	  program;
-	output	  busy;
-	output	  drdout;
-	output	  osc;
-	output	  rtpbusy;
-
-	wire  sub_wire0;
-	wire  sub_wire1;
-	wire  sub_wire2;
-	wire  sub_wire3;
-	wire  osc = sub_wire0;
-	wire  rtpbusy = sub_wire1;
-	wire  drdout = sub_wire2;
-	wire  busy = sub_wire3;
-
-	UFM_altufm_none_imr	UFM_altufm_none_imr_component (
-				.arshft (arshft),
-				.drclk (drclk),
-				.erase (erase),
-				.program (program),
-				.arclk (arclk),
-				.drdin (drdin),
-				.oscena (oscena),
-				.ardin (ardin),
-				.drshft (drshft),
-				.osc (sub_wire0),
-				.rtpbusy (sub_wire1),
-				.drdout (sub_wire2),
-				.busy (sub_wire3));
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
-// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
-// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2GS-MAX.mif"
-// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
-// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
-// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000"
-// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9"
-// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk"
-// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0
-// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin"
-// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0
-// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft"
-// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0
-// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk"
-// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0
-// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin"
-// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0
-// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout"
-// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0
-// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft"
-// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0
-// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase"
-// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0
-// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc"
-// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0
-// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena"
-// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0
-// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program"
-// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0
-// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy"
-// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
-// Retrieval info: LIB_FILE: maxii
diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.(0).cnf.cdb b/CPLD-old/MAX/MAXII/db/RAM2GS.(0).cnf.cdb
deleted file mode 100644
index b4b4e463d631023d227d6401c0a54997f83bc633..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.cmp.logdb b/CPLD-old/MAX/MAXII/db/RAM2GS.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/CPLD-old/MAX/MAXII/db/RAM2GS.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
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diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.cmp.rdb b/CPLD-old/MAX/MAXII/db/RAM2GS.cmp.rdb
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xeGH`v`oL_NVPgNQ`FWOsTvqXFQ2W91CD(K& Bank[0].CLK
-PHI2 => Bank[1].CLK
-PHI2 => Bank[2].CLK
-PHI2 => Bank[3].CLK
-PHI2 => Bank[4].CLK
-PHI2 => Bank[5].CLK
-PHI2 => Bank[6].CLK
-PHI2 => Bank[7].CLK
-PHI2 => RA11.CLK
-PHI2 => PHI2r.DATAIN
-PHI2 => CmdDRDIn.CLK
-PHI2 => CmdDRCLK.CLK
-PHI2 => CmdUFMPrgm.CLK
-PHI2 => CmdUFMErase.CLK
-PHI2 => CmdSubmitted.CLK
-PHI2 => Cmdn8MEGEN.CLK
-PHI2 => XOR8MEG.CLK
-PHI2 => ADSubmitted.CLK
-PHI2 => C1Submitted.CLK
-PHI2 => UFMOscEN.CLK
-PHI2 => CmdEnable.CLK
-MAin[0] => RA.DATAA
-MAin[0] => RowA.DATAB
-MAin[0] => Equal0.IN7
-MAin[0] => Equal1.IN7
-MAin[0] => Equal3.IN6
-MAin[1] => RA.DATAA
-MAin[1] => RowA.DATAB
-MAin[1] => Equal0.IN6
-MAin[1] => Equal1.IN6
-MAin[1] => Equal3.IN7
-MAin[2] => RA.DATAA
-MAin[2] => RowA.DATAB
-MAin[2] => Equal0.IN5
-MAin[2] => Equal1.IN5
-MAin[2] => Equal3.IN5
-MAin[3] => RA.DATAA
-MAin[3] => RowA.DATAB
-MAin[3] => Equal0.IN4
-MAin[3] => Equal1.IN4
-MAin[3] => Equal3.IN4
-MAin[4] => RA.DATAA
-MAin[4] => RowA.DATAB
-MAin[4] => Equal0.IN3
-MAin[4] => Equal1.IN3
-MAin[4] => Equal3.IN3
-MAin[5] => RA.DATAA
-MAin[5] => RowA.DATAB
-MAin[5] => Equal0.IN2
-MAin[5] => Equal1.IN2
-MAin[5] => Equal3.IN2
-MAin[6] => RA.DATAA
-MAin[6] => RowA.DATAB
-MAin[6] => Equal0.IN1
-MAin[6] => Equal1.IN1
-MAin[6] => Equal3.IN1
-MAin[7] => RA.DATAA
-MAin[7] => RowA.DATAB
-MAin[7] => Equal0.IN0
-MAin[7] => Equal1.IN0
-MAin[7] => Equal3.IN0
-MAin[8] => RA.DATAA
-MAin[8] => RowA.DATAB
-MAin[9] => RA.DATAA
-MAin[9] => comb.DATAA
-MAin[9] => RowA.DATAB
-MAin[9] => comb.DATAA
-CROW[0] => RBA.DATAB
-CROW[1] => RBA.DATAB
-Din[0] => CmdDRDIn.DATAB
-Din[0] => XOR8MEG.DATAB
-Din[0] => WRD[0].DATAIN
-Din[0] => Bank[0].DATAIN
-Din[0] => Equal14.IN2
-Din[0] => Equal15.IN4
-Din[0] => Cmdn8MEGEN.DATAB
-Din[1] => CmdDRCLK.DATAB
-Din[1] => WRD[1].DATAIN
-Din[1] => Bank[1].DATAIN
-Din[1] => Equal14.IN7
-Din[1] => Equal15.IN7
-Din[2] => CmdUFMPrgm.DATAB
-Din[2] => WRD[2].DATAIN
-Din[2] => Bank[2].DATAIN
-Din[2] => Equal14.IN6
-Din[2] => Equal15.IN3
-Din[3] => CmdUFMErase.DATAB
-Din[3] => WRD[3].DATAIN
-Din[3] => Bank[3].DATAIN
-Din[3] => Equal14.IN5
-Din[3] => Equal15.IN2
-Din[4] => WRD[4].DATAIN
-Din[4] => Bank[4].DATAIN
-Din[4] => Equal14.IN4
-Din[4] => Equal15.IN6
-Din[4] => Equal16.IN3
-Din[4] => Equal17.IN0
-Din[4] => Equal18.IN3
-Din[5] => WRD[5].DATAIN
-Din[5] => Bank[5].DATAIN
-Din[5] => Equal14.IN3
-Din[5] => Equal15.IN1
-Din[5] => Equal16.IN2
-Din[5] => Equal17.IN3
-Din[5] => Equal18.IN0
-Din[6] => RA11.IN1
-Din[6] => WRD[6].DATAIN
-Din[6] => Bank[6].DATAIN
-Din[6] => Equal14.IN1
-Din[6] => Equal15.IN5
-Din[6] => Equal16.IN1
-Din[6] => Equal17.IN2
-Din[6] => Equal18.IN2
-Din[7] => WRD[7].DATAIN
-Din[7] => Bank[7].DATAIN
-Din[7] => Equal14.IN0
-Din[7] => Equal15.IN0
-Din[7] => Equal16.IN0
-Din[7] => Equal17.IN1
-Din[7] => Equal18.IN1
-Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE
-Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE
-Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE
-Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE
-Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE
-Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE
-Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE
-Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE
-nCCAS => WRD[0].CLK
-nCCAS => WRD[1].CLK
-nCCAS => WRD[2].CLK
-nCCAS => WRD[3].CLK
-nCCAS => WRD[4].CLK
-nCCAS => WRD[5].CLK
-nCCAS => WRD[6].CLK
-nCCAS => WRD[7].CLK
-nCCAS => comb.IN0
-nCCAS => CBR.DATAIN
-nCCAS => CASr.DATAIN
-nCRAS => CBR.CLK
-nCRAS => FWEr.CLK
-nCRAS => RowA[0].CLK
-nCRAS => RowA[1].CLK
-nCRAS => RowA[2].CLK
-nCRAS => RowA[3].CLK
-nCRAS => RowA[4].CLK
-nCRAS => RowA[5].CLK
-nCRAS => RowA[6].CLK
-nCRAS => RowA[7].CLK
-nCRAS => RowA[8].CLK
-nCRAS => RowA[9].CLK
-nCRAS => RBA[0]~reg0.CLK
-nCRAS => RBA[1]~reg0.CLK
-nCRAS => comb.IN1
-nCRAS => RASr.DATAIN
-nFWE => comb.IN1
-nFWE => CMDWR.IN1
-nFWE => ADWR.IN1
-nFWE => C1WR.IN1
-nFWE => FWEr.DATAIN
-LED <= comb.DB_MAX_OUTPUT_PORT_TYPE
-RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE
-RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE
-RD[0] <> RD[0]
-RD[1] <> RD[1]
-RD[2] <> RD[2]
-RD[3] <> RD[3]
-RD[4] <> RD[4]
-RD[5] <> RD[5]
-RD[6] <> RD[6]
-RD[7] <> RD[7]
-nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RCLK => UFMProgram.CLK
-RCLK => UFMErase.CLK
-RCLK => UFMReqErase.CLK
-RCLK => LEDEN.CLK
-RCLK => UFMInitDone.CLK
-RCLK => n8MEGEN.CLK
-RCLK => UFMD[15].CLK
-RCLK => DRShift.CLK
-RCLK => DRDIn.CLK
-RCLK => DRCLK.CLK
-RCLK => ARShift.CLK
-RCLK => ARCLK.CLK
-RCLK => Ready.CLK
-RCLK => IS[0].CLK
-RCLK => IS[1].CLK
-RCLK => IS[2].CLK
-RCLK => IS[3].CLK
-RCLK => nRowColSel.CLK
-RCLK => RCKEEN.CLK
-RCLK => RA10.CLK
-RCLK => nRWE~reg0.CLK
-RCLK => nRCAS~reg0.CLK
-RCLK => nRRAS~reg0.CLK
-RCLK => nRCS~reg0.CLK
-RCLK => RCKE~reg0.CLK
-RCLK => InitReady.CLK
-RCLK => FS[0].CLK
-RCLK => FS[1].CLK
-RCLK => FS[2].CLK
-RCLK => FS[3].CLK
-RCLK => FS[4].CLK
-RCLK => FS[5].CLK
-RCLK => FS[6].CLK
-RCLK => FS[7].CLK
-RCLK => FS[8].CLK
-RCLK => FS[9].CLK
-RCLK => FS[10].CLK
-RCLK => FS[11].CLK
-RCLK => FS[12].CLK
-RCLK => FS[13].CLK
-RCLK => FS[14].CLK
-RCLK => FS[15].CLK
-RCLK => FS[16].CLK
-RCLK => FS[17].CLK
-RCLK => S[0].CLK
-RCLK => S[1].CLK
-RCLK => CASr3.CLK
-RCLK => CASr2.CLK
-RCLK => CASr.CLK
-RCLK => RASr3.CLK
-RCLK => RASr2.CLK
-RCLK => RASr.CLK
-RCLK => PHI2r3.CLK
-RCLK => PHI2r2.CLK
-RCLK => PHI2r.CLK
-RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RDQMH <= comb.DB_MAX_OUTPUT_PORT_TYPE
-RDQML <= comb.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|RAM2GS|UFM:UFM_inst
-arclk => arclk.IN1
-ardin => ardin.IN1
-arshft => arshft.IN1
-drclk => drclk.IN1
-drdin => drdin.IN1
-drshft => drshft.IN1
-erase => erase.IN1
-oscena => oscena.IN1
-program => program.IN1
-busy <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.busy
-drdout <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.drdout
-osc <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.osc
-rtpbusy <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.rtpbusy
-
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-|RAM2GS|UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component
-arclk => maxii_ufm_block1.ARCLK
-ardin => maxii_ufm_block1.ARDIN
-arshft => maxii_ufm_block1.ARSHFT
-busy <= maxii_ufm_block1.BUSY
-drclk => maxii_ufm_block1.DRCLK
-drdin => maxii_ufm_block1.DRDIN
-drdout <= maxii_ufm_block1.DRDOUT
-drshft => maxii_ufm_block1.DRSHFT
-erase => maxii_ufm_block1.ERASE
-osc <= maxii_ufm_block1.OSC
-oscena => maxii_ufm_block1.OSCENA
-program => maxii_ufm_block1.PROGRAM
-rtpbusy <= maxii_ufm_block1.BGPBUSY
-
-
diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.hif b/CPLD-old/MAX/MAXII/db/RAM2GS.hif
deleted file mode 100644
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diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.ipinfo b/CPLD-old/MAX/MAXII/db/RAM2GS.ipinfo
deleted file mode 100644
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diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.lpc.html b/CPLD-old/MAX/MAXII/db/RAM2GS.lpc.html
deleted file mode 100644
index 76d3fb3..0000000
--- a/CPLD-old/MAX/MAXII/db/RAM2GS.lpc.html
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    HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
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diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.smart_action.txt b/CPLD-old/MAX/MAXII/db/RAM2GS.smart_action.txt
deleted file mode 100644
index c8e8a13..0000000
--- a/CPLD-old/MAX/MAXII/db/RAM2GS.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.sta.qmsg b/CPLD-old/MAX/MAXII/db/RAM2GS.sta.qmsg
deleted file mode 100644
index 33c9310..0000000
--- a/CPLD-old/MAX/MAXII/db/RAM2GS.sta.qmsg
+++ /dev/null
@@ -1,23 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153618889 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:18 2021 " "Processing started: Mon Aug 16 18:40:18 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1629153618967 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153619091 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153619138 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153619138 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1629153619201 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1629153619419 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1629153619466 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1629153619466 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1629153619481 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 ARCLK  " "  -99.000       -99.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 DRCLK  " "  -99.000       -99.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -8.339      -245.761 RCLK  " "   -8.339      -245.761 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -8.271       -88.383 PHI2  " "   -8.271       -88.383 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.317        -2.784 nCRAS  " "   -0.317        -2.784 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.858 " "Worst-case hold slack is -16.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.858       -16.858 ARCLK  " "  -16.858       -16.858 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.363       -16.363 DRCLK  " "  -16.363       -16.363 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.103        -0.195 nCRAS  " "   -0.103        -0.195 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.060        -0.060 PHI2  " "   -0.060        -0.060 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.192         0.000 RCLK  " "    1.192         0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153619481 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153619481 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 ARCLK  " "  -29.500       -59.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 DRCLK  " "  -29.500       -59.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 PHI2  " "   -2.289        -2.289 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 RCLK  " "   -2.289        -2.289 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCCAS  " "   -2.289        -2.289 nCCAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCRAS  " "   -2.289        -2.289 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1629153619559 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153619575 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153619575 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:19 2021 " "Processing ended: Mon Aug 16 18:40:19 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""}
diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.sta.rdb b/CPLD-old/MAX/MAXII/db/RAM2GS.sta.rdb
deleted file mode 100644
index 1d009218e1e950ef537174349c457013236bc5ef..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.syn_hier_info b/CPLD-old/MAX/MAXII/db/RAM2GS.syn_hier_info
deleted file mode 100644
index e69de29..0000000
diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.tis_db_list.ddb b/CPLD-old/MAX/MAXII/db/RAM2GS.tis_db_list.ddb
deleted file mode 100644
index 91bbe104745429a84af8ec3fe7aa1f8ec8927ccf..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 191
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diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.tmw_info b/CPLD-old/MAX/MAXII/db/RAM2GS.tmw_info
deleted file mode 100644
index 16f5f5b..0000000
--- a/CPLD-old/MAX/MAXII/db/RAM2GS.tmw_info
+++ /dev/null
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diff --git a/CPLD-old/MAX/MAXII/db/RAM2GS.vpr.ammdb b/CPLD-old/MAX/MAXII/db/RAM2GS.vpr.ammdb
deleted file mode 100644
index e64e99276b94253d28f84016db50be4d5ff08ac4..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CPLD-old/MAX/MAXII/db/logic_util_heursitic.dat b/CPLD-old/MAX/MAXII/db/logic_util_heursitic.dat
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GIT binary patch
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diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.asm.rpt b/CPLD-old/MAX/MAXII/output_files/RAM2GS.asm.rpt
deleted file mode 100644
index 878a98d..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.asm.rpt
+++ /dev/null
@@ -1,114 +0,0 @@
-Assembler report for RAM2GS
-Mon Aug 16 18:40:17 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Mon Aug 16 18:40:17 2021 ;
-; Revision Name         ; RAM2GS                                ;
-; Top-level Entity Name ; RAM2GS                                ;
-; Family                ; MAX II                                ;
-; Device                ; EPM240T100C5                          ;
-+-----------------------+---------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Assembler Settings                                                                                      ;
-+-----------------------------------------------------------------------------+-----------+---------------+
-; Option                                                                      ; Setting   ; Default Value ;
-+-----------------------------------------------------------------------------+-----------+---------------+
-; Use smart compilation                                                       ; Off       ; Off           ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On        ; On            ;
-; Enable compact report table                                                 ; Off       ; Off           ;
-; Compression mode                                                            ; Off       ; Off           ;
-; Clock source for configuration device                                       ; Internal  ; Internal      ;
-; Clock frequency of the configuration device                                 ; 10 MHZ    ; 10 MHz        ;
-; Divide clock frequency by                                                   ; 1         ; 1             ;
-; Auto user code                                                              ; On        ; On            ;
-; Security bit                                                                ; Off       ; Off           ;
-; Use configuration device                                                    ; On        ; On            ;
-; Configuration device                                                        ; Auto      ; Auto          ;
-; Configuration device auto user code                                         ; Off       ; Off           ;
-; Generate Tabular Text File (.ttf) For Target Device                         ; Off       ; Off           ;
-; Generate Raw Binary File (.rbf) For Target Device                           ; Off       ; Off           ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off       ; Off           ;
-; Hexadecimal Output File start address                                       ; 0         ; 0             ;
-; Hexadecimal Output File count direction                                     ; Up        ; Up            ;
-; Generate Serial Vector Format File (.svf) for Target Device                 ; Off       ; Off           ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off       ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off       ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On        ; On            ;
-; In-System Programming Default Clamp State                                   ; Tri-state ; Tri-state     ;
-+-----------------------------------------------------------------------------+-----------+---------------+
-
-
-+-----------------------------------------------------------------------------+
-; Assembler Generated Files                                                   ;
-+-----------------------------------------------------------------------------+
-; File Name                                                                   ;
-+-----------------------------------------------------------------------------+
-; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pof ;
-+-----------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------+
-; Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pof ;
-+----------------+--------------------------------------------------------------------------------------+
-; Option         ; Setting                                                                              ;
-+----------------+--------------------------------------------------------------------------------------+
-; Device         ; EPM240T100C5                                                                         ;
-; JTAG usercode  ; 0x001737AB                                                                           ;
-; Checksum       ; 0x00173A1B                                                                           ;
-+----------------+--------------------------------------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II 64-Bit Assembler
-    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Mon Aug 16 18:40:17 2021
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 381 megabytes
-    Info: Processing ended: Mon Aug 16 18:40:17 2021
-    Info: Elapsed time: 00:00:00
-    Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.done b/CPLD-old/MAX/MAXII/output_files/RAM2GS.done
deleted file mode 100644
index ad0c117..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.done
+++ /dev/null
@@ -1 +0,0 @@
-Mon Aug 16 18:40:20 2021
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.fit.rpt b/CPLD-old/MAX/MAXII/output_files/RAM2GS.fit.rpt
deleted file mode 100644
index 29e0daf..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.fit.rpt
+++ /dev/null
@@ -1,998 +0,0 @@
-Fitter report for RAM2GS
-Mon Aug 16 18:40:16 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. Pin-Out File
-  6. Fitter Resource Usage Summary
-  7. Input Pins
-  8. Output Pins
-  9. Bidir Pins
- 10. I/O Bank Usage
- 11. All Package Pins
- 12. Output Pin Default Load For Reported TCO
- 13. Fitter Resource Utilization by Entity
- 14. Delay Chain Summary
- 15. Control Signals
- 16. Global & Other Fast Signals
- 17. Non-Global High Fan-Out Signals
- 18. Other Routing Usage Summary
- 19. LAB Logic Elements
- 20. LAB-wide Signals
- 21. LAB Signals Sourced
- 22. LAB Signals Sourced Out
- 23. LAB Distinct Inputs
- 24. Fitter Device Options
- 25. Estimated Delay Added for Hold Timing Summary
- 26. Estimated Delay Added for Hold Timing Details
- 27. Fitter Messages
- 28. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------+
-; Fitter Summary                                                              ;
-+---------------------------+-------------------------------------------------+
-; Fitter Status             ; Successful - Mon Aug 16 18:40:16 2021           ;
-; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name             ; RAM2GS                                          ;
-; Top-level Entity Name     ; RAM2GS                                          ;
-; Family                    ; MAX II                                          ;
-; Device                    ; EPM240T100C5                                    ;
-; Timing Models             ; Final                                           ;
-; Total logic elements      ; 168 / 240 ( 70 % )                              ;
-; Total pins                ; 63 / 80 ( 79 % )                                ;
-; Total virtual pins        ; 0                                               ;
-; UFM blocks                ; 1 / 1 ( 100 % )                                 ;
-+---------------------------+-------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                              ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Option                                                                     ; Setting                        ; Default Value                  ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Device                                                                     ; EPM240T100C5                   ;                                ;
-; Minimum Core Junction Temperature                                          ; 0                              ;                                ;
-; Maximum Core Junction Temperature                                          ; 85                             ;                                ;
-; Placement Effort Multiplier                                                ; 10                             ; 1.0                            ;
-; Router Effort Multiplier                                                   ; 10                             ; 1.0                            ;
-; Fit Attempts to Skip                                                       ; 0                              ; 0.0                            ;
-; Device I/O Standard                                                        ; 3.3-V LVTTL                    ;                                ;
-; Optimize Multi-Corner Timing                                               ; On                             ; Off                            ;
-; Optimize IOC Register Placement for Timing                                 ; Pack All IO Registers          ; Normal                         ;
-; Enable Bus-Hold Circuitry                                                  ; On                             ; Off                            ;
-; Fitter Effort                                                              ; Standard Fit                   ; Auto Fit                       ;
-; Use smart compilation                                                      ; Off                            ; Off                            ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                             ; On                             ;
-; Enable compact report table                                                ; Off                            ; Off                            ;
-; Router Timing Optimization Level                                           ; Normal                         ; Normal                         ;
-; Always Enable Input Buffers                                                ; Off                            ; Off                            ;
-; Optimize Hold Timing                                                       ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
-; Guarantee I/O Paths Have Zero Hold Time at Fast Corner                     ; On                             ; On                             ;
-; PowerPlay Power Optimization                                               ; Normal compilation             ; Normal compilation             ;
-; Optimize Timing                                                            ; Normal compilation             ; Normal compilation             ;
-; Optimize Timing for ECOs                                                   ; Off                            ; Off                            ;
-; Regenerate full fit report during ECO compiles                             ; Off                            ; Off                            ;
-; Limit to One Fitting Attempt                                               ; Off                            ; Off                            ;
-; Final Placement Optimizations                                              ; Automatically                  ; Automatically                  ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                  ; Automatically                  ;
-; Fitter Initial Placement Seed                                              ; 1                              ; 1                              ;
-; Slow Slew Rate                                                             ; Off                            ; Off                            ;
-; PCI I/O                                                                    ; Off                            ; Off                            ;
-; Weak Pull-Up Resistor                                                      ; Off                            ; Off                            ;
-; Auto Delay Chains                                                          ; On                             ; On                             ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                            ; Off                            ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                            ; Off                            ;
-; Perform Register Duplication for Performance                               ; Off                            ; Off                            ;
-; Perform Register Retiming for Performance                                  ; Off                            ; Off                            ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                            ; Off                            ;
-; Physical Synthesis Effort Level                                            ; Normal                         ; Normal                         ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                           ; Auto                           ;
-; Auto Register Duplication                                                  ; Auto                           ; Auto                           ;
-; Auto Global Clock                                                          ; On                             ; On                             ;
-; Auto Global Register Control Signals                                       ; On                             ; On                             ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                            ; Off                            ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 12     ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.pin.
-
-
-+------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                    ;
-+---------------------------------------------+--------------------+
-; Resource                                    ; Usage              ;
-+---------------------------------------------+--------------------+
-; Total logic elements                        ; 168 / 240 ( 70 % ) ;
-;     -- Combinational with no register       ; 71                 ;
-;     -- Register only                        ; 20                 ;
-;     -- Combinational with a register        ; 77                 ;
-;                                             ;                    ;
-; Logic element usage by number of LUT inputs ;                    ;
-;     -- 4 input functions                    ; 58                 ;
-;     -- 3 input functions                    ; 40                 ;
-;     -- 2 input functions                    ; 41                 ;
-;     -- 1 input functions                    ; 8                  ;
-;     -- 0 input functions                    ; 1                  ;
-;                                             ;                    ;
-; Logic elements by mode                      ;                    ;
-;     -- normal mode                          ; 152                ;
-;     -- arithmetic mode                      ; 16                 ;
-;     -- qfbk mode                            ; 7                  ;
-;     -- register cascade mode                ; 0                  ;
-;     -- synchronous clear/load mode          ; 25                 ;
-;     -- asynchronous clear/load mode         ; 0                  ;
-;                                             ;                    ;
-; Total registers                             ; 97 / 240 ( 40 % )  ;
-; Total LABs                                  ; 23 / 24 ( 96 % )   ;
-; Logic elements in carry chains              ; 17                 ;
-; Virtual pins                                ; 0                  ;
-; I/O pins                                    ; 63 / 80 ( 79 % )   ;
-;     -- Clock pins                           ; 2 / 4 ( 50 % )     ;
-;                                             ;                    ;
-; Global signals                              ; 4                  ;
-; UFM blocks                                  ; 1 / 1 ( 100 % )    ;
-; Global clocks                               ; 4 / 4 ( 100 % )    ;
-; JTAGs                                       ; 0 / 1 ( 0 % )      ;
-; Average interconnect usage (total/H/V)      ; 21% / 23% / 19%    ;
-; Peak interconnect usage (total/H/V)         ; 21% / 23% / 19%    ;
-; Maximum fan-out                             ; 55                 ;
-; Highest non-global fan-out                  ; 39                 ;
-; Total fan-out                               ; 643                ;
-; Average fan-out                             ; 2.77               ;
-+---------------------------------------------+--------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                     ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
-; CROW[0] ; 54    ; 2        ; 8            ; 1            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; CROW[1] ; 55    ; 2        ; 8            ; 1            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[0]  ; 42    ; 1        ; 5            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[1]  ; 36    ; 1        ; 4            ; 0            ; 2           ; 4                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[2]  ; 35    ; 1        ; 3            ; 0            ; 0           ; 5                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[3]  ; 37    ; 1        ; 4            ; 0            ; 1           ; 5                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[4]  ; 39    ; 1        ; 5            ; 0            ; 3           ; 7                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[5]  ; 38    ; 1        ; 4            ; 0            ; 0           ; 7                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[6]  ; 41    ; 1        ; 5            ; 0            ; 1           ; 8                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[7]  ; 40    ; 1        ; 5            ; 0            ; 2           ; 6                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[0] ; 49    ; 1        ; 7            ; 0            ; 2           ; 5                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[1] ; 51    ; 1        ; 7            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[2] ; 50    ; 1        ; 7            ; 0            ; 1           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[3] ; 71    ; 2        ; 8            ; 4            ; 3           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[4] ; 70    ; 2        ; 8            ; 4            ; 4           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[5] ; 69    ; 2        ; 8            ; 3            ; 0           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[6] ; 72    ; 2        ; 8            ; 4            ; 2           ; 4                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[7] ; 68    ; 2        ; 8            ; 3            ; 1           ; 4                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[8] ; 73    ; 2        ; 8            ; 4            ; 1           ; 2                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[9] ; 74    ; 2        ; 8            ; 4            ; 0           ; 4                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; PHI2    ; 52    ; 2        ; 8            ; 1            ; 4           ; 21                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; RCLK    ; 12    ; 1        ; 1            ; 3            ; 3           ; 55                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; nCCAS   ; 53    ; 2        ; 8            ; 1            ; 3           ; 11                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; nCRAS   ; 67    ; 2        ; 8            ; 3            ; 2           ; 16                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; nFWE    ; 48    ; 1        ; 6            ; 0            ; 0           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                               ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Dout[0] ; 33    ; 1        ; 3            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[1] ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[2] ; 56    ; 2        ; 8            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[3] ; 47    ; 1        ; 6            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[4] ; 44    ; 1        ; 6            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[5] ; 28    ; 1        ; 2            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[6] ; 34    ; 1        ; 3            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[7] ; 43    ; 1        ; 6            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; LED     ; 66    ; 2        ; 8            ; 3            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVTTL  ; 16mA             ; yes                    ; Fitter               ; 10 pF ; -                    ; -                   ;
-; RA[0]   ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[10]  ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[11]  ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[1]   ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[2]   ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[3]   ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[4]   ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[5]   ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[6]   ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[7]   ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[8]   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[9]   ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RBA[0]  ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RBA[1]  ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RCKE    ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RDQMH   ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RDQML   ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRCAS   ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nRCS    ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRRAS   ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nRWE    ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Bidir Pins                                                                                                                                                                                                                                                                                                                                                    ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; RD[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[1] ; 90    ; 2        ; 4            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[2] ; 89    ; 2        ; 4            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[3] ; 99    ; 2        ; 2            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[4] ; 92    ; 2        ; 3            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[7] ; 97    ; 2        ; 3            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------+
-; I/O Bank Usage                                              ;
-+----------+-------------------+---------------+--------------+
-; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
-+----------+-------------------+---------------+--------------+
-; 1        ; 38 / 38 ( 100 % ) ; 3.3V          ; --           ;
-; 2        ; 25 / 42 ( 60 % )  ; 3.3V          ; --           ;
-+----------+-------------------+---------------+--------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                               ;
-+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage   ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
-; 1        ; 83         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 2        ; 0          ; 1        ; RDQMH          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 3        ; 1          ; 1        ; nRCS           ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 4        ; 2          ; 1        ; nRCAS          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 5        ; 3          ; 1        ; RBA[0]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 6        ; 4          ; 1        ; nRRAS          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 7        ; 5          ; 1        ; RA[11]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 8        ; 6          ; 1        ; RCKE           ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 9        ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 10       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 11       ;            ;          ; GNDINT         ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 12       ; 7          ; 1        ; RCLK           ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 13       ;            ;          ; VCCINT         ; power  ;              ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
-; 14       ; 8          ; 1        ; RBA[1]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 15       ; 9          ; 1        ; RA[9]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 16       ; 10         ; 1        ; RA[10]         ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 17       ; 11         ; 1        ; RA[8]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 18       ; 12         ; 1        ; RA[0]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 19       ; 13         ; 1        ; RA[7]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 20       ; 14         ; 1        ; RA[1]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 21       ; 15         ; 1        ; RA[6]          ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 22       ; 16         ; 1        ; #TMS           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
-; 23       ; 17         ; 1        ; #TDI           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
-; 24       ; 18         ; 1        ; #TCK           ; input  ;              ;           ; --         ;                 ; --       ; --           ;
-; 25       ; 19         ; 1        ; #TDO           ; output ;              ;           ; --         ;                 ; --       ; --           ;
-; 26       ; 20         ; 1        ; RA[4]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 27       ; 21         ; 1        ; RA[3]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 28       ; 22         ; 1        ; Dout[5]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 29       ; 23         ; 1        ; RA[5]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 30       ; 24         ; 1        ; RA[2]          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 31       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 32       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 33       ; 25         ; 1        ; Dout[0]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 34       ; 26         ; 1        ; Dout[6]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 35       ; 27         ; 1        ; Din[2]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 36       ; 28         ; 1        ; Din[1]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 37       ; 29         ; 1        ; Din[3]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 38       ; 30         ; 1        ; Din[5]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 39       ; 31         ; 1        ; Din[4]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 40       ; 32         ; 1        ; Din[7]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 41       ; 33         ; 1        ; Din[6]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 42       ; 34         ; 1        ; Din[0]         ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 43       ; 35         ; 1        ; Dout[7]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 44       ; 36         ; 1        ; Dout[4]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 45       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 46       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 47       ; 37         ; 1        ; Dout[3]        ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 48       ; 38         ; 1        ; nFWE           ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 49       ; 39         ; 1        ; MAin[0]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 50       ; 40         ; 1        ; MAin[2]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 51       ; 41         ; 1        ; MAin[1]        ; input  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 52       ; 42         ; 2        ; PHI2           ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 53       ; 43         ; 2        ; nCCAS          ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 54       ; 44         ; 2        ; CROW[0]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 55       ; 45         ; 2        ; CROW[1]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 56       ; 46         ; 2        ; Dout[2]        ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 57       ; 47         ; 2        ; Dout[1]        ; output ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 58       ; 48         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 59       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 60       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 61       ; 49         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 62       ; 50         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 63       ;            ;          ; VCCINT         ; power  ;              ; 2.5V/3.3V ; --         ;                 ; --       ; --           ;
-; 64       ; 51         ; 2        ; GND*           ;        ;              ;           ; Row I/O    ;                 ; no       ; Off          ;
-; 65       ;            ;          ; GNDINT         ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 66       ; 52         ; 2        ; LED            ; output ; 3.3-V LVTTL  ;           ; Row I/O    ; N               ; yes      ; Off          ;
-; 67       ; 53         ; 2        ; nCRAS          ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 68       ; 54         ; 2        ; MAin[7]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 69       ; 55         ; 2        ; MAin[5]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 70       ; 56         ; 2        ; MAin[4]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 71       ; 57         ; 2        ; MAin[3]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 72       ; 58         ; 2        ; MAin[6]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 73       ; 59         ; 2        ; MAin[8]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 74       ; 60         ; 2        ; MAin[9]        ; input  ; 3.3-V LVCMOS ;           ; Row I/O    ; Y               ; yes      ; Off          ;
-; 75       ; 61         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 76       ; 62         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 77       ; 63         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 78       ; 64         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 79       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 80       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 81       ; 65         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 82       ; 66         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 83       ; 67         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 84       ; 68         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 85       ; 69         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 86       ; 70         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 87       ; 71         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 88       ; 72         ; 2        ; GND*           ;        ;              ;           ; Column I/O ;                 ; no       ; Off          ;
-; 89       ; 73         ; 2        ; RD[2]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 90       ; 74         ; 2        ; RD[1]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 91       ; 75         ; 2        ; RD[5]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 92       ; 76         ; 2        ; RD[4]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 93       ;            ;          ; GNDIO          ; gnd    ;              ;           ; --         ;                 ; --       ; --           ;
-; 94       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V      ; --         ;                 ; --       ; --           ;
-; 95       ; 77         ; 2        ; RD[6]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 96       ; 78         ; 2        ; RD[0]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 97       ; 79         ; 2        ; RD[7]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 98       ; 80         ; 2        ; RDQML          ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 99       ; 81         ; 2        ; RD[3]          ; bidir  ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-; 100      ; 82         ; 2        ; nRWE           ; output ; 3.3-V LVCMOS ;           ; Column I/O ; Y               ; yes      ; Off          ;
-+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------------------+
-; Output Pin Default Load For Reported TCO                    ;
-+----------------------------+-------+------------------------+
-; I/O Standard               ; Load  ; Termination Resistance ;
-+----------------------------+-------+------------------------+
-; 3.3-V LVTTL                ; 10 pF ; Not Available          ;
-; 3.3-V LVCMOS               ; 10 pF ; Not Available          ;
-; 2.5 V                      ; 10 pF ; Not Available          ;
-; 1.8 V                      ; 10 pF ; Not Available          ;
-; 1.5 V                      ; 10 pF ; Not Available          ;
-; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available          ;
-; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available          ;
-+----------------------------+-------+------------------------+
-Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                  ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; |RAM2GS                                                   ; 168 (168)   ; 97           ; 1          ; 63   ; 0            ; 71 (71)      ; 20 (20)           ; 77 (77)          ; 17 (17)         ; 7 (7)      ; |RAM2GS                                                                ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; work         ;
-;       |UFM_altufm_none_imr:UFM_altufm_none_imr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------+
-; Delay Chain Summary                ;
-+---------+----------+---------------+
-; Name    ; Pin Type ; Pad to Core 0 ;
-+---------+----------+---------------+
-; nCRAS   ; Input    ; (0)           ;
-; MAin[0] ; Input    ; (0)           ;
-; MAin[1] ; Input    ; (0)           ;
-; MAin[2] ; Input    ; (0)           ;
-; MAin[3] ; Input    ; (0)           ;
-; MAin[4] ; Input    ; (0)           ;
-; MAin[5] ; Input    ; (0)           ;
-; MAin[6] ; Input    ; (0)           ;
-; MAin[7] ; Input    ; (0)           ;
-; MAin[8] ; Input    ; (0)           ;
-; MAin[9] ; Input    ; (0)           ;
-; RCLK    ; Input    ; (0)           ;
-; CROW[0] ; Input    ; (1)           ;
-; CROW[1] ; Input    ; (1)           ;
-; PHI2    ; Input    ; (0)           ;
-; Din[6]  ; Input    ; (1)           ;
-; nFWE    ; Input    ; (1)           ;
-; Din[0]  ; Input    ; (1)           ;
-; Din[7]  ; Input    ; (1)           ;
-; Din[1]  ; Input    ; (1)           ;
-; Din[4]  ; Input    ; (1)           ;
-; Din[5]  ; Input    ; (1)           ;
-; Din[2]  ; Input    ; (1)           ;
-; Din[3]  ; Input    ; (1)           ;
-; nCCAS   ; Input    ; (0)           ;
-; Dout[0] ; Output   ; --            ;
-; Dout[1] ; Output   ; --            ;
-; Dout[2] ; Output   ; --            ;
-; Dout[3] ; Output   ; --            ;
-; Dout[4] ; Output   ; --            ;
-; Dout[5] ; Output   ; --            ;
-; Dout[6] ; Output   ; --            ;
-; Dout[7] ; Output   ; --            ;
-; LED     ; Output   ; --            ;
-; RBA[0]  ; Output   ; --            ;
-; RBA[1]  ; Output   ; --            ;
-; RA[0]   ; Output   ; --            ;
-; RA[1]   ; Output   ; --            ;
-; RA[2]   ; Output   ; --            ;
-; RA[3]   ; Output   ; --            ;
-; RA[4]   ; Output   ; --            ;
-; RA[5]   ; Output   ; --            ;
-; RA[6]   ; Output   ; --            ;
-; RA[7]   ; Output   ; --            ;
-; RA[8]   ; Output   ; --            ;
-; RA[9]   ; Output   ; --            ;
-; RA[10]  ; Output   ; --            ;
-; RA[11]  ; Output   ; --            ;
-; nRCS    ; Output   ; --            ;
-; RCKE    ; Output   ; --            ;
-; nRWE    ; Output   ; --            ;
-; nRRAS   ; Output   ; --            ;
-; nRCAS   ; Output   ; --            ;
-; RDQMH   ; Output   ; --            ;
-; RDQML   ; Output   ; --            ;
-; RD[0]   ; Bidir    ; (0)           ;
-; RD[1]   ; Bidir    ; (0)           ;
-; RD[2]   ; Bidir    ; (0)           ;
-; RD[3]   ; Bidir    ; (0)           ;
-; RD[4]   ; Bidir    ; (0)           ;
-; RD[5]   ; Bidir    ; (0)           ;
-; RD[6]   ; Bidir    ; (0)           ;
-; RD[7]   ; Bidir    ; (0)           ;
-+---------+----------+---------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                     ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; Name           ; Location    ; Fan-Out ; Usage                   ; Global ; Global Resource Used ; Global Line Name ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; CmdDRDIn~1     ; LC_X6_Y2_N5 ; 4       ; Clock enable            ; no     ; --                   ; --               ;
-; CmdSubmitted~0 ; LC_X5_Y2_N5 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
-; DRDIn~1        ; LC_X4_Y1_N2 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
-; PHI2           ; PIN_52      ; 21      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ;
-; RCLK           ; PIN_12      ; 55      ; Clock                   ; yes    ; Global Clock         ; GCLK0            ;
-; Ready          ; LC_X3_Y4_N6 ; 39      ; Sync. clear, Sync. load ; no     ; --                   ; --               ;
-; always8~5      ; LC_X6_Y2_N2 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
-; comb~3         ; LC_X4_Y4_N9 ; 8       ; Output enable           ; no     ; --                   ; --               ;
-; nCCAS          ; PIN_53      ; 11      ; Clock                   ; yes    ; Global Clock         ; GCLK2            ;
-; nCRAS          ; PIN_67      ; 16      ; Clock                   ; yes    ; Global Clock         ; GCLK1            ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-
-
-+----------------------------------------------------------------------+
-; Global & Other Fast Signals                                          ;
-+-------+----------+---------+----------------------+------------------+
-; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
-+-------+----------+---------+----------------------+------------------+
-; PHI2  ; PIN_52   ; 21      ; Global Clock         ; GCLK3            ;
-; RCLK  ; PIN_12   ; 55      ; Global Clock         ; GCLK0            ;
-; nCCAS ; PIN_53   ; 11      ; Global Clock         ; GCLK2            ;
-; nCRAS ; PIN_67   ; 16      ; Global Clock         ; GCLK1            ;
-+-------+----------+---------+----------------------+------------------+
-
-
-+-------------------------------------------------------------------------------------------------------+
-; Non-Global High Fan-Out Signals                                                                       ;
-+---------------------------------------------------------------------------------------------+---------+
-; Name                                                                                        ; Fan-Out ;
-+---------------------------------------------------------------------------------------------+---------+
-; Ready                                                                                       ; 39      ;
-; nRowColSel                                                                                  ; 13      ;
-; S[1]                                                                                        ; 12      ;
-; S[0]                                                                                        ; 12      ;
-; RASr2                                                                                       ; 9       ;
-; Din[6]                                                                                      ; 8       ;
-; comb~3                                                                                      ; 8       ;
-; Din[5]                                                                                      ; 7       ;
-; Din[4]                                                                                      ; 7       ;
-; IS[0]~0                                                                                     ; 7       ;
-; Din[7]                                                                                      ; 6       ;
-; Din[0]                                                                                      ; 6       ;
-; MAin[1]                                                                                     ; 6       ;
-; IS[0]                                                                                       ; 6       ;
-; FS[4]                                                                                       ; 6       ;
-; Din[3]                                                                                      ; 5       ;
-; Din[2]                                                                                      ; 5       ;
-; MAin[0]                                                                                     ; 5       ;
-; FS[8]~31                                                                                    ; 5       ;
-; FS[3]~13                                                                                    ; 5       ;
-; FS[3]                                                                                       ; 5       ;
-; IS[1]                                                                                       ; 5       ;
-; CBR                                                                                         ; 5       ;
-; FWEr                                                                                        ; 5       ;
-; FS[6]                                                                                       ; 5       ;
-; FS[5]                                                                                       ; 5       ;
-; FS[17]                                                                                      ; 5       ;
-; FS[16]                                                                                      ; 5       ;
-; UFMD[15]                                                                                    ; 5       ;
-; Din[1]                                                                                      ; 4       ;
-; MAin[9]                                                                                     ; 4       ;
-; MAin[7]                                                                                     ; 4       ;
-; MAin[6]                                                                                     ; 4       ;
-; CmdDRDIn~1                                                                                  ; 4       ;
-; FS[13]~27                                                                                   ; 4       ;
-; CMDWR~2                                                                                     ; 4       ;
-; UFMReqErase                                                                                 ; 4       ;
-; always9~3                                                                                   ; 4       ;
-; DRCLK~0                                                                                     ; 4       ;
-; always9~2                                                                                   ; 4       ;
-; Equal9~0                                                                                    ; 4       ;
-; IS[3]                                                                                       ; 4       ;
-; IS[2]                                                                                       ; 4       ;
-; InitReady                                                                                   ; 4       ;
-; always9~0                                                                                   ; 4       ;
-; nFWE                                                                                        ; 3       ;
-; MAin[5]                                                                                     ; 3       ;
-; MAin[4]                                                                                     ; 3       ;
-; MAin[3]                                                                                     ; 3       ;
-; MAin[2]                                                                                     ; 3       ;
-; always8~5                                                                                   ; 3       ;
-; CMDWR                                                                                       ; 3       ;
-; CmdEnable                                                                                   ; 3       ;
-; FS[0]                                                                                       ; 3       ;
-; always8~4                                                                                   ; 3       ;
-; always8~2                                                                                   ; 3       ;
-; Equal0~0                                                                                    ; 3       ;
-; nRCS~3                                                                                      ; 3       ;
-; n8MEGEN                                                                                     ; 3       ;
-; UFMInitDone~0                                                                               ; 3       ;
-; UFMInitDone                                                                                 ; 3       ;
-; RCKE~reg0                                                                                   ; 3       ;
-; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; 3       ;
-; MAin[8]                                                                                     ; 2       ;
-; CmdSubmitted~0                                                                              ; 2       ;
-; Equal17~0                                                                                   ; 2       ;
-; CmdDRDIn~0                                                                                  ; 2       ;
-; XOR8MEG~0                                                                                   ; 2       ;
-; Equal0~3                                                                                    ; 2       ;
-; Ready~0                                                                                     ; 2       ;
-; Equal26~0                                                                                   ; 2       ;
-; FS[9]                                                                                       ; 2       ;
-; FS[8]                                                                                       ; 2       ;
-; Equal5~1                                                                                    ; 2       ;
-; FS[14]                                                                                      ; 2       ;
-; FS[13]                                                                                      ; 2       ;
-; FS[12]                                                                                      ; 2       ;
-; FS[11]                                                                                      ; 2       ;
-; FS[10]                                                                                      ; 2       ;
-; FS[15]                                                                                      ; 2       ;
-; Equal24~0                                                                                   ; 2       ;
-; FS[2]                                                                                       ; 2       ;
-; FS[1]                                                                                       ; 2       ;
-; UFMOscEN~0                                                                                  ; 2       ;
-; C1Submitted                                                                                 ; 2       ;
-; Equal0~1                                                                                    ; 2       ;
-; always8~0                                                                                   ; 2       ;
-; CmdUFMErase                                                                                 ; 2       ;
-; CmdUFMPrgm                                                                                  ; 2       ;
-; always9~4                                                                                   ; 2       ;
-; PHI2r2                                                                                      ; 2       ;
-; DRDIn~1                                                                                     ; 2       ;
-; CmdSubmitted                                                                                ; 2       ;
-; RASr                                                                                        ; 2       ;
-; RCKEEN                                                                                      ; 2       ;
-; CASr2                                                                                       ; 2       ;
-; nRRAS~0                                                                                     ; 2       ;
-; nRCS~1                                                                                      ; 2       ;
-; nRCS~0                                                                                      ; 2       ;
-; XOR8MEG                                                                                     ; 2       ;
-; RA10~0                                                                                      ; 2       ;
-; nRowColSel~0                                                                                ; 2       ;
-; always9~1                                                                                   ; 2       ;
-; FS[7]                                                                                       ; 2       ;
-; UFMOscEN                                                                                    ; 2       ;
-; UFMErase                                                                                    ; 2       ;
-; UFMProgram                                                                                  ; 2       ;
-; LEDEN                                                                                       ; 2       ;
-; UFMProgram~_wirecell                                                                        ; 1       ;
-; UFMOscEN~_wirecell                                                                          ; 1       ;
-; UFMErase~_wirecell                                                                          ; 1       ;
-; RD[7]~7                                                                                     ; 1       ;
-; RD[6]~6                                                                                     ; 1       ;
-; RD[5]~5                                                                                     ; 1       ;
-; RD[4]~4                                                                                     ; 1       ;
-; RD[3]~3                                                                                     ; 1       ;
-; RD[2]~2                                                                                     ; 1       ;
-; RD[1]~1                                                                                     ; 1       ;
-; RD[0]~0                                                                                     ; 1       ;
-; CROW[1]                                                                                     ; 1       ;
-; CROW[0]                                                                                     ; 1       ;
-; CmdEnable~1                                                                                 ; 1       ;
-; CmdEnable~0                                                                                 ; 1       ;
-; PHI2r                                                                                       ; 1       ;
-; RCKEEN~2                                                                                    ; 1       ;
-; RCKEEN~1                                                                                    ; 1       ;
-; RCKEEN~0                                                                                    ; 1       ;
-; CASr                                                                                        ; 1       ;
-; Equal16~0                                                                                   ; 1       ;
-; n8MEGEN~3                                                                                   ; 1       ;
-; PHI2r3                                                                                      ; 1       ;
-; n8MEGEN~2                                                                                   ; 1       ;
-; n8MEGEN~1                                                                                   ; 1       ;
-; n8MEGEN~0                                                                                   ; 1       ;
-; Cmdn8MEGEN                                                                                  ; 1       ;
-; IS[0]~3                                                                                     ; 1       ;
-; Ready~1                                                                                     ; 1       ;
-; FS[9]~33COUT1_62                                                                            ; 1       ;
-; FS[9]~33                                                                                    ; 1       ;
-; FS[14]~29COUT1_70                                                                           ; 1       ;
-; FS[14]~29                                                                                   ; 1       ;
-; Equal5~0                                                                                    ; 1       ;
-; FS[12]~25COUT1_68                                                                           ; 1       ;
-; FS[12]~25                                                                                   ; 1       ;
-; FS[11]~23COUT1_66                                                                           ; 1       ;
-; FS[11]~23                                                                                   ; 1       ;
-; FS[10]~21COUT1_64                                                                           ; 1       ;
-; FS[10]~21                                                                                   ; 1       ;
-; FS[15]~19COUT1_72                                                                           ; 1       ;
-; FS[15]~19                                                                                   ; 1       ;
-; UFMD[15]~0                                                                                  ; 1       ;
-; FS[2]~17COUT1_52                                                                            ; 1       ;
-; FS[2]~17                                                                                    ; 1       ;
-; FS[1]~15COUT1_50                                                                            ; 1       ;
-; FS[1]~15                                                                                    ; 1       ;
-; WRD[7]                                                                                      ; 1       ;
-; WRD[6]                                                                                      ; 1       ;
-; WRD[5]                                                                                      ; 1       ;
-; WRD[4]                                                                                      ; 1       ;
-; WRD[3]                                                                                      ; 1       ;
-; WRD[2]                                                                                      ; 1       ;
-; WRD[1]                                                                                      ; 1       ;
-; WRD[0]                                                                                      ; 1       ;
-; ADSubmitted                                                                                 ; 1       ;
-; always8~3                                                                                   ; 1       ;
-; Equal0~2                                                                                    ; 1       ;
-; always8~1                                                                                   ; 1       ;
-; Equal1~0                                                                                    ; 1       ;
-; CMDWR~1                                                                                     ; 1       ;
-; Bank[7]                                                                                     ; 1       ;
-; Bank[6]                                                                                     ; 1       ;
-; Bank[5]                                                                                     ; 1       ;
-; CMDWR~0                                                                                     ; 1       ;
-; Bank[2]                                                                                     ; 1       ;
-; Bank[3]                                                                                     ; 1       ;
-; Bank[1]                                                                                     ; 1       ;
-; always9~5                                                                                   ; 1       ;
-; ARCLK~0                                                                                     ; 1       ;
-; CmdDRCLK                                                                                    ; 1       ;
-; CmdDRDIn                                                                                    ; 1       ;
-; nRCAS~1                                                                                     ; 1       ;
-; nRCAS~0                                                                                     ; 1       ;
-; nRWE~0                                                                                      ; 1       ;
-; RASr3                                                                                       ; 1       ;
-; nRCS~4                                                                                      ; 1       ;
-; nRCS~2                                                                                      ; 1       ;
-; nRowColSel~1                                                                                ; 1       ;
-; FS[4]~11COUT1_54                                                                            ; 1       ;
-; FS[4]~11                                                                                    ; 1       ;
-; FS[6]~9COUT1_58                                                                             ; 1       ;
-; FS[6]~9                                                                                     ; 1       ;
-; FS[5]~7COUT1_56                                                                             ; 1       ;
-; FS[5]~7                                                                                     ; 1       ;
-; FS[7]~5COUT1_60                                                                             ; 1       ;
-; FS[7]~5                                                                                     ; 1       ;
-; FS[16]~1COUT1_74                                                                            ; 1       ;
-; FS[16]~1                                                                                    ; 1       ;
-; ARShift                                                                                     ; 1       ;
-; ARCLK                                                                                       ; 1       ;
-; DRShift                                                                                     ; 1       ;
-; DRCLK                                                                                       ; 1       ;
-; DRDIn                                                                                       ; 1       ;
-; comb~2                                                                                      ; 1       ;
-; comb~1                                                                                      ; 1       ;
-; nRCAS~reg0                                                                                  ; 1       ;
-; nRRAS~reg0                                                                                  ; 1       ;
-; nRWE~reg0                                                                                   ; 1       ;
-; nRCS~reg0                                                                                   ; 1       ;
-; RA11                                                                                        ; 1       ;
-; RA10                                                                                        ; 1       ;
-; RA~9                                                                                        ; 1       ;
-; RowA[9]                                                                                     ; 1       ;
-; RA~8                                                                                        ; 1       ;
-; RowA[8]                                                                                     ; 1       ;
-; RA~7                                                                                        ; 1       ;
-; RowA[7]                                                                                     ; 1       ;
-; RA~6                                                                                        ; 1       ;
-; RowA[6]                                                                                     ; 1       ;
-; RA~5                                                                                        ; 1       ;
-; RowA[5]                                                                                     ; 1       ;
-; RA~4                                                                                        ; 1       ;
-; RowA[4]                                                                                     ; 1       ;
-; RA~3                                                                                        ; 1       ;
-; RowA[3]                                                                                     ; 1       ;
-; RA~2                                                                                        ; 1       ;
-; RowA[2]                                                                                     ; 1       ;
-; RA~1                                                                                        ; 1       ;
-; RowA[1]                                                                                     ; 1       ;
-; RA~0                                                                                        ; 1       ;
-; RowA[0]                                                                                     ; 1       ;
-; RBA[1]~reg0                                                                                 ; 1       ;
-; RBA[0]~reg0                                                                                 ; 1       ;
-; comb~0                                                                                      ; 1       ;
-+---------------------------------------------------------------------------------------------+---------+
-
-
-+--------------------------------------------------+
-; Other Routing Usage Summary                      ;
-+-----------------------------+--------------------+
-; Other Routing Resource Type ; Usage              ;
-+-----------------------------+--------------------+
-; C4s                         ; 126 / 784 ( 16 % ) ;
-; Direct links                ; 41 / 888 ( 5 % )   ;
-; Global clocks               ; 4 / 4 ( 100 % )    ;
-; LAB clocks                  ; 16 / 32 ( 50 % )   ;
-; LUT chains                  ; 17 / 216 ( 8 % )   ;
-; Local interconnects         ; 252 / 888 ( 28 % ) ;
-; R4s                         ; 134 / 704 ( 19 % ) ;
-+-----------------------------+--------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements                                                        ;
-+--------------------------------------------+------------------------------+
-; Number of Logic Elements  (Average = 7.30) ; Number of LABs  (Total = 23) ;
-+--------------------------------------------+------------------------------+
-; 1                                          ; 2                            ;
-; 2                                          ; 3                            ;
-; 3                                          ; 0                            ;
-; 4                                          ; 1                            ;
-; 5                                          ; 1                            ;
-; 6                                          ; 0                            ;
-; 7                                          ; 1                            ;
-; 8                                          ; 3                            ;
-; 9                                          ; 0                            ;
-; 10                                         ; 12                           ;
-+--------------------------------------------+------------------------------+
-
-
-+-------------------------------------------------------------------+
-; LAB-wide Signals                                                  ;
-+------------------------------------+------------------------------+
-; LAB-wide Signals  (Average = 1.26) ; Number of LABs  (Total = 23) ;
-+------------------------------------+------------------------------+
-; 1 Clock                            ; 17                           ;
-; 1 Clock enable                     ; 2                            ;
-; 1 Sync. clear                      ; 4                            ;
-; 1 Sync. load                       ; 1                            ;
-; 2 Clocks                           ; 5                            ;
-+------------------------------------+------------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced                                                        ;
-+---------------------------------------------+------------------------------+
-; Number of Signals Sourced  (Average = 7.57) ; Number of LABs  (Total = 23) ;
-+---------------------------------------------+------------------------------+
-; 0                                           ; 0                            ;
-; 1                                           ; 2                            ;
-; 2                                           ; 3                            ;
-; 3                                           ; 0                            ;
-; 4                                           ; 1                            ;
-; 5                                           ; 0                            ;
-; 6                                           ; 0                            ;
-; 7                                           ; 2                            ;
-; 8                                           ; 3                            ;
-; 9                                           ; 0                            ;
-; 10                                          ; 9                            ;
-; 11                                          ; 2                            ;
-; 12                                          ; 1                            ;
-+---------------------------------------------+------------------------------+
-
-
-+--------------------------------------------------------------------------------+
-; LAB Signals Sourced Out                                                        ;
-+-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out  (Average = 5.17) ; Number of LABs  (Total = 23) ;
-+-------------------------------------------------+------------------------------+
-; 0                                               ; 0                            ;
-; 1                                               ; 3                            ;
-; 2                                               ; 2                            ;
-; 3                                               ; 0                            ;
-; 4                                               ; 4                            ;
-; 5                                               ; 3                            ;
-; 6                                               ; 3                            ;
-; 7                                               ; 4                            ;
-; 8                                               ; 2                            ;
-; 9                                               ; 1                            ;
-; 10                                              ; 1                            ;
-+-------------------------------------------------+------------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Distinct Inputs                                                        ;
-+---------------------------------------------+------------------------------+
-; Number of Distinct Inputs  (Average = 9.04) ; Number of LABs  (Total = 23) ;
-+---------------------------------------------+------------------------------+
-; 0                                           ; 0                            ;
-; 1                                           ; 2                            ;
-; 2                                           ; 1                            ;
-; 3                                           ; 3                            ;
-; 4                                           ; 0                            ;
-; 5                                           ; 0                            ;
-; 6                                           ; 1                            ;
-; 7                                           ; 3                            ;
-; 8                                           ; 1                            ;
-; 9                                           ; 2                            ;
-; 10                                          ; 1                            ;
-; 11                                          ; 0                            ;
-; 12                                          ; 1                            ;
-; 13                                          ; 2                            ;
-; 14                                          ; 2                            ;
-; 15                                          ; 1                            ;
-; 16                                          ; 1                            ;
-; 17                                          ; 1                            ;
-; 18                                          ; 1                            ;
-+---------------------------------------------+------------------------------+
-
-
-+-------------------------------------------------------------------------+
-; Fitter Device Options                                                   ;
-+----------------------------------------------+--------------------------+
-; Option                                       ; Setting                  ;
-+----------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
-; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
-; Enable device-wide output enable (DEV_OE)    ; Off                      ;
-; Enable INIT_DONE output                      ; Off                      ;
-; Configuration scheme                         ; Passive Serial           ;
-; Reserve all unused pins                      ; As output driving ground ;
-; Base pin-out file on sameframe device        ; Off                      ;
-+----------------------------------------------+--------------------------+
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary              ;
-+-----------------+----------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-; I/O             ; nCRAS                ; 1.3               ;
-; I/O             ; RCLK                 ; 1.2               ;
-+-----------------+----------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer.
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details              ;
-+-----------------+----------------------+-------------------+
-; Source Register ; Destination Register ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-; nCCAS           ; CBR                  ; 1.303             ;
-; PHI2            ; PHI2r                ; 0.610             ;
-; nCRAS           ; RASr                 ; 0.301             ;
-+-----------------+----------------------+-------------------+
-Note: This table only shows the top 3 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (119006): Selected device EPM240T100C5 for design "RAM2GS"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
-    Info (176445): Device EPM240T100I5 is compatible
-    Info (176445): Device EPM240T100A5 is compatible
-    Info (176445): Device EPM570T100C5 is compatible
-    Info (176445): Device EPM570T100I5 is compatible
-    Info (176445): Device EPM570T100A5 is compatible
-Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 63 total pins
-    Info (169086): Pin LED not assigned to an exact location on the device
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
-    Info (332127): Assuming a default timing requirement
-Info (332111): Found 6 clocks
-    Info (332111):   Period   Clock Name
-    Info (332111): ======== ============
-    Info (332111):    1.000        ARCLK
-    Info (332111):    1.000        DRCLK
-    Info (332111):    1.000        nCCAS
-    Info (332111):    1.000        nCRAS
-    Info (332111):    1.000         PHI2
-    Info (332111):    1.000         RCLK
-Info (186079): Completed User Assigned Global Signals Promotion Operation
-Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12
-Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock
-    Info (186217): Destination "PHI2r" may be non-global or may not use global clock
-Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position
-Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock
-    Info (186217): Destination "comb~0" may be non-global or may not use global clock
-    Info (186217): Destination "RASr" may be non-global or may not use global clock
-Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position
-Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock
-    Info (186217): Destination "CBR" may be non-global or may not use global clock
-    Info (186217): Destination "comb~3" may be non-global or may not use global clock
-    Info (186217): Destination "CASr" may be non-global or may not use global clock
-Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position
-Info (186079): Completed Auto Global Promotion Operation
-Info (176234): Starting register packing
-Info (186391): Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
-Info (186468): Started processing fast register assignments
-Info (186469): Finished processing fast register assignments
-Info (176235): Finished register packing
-Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
-    Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
-        Info (176212): I/O standards used: 3.3-V LVTTL.
-Info (176215): I/O bank details before I/O pin placement
-    Info (176214): Statistics of I/O banks
-        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  0 pins available
-        Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used --  18 pins available
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 18% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.28 seconds.
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
-Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg
-Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 548 megabytes
-    Info: Processing ended: Mon Aug 16 18:40:16 2021
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:03
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg.
-
-
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.fit.smsg b/CPLD-old/MAX/MAXII/output_files/RAM2GS.fit.smsg
deleted file mode 100644
index 6df10d8..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.fit.smsg
+++ /dev/null
@@ -1,4 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176244): Moving registers into LUTs to improve timing and density
-Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.fit.summary b/CPLD-old/MAX/MAXII/output_files/RAM2GS.fit.summary
deleted file mode 100644
index 6659118..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.fit.summary
+++ /dev/null
@@ -1,11 +0,0 @@
-Fitter Status : Successful - Mon Aug 16 18:40:16 2021
-Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-Revision Name : RAM2GS
-Top-level Entity Name : RAM2GS
-Family : MAX II
-Device : EPM240T100C5
-Timing Models : Final
-Total logic elements : 168 / 240 ( 70 % )
-Total pins : 63 / 80 ( 79 % )
-Total virtual pins : 0
-UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.flow.rpt b/CPLD-old/MAX/MAXII/output_files/RAM2GS.flow.rpt
deleted file mode 100644
index cd5d6a1..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.flow.rpt
+++ /dev/null
@@ -1,126 +0,0 @@
-Flow report for RAM2GS
-Mon Aug 16 18:40:19 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------+
-; Flow Summary                                                                ;
-+---------------------------+-------------------------------------------------+
-; Flow Status               ; Successful - Mon Aug 16 18:40:17 2021           ;
-; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name             ; RAM2GS                                          ;
-; Top-level Entity Name     ; RAM2GS                                          ;
-; Family                    ; MAX II                                          ;
-; Device                    ; EPM240T100C5                                    ;
-; Timing Models             ; Final                                           ;
-; Total logic elements      ; 168 / 240 ( 70 % )                              ;
-; Total pins                ; 63 / 80 ( 79 % )                                ;
-; Total virtual pins        ; 0                                               ;
-; UFM blocks                ; 1 / 1 ( 100 % )                                 ;
-+---------------------------+-------------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings                           ;
-+-------------------+---------------------+
-; Option            ; Setting             ;
-+-------------------+---------------------+
-; Start date & time ; 08/16/2021 18:40:12 ;
-; Main task         ; Compilation         ;
-; Revision Name     ; RAM2GS              ;
-+-------------------+---------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                     ;
-+--------------------------------------------+------------------------------+---------------+-------------+------------+
-; Assignment Name                            ; Value                        ; Default Value ; Entity Name ; Section Id ;
-+--------------------------------------------+------------------------------+---------------+-------------+------------+
-; ALLOW_POWER_UP_DONT_CARE                   ; Off                          ; On            ; --          ; --         ;
-; COMPILER_SIGNATURE_ID                      ; 962837114763.162915361100164 ; --            ; --          ; --         ;
-; ENABLE_BUS_HOLD_CIRCUITRY                  ; On                           ; Off           ; --          ; --         ;
-; FITTER_EFFORT                              ; Standard Fit                 ; Auto Fit      ; --          ; --         ;
-; IP_TOOL_NAME                               ; ALTUFM_NONE                  ; --            ; --          ; --         ;
-; IP_TOOL_VERSION                            ; 13.0                         ; --            ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP                     ; 85                           ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP                     ; 0                            ; --            ; --          ; --         ;
-; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers        ; Normal        ; --          ; --         ;
-; OPTIMIZE_MULTI_CORNER_TIMING               ; On                           ; Off           ; --          ; --         ;
-; PLACEMENT_EFFORT_MULTIPLIER                ; 10                           ; 1.0           ; --          ; --         ;
-; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE         ; 12.5 %                       ; 12.5%         ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY                   ; output_files                 ; --            ; --          ; --         ;
-; ROUTER_EFFORT_MULTIPLIER                   ; 10                           ; 1.0           ; --          ; --         ;
-; SAFE_STATE_MACHINE                         ; On                           ; Off           ; --          ; --         ;
-; SYNTH_TIMING_DRIVEN_SYNTHESIS              ; Off                          ; --            ; --          ; --         ;
-+--------------------------------------------+------------------------------+---------------+-------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 421 MB              ; 00:00:01                           ;
-; Fitter                    ; 00:00:03     ; 1.0                     ; 548 MB              ; 00:00:03                           ;
-; Assembler                 ; 00:00:00     ; 1.0                     ; 381 MB              ; 00:00:01                           ;
-; TimeQuest Timing Analyzer ; 00:00:01     ; 1.0                     ; 374 MB              ; 00:00:01                           ;
-; Total                     ; 00:00:05     ; --                      ; --                  ; 00:00:06                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                        ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Analysis & Synthesis      ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; Fitter                    ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; Assembler                 ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; TimeQuest Timing Analyzer ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-+---------------------------+------------------+-----------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
-quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
-quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
-quartus_sta RAM2GS-MAXII -c RAM2GS
-
-
-
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.jdi b/CPLD-old/MAX/MAXII/output_files/RAM2GS.jdi
deleted file mode 100644
index 8f5f174..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-  
-    
-  
-  
-    
-  
-
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.map.rpt b/CPLD-old/MAX/MAXII/output_files/RAM2GS.map.rpt
deleted file mode 100644
index d013013..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.map.rpt
+++ /dev/null
@@ -1,309 +0,0 @@
-Analysis & Synthesis report for RAM2GS
-Mon Aug 16 18:40:12 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. Analysis & Synthesis IP Cores Summary
-  9. General Register Statistics
- 10. Inverted Register Statistics
- 11. Multiplexer Restructuring Statistics (Restructuring Performed)
- 12. Port Connectivity Checks: "UFM:UFM_inst"
- 13. Analysis & Synthesis Messages
- 14. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                  ;
-+-----------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon Aug 16 18:40:12 2021           ;
-; Quartus II 64-Bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name               ; RAM2GS                                          ;
-; Top-level Entity Name       ; RAM2GS                                          ;
-; Family                      ; MAX II                                          ;
-; Total logic elements        ; 177                                             ;
-; Total pins                  ; 63                                              ;
-; Total virtual pins          ; 0                                               ;
-; UFM blocks                  ; 1 / 1 ( 100 % )                                 ;
-+-----------------------------+-------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                        ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                                     ; Setting            ; Default Value      ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                                     ; EPM240T100C5       ;                    ;
-; Top-level entity name                                                      ; RAM2GS             ; RAM2GS             ;
-; Family name                                                                ; MAX II             ; Cyclone IV GX      ;
-; Safe State Machine                                                         ; On                 ; Off                ;
-; Power-Up Don't Care                                                        ; Off                ; On                 ;
-; Use smart compilation                                                      ; Off                ; Off                ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
-; Enable compact report table                                                ; Off                ; Off                ;
-; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
-; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
-; Preserve fewer node names                                                  ; On                 ; On                 ;
-; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
-; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
-; State Machine Processing                                                   ; Auto               ; Auto               ;
-; Extract Verilog State Machines                                             ; On                 ; On                 ;
-; Extract VHDL State Machines                                                ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
-; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
-; Parallel Synthesis                                                         ; On                 ; On                 ;
-; NOT Gate Push-Back                                                         ; On                 ; On                 ;
-; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
-; Remove Duplicate Registers                                                 ; On                 ; On                 ;
-; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
-; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
-; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
-; Optimization Technique                                                     ; Balanced           ; Balanced           ;
-; Carry Chain Length                                                         ; 70                 ; 70                 ;
-; Auto Carry Chains                                                          ; On                 ; On                 ;
-; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
-; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
-; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
-; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
-; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
-; Auto Resource Sharing                                                      ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
-; Report Parameter Settings                                                  ; On                 ; On                 ;
-; Report Source Assignments                                                  ; On                 ; On                 ;
-; Report Connectivity Checks                                                 ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
-; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
-; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
-; HDL message level                                                          ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
-; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
-; Clock MUX Protection                                                       ; On                 ; On                 ;
-; Block Design Naming                                                        ; Auto               ; Auto               ;
-; Synthesis Effort                                                           ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
-; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
-; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
-; Synthesis Seed                                                             ; 1                  ; 1                  ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 12     ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                  ;
-+----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type                   ; File Name with Absolute Path                               ; Library ;
-+----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
-; ../RAM2GS-MAX.v                  ; yes             ; User Verilog HDL File       ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v ;         ;
-; UFM.v                            ; yes             ; User Wizard-Generated File  ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v  ;         ;
-+----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary         ;
-+---------------------------------------------+-------+
-; Resource                                    ; Usage ;
-+---------------------------------------------+-------+
-; Total logic elements                        ; 177   ;
-;     -- Combinational with no register       ; 80    ;
-;     -- Register only                        ; 29    ;
-;     -- Combinational with a register        ; 68    ;
-;                                             ;       ;
-; Logic element usage by number of LUT inputs ;       ;
-;     -- 4 input functions                    ; 58    ;
-;     -- 3 input functions                    ; 40    ;
-;     -- 2 input functions                    ; 41    ;
-;     -- 1 input functions                    ; 8     ;
-;     -- 0 input functions                    ; 1     ;
-;                                             ;       ;
-; Logic elements by mode                      ;       ;
-;     -- normal mode                          ; 161   ;
-;     -- arithmetic mode                      ; 16    ;
-;     -- qfbk mode                            ; 0     ;
-;     -- register cascade mode                ; 0     ;
-;     -- synchronous clear/load mode          ; 9     ;
-;     -- asynchronous clear/load mode         ; 0     ;
-;                                             ;       ;
-; Total registers                             ; 97    ;
-; Total logic cells in carry chains           ; 17    ;
-; I/O pins                                    ; 63    ;
-; UFM blocks                                  ; 1     ;
-; Maximum fan-out node                        ; RCLK  ;
-; Maximum fan-out                             ; 55    ;
-; Total fan-out                               ; 643   ;
-; Average fan-out                             ; 2.67  ;
-+---------------------------------------------+-------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                    ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; |RAM2GS                                                   ; 177 (177)   ; 97           ; 1          ; 63   ; 0            ; 80 (80)      ; 29 (29)           ; 68 (68)          ; 17 (17)         ; 0 (0)      ; |RAM2GS                                                                ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; work         ;
-;       |UFM_altufm_none_imr:UFM_altufm_none_imr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis IP Cores Summary                                                                                                            ;
-+--------+--------------+---------+--------------+--------------+----------------------+-----------------------------------------------------------+
-; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File                                           ;
-+--------+--------------+---------+--------------+--------------+----------------------+-----------------------------------------------------------+
-; Altera ; ALTUFM_NONE  ; 13.0    ; N/A          ; N/A          ; |RAM2GS|UFM:UFM_inst ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v ;
-+--------+--------------+---------+--------------+--------------+----------------------+-----------------------------------------------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 97    ;
-; Number of registers using Synchronous Clear  ; 6     ;
-; Number of registers using Synchronous Load   ; 3     ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 10    ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+--------------------------------------------------+
-; Inverted Register Statistics                     ;
-+----------------------------------------+---------+
-; Inverted Register                      ; Fan out ;
-+----------------------------------------+---------+
-; nRCS~reg0                              ; 1       ;
-; nRWE~reg0                              ; 1       ;
-; nRRAS~reg0                             ; 1       ;
-; nRCAS~reg0                             ; 1       ;
-; Total number of inverted registers = 4 ;         ;
-+----------------------------------------+---------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|S[0]               ;
-; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|ADSubmitted        ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "UFM:UFM_inst"                                                                          ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-; Port    ; Type   ; Severity ; Details                                                                             ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-; ardin   ; Input  ; Info     ; Stuck at GND                                                                        ;
-; busy    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; osc     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; rtpbusy ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 64-Bit Analysis & Synthesis
-    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Mon Aug 16 18:40:11 2021
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (12021): Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v
-    Info (12023): Found entity 1: RAM2GS
-Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
-    Info (12023): Found entity 1: UFM_altufm_none_imr
-    Info (12023): Found entity 2: UFM
-Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
-Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2)
-Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18)
-Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4)
-Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
-Info (12128): Elaborating entity "UFM_altufm_none_imr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component"
-Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/RAM2GS-MAX.mif -- setting all initial values to 0
-Warning (18029): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated
-Warning (18029): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated
-Warning (18029): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated
-Warning (18029): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated
-Warning (18029): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated
-Warning (18029): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated
-Warning (18029): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated
-Warning (18029): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated
-Info (21057): Implemented 241 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 25 input pins
-    Info (21059): Implemented 30 output pins
-    Info (21060): Implemented 8 bidirectional pins
-    Info (21061): Implemented 177 logic cells
-    Info (21070): Implemented 1 User Flash Memory blocks
-Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg
-Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings
-    Info: Peak virtual memory: 421 megabytes
-    Info: Processing ended: Mon Aug 16 18:40:12 2021
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg.
-
-
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.map.smsg b/CPLD-old/MAX/MAXII/output_files/RAM2GS.map.smsg
deleted file mode 100644
index a8e8eb9..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.map.smsg
+++ /dev/null
@@ -1,3 +0,0 @@
-Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(56): extended using "x" or "z"
-Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword
-Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.map.summary b/CPLD-old/MAX/MAXII/output_files/RAM2GS.map.summary
deleted file mode 100644
index 4c4a5bb..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.map.summary
+++ /dev/null
@@ -1,9 +0,0 @@
-Analysis & Synthesis Status : Successful - Mon Aug 16 18:40:12 2021
-Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-Revision Name : RAM2GS
-Top-level Entity Name : RAM2GS
-Family : MAX II
-Total logic elements : 177
-Total pins : 63
-Total virtual pins : 0
-UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.pin b/CPLD-old/MAX/MAXII/output_files/RAM2GS.pin
deleted file mode 100644
index 4acd586..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.pin
+++ /dev/null
@@ -1,164 +0,0 @@
- -- Copyright (C) 1991-2013 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Altera Program License 
- -- Subscription Agreement, Altera MegaCore Function License 
- -- Agreement, or other applicable license agreement, including, 
- -- without limitation, that your use is for the sole purpose of 
- -- programming logic devices manufactured by Altera and sold by 
- -- Altera or its authorized distributors.  Please refer to the 
- -- applicable agreement for further details.
- -- 
- -- This is a Quartus II output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus II input file. This file cannot be used
- -- to make Quartus II pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus II help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (2.5V/3.3V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --					Bank 1:		3.3V
- --					Bank 2:		3.3V
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --					It can also be used to report unused dedicated pins. The connection
- --					on the board for unused dedicated pins depends on whether this will
- --					be used in a future design. One example is device migration. When
- --					using device migration, refer to the device pin-tables. If it is a
- --					GND pin in the pin table or if it will not be used in a future design
- --					for another purpose the it MUST be connected to GND. If it is an unused
- --					dedicated pin, then it can be connected to a valid signal on the board
- --					(low, high, or toggling) if that signal is required for a different
- --					revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --					This pin should be connected to GND. It may also be connected  to a
- --					valid signal  on the board  (low, high, or toggling)  if that signal
- --					is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --           	    or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-CHIP  "RAM2GS"  ASSIGNED TO AN: EPM240T100C5
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND*                         : 1         :        :                   :         : 2         :                
-RDQMH                        : 2         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRCS                         : 3         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRCAS                        : 4         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RBA[0]                       : 5         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRRAS                        : 6         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[11]                       : 7         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RCKE                         : 8         : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
-GNDIO                        : 10        : gnd    :                   :         :           :                
-GNDINT                       : 11        : gnd    :                   :         :           :                
-RCLK                         : 12        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-VCCINT                       : 13        : power  :                   : 2.5V/3.3V :           :                
-RBA[1]                       : 14        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[9]                        : 15        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[10]                       : 16        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[8]                        : 17        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[0]                        : 18        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[7]                        : 19        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[1]                        : 20        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[6]                        : 21        : output : 3.3-V LVCMOS      :         : 1         : Y              
-TMS                          : 22        : input  :                   :         : 1         :                
-TDI                          : 23        : input  :                   :         : 1         :                
-TCK                          : 24        : input  :                   :         : 1         :                
-TDO                          : 25        : output :                   :         : 1         :                
-RA[4]                        : 26        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[3]                        : 27        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[5]                      : 28        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[5]                        : 29        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[2]                        : 30        : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
-GNDIO                        : 32        : gnd    :                   :         :           :                
-Dout[0]                      : 33        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[6]                      : 34        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Din[2]                       : 35        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[1]                       : 36        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[3]                       : 37        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[5]                       : 38        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[4]                       : 39        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[7]                       : 40        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[6]                       : 41        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[0]                       : 42        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[7]                      : 43        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[4]                      : 44        : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 45        : power  :                   : 3.3V    : 1         :                
-GNDIO                        : 46        : gnd    :                   :         :           :                
-Dout[3]                      : 47        : output : 3.3-V LVCMOS      :         : 1         : Y              
-nFWE                         : 48        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[0]                      : 49        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[2]                      : 50        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[1]                      : 51        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-PHI2                         : 52        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-nCCAS                        : 53        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-CROW[0]                      : 54        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-CROW[1]                      : 55        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-Dout[2]                      : 56        : output : 3.3-V LVCMOS      :         : 2         : Y              
-Dout[1]                      : 57        : output : 3.3-V LVCMOS      :         : 2         : Y              
-GND*                         : 58        :        :                   :         : 2         :                
-VCCIO2                       : 59        : power  :                   : 3.3V    : 2         :                
-GNDIO                        : 60        : gnd    :                   :         :           :                
-GND*                         : 61        :        :                   :         : 2         :                
-GND*                         : 62        :        :                   :         : 2         :                
-VCCINT                       : 63        : power  :                   : 2.5V/3.3V :           :                
-GND*                         : 64        :        :                   :         : 2         :                
-GNDINT                       : 65        : gnd    :                   :         :           :                
-LED                          : 66        : output : 3.3-V LVTTL       :         : 2         : N              
-nCRAS                        : 67        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[7]                      : 68        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[5]                      : 69        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[4]                      : 70        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[3]                      : 71        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[6]                      : 72        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[8]                      : 73        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[9]                      : 74        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-GND*                         : 75        :        :                   :         : 2         :                
-GND*                         : 76        :        :                   :         : 2         :                
-GND*                         : 77        :        :                   :         : 2         :                
-GND*                         : 78        :        :                   :         : 2         :                
-GNDIO                        : 79        : gnd    :                   :         :           :                
-VCCIO2                       : 80        : power  :                   : 3.3V    : 2         :                
-GND*                         : 81        :        :                   :         : 2         :                
-GND*                         : 82        :        :                   :         : 2         :                
-GND*                         : 83        :        :                   :         : 2         :                
-GND*                         : 84        :        :                   :         : 2         :                
-GND*                         : 85        :        :                   :         : 2         :                
-GND*                         : 86        :        :                   :         : 2         :                
-GND*                         : 87        :        :                   :         : 2         :                
-GND*                         : 88        :        :                   :         : 2         :                
-RD[2]                        : 89        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[1]                        : 90        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[5]                        : 91        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[4]                        : 92        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-GNDIO                        : 93        : gnd    :                   :         :           :                
-VCCIO2                       : 94        : power  :                   : 3.3V    : 2         :                
-RD[6]                        : 95        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[0]                        : 96        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[7]                        : 97        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RDQML                        : 98        : output : 3.3-V LVCMOS      :         : 2         : Y              
-RD[3]                        : 99        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-nRWE                         : 100       : output : 3.3-V LVCMOS      :         : 2         : Y              
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.pof b/CPLD-old/MAX/MAXII/output_files/RAM2GS.pof
deleted file mode 100644
index f288ab0dfb2c6e99db0de99f100b49770bc48f9c..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.sta.rpt b/CPLD-old/MAX/MAXII/output_files/RAM2GS.sta.rpt
deleted file mode 100644
index b9aa2bf..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.sta.rpt
+++ /dev/null
@@ -1,1576 +0,0 @@
-TimeQuest Timing Analyzer report for RAM2GS
-Mon Aug 16 18:40:19 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. Clocks
-  5. Fmax Summary
-  6. Setup Summary
-  7. Hold Summary
-  8. Recovery Summary
-  9. Removal Summary
- 10. Minimum Pulse Width Summary
- 11. Setup: 'ARCLK'
- 12. Setup: 'DRCLK'
- 13. Setup: 'RCLK'
- 14. Setup: 'PHI2'
- 15. Setup: 'nCRAS'
- 16. Hold: 'ARCLK'
- 17. Hold: 'DRCLK'
- 18. Hold: 'nCRAS'
- 19. Hold: 'PHI2'
- 20. Hold: 'RCLK'
- 21. Minimum Pulse Width: 'ARCLK'
- 22. Minimum Pulse Width: 'DRCLK'
- 23. Minimum Pulse Width: 'PHI2'
- 24. Minimum Pulse Width: 'RCLK'
- 25. Minimum Pulse Width: 'nCCAS'
- 26. Minimum Pulse Width: 'nCRAS'
- 27. Setup Times
- 28. Hold Times
- 29. Clock to Output Times
- 30. Minimum Clock to Output Times
- 31. Propagation Delay
- 32. Minimum Propagation Delay
- 33. Output Enable Times
- 34. Minimum Output Enable Times
- 35. Output Disable Times
- 36. Minimum Output Disable Times
- 37. Setup Transfers
- 38. Hold Transfers
- 39. Report TCCS
- 40. Report RSKM
- 41. Unconstrained Paths
- 42. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+----------------------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                                      ;
-+--------------------+-------------------------------------------------------------------+
-; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
-; Revision Name      ; RAM2GS                                                            ;
-; Device Family      ; MAX II                                                            ;
-; Device Name        ; EPM240T100C5                                                      ;
-; Timing Models      ; Final                                                             ;
-; Delay Model        ; Slow Model                                                        ;
-; Rise/Fall Delays   ; Unavailable                                                       ;
-+--------------------+-------------------------------------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 12     ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                            ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets   ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; ARCLK      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ARCLK } ;
-; DRCLK      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DRCLK } ;
-; nCCAS      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCCAS } ;
-; nCRAS      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCRAS } ;
-; PHI2       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { PHI2 }  ;
-; RCLK       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { RCLK }  ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-
-
-+--------------------------------------------------+
-; Fmax Summary                                     ;
-+------------+-----------------+------------+------+
-; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+------------+------+
-; 10.0 MHz   ; 10.0 MHz        ; ARCLK      ;      ;
-; 10.0 MHz   ; 10.0 MHz        ; DRCLK      ;      ;
-; 57.01 MHz  ; 57.01 MHz       ; PHI2       ;      ;
-; 121.57 MHz ; 121.57 MHz      ; RCLK       ;      ;
-+------------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+---------------------------------+
-; Setup Summary                   ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; ARCLK ; -99.000 ; -99.000       ;
-; DRCLK ; -99.000 ; -99.000       ;
-; RCLK  ; -8.339  ; -245.761      ;
-; PHI2  ; -8.271  ; -88.383       ;
-; nCRAS ; -0.317  ; -2.784        ;
-+-------+---------+---------------+
-
-
-+---------------------------------+
-; Hold Summary                    ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; ARCLK ; -16.858 ; -16.858       ;
-; DRCLK ; -16.363 ; -16.363       ;
-; nCRAS ; -0.103  ; -0.195        ;
-; PHI2  ; -0.060  ; -0.060        ;
-; RCLK  ; 1.192   ; 0.000         ;
-+-------+---------+---------------+
-
-
---------------------
-; Recovery Summary ;
---------------------
-No paths to report.
-
-
--------------------
-; Removal Summary ;
--------------------
-No paths to report.
-
-
-+---------------------------------+
-; Minimum Pulse Width Summary     ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; ARCLK ; -29.500 ; -59.000       ;
-; DRCLK ; -29.500 ; -59.000       ;
-; PHI2  ; -2.289  ; -2.289        ;
-; RCLK  ; -2.289  ; -2.289        ;
-; nCCAS ; -2.289  ; -2.289        ;
-; nCRAS ; -2.289  ; -2.289        ;
-+-------+---------+---------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'ARCLK'                                                                                                                                                                                                                                                                                    ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -99.000 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 1.000        ; 0.000      ; 80.000     ;
-; -22.142 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 1.000        ; -1.613     ; 1.529      ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'DRCLK'                                                                                                                                                                                                                                                            ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -99.000 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 1.000        ; 0.000      ; 80.000     ;
-; -22.699 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 1.000        ; -1.595     ; 2.104      ;
-; -22.637 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 1.000        ; -1.595     ; 2.042      ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'RCLK'                                                                                                                                                                            ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node                                                                                   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; -8.339 ; CmdSubmitted                                                                                ; n8MEGEN     ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 5.262      ;
-; -7.863 ; CmdSubmitted                                                                                ; DRCLK       ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 4.786      ;
-; -7.540 ; FWEr                                                                                        ; nRowColSel  ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 5.138      ;
-; -7.536 ; FWEr                                                                                        ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 5.134      ;
-; -7.431 ; CmdSubmitted                                                                                ; DRDIn       ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 4.354      ;
-; -7.397 ; Cmdn8MEGEN                                                                                  ; n8MEGEN     ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 4.320      ;
-; -7.226 ; FS[12]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.893      ;
-; -7.147 ; IS[2]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.814      ;
-; -7.078 ; FS[11]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.745      ;
-; -7.033 ; CBR                                                                                         ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 4.631      ;
-; -7.000 ; CBR                                                                                         ; nRowColSel  ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 4.598      ;
-; -6.983 ; S[1]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.650      ;
-; -6.966 ; IS[3]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.633      ;
-; -6.929 ; FWEr                                                                                        ; nRWE~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 4.527      ;
-; -6.898 ; FS[13]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.565      ;
-; -6.794 ; InitReady                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.461      ;
-; -6.759 ; FS[12]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.426      ;
-; -6.748 ; FWEr                                                                                        ; nRCS~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 4.346      ;
-; -6.664 ; FS[16]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.331      ;
-; -6.657 ; FS[16]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.324      ;
-; -6.657 ; CBR                                                                                         ; RCKEEN      ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 4.255      ;
-; -6.654 ; FS[16]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.321      ;
-; -6.621 ; IS[1]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.288      ;
-; -6.620 ; CmdDRDIn                                                                                    ; DRDIn       ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 3.543      ;
-; -6.611 ; FS[11]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.278      ;
-; -6.559 ; FS[17]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.226      ;
-; -6.552 ; FS[17]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.219      ;
-; -6.549 ; FS[17]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.216      ;
-; -6.541 ; FS[10]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.208      ;
-; -6.499 ; RASr2                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.166      ;
-; -6.451 ; FS[7]                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.118      ;
-; -6.444 ; FS[7]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.111      ;
-; -6.441 ; FS[7]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.108      ;
-; -6.431 ; FS[13]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.098      ;
-; -6.416 ; IS[0]                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.083      ;
-; -6.389 ; CBR                                                                                         ; nRWE~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 3.987      ;
-; -6.373 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; n8MEGEN     ; DRCLK        ; RCLK        ; 1.000        ; 1.595      ; 8.635      ;
-; -6.359 ; FS[16]                                                                                      ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.026      ;
-; -6.351 ; FS[12]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 7.018      ;
-; -6.312 ; CmdDRCLK                                                                                    ; DRCLK       ; PHI2         ; RCLK        ; 0.500        ; -3.244     ; 3.235      ;
-; -6.282 ; S[0]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.949      ;
-; -6.257 ; FWEr                                                                                        ; RCKEEN      ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 3.855      ;
-; -6.254 ; FS[17]                                                                                      ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.921      ;
-; -6.250 ; CBR                                                                                         ; nRCS~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -2.569     ; 3.848      ;
-; -6.203 ; FS[11]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.870      ;
-; -6.195 ; FS[16]                                                                                      ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.862      ;
-; -6.159 ; FS[16]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.826      ;
-; -6.146 ; FS[7]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.813      ;
-; -6.099 ; RCKE~reg0                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.766      ;
-; -6.090 ; FS[17]                                                                                      ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.757      ;
-; -6.074 ; FS[10]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.741      ;
-; -6.054 ; FS[17]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.721      ;
-; -6.023 ; FS[13]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.690      ;
-; -5.982 ; FS[7]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.649      ;
-; -5.946 ; FS[7]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.613      ;
-; -5.885 ; FS[2]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.552      ;
-; -5.827 ; Ready                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.494      ;
-; -5.783 ; S[1]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.450      ;
-; -5.753 ; FS[0]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.420      ;
-; -5.751 ; RASr2                                                                                       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.418      ;
-; -5.703 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; LEDEN       ; DRCLK        ; RCLK        ; 1.000        ; 1.595      ; 7.965      ;
-; -5.684 ; FS[2]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.351      ;
-; -5.666 ; FS[10]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.333      ;
-; -5.664 ; S[0]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.331      ;
-; -5.663 ; FS[17]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.330      ;
-; -5.657 ; FS[6]                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.324      ;
-; -5.655 ; FS[4]                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.322      ;
-; -5.650 ; FS[6]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.317      ;
-; -5.648 ; FS[4]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.315      ;
-; -5.647 ; FS[6]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.314      ;
-; -5.645 ; FS[4]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.312      ;
-; -5.626 ; FS[6]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.293      ;
-; -5.604 ; FS[14]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.271      ;
-; -5.594 ; InitReady                                                                                   ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.261      ;
-; -5.578 ; Ready                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.245      ;
-; -5.571 ; Ready                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.238      ;
-; -5.568 ; Ready                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.235      ;
-; -5.558 ; FS[3]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.225      ;
-; -5.555 ; UFMInitDone                                                                                 ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.222      ;
-; -5.552 ; FS[0]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.219      ;
-; -5.548 ; UFMInitDone                                                                                 ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.215      ;
-; -5.545 ; UFMInitDone                                                                                 ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.212      ;
-; -5.544 ; S[0]                                                                                        ; RCKEEN      ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.211      ;
-; -5.535 ; FS[16]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.202      ;
-; -5.451 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; UFMD[15]    ; DRCLK        ; RCLK        ; 1.000        ; 1.595      ; 7.713      ;
-; -5.438 ; FS[16]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.105      ;
-; -5.430 ; FS[17]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.097      ;
-; -5.398 ; Ready                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.065      ;
-; -5.395 ; Ready                                                                                       ; DRDIn       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.062      ;
-; -5.386 ; RASr2                                                                                       ; RCKEEN      ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.053      ;
-; -5.363 ; FS[5]                                                                                       ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.030      ;
-; -5.357 ; FS[3]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.024      ;
-; -5.356 ; FS[5]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.023      ;
-; -5.353 ; FS[5]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.020      ;
-; -5.345 ; FS[16]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.012      ;
-; -5.333 ; FS[17]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 6.000      ;
-; -5.332 ; FS[5]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.999      ;
-; -5.329 ; FS[4]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.996      ;
-; -5.329 ; FS[6]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.996      ;
-; -5.325 ; FS[15]                                                                                      ; InitReady   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 5.992      ;
-+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Setup: 'PHI2'                                                                                             ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -8.271 ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.438      ;
-; -8.271 ; Bank[3]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.438      ;
-; -8.271 ; Bank[3]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.438      ;
-; -8.271 ; Bank[3]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.438      ;
-; -8.251 ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.418      ;
-; -8.115 ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.282      ;
-; -8.115 ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.282      ;
-; -8.115 ; Bank[2]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.282      ;
-; -8.115 ; Bank[2]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.282      ;
-; -8.095 ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 8.262      ;
-; -7.799 ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.966      ;
-; -7.799 ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.966      ;
-; -7.643 ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.810      ;
-; -7.643 ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.810      ;
-; -7.577 ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.744      ;
-; -7.577 ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.744      ;
-; -7.577 ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.744      ;
-; -7.577 ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.744      ;
-; -7.557 ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.724      ;
-; -7.105 ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.272      ;
-; -7.105 ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.272      ;
-; -7.088 ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.255      ;
-; -7.088 ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.255      ;
-; -7.075 ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.242      ;
-; -7.075 ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.242      ;
-; -7.075 ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.242      ;
-; -7.075 ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.242      ;
-; -7.055 ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.222      ;
-; -7.054 ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.221      ;
-; -7.054 ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.221      ;
-; -7.054 ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.221      ;
-; -7.054 ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.221      ;
-; -7.034 ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.201      ;
-; -6.998 ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.165      ;
-; -6.932 ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.099      ;
-; -6.932 ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.099      ;
-; -6.900 ; Bank[5]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.067      ;
-; -6.900 ; Bank[5]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.067      ;
-; -6.900 ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.067      ;
-; -6.900 ; Bank[5]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.067      ;
-; -6.880 ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.047      ;
-; -6.872 ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.039      ;
-; -6.842 ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 7.009      ;
-; -6.716 ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.883      ;
-; -6.603 ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.770      ;
-; -6.603 ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.770      ;
-; -6.582 ; Bank[7]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.749      ;
-; -6.582 ; Bank[7]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.749      ;
-; -6.428 ; Bank[5]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.595      ;
-; -6.428 ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.595      ;
-; -6.394 ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.561      ;
-; -6.394 ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.561      ;
-; -6.362 ; Bank[6]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.529      ;
-; -6.362 ; Bank[6]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.529      ;
-; -6.362 ; Bank[6]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.529      ;
-; -6.362 ; Bank[6]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.529      ;
-; -6.342 ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.509      ;
-; -6.304 ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.471      ;
-; -6.178 ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.345      ;
-; -5.892 ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.059      ;
-; -5.892 ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.059      ;
-; -5.890 ; Bank[6]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.057      ;
-; -5.890 ; Bank[6]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.057      ;
-; -5.871 ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.038      ;
-; -5.871 ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.038      ;
-; -5.847 ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.014      ;
-; -5.847 ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.014      ;
-; -5.847 ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.014      ;
-; -5.847 ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.014      ;
-; -5.827 ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.994      ;
-; -5.802 ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.969      ;
-; -5.781 ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.948      ;
-; -5.717 ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.884      ;
-; -5.717 ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.884      ;
-; -5.676 ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.843      ;
-; -5.655 ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.822      ;
-; -5.627 ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.794      ;
-; -5.501 ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.668      ;
-; -5.375 ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.542      ;
-; -5.375 ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.542      ;
-; -5.179 ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.346      ;
-; -5.179 ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.346      ;
-; -5.089 ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.256      ;
-; -4.963 ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 5.130      ;
-; -4.664 ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 4.831      ;
-; -4.664 ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 4.831      ;
-; -4.574 ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 4.741      ;
-; -4.448 ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 4.615      ;
-; -4.234 ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.901      ;
-; -4.234 ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.901      ;
-; -3.754 ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.421      ;
-; -3.695 ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.362      ;
-; -3.674 ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.341      ;
-; -3.674 ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.341      ;
-; -3.674 ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.341      ;
-; -3.674 ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 4.341      ;
-; -3.404 ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 3.571      ;
-; -3.307 ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 3.974      ;
-; -3.297 ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 3.964      ;
-; -2.824 ; UFMOscEN    ; UFMOscEN     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 3.491      ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Setup: 'nCRAS'                                                                                         ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.317 ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.053      ;
-; -0.311 ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.047      ;
-; -0.310 ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.046      ;
-; -0.277 ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.013      ;
-; -0.276 ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.012      ;
-; -0.275 ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.011      ;
-; -0.267 ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 3.003      ;
-; -0.253 ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 2.989      ;
-; -0.252 ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 2.988      ;
-; -0.246 ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 2.982      ;
-; 0.038  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.500        ; 5.917      ; 6.046      ;
-; 0.079  ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 2.657      ;
-; 0.538  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 1.000        ; 5.917      ; 6.046      ;
-; 0.549  ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; 0.500        ; 2.569      ; 2.187      ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'ARCLK'                                                                                                                                                                                                                                                                                     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.858 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 0.000        ; -1.613     ; 1.529      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'DRCLK'                                                                                                                                                                                                                                                             ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.363 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -1.595     ; 2.042      ;
-; -16.301 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -1.595     ; 2.104      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Hold: 'nCRAS'                                                                                          ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.103 ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 2.187      ;
-; -0.092 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.000        ; 5.917      ; 6.046      ;
-; 0.367  ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 2.657      ;
-; 0.408  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; -0.500       ; 5.917      ; 6.046      ;
-; 0.692  ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 2.982      ;
-; 0.698  ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 2.988      ;
-; 0.699  ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 2.989      ;
-; 0.713  ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.003      ;
-; 0.721  ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.011      ;
-; 0.722  ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.012      ;
-; 0.723  ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.013      ;
-; 0.756  ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.046      ;
-; 0.757  ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.047      ;
-; 0.763  ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; -0.500       ; 2.569      ; 3.053      ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Hold: 'PHI2'                                                                                              ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -0.060 ; Ready       ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 3.244      ; 3.405      ;
-; 0.172  ; n8MEGEN     ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; -0.500       ; 3.244      ; 3.137      ;
-; 0.206  ; n8MEGEN     ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 3.244      ; 3.671      ;
-; 2.578  ; XOR8MEG     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.799      ;
-; 2.676  ; C1Submitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 2.897      ;
-; 3.054  ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.275      ;
-; 3.270  ; UFMOscEN    ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.491      ;
-; 3.565  ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.286      ;
-; 3.566  ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.287      ;
-; 3.743  ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.964      ;
-; 3.753  ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 3.974      ;
-; 3.850  ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.571      ;
-; 4.080  ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.801      ;
-; 4.081  ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 3.802      ;
-; 4.120  ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.341      ;
-; 4.120  ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.341      ;
-; 4.120  ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.341      ;
-; 4.120  ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.341      ;
-; 4.141  ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.362      ;
-; 4.200  ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.421      ;
-; 4.618  ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.339      ;
-; 4.619  ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.340      ;
-; 4.680  ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.901      ;
-; 4.680  ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 4.901      ;
-; 4.772  ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.493      ;
-; 4.773  ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.494      ;
-; 4.774  ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.495      ;
-; 4.793  ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.514      ;
-; 4.794  ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.515      ;
-; 4.894  ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.615      ;
-; 5.025  ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 4.746      ;
-; 5.289  ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.010      ;
-; 5.295  ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.016      ;
-; 5.296  ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.017      ;
-; 5.409  ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.130      ;
-; 5.540  ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.261      ;
-; 5.821  ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.542      ;
-; 5.821  ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.542      ;
-; 5.827  ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.548      ;
-; 5.833  ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.554      ;
-; 5.834  ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.555      ;
-; 5.947  ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.668      ;
-; 5.981  ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.702      ;
-; 5.989  ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.710      ;
-; 5.990  ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.711      ;
-; 6.002  ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.723      ;
-; 6.078  ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.799      ;
-; 6.101  ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.822      ;
-; 6.122  ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.843      ;
-; 6.232  ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.953      ;
-; 6.253  ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 5.974      ;
-; 6.293  ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.014      ;
-; 6.293  ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.014      ;
-; 6.293  ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.014      ;
-; 6.293  ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.014      ;
-; 6.336  ; Bank[6]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.057      ;
-; 6.336  ; Bank[6]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.057      ;
-; 6.504  ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.225      ;
-; 6.624  ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.345      ;
-; 6.755  ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.476      ;
-; 6.808  ; Bank[6]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.529      ;
-; 6.808  ; Bank[6]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.529      ;
-; 6.808  ; Bank[6]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.529      ;
-; 6.808  ; Bank[6]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.529      ;
-; 6.874  ; Bank[5]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.595      ;
-; 6.874  ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.595      ;
-; 7.028  ; Bank[7]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.749      ;
-; 7.028  ; Bank[7]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.749      ;
-; 7.042  ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.763      ;
-; 7.049  ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.770      ;
-; 7.049  ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.770      ;
-; 7.162  ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.883      ;
-; 7.198  ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.919      ;
-; 7.293  ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.014      ;
-; 7.318  ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.039      ;
-; 7.346  ; Bank[5]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.067      ;
-; 7.346  ; Bank[5]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.067      ;
-; 7.346  ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.067      ;
-; 7.346  ; Bank[5]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.067      ;
-; 7.449  ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.170      ;
-; 7.500  ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.221      ;
-; 7.500  ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.221      ;
-; 7.500  ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.221      ;
-; 7.500  ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.221      ;
-; 7.521  ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.242      ;
-; 7.521  ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.242      ;
-; 7.521  ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.242      ;
-; 7.521  ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.242      ;
-; 7.551  ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.272      ;
-; 7.551  ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.272      ;
-; 8.023  ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.744      ;
-; 8.023  ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.744      ;
-; 8.023  ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.744      ;
-; 8.023  ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.744      ;
-; 8.089  ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.810      ;
-; 8.089  ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.810      ;
-; 8.245  ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.966      ;
-; 8.245  ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 7.966      ;
-; 8.561  ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.282      ;
-; 8.561  ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 8.282      ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Hold: 'RCLK'                                                                                            ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; 1.192 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; 0.000        ; 3.348      ; 4.761      ;
-; 1.245 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; 0.000        ; 3.348      ; 4.814      ;
-; 1.338 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; 0.000        ; 3.348      ; 4.907      ;
-; 1.659 ; FS[17]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.880      ;
-; 1.692 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; -0.500       ; 3.348      ; 4.761      ;
-; 1.693 ; FS[0]       ; FS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.914      ;
-; 1.703 ; IS[1]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.924      ;
-; 1.704 ; S[0]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.925      ;
-; 1.706 ; S[0]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 1.927      ;
-; 1.745 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; -0.500       ; 3.348      ; 4.814      ;
-; 1.809 ; PHI2r2      ; PHI2r3      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.030      ;
-; 1.829 ; CASr2       ; CASr3       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.050      ;
-; 1.838 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; -0.500       ; 3.348      ; 4.907      ;
-; 1.952 ; IS[3]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.173      ;
-; 1.961 ; S[1]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.182      ;
-; 1.966 ; S[1]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.187      ;
-; 2.108 ; FS[6]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.329      ;
-; 2.116 ; FS[9]       ; FS[9]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.337      ;
-; 2.117 ; FS[16]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
-; 2.117 ; UFMInitDone ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.338      ;
-; 2.124 ; RASr2       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.345      ;
-; 2.126 ; UFMD[15]    ; UFMD[15]    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.347      ;
-; 2.143 ; FS[8]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.364      ;
-; 2.144 ; FS[10]      ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.365      ;
-; 2.144 ; FS[11]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.365      ;
-; 2.145 ; InitReady   ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.366      ;
-; 2.148 ; IS[0]       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.369      ;
-; 2.151 ; CASr2       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.372      ;
-; 2.160 ; IS[2]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.381      ;
-; 2.164 ; FS[0]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.385      ;
-; 2.215 ; RASr3       ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.436      ;
-; 2.230 ; LEDEN       ; LEDEN       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.451      ;
-; 2.230 ; FS[7]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.451      ;
-; 2.239 ; FS[5]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
-; 2.239 ; FS[4]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
-; 2.239 ; FS[15]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
-; 2.239 ; FS[14]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.460      ;
-; 2.241 ; FS[12]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.462      ;
-; 2.242 ; FS[2]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.463      ;
-; 2.250 ; FS[3]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.471      ;
-; 2.250 ; FS[13]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.471      ;
-; 2.267 ; Ready       ; Ready       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.488      ;
-; 2.270 ; UFMProgram  ; UFMProgram  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.491      ;
-; 2.271 ; UFMErase    ; UFMErase    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.492      ;
-; 2.282 ; IS[1]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.503      ;
-; 2.332 ; CASr2       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.553      ;
-; 2.385 ; RASr        ; RASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.606      ;
-; 2.395 ; IS[0]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.616      ;
-; 2.414 ; PHI2r       ; PHI2r2      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.635      ;
-; 2.596 ; RASr2       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.817      ;
-; 2.605 ; FS[1]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.826      ;
-; 2.647 ; RASr        ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.868      ;
-; 2.674 ; PHI2r2      ; DRDIn       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.895      ;
-; 2.689 ; S[0]        ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.910      ;
-; 2.704 ; IS[0]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.925      ;
-; 2.741 ; Ready       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.962      ;
-; 2.744 ; Ready       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.965      ;
-; 2.748 ; Ready       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 2.969      ;
-; 2.797 ; IS[3]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.018      ;
-; 2.799 ; RASr2       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.020      ;
-; 2.825 ; RASr2       ; RASr3       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.046      ;
-; 2.939 ; CASr2       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.160      ;
-; 2.940 ; FS[6]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.161      ;
-; 2.948 ; FS[9]       ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.169      ;
-; 2.949 ; FS[16]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.170      ;
-; 2.974 ; Ready       ; RCKEEN      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.195      ;
-; 2.976 ; FS[10]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.197      ;
-; 2.976 ; FS[11]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.197      ;
-; 2.996 ; FS[0]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.217      ;
-; 3.051 ; FS[6]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.272      ;
-; 3.059 ; FS[9]       ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.280      ;
-; 3.060 ; CASr        ; CASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.281      ;
-; 3.076 ; CASr3       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.297      ;
-; 3.087 ; FS[11]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.308      ;
-; 3.087 ; FS[10]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.308      ;
-; 3.089 ; n8MEGEN     ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.310      ;
-; 3.106 ; PHI2r2      ; DRCLK       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.327      ;
-; 3.107 ; FS[0]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.328      ;
-; 3.112 ; FS[17]      ; InitReady   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.333      ;
-; 3.117 ; RCKEEN      ; RCKEEN      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.338      ;
-; 3.161 ; S[0]        ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.382      ;
-; 3.170 ; FS[7]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
-; 3.170 ; FS[9]       ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.391      ;
-; 3.174 ; RASr2       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.395      ;
-; 3.179 ; FS[5]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
-; 3.179 ; FS[4]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
-; 3.179 ; FS[15]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
-; 3.179 ; FS[14]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.400      ;
-; 3.181 ; FS[12]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.402      ;
-; 3.182 ; FS[2]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.403      ;
-; 3.184 ; Ready       ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.405      ;
-; 3.198 ; FS[10]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.419      ;
-; 3.199 ; IS[0]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.420      ;
-; 3.201 ; InitReady   ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.422      ;
-; 3.226 ; Ready       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.447      ;
-; 3.257 ; CASr3       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.478      ;
-; 3.281 ; FS[9]       ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.502      ;
-; 3.285 ; RASr2       ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.506      ;
-; 3.289 ; RASr2       ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.510      ;
-; 3.290 ; FS[5]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.511      ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'ARCLK'                                                                                                                                                              ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
-; Slack   ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                                                                  ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
-; -29.500 ; 0.500        ; 30.000         ; High Pulse Width ; ARCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
-; -29.500 ; 0.500        ; 30.000         ; Low Pulse Width  ; ARCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; ARCLK ; Rise       ; ARCLK|regout                                                                                            ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; ARCLK ; Rise       ; ARCLK|regout                                                                                            ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; ARCLK ; Rise       ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|arclk                                           ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; ARCLK ; Rise       ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|arclk                                           ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'DRCLK'                                                                                                                                                  ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
-; Slack   ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                                                      ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
-; -29.500 ; 0.500        ; 30.000         ; High Pulse Width ; DRCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ;
-; -29.500 ; 0.500        ; 30.000         ; Low Pulse Width  ; DRCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component|wire_maxii_ufm_block1_drdout ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; DRCLK ; Rise       ; DRCLK|regout                                                                                ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; DRCLK ; Rise       ; DRCLK|regout                                                                                ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; DRCLK ; Rise       ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|drclk                               ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; DRCLK ; Rise       ; UFM_inst|UFM_altufm_none_imr_component|maxii_ufm_block1|drclk                               ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'PHI2'                                                                       ;
-+--------+--------------+----------------+------------------+-------+------------+------------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target           ;
-+--------+--------------+----------------+------------------+-------+------------+------------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; PHI2  ; Rise       ; PHI2             ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; ADSubmitted      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; ADSubmitted      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[0]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[0]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[1]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[1]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[2]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[2]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[3]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[3]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[4]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[4]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[5]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[5]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[6]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[6]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; Bank[7]          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[7]          ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; C1Submitted      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; C1Submitted      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdDRCLK         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdDRCLK         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdDRDIn         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdDRDIn         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdEnable        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdEnable        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdSubmitted     ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdSubmitted     ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdUFMErase      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdUFMErase      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; CmdUFMPrgm       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdUFMPrgm       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; Cmdn8MEGEN       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; Cmdn8MEGEN       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Rise       ; RA11             ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Rise       ; RA11             ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; UFMOscEN         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; UFMOscEN         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; PHI2  ; Fall       ; XOR8MEG          ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; PHI2  ; Fall       ; XOR8MEG          ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; ADSubmitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; ADSubmitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[0]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[0]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[1]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[1]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[2]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[2]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[3]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[3]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[4]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[4]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[5]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[5]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[6]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[6]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[7]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[7]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; C1Submitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; C1Submitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdDRCLK|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdDRCLK|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdDRDIn|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdDRDIn|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdEnable|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdEnable|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdSubmitted|clk ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdSubmitted|clk ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdUFMErase|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdUFMErase|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdUFMPrgm|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdUFMPrgm|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Cmdn8MEGEN|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Cmdn8MEGEN|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; PHI2|combout     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; PHI2|combout     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; RA11|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; RA11|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; UFMOscEN|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; UFMOscEN|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; XOR8MEG|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; XOR8MEG|clk      ;
-+--------+--------------+----------------+------------------+-------+------------+------------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'RCLK'                                                                  ;
-+--------+--------------+----------------+------------------+-------+------------+-------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target      ;
-+--------+--------------+----------------+------------------+-------+------------+-------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; RCLK  ; Rise       ; RCLK        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; ARCLK       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; ARCLK       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; ARShift     ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; ARShift     ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; CASr        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; CASr2       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr2       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; CASr3       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr3       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; DRCLK       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; DRCLK       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; DRDIn       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; DRDIn       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; DRShift     ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; DRShift     ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[0]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[0]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[10]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[10]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[11]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[11]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[12]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[12]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[13]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[13]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[14]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[14]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[15]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[15]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[16]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[16]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[17]      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[17]      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[1]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[1]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[2]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[2]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[3]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[3]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[4]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[4]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[5]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[5]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[6]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[6]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[7]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[7]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[8]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[8]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; FS[9]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[9]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[0]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[0]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[1]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[1]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[2]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[2]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; IS[3]       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[3]       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; InitReady   ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; InitReady   ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; LEDEN       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; LEDEN       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r2      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r2      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r3      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r3      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RA10        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RA10        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RASr        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RASr2       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr2       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RASr3       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr3       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RCKEEN      ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RCKEEN      ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; RCKE~reg0   ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; RCKE~reg0   ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; Ready       ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; Ready       ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; S[0]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; S[0]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; S[1]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; S[1]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMD[15]    ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMD[15]    ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMErase    ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMErase    ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMInitDone ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMInitDone ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMProgram  ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMProgram  ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; UFMReqErase ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMReqErase ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; RCLK  ; Rise       ; n8MEGEN     ;
-+--------+--------------+----------------+------------------+-------+------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'nCCAS'                                                                   ;
-+--------+--------------+----------------+------------------+-------+------------+---------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target        ;
-+--------+--------------+----------------+------------------+-------+------------+---------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; nCCAS ; Rise       ; nCCAS         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[0]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[0]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[1]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[1]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[2]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[2]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[3]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[3]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[4]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[4]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[5]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[5]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[6]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[6]        ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCCAS ; Fall       ; WRD[7]        ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[7]        ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[0]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[0]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[1]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[1]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[2]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[2]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[3]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[3]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[4]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[4]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[5]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[5]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[6]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[6]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[7]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[7]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; nCCAS|combout ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; nCCAS|combout ;
-+--------+--------------+----------------+------------------+-------+------------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'nCRAS'                                                                     ;
-+--------+--------------+----------------+------------------+-------+------------+-----------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target          ;
-+--------+--------------+----------------+------------------+-------+------------+-----------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; nCRAS ; Rise       ; nCRAS           ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; CBR             ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; CBR             ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; FWEr            ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; FWEr            ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RBA[0]~reg0     ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RBA[0]~reg0     ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RBA[1]~reg0     ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RBA[1]~reg0     ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[0]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[0]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[1]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[1]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[2]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[2]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[3]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[3]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[4]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[4]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[5]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[5]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[6]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[6]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[7]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[7]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[8]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[8]         ;
-; 0.234  ; 0.500        ; 0.266          ; High Pulse Width ; nCRAS ; Fall       ; RowA[9]         ;
-; 0.234  ; 0.500        ; 0.266          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[9]         ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; CBR|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; CBR|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; FWEr|clk        ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; FWEr|clk        ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RBA[0]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RBA[0]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RBA[1]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RBA[1]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[0]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[0]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[1]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[1]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[2]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[2]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[3]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[3]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[4]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[4]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[5]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[5]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[6]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[6]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[7]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[7]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[8]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[8]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[9]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[9]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; nCRAS|combout   ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; nCRAS|combout   ;
-+--------+--------------+----------------+------------------+-------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Setup Times                                                             ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Din[*]    ; PHI2       ; 1.258  ; 1.258  ; Rise       ; PHI2            ;
-;  Din[0]   ; PHI2       ; -0.399 ; -0.399 ; Rise       ; PHI2            ;
-;  Din[1]   ; PHI2       ; -0.465 ; -0.465 ; Rise       ; PHI2            ;
-;  Din[2]   ; PHI2       ; -0.419 ; -0.419 ; Rise       ; PHI2            ;
-;  Din[3]   ; PHI2       ; -0.432 ; -0.432 ; Rise       ; PHI2            ;
-;  Din[4]   ; PHI2       ; -0.403 ; -0.403 ; Rise       ; PHI2            ;
-;  Din[5]   ; PHI2       ; -0.284 ; -0.284 ; Rise       ; PHI2            ;
-;  Din[6]   ; PHI2       ; 1.258  ; 1.258  ; Rise       ; PHI2            ;
-;  Din[7]   ; PHI2       ; -0.455 ; -0.455 ; Rise       ; PHI2            ;
-; Din[*]    ; PHI2       ; 6.350  ; 6.350  ; Fall       ; PHI2            ;
-;  Din[0]   ; PHI2       ; 6.350  ; 6.350  ; Fall       ; PHI2            ;
-;  Din[1]   ; PHI2       ; 5.955  ; 5.955  ; Fall       ; PHI2            ;
-;  Din[2]   ; PHI2       ; 5.770  ; 5.770  ; Fall       ; PHI2            ;
-;  Din[3]   ; PHI2       ; 6.091  ; 6.091  ; Fall       ; PHI2            ;
-;  Din[4]   ; PHI2       ; 6.121  ; 6.121  ; Fall       ; PHI2            ;
-;  Din[5]   ; PHI2       ; 5.943  ; 5.943  ; Fall       ; PHI2            ;
-;  Din[6]   ; PHI2       ; 5.355  ; 5.355  ; Fall       ; PHI2            ;
-;  Din[7]   ; PHI2       ; 5.526  ; 5.526  ; Fall       ; PHI2            ;
-; MAin[*]   ; PHI2       ; 6.395  ; 6.395  ; Fall       ; PHI2            ;
-;  MAin[0]  ; PHI2       ; 3.121  ; 3.121  ; Fall       ; PHI2            ;
-;  MAin[1]  ; PHI2       ; 3.011  ; 3.011  ; Fall       ; PHI2            ;
-;  MAin[2]  ; PHI2       ; 6.395  ; 6.395  ; Fall       ; PHI2            ;
-;  MAin[3]  ; PHI2       ; 5.274  ; 5.274  ; Fall       ; PHI2            ;
-;  MAin[4]  ; PHI2       ; 5.540  ; 5.540  ; Fall       ; PHI2            ;
-;  MAin[5]  ; PHI2       ; 6.213  ; 6.213  ; Fall       ; PHI2            ;
-;  MAin[6]  ; PHI2       ; 4.745  ; 4.745  ; Fall       ; PHI2            ;
-;  MAin[7]  ; PHI2       ; 5.629  ; 5.629  ; Fall       ; PHI2            ;
-; nFWE      ; PHI2       ; 4.554  ; 4.554  ; Fall       ; PHI2            ;
-; PHI2      ; RCLK       ; 1.892  ; 1.892  ; Rise       ; RCLK            ;
-; nCCAS     ; RCLK       ; 1.746  ; 1.746  ; Rise       ; RCLK            ;
-; nCRAS     ; RCLK       ; 1.799  ; 1.799  ; Rise       ; RCLK            ;
-; Din[*]    ; nCCAS      ; -0.186 ; -0.186 ; Fall       ; nCCAS           ;
-;  Din[0]   ; nCCAS      ; -0.211 ; -0.211 ; Fall       ; nCCAS           ;
-;  Din[1]   ; nCCAS      ; -0.524 ; -0.524 ; Fall       ; nCCAS           ;
-;  Din[2]   ; nCCAS      ; -0.467 ; -0.467 ; Fall       ; nCCAS           ;
-;  Din[3]   ; nCCAS      ; -0.495 ; -0.495 ; Fall       ; nCCAS           ;
-;  Din[4]   ; nCCAS      ; -0.201 ; -0.201 ; Fall       ; nCCAS           ;
-;  Din[5]   ; nCCAS      ; -0.387 ; -0.387 ; Fall       ; nCCAS           ;
-;  Din[6]   ; nCCAS      ; -0.186 ; -0.186 ; Fall       ; nCCAS           ;
-;  Din[7]   ; nCCAS      ; -0.459 ; -0.459 ; Fall       ; nCCAS           ;
-; CROW[*]   ; nCRAS      ; 1.569  ; 1.569  ; Fall       ; nCRAS           ;
-;  CROW[0]  ; nCRAS      ; 1.396  ; 1.396  ; Fall       ; nCRAS           ;
-;  CROW[1]  ; nCRAS      ; 1.569  ; 1.569  ; Fall       ; nCRAS           ;
-; MAin[*]   ; nCRAS      ; -0.660 ; -0.660 ; Fall       ; nCRAS           ;
-;  MAin[0]  ; nCRAS      ; -0.660 ; -0.660 ; Fall       ; nCRAS           ;
-;  MAin[1]  ; nCRAS      ; -0.783 ; -0.783 ; Fall       ; nCRAS           ;
-;  MAin[2]  ; nCRAS      ; -1.185 ; -1.185 ; Fall       ; nCRAS           ;
-;  MAin[3]  ; nCRAS      ; -1.355 ; -1.355 ; Fall       ; nCRAS           ;
-;  MAin[4]  ; nCRAS      ; -1.507 ; -1.507 ; Fall       ; nCRAS           ;
-;  MAin[5]  ; nCRAS      ; -1.728 ; -1.728 ; Fall       ; nCRAS           ;
-;  MAin[6]  ; nCRAS      ; -1.433 ; -1.433 ; Fall       ; nCRAS           ;
-;  MAin[7]  ; nCRAS      ; -1.123 ; -1.123 ; Fall       ; nCRAS           ;
-;  MAin[8]  ; nCRAS      ; -1.416 ; -1.416 ; Fall       ; nCRAS           ;
-;  MAin[9]  ; nCRAS      ; -1.500 ; -1.500 ; Fall       ; nCRAS           ;
-; nCCAS     ; nCRAS      ; 0.462  ; 0.462  ; Fall       ; nCRAS           ;
-; nFWE      ; nCRAS      ; 1.077  ; 1.077  ; Fall       ; nCRAS           ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Hold Times                                                              ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Din[*]    ; PHI2       ; 1.019  ; 1.019  ; Rise       ; PHI2            ;
-;  Din[0]   ; PHI2       ; 0.953  ; 0.953  ; Rise       ; PHI2            ;
-;  Din[1]   ; PHI2       ; 1.019  ; 1.019  ; Rise       ; PHI2            ;
-;  Din[2]   ; PHI2       ; 0.973  ; 0.973  ; Rise       ; PHI2            ;
-;  Din[3]   ; PHI2       ; 0.986  ; 0.986  ; Rise       ; PHI2            ;
-;  Din[4]   ; PHI2       ; 0.957  ; 0.957  ; Rise       ; PHI2            ;
-;  Din[5]   ; PHI2       ; 0.838  ; 0.838  ; Rise       ; PHI2            ;
-;  Din[6]   ; PHI2       ; 0.033  ; 0.033  ; Rise       ; PHI2            ;
-;  Din[7]   ; PHI2       ; 1.009  ; 1.009  ; Rise       ; PHI2            ;
-; Din[*]    ; PHI2       ; 0.456  ; 0.456  ; Fall       ; PHI2            ;
-;  Din[0]   ; PHI2       ; 0.456  ; 0.456  ; Fall       ; PHI2            ;
-;  Din[1]   ; PHI2       ; 0.037  ; 0.037  ; Fall       ; PHI2            ;
-;  Din[2]   ; PHI2       ; -0.029 ; -0.029 ; Fall       ; PHI2            ;
-;  Din[3]   ; PHI2       ; -0.577 ; -0.577 ; Fall       ; PHI2            ;
-;  Din[4]   ; PHI2       ; 0.113  ; 0.113  ; Fall       ; PHI2            ;
-;  Din[5]   ; PHI2       ; -1.945 ; -1.945 ; Fall       ; PHI2            ;
-;  Din[6]   ; PHI2       ; -1.358 ; -1.358 ; Fall       ; PHI2            ;
-;  Din[7]   ; PHI2       ; -1.521 ; -1.521 ; Fall       ; PHI2            ;
-; MAin[*]   ; PHI2       ; 0.373  ; 0.373  ; Fall       ; PHI2            ;
-;  MAin[0]  ; PHI2       ; 0.263  ; 0.263  ; Fall       ; PHI2            ;
-;  MAin[1]  ; PHI2       ; 0.373  ; 0.373  ; Fall       ; PHI2            ;
-;  MAin[2]  ; PHI2       ; -1.645 ; -1.645 ; Fall       ; PHI2            ;
-;  MAin[3]  ; PHI2       ; -0.524 ; -0.524 ; Fall       ; PHI2            ;
-;  MAin[4]  ; PHI2       ; -0.790 ; -0.790 ; Fall       ; PHI2            ;
-;  MAin[5]  ; PHI2       ; -1.463 ; -1.463 ; Fall       ; PHI2            ;
-;  MAin[6]  ; PHI2       ; -1.361 ; -1.361 ; Fall       ; PHI2            ;
-;  MAin[7]  ; PHI2       ; -2.245 ; -2.245 ; Fall       ; PHI2            ;
-; nFWE      ; PHI2       ; -1.272 ; -1.272 ; Fall       ; PHI2            ;
-; PHI2      ; RCLK       ; -1.338 ; -1.338 ; Rise       ; RCLK            ;
-; nCCAS     ; RCLK       ; -1.192 ; -1.192 ; Rise       ; RCLK            ;
-; nCRAS     ; RCLK       ; -1.245 ; -1.245 ; Rise       ; RCLK            ;
-; Din[*]    ; nCCAS      ; 1.078  ; 1.078  ; Fall       ; nCCAS           ;
-;  Din[0]   ; nCCAS      ; 0.765  ; 0.765  ; Fall       ; nCCAS           ;
-;  Din[1]   ; nCCAS      ; 1.078  ; 1.078  ; Fall       ; nCCAS           ;
-;  Din[2]   ; nCCAS      ; 1.021  ; 1.021  ; Fall       ; nCCAS           ;
-;  Din[3]   ; nCCAS      ; 1.049  ; 1.049  ; Fall       ; nCCAS           ;
-;  Din[4]   ; nCCAS      ; 0.755  ; 0.755  ; Fall       ; nCCAS           ;
-;  Din[5]   ; nCCAS      ; 0.941  ; 0.941  ; Fall       ; nCCAS           ;
-;  Din[6]   ; nCCAS      ; 0.740  ; 0.740  ; Fall       ; nCCAS           ;
-;  Din[7]   ; nCCAS      ; 1.013  ; 1.013  ; Fall       ; nCCAS           ;
-; CROW[*]   ; nCRAS      ; -0.842 ; -0.842 ; Fall       ; nCRAS           ;
-;  CROW[0]  ; nCRAS      ; -0.842 ; -0.842 ; Fall       ; nCRAS           ;
-;  CROW[1]  ; nCRAS      ; -1.015 ; -1.015 ; Fall       ; nCRAS           ;
-; MAin[*]   ; nCRAS      ; 2.282  ; 2.282  ; Fall       ; nCRAS           ;
-;  MAin[0]  ; nCRAS      ; 1.214  ; 1.214  ; Fall       ; nCRAS           ;
-;  MAin[1]  ; nCRAS      ; 1.337  ; 1.337  ; Fall       ; nCRAS           ;
-;  MAin[2]  ; nCRAS      ; 1.739  ; 1.739  ; Fall       ; nCRAS           ;
-;  MAin[3]  ; nCRAS      ; 1.909  ; 1.909  ; Fall       ; nCRAS           ;
-;  MAin[4]  ; nCRAS      ; 2.061  ; 2.061  ; Fall       ; nCRAS           ;
-;  MAin[5]  ; nCRAS      ; 2.282  ; 2.282  ; Fall       ; nCRAS           ;
-;  MAin[6]  ; nCRAS      ; 1.987  ; 1.987  ; Fall       ; nCRAS           ;
-;  MAin[7]  ; nCRAS      ; 1.677  ; 1.677  ; Fall       ; nCRAS           ;
-;  MAin[8]  ; nCRAS      ; 1.970  ; 1.970  ; Fall       ; nCRAS           ;
-;  MAin[9]  ; nCRAS      ; 2.054  ; 2.054  ; Fall       ; nCRAS           ;
-; nCCAS     ; nCRAS      ; 0.092  ; 0.092  ; Fall       ; nCRAS           ;
-; nFWE      ; nCRAS      ; -0.523 ; -0.523 ; Fall       ; nCRAS           ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Clock to Output Times                                                   ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; RA[*]     ; PHI2       ; 12.060 ; 12.060 ; Rise       ; PHI2            ;
-;  RA[11]   ; PHI2       ; 12.060 ; 12.060 ; Rise       ; PHI2            ;
-; LED       ; RCLK       ; 9.813  ; 9.813  ; Rise       ; RCLK            ;
-; RA[*]     ; RCLK       ; 12.293 ; 12.293 ; Rise       ; RCLK            ;
-;  RA[0]    ; RCLK       ; 12.293 ; 12.293 ; Rise       ; RCLK            ;
-;  RA[1]    ; RCLK       ; 11.412 ; 11.412 ; Rise       ; RCLK            ;
-;  RA[2]    ; RCLK       ; 11.273 ; 11.273 ; Rise       ; RCLK            ;
-;  RA[3]    ; RCLK       ; 10.539 ; 10.539 ; Rise       ; RCLK            ;
-;  RA[4]    ; RCLK       ; 11.236 ; 11.236 ; Rise       ; RCLK            ;
-;  RA[5]    ; RCLK       ; 11.157 ; 11.157 ; Rise       ; RCLK            ;
-;  RA[6]    ; RCLK       ; 11.290 ; 11.290 ; Rise       ; RCLK            ;
-;  RA[7]    ; RCLK       ; 11.217 ; 11.217 ; Rise       ; RCLK            ;
-;  RA[8]    ; RCLK       ; 11.381 ; 11.381 ; Rise       ; RCLK            ;
-;  RA[9]    ; RCLK       ; 11.302 ; 11.302 ; Rise       ; RCLK            ;
-;  RA[10]   ; RCLK       ; 8.195  ; 8.195  ; Rise       ; RCLK            ;
-; RCKE      ; RCLK       ; 7.518  ; 7.518  ; Rise       ; RCLK            ;
-; RDQMH     ; RCLK       ; 10.547 ; 10.547 ; Rise       ; RCLK            ;
-; RDQML     ; RCLK       ; 11.010 ; 11.010 ; Rise       ; RCLK            ;
-; nRCAS     ; RCLK       ; 7.518  ; 7.518  ; Rise       ; RCLK            ;
-; nRCS      ; RCLK       ; 8.142  ; 8.142  ; Rise       ; RCLK            ;
-; nRRAS     ; RCLK       ; 7.536  ; 7.536  ; Rise       ; RCLK            ;
-; nRWE      ; RCLK       ; 8.637  ; 8.637  ; Rise       ; RCLK            ;
-; RD[*]     ; nCCAS      ; 19.663 ; 19.663 ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 18.824 ; 18.824 ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 18.920 ; 18.920 ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 18.917 ; 18.917 ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 19.501 ; 19.501 ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 18.823 ; 18.823 ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 18.946 ; 18.946 ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 19.663 ; 19.663 ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 18.951 ; 18.951 ; Fall       ; nCCAS           ;
-; LED       ; nCRAS      ; 6.153  ; 6.153  ; Rise       ; nCRAS           ;
-; LED       ; nCRAS      ; 6.153  ; 6.153  ; Fall       ; nCRAS           ;
-; RA[*]     ; nCRAS      ; 13.196 ; 13.196 ; Fall       ; nCRAS           ;
-;  RA[0]    ; nCRAS      ; 12.954 ; 12.954 ; Fall       ; nCRAS           ;
-;  RA[1]    ; nCRAS      ; 12.928 ; 12.928 ; Fall       ; nCRAS           ;
-;  RA[2]    ; nCRAS      ; 12.374 ; 12.374 ; Fall       ; nCRAS           ;
-;  RA[3]    ; nCRAS      ; 13.196 ; 13.196 ; Fall       ; nCRAS           ;
-;  RA[4]    ; nCRAS      ; 12.862 ; 12.862 ; Fall       ; nCRAS           ;
-;  RA[5]    ; nCRAS      ; 12.781 ; 12.781 ; Fall       ; nCRAS           ;
-;  RA[6]    ; nCRAS      ; 13.093 ; 13.093 ; Fall       ; nCRAS           ;
-;  RA[7]    ; nCRAS      ; 13.020 ; 13.020 ; Fall       ; nCRAS           ;
-;  RA[8]    ; nCRAS      ; 13.070 ; 13.070 ; Fall       ; nCRAS           ;
-;  RA[9]    ; nCRAS      ; 13.106 ; 13.106 ; Fall       ; nCRAS           ;
-; RBA[*]    ; nCRAS      ; 10.091 ; 10.091 ; Fall       ; nCRAS           ;
-;  RBA[0]   ; nCRAS      ; 10.087 ; 10.087 ; Fall       ; nCRAS           ;
-;  RBA[1]   ; nCRAS      ; 10.091 ; 10.091 ; Fall       ; nCRAS           ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Minimum Clock to Output Times                                           ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; RA[*]     ; PHI2       ; 12.060 ; 12.060 ; Rise       ; PHI2            ;
-;  RA[11]   ; PHI2       ; 12.060 ; 12.060 ; Rise       ; PHI2            ;
-; LED       ; RCLK       ; 9.813  ; 9.813  ; Rise       ; RCLK            ;
-; RA[*]     ; RCLK       ; 8.195  ; 8.195  ; Rise       ; RCLK            ;
-;  RA[0]    ; RCLK       ; 12.293 ; 12.293 ; Rise       ; RCLK            ;
-;  RA[1]    ; RCLK       ; 11.412 ; 11.412 ; Rise       ; RCLK            ;
-;  RA[2]    ; RCLK       ; 11.273 ; 11.273 ; Rise       ; RCLK            ;
-;  RA[3]    ; RCLK       ; 10.539 ; 10.539 ; Rise       ; RCLK            ;
-;  RA[4]    ; RCLK       ; 11.236 ; 11.236 ; Rise       ; RCLK            ;
-;  RA[5]    ; RCLK       ; 11.157 ; 11.157 ; Rise       ; RCLK            ;
-;  RA[6]    ; RCLK       ; 11.290 ; 11.290 ; Rise       ; RCLK            ;
-;  RA[7]    ; RCLK       ; 11.217 ; 11.217 ; Rise       ; RCLK            ;
-;  RA[8]    ; RCLK       ; 11.381 ; 11.381 ; Rise       ; RCLK            ;
-;  RA[9]    ; RCLK       ; 11.302 ; 11.302 ; Rise       ; RCLK            ;
-;  RA[10]   ; RCLK       ; 8.195  ; 8.195  ; Rise       ; RCLK            ;
-; RCKE      ; RCLK       ; 7.518  ; 7.518  ; Rise       ; RCLK            ;
-; RDQMH     ; RCLK       ; 10.547 ; 10.547 ; Rise       ; RCLK            ;
-; RDQML     ; RCLK       ; 11.010 ; 11.010 ; Rise       ; RCLK            ;
-; nRCAS     ; RCLK       ; 7.518  ; 7.518  ; Rise       ; RCLK            ;
-; nRCS      ; RCLK       ; 8.142  ; 8.142  ; Rise       ; RCLK            ;
-; nRRAS     ; RCLK       ; 7.536  ; 7.536  ; Rise       ; RCLK            ;
-; nRWE      ; RCLK       ; 8.637  ; 8.637  ; Rise       ; RCLK            ;
-; RD[*]     ; nCCAS      ; 18.823 ; 18.823 ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 18.824 ; 18.824 ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 18.920 ; 18.920 ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 18.917 ; 18.917 ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 19.501 ; 19.501 ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 18.823 ; 18.823 ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 18.946 ; 18.946 ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 19.663 ; 19.663 ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 18.951 ; 18.951 ; Fall       ; nCCAS           ;
-; LED       ; nCRAS      ; 6.153  ; 6.153  ; Rise       ; nCRAS           ;
-; LED       ; nCRAS      ; 6.153  ; 6.153  ; Fall       ; nCRAS           ;
-; RA[*]     ; nCRAS      ; 12.374 ; 12.374 ; Fall       ; nCRAS           ;
-;  RA[0]    ; nCRAS      ; 12.954 ; 12.954 ; Fall       ; nCRAS           ;
-;  RA[1]    ; nCRAS      ; 12.928 ; 12.928 ; Fall       ; nCRAS           ;
-;  RA[2]    ; nCRAS      ; 12.374 ; 12.374 ; Fall       ; nCRAS           ;
-;  RA[3]    ; nCRAS      ; 13.196 ; 13.196 ; Fall       ; nCRAS           ;
-;  RA[4]    ; nCRAS      ; 12.862 ; 12.862 ; Fall       ; nCRAS           ;
-;  RA[5]    ; nCRAS      ; 12.781 ; 12.781 ; Fall       ; nCRAS           ;
-;  RA[6]    ; nCRAS      ; 13.093 ; 13.093 ; Fall       ; nCRAS           ;
-;  RA[7]    ; nCRAS      ; 13.020 ; 13.020 ; Fall       ; nCRAS           ;
-;  RA[8]    ; nCRAS      ; 13.070 ; 13.070 ; Fall       ; nCRAS           ;
-;  RA[9]    ; nCRAS      ; 13.106 ; 13.106 ; Fall       ; nCRAS           ;
-; RBA[*]    ; nCRAS      ; 10.087 ; 10.087 ; Fall       ; nCRAS           ;
-;  RBA[0]   ; nCRAS      ; 10.087 ; 10.087 ; Fall       ; nCRAS           ;
-;  RBA[1]   ; nCRAS      ; 10.091 ; 10.091 ; Fall       ; nCRAS           ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+------------------------------------------------------+
-; Propagation Delay                                    ;
-+------------+-------------+--------+----+----+--------+
-; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
-+------------+-------------+--------+----+----+--------+
-; MAin[0]    ; RA[0]       ; 10.197 ;    ;    ; 10.197 ;
-; MAin[1]    ; RA[1]       ; 9.846  ;    ;    ; 9.846  ;
-; MAin[2]    ; RA[2]       ; 9.051  ;    ;    ; 9.051  ;
-; MAin[3]    ; RA[3]       ; 8.214  ;    ;    ; 8.214  ;
-; MAin[4]    ; RA[4]       ; 8.144  ;    ;    ; 8.144  ;
-; MAin[5]    ; RA[5]       ; 8.753  ;    ;    ; 8.753  ;
-; MAin[6]    ; RA[6]       ; 8.281  ;    ;    ; 8.281  ;
-; MAin[7]    ; RA[7]       ; 9.251  ;    ;    ; 9.251  ;
-; MAin[8]    ; RA[8]       ; 8.196  ;    ;    ; 8.196  ;
-; MAin[9]    ; RA[9]       ; 8.221  ;    ;    ; 8.221  ;
-; MAin[9]    ; RDQMH       ; 7.373  ;    ;    ; 7.373  ;
-; MAin[9]    ; RDQML       ; 7.833  ;    ;    ; 7.833  ;
-; RD[0]      ; Dout[0]     ; 6.115  ;    ;    ; 6.115  ;
-; RD[1]      ; Dout[1]     ; 6.297  ;    ;    ; 6.297  ;
-; RD[2]      ; Dout[2]     ; 6.244  ;    ;    ; 6.244  ;
-; RD[3]      ; Dout[3]     ; 6.825  ;    ;    ; 6.825  ;
-; RD[4]      ; Dout[4]     ; 6.717  ;    ;    ; 6.717  ;
-; RD[5]      ; Dout[5]     ; 6.723  ;    ;    ; 6.723  ;
-; RD[6]      ; Dout[6]     ; 6.184  ;    ;    ; 6.184  ;
-; RD[7]      ; Dout[7]     ; 6.756  ;    ;    ; 6.756  ;
-; nFWE       ; RD[0]       ; 16.365 ;    ;    ; 16.365 ;
-; nFWE       ; RD[1]       ; 16.324 ;    ;    ; 16.324 ;
-; nFWE       ; RD[2]       ; 16.324 ;    ;    ; 16.324 ;
-; nFWE       ; RD[3]       ; 16.365 ;    ;    ; 16.365 ;
-; nFWE       ; RD[4]       ; 16.365 ;    ;    ; 16.365 ;
-; nFWE       ; RD[5]       ; 16.324 ;    ;    ; 16.324 ;
-; nFWE       ; RD[6]       ; 16.365 ;    ;    ; 16.365 ;
-; nFWE       ; RD[7]       ; 16.365 ;    ;    ; 16.365 ;
-+------------+-------------+--------+----+----+--------+
-
-
-+------------------------------------------------------+
-; Minimum Propagation Delay                            ;
-+------------+-------------+--------+----+----+--------+
-; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
-+------------+-------------+--------+----+----+--------+
-; MAin[0]    ; RA[0]       ; 10.197 ;    ;    ; 10.197 ;
-; MAin[1]    ; RA[1]       ; 9.846  ;    ;    ; 9.846  ;
-; MAin[2]    ; RA[2]       ; 9.051  ;    ;    ; 9.051  ;
-; MAin[3]    ; RA[3]       ; 8.214  ;    ;    ; 8.214  ;
-; MAin[4]    ; RA[4]       ; 8.144  ;    ;    ; 8.144  ;
-; MAin[5]    ; RA[5]       ; 8.753  ;    ;    ; 8.753  ;
-; MAin[6]    ; RA[6]       ; 8.281  ;    ;    ; 8.281  ;
-; MAin[7]    ; RA[7]       ; 9.251  ;    ;    ; 9.251  ;
-; MAin[8]    ; RA[8]       ; 8.196  ;    ;    ; 8.196  ;
-; MAin[9]    ; RA[9]       ; 8.221  ;    ;    ; 8.221  ;
-; MAin[9]    ; RDQMH       ; 7.373  ;    ;    ; 7.373  ;
-; MAin[9]    ; RDQML       ; 7.833  ;    ;    ; 7.833  ;
-; RD[0]      ; Dout[0]     ; 6.115  ;    ;    ; 6.115  ;
-; RD[1]      ; Dout[1]     ; 6.297  ;    ;    ; 6.297  ;
-; RD[2]      ; Dout[2]     ; 6.244  ;    ;    ; 6.244  ;
-; RD[3]      ; Dout[3]     ; 6.825  ;    ;    ; 6.825  ;
-; RD[4]      ; Dout[4]     ; 6.717  ;    ;    ; 6.717  ;
-; RD[5]      ; Dout[5]     ; 6.723  ;    ;    ; 6.723  ;
-; RD[6]      ; Dout[6]     ; 6.184  ;    ;    ; 6.184  ;
-; RD[7]      ; Dout[7]     ; 6.756  ;    ;    ; 6.756  ;
-; nFWE       ; RD[0]       ; 16.365 ;    ;    ; 16.365 ;
-; nFWE       ; RD[1]       ; 16.324 ;    ;    ; 16.324 ;
-; nFWE       ; RD[2]       ; 16.324 ;    ;    ; 16.324 ;
-; nFWE       ; RD[3]       ; 16.365 ;    ;    ; 16.365 ;
-; nFWE       ; RD[4]       ; 16.365 ;    ;    ; 16.365 ;
-; nFWE       ; RD[5]       ; 16.324 ;    ;    ; 16.324 ;
-; nFWE       ; RD[6]       ; 16.365 ;    ;    ; 16.365 ;
-; nFWE       ; RD[7]       ; 16.365 ;    ;    ; 16.365 ;
-+------------+-------------+--------+----+----+--------+
-
-
-+-----------------------------------------------------------------------+
-; Output Enable Times                                                   ;
-+-----------+------------+--------+------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
-+-----------+------------+--------+------+------------+-----------------+
-
-
-+-----------------------------------------------------------------------+
-; Minimum Output Enable Times                                           ;
-+-----------+------------+--------+------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.659 ;      ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 13.700 ;      ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.659 ;      ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 13.700 ;      ; Fall       ; nCCAS           ;
-+-----------+------------+--------+------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------------+
-; Output Disable Times                                                          ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------------+
-; Minimum Output Disable Times                                                  ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.659    ;           ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 13.700    ;           ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 13.659    ;           ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 13.700    ;           ; Fall       ; nCCAS           ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-
-
-+-------------------------------------------------------------------+
-; Setup Transfers                                                   ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
-; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
-; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 14       ;
-; RCLK       ; PHI2     ; 2        ; 0        ; 1        ; 0        ;
-; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
-; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
-; PHI2       ; RCLK     ; 1        ; 11       ; 0        ; 0        ;
-; RCLK       ; RCLK     ; 620      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-------------------------------------------------------------------+
-; Hold Transfers                                                    ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
-; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
-; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 14       ;
-; RCLK       ; PHI2     ; 2        ; 0        ; 1        ; 0        ;
-; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
-; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
-; PHI2       ; RCLK     ; 1        ; 11       ; 0        ; 0        ;
-; RCLK       ; RCLK     ; 620      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths                            ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 31    ; 31   ;
-; Unconstrained Input Port Paths  ; 232   ; 232  ;
-; Unconstrained Output Ports      ; 38    ; 38   ;
-; Unconstrained Output Port Paths ; 77    ; 77   ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
-    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Mon Aug 16 18:40:18 2021
-Info: Command: quartus_sta RAM2GS-MAXII -c RAM2GS
-Info: qsta_default_script.tcl version: #1
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (306004): Started post-fitting delay annotation
-Info (306005): Delay annotation completed successfully
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
-    Info (332105): create_clock -period 1.000 -name DRCLK DRCLK
-    Info (332105): create_clock -period 1.000 -name ARCLK ARCLK
-    Info (332105): create_clock -period 1.000 -name RCLK RCLK
-    Info (332105): create_clock -period 1.000 -name nCRAS nCRAS
-    Info (332105): create_clock -period 1.000 -name PHI2 PHI2
-    Info (332105): create_clock -period 1.000 -name nCCAS nCCAS
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Critical Warning (332148): Timing requirements not met
-Info (332146): Worst-case setup slack is -99.000
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):   -99.000       -99.000 ARCLK 
-    Info (332119):   -99.000       -99.000 DRCLK 
-    Info (332119):    -8.339      -245.761 RCLK 
-    Info (332119):    -8.271       -88.383 PHI2 
-    Info (332119):    -0.317        -2.784 nCRAS 
-Info (332146): Worst-case hold slack is -16.858
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):   -16.858       -16.858 ARCLK 
-    Info (332119):   -16.363       -16.363 DRCLK 
-    Info (332119):    -0.103        -0.195 nCRAS 
-    Info (332119):    -0.060        -0.060 PHI2 
-    Info (332119):     1.192         0.000 RCLK 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -29.500
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):   -29.500       -59.000 ARCLK 
-    Info (332119):   -29.500       -59.000 DRCLK 
-    Info (332119):    -2.289        -2.289 PHI2 
-    Info (332119):    -2.289        -2.289 RCLK 
-    Info (332119):    -2.289        -2.289 nCCAS 
-    Info (332119):    -2.289        -2.289 nCRAS 
-Info (332001): The selected device family is not supported by the report_metastability command.
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
-    Info: Peak virtual memory: 374 megabytes
-    Info: Processing ended: Mon Aug 16 18:40:19 2021
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/CPLD-old/MAX/MAXII/output_files/RAM2GS.sta.summary b/CPLD-old/MAX/MAXII/output_files/RAM2GS.sta.summary
deleted file mode 100644
index adebd09..0000000
--- a/CPLD-old/MAX/MAXII/output_files/RAM2GS.sta.summary
+++ /dev/null
@@ -1,69 +0,0 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type  : Setup 'ARCLK'
-Slack : -99.000
-TNS   : -99.000
-
-Type  : Setup 'DRCLK'
-Slack : -99.000
-TNS   : -99.000
-
-Type  : Setup 'RCLK'
-Slack : -8.339
-TNS   : -245.761
-
-Type  : Setup 'PHI2'
-Slack : -8.271
-TNS   : -88.383
-
-Type  : Setup 'nCRAS'
-Slack : -0.317
-TNS   : -2.784
-
-Type  : Hold 'ARCLK'
-Slack : -16.858
-TNS   : -16.858
-
-Type  : Hold 'DRCLK'
-Slack : -16.363
-TNS   : -16.363
-
-Type  : Hold 'nCRAS'
-Slack : -0.103
-TNS   : -0.195
-
-Type  : Hold 'PHI2'
-Slack : -0.060
-TNS   : -0.060
-
-Type  : Hold 'RCLK'
-Slack : 1.192
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'ARCLK'
-Slack : -29.500
-TNS   : -59.000
-
-Type  : Minimum Pulse Width 'DRCLK'
-Slack : -29.500
-TNS   : -59.000
-
-Type  : Minimum Pulse Width 'PHI2'
-Slack : -2.289
-TNS   : -2.289
-
-Type  : Minimum Pulse Width 'RCLK'
-Slack : -2.289
-TNS   : -2.289
-
-Type  : Minimum Pulse Width 'nCCAS'
-Slack : -2.289
-TNS   : -2.289
-
-Type  : Minimum Pulse Width 'nCRAS'
-Slack : -2.289
-TNS   : -2.289
-
-------------------------------------------------------------
diff --git a/CPLD-old/MAX/MAXV/RAM2GS-MAXV.qpf b/CPLD-old/MAX/MAXV/RAM2GS-MAXV.qpf
deleted file mode 100644
index 8fb201a..0000000
--- a/CPLD-old/MAX/MAXV/RAM2GS-MAXV.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-# Date created = 18:33:17  August 16, 2021
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.0"
-DATE = "18:33:17  August 16, 2021"
-
-# Revisions
-
-PROJECT_REVISION = "RAM2GS"
diff --git a/CPLD-old/MAX/MAXV/RAM2GS.qsf b/CPLD-old/MAX/MAXV/RAM2GS.qsf
deleted file mode 100644
index ecad28a..0000000
--- a/CPLD-old/MAX/MAXV/RAM2GS.qsf
+++ /dev/null
@@ -1,212 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
-# Date created = 21:16:34  March 08, 2020
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		RAM4GS_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "MAX V"
-set_global_assignment -name DEVICE 5M240ZT100C5
-set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34  MARCH 08, 2020"
-set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-set_global_assignment -name SMART_RECOMPILE OFF
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
-set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON
-set_global_assignment -name SAFE_STATE_MACHINE ON
-
-
-
-set_location_assignment PIN_12 -to RCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK
-
-set_location_assignment PIN_52 -to PHI2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI2
-
-set_location_assignment PIN_67 -to nCRAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCRAS
-
-set_location_assignment PIN_53 -to nCCAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCCAS
-
-set_location_assignment PIN_48 -to nFWE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nFWE
-
-set_location_assignment PIN_49 -to MAin[0]
-set_location_assignment PIN_51 -to MAin[1]
-set_location_assignment PIN_50 -to MAin[2]
-set_location_assignment PIN_71 -to MAin[3]
-set_location_assignment PIN_70 -to MAin[4]
-set_location_assignment PIN_69 -to MAin[5]
-set_location_assignment PIN_72 -to MAin[6]
-set_location_assignment PIN_68 -to MAin[7]
-set_location_assignment PIN_73 -to MAin[8]
-set_location_assignment PIN_74 -to MAin[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MAin
-
-set_location_assignment PIN_54 -to CROW[0]
-set_location_assignment PIN_55 -to CROW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CROW
-
-set_location_assignment PIN_35 -to Din[2]
-set_location_assignment PIN_36 -to Din[1]
-set_location_assignment PIN_37 -to Din[3]
-set_location_assignment PIN_38 -to Din[5]
-set_location_assignment PIN_39 -to Din[4]
-set_location_assignment PIN_40 -to Din[7]
-set_location_assignment PIN_41 -to Din[6]
-set_location_assignment PIN_42 -to Din[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
-
-set_location_assignment PIN_33 -to Dout[0]
-set_location_assignment PIN_57 -to Dout[1]
-set_location_assignment PIN_56 -to Dout[2]
-set_location_assignment PIN_47 -to Dout[3]
-set_location_assignment PIN_44 -to Dout[4]
-set_location_assignment PIN_28 -to Dout[5]
-set_location_assignment PIN_34 -to Dout[6]
-set_location_assignment PIN_43 -to Dout[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
-
-set_location_assignment PIN_8 -to RCKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCKE
-
-set_location_assignment PIN_3 -to nRCS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCS
-
-set_location_assignment PIN_100 -to nRWE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
-
-set_location_assignment PIN_6 -to nRRAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRRAS
-
-set_location_assignment PIN_4 -to nRCAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCAS
-
-set_location_assignment PIN_5 -to RBA[0]
-set_location_assignment PIN_14 -to RBA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RBA
-
-set_location_assignment PIN_18 -to RA[0]
-set_location_assignment PIN_20 -to RA[1]
-set_location_assignment PIN_30 -to RA[2]
-set_location_assignment PIN_27 -to RA[3]
-set_location_assignment PIN_26 -to RA[4]
-set_location_assignment PIN_29 -to RA[5]
-set_location_assignment PIN_21 -to RA[6]
-set_location_assignment PIN_19 -to RA[7]
-set_location_assignment PIN_17 -to RA[8]
-set_location_assignment PIN_15 -to RA[9]
-set_location_assignment PIN_16 -to RA[10]
-set_location_assignment PIN_7 -to RA[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
-
-set_location_assignment PIN_2 -to RDQMH
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQMH
-
-set_location_assignment PIN_98 -to RDQML
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQML
-
-set_location_assignment PIN_96 -to RD[0]
-set_location_assignment PIN_90 -to RD[1]
-set_location_assignment PIN_89 -to RD[2]
-set_location_assignment PIN_99 -to RD[3]
-set_location_assignment PIN_92 -to RD[4]
-set_location_assignment PIN_91 -to RD[5]
-set_location_assignment PIN_95 -to RD[6]
-set_location_assignment PIN_97 -to RD[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
-
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS
-set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to MAin
-set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to CROW
-set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to Din
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to Dout
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to Dout
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCKE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RCKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRWE
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRRAS
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRRAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCAS
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCAS
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RBA
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RBA
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RBA
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RA
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RA
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQMH
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQMH
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQML
-set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
-set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
-set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
-set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v"
-set_global_assignment -name MIF_FILE "../RAM2GS-MAX.mif"
-set_global_assignment -name QIP_FILE UFM.qip
\ No newline at end of file
diff --git a/CPLD-old/MAX/MAXV/RAM2GS.qws b/CPLD-old/MAX/MAXV/RAM2GS.qws
deleted file mode 100644
index 9b197653715f02733573d21d56802889fdc64823..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.asm.qmsg b/CPLD-old/MAX/MAXV/db/RAM2GS.asm.qmsg
deleted file mode 100644
index 1db2993..0000000
--- a/CPLD-old/MAX/MAXV/db/RAM2GS.asm.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153622162 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153622162 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:21 2021 " "Processing started: Mon Aug 16 18:40:21 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153622162 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1629153622162 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1629153622162 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1629153622381 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1629153622381 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153622537 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:22 2021 " "Processing ended: Mon Aug 16 18:40:22 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153622537 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153622537 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153622537 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1629153622537 ""}
diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.asm.rdb b/CPLD-old/MAX/MAXV/db/RAM2GS.asm.rdb
deleted file mode 100644
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GIT binary patch
literal 0
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diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.asm_labs.ddb b/CPLD-old/MAX/MAXV/db/RAM2GS.asm_labs.ddb
deleted file mode 100644
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GIT binary patch
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diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.cmp.cdb b/CPLD-old/MAX/MAXV/db/RAM2GS.cmp.cdb
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diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.cmp.kpt b/CPLD-old/MAX/MAXV/db/RAM2GS.cmp.kpt
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index 73afc77cce3987b44386c824647e1f5ad09811f6..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.cmp.logdb b/CPLD-old/MAX/MAXV/db/RAM2GS.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/CPLD-old/MAX/MAXV/db/RAM2GS.cmp.logdb
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diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.cmp.rdb b/CPLD-old/MAX/MAXV/db/RAM2GS.cmp.rdb
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diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.db_info b/CPLD-old/MAX/MAXV/db/RAM2GS.db_info
deleted file mode 100644
index 816de1e..0000000
--- a/CPLD-old/MAX/MAXV/db/RAM2GS.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-Version_Index = 302049280
-Creation_Time = Mon Aug 16 18:36:34 2021
diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.fit.qmsg b/CPLD-old/MAX/MAXV/db/RAM2GS.fit.qmsg
deleted file mode 100644
index 5f9e7a9..0000000
--- a/CPLD-old/MAX/MAXV/db/RAM2GS.fit.qmsg
+++ /dev/null
@@ -1,46 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1629153618530 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2GS\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1629153618530 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153618577 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153618577 ""}
-{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1629153618639 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1629153618639 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153618748 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1629153618748 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 63 " "No exact pin location assignment(s) for 1 pins of 63 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LED " "Pin LED not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LED } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 11 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LED } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 336 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1629153618764 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1629153618764 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1629153618842 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1629153618842 ""}
-{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1629153618857 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        ARCLK " "   1.000        ARCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        DRCLK " "   1.000        DRCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCCAS " "   1.000        nCCAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        nCRAS " "   1.000        nCRAS" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         PHI2 " "   1.000         PHI2" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         RCLK " "   1.000         RCLK" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618857 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 38 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 17 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""}  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 332 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 18 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""}  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 334 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 21 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~3 " "Destination \"comb~3\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 19 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153618857 ""}  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 0 { 0 ""} 0 333 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153618857 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1629153618873 ""}
-{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1629153618889 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1629153618889 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1629153618904 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1629153618904 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1629153618904 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1629153618904 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1629153618920 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1629153618920 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1629153618920 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153618920 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 24 17 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used --  17 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153618920 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1629153618920 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1629153618920 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153618951 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1629153619045 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153619232 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1629153619247 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1629153619871 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153619871 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1629153619903 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1629153620137 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1629153620137 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153621129 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1629153621129 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153621139 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1629153621169 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1629153621219 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "548 " "Peak virtual memory: 548 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153621239 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:21 2021 " "Processing ended: Mon Aug 16 18:40:21 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153621239 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153621239 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153621239 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1629153621239 ""}
diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.hier_info b/CPLD-old/MAX/MAXV/db/RAM2GS.hier_info
deleted file mode 100644
index d04c06b..0000000
--- a/CPLD-old/MAX/MAXV/db/RAM2GS.hier_info
+++ /dev/null
@@ -1,280 +0,0 @@
-|RAM2GS
-PHI2 => Bank[0].CLK
-PHI2 => Bank[1].CLK
-PHI2 => Bank[2].CLK
-PHI2 => Bank[3].CLK
-PHI2 => Bank[4].CLK
-PHI2 => Bank[5].CLK
-PHI2 => Bank[6].CLK
-PHI2 => Bank[7].CLK
-PHI2 => RA11.CLK
-PHI2 => PHI2r.DATAIN
-PHI2 => CmdDRDIn.CLK
-PHI2 => CmdDRCLK.CLK
-PHI2 => CmdUFMPrgm.CLK
-PHI2 => CmdUFMErase.CLK
-PHI2 => CmdSubmitted.CLK
-PHI2 => Cmdn8MEGEN.CLK
-PHI2 => XOR8MEG.CLK
-PHI2 => ADSubmitted.CLK
-PHI2 => C1Submitted.CLK
-PHI2 => UFMOscEN.CLK
-PHI2 => CmdEnable.CLK
-MAin[0] => RA.DATAA
-MAin[0] => RowA.DATAB
-MAin[0] => Equal0.IN7
-MAin[0] => Equal1.IN7
-MAin[0] => Equal3.IN6
-MAin[1] => RA.DATAA
-MAin[1] => RowA.DATAB
-MAin[1] => Equal0.IN6
-MAin[1] => Equal1.IN6
-MAin[1] => Equal3.IN7
-MAin[2] => RA.DATAA
-MAin[2] => RowA.DATAB
-MAin[2] => Equal0.IN5
-MAin[2] => Equal1.IN5
-MAin[2] => Equal3.IN5
-MAin[3] => RA.DATAA
-MAin[3] => RowA.DATAB
-MAin[3] => Equal0.IN4
-MAin[3] => Equal1.IN4
-MAin[3] => Equal3.IN4
-MAin[4] => RA.DATAA
-MAin[4] => RowA.DATAB
-MAin[4] => Equal0.IN3
-MAin[4] => Equal1.IN3
-MAin[4] => Equal3.IN3
-MAin[5] => RA.DATAA
-MAin[5] => RowA.DATAB
-MAin[5] => Equal0.IN2
-MAin[5] => Equal1.IN2
-MAin[5] => Equal3.IN2
-MAin[6] => RA.DATAA
-MAin[6] => RowA.DATAB
-MAin[6] => Equal0.IN1
-MAin[6] => Equal1.IN1
-MAin[6] => Equal3.IN1
-MAin[7] => RA.DATAA
-MAin[7] => RowA.DATAB
-MAin[7] => Equal0.IN0
-MAin[7] => Equal1.IN0
-MAin[7] => Equal3.IN0
-MAin[8] => RA.DATAA
-MAin[8] => RowA.DATAB
-MAin[9] => RA.DATAA
-MAin[9] => comb.DATAA
-MAin[9] => RowA.DATAB
-MAin[9] => comb.DATAA
-CROW[0] => RBA.DATAB
-CROW[1] => RBA.DATAB
-Din[0] => CmdDRDIn.DATAB
-Din[0] => XOR8MEG.DATAB
-Din[0] => WRD[0].DATAIN
-Din[0] => Bank[0].DATAIN
-Din[0] => Equal14.IN2
-Din[0] => Equal15.IN4
-Din[0] => Cmdn8MEGEN.DATAB
-Din[1] => CmdDRCLK.DATAB
-Din[1] => WRD[1].DATAIN
-Din[1] => Bank[1].DATAIN
-Din[1] => Equal14.IN7
-Din[1] => Equal15.IN7
-Din[2] => CmdUFMPrgm.DATAB
-Din[2] => WRD[2].DATAIN
-Din[2] => Bank[2].DATAIN
-Din[2] => Equal14.IN6
-Din[2] => Equal15.IN3
-Din[3] => CmdUFMErase.DATAB
-Din[3] => WRD[3].DATAIN
-Din[3] => Bank[3].DATAIN
-Din[3] => Equal14.IN5
-Din[3] => Equal15.IN2
-Din[4] => WRD[4].DATAIN
-Din[4] => Bank[4].DATAIN
-Din[4] => Equal14.IN4
-Din[4] => Equal15.IN6
-Din[4] => Equal16.IN3
-Din[4] => Equal17.IN0
-Din[4] => Equal18.IN3
-Din[5] => WRD[5].DATAIN
-Din[5] => Bank[5].DATAIN
-Din[5] => Equal14.IN3
-Din[5] => Equal15.IN1
-Din[5] => Equal16.IN2
-Din[5] => Equal17.IN3
-Din[5] => Equal18.IN0
-Din[6] => RA11.IN1
-Din[6] => WRD[6].DATAIN
-Din[6] => Bank[6].DATAIN
-Din[6] => Equal14.IN1
-Din[6] => Equal15.IN5
-Din[6] => Equal16.IN1
-Din[6] => Equal17.IN2
-Din[6] => Equal18.IN2
-Din[7] => WRD[7].DATAIN
-Din[7] => Bank[7].DATAIN
-Din[7] => Equal14.IN0
-Din[7] => Equal15.IN0
-Din[7] => Equal16.IN0
-Din[7] => Equal17.IN1
-Din[7] => Equal18.IN1
-Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE
-Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE
-Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE
-Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE
-Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE
-Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE
-Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE
-Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE
-nCCAS => WRD[0].CLK
-nCCAS => WRD[1].CLK
-nCCAS => WRD[2].CLK
-nCCAS => WRD[3].CLK
-nCCAS => WRD[4].CLK
-nCCAS => WRD[5].CLK
-nCCAS => WRD[6].CLK
-nCCAS => WRD[7].CLK
-nCCAS => comb.IN0
-nCCAS => CBR.DATAIN
-nCCAS => CASr.DATAIN
-nCRAS => CBR.CLK
-nCRAS => FWEr.CLK
-nCRAS => RowA[0].CLK
-nCRAS => RowA[1].CLK
-nCRAS => RowA[2].CLK
-nCRAS => RowA[3].CLK
-nCRAS => RowA[4].CLK
-nCRAS => RowA[5].CLK
-nCRAS => RowA[6].CLK
-nCRAS => RowA[7].CLK
-nCRAS => RowA[8].CLK
-nCRAS => RowA[9].CLK
-nCRAS => RBA[0]~reg0.CLK
-nCRAS => RBA[1]~reg0.CLK
-nCRAS => comb.IN1
-nCRAS => RASr.DATAIN
-nFWE => comb.IN1
-nFWE => CMDWR.IN1
-nFWE => ADWR.IN1
-nFWE => C1WR.IN1
-nFWE => FWEr.DATAIN
-LED <= comb.DB_MAX_OUTPUT_PORT_TYPE
-RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
-RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE
-RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE
-RD[0] <> RD[0]
-RD[1] <> RD[1]
-RD[2] <> RD[2]
-RD[3] <> RD[3]
-RD[4] <> RD[4]
-RD[5] <> RD[5]
-RD[6] <> RD[6]
-RD[7] <> RD[7]
-nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RCLK => UFMProgram.CLK
-RCLK => UFMErase.CLK
-RCLK => UFMReqErase.CLK
-RCLK => LEDEN.CLK
-RCLK => UFMInitDone.CLK
-RCLK => n8MEGEN.CLK
-RCLK => UFMD[15].CLK
-RCLK => DRShift.CLK
-RCLK => DRDIn.CLK
-RCLK => DRCLK.CLK
-RCLK => ARShift.CLK
-RCLK => ARCLK.CLK
-RCLK => Ready.CLK
-RCLK => IS[0].CLK
-RCLK => IS[1].CLK
-RCLK => IS[2].CLK
-RCLK => IS[3].CLK
-RCLK => nRowColSel.CLK
-RCLK => RCKEEN.CLK
-RCLK => RA10.CLK
-RCLK => nRWE~reg0.CLK
-RCLK => nRCAS~reg0.CLK
-RCLK => nRRAS~reg0.CLK
-RCLK => nRCS~reg0.CLK
-RCLK => RCKE~reg0.CLK
-RCLK => InitReady.CLK
-RCLK => FS[0].CLK
-RCLK => FS[1].CLK
-RCLK => FS[2].CLK
-RCLK => FS[3].CLK
-RCLK => FS[4].CLK
-RCLK => FS[5].CLK
-RCLK => FS[6].CLK
-RCLK => FS[7].CLK
-RCLK => FS[8].CLK
-RCLK => FS[9].CLK
-RCLK => FS[10].CLK
-RCLK => FS[11].CLK
-RCLK => FS[12].CLK
-RCLK => FS[13].CLK
-RCLK => FS[14].CLK
-RCLK => FS[15].CLK
-RCLK => FS[16].CLK
-RCLK => FS[17].CLK
-RCLK => S[0].CLK
-RCLK => S[1].CLK
-RCLK => CASr3.CLK
-RCLK => CASr2.CLK
-RCLK => CASr.CLK
-RCLK => RASr3.CLK
-RCLK => RASr2.CLK
-RCLK => RASr.CLK
-RCLK => PHI2r3.CLK
-RCLK => PHI2r2.CLK
-RCLK => PHI2r.CLK
-RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-RDQMH <= comb.DB_MAX_OUTPUT_PORT_TYPE
-RDQML <= comb.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|RAM2GS|UFM:UFM_inst
-arclk => arclk.IN1
-ardin => ardin.IN1
-arshft => arshft.IN1
-drclk => drclk.IN1
-drdin => drdin.IN1
-drshft => drshft.IN1
-erase => erase.IN1
-oscena => oscena.IN1
-program => program.IN1
-busy <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.busy
-drdout <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.drdout
-osc <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.osc
-rtpbusy <= UFM_altufm_none_mjr:UFM_altufm_none_mjr_component.rtpbusy
-
-
-|RAM2GS|UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component
-arclk => maxii_ufm_block1.ARCLK
-ardin => maxii_ufm_block1.ARDIN
-arshft => maxii_ufm_block1.ARSHFT
-busy <= maxii_ufm_block1.BUSY
-drclk => maxii_ufm_block1.DRCLK
-drdin => maxii_ufm_block1.DRDIN
-drdout <= maxii_ufm_block1.DRDOUT
-drshft => maxii_ufm_block1.DRSHFT
-erase => maxii_ufm_block1.ERASE
-osc <= maxii_ufm_block1.OSC
-oscena => maxii_ufm_block1.OSCENA
-program => maxii_ufm_block1.PROGRAM
-rtpbusy <= maxii_ufm_block1.BGPBUSY
-
-
diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.hif b/CPLD-old/MAX/MAXV/db/RAM2GS.hif
deleted file mode 100644
index 6fb7059b3f10346fe7560225c337fa832382b096..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 587
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zohHA@63-^Cw+`{rSvg^gsH?&bytO~Iaj=;9jyu1y+}79W-i_|eUC+1i#`c}1H-C*d
z_1qxz*V8a)zxu=6$`emIld
ZJsPHYdXVev=QpPDN|<2a&3FFn9^M9oB60u#

diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.ipinfo b/CPLD-old/MAX/MAXV/db/RAM2GS.ipinfo
deleted file mode 100644
index fa2304dd52e67aba538ff1d8d0aba1434af3953a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 177
zcmWe+U|?9w%?KomfzSy^hou%3XXfWA7#iyt=ouR+VDHxdP8ye{w85kNX
z1g932WhSR81SBSBD;O#SdntscCMme4WR?JRasUkhfhGvWpbMopLg@;|U;qFAuV+&L
z@&Es?U`$F$NC`+tNHEwhyFu2&kb`Msdc*p~@q5x8_AH-2yM9l%u*aN6&JK_x|NjR7
DEJZLE

diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.lpc.html b/CPLD-old/MAX/MAXV/db/RAM2GS.lpc.html
deleted file mode 100644
index 707f37e..0000000
--- a/CPLD-old/MAX/MAXV/db/RAM2GS.lpc.html
+++ /dev/null
@@ -1,50 +0,0 @@
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    HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
    UFM_inst|UFM_altufm_none_mjr_component9000400000000
    UFM_inst9101411100000
    
diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.lpc.rdb b/CPLD-old/MAX/MAXV/db/RAM2GS.lpc.rdb
deleted file mode 100644
index 8216994aeb44be36d9eb61f771fd5be8ab8a6518..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 509
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diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.lpc.txt b/CPLD-old/MAX/MAXV/db/RAM2GS.lpc.txt
deleted file mode 100644
index 17b369e..0000000
--- a/CPLD-old/MAX/MAXV/db/RAM2GS.lpc.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                                                  ;
-+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy                              ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; UFM_inst|UFM_altufm_none_mjr_component ; 9     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; UFM_inst                               ; 9     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.map.cdb b/CPLD-old/MAX/MAXV/db/RAM2GS.map.cdb
deleted file mode 100644
index e4871a7e489cf02a26baaf719ccae998556344cb..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.map.logdb b/CPLD-old/MAX/MAXV/db/RAM2GS.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/CPLD-old/MAX/MAXV/db/RAM2GS.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.map.qmsg b/CPLD-old/MAX/MAXV/db/RAM2GS.map.qmsg
deleted file mode 100644
index 92e65f5..0000000
--- a/CPLD-old/MAX/MAXV/db/RAM2GS.map.qmsg
+++ /dev/null
@@ -1,27 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153616333 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:16 2021 " "Processing started: Mon Aug 16 18:40:16 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153616333 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153616598 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(56) " "Verilog HDL warning at RAM2GS-MAX.v(56): extended using \"x\" or \"z\"" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1629153616661 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153616661 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153616661 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 72 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153616707 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 188 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153616707 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_mjr " "Found entity 1: UFM_altufm_none_mjr" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153616707 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" {  } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 165 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153616707 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153616707 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1629153616739 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(158) " "Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2)" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 158 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153616754 "|RAM2GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(163) " "Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18)" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153616754 "|RAM2GS"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(290) " "Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4)" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 290 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153616754 "|RAM2GS"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" {  } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 87 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153616770 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_mjr UFM:UFM_inst\|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component " "Elaborating entity \"UFM_altufm_none_mjr\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component\"" {  } { { "UFM.v" "UFM_altufm_none_mjr_component" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v" 216 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153616770 ""}
-{ "Critical Warning" "WCDB_CDB_FILE_NOT_FOUND" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/RAM2GS-MAX.mif " "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/RAM2GS-MAX.mif -- setting all initial values to 0" {  } {  } 1 127003 "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! -- setting all initial values to 0" 0 0 "Quartus II" 0 -1 1629153616785 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
-{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" {  } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } }  } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153617207 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_LCELLS" "177 " "Implemented 177 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1629153617319 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" {  } {  } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1629153617319 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1629153617319 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1629153617350 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153617380 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:17 2021 " "Processing ended: Mon Aug 16 18:40:17 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153617380 ""}
diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.map.rdb b/CPLD-old/MAX/MAXV/db/RAM2GS.map.rdb
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diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.sld_design_entry_dsc.sci b/CPLD-old/MAX/MAXV/db/RAM2GS.sld_design_entry_dsc.sci
deleted file mode 100644
index 1d6d60ff385eac213bc3fcb4244fa82d1a8f7a3a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.smart_action.txt b/CPLD-old/MAX/MAXV/db/RAM2GS.smart_action.txt
deleted file mode 100644
index c8e8a13..0000000
--- a/CPLD-old/MAX/MAXV/db/RAM2GS.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.sta.qmsg b/CPLD-old/MAX/MAXV/db/RAM2GS.sta.qmsg
deleted file mode 100644
index 734cddd..0000000
--- a/CPLD-old/MAX/MAXV/db/RAM2GS.sta.qmsg
+++ /dev/null
@@ -1,23 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153623584 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:23 2021 " "Processing started: Mon Aug 16 18:40:23 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153623584 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1629153623662 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153623787 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153623834 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153623834 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1629153623896 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1629153624208 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1629153624255 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624255 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1629153624255 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1629153624270 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 ARCLK  " "  -99.000       -99.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -99.000       -99.000 DRCLK  " "  -99.000       -99.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -23.638      -216.621 PHI2  " "  -23.638      -216.621 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -19.942      -610.547 RCLK  " "  -19.942      -610.547 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.072        -6.479 nCRAS  " "   -3.072        -6.479 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.153 " "Worst-case hold slack is -16.153" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -16.153       -16.153 ARCLK  " "  -16.153       -16.153 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -14.623       -14.623 DRCLK  " "  -14.623       -14.623 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.569        -3.433 PHI2  " "   -2.569        -3.433 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.713        -2.822 nCRAS  " "   -0.713        -2.822 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.127         0.000 RCLK  " "    2.127         0.000 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153624270 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153624270 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 ARCLK  " "  -29.500       -59.000 ARCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -29.500       -59.000 DRCLK  " "  -29.500       -59.000 DRCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 PHI2  " "   -2.289        -2.289 PHI2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 RCLK  " "   -2.289        -2.289 RCLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCCAS  " "   -2.289        -2.289 nCCAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 nCRAS  " "   -2.289        -2.289 nCRAS " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153624270 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1629153624348 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153624348 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153624348 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "368 " "Peak virtual memory: 368 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153624395 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:24 2021 " "Processing ended: Mon Aug 16 18:40:24 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153624395 ""}
diff --git a/CPLD-old/MAX/MAXV/db/RAM2GS.sta.rdb b/CPLD-old/MAX/MAXV/db/RAM2GS.sta.rdb
deleted file mode 100644
index e9c2f8b2e71d80571657495ed6de634edc794336..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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zfeN(AN7;FvntA@!%JaGB=828xkcsEtEj*8dJ^Jw@^G?gfbmx=r+L2GR*Jy(@v7?l0_?lZdb*=ci-io0J^%J(*zgH+UgMpwSQ-5jL4
zKOehxB=oTRaw@bVp=%qAnnOz4zR>cT>VE6fUe^CNagX+Gb>B$Regw2-q`KGn2X>T*
z+9&P?OGG>Nb8X9Fb4Y31rdvj;`{tx?hifwKzTvHWy|_6@DPN4!(xKmu8nOGW&$Z(u
zt9*-dOU1Mu-I2Ka1Df)kqvjx`{X}hpNNFnr{~yqfZDe%6Ne%5dplJ`YIi$3of@)dq
f=zdLU3ocKQdi=@5|HilcQGPkUdhx~IKaIlBbfH1-

diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.asm.rpt b/CPLD-old/MAX/MAXV/output_files/RAM2GS.asm.rpt
deleted file mode 100644
index f918f0d..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.asm.rpt
+++ /dev/null
@@ -1,114 +0,0 @@
-Assembler report for RAM2GS
-Mon Aug 16 18:40:22 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Mon Aug 16 18:40:22 2021 ;
-; Revision Name         ; RAM2GS                                ;
-; Top-level Entity Name ; RAM2GS                                ;
-; Family                ; MAX V                                 ;
-; Device                ; 5M240ZT100C5                          ;
-+-----------------------+---------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Assembler Settings                                                                                      ;
-+-----------------------------------------------------------------------------+-----------+---------------+
-; Option                                                                      ; Setting   ; Default Value ;
-+-----------------------------------------------------------------------------+-----------+---------------+
-; Use smart compilation                                                       ; Off       ; Off           ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On        ; On            ;
-; Enable compact report table                                                 ; Off       ; Off           ;
-; Compression mode                                                            ; Off       ; Off           ;
-; Clock source for configuration device                                       ; Internal  ; Internal      ;
-; Clock frequency of the configuration device                                 ; 10 MHZ    ; 10 MHz        ;
-; Divide clock frequency by                                                   ; 1         ; 1             ;
-; Auto user code                                                              ; On        ; On            ;
-; Security bit                                                                ; Off       ; Off           ;
-; Use configuration device                                                    ; On        ; On            ;
-; Configuration device                                                        ; Auto      ; Auto          ;
-; Configuration device auto user code                                         ; Off       ; Off           ;
-; Generate Tabular Text File (.ttf) For Target Device                         ; Off       ; Off           ;
-; Generate Raw Binary File (.rbf) For Target Device                           ; Off       ; Off           ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off       ; Off           ;
-; Hexadecimal Output File start address                                       ; 0         ; 0             ;
-; Hexadecimal Output File count direction                                     ; Up        ; Up            ;
-; Generate Serial Vector Format File (.svf) for Target Device                 ; Off       ; Off           ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off       ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off       ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On        ; On            ;
-; In-System Programming Default Clamp State                                   ; Tri-state ; Tri-state     ;
-+-----------------------------------------------------------------------------+-----------+---------------+
-
-
-+----------------------------------------------------------------------------+
-; Assembler Generated Files                                                  ;
-+----------------------------------------------------------------------------+
-; File Name                                                                  ;
-+----------------------------------------------------------------------------+
-; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pof ;
-+----------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------+
-; Assembler Device Options: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pof ;
-+----------------+-------------------------------------------------------------------------------------+
-; Option         ; Setting                                                                             ;
-+----------------+-------------------------------------------------------------------------------------+
-; Device         ; 5M240ZT100C5                                                                        ;
-; JTAG usercode  ; 0x00172F05                                                                          ;
-; Checksum       ; 0x001732F5                                                                          ;
-+----------------+-------------------------------------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II 64-Bit Assembler
-    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Mon Aug 16 18:40:21 2021
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 381 megabytes
-    Info: Processing ended: Mon Aug 16 18:40:22 2021
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.done b/CPLD-old/MAX/MAXV/output_files/RAM2GS.done
deleted file mode 100644
index 576e1e8..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.done
+++ /dev/null
@@ -1 +0,0 @@
-Mon Aug 16 18:40:25 2021
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.fit.rpt b/CPLD-old/MAX/MAXV/output_files/RAM2GS.fit.rpt
deleted file mode 100644
index 1cd6280..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.fit.rpt
+++ /dev/null
@@ -1,1002 +0,0 @@
-Fitter report for RAM2GS
-Mon Aug 16 18:40:21 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. Pin-Out File
-  6. Fitter Resource Usage Summary
-  7. Input Pins
-  8. Output Pins
-  9. Bidir Pins
- 10. I/O Bank Usage
- 11. All Package Pins
- 12. Output Pin Default Load For Reported TCO
- 13. Fitter Resource Utilization by Entity
- 14. Delay Chain Summary
- 15. Control Signals
- 16. Global & Other Fast Signals
- 17. Non-Global High Fan-Out Signals
- 18. Other Routing Usage Summary
- 19. LAB Logic Elements
- 20. LAB-wide Signals
- 21. LAB Signals Sourced
- 22. LAB Signals Sourced Out
- 23. LAB Distinct Inputs
- 24. Fitter Device Options
- 25. Estimated Delay Added for Hold Timing Summary
- 26. Estimated Delay Added for Hold Timing Details
- 27. Fitter Messages
- 28. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------+
-; Fitter Summary                                                              ;
-+---------------------------+-------------------------------------------------+
-; Fitter Status             ; Successful - Mon Aug 16 18:40:21 2021           ;
-; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name             ; RAM2GS                                          ;
-; Top-level Entity Name     ; RAM2GS                                          ;
-; Family                    ; MAX V                                           ;
-; Device                    ; 5M240ZT100C5                                    ;
-; Timing Models             ; Final                                           ;
-; Total logic elements      ; 168 / 240 ( 70 % )                              ;
-; Total pins                ; 63 / 79 ( 80 % )                                ;
-; Total virtual pins        ; 0                                               ;
-; UFM blocks                ; 1 / 1 ( 100 % )                                 ;
-+---------------------------+-------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                              ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Option                                                                     ; Setting                        ; Default Value                  ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Device                                                                     ; 5M240ZT100C5                   ;                                ;
-; Minimum Core Junction Temperature                                          ; 0                              ;                                ;
-; Maximum Core Junction Temperature                                          ; 85                             ;                                ;
-; Placement Effort Multiplier                                                ; 10                             ; 1.0                            ;
-; Router Effort Multiplier                                                   ; 10                             ; 1.0                            ;
-; Fit Attempts to Skip                                                       ; 0                              ; 0.0                            ;
-; Device I/O Standard                                                        ; 3.3-V LVTTL                    ;                                ;
-; Optimize Multi-Corner Timing                                               ; On                             ; Off                            ;
-; Optimize IOC Register Placement for Timing                                 ; Pack All IO Registers          ; Normal                         ;
-; Enable Bus-Hold Circuitry                                                  ; On                             ; Off                            ;
-; Fitter Effort                                                              ; Standard Fit                   ; Auto Fit                       ;
-; Use smart compilation                                                      ; Off                            ; Off                            ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                             ; On                             ;
-; Enable compact report table                                                ; Off                            ; Off                            ;
-; Router Timing Optimization Level                                           ; Normal                         ; Normal                         ;
-; Always Enable Input Buffers                                                ; Off                            ; Off                            ;
-; Optimize Hold Timing                                                       ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
-; Guarantee I/O Paths Have Zero Hold Time at Fast Corner                     ; On                             ; On                             ;
-; PowerPlay Power Optimization                                               ; Normal compilation             ; Normal compilation             ;
-; Optimize Timing                                                            ; Normal compilation             ; Normal compilation             ;
-; Optimize Timing for ECOs                                                   ; Off                            ; Off                            ;
-; Regenerate full fit report during ECO compiles                             ; Off                            ; Off                            ;
-; Limit to One Fitting Attempt                                               ; Off                            ; Off                            ;
-; Final Placement Optimizations                                              ; Automatically                  ; Automatically                  ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                  ; Automatically                  ;
-; Fitter Initial Placement Seed                                              ; 1                              ; 1                              ;
-; Slow Slew Rate                                                             ; Off                            ; Off                            ;
-; PCI I/O                                                                    ; Off                            ; Off                            ;
-; Weak Pull-Up Resistor                                                      ; Off                            ; Off                            ;
-; Auto Delay Chains                                                          ; On                             ; On                             ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                            ; Off                            ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                            ; Off                            ;
-; Perform Register Duplication for Performance                               ; Off                            ; Off                            ;
-; Perform Register Retiming for Performance                                  ; Off                            ; Off                            ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                            ; Off                            ;
-; Physical Synthesis Effort Level                                            ; Normal                         ; Normal                         ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                           ; Auto                           ;
-; Auto Register Duplication                                                  ; Auto                           ; Auto                           ;
-; Auto Global Clock                                                          ; On                             ; On                             ;
-; Auto Global Register Control Signals                                       ; On                             ; On                             ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                            ; Off                            ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 12     ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.pin.
-
-
-+------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                    ;
-+---------------------------------------------+--------------------+
-; Resource                                    ; Usage              ;
-+---------------------------------------------+--------------------+
-; Total logic elements                        ; 168 / 240 ( 70 % ) ;
-;     -- Combinational with no register       ; 71                 ;
-;     -- Register only                        ; 20                 ;
-;     -- Combinational with a register        ; 77                 ;
-;                                             ;                    ;
-; Logic element usage by number of LUT inputs ;                    ;
-;     -- 4 input functions                    ; 58                 ;
-;     -- 3 input functions                    ; 40                 ;
-;     -- 2 input functions                    ; 41                 ;
-;     -- 1 input functions                    ; 8                  ;
-;     -- 0 input functions                    ; 1                  ;
-;                                             ;                    ;
-; Logic elements by mode                      ;                    ;
-;     -- normal mode                          ; 152                ;
-;     -- arithmetic mode                      ; 16                 ;
-;     -- qfbk mode                            ; 7                  ;
-;     -- register cascade mode                ; 0                  ;
-;     -- synchronous clear/load mode          ; 24                 ;
-;     -- asynchronous clear/load mode         ; 0                  ;
-;                                             ;                    ;
-; Total registers                             ; 97 / 240 ( 40 % )  ;
-; Total LABs                                  ; 21 / 24 ( 88 % )   ;
-; Logic elements in carry chains              ; 17                 ;
-; Virtual pins                                ; 0                  ;
-; I/O pins                                    ; 63 / 79 ( 80 % )   ;
-;     -- Clock pins                           ; 3 / 4 ( 75 % )     ;
-;                                             ;                    ;
-; Global signals                              ; 4                  ;
-; UFM blocks                                  ; 1 / 1 ( 100 % )    ;
-; Global clocks                               ; 4 / 4 ( 100 % )    ;
-; JTAGs                                       ; 0 / 1 ( 0 % )      ;
-; Average interconnect usage (total/H/V)      ; 27% / 29% / 25%    ;
-; Peak interconnect usage (total/H/V)         ; 27% / 29% / 25%    ;
-; Maximum fan-out                             ; 55                 ;
-; Highest non-global fan-out                  ; 39                 ;
-; Total fan-out                               ; 643                ;
-; Average fan-out                             ; 2.77               ;
-+---------------------------------------------+--------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                     ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
-; CROW[0] ; 54    ; 2        ; 8            ; 1            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; CROW[1] ; 55    ; 2        ; 8            ; 1            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[0]  ; 42    ; 1        ; 5            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[1]  ; 36    ; 1        ; 4            ; 0            ; 2           ; 4                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[2]  ; 35    ; 1        ; 3            ; 0            ; 0           ; 5                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[3]  ; 37    ; 1        ; 4            ; 0            ; 1           ; 5                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[4]  ; 39    ; 1        ; 5            ; 0            ; 3           ; 7                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[5]  ; 38    ; 1        ; 4            ; 0            ; 0           ; 7                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[6]  ; 41    ; 1        ; 5            ; 0            ; 1           ; 8                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; Din[7]  ; 40    ; 1        ; 5            ; 0            ; 2           ; 6                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[0] ; 49    ; 1        ; 7            ; 0            ; 2           ; 5                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[1] ; 51    ; 1        ; 7            ; 0            ; 0           ; 6                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[2] ; 50    ; 1        ; 7            ; 0            ; 1           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[3] ; 71    ; 2        ; 8            ; 4            ; 3           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[4] ; 70    ; 2        ; 8            ; 4            ; 4           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[5] ; 69    ; 2        ; 8            ; 3            ; 0           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[6] ; 72    ; 2        ; 8            ; 4            ; 2           ; 4                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[7] ; 68    ; 2        ; 8            ; 3            ; 1           ; 4                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[8] ; 73    ; 2        ; 8            ; 4            ; 1           ; 2                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; MAin[9] ; 74    ; 2        ; 8            ; 4            ; 0           ; 4                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; PHI2    ; 52    ; 2        ; 8            ; 1            ; 4           ; 21                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; RCLK    ; 12    ; 1        ; 1            ; 3            ; 3           ; 55                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; nCCAS   ; 53    ; 2        ; 8            ; 1            ; 3           ; 11                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; nCRAS   ; 67    ; 2        ; 8            ; 3            ; 2           ; 16                    ; 0                  ; yes    ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-; nFWE    ; 48    ; 1        ; 6            ; 0            ; 0           ; 3                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVCMOS ; User                 ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                               ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Dout[0] ; 33    ; 1        ; 3            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[1] ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[2] ; 56    ; 2        ; 8            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[3] ; 47    ; 1        ; 6            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[4] ; 44    ; 1        ; 6            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[5] ; 28    ; 1        ; 2            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[6] ; 34    ; 1        ; 3            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; Dout[7] ; 43    ; 1        ; 6            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; LED     ; 62    ; 2        ; 8            ; 2            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVTTL  ; 16mA             ; yes                    ; Fitter               ; 10 pF ; -                    ; -                   ;
-; RA[0]   ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[10]  ; 16    ; 1        ; 1            ; 2            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[11]  ; 7     ; 1        ; 1            ; 3            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[1]   ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[2]   ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[3]   ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[4]   ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[5]   ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[6]   ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[7]   ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[8]   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RA[9]   ; 15    ; 1        ; 1            ; 2            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RBA[0]  ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RBA[1]  ; 14    ; 1        ; 1            ; 2            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; RCKE    ; 8     ; 1        ; 1            ; 3            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RDQMH   ; 2     ; 1        ; 1            ; 4            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; RDQML   ; 98    ; 2        ; 2            ; 5            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRCAS   ; 4     ; 1        ; 1            ; 4            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nRCS    ; 3     ; 1        ; 1            ; 4            ; 1           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRRAS   ; 6     ; 1        ; 1            ; 3            ; 0           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
-; nRWE    ; 100   ; 2        ; 2            ; 5            ; 2           ; no              ; no             ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVCMOS ; 4mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Bidir Pins                                                                                                                                                                                                                                                                                                                                                    ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; RD[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[1] ; 90    ; 2        ; 4            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[2] ; 89    ; 2        ; 4            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[3] ; 99    ; 2        ; 2            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[4] ; 92    ; 2        ; 3            ; 5            ; 0           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[6] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; yes                    ; User                 ; 10 pF ; comb~3               ; -                   ;
-; RD[7] ; 97    ; 2        ; 3            ; 5            ; 3           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVCMOS ; 8mA              ; no                     ; User                 ; 10 pF ; comb~3               ; -                   ;
-+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------+
-; I/O Bank Usage                                              ;
-+----------+-------------------+---------------+--------------+
-; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
-+----------+-------------------+---------------+--------------+
-; 1        ; 38 / 38 ( 100 % ) ; 3.3V          ; --           ;
-; 2        ; 25 / 41 ( 61 % )  ; 3.3V          ; --           ;
-+----------+-------------------+---------------+--------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                             ;
-+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; 1        ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 2        ; 0          ; 1        ; RDQMH          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 3        ; 1          ; 1        ; nRCS           ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 4        ; 2          ; 1        ; nRCAS          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 5        ; 3          ; 1        ; RBA[0]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 6        ; 4          ; 1        ; nRRAS          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 7        ; 5          ; 1        ; RA[11]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 8        ; 6          ; 1        ; RCKE           ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 9        ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 10       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 11       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 12       ; 7          ; 1        ; RCLK           ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 13       ;            ;          ; VCCINT         ; power  ;              ; 1.8V    ; --         ;                 ; --       ; --           ;
-; 14       ; 8          ; 1        ; RBA[1]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 15       ; 9          ; 1        ; RA[9]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 16       ; 10         ; 1        ; RA[10]         ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 17       ; 11         ; 1        ; RA[8]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 18       ; 12         ; 1        ; RA[0]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 19       ; 13         ; 1        ; RA[7]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 20       ; 14         ; 1        ; RA[1]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 21       ; 15         ; 1        ; RA[6]          ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 22       ; 16         ; 1        ; #TMS           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; 23       ; 17         ; 1        ; #TDI           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; 24       ; 18         ; 1        ; #TCK           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; 25       ; 19         ; 1        ; #TDO           ; output ;              ;         ; --         ;                 ; --       ; --           ;
-; 26       ; 20         ; 1        ; RA[4]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 27       ; 21         ; 1        ; RA[3]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 28       ; 22         ; 1        ; Dout[5]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 29       ; 23         ; 1        ; RA[5]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 30       ; 24         ; 1        ; RA[2]          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 31       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 32       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 33       ; 25         ; 1        ; Dout[0]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 34       ; 26         ; 1        ; Dout[6]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 35       ; 27         ; 1        ; Din[2]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 36       ; 28         ; 1        ; Din[1]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 37       ; 29         ; 1        ; Din[3]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 38       ; 30         ; 1        ; Din[5]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 39       ; 31         ; 1        ; Din[4]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 40       ; 32         ; 1        ; Din[7]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 41       ; 33         ; 1        ; Din[6]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 42       ; 34         ; 1        ; Din[0]         ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 43       ; 35         ; 1        ; Dout[7]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 44       ; 36         ; 1        ; Dout[4]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 45       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 46       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 47       ; 37         ; 1        ; Dout[3]        ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 48       ; 38         ; 1        ; nFWE           ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 49       ; 39         ; 1        ; MAin[0]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 50       ; 40         ; 1        ; MAin[2]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 51       ; 41         ; 1        ; MAin[1]        ; input  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 52       ; 42         ; 2        ; PHI2           ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 53       ; 43         ; 2        ; nCCAS          ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 54       ; 44         ; 2        ; CROW[0]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 55       ; 45         ; 2        ; CROW[1]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 56       ; 46         ; 2        ; Dout[2]        ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 57       ; 47         ; 2        ; Dout[1]        ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 58       ; 48         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
-; 59       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 60       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 61       ; 49         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
-; 62       ; 50         ; 2        ; LED            ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; yes      ; Off          ;
-; 63       ;            ;          ; VCCINT         ; power  ;              ; 1.8V    ; --         ;                 ; --       ; --           ;
-; 64       ; 51         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
-; 65       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 66       ; 52         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
-; 67       ; 53         ; 2        ; nCRAS          ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 68       ; 54         ; 2        ; MAin[7]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 69       ; 55         ; 2        ; MAin[5]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 70       ; 56         ; 2        ; MAin[4]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 71       ; 57         ; 2        ; MAin[3]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 72       ; 58         ; 2        ; MAin[6]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 73       ; 59         ; 2        ; MAin[8]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 74       ; 60         ; 2        ; MAin[9]        ; input  ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; yes      ; Off          ;
-; 75       ; 61         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 76       ; 62         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 77       ; 63         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 78       ; 64         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 79       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 80       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 81       ; 65         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 82       ; 66         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 83       ; 67         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 84       ; 68         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 85       ; 69         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 86       ; 70         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 87       ; 71         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 88       ; 72         ; 2        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
-; 89       ; 73         ; 2        ; RD[2]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 90       ; 74         ; 2        ; RD[1]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 91       ; 75         ; 2        ; RD[5]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 92       ; 76         ; 2        ; RD[4]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 93       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; 94       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; 95       ; 77         ; 2        ; RD[6]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 96       ; 78         ; 2        ; RD[0]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 97       ; 79         ; 2        ; RD[7]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 98       ; 80         ; 2        ; RDQML          ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 99       ; 81         ; 2        ; RD[3]          ; bidir  ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-; 100      ; 82         ; 2        ; nRWE           ; output ; 3.3-V LVCMOS ;         ; Column I/O ; Y               ; yes      ; Off          ;
-+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------------------+
-; Output Pin Default Load For Reported TCO                    ;
-+----------------------------+-------+------------------------+
-; I/O Standard               ; Load  ; Termination Resistance ;
-+----------------------------+-------+------------------------+
-; 3.3-V LVTTL                ; 10 pF ; Not Available          ;
-; 3.3-V LVCMOS               ; 10 pF ; Not Available          ;
-; 2.5 V                      ; 10 pF ; Not Available          ;
-; 1.8 V                      ; 10 pF ; Not Available          ;
-; 1.5 V                      ; 10 pF ; Not Available          ;
-; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available          ;
-; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available          ;
-; 1.2 V                      ; 10 pF ; Not Available          ;
-; LVDS_E_3R                  ; 10 pF ; Not Available          ;
-; RSDS_E_3R                  ; 10 pF ; Not Available          ;
-+----------------------------+-------+------------------------+
-Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                  ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; |RAM2GS                                                   ; 168 (168)   ; 97           ; 1          ; 63   ; 0            ; 71 (71)      ; 20 (20)           ; 77 (77)          ; 17 (17)         ; 7 (7)      ; |RAM2GS                                                                ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; work         ;
-;       |UFM_altufm_none_mjr:UFM_altufm_none_mjr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------+
-; Delay Chain Summary                ;
-+---------+----------+---------------+
-; Name    ; Pin Type ; Pad to Core 0 ;
-+---------+----------+---------------+
-; nCRAS   ; Input    ; (0)           ;
-; MAin[0] ; Input    ; (0)           ;
-; MAin[1] ; Input    ; (0)           ;
-; MAin[2] ; Input    ; (0)           ;
-; MAin[3] ; Input    ; (0)           ;
-; MAin[4] ; Input    ; (0)           ;
-; MAin[5] ; Input    ; (0)           ;
-; MAin[6] ; Input    ; (0)           ;
-; MAin[7] ; Input    ; (0)           ;
-; MAin[8] ; Input    ; (0)           ;
-; MAin[9] ; Input    ; (0)           ;
-; RCLK    ; Input    ; (0)           ;
-; CROW[0] ; Input    ; (1)           ;
-; CROW[1] ; Input    ; (1)           ;
-; PHI2    ; Input    ; (0)           ;
-; Din[6]  ; Input    ; (1)           ;
-; nFWE    ; Input    ; (1)           ;
-; Din[0]  ; Input    ; (1)           ;
-; Din[7]  ; Input    ; (1)           ;
-; Din[1]  ; Input    ; (1)           ;
-; Din[4]  ; Input    ; (1)           ;
-; Din[5]  ; Input    ; (1)           ;
-; Din[2]  ; Input    ; (1)           ;
-; Din[3]  ; Input    ; (1)           ;
-; nCCAS   ; Input    ; (0)           ;
-; Dout[0] ; Output   ; --            ;
-; Dout[1] ; Output   ; --            ;
-; Dout[2] ; Output   ; --            ;
-; Dout[3] ; Output   ; --            ;
-; Dout[4] ; Output   ; --            ;
-; Dout[5] ; Output   ; --            ;
-; Dout[6] ; Output   ; --            ;
-; Dout[7] ; Output   ; --            ;
-; LED     ; Output   ; --            ;
-; RBA[0]  ; Output   ; --            ;
-; RBA[1]  ; Output   ; --            ;
-; RA[0]   ; Output   ; --            ;
-; RA[1]   ; Output   ; --            ;
-; RA[2]   ; Output   ; --            ;
-; RA[3]   ; Output   ; --            ;
-; RA[4]   ; Output   ; --            ;
-; RA[5]   ; Output   ; --            ;
-; RA[6]   ; Output   ; --            ;
-; RA[7]   ; Output   ; --            ;
-; RA[8]   ; Output   ; --            ;
-; RA[9]   ; Output   ; --            ;
-; RA[10]  ; Output   ; --            ;
-; RA[11]  ; Output   ; --            ;
-; nRCS    ; Output   ; --            ;
-; RCKE    ; Output   ; --            ;
-; nRWE    ; Output   ; --            ;
-; nRRAS   ; Output   ; --            ;
-; nRCAS   ; Output   ; --            ;
-; RDQMH   ; Output   ; --            ;
-; RDQML   ; Output   ; --            ;
-; RD[0]   ; Bidir    ; (0)           ;
-; RD[1]   ; Bidir    ; (0)           ;
-; RD[2]   ; Bidir    ; (0)           ;
-; RD[3]   ; Bidir    ; (0)           ;
-; RD[4]   ; Bidir    ; (0)           ;
-; RD[5]   ; Bidir    ; (0)           ;
-; RD[6]   ; Bidir    ; (0)           ;
-; RD[7]   ; Bidir    ; (0)           ;
-+---------+----------+---------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                     ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; Name           ; Location    ; Fan-Out ; Usage                   ; Global ; Global Resource Used ; Global Line Name ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; CmdDRDIn~1     ; LC_X5_Y4_N5 ; 4       ; Clock enable            ; no     ; --                   ; --               ;
-; CmdSubmitted~0 ; LC_X6_Y2_N4 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
-; DRDIn~1        ; LC_X4_Y1_N2 ; 2       ; Clock enable            ; no     ; --                   ; --               ;
-; PHI2           ; PIN_52      ; 21      ; Clock                   ; yes    ; Global Clock         ; GCLK1            ;
-; RCLK           ; PIN_12      ; 55      ; Clock                   ; yes    ; Global Clock         ; GCLK0            ;
-; Ready          ; LC_X3_Y2_N8 ; 39      ; Sync. clear, Sync. load ; no     ; --                   ; --               ;
-; always8~5      ; LC_X7_Y3_N1 ; 3       ; Clock enable            ; no     ; --                   ; --               ;
-; comb~3         ; LC_X4_Y4_N6 ; 8       ; Output enable           ; no     ; --                   ; --               ;
-; nCCAS          ; PIN_53      ; 11      ; Clock                   ; yes    ; Global Clock         ; GCLK2            ;
-; nCRAS          ; PIN_67      ; 16      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ;
-+----------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-
-
-+----------------------------------------------------------------------+
-; Global & Other Fast Signals                                          ;
-+-------+----------+---------+----------------------+------------------+
-; Name  ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
-+-------+----------+---------+----------------------+------------------+
-; PHI2  ; PIN_52   ; 21      ; Global Clock         ; GCLK1            ;
-; RCLK  ; PIN_12   ; 55      ; Global Clock         ; GCLK0            ;
-; nCCAS ; PIN_53   ; 11      ; Global Clock         ; GCLK2            ;
-; nCRAS ; PIN_67   ; 16      ; Global Clock         ; GCLK3            ;
-+-------+----------+---------+----------------------+------------------+
-
-
-+-------------------------------------------------------------------------------------------------------+
-; Non-Global High Fan-Out Signals                                                                       ;
-+---------------------------------------------------------------------------------------------+---------+
-; Name                                                                                        ; Fan-Out ;
-+---------------------------------------------------------------------------------------------+---------+
-; Ready                                                                                       ; 39      ;
-; nRowColSel                                                                                  ; 13      ;
-; S[1]                                                                                        ; 12      ;
-; S[0]                                                                                        ; 12      ;
-; RASr2                                                                                       ; 9       ;
-; Din[6]                                                                                      ; 8       ;
-; comb~3                                                                                      ; 8       ;
-; Din[5]                                                                                      ; 7       ;
-; Din[4]                                                                                      ; 7       ;
-; IS[0]~0                                                                                     ; 7       ;
-; Din[7]                                                                                      ; 6       ;
-; Din[0]                                                                                      ; 6       ;
-; MAin[1]                                                                                     ; 6       ;
-; IS[0]                                                                                       ; 6       ;
-; FS[4]                                                                                       ; 6       ;
-; Din[3]                                                                                      ; 5       ;
-; Din[2]                                                                                      ; 5       ;
-; MAin[0]                                                                                     ; 5       ;
-; FS[8]~31                                                                                    ; 5       ;
-; FS[3]~13                                                                                    ; 5       ;
-; FS[3]                                                                                       ; 5       ;
-; IS[1]                                                                                       ; 5       ;
-; CBR                                                                                         ; 5       ;
-; FWEr                                                                                        ; 5       ;
-; FS[6]                                                                                       ; 5       ;
-; FS[5]                                                                                       ; 5       ;
-; FS[17]                                                                                      ; 5       ;
-; FS[16]                                                                                      ; 5       ;
-; UFMD[15]                                                                                    ; 5       ;
-; Din[1]                                                                                      ; 4       ;
-; MAin[9]                                                                                     ; 4       ;
-; MAin[7]                                                                                     ; 4       ;
-; MAin[6]                                                                                     ; 4       ;
-; CmdDRDIn~1                                                                                  ; 4       ;
-; FS[13]~27                                                                                   ; 4       ;
-; CMDWR~2                                                                                     ; 4       ;
-; UFMReqErase                                                                                 ; 4       ;
-; always9~3                                                                                   ; 4       ;
-; DRCLK~0                                                                                     ; 4       ;
-; always9~2                                                                                   ; 4       ;
-; Equal9~0                                                                                    ; 4       ;
-; IS[3]                                                                                       ; 4       ;
-; IS[2]                                                                                       ; 4       ;
-; InitReady                                                                                   ; 4       ;
-; always9~0                                                                                   ; 4       ;
-; nFWE                                                                                        ; 3       ;
-; MAin[5]                                                                                     ; 3       ;
-; MAin[4]                                                                                     ; 3       ;
-; MAin[3]                                                                                     ; 3       ;
-; MAin[2]                                                                                     ; 3       ;
-; always8~5                                                                                   ; 3       ;
-; CMDWR                                                                                       ; 3       ;
-; CmdEnable                                                                                   ; 3       ;
-; FS[0]                                                                                       ; 3       ;
-; always8~4                                                                                   ; 3       ;
-; always8~2                                                                                   ; 3       ;
-; Equal0~0                                                                                    ; 3       ;
-; nRCS~3                                                                                      ; 3       ;
-; n8MEGEN                                                                                     ; 3       ;
-; UFMInitDone~0                                                                               ; 3       ;
-; UFMInitDone                                                                                 ; 3       ;
-; RCKE~reg0                                                                                   ; 3       ;
-; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; 3       ;
-; MAin[8]                                                                                     ; 2       ;
-; CmdSubmitted~0                                                                              ; 2       ;
-; Equal17~0                                                                                   ; 2       ;
-; CmdDRDIn~0                                                                                  ; 2       ;
-; XOR8MEG~0                                                                                   ; 2       ;
-; Equal0~3                                                                                    ; 2       ;
-; Ready~0                                                                                     ; 2       ;
-; Equal26~0                                                                                   ; 2       ;
-; FS[9]                                                                                       ; 2       ;
-; FS[8]                                                                                       ; 2       ;
-; Equal5~1                                                                                    ; 2       ;
-; FS[14]                                                                                      ; 2       ;
-; FS[13]                                                                                      ; 2       ;
-; FS[12]                                                                                      ; 2       ;
-; FS[11]                                                                                      ; 2       ;
-; FS[10]                                                                                      ; 2       ;
-; FS[15]                                                                                      ; 2       ;
-; Equal24~0                                                                                   ; 2       ;
-; FS[2]                                                                                       ; 2       ;
-; FS[1]                                                                                       ; 2       ;
-; UFMOscEN~0                                                                                  ; 2       ;
-; C1Submitted                                                                                 ; 2       ;
-; Equal0~1                                                                                    ; 2       ;
-; always8~0                                                                                   ; 2       ;
-; CmdUFMErase                                                                                 ; 2       ;
-; CmdUFMPrgm                                                                                  ; 2       ;
-; always9~4                                                                                   ; 2       ;
-; PHI2r2                                                                                      ; 2       ;
-; DRDIn~1                                                                                     ; 2       ;
-; CmdSubmitted                                                                                ; 2       ;
-; RASr                                                                                        ; 2       ;
-; RCKEEN                                                                                      ; 2       ;
-; CASr2                                                                                       ; 2       ;
-; nRRAS~0                                                                                     ; 2       ;
-; nRCS~1                                                                                      ; 2       ;
-; nRCS~0                                                                                      ; 2       ;
-; XOR8MEG                                                                                     ; 2       ;
-; RA10~0                                                                                      ; 2       ;
-; nRowColSel~0                                                                                ; 2       ;
-; always9~1                                                                                   ; 2       ;
-; FS[7]                                                                                       ; 2       ;
-; UFMOscEN                                                                                    ; 2       ;
-; UFMErase                                                                                    ; 2       ;
-; UFMProgram                                                                                  ; 2       ;
-; LEDEN                                                                                       ; 2       ;
-; UFMProgram~_wirecell                                                                        ; 1       ;
-; UFMOscEN~_wirecell                                                                          ; 1       ;
-; UFMErase~_wirecell                                                                          ; 1       ;
-; RD[7]~7                                                                                     ; 1       ;
-; RD[6]~6                                                                                     ; 1       ;
-; RD[5]~5                                                                                     ; 1       ;
-; RD[4]~4                                                                                     ; 1       ;
-; RD[3]~3                                                                                     ; 1       ;
-; RD[2]~2                                                                                     ; 1       ;
-; RD[1]~1                                                                                     ; 1       ;
-; RD[0]~0                                                                                     ; 1       ;
-; CROW[1]                                                                                     ; 1       ;
-; CROW[0]                                                                                     ; 1       ;
-; CmdEnable~1                                                                                 ; 1       ;
-; CmdEnable~0                                                                                 ; 1       ;
-; PHI2r                                                                                       ; 1       ;
-; RCKEEN~2                                                                                    ; 1       ;
-; RCKEEN~1                                                                                    ; 1       ;
-; RCKEEN~0                                                                                    ; 1       ;
-; CASr                                                                                        ; 1       ;
-; Equal16~0                                                                                   ; 1       ;
-; n8MEGEN~3                                                                                   ; 1       ;
-; PHI2r3                                                                                      ; 1       ;
-; n8MEGEN~2                                                                                   ; 1       ;
-; n8MEGEN~1                                                                                   ; 1       ;
-; n8MEGEN~0                                                                                   ; 1       ;
-; Cmdn8MEGEN                                                                                  ; 1       ;
-; IS[0]~3                                                                                     ; 1       ;
-; Ready~1                                                                                     ; 1       ;
-; FS[9]~33COUT1_62                                                                            ; 1       ;
-; FS[9]~33                                                                                    ; 1       ;
-; FS[14]~29COUT1_70                                                                           ; 1       ;
-; FS[14]~29                                                                                   ; 1       ;
-; Equal5~0                                                                                    ; 1       ;
-; FS[12]~25COUT1_68                                                                           ; 1       ;
-; FS[12]~25                                                                                   ; 1       ;
-; FS[11]~23COUT1_66                                                                           ; 1       ;
-; FS[11]~23                                                                                   ; 1       ;
-; FS[10]~21COUT1_64                                                                           ; 1       ;
-; FS[10]~21                                                                                   ; 1       ;
-; FS[15]~19COUT1_72                                                                           ; 1       ;
-; FS[15]~19                                                                                   ; 1       ;
-; UFMD[15]~0                                                                                  ; 1       ;
-; FS[2]~17COUT1_52                                                                            ; 1       ;
-; FS[2]~17                                                                                    ; 1       ;
-; FS[1]~15COUT1_50                                                                            ; 1       ;
-; FS[1]~15                                                                                    ; 1       ;
-; WRD[7]                                                                                      ; 1       ;
-; WRD[6]                                                                                      ; 1       ;
-; WRD[5]                                                                                      ; 1       ;
-; WRD[4]                                                                                      ; 1       ;
-; WRD[3]                                                                                      ; 1       ;
-; WRD[2]                                                                                      ; 1       ;
-; WRD[1]                                                                                      ; 1       ;
-; WRD[0]                                                                                      ; 1       ;
-; ADSubmitted                                                                                 ; 1       ;
-; always8~3                                                                                   ; 1       ;
-; Equal0~2                                                                                    ; 1       ;
-; always8~1                                                                                   ; 1       ;
-; Equal1~0                                                                                    ; 1       ;
-; CMDWR~1                                                                                     ; 1       ;
-; Bank[7]                                                                                     ; 1       ;
-; Bank[6]                                                                                     ; 1       ;
-; Bank[5]                                                                                     ; 1       ;
-; CMDWR~0                                                                                     ; 1       ;
-; Bank[2]                                                                                     ; 1       ;
-; Bank[3]                                                                                     ; 1       ;
-; Bank[1]                                                                                     ; 1       ;
-; always9~5                                                                                   ; 1       ;
-; ARCLK~0                                                                                     ; 1       ;
-; CmdDRCLK                                                                                    ; 1       ;
-; CmdDRDIn                                                                                    ; 1       ;
-; nRCAS~1                                                                                     ; 1       ;
-; nRCAS~0                                                                                     ; 1       ;
-; nRWE~0                                                                                      ; 1       ;
-; RASr3                                                                                       ; 1       ;
-; nRCS~4                                                                                      ; 1       ;
-; nRCS~2                                                                                      ; 1       ;
-; nRowColSel~1                                                                                ; 1       ;
-; FS[4]~11COUT1_54                                                                            ; 1       ;
-; FS[4]~11                                                                                    ; 1       ;
-; FS[6]~9COUT1_58                                                                             ; 1       ;
-; FS[6]~9                                                                                     ; 1       ;
-; FS[5]~7COUT1_56                                                                             ; 1       ;
-; FS[5]~7                                                                                     ; 1       ;
-; FS[7]~5COUT1_60                                                                             ; 1       ;
-; FS[7]~5                                                                                     ; 1       ;
-; FS[16]~1COUT1_74                                                                            ; 1       ;
-; FS[16]~1                                                                                    ; 1       ;
-; ARShift                                                                                     ; 1       ;
-; ARCLK                                                                                       ; 1       ;
-; DRShift                                                                                     ; 1       ;
-; DRCLK                                                                                       ; 1       ;
-; DRDIn                                                                                       ; 1       ;
-; comb~2                                                                                      ; 1       ;
-; comb~1                                                                                      ; 1       ;
-; nRCAS~reg0                                                                                  ; 1       ;
-; nRRAS~reg0                                                                                  ; 1       ;
-; nRWE~reg0                                                                                   ; 1       ;
-; nRCS~reg0                                                                                   ; 1       ;
-; RA11                                                                                        ; 1       ;
-; RA10                                                                                        ; 1       ;
-; RA~9                                                                                        ; 1       ;
-; RowA[9]                                                                                     ; 1       ;
-; RA~8                                                                                        ; 1       ;
-; RowA[8]                                                                                     ; 1       ;
-; RA~7                                                                                        ; 1       ;
-; RowA[7]                                                                                     ; 1       ;
-; RA~6                                                                                        ; 1       ;
-; RowA[6]                                                                                     ; 1       ;
-; RA~5                                                                                        ; 1       ;
-; RowA[5]                                                                                     ; 1       ;
-; RA~4                                                                                        ; 1       ;
-; RowA[4]                                                                                     ; 1       ;
-; RA~3                                                                                        ; 1       ;
-; RowA[3]                                                                                     ; 1       ;
-; RA~2                                                                                        ; 1       ;
-; RowA[2]                                                                                     ; 1       ;
-; RA~1                                                                                        ; 1       ;
-; RowA[1]                                                                                     ; 1       ;
-; RA~0                                                                                        ; 1       ;
-; RowA[0]                                                                                     ; 1       ;
-; RBA[1]~reg0                                                                                 ; 1       ;
-; RBA[0]~reg0                                                                                 ; 1       ;
-; comb~0                                                                                      ; 1       ;
-+---------------------------------------------------------------------------------------------+---------+
-
-
-+--------------------------------------------------+
-; Other Routing Usage Summary                      ;
-+-----------------------------+--------------------+
-; Other Routing Resource Type ; Usage              ;
-+-----------------------------+--------------------+
-; C4s                         ; 162 / 784 ( 21 % ) ;
-; Direct links                ; 39 / 888 ( 4 % )   ;
-; Global clocks               ; 4 / 4 ( 100 % )    ;
-; LAB clocks                  ; 15 / 32 ( 47 % )   ;
-; LUT chains                  ; 20 / 216 ( 9 % )   ;
-; Local interconnects         ; 275 / 888 ( 31 % ) ;
-; R4s                         ; 173 / 704 ( 25 % ) ;
-+-----------------------------+--------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements                                                        ;
-+--------------------------------------------+------------------------------+
-; Number of Logic Elements  (Average = 8.00) ; Number of LABs  (Total = 21) ;
-+--------------------------------------------+------------------------------+
-; 1                                          ; 0                            ;
-; 2                                          ; 1                            ;
-; 3                                          ; 2                            ;
-; 4                                          ; 0                            ;
-; 5                                          ; 3                            ;
-; 6                                          ; 0                            ;
-; 7                                          ; 1                            ;
-; 8                                          ; 0                            ;
-; 9                                          ; 2                            ;
-; 10                                         ; 12                           ;
-+--------------------------------------------+------------------------------+
-
-
-+-------------------------------------------------------------------+
-; LAB-wide Signals                                                  ;
-+------------------------------------+------------------------------+
-; LAB-wide Signals  (Average = 1.33) ; Number of LABs  (Total = 21) ;
-+------------------------------------+------------------------------+
-; 1 Clock                            ; 12                           ;
-; 1 Clock enable                     ; 2                            ;
-; 1 Sync. clear                      ; 4                            ;
-; 1 Sync. load                       ; 1                            ;
-; 2 Clocks                           ; 9                            ;
-+------------------------------------+------------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Signals Sourced                                                        ;
-+---------------------------------------------+------------------------------+
-; Number of Signals Sourced  (Average = 8.29) ; Number of LABs  (Total = 21) ;
-+---------------------------------------------+------------------------------+
-; 0                                           ; 0                            ;
-; 1                                           ; 0                            ;
-; 2                                           ; 1                            ;
-; 3                                           ; 1                            ;
-; 4                                           ; 1                            ;
-; 5                                           ; 3                            ;
-; 6                                           ; 0                            ;
-; 7                                           ; 1                            ;
-; 8                                           ; 0                            ;
-; 9                                           ; 1                            ;
-; 10                                          ; 9                            ;
-; 11                                          ; 4                            ;
-+---------------------------------------------+------------------------------+
-
-
-+--------------------------------------------------------------------------------+
-; LAB Signals Sourced Out                                                        ;
-+-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out  (Average = 5.76) ; Number of LABs  (Total = 21) ;
-+-------------------------------------------------+------------------------------+
-; 0                                               ; 0                            ;
-; 1                                               ; 0                            ;
-; 2                                               ; 2                            ;
-; 3                                               ; 2                            ;
-; 4                                               ; 4                            ;
-; 5                                               ; 2                            ;
-; 6                                               ; 3                            ;
-; 7                                               ; 2                            ;
-; 8                                               ; 3                            ;
-; 9                                               ; 1                            ;
-; 10                                              ; 2                            ;
-+-------------------------------------------------+------------------------------+
-
-
-+-----------------------------------------------------------------------------+
-; LAB Distinct Inputs                                                         ;
-+----------------------------------------------+------------------------------+
-; Number of Distinct Inputs  (Average = 11.29) ; Number of LABs  (Total = 21) ;
-+----------------------------------------------+------------------------------+
-; 0                                            ; 0                            ;
-; 1                                            ; 0                            ;
-; 2                                            ; 0                            ;
-; 3                                            ; 2                            ;
-; 4                                            ; 0                            ;
-; 5                                            ; 0                            ;
-; 6                                            ; 2                            ;
-; 7                                            ; 1                            ;
-; 8                                            ; 0                            ;
-; 9                                            ; 1                            ;
-; 10                                           ; 2                            ;
-; 11                                           ; 2                            ;
-; 12                                           ; 4                            ;
-; 13                                           ; 1                            ;
-; 14                                           ; 1                            ;
-; 15                                           ; 1                            ;
-; 16                                           ; 2                            ;
-; 17                                           ; 0                            ;
-; 18                                           ; 0                            ;
-; 19                                           ; 1                            ;
-; 20                                           ; 1                            ;
-+----------------------------------------------+------------------------------+
-
-
-+-------------------------------------------------------------------------+
-; Fitter Device Options                                                   ;
-+----------------------------------------------+--------------------------+
-; Option                                       ; Setting                  ;
-+----------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
-; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
-; Enable device-wide output enable (DEV_OE)    ; Off                      ;
-; Enable INIT_DONE output                      ; Off                      ;
-; Configuration scheme                         ; Passive Serial           ;
-; Reserve all unused pins                      ; As output driving ground ;
-; Base pin-out file on sameframe device        ; Off                      ;
-+----------------------------------------------+--------------------------+
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary              ;
-+-----------------+----------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-; I/O             ; nCRAS                ; 1.4               ;
-+-----------------+----------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer.
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details              ;
-+-----------------+----------------------+-------------------+
-; Source Register ; Destination Register ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-; nCCAS           ; CBR                  ; 1.374             ;
-; PHI2            ; PHI2r                ; 0.176             ;
-+-----------------+----------------------+-------------------+
-Note: This table only shows the top 2 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (119006): Selected device 5M240ZT100C5 for design "RAM2GS"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
-    Info (176445): Device 5M80ZT100C5 is compatible
-    Info (176445): Device 5M80ZT100I5 is compatible
-    Info (176445): Device 5M160ZT100C5 is compatible
-    Info (176445): Device 5M160ZT100I5 is compatible
-    Info (176445): Device 5M240ZT100I5 is compatible
-    Info (176445): Device 5M570ZT100C5 is compatible
-    Info (176445): Device 5M570ZT100I5 is compatible
-Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 63 total pins
-    Info (169086): Pin LED not assigned to an exact location on the device
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
-    Info (332127): Assuming a default timing requirement
-Info (332111): Found 6 clocks
-    Info (332111):   Period   Clock Name
-    Info (332111): ======== ============
-    Info (332111):    1.000        ARCLK
-    Info (332111):    1.000        DRCLK
-    Info (332111):    1.000        nCCAS
-    Info (332111):    1.000        nCRAS
-    Info (332111):    1.000         PHI2
-    Info (332111):    1.000         RCLK
-Info (186079): Completed User Assigned Global Signals Promotion Operation
-Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12
-Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock
-    Info (186217): Destination "PHI2r" may be non-global or may not use global clock
-Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position
-Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock
-    Info (186217): Destination "comb~0" may be non-global or may not use global clock
-    Info (186217): Destination "RASr" may be non-global or may not use global clock
-Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position
-Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock
-    Info (186217): Destination "CBR" may be non-global or may not use global clock
-    Info (186217): Destination "comb~3" may be non-global or may not use global clock
-    Info (186217): Destination "CASr" may be non-global or may not use global clock
-Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position
-Info (186079): Completed Auto Global Promotion Operation
-Info (176234): Starting register packing
-Info (186391): Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
-Info (186468): Started processing fast register assignments
-Info (186469): Finished processing fast register assignments
-Info (176235): Finished register packing
-Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
-    Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
-        Info (176212): I/O standards used: 3.3-V LVTTL.
-Info (176215): I/O bank details before I/O pin placement
-    Info (176214): Statistics of I/O banks
-        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  0 pins available
-        Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used --  17 pins available
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 20% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds.
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
-Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg
-Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 548 megabytes
-    Info: Processing ended: Mon Aug 16 18:40:21 2021
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:03
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.fit.smsg.
-
-
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.fit.smsg b/CPLD-old/MAX/MAXV/output_files/RAM2GS.fit.smsg
deleted file mode 100644
index 6df10d8..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.fit.smsg
+++ /dev/null
@@ -1,4 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176244): Moving registers into LUTs to improve timing and density
-Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.fit.summary b/CPLD-old/MAX/MAXV/output_files/RAM2GS.fit.summary
deleted file mode 100644
index 9f20503..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.fit.summary
+++ /dev/null
@@ -1,11 +0,0 @@
-Fitter Status : Successful - Mon Aug 16 18:40:21 2021
-Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-Revision Name : RAM2GS
-Top-level Entity Name : RAM2GS
-Family : MAX V
-Device : 5M240ZT100C5
-Timing Models : Final
-Total logic elements : 168 / 240 ( 70 % )
-Total pins : 63 / 79 ( 80 % )
-Total virtual pins : 0
-UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.flow.rpt b/CPLD-old/MAX/MAXV/output_files/RAM2GS.flow.rpt
deleted file mode 100644
index 3bd2467..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.flow.rpt
+++ /dev/null
@@ -1,126 +0,0 @@
-Flow report for RAM2GS
-Mon Aug 16 18:40:24 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------+
-; Flow Summary                                                                ;
-+---------------------------+-------------------------------------------------+
-; Flow Status               ; Successful - Mon Aug 16 18:40:22 2021           ;
-; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name             ; RAM2GS                                          ;
-; Top-level Entity Name     ; RAM2GS                                          ;
-; Family                    ; MAX V                                           ;
-; Device                    ; 5M240ZT100C5                                    ;
-; Timing Models             ; Final                                           ;
-; Total logic elements      ; 168 / 240 ( 70 % )                              ;
-; Total pins                ; 63 / 79 ( 80 % )                                ;
-; Total virtual pins        ; 0                                               ;
-; UFM blocks                ; 1 / 1 ( 100 % )                                 ;
-+---------------------------+-------------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings                           ;
-+-------------------+---------------------+
-; Option            ; Setting             ;
-+-------------------+---------------------+
-; Start date & time ; 08/16/2021 18:40:16 ;
-; Main task         ; Compilation         ;
-; Revision Name     ; RAM2GS              ;
-+-------------------+---------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                     ;
-+--------------------------------------------+------------------------------+---------------+-------------+------------+
-; Assignment Name                            ; Value                        ; Default Value ; Entity Name ; Section Id ;
-+--------------------------------------------+------------------------------+---------------+-------------+------------+
-; ALLOW_POWER_UP_DONT_CARE                   ; Off                          ; On            ; --          ; --         ;
-; COMPILER_SIGNATURE_ID                      ; 962837114763.162915361605944 ; --            ; --          ; --         ;
-; ENABLE_BUS_HOLD_CIRCUITRY                  ; On                           ; Off           ; --          ; --         ;
-; FITTER_EFFORT                              ; Standard Fit                 ; Auto Fit      ; --          ; --         ;
-; IP_TOOL_NAME                               ; ALTUFM_NONE                  ; --            ; --          ; --         ;
-; IP_TOOL_VERSION                            ; 13.0                         ; --            ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP                     ; 85                           ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP                     ; 0                            ; --            ; --          ; --         ;
-; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers        ; Normal        ; --          ; --         ;
-; OPTIMIZE_MULTI_CORNER_TIMING               ; On                           ; Off           ; --          ; --         ;
-; PLACEMENT_EFFORT_MULTIPLIER                ; 10                           ; 1.0           ; --          ; --         ;
-; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE         ; 12.5 %                       ; 12.5%         ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY                   ; output_files                 ; --            ; --          ; --         ;
-; ROUTER_EFFORT_MULTIPLIER                   ; 10                           ; 1.0           ; --          ; --         ;
-; SAFE_STATE_MACHINE                         ; On                           ; Off           ; --          ; --         ;
-; SYNTH_TIMING_DRIVEN_SYNTHESIS              ; Off                          ; --            ; --          ; --         ;
-+--------------------------------------------+------------------------------+---------------+-------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 421 MB              ; 00:00:01                           ;
-; Fitter                    ; 00:00:03     ; 1.0                     ; 548 MB              ; 00:00:03                           ;
-; Assembler                 ; 00:00:01     ; 1.0                     ; 381 MB              ; 00:00:01                           ;
-; TimeQuest Timing Analyzer ; 00:00:01     ; 1.0                     ; 368 MB              ; 00:00:01                           ;
-; Total                     ; 00:00:06     ; --                      ; --                  ; 00:00:06                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                        ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Analysis & Synthesis      ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; Fitter                    ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; Assembler                 ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; TimeQuest Timing Analyzer ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-+---------------------------+------------------+-----------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
-quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
-quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
-quartus_sta RAM2GS-MAXV -c RAM2GS
-
-
-
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.jdi b/CPLD-old/MAX/MAXV/output_files/RAM2GS.jdi
deleted file mode 100644
index 448e697..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-  
-    
-  
-  
-    
-  
-
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.map.rpt b/CPLD-old/MAX/MAXV/output_files/RAM2GS.map.rpt
deleted file mode 100644
index ac1eb15..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.map.rpt
+++ /dev/null
@@ -1,309 +0,0 @@
-Analysis & Synthesis report for RAM2GS
-Mon Aug 16 18:40:17 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. Analysis & Synthesis IP Cores Summary
-  9. General Register Statistics
- 10. Inverted Register Statistics
- 11. Multiplexer Restructuring Statistics (Restructuring Performed)
- 12. Port Connectivity Checks: "UFM:UFM_inst"
- 13. Analysis & Synthesis Messages
- 14. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                  ;
-+-----------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon Aug 16 18:40:17 2021           ;
-; Quartus II 64-Bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name               ; RAM2GS                                          ;
-; Top-level Entity Name       ; RAM2GS                                          ;
-; Family                      ; MAX V                                           ;
-; Total logic elements        ; 177                                             ;
-; Total pins                  ; 63                                              ;
-; Total virtual pins          ; 0                                               ;
-; UFM blocks                  ; 1 / 1 ( 100 % )                                 ;
-+-----------------------------+-------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                        ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                                     ; Setting            ; Default Value      ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                                     ; 5M240ZT100C5       ;                    ;
-; Top-level entity name                                                      ; RAM2GS             ; RAM2GS             ;
-; Family name                                                                ; MAX V              ; Cyclone IV GX      ;
-; Safe State Machine                                                         ; On                 ; Off                ;
-; Power-Up Don't Care                                                        ; Off                ; On                 ;
-; Use smart compilation                                                      ; Off                ; Off                ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
-; Enable compact report table                                                ; Off                ; Off                ;
-; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
-; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
-; Preserve fewer node names                                                  ; On                 ; On                 ;
-; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
-; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
-; State Machine Processing                                                   ; Auto               ; Auto               ;
-; Extract Verilog State Machines                                             ; On                 ; On                 ;
-; Extract VHDL State Machines                                                ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
-; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
-; Parallel Synthesis                                                         ; On                 ; On                 ;
-; NOT Gate Push-Back                                                         ; On                 ; On                 ;
-; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
-; Remove Duplicate Registers                                                 ; On                 ; On                 ;
-; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
-; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
-; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
-; Optimization Technique                                                     ; Balanced           ; Balanced           ;
-; Carry Chain Length                                                         ; 70                 ; 70                 ;
-; Auto Carry Chains                                                          ; On                 ; On                 ;
-; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
-; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
-; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
-; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
-; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
-; Auto Resource Sharing                                                      ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
-; Report Parameter Settings                                                  ; On                 ; On                 ;
-; Report Source Assignments                                                  ; On                 ; On                 ;
-; Report Connectivity Checks                                                 ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
-; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
-; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
-; HDL message level                                                          ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
-; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
-; Clock MUX Protection                                                       ; On                 ; On                 ;
-; Block Design Naming                                                        ; Auto               ; Auto               ;
-; Synthesis Effort                                                           ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
-; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
-; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
-; Synthesis Seed                                                             ; 1                  ; 1                  ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 12     ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                  ;
-+----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type                   ; File Name with Absolute Path                               ; Library ;
-+----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
-; ../RAM2GS-MAX.v                  ; yes             ; User Verilog HDL File       ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v ;         ;
-; UFM.v                            ; yes             ; User Wizard-Generated File  ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v   ;         ;
-+----------------------------------+-----------------+-----------------------------+------------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary         ;
-+---------------------------------------------+-------+
-; Resource                                    ; Usage ;
-+---------------------------------------------+-------+
-; Total logic elements                        ; 177   ;
-;     -- Combinational with no register       ; 80    ;
-;     -- Register only                        ; 29    ;
-;     -- Combinational with a register        ; 68    ;
-;                                             ;       ;
-; Logic element usage by number of LUT inputs ;       ;
-;     -- 4 input functions                    ; 58    ;
-;     -- 3 input functions                    ; 40    ;
-;     -- 2 input functions                    ; 41    ;
-;     -- 1 input functions                    ; 8     ;
-;     -- 0 input functions                    ; 1     ;
-;                                             ;       ;
-; Logic elements by mode                      ;       ;
-;     -- normal mode                          ; 161   ;
-;     -- arithmetic mode                      ; 16    ;
-;     -- qfbk mode                            ; 0     ;
-;     -- register cascade mode                ; 0     ;
-;     -- synchronous clear/load mode          ; 9     ;
-;     -- asynchronous clear/load mode         ; 0     ;
-;                                             ;       ;
-; Total registers                             ; 97    ;
-; Total logic cells in carry chains           ; 17    ;
-; I/O pins                                    ; 63    ;
-; UFM blocks                                  ; 1     ;
-; Maximum fan-out node                        ; RCLK  ;
-; Maximum fan-out                             ; 55    ;
-; Total fan-out                               ; 643   ;
-; Average fan-out                             ; 2.67  ;
-+---------------------------------------------+-------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                    ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Library Name ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-; |RAM2GS                                                   ; 177 (177)   ; 97           ; 1          ; 63   ; 0            ; 80 (80)      ; 29 (29)           ; 68 (68)          ; 17 (17)         ; 0 (0)      ; |RAM2GS                                                                ; work         ;
-;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst                                                   ; work         ;
-;       |UFM_altufm_none_mjr:UFM_altufm_none_mjr_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component ; work         ;
-+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis IP Cores Summary                                                                                                           ;
-+--------+--------------+---------+--------------+--------------+----------------------+----------------------------------------------------------+
-; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File                                          ;
-+--------+--------------+---------+--------------+--------------+----------------------+----------------------------------------------------------+
-; Altera ; ALTUFM_NONE  ; 13.0    ; N/A          ; N/A          ; |RAM2GS|UFM:UFM_inst ; C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/UFM.v ;
-+--------+--------------+---------+--------------+--------------+----------------------+----------------------------------------------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 97    ;
-; Number of registers using Synchronous Clear  ; 6     ;
-; Number of registers using Synchronous Load   ; 3     ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 10    ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+--------------------------------------------------+
-; Inverted Register Statistics                     ;
-+----------------------------------------+---------+
-; Inverted Register                      ; Fan out ;
-+----------------------------------------+---------+
-; nRCS~reg0                              ; 1       ;
-; nRWE~reg0                              ; 1       ;
-; nRRAS~reg0                             ; 1       ;
-; nRCAS~reg0                             ; 1       ;
-; Total number of inverted registers = 4 ;         ;
-+----------------------------------------+---------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|S[0]               ;
-; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM2GS|ADSubmitted        ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "UFM:UFM_inst"                                                                          ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-; Port    ; Type   ; Severity ; Details                                                                             ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-; ardin   ; Input  ; Info     ; Stuck at GND                                                                        ;
-; busy    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; osc     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; rtpbusy ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 64-Bit Analysis & Synthesis
-    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Mon Aug 16 18:40:16 2021
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (12021): Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v
-    Info (12023): Found entity 1: RAM2GS
-Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
-    Info (12023): Found entity 1: UFM_altufm_none_mjr
-    Info (12023): Found entity 2: UFM
-Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
-Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2)
-Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18)
-Warning (10230): Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4)
-Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
-Info (12128): Elaborating entity "UFM_altufm_none_mjr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component"
-Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/RAM2GS-MAX.mif -- setting all initial values to 0
-Warning (18029): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated
-Warning (18029): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated
-Warning (18029): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated
-Warning (18029): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated
-Warning (18029): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated
-Warning (18029): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated
-Warning (18029): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated
-Warning (18029): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated
-Info (21057): Implemented 241 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 25 input pins
-    Info (21059): Implemented 30 output pins
-    Info (21060): Implemented 8 bidirectional pins
-    Info (21061): Implemented 177 logic cells
-    Info (21070): Implemented 1 User Flash Memory blocks
-Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg
-Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings
-    Info: Peak virtual memory: 421 megabytes
-    Info: Processing ended: Mon Aug 16 18:40:17 2021
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXV/output_files/RAM2GS.map.smsg.
-
-
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.map.smsg b/CPLD-old/MAX/MAXV/output_files/RAM2GS.map.smsg
deleted file mode 100644
index a8e8eb9..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.map.smsg
+++ /dev/null
@@ -1,3 +0,0 @@
-Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(56): extended using "x" or "z"
-Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword
-Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.map.summary b/CPLD-old/MAX/MAXV/output_files/RAM2GS.map.summary
deleted file mode 100644
index 68f556c..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.map.summary
+++ /dev/null
@@ -1,9 +0,0 @@
-Analysis & Synthesis Status : Successful - Mon Aug 16 18:40:17 2021
-Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-Revision Name : RAM2GS
-Top-level Entity Name : RAM2GS
-Family : MAX V
-Total logic elements : 177
-Total pins : 63
-Total virtual pins : 0
-UFM blocks : 1 / 1 ( 100 % )
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.pin b/CPLD-old/MAX/MAXV/output_files/RAM2GS.pin
deleted file mode 100644
index 299181b..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.pin
+++ /dev/null
@@ -1,164 +0,0 @@
- -- Copyright (C) 1991-2013 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Altera Program License 
- -- Subscription Agreement, Altera MegaCore Function License 
- -- Agreement, or other applicable license agreement, including, 
- -- without limitation, that your use is for the sole purpose of 
- -- programming logic devices manufactured by Altera and sold by 
- -- Altera or its authorized distributors.  Please refer to the 
- -- applicable agreement for further details.
- -- 
- -- This is a Quartus II output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus II input file. This file cannot be used
- -- to make Quartus II pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus II help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.8V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --					Bank 1:		3.3V
- --					Bank 2:		3.3V
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --					It can also be used to report unused dedicated pins. The connection
- --					on the board for unused dedicated pins depends on whether this will
- --					be used in a future design. One example is device migration. When
- --					using device migration, refer to the device pin-tables. If it is a
- --					GND pin in the pin table or if it will not be used in a future design
- --					for another purpose the it MUST be connected to GND. If it is an unused
- --					dedicated pin, then it can be connected to a valid signal on the board
- --					(low, high, or toggling) if that signal is required for a different
- --					revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --					This pin should be connected to GND. It may also be connected  to a
- --					valid signal  on the board  (low, high, or toggling)  if that signal
- --					is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --           	    or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-CHIP  "RAM2GS"  ASSIGNED TO AN: 5M240ZT100C5
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : 1         : gnd    :                   :         :           :                
-RDQMH                        : 2         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRCS                         : 3         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRCAS                        : 4         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RBA[0]                       : 5         : output : 3.3-V LVCMOS      :         : 1         : Y              
-nRRAS                        : 6         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[11]                       : 7         : output : 3.3-V LVCMOS      :         : 1         : Y              
-RCKE                         : 8         : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
-GND                          : 10        : gnd    :                   :         :           :                
-GND                          : 11        : gnd    :                   :         :           :                
-RCLK                         : 12        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-VCCINT                       : 13        : power  :                   : 1.8V    :           :                
-RBA[1]                       : 14        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[9]                        : 15        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[10]                       : 16        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[8]                        : 17        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[0]                        : 18        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[7]                        : 19        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[1]                        : 20        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[6]                        : 21        : output : 3.3-V LVCMOS      :         : 1         : Y              
-TMS                          : 22        : input  :                   :         : 1         :                
-TDI                          : 23        : input  :                   :         : 1         :                
-TCK                          : 24        : input  :                   :         : 1         :                
-TDO                          : 25        : output :                   :         : 1         :                
-RA[4]                        : 26        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[3]                        : 27        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[5]                      : 28        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[5]                        : 29        : output : 3.3-V LVCMOS      :         : 1         : Y              
-RA[2]                        : 30        : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
-GND                          : 32        : gnd    :                   :         :           :                
-Dout[0]                      : 33        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[6]                      : 34        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Din[2]                       : 35        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[1]                       : 36        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[3]                       : 37        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[5]                       : 38        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[4]                       : 39        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[7]                       : 40        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[6]                       : 41        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Din[0]                       : 42        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[7]                      : 43        : output : 3.3-V LVCMOS      :         : 1         : Y              
-Dout[4]                      : 44        : output : 3.3-V LVCMOS      :         : 1         : Y              
-VCCIO1                       : 45        : power  :                   : 3.3V    : 1         :                
-GND                          : 46        : gnd    :                   :         :           :                
-Dout[3]                      : 47        : output : 3.3-V LVCMOS      :         : 1         : Y              
-nFWE                         : 48        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[0]                      : 49        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[2]                      : 50        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-MAin[1]                      : 51        : input  : 3.3-V LVCMOS      :         : 1         : Y              
-PHI2                         : 52        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-nCCAS                        : 53        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-CROW[0]                      : 54        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-CROW[1]                      : 55        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-Dout[2]                      : 56        : output : 3.3-V LVCMOS      :         : 2         : Y              
-Dout[1]                      : 57        : output : 3.3-V LVCMOS      :         : 2         : Y              
-GND*                         : 58        :        :                   :         : 2         :                
-VCCIO2                       : 59        : power  :                   : 3.3V    : 2         :                
-GND                          : 60        : gnd    :                   :         :           :                
-GND*                         : 61        :        :                   :         : 2         :                
-LED                          : 62        : output : 3.3-V LVTTL       :         : 2         : N              
-VCCINT                       : 63        : power  :                   : 1.8V    :           :                
-GND*                         : 64        :        :                   :         : 2         :                
-GND                          : 65        : gnd    :                   :         :           :                
-GND*                         : 66        :        :                   :         : 2         :                
-nCRAS                        : 67        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[7]                      : 68        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[5]                      : 69        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[4]                      : 70        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[3]                      : 71        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[6]                      : 72        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[8]                      : 73        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-MAin[9]                      : 74        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-GND*                         : 75        :        :                   :         : 2         :                
-GND*                         : 76        :        :                   :         : 2         :                
-GND*                         : 77        :        :                   :         : 2         :                
-GND*                         : 78        :        :                   :         : 2         :                
-GND                          : 79        : gnd    :                   :         :           :                
-VCCIO2                       : 80        : power  :                   : 3.3V    : 2         :                
-GND*                         : 81        :        :                   :         : 2         :                
-GND*                         : 82        :        :                   :         : 2         :                
-GND*                         : 83        :        :                   :         : 2         :                
-GND*                         : 84        :        :                   :         : 2         :                
-GND*                         : 85        :        :                   :         : 2         :                
-GND*                         : 86        :        :                   :         : 2         :                
-GND*                         : 87        :        :                   :         : 2         :                
-GND*                         : 88        :        :                   :         : 2         :                
-RD[2]                        : 89        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[1]                        : 90        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[5]                        : 91        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[4]                        : 92        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-GND                          : 93        : gnd    :                   :         :           :                
-VCCIO2                       : 94        : power  :                   : 3.3V    : 2         :                
-RD[6]                        : 95        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[0]                        : 96        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RD[7]                        : 97        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-RDQML                        : 98        : output : 3.3-V LVCMOS      :         : 2         : Y              
-RD[3]                        : 99        : bidir  : 3.3-V LVCMOS      :         : 2         : Y              
-nRWE                         : 100       : output : 3.3-V LVCMOS      :         : 2         : Y              
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.pof b/CPLD-old/MAX/MAXV/output_files/RAM2GS.pof
deleted file mode 100644
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GIT binary patch
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diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.sta.rpt b/CPLD-old/MAX/MAXV/output_files/RAM2GS.sta.rpt
deleted file mode 100644
index 34ffbe8..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.sta.rpt
+++ /dev/null
@@ -1,1576 +0,0 @@
-TimeQuest Timing Analyzer report for RAM2GS
-Mon Aug 16 18:40:24 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. Clocks
-  5. Fmax Summary
-  6. Setup Summary
-  7. Hold Summary
-  8. Recovery Summary
-  9. Removal Summary
- 10. Minimum Pulse Width Summary
- 11. Setup: 'ARCLK'
- 12. Setup: 'DRCLK'
- 13. Setup: 'PHI2'
- 14. Setup: 'RCLK'
- 15. Setup: 'nCRAS'
- 16. Hold: 'ARCLK'
- 17. Hold: 'DRCLK'
- 18. Hold: 'PHI2'
- 19. Hold: 'nCRAS'
- 20. Hold: 'RCLK'
- 21. Minimum Pulse Width: 'ARCLK'
- 22. Minimum Pulse Width: 'DRCLK'
- 23. Minimum Pulse Width: 'PHI2'
- 24. Minimum Pulse Width: 'RCLK'
- 25. Minimum Pulse Width: 'nCCAS'
- 26. Minimum Pulse Width: 'nCRAS'
- 27. Setup Times
- 28. Hold Times
- 29. Clock to Output Times
- 30. Minimum Clock to Output Times
- 31. Propagation Delay
- 32. Minimum Propagation Delay
- 33. Output Enable Times
- 34. Minimum Output Enable Times
- 35. Output Disable Times
- 36. Minimum Output Disable Times
- 37. Setup Transfers
- 38. Hold Transfers
- 39. Report TCCS
- 40. Report RSKM
- 41. Unconstrained Paths
- 42. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+----------------------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                                      ;
-+--------------------+-------------------------------------------------------------------+
-; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
-; Revision Name      ; RAM2GS                                                            ;
-; Device Family      ; MAX V                                                             ;
-; Device Name        ; 5M240ZT100C5                                                      ;
-; Timing Models      ; Final                                                             ;
-; Delay Model        ; Slow Model                                                        ;
-; Rise/Fall Delays   ; Unavailable                                                       ;
-+--------------------+-------------------------------------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 12     ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                            ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets   ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-; ARCLK      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ARCLK } ;
-; DRCLK      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DRCLK } ;
-; nCCAS      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCCAS } ;
-; nCRAS      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { nCRAS } ;
-; PHI2       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { PHI2 }  ;
-; RCLK       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { RCLK }  ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
-
-
-+-------------------------------------------------+
-; Fmax Summary                                    ;
-+-----------+-----------------+------------+------+
-; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
-+-----------+-----------------+------------+------+
-; 10.0 MHz  ; 10.0 MHz        ; ARCLK      ;      ;
-; 10.0 MHz  ; 10.0 MHz        ; DRCLK      ;      ;
-; 20.71 MHz ; 20.71 MHz       ; PHI2       ;      ;
-; 47.75 MHz ; 47.75 MHz       ; RCLK       ;      ;
-+-----------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+---------------------------------+
-; Setup Summary                   ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; ARCLK ; -99.000 ; -99.000       ;
-; DRCLK ; -99.000 ; -99.000       ;
-; PHI2  ; -23.638 ; -216.621      ;
-; RCLK  ; -19.942 ; -610.547      ;
-; nCRAS ; -3.072  ; -6.479        ;
-+-------+---------+---------------+
-
-
-+---------------------------------+
-; Hold Summary                    ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; ARCLK ; -16.153 ; -16.153       ;
-; DRCLK ; -14.623 ; -14.623       ;
-; PHI2  ; -2.569  ; -3.433        ;
-; nCRAS ; -0.713  ; -2.822        ;
-; RCLK  ; 2.127   ; 0.000         ;
-+-------+---------+---------------+
-
-
---------------------
-; Recovery Summary ;
---------------------
-No paths to report.
-
-
--------------------
-; Removal Summary ;
--------------------
-No paths to report.
-
-
-+---------------------------------+
-; Minimum Pulse Width Summary     ;
-+-------+---------+---------------+
-; Clock ; Slack   ; End Point TNS ;
-+-------+---------+---------------+
-; ARCLK ; -29.500 ; -59.000       ;
-; DRCLK ; -29.500 ; -59.000       ;
-; PHI2  ; -2.289  ; -2.289        ;
-; RCLK  ; -2.289  ; -2.289        ;
-; nCCAS ; -2.289  ; -2.289        ;
-; nCRAS ; -2.289  ; -2.289        ;
-+-------+---------+---------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'ARCLK'                                                                                                                                                                                                                                                                                    ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -99.000 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 1.000        ; 0.000      ; 80.000     ;
-; -22.847 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 1.000        ; -0.884     ; 2.963      ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'DRCLK'                                                                                                                                                                                                                                                            ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -99.000 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 1.000        ; 0.000      ; 80.000     ;
-; -24.468 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 1.000        ; -0.994     ; 4.474      ;
-; -24.377 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 1.000        ; -0.994     ; 4.383      ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Setup: 'PHI2'                                                                                              ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -23.638 ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 23.817     ;
-; -23.413 ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 23.592     ;
-; -22.503 ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 22.682     ;
-; -21.937 ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 22.116     ;
-; -21.404 ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 21.583     ;
-; -21.232 ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 21.411     ;
-; -21.179 ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 21.358     ;
-; -20.812 ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.991     ;
-; -20.269 ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.448     ;
-; -20.229 ; Bank[1]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.408     ;
-; -20.229 ; Bank[1]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.408     ;
-; -20.229 ; Bank[1]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.408     ;
-; -20.229 ; Bank[1]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.408     ;
-; -20.189 ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.368     ;
-; -20.004 ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.183     ;
-; -20.004 ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.183     ;
-; -20.004 ; Bank[2]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.183     ;
-; -20.004 ; Bank[2]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 20.183     ;
-; -19.703 ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.882     ;
-; -19.309 ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.488     ;
-; -19.309 ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.488     ;
-; -19.094 ; Bank[5]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.273     ;
-; -19.094 ; Bank[5]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.273     ;
-; -19.094 ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.273     ;
-; -19.094 ; Bank[5]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.273     ;
-; -19.084 ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.263     ;
-; -19.084 ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.263     ;
-; -18.998 ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 19.177     ;
-; -18.578 ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.757     ;
-; -18.528 ; Bank[3]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.707     ;
-; -18.528 ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.707     ;
-; -18.528 ; Bank[3]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.707     ;
-; -18.528 ; Bank[3]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.707     ;
-; -18.174 ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.353     ;
-; -18.174 ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.353     ;
-; -17.993 ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.172     ;
-; -17.955 ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.134     ;
-; -17.823 ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.002     ;
-; -17.823 ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.002     ;
-; -17.823 ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.002     ;
-; -17.823 ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 18.002     ;
-; -17.608 ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.787     ;
-; -17.608 ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.787     ;
-; -17.403 ; Bank[6]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.582     ;
-; -17.403 ; Bank[6]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.582     ;
-; -17.403 ; Bank[6]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.582     ;
-; -17.403 ; Bank[6]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.582     ;
-; -16.903 ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.082     ;
-; -16.903 ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 17.082     ;
-; -16.780 ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.959     ;
-; -16.780 ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.959     ;
-; -16.780 ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.959     ;
-; -16.780 ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.959     ;
-; -16.483 ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.662     ;
-; -16.483 ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.662     ;
-; -15.860 ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.039     ;
-; -15.860 ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 16.039     ;
-; -15.759 ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 15.938     ;
-; -15.305 ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 15.484     ;
-; -15.305 ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 15.484     ;
-; -15.080 ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 15.259     ;
-; -15.080 ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 15.259     ;
-; -14.777 ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.956     ;
-; -14.584 ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.763     ;
-; -14.584 ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.763     ;
-; -14.584 ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.763     ;
-; -14.584 ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.763     ;
-; -14.552 ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.731     ;
-; -14.170 ; Bank[5]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.349     ;
-; -14.170 ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 14.349     ;
-; -13.664 ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.843     ;
-; -13.664 ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.843     ;
-; -13.642 ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.821     ;
-; -13.604 ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.783     ;
-; -13.604 ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.783     ;
-; -13.076 ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.255     ;
-; -12.899 ; Bank[7]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.078     ;
-; -12.899 ; Bank[7]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 13.078     ;
-; -12.479 ; Bank[6]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.658     ;
-; -12.479 ; Bank[6]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.658     ;
-; -12.415 ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 13.094     ;
-; -12.415 ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 13.094     ;
-; -12.415 ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 13.094     ;
-; -12.415 ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 13.094     ;
-; -12.371 ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.550     ;
-; -11.951 ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.130     ;
-; -11.942 ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 12.621     ;
-; -11.942 ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 12.621     ;
-; -11.856 ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.035     ;
-; -11.856 ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 12.035     ;
-; -11.414 ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 12.093     ;
-; -11.328 ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 11.507     ;
-; -9.660  ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.839      ;
-; -9.660  ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.839      ;
-; -9.132  ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 9.311      ;
-; -8.463  ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 9.142      ;
-; -8.261  ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 8.940      ;
-; -7.499  ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 8.178      ;
-; -6.906  ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 1.000        ; 0.000      ; 7.585      ;
-; -6.658  ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; 0.500        ; 0.000      ; 6.837      ;
-+---------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'RCLK'                                                                                                                                                                             ;
-+---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-; -19.942 ; FS[17]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 20.621     ;
-; -19.941 ; FS[17]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 20.620     ;
-; -19.634 ; FS[16]                                                                                      ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 20.313     ;
-; -19.633 ; FS[16]                                                                                      ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 20.312     ;
-; -18.886 ; FS[17]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 19.565     ;
-; -18.787 ; FS[17]                                                                                      ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 19.466     ;
-; -18.771 ; FS[7]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 19.450     ;
-; -18.770 ; FS[7]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 19.449     ;
-; -18.479 ; FS[16]                                                                                      ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 19.158     ;
-; -18.118 ; FS[16]                                                                                      ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 18.797     ;
-; -17.725 ; CmdSubmitted                                                                                ; DRCLK       ; PHI2         ; RCLK        ; 0.500        ; -6.837     ; 11.067     ;
-; -17.709 ; FWEr                                                                                        ; RCKEEN      ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 13.152     ;
-; -17.616 ; FS[7]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 18.295     ;
-; -17.380 ; FS[6]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 18.059     ;
-; -17.379 ; FS[6]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 18.058     ;
-; -17.204 ; FS[17]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.883     ;
-; -17.204 ; UFMInitDone                                                                                 ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.883     ;
-; -17.203 ; UFMInitDone                                                                                 ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.882     ;
-; -16.737 ; FS[17]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.416     ;
-; -16.735 ; FS[17]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.414     ;
-; -16.583 ; CmdSubmitted                                                                                ; DRDIn       ; PHI2         ; RCLK        ; 0.500        ; -6.837     ; 9.925      ;
-; -16.436 ; FS[16]                                                                                      ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.115     ;
-; -16.429 ; FS[16]                                                                                      ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.108     ;
-; -16.427 ; FS[16]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.106     ;
-; -16.336 ; FS[17]                                                                                      ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 17.015     ;
-; -16.318 ; FS[6]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.997     ;
-; -16.095 ; FS[12]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.774     ;
-; -16.049 ; UFMInitDone                                                                                 ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.728     ;
-; -16.028 ; FS[16]                                                                                      ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.707     ;
-; -15.980 ; CBR                                                                                         ; RCKEEN      ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 11.423     ;
-; -15.962 ; FS[5]                                                                                       ; DRShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.641     ;
-; -15.961 ; FS[5]                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.640     ;
-; -15.903 ; CmdSubmitted                                                                                ; n8MEGEN     ; PHI2         ; RCLK        ; 0.500        ; -6.837     ; 9.245      ;
-; -15.834 ; FS[7]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.513     ;
-; -15.712 ; FS[12]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.391     ;
-; -15.711 ; FWEr                                                                                        ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 11.154     ;
-; -15.707 ; FWEr                                                                                        ; nRCS~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 11.150     ;
-; -15.566 ; FS[7]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.245     ;
-; -15.564 ; FS[7]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.243     ;
-; -15.554 ; Ready                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.233     ;
-; -15.538 ; Ready                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.217     ;
-; -15.499 ; Ready                                                                                       ; IS[2]       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.178     ;
-; -15.419 ; FS[10]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 16.098     ;
-; -15.371 ; CBR                                                                                         ; nRCAS~reg0  ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 10.814     ;
-; -15.367 ; CBR                                                                                         ; nRCS~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 10.810     ;
-; -15.320 ; RASr2                                                                                       ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.999     ;
-; -15.308 ; FS[4]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.987     ;
-; -15.304 ; CmdDRCLK                                                                                    ; DRCLK       ; PHI2         ; RCLK        ; 0.500        ; -6.837     ; 8.646      ;
-; -15.236 ; S[0]                                                                                        ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.915     ;
-; -15.235 ; FS[13]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.914     ;
-; -15.165 ; FS[7]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.844     ;
-; -15.036 ; FS[10]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.715     ;
-; -14.996 ; InitReady                                                                                   ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.675     ;
-; -14.925 ; RASr2                                                                                       ; nRCS~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.604     ;
-; -14.894 ; UFMReqErase                                                                                 ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.573     ;
-; -14.868 ; FS[5]                                                                                       ; ARShift     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.547     ;
-; -14.852 ; FS[13]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.531     ;
-; -14.765 ; FS[4]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.444     ;
-; -14.728 ; FS[17]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.407     ;
-; -14.670 ; S[0]                                                                                        ; RCKEEN      ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.349     ;
-; -14.620 ; FWEr                                                                                        ; nRWE~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 10.063     ;
-; -14.568 ; S[0]                                                                                        ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.247     ;
-; -14.564 ; FS[4]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.243     ;
-; -14.562 ; FS[4]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.241     ;
-; -14.536 ; FS[6]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.215     ;
-; -14.469 ; Ready                                                                                       ; DRCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.148     ;
-; -14.469 ; S[1]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.148     ;
-; -14.420 ; FS[16]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.099     ;
-; -14.370 ; FS[11]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 15.049     ;
-; -14.285 ; S[0]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.964     ;
-; -14.280 ; CBR                                                                                         ; nRWE~reg0   ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 9.723      ;
-; -14.270 ; InitReady                                                                                   ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.949     ;
-; -14.267 ; UFMInitDone                                                                                 ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.946     ;
-; -14.182 ; Ready                                                                                       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.861     ;
-; -14.180 ; Ready                                                                                       ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.859     ;
-; -14.177 ; FS[6]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.856     ;
-; -14.175 ; FS[6]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.854     ;
-; -14.142 ; S[0]                                                                                        ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.821     ;
-; -14.059 ; S[1]                                                                                        ; RCKEEN      ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.738     ;
-; -14.045 ; InitReady                                                                                   ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.724     ;
-; -14.017 ; FS[5]                                                                                       ; ARCLK       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.696     ;
-; -13.999 ; UFMInitDone                                                                                 ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.678     ;
-; -13.997 ; UFMInitDone                                                                                 ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.676     ;
-; -13.987 ; FS[11]                                                                                      ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.666     ;
-; -13.985 ; FS[2]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.664     ;
-; -13.979 ; IS[2]                                                                                       ; Ready       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.658     ;
-; -13.957 ; S[1]                                                                                        ; nRRAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.636     ;
-; -13.920 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; n8MEGEN     ; DRCLK        ; RCLK        ; 1.000        ; 0.994      ; 15.593     ;
-; -13.911 ; RASr2                                                                                       ; RCKEEN      ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.590     ;
-; -13.902 ; InitReady                                                                                   ; nRWE~reg0   ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.581     ;
-; -13.816 ; FS[5]                                                                                       ; LEDEN       ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.495     ;
-; -13.814 ; FS[5]                                                                                       ; UFMInitDone ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.493     ;
-; -13.804 ; FWEr                                                                                        ; nRowColSel  ; nCRAS        ; RCLK        ; 0.500        ; -4.736     ; 9.247      ;
-; -13.774 ; FS[6]                                                                                       ; UFMD[15]    ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.453     ;
-; -13.771 ; FS[1]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.450     ;
-; -13.744 ; RASr2                                                                                       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.423     ;
-; -13.663 ; FS[7]                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.342     ;
-; -13.640 ; Ready                                                                                       ; n8MEGEN     ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.319     ;
-; -13.640 ; S[1]                                                                                        ; nRCAS~reg0  ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.319     ;
-; -13.631 ; FS[15]                                                                                      ; UFMReqErase ; RCLK         ; RCLK        ; 1.000        ; 0.000      ; 14.310     ;
-+---------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Setup: 'nCRAS'                                                                                         ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -3.072 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.500        ; 9.682      ; 12.933     ;
-; -2.572 ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 1.000        ; 9.682      ; 12.933     ;
-; -1.936 ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 6.851      ;
-; -1.471 ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 6.386      ;
-; 0.029  ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.886      ;
-; 0.030  ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.885      ;
-; 0.031  ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.884      ;
-; 0.033  ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.882      ;
-; 0.042  ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.873      ;
-; 0.042  ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 4.873      ;
-; 1.342  ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 3.573      ;
-; 1.343  ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 3.572      ;
-; 1.344  ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 3.571      ;
-; 1.353  ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; 0.500        ; 4.736      ; 3.562      ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'ARCLK'                                                                                                                                                                                                                                                                                     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                               ; To Node                                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -16.153 ; ARShift                                                                                                 ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK         ; ARCLK       ; 0.000        ; -0.884     ; 2.963      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK        ; ARCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'DRCLK'                                                                                                                                                                                                                                                             ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack   ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -14.623 ; DRShift                                                                                     ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -0.994     ; 4.383      ;
-; -14.532 ; DRDIn                                                                                       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; RCLK         ; DRCLK       ; 0.000        ; -0.994     ; 4.474      ;
-; 60.000  ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ; DRCLK        ; DRCLK       ; 0.000        ; 0.000      ; 80.000     ;
-+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Hold: 'PHI2'                                                                                              ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node   ; To Node      ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-; -2.569 ; n8MEGEN     ; Cmdn8MEGEN   ; RCLK         ; PHI2        ; -0.500       ; 6.837      ; 3.807      ;
-; -0.864 ; Ready       ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 6.837      ; 6.012      ;
-; -0.191 ; n8MEGEN     ; RA11         ; RCLK         ; PHI2        ; 0.000        ; 6.837      ; 6.685      ;
-; 5.284  ; UFMOscEN    ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.323      ;
-; 5.457  ; XOR8MEG     ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 5.496      ;
-; 6.515  ; C1Submitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 6.554      ;
-; 7.298  ; XOR8MEG     ; RA11         ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 6.837      ;
-; 7.546  ; ADSubmitted ; UFMOscEN     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 7.585      ;
-; 8.139  ; CmdEnable   ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 8.178      ;
-; 8.901  ; C1Submitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 8.940      ;
-; 9.103  ; ADSubmitted ; CmdEnable    ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 9.142      ;
-; 9.772  ; Bank[4]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.311      ;
-; 10.300 ; Bank[4]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.839      ;
-; 10.300 ; Bank[4]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.839      ;
-; 10.451 ; Bank[4]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.990      ;
-; 10.454 ; Bank[4]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 9.993      ;
-; 11.968 ; Bank[0]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 11.507     ;
-; 12.054 ; CmdEnable   ; XOR8MEG      ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 12.093     ;
-; 12.106 ; Bank[4]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 11.645     ;
-; 12.496 ; Bank[0]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.035     ;
-; 12.496 ; Bank[0]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.035     ;
-; 12.582 ; CmdEnable   ; CmdSubmitted ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 12.621     ;
-; 12.582 ; CmdEnable   ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 12.621     ;
-; 12.591 ; Bank[6]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.130     ;
-; 12.647 ; Bank[0]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.186     ;
-; 12.650 ; Bank[0]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.189     ;
-; 13.011 ; Bank[7]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.550     ;
-; 13.055 ; CmdEnable   ; CmdUFMPrgm   ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 13.094     ;
-; 13.055 ; CmdEnable   ; CmdUFMErase  ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 13.094     ;
-; 13.055 ; CmdEnable   ; CmdDRDIn     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 13.094     ;
-; 13.055 ; CmdEnable   ; CmdDRCLK     ; PHI2         ; PHI2        ; 0.000        ; 0.000      ; 13.094     ;
-; 13.119 ; Bank[6]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.658     ;
-; 13.119 ; Bank[6]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.658     ;
-; 13.270 ; Bank[6]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.809     ;
-; 13.273 ; Bank[6]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 12.812     ;
-; 13.539 ; Bank[7]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.078     ;
-; 13.539 ; Bank[7]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.078     ;
-; 13.663 ; Bank[4]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.202     ;
-; 13.690 ; Bank[7]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.229     ;
-; 13.693 ; Bank[7]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.232     ;
-; 13.716 ; Bank[3]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.255     ;
-; 14.244 ; Bank[3]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.783     ;
-; 14.244 ; Bank[3]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.783     ;
-; 14.282 ; Bank[5]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.821     ;
-; 14.302 ; Bank[0]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.841     ;
-; 14.395 ; Bank[3]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.934     ;
-; 14.398 ; Bank[3]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 13.937     ;
-; 14.810 ; Bank[5]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.349     ;
-; 14.810 ; Bank[5]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.349     ;
-; 14.925 ; Bank[6]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.464     ;
-; 14.961 ; Bank[5]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.500     ;
-; 14.964 ; Bank[5]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.503     ;
-; 15.192 ; Bank[2]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.731     ;
-; 15.224 ; Bank[4]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.763     ;
-; 15.224 ; Bank[4]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.763     ;
-; 15.224 ; Bank[4]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.763     ;
-; 15.224 ; Bank[4]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.763     ;
-; 15.345 ; Bank[7]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.884     ;
-; 15.417 ; Bank[1]     ; XOR8MEG      ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 14.956     ;
-; 15.720 ; Bank[2]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.259     ;
-; 15.720 ; Bank[2]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.259     ;
-; 15.859 ; Bank[0]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.398     ;
-; 15.871 ; Bank[2]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.410     ;
-; 15.874 ; Bank[2]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.413     ;
-; 15.945 ; Bank[1]     ; CmdSubmitted ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.484     ;
-; 15.945 ; Bank[1]     ; Cmdn8MEGEN   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.484     ;
-; 16.050 ; Bank[3]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.589     ;
-; 16.096 ; Bank[1]     ; ADSubmitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.635     ;
-; 16.099 ; Bank[1]     ; C1Submitted  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 15.638     ;
-; 16.482 ; Bank[6]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.021     ;
-; 16.616 ; Bank[5]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.155     ;
-; 16.902 ; Bank[7]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.441     ;
-; 17.420 ; Bank[0]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.959     ;
-; 17.420 ; Bank[0]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.959     ;
-; 17.420 ; Bank[0]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.959     ;
-; 17.420 ; Bank[0]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 16.959     ;
-; 17.526 ; Bank[2]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.065     ;
-; 17.607 ; Bank[3]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.146     ;
-; 17.751 ; Bank[1]     ; UFMOscEN     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.290     ;
-; 18.043 ; Bank[6]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.582     ;
-; 18.043 ; Bank[6]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.582     ;
-; 18.043 ; Bank[6]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.582     ;
-; 18.043 ; Bank[6]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.582     ;
-; 18.173 ; Bank[5]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 17.712     ;
-; 18.463 ; Bank[7]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.002     ;
-; 18.463 ; Bank[7]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.002     ;
-; 18.463 ; Bank[7]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.002     ;
-; 18.463 ; Bank[7]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.002     ;
-; 19.083 ; Bank[2]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.622     ;
-; 19.168 ; Bank[3]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.707     ;
-; 19.168 ; Bank[3]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.707     ;
-; 19.168 ; Bank[3]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.707     ;
-; 19.168 ; Bank[3]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.707     ;
-; 19.308 ; Bank[1]     ; CmdEnable    ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 18.847     ;
-; 19.734 ; Bank[5]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 19.273     ;
-; 19.734 ; Bank[5]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 19.273     ;
-; 19.734 ; Bank[5]     ; CmdDRDIn     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 19.273     ;
-; 19.734 ; Bank[5]     ; CmdDRCLK     ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 19.273     ;
-; 20.644 ; Bank[2]     ; CmdUFMPrgm   ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 20.183     ;
-; 20.644 ; Bank[2]     ; CmdUFMErase  ; PHI2         ; PHI2        ; -0.500       ; 0.000      ; 20.183     ;
-+--------+-------------+--------------+--------------+-------------+--------------+------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Hold: 'nCRAS'                                                                                          ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack  ; From Node ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -0.713 ; Ready     ; RowA[1]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 3.562      ;
-; -0.704 ; Ready     ; RowA[9]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 3.571      ;
-; -0.703 ; Ready     ; RowA[6]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 3.572      ;
-; -0.702 ; Ready     ; RowA[0]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 3.573      ;
-; 0.598  ; Ready     ; RowA[2]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.873      ;
-; 0.598  ; Ready     ; RowA[7]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.873      ;
-; 0.607  ; Ready     ; RowA[4]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.882      ;
-; 0.609  ; Ready     ; RowA[3]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.884      ;
-; 0.610  ; Ready     ; RBA[1]~reg0 ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.885      ;
-; 0.611  ; Ready     ; RowA[8]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 4.886      ;
-; 2.111  ; Ready     ; RBA[0]~reg0 ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 6.386      ;
-; 2.576  ; Ready     ; RowA[5]     ; RCLK         ; nCRAS       ; -0.500       ; 4.736      ; 6.851      ;
-; 3.212  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; 0.000        ; 9.682      ; 12.933     ;
-; 3.712  ; nCCAS     ; CBR         ; nCCAS        ; nCRAS       ; -0.500       ; 9.682      ; 12.933     ;
-+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Hold: 'RCLK'                                                                                            ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; 2.127 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; 0.000        ; 4.946      ; 7.112      ;
-; 2.325 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; 0.000        ; 4.946      ; 7.310      ;
-; 2.627 ; PHI2        ; PHI2r       ; PHI2         ; RCLK        ; -0.500       ; 4.946      ; 7.112      ;
-; 2.825 ; nCCAS       ; CASr        ; nCCAS        ; RCLK        ; -0.500       ; 4.946      ; 7.310      ;
-; 3.362 ; FS[17]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.401      ;
-; 3.382 ; IS[3]       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.421      ;
-; 3.813 ; S[0]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.852      ;
-; 3.827 ; S[0]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.866      ;
-; 3.902 ; IS[1]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 3.941      ;
-; 3.997 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; 0.000        ; 4.946      ; 8.982      ;
-; 4.411 ; CASr2       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.450      ;
-; 4.478 ; FS[0]       ; FS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.517      ;
-; 4.497 ; nCRAS       ; RASr        ; nCRAS        ; RCLK        ; -0.500       ; 4.946      ; 8.982      ;
-; 4.580 ; IS[0]       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.619      ;
-; 4.581 ; IS[0]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 4.620      ;
-; 5.217 ; FS[6]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.256      ;
-; 5.228 ; FS[10]      ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.267      ;
-; 5.228 ; FS[9]       ; FS[9]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.267      ;
-; 5.229 ; FS[16]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.268      ;
-; 5.229 ; UFMReqErase ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.268      ;
-; 5.229 ; FS[11]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.268      ;
-; 5.241 ; FS[8]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.280      ;
-; 5.244 ; RCKEEN      ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.283      ;
-; 5.254 ; FS[1]       ; FS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.293      ;
-; 5.269 ; UFMInitDone ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.308      ;
-; 5.275 ; UFMErase    ; UFMErase    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.314      ;
-; 5.335 ; S[1]        ; S[1]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.374      ;
-; 5.337 ; S[1]        ; S[0]        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.376      ;
-; 5.392 ; PHI2r2      ; DRDIn       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.431      ;
-; 5.431 ; FS[12]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.470      ;
-; 5.440 ; FS[7]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.479      ;
-; 5.440 ; FS[14]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.479      ;
-; 5.441 ; FS[15]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.480      ;
-; 5.441 ; FS[13]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.480      ;
-; 5.444 ; RASr3       ; RCKE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.483      ;
-; 5.444 ; n8MEGEN     ; n8MEGEN     ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.483      ;
-; 5.452 ; FS[5]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.491      ;
-; 5.452 ; FS[4]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.491      ;
-; 5.454 ; FS[2]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.493      ;
-; 5.466 ; FS[3]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.505      ;
-; 5.498 ; CASr2       ; nRCS~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.537      ;
-; 5.502 ; CASr2       ; nRCAS~reg0  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.541      ;
-; 5.521 ; UFMD[15]    ; UFMD[15]    ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.560      ;
-; 5.523 ; UFMD[15]    ; UFMInitDone ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.562      ;
-; 5.524 ; UFMD[15]    ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.563      ;
-; 5.525 ; UFMD[15]    ; LEDEN       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.564      ;
-; 5.551 ; IS[0]       ; IS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.590      ;
-; 5.564 ; IS[1]       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.603      ;
-; 5.595 ; Ready       ; Ready       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.634      ;
-; 5.690 ; RCKEEN      ; RCKEEN      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.729      ;
-; 5.715 ; nRowColSel  ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.754      ;
-; 5.717 ; RASr2       ; IS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.756      ;
-; 5.730 ; RASr2       ; IS[0]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.769      ;
-; 5.730 ; RASr2       ; IS[1]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.769      ;
-; 5.952 ; FS[6]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 5.991      ;
-; 5.963 ; FS[9]       ; FS[10]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.002      ;
-; 5.963 ; FS[10]      ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.002      ;
-; 5.964 ; FS[16]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.003      ;
-; 5.964 ; FS[11]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.003      ;
-; 5.969 ; CASr3       ; nRowColSel  ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.008      ;
-; 5.989 ; FS[1]       ; FS[2]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.028      ;
-; 6.025 ; Ready       ; UFMReqErase ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.064      ;
-; 6.096 ; FS[6]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.135      ;
-; 6.107 ; FS[9]       ; FS[11]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.146      ;
-; 6.107 ; FS[10]      ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.146      ;
-; 6.108 ; FS[11]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.147      ;
-; 6.113 ; RASr        ; RASr2       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.152      ;
-; 6.133 ; FS[1]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.172      ;
-; 6.173 ; PHI2r2      ; PHI2r3      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.212      ;
-; 6.251 ; FS[9]       ; FS[12]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.290      ;
-; 6.251 ; FS[10]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.290      ;
-; 6.334 ; LEDEN       ; LEDEN       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.373      ;
-; 6.395 ; FS[9]       ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.434      ;
-; 6.433 ; FS[12]      ; FS[13]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.472      ;
-; 6.442 ; FS[14]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.481      ;
-; 6.442 ; FS[7]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.481      ;
-; 6.443 ; FS[15]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.482      ;
-; 6.454 ; FS[5]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.493      ;
-; 6.454 ; FS[4]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.493      ;
-; 6.456 ; FS[2]       ; FS[3]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.495      ;
-; 6.534 ; PHI2r2      ; DRCLK       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.573      ;
-; 6.560 ; IS[3]       ; RA10        ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.599      ;
-; 6.586 ; FS[14]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.625      ;
-; 6.587 ; FS[15]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.626      ;
-; 6.595 ; PHI2r       ; PHI2r2      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.634      ;
-; 6.598 ; FS[5]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.637      ;
-; 6.598 ; FS[4]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.637      ;
-; 6.730 ; FS[14]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.769      ;
-; 6.742 ; FS[5]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.781      ;
-; 6.742 ; FS[4]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.781      ;
-; 6.744 ; FS[11]      ; FS[17]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.783      ;
-; 6.744 ; FS[11]      ; FS[16]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.783      ;
-; 6.744 ; FS[11]      ; FS[15]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.783      ;
-; 6.744 ; FS[11]      ; FS[14]      ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.783      ;
-; 6.769 ; FS[1]       ; FS[6]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.808      ;
-; 6.769 ; FS[1]       ; FS[5]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.808      ;
-; 6.769 ; FS[1]       ; FS[7]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.808      ;
-; 6.769 ; FS[1]       ; FS[4]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.808      ;
-; 6.769 ; FS[1]       ; FS[8]       ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.808      ;
-; 6.785 ; CASr3       ; nRWE~reg0   ; RCLK         ; RCLK        ; 0.000        ; 0.000      ; 6.824      ;
-+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'ARCLK'                                                                                                                                                              ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
-; Slack   ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                                                                  ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
-; -29.500 ; 0.500        ; 30.000         ; High Pulse Width ; ARCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
-; -29.500 ; 0.500        ; 30.000         ; Low Pulse Width  ; ARCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; ARCLK ; Rise       ; ARCLK|regout                                                                                            ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; ARCLK ; Rise       ; ARCLK|regout                                                                                            ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; ARCLK ; Rise       ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|arclk                                           ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; ARCLK ; Rise       ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|arclk                                           ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'DRCLK'                                                                                                                                                  ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
-; Slack   ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                                                                      ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
-; -29.500 ; 0.500        ; 30.000         ; High Pulse Width ; DRCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ;
-; -29.500 ; 0.500        ; 30.000         ; Low Pulse Width  ; DRCLK ; Rise       ; UFM:UFM_inst|UFM_altufm_none_mjr:UFM_altufm_none_mjr_component|wire_maxii_ufm_block1_drdout ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; DRCLK ; Rise       ; DRCLK|regout                                                                                ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; DRCLK ; Rise       ; DRCLK|regout                                                                                ;
-; 0.500   ; 0.500        ; 0.000          ; High Pulse Width ; DRCLK ; Rise       ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|drclk                               ;
-; 0.500   ; 0.500        ; 0.000          ; Low Pulse Width  ; DRCLK ; Rise       ; UFM_inst|UFM_altufm_none_mjr_component|maxii_ufm_block1|drclk                               ;
-+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'PHI2'                                                                       ;
-+--------+--------------+----------------+------------------+-------+------------+------------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target           ;
-+--------+--------------+----------------+------------------+-------+------------+------------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; PHI2  ; Rise       ; PHI2             ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; ADSubmitted      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; ADSubmitted      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[0]          ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[0]          ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[1]          ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[1]          ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[2]          ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[2]          ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[3]          ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[3]          ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[4]          ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[4]          ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[5]          ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[5]          ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[6]          ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[6]          ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; Bank[7]          ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[7]          ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; C1Submitted      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; C1Submitted      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdDRCLK         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdDRCLK         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdDRDIn         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdDRDIn         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdEnable        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdEnable        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdSubmitted     ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdSubmitted     ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdUFMErase      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdUFMErase      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; CmdUFMPrgm       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; CmdUFMPrgm       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; Cmdn8MEGEN       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; Cmdn8MEGEN       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Rise       ; RA11             ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Rise       ; RA11             ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; UFMOscEN         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; UFMOscEN         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; PHI2  ; Fall       ; XOR8MEG          ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; PHI2  ; Fall       ; XOR8MEG          ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; ADSubmitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; ADSubmitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[0]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[0]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[1]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[1]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[2]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[2]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[3]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[3]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[4]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[4]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[5]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[5]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[6]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[6]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Bank[7]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Bank[7]|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; C1Submitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; C1Submitted|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdDRCLK|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdDRCLK|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdDRDIn|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdDRDIn|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdEnable|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdEnable|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdSubmitted|clk ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdSubmitted|clk ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdUFMErase|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdUFMErase|clk  ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; CmdUFMPrgm|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; CmdUFMPrgm|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; Cmdn8MEGEN|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; Cmdn8MEGEN|clk   ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; PHI2|combout     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; PHI2|combout     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; RA11|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; RA11|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; UFMOscEN|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; UFMOscEN|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; PHI2  ; Rise       ; XOR8MEG|clk      ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; PHI2  ; Rise       ; XOR8MEG|clk      ;
-+--------+--------------+----------------+------------------+-------+------------+------------------+
-
-
-+----------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'RCLK'                                                                  ;
-+--------+--------------+----------------+------------------+-------+------------+-------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target      ;
-+--------+--------------+----------------+------------------+-------+------------+-------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; RCLK  ; Rise       ; RCLK        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; ARCLK       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; ARCLK       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; ARShift     ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; ARShift     ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; CASr        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; CASr2       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr2       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; CASr3       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; CASr3       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; DRCLK       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; DRCLK       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; DRDIn       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; DRDIn       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; DRShift     ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; DRShift     ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[0]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[0]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[10]      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[10]      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[11]      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[11]      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[12]      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[12]      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[13]      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[13]      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[14]      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[14]      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[15]      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[15]      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[16]      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[16]      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[17]      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[17]      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[1]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[1]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[2]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[2]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[3]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[3]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[4]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[4]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[5]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[5]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[6]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[6]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[7]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[7]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[8]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[8]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; FS[9]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; FS[9]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; IS[0]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[0]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; IS[1]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[1]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; IS[2]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[2]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; IS[3]       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; IS[3]       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; InitReady   ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; InitReady   ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; LEDEN       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; LEDEN       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r2      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r2      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; PHI2r3      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; PHI2r3      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RA10        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RA10        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RASr        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RASr2       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr2       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RASr3       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RASr3       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RCKEEN      ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RCKEEN      ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; RCKE~reg0   ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; RCKE~reg0   ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; Ready       ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; Ready       ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; S[0]        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; S[0]        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; S[1]        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; S[1]        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; UFMD[15]    ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMD[15]    ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; UFMErase    ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMErase    ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; UFMInitDone ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMInitDone ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; UFMProgram  ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMProgram  ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; UFMReqErase ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; RCLK  ; Rise       ; UFMReqErase ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; RCLK  ; Rise       ; n8MEGEN     ;
-+--------+--------------+----------------+------------------+-------+------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'nCCAS'                                                                   ;
-+--------+--------------+----------------+------------------+-------+------------+---------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target        ;
-+--------+--------------+----------------+------------------+-------+------------+---------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; nCCAS ; Rise       ; nCCAS         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[0]        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[0]        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[1]        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[1]        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[2]        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[2]        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[3]        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[3]        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[4]        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[4]        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[5]        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[5]        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[6]        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[6]        ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCCAS ; Fall       ; WRD[7]        ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCCAS ; Fall       ; WRD[7]        ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[0]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[0]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[1]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[1]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[2]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[2]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[3]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[3]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[4]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[4]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[5]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[5]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[6]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[6]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; WRD[7]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; WRD[7]|clk    ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCCAS ; Rise       ; nCCAS|combout ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCCAS ; Rise       ; nCCAS|combout ;
-+--------+--------------+----------------+------------------+-------+------------+---------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'nCRAS'                                                                     ;
-+--------+--------------+----------------+------------------+-------+------------+-----------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target          ;
-+--------+--------------+----------------+------------------+-------+------------+-----------------+
-; -2.289 ; 1.000        ; 3.289          ; Port Rate        ; nCRAS ; Rise       ; nCRAS           ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; CBR             ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; CBR             ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; FWEr            ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; FWEr            ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RBA[0]~reg0     ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RBA[0]~reg0     ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RBA[1]~reg0     ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RBA[1]~reg0     ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[0]         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[0]         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[1]         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[1]         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[2]         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[2]         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[3]         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[3]         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[4]         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[4]         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[5]         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[5]         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[6]         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[6]         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[7]         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[7]         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[8]         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[8]         ;
-; 0.161  ; 0.500        ; 0.339          ; High Pulse Width ; nCRAS ; Fall       ; RowA[9]         ;
-; 0.161  ; 0.500        ; 0.339          ; Low Pulse Width  ; nCRAS ; Fall       ; RowA[9]         ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; CBR|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; CBR|clk         ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; FWEr|clk        ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; FWEr|clk        ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RBA[0]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RBA[0]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RBA[1]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RBA[1]~reg0|clk ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[0]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[0]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[1]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[1]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[2]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[2]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[3]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[3]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[4]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[4]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[5]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[5]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[6]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[6]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[7]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[7]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[8]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[8]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; RowA[9]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; RowA[9]|clk     ;
-; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; nCRAS ; Rise       ; nCRAS|combout   ;
-; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; nCRAS ; Rise       ; nCRAS|combout   ;
-+--------+--------------+----------------+------------------+-------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Setup Times                                                             ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Din[*]    ; PHI2       ; 5.619  ; 5.619  ; Rise       ; PHI2            ;
-;  Din[0]   ; PHI2       ; 1.618  ; 1.618  ; Rise       ; PHI2            ;
-;  Din[1]   ; PHI2       ; 1.922  ; 1.922  ; Rise       ; PHI2            ;
-;  Din[2]   ; PHI2       ; 3.930  ; 3.930  ; Rise       ; PHI2            ;
-;  Din[3]   ; PHI2       ; 1.790  ; 1.790  ; Rise       ; PHI2            ;
-;  Din[4]   ; PHI2       ; 5.619  ; 5.619  ; Rise       ; PHI2            ;
-;  Din[5]   ; PHI2       ; 1.892  ; 1.892  ; Rise       ; PHI2            ;
-;  Din[6]   ; PHI2       ; 0.488  ; 0.488  ; Rise       ; PHI2            ;
-;  Din[7]   ; PHI2       ; -1.895 ; -1.895 ; Rise       ; PHI2            ;
-; Din[*]    ; PHI2       ; 18.851 ; 18.851 ; Fall       ; PHI2            ;
-;  Din[0]   ; PHI2       ; 15.527 ; 15.527 ; Fall       ; PHI2            ;
-;  Din[1]   ; PHI2       ; 18.391 ; 18.391 ; Fall       ; PHI2            ;
-;  Din[2]   ; PHI2       ; 18.150 ; 18.150 ; Fall       ; PHI2            ;
-;  Din[3]   ; PHI2       ; 18.836 ; 18.836 ; Fall       ; PHI2            ;
-;  Din[4]   ; PHI2       ; 18.731 ; 18.731 ; Fall       ; PHI2            ;
-;  Din[5]   ; PHI2       ; 18.851 ; 18.851 ; Fall       ; PHI2            ;
-;  Din[6]   ; PHI2       ; 16.140 ; 16.140 ; Fall       ; PHI2            ;
-;  Din[7]   ; PHI2       ; 17.790 ; 17.790 ; Fall       ; PHI2            ;
-; MAin[*]   ; PHI2       ; 27.296 ; 27.296 ; Fall       ; PHI2            ;
-;  MAin[0]  ; PHI2       ; 18.855 ; 18.855 ; Fall       ; PHI2            ;
-;  MAin[1]  ; PHI2       ; 17.223 ; 17.223 ; Fall       ; PHI2            ;
-;  MAin[2]  ; PHI2       ; 22.057 ; 22.057 ; Fall       ; PHI2            ;
-;  MAin[3]  ; PHI2       ; 26.915 ; 26.915 ; Fall       ; PHI2            ;
-;  MAin[4]  ; PHI2       ; 22.048 ; 22.048 ; Fall       ; PHI2            ;
-;  MAin[5]  ; PHI2       ; 27.296 ; 27.296 ; Fall       ; PHI2            ;
-;  MAin[6]  ; PHI2       ; 23.411 ; 23.411 ; Fall       ; PHI2            ;
-;  MAin[7]  ; PHI2       ; 26.379 ; 26.379 ; Fall       ; PHI2            ;
-; nFWE      ; PHI2       ; 15.594 ; 15.594 ; Fall       ; PHI2            ;
-; PHI2      ; RCLK       ; 2.487  ; 2.487  ; Rise       ; RCLK            ;
-; nCCAS     ; RCLK       ; 2.685  ; 2.685  ; Rise       ; RCLK            ;
-; nCRAS     ; RCLK       ; 4.357  ; 4.357  ; Rise       ; RCLK            ;
-; Din[*]    ; nCCAS      ; 0.702  ; 0.702  ; Fall       ; nCCAS           ;
-;  Din[0]   ; nCCAS      ; -0.028 ; -0.028 ; Fall       ; nCCAS           ;
-;  Din[1]   ; nCCAS      ; -1.852 ; -1.852 ; Fall       ; nCCAS           ;
-;  Din[2]   ; nCCAS      ; -1.623 ; -1.623 ; Fall       ; nCCAS           ;
-;  Din[3]   ; nCCAS      ; -1.611 ; -1.611 ; Fall       ; nCCAS           ;
-;  Din[4]   ; nCCAS      ; -1.202 ; -1.202 ; Fall       ; nCCAS           ;
-;  Din[5]   ; nCCAS      ; -1.860 ; -1.860 ; Fall       ; nCCAS           ;
-;  Din[6]   ; nCCAS      ; 0.702  ; 0.702  ; Fall       ; nCCAS           ;
-;  Din[7]   ; nCCAS      ; -1.657 ; -1.657 ; Fall       ; nCCAS           ;
-; CROW[*]   ; nCRAS      ; 5.538  ; 5.538  ; Fall       ; nCRAS           ;
-;  CROW[0]  ; nCRAS      ; 5.538  ; 5.538  ; Fall       ; nCRAS           ;
-;  CROW[1]  ; nCRAS      ; 3.990  ; 3.990  ; Fall       ; nCRAS           ;
-; MAin[*]   ; nCRAS      ; 5.521  ; 5.521  ; Fall       ; nCRAS           ;
-;  MAin[0]  ; nCRAS      ; 2.776  ; 2.776  ; Fall       ; nCRAS           ;
-;  MAin[1]  ; nCRAS      ; 2.635  ; 2.635  ; Fall       ; nCRAS           ;
-;  MAin[2]  ; nCRAS      ; 2.575  ; 2.575  ; Fall       ; nCRAS           ;
-;  MAin[3]  ; nCRAS      ; 1.972  ; 1.972  ; Fall       ; nCRAS           ;
-;  MAin[4]  ; nCRAS      ; 3.637  ; 3.637  ; Fall       ; nCRAS           ;
-;  MAin[5]  ; nCRAS      ; 4.180  ; 4.180  ; Fall       ; nCRAS           ;
-;  MAin[6]  ; nCRAS      ; 2.129  ; 2.129  ; Fall       ; nCRAS           ;
-;  MAin[7]  ; nCRAS      ; 5.521  ; 5.521  ; Fall       ; nCRAS           ;
-;  MAin[8]  ; nCRAS      ; 3.654  ; 3.654  ; Fall       ; nCRAS           ;
-;  MAin[9]  ; nCRAS      ; 2.363  ; 2.363  ; Fall       ; nCRAS           ;
-; nCCAS     ; nCRAS      ; 3.572  ; 3.572  ; Fall       ; nCRAS           ;
-; nFWE      ; nCRAS      ; 2.828  ; 2.828  ; Fall       ; nCRAS           ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+---------------------------------------------------------------------------+
-; Hold Times                                                                ;
-+-----------+------------+---------+---------+------------+-----------------+
-; Data Port ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference ;
-+-----------+------------+---------+---------+------------+-----------------+
-; Din[*]    ; PHI2       ; 2.255   ; 2.255   ; Rise       ; PHI2            ;
-;  Din[0]   ; PHI2       ; -1.258  ; -1.258  ; Rise       ; PHI2            ;
-;  Din[1]   ; PHI2       ; -1.562  ; -1.562  ; Rise       ; PHI2            ;
-;  Din[2]   ; PHI2       ; -3.570  ; -3.570  ; Rise       ; PHI2            ;
-;  Din[3]   ; PHI2       ; -1.430  ; -1.430  ; Rise       ; PHI2            ;
-;  Din[4]   ; PHI2       ; -5.259  ; -5.259  ; Rise       ; PHI2            ;
-;  Din[5]   ; PHI2       ; -1.532  ; -1.532  ; Rise       ; PHI2            ;
-;  Din[6]   ; PHI2       ; 0.023   ; 0.023   ; Rise       ; PHI2            ;
-;  Din[7]   ; PHI2       ; 2.255   ; 2.255   ; Rise       ; PHI2            ;
-; Din[*]    ; PHI2       ; 1.977   ; 1.977   ; Fall       ; PHI2            ;
-;  Din[0]   ; PHI2       ; 1.489   ; 1.489   ; Fall       ; PHI2            ;
-;  Din[1]   ; PHI2       ; 1.963   ; 1.963   ; Fall       ; PHI2            ;
-;  Din[2]   ; PHI2       ; 0.106   ; 0.106   ; Fall       ; PHI2            ;
-;  Din[3]   ; PHI2       ; -0.228  ; -0.228  ; Fall       ; PHI2            ;
-;  Din[4]   ; PHI2       ; 1.977   ; 1.977   ; Fall       ; PHI2            ;
-;  Din[5]   ; PHI2       ; -5.179  ; -5.179  ; Fall       ; PHI2            ;
-;  Din[6]   ; PHI2       ; -4.432  ; -4.432  ; Fall       ; PHI2            ;
-;  Din[7]   ; PHI2       ; -6.067  ; -6.067  ; Fall       ; PHI2            ;
-; MAin[*]   ; PHI2       ; -1.458  ; -1.458  ; Fall       ; PHI2            ;
-;  MAin[0]  ; PHI2       ; -3.579  ; -3.579  ; Fall       ; PHI2            ;
-;  MAin[1]  ; PHI2       ; -1.458  ; -1.458  ; Fall       ; PHI2            ;
-;  MAin[2]  ; PHI2       ; -10.193 ; -10.193 ; Fall       ; PHI2            ;
-;  MAin[3]  ; PHI2       ; -15.051 ; -15.051 ; Fall       ; PHI2            ;
-;  MAin[4]  ; PHI2       ; -10.184 ; -10.184 ; Fall       ; PHI2            ;
-;  MAin[5]  ; PHI2       ; -15.432 ; -15.432 ; Fall       ; PHI2            ;
-;  MAin[6]  ; PHI2       ; -10.945 ; -10.945 ; Fall       ; PHI2            ;
-;  MAin[7]  ; PHI2       ; -11.673 ; -11.673 ; Fall       ; PHI2            ;
-; nFWE      ; PHI2       ; -6.373  ; -6.373  ; Fall       ; PHI2            ;
-; PHI2      ; RCLK       ; -2.127  ; -2.127  ; Rise       ; RCLK            ;
-; nCCAS     ; RCLK       ; -2.325  ; -2.325  ; Rise       ; RCLK            ;
-; nCRAS     ; RCLK       ; -3.997  ; -3.997  ; Rise       ; RCLK            ;
-; Din[*]    ; nCCAS      ; 2.220   ; 2.220   ; Fall       ; nCCAS           ;
-;  Din[0]   ; nCCAS      ; 0.388   ; 0.388   ; Fall       ; nCCAS           ;
-;  Din[1]   ; nCCAS      ; 2.212   ; 2.212   ; Fall       ; nCCAS           ;
-;  Din[2]   ; nCCAS      ; 1.983   ; 1.983   ; Fall       ; nCCAS           ;
-;  Din[3]   ; nCCAS      ; 1.971   ; 1.971   ; Fall       ; nCCAS           ;
-;  Din[4]   ; nCCAS      ; 1.562   ; 1.562   ; Fall       ; nCCAS           ;
-;  Din[5]   ; nCCAS      ; 2.220   ; 2.220   ; Fall       ; nCCAS           ;
-;  Din[6]   ; nCCAS      ; -0.342  ; -0.342  ; Fall       ; nCCAS           ;
-;  Din[7]   ; nCCAS      ; 2.017   ; 2.017   ; Fall       ; nCCAS           ;
-; CROW[*]   ; nCRAS      ; -3.630  ; -3.630  ; Fall       ; nCRAS           ;
-;  CROW[0]  ; nCRAS      ; -5.178  ; -5.178  ; Fall       ; nCRAS           ;
-;  CROW[1]  ; nCRAS      ; -3.630  ; -3.630  ; Fall       ; nCRAS           ;
-; MAin[*]   ; nCRAS      ; -1.612  ; -1.612  ; Fall       ; nCRAS           ;
-;  MAin[0]  ; nCRAS      ; -2.416  ; -2.416  ; Fall       ; nCRAS           ;
-;  MAin[1]  ; nCRAS      ; -2.275  ; -2.275  ; Fall       ; nCRAS           ;
-;  MAin[2]  ; nCRAS      ; -2.215  ; -2.215  ; Fall       ; nCRAS           ;
-;  MAin[3]  ; nCRAS      ; -1.612  ; -1.612  ; Fall       ; nCRAS           ;
-;  MAin[4]  ; nCRAS      ; -3.277  ; -3.277  ; Fall       ; nCRAS           ;
-;  MAin[5]  ; nCRAS      ; -3.820  ; -3.820  ; Fall       ; nCRAS           ;
-;  MAin[6]  ; nCRAS      ; -1.769  ; -1.769  ; Fall       ; nCRAS           ;
-;  MAin[7]  ; nCRAS      ; -5.161  ; -5.161  ; Fall       ; nCRAS           ;
-;  MAin[8]  ; nCRAS      ; -3.294  ; -3.294  ; Fall       ; nCRAS           ;
-;  MAin[9]  ; nCRAS      ; -2.003  ; -2.003  ; Fall       ; nCRAS           ;
-; nCCAS     ; nCRAS      ; -3.212  ; -3.212  ; Fall       ; nCRAS           ;
-; nFWE      ; nCRAS      ; -2.468  ; -2.468  ; Fall       ; nCRAS           ;
-+-----------+------------+---------+---------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Clock to Output Times                                                   ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; RA[*]     ; PHI2       ; 24.450 ; 24.450 ; Rise       ; PHI2            ;
-;  RA[11]   ; PHI2       ; 24.450 ; 24.450 ; Rise       ; PHI2            ;
-; LED       ; RCLK       ; 15.471 ; 15.471 ; Rise       ; RCLK            ;
-; RA[*]     ; RCLK       ; 25.685 ; 25.685 ; Rise       ; RCLK            ;
-;  RA[0]    ; RCLK       ; 25.623 ; 25.623 ; Rise       ; RCLK            ;
-;  RA[1]    ; RCLK       ; 21.305 ; 21.305 ; Rise       ; RCLK            ;
-;  RA[2]    ; RCLK       ; 21.360 ; 21.360 ; Rise       ; RCLK            ;
-;  RA[3]    ; RCLK       ; 18.901 ; 18.901 ; Rise       ; RCLK            ;
-;  RA[4]    ; RCLK       ; 21.634 ; 21.634 ; Rise       ; RCLK            ;
-;  RA[5]    ; RCLK       ; 15.577 ; 15.577 ; Rise       ; RCLK            ;
-;  RA[6]    ; RCLK       ; 25.685 ; 25.685 ; Rise       ; RCLK            ;
-;  RA[7]    ; RCLK       ; 20.958 ; 20.958 ; Rise       ; RCLK            ;
-;  RA[8]    ; RCLK       ; 15.905 ; 15.905 ; Rise       ; RCLK            ;
-;  RA[9]    ; RCLK       ; 24.925 ; 24.925 ; Rise       ; RCLK            ;
-;  RA[10]   ; RCLK       ; 14.506 ; 14.506 ; Rise       ; RCLK            ;
-; RCKE      ; RCLK       ; 10.963 ; 10.963 ; Rise       ; RCLK            ;
-; RDQMH     ; RCLK       ; 15.935 ; 15.935 ; Rise       ; RCLK            ;
-; RDQML     ; RCLK       ; 15.786 ; 15.786 ; Rise       ; RCLK            ;
-; nRCAS     ; RCLK       ; 8.987  ; 8.987  ; Rise       ; RCLK            ;
-; nRCS      ; RCLK       ; 10.963 ; 10.963 ; Rise       ; RCLK            ;
-; nRRAS     ; RCLK       ; 8.992  ; 8.992  ; Rise       ; RCLK            ;
-; nRWE      ; RCLK       ; 12.898 ; 12.898 ; Rise       ; RCLK            ;
-; RD[*]     ; nCCAS      ; 28.474 ; 28.474 ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 26.092 ; 26.092 ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 22.744 ; 22.744 ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 22.737 ; 22.737 ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 28.474 ; 28.474 ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 28.317 ; 28.317 ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 26.726 ; 26.726 ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 22.737 ; 22.737 ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 28.330 ; 28.330 ; Fall       ; nCCAS           ;
-; LED       ; nCRAS      ; 19.187 ; 19.187 ; Rise       ; nCRAS           ;
-; LED       ; nCRAS      ; 19.187 ; 19.187 ; Fall       ; nCRAS           ;
-; RA[*]     ; nCRAS      ; 23.706 ; 23.706 ; Fall       ; nCRAS           ;
-;  RA[0]    ; nCRAS      ; 22.368 ; 22.368 ; Fall       ; nCRAS           ;
-;  RA[1]    ; nCRAS      ; 23.706 ; 23.706 ; Fall       ; nCRAS           ;
-;  RA[2]    ; nCRAS      ; 21.361 ; 21.361 ; Fall       ; nCRAS           ;
-;  RA[3]    ; nCRAS      ; 22.589 ; 22.589 ; Fall       ; nCRAS           ;
-;  RA[4]    ; nCRAS      ; 20.580 ; 20.580 ; Fall       ; nCRAS           ;
-;  RA[5]    ; nCRAS      ; 16.352 ; 16.352 ; Fall       ; nCRAS           ;
-;  RA[6]    ; nCRAS      ; 20.958 ; 20.958 ; Fall       ; nCRAS           ;
-;  RA[7]    ; nCRAS      ; 19.907 ; 19.907 ; Fall       ; nCRAS           ;
-;  RA[8]    ; nCRAS      ; 17.186 ; 17.186 ; Fall       ; nCRAS           ;
-;  RA[9]    ; nCRAS      ; 20.624 ; 20.624 ; Fall       ; nCRAS           ;
-; RBA[*]    ; nCRAS      ; 15.699 ; 15.699 ; Fall       ; nCRAS           ;
-;  RBA[0]   ; nCRAS      ; 15.699 ; 15.699 ; Fall       ; nCRAS           ;
-;  RBA[1]   ; nCRAS      ; 13.728 ; 13.728 ; Fall       ; nCRAS           ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Minimum Clock to Output Times                                           ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; RA[*]     ; PHI2       ; 24.450 ; 24.450 ; Rise       ; PHI2            ;
-;  RA[11]   ; PHI2       ; 24.450 ; 24.450 ; Rise       ; PHI2            ;
-; LED       ; RCLK       ; 15.471 ; 15.471 ; Rise       ; RCLK            ;
-; RA[*]     ; RCLK       ; 14.506 ; 14.506 ; Rise       ; RCLK            ;
-;  RA[0]    ; RCLK       ; 25.623 ; 25.623 ; Rise       ; RCLK            ;
-;  RA[1]    ; RCLK       ; 21.305 ; 21.305 ; Rise       ; RCLK            ;
-;  RA[2]    ; RCLK       ; 21.360 ; 21.360 ; Rise       ; RCLK            ;
-;  RA[3]    ; RCLK       ; 18.901 ; 18.901 ; Rise       ; RCLK            ;
-;  RA[4]    ; RCLK       ; 21.634 ; 21.634 ; Rise       ; RCLK            ;
-;  RA[5]    ; RCLK       ; 15.577 ; 15.577 ; Rise       ; RCLK            ;
-;  RA[6]    ; RCLK       ; 25.685 ; 25.685 ; Rise       ; RCLK            ;
-;  RA[7]    ; RCLK       ; 20.958 ; 20.958 ; Rise       ; RCLK            ;
-;  RA[8]    ; RCLK       ; 15.905 ; 15.905 ; Rise       ; RCLK            ;
-;  RA[9]    ; RCLK       ; 24.925 ; 24.925 ; Rise       ; RCLK            ;
-;  RA[10]   ; RCLK       ; 14.506 ; 14.506 ; Rise       ; RCLK            ;
-; RCKE      ; RCLK       ; 10.963 ; 10.963 ; Rise       ; RCLK            ;
-; RDQMH     ; RCLK       ; 15.935 ; 15.935 ; Rise       ; RCLK            ;
-; RDQML     ; RCLK       ; 15.786 ; 15.786 ; Rise       ; RCLK            ;
-; nRCAS     ; RCLK       ; 8.987  ; 8.987  ; Rise       ; RCLK            ;
-; nRCS      ; RCLK       ; 10.963 ; 10.963 ; Rise       ; RCLK            ;
-; nRRAS     ; RCLK       ; 8.992  ; 8.992  ; Rise       ; RCLK            ;
-; nRWE      ; RCLK       ; 12.898 ; 12.898 ; Rise       ; RCLK            ;
-; RD[*]     ; nCCAS      ; 22.737 ; 22.737 ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 26.092 ; 26.092 ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 22.744 ; 22.744 ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 22.737 ; 22.737 ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 28.474 ; 28.474 ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 28.317 ; 28.317 ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 26.726 ; 26.726 ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 22.737 ; 22.737 ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 28.330 ; 28.330 ; Fall       ; nCCAS           ;
-; LED       ; nCRAS      ; 19.187 ; 19.187 ; Rise       ; nCRAS           ;
-; LED       ; nCRAS      ; 19.187 ; 19.187 ; Fall       ; nCRAS           ;
-; RA[*]     ; nCRAS      ; 16.352 ; 16.352 ; Fall       ; nCRAS           ;
-;  RA[0]    ; nCRAS      ; 22.368 ; 22.368 ; Fall       ; nCRAS           ;
-;  RA[1]    ; nCRAS      ; 23.706 ; 23.706 ; Fall       ; nCRAS           ;
-;  RA[2]    ; nCRAS      ; 21.361 ; 21.361 ; Fall       ; nCRAS           ;
-;  RA[3]    ; nCRAS      ; 22.589 ; 22.589 ; Fall       ; nCRAS           ;
-;  RA[4]    ; nCRAS      ; 20.580 ; 20.580 ; Fall       ; nCRAS           ;
-;  RA[5]    ; nCRAS      ; 16.352 ; 16.352 ; Fall       ; nCRAS           ;
-;  RA[6]    ; nCRAS      ; 20.958 ; 20.958 ; Fall       ; nCRAS           ;
-;  RA[7]    ; nCRAS      ; 19.907 ; 19.907 ; Fall       ; nCRAS           ;
-;  RA[8]    ; nCRAS      ; 17.186 ; 17.186 ; Fall       ; nCRAS           ;
-;  RA[9]    ; nCRAS      ; 20.624 ; 20.624 ; Fall       ; nCRAS           ;
-; RBA[*]    ; nCRAS      ; 13.728 ; 13.728 ; Fall       ; nCRAS           ;
-;  RBA[0]   ; nCRAS      ; 15.699 ; 15.699 ; Fall       ; nCRAS           ;
-;  RBA[1]   ; nCRAS      ; 13.728 ; 13.728 ; Fall       ; nCRAS           ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+------------------------------------------------------+
-; Propagation Delay                                    ;
-+------------+-------------+--------+----+----+--------+
-; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
-+------------+-------------+--------+----+----+--------+
-; MAin[0]    ; RA[0]       ; 17.864 ;    ;    ; 17.864 ;
-; MAin[1]    ; RA[1]       ; 16.466 ;    ;    ; 16.466 ;
-; MAin[2]    ; RA[2]       ; 16.451 ;    ;    ; 16.451 ;
-; MAin[3]    ; RA[3]       ; 16.947 ;    ;    ; 16.947 ;
-; MAin[4]    ; RA[4]       ; 17.984 ;    ;    ; 17.984 ;
-; MAin[5]    ; RA[5]       ; 14.301 ;    ;    ; 14.301 ;
-; MAin[6]    ; RA[6]       ; 18.987 ;    ;    ; 18.987 ;
-; MAin[7]    ; RA[7]       ; 19.195 ;    ;    ; 19.195 ;
-; MAin[8]    ; RA[8]       ; 14.224 ;    ;    ; 14.224 ;
-; MAin[9]    ; RA[9]       ; 15.902 ;    ;    ; 15.902 ;
-; MAin[9]    ; RDQMH       ; 17.747 ;    ;    ; 17.747 ;
-; MAin[9]    ; RDQML       ; 17.598 ;    ;    ; 17.598 ;
-; RD[0]      ; Dout[0]     ; 10.392 ;    ;    ; 10.392 ;
-; RD[1]      ; Dout[1]     ; 12.469 ;    ;    ; 12.469 ;
-; RD[2]      ; Dout[2]     ; 10.547 ;    ;    ; 10.547 ;
-; RD[3]      ; Dout[3]     ; 12.366 ;    ;    ; 12.366 ;
-; RD[4]      ; Dout[4]     ; 12.337 ;    ;    ; 12.337 ;
-; RD[5]      ; Dout[5]     ; 12.176 ;    ;    ; 12.176 ;
-; RD[6]      ; Dout[6]     ; 10.385 ;    ;    ; 10.385 ;
-; RD[7]      ; Dout[7]     ; 12.251 ;    ;    ; 12.251 ;
-; nFWE       ; RD[0]       ; 24.642 ;    ;    ; 24.642 ;
-; nFWE       ; RD[1]       ; 22.824 ;    ;    ; 22.824 ;
-; nFWE       ; RD[2]       ; 22.824 ;    ;    ; 22.824 ;
-; nFWE       ; RD[3]       ; 24.642 ;    ;    ; 24.642 ;
-; nFWE       ; RD[4]       ; 24.642 ;    ;    ; 24.642 ;
-; nFWE       ; RD[5]       ; 22.824 ;    ;    ; 22.824 ;
-; nFWE       ; RD[6]       ; 24.642 ;    ;    ; 24.642 ;
-; nFWE       ; RD[7]       ; 24.642 ;    ;    ; 24.642 ;
-+------------+-------------+--------+----+----+--------+
-
-
-+------------------------------------------------------+
-; Minimum Propagation Delay                            ;
-+------------+-------------+--------+----+----+--------+
-; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
-+------------+-------------+--------+----+----+--------+
-; MAin[0]    ; RA[0]       ; 17.864 ;    ;    ; 17.864 ;
-; MAin[1]    ; RA[1]       ; 16.466 ;    ;    ; 16.466 ;
-; MAin[2]    ; RA[2]       ; 16.451 ;    ;    ; 16.451 ;
-; MAin[3]    ; RA[3]       ; 16.947 ;    ;    ; 16.947 ;
-; MAin[4]    ; RA[4]       ; 17.984 ;    ;    ; 17.984 ;
-; MAin[5]    ; RA[5]       ; 14.301 ;    ;    ; 14.301 ;
-; MAin[6]    ; RA[6]       ; 18.987 ;    ;    ; 18.987 ;
-; MAin[7]    ; RA[7]       ; 19.195 ;    ;    ; 19.195 ;
-; MAin[8]    ; RA[8]       ; 14.224 ;    ;    ; 14.224 ;
-; MAin[9]    ; RA[9]       ; 15.902 ;    ;    ; 15.902 ;
-; MAin[9]    ; RDQMH       ; 17.747 ;    ;    ; 17.747 ;
-; MAin[9]    ; RDQML       ; 17.598 ;    ;    ; 17.598 ;
-; RD[0]      ; Dout[0]     ; 10.392 ;    ;    ; 10.392 ;
-; RD[1]      ; Dout[1]     ; 12.469 ;    ;    ; 12.469 ;
-; RD[2]      ; Dout[2]     ; 10.547 ;    ;    ; 10.547 ;
-; RD[3]      ; Dout[3]     ; 12.366 ;    ;    ; 12.366 ;
-; RD[4]      ; Dout[4]     ; 12.337 ;    ;    ; 12.337 ;
-; RD[5]      ; Dout[5]     ; 12.176 ;    ;    ; 12.176 ;
-; RD[6]      ; Dout[6]     ; 10.385 ;    ;    ; 10.385 ;
-; RD[7]      ; Dout[7]     ; 12.251 ;    ;    ; 12.251 ;
-; nFWE       ; RD[0]       ; 24.642 ;    ;    ; 24.642 ;
-; nFWE       ; RD[1]       ; 22.824 ;    ;    ; 22.824 ;
-; nFWE       ; RD[2]       ; 22.824 ;    ;    ; 22.824 ;
-; nFWE       ; RD[3]       ; 24.642 ;    ;    ; 24.642 ;
-; nFWE       ; RD[4]       ; 24.642 ;    ;    ; 24.642 ;
-; nFWE       ; RD[5]       ; 22.824 ;    ;    ; 22.824 ;
-; nFWE       ; RD[6]       ; 24.642 ;    ;    ; 24.642 ;
-; nFWE       ; RD[7]       ; 24.642 ;    ;    ; 24.642 ;
-+------------+-------------+--------+----+----+--------+
-
-
-+-----------------------------------------------------------------------+
-; Output Enable Times                                                   ;
-+-----------+------------+--------+------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
-+-----------+------------+--------+------+------------+-----------------+
-
-
-+-----------------------------------------------------------------------+
-; Minimum Output Enable Times                                           ;
-+-----------+------------+--------+------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 20.845 ;      ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 22.663 ;      ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 20.845 ;      ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 22.663 ;      ; Fall       ; nCCAS           ;
-+-----------+------------+--------+------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------------+
-; Output Disable Times                                                          ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------------+
-; Minimum Output Disable Times                                                  ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; RD[*]     ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 20.845    ;           ; Rise       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 22.663    ;           ; Rise       ; nCCAS           ;
-; RD[*]     ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
-;  RD[0]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
-;  RD[1]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
-;  RD[2]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
-;  RD[3]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
-;  RD[4]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
-;  RD[5]    ; nCCAS      ; 20.845    ;           ; Fall       ; nCCAS           ;
-;  RD[6]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
-;  RD[7]    ; nCCAS      ; 22.663    ;           ; Fall       ; nCCAS           ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-
-
-+-------------------------------------------------------------------+
-; Setup Transfers                                                   ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
-; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
-; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 14       ;
-; RCLK       ; PHI2     ; 2        ; 0        ; 1        ; 0        ;
-; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
-; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
-; PHI2       ; RCLK     ; 1        ; 11       ; 0        ; 0        ;
-; RCLK       ; RCLK     ; 620      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-------------------------------------------------------------------+
-; Hold Transfers                                                    ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; ARCLK      ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; ARCLK    ; 1        ; 0        ; 0        ; 0        ;
-; DRCLK      ; DRCLK    ; 1        ; 0        ; 0        ; 0        ;
-; RCLK       ; DRCLK    ; 2        ; 0        ; 0        ; 0        ;
-; nCCAS      ; nCRAS    ; 0        ; 0        ; 1        ; 1        ;
-; RCLK       ; nCRAS    ; 0        ; 0        ; 12       ; 0        ;
-; PHI2       ; PHI2     ; 0        ; 1        ; 160      ; 14       ;
-; RCLK       ; PHI2     ; 2        ; 0        ; 1        ; 0        ;
-; DRCLK      ; RCLK     ; 3        ; 0        ; 0        ; 0        ;
-; nCCAS      ; RCLK     ; 1        ; 1        ; 0        ; 0        ;
-; nCRAS      ; RCLK     ; 1        ; 17       ; 0        ; 0        ;
-; PHI2       ; RCLK     ; 1        ; 11       ; 0        ; 0        ;
-; RCLK       ; RCLK     ; 620      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths                            ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 31    ; 31   ;
-; Unconstrained Input Port Paths  ; 232   ; 232  ;
-; Unconstrained Output Ports      ; 38    ; 38   ;
-; Unconstrained Output Port Paths ; 77    ; 77   ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
-    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Mon Aug 16 18:40:23 2021
-Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS
-Info: qsta_default_script.tcl version: #1
-Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (306004): Started post-fitting delay annotation
-Info (306005): Delay annotation completed successfully
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
-    Info (332105): create_clock -period 1.000 -name DRCLK DRCLK
-    Info (332105): create_clock -period 1.000 -name ARCLK ARCLK
-    Info (332105): create_clock -period 1.000 -name RCLK RCLK
-    Info (332105): create_clock -period 1.000 -name nCRAS nCRAS
-    Info (332105): create_clock -period 1.000 -name PHI2 PHI2
-    Info (332105): create_clock -period 1.000 -name nCCAS nCCAS
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Critical Warning (332148): Timing requirements not met
-Info (332146): Worst-case setup slack is -99.000
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):   -99.000       -99.000 ARCLK 
-    Info (332119):   -99.000       -99.000 DRCLK 
-    Info (332119):   -23.638      -216.621 PHI2 
-    Info (332119):   -19.942      -610.547 RCLK 
-    Info (332119):    -3.072        -6.479 nCRAS 
-Info (332146): Worst-case hold slack is -16.153
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):   -16.153       -16.153 ARCLK 
-    Info (332119):   -14.623       -14.623 DRCLK 
-    Info (332119):    -2.569        -3.433 PHI2 
-    Info (332119):    -0.713        -2.822 nCRAS 
-    Info (332119):     2.127         0.000 RCLK 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -29.500
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):   -29.500       -59.000 ARCLK 
-    Info (332119):   -29.500       -59.000 DRCLK 
-    Info (332119):    -2.289        -2.289 PHI2 
-    Info (332119):    -2.289        -2.289 RCLK 
-    Info (332119):    -2.289        -2.289 nCCAS 
-    Info (332119):    -2.289        -2.289 nCRAS 
-Info (332001): The selected device family is not supported by the report_metastability command.
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
-    Info: Peak virtual memory: 368 megabytes
-    Info: Processing ended: Mon Aug 16 18:40:24 2021
-    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/CPLD-old/MAX/MAXV/output_files/RAM2GS.sta.summary b/CPLD-old/MAX/MAXV/output_files/RAM2GS.sta.summary
deleted file mode 100644
index 44e8308..0000000
--- a/CPLD-old/MAX/MAXV/output_files/RAM2GS.sta.summary
+++ /dev/null
@@ -1,69 +0,0 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type  : Setup 'ARCLK'
-Slack : -99.000
-TNS   : -99.000
-
-Type  : Setup 'DRCLK'
-Slack : -99.000
-TNS   : -99.000
-
-Type  : Setup 'PHI2'
-Slack : -23.638
-TNS   : -216.621
-
-Type  : Setup 'RCLK'
-Slack : -19.942
-TNS   : -610.547
-
-Type  : Setup 'nCRAS'
-Slack : -3.072
-TNS   : -6.479
-
-Type  : Hold 'ARCLK'
-Slack : -16.153
-TNS   : -16.153
-
-Type  : Hold 'DRCLK'
-Slack : -14.623
-TNS   : -14.623
-
-Type  : Hold 'PHI2'
-Slack : -2.569
-TNS   : -3.433
-
-Type  : Hold 'nCRAS'
-Slack : -0.713
-TNS   : -2.822
-
-Type  : Hold 'RCLK'
-Slack : 2.127
-TNS   : 0.000
-
-Type  : Minimum Pulse Width 'ARCLK'
-Slack : -29.500
-TNS   : -59.000
-
-Type  : Minimum Pulse Width 'DRCLK'
-Slack : -29.500
-TNS   : -59.000
-
-Type  : Minimum Pulse Width 'PHI2'
-Slack : -2.289
-TNS   : -2.289
-
-Type  : Minimum Pulse Width 'RCLK'
-Slack : -2.289
-TNS   : -2.289
-
-Type  : Minimum Pulse Width 'nCCAS'
-Slack : -2.289
-TNS   : -2.289
-
-Type  : Minimum Pulse Width 'nCRAS'
-Slack : -2.289
-TNS   : -2.289
-
-------------------------------------------------------------
diff --git a/CPLD-old/MAX/RAM2GS-MAX.mif b/CPLD-old/MAX/RAM2GS-MAX.mif
deleted file mode 100644
index 65c8441..0000000
--- a/CPLD-old/MAX/RAM2GS-MAX.mif
+++ /dev/null
@@ -1,27 +0,0 @@
--- Copyright (C) 1991-2013 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- Quartus II generated Memory Initialization File (.mif)
-
-WIDTH=16;
-DEPTH=512;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-	[000..0FD]  :   0000;
-	0FE  :   7FFF;
-	[0FF..1FF]  :   FFFF;
-END;
diff --git a/CPLD-old/MAX/RAM2GS-MAX.v b/CPLD-old/MAX/RAM2GS-MAX.v
deleted file mode 100644
index ebb32f0..0000000
--- a/CPLD-old/MAX/RAM2GS-MAX.v
+++ /dev/null
@@ -1,467 +0,0 @@
-module RAM2GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE, LED,
-			  RBA, RA, RD, nRCS, RCLK, RCKE,
-			  nRWE, nRRAS, nRCAS, RDQMH, RDQML);
-
-	/* 65816 Phase 2 Clock */
-	input PHI2;
-
-	/* Async. DRAM Control Inputs */
-	input nCCAS, nCRAS;
-
-	/* Synchronized PHI2 and DRAM signals */
-	reg PHI2r, PHI2r2, PHI2r3;
-	reg RASr, RASr2, RASr3;
-	reg CASr, CASr2, CASr3;
-	reg FWEr;
-	reg CBR;
-
-	/* Activity LED */
-	reg LEDEN = 0;
-	output LED;
-	assign LED = ~(~nCRAS &&  LEDEN);
-
-	/* 65816 Data */
-	input [7:0] Din;
-	output [7:0] Dout;
-	assign Dout[7:0] = RD[7:0];
-
-	/* Latched 65816 Bank Address */
-	reg [7:0] Bank;
-
-	/* Async. DRAM Address Bus */
-	input [1:0] CROW;
-	input [9:0] MAin;
-	input nFWE;
-	reg n8MEGEN = 0;
-	reg XOR8MEG = 0;
-	
-	/* SDRAM Clock */
-	input RCLK;
-	
-	/* SDRAM */
-	reg RCKEEN;
-	output reg RCKE = 0;
-	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
-	output reg [1:0] RBA;
-	reg nRowColSel;
-	reg RA11;
-	reg RA10;
-	reg [9:0] RowA;
-	output [11:0] RA;
-	assign RA[11] = RA11;
-	assign RA[10] = RA10;
-	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML, RDQMH;
-	assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	assign RDQMH = ~nRowColSel ? 1'b1 :  MAin[9];
-	reg [7:0] WRD;
-	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
-
-	/* UFM Interface */
-	reg [15:15] UFMD = 0; // UFM data register bit 15
-	reg ARCLK = 0; // UFM address register clock
-	// UFM address register data input tied to 0
-	reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
-	reg DRCLK = 0; // UFM data register clock
-	reg DRDIn = 0; // UFM data register input
-	reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
-	reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
-	reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
-	reg UFMOscEN = 0; // UFM oscillator enable
-	wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
-	wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
-	wire DRDOut; // UFM data output
-	// UFM oscillator always enabled
-	wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
-	UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
-		.arclk (ARCLK),
-		.ardin (1'b0),
-		.arshft (ARShift),
-		.drclk (DRCLK),
-		.drdin (DRDIn),
-		.drshft (DRShift),
-		.erase (UFMErase),
-		.oscena (UFMOscEN),
-		.program (UFMProgram),
-		.busy (UFMBusy),
-		.drdout (DRDOut),
-		.osc (UFMOsc),
-		.rtpbusy (RTPBusy));
-	reg UFMBusyReg = 0; // UFMBusy registered to sync with RCLK
-	reg RTPBusyReg = 0; // RTPBusy registered to sync with RCLK
-
-	/* UFM State */
-	reg UFMInitDone = 0; // 1 if UFM initialization finished
-	reg UFMReqErase = 0; // 1 if UFM requires erase
-
-	/* UFM Command Interface */
-	reg C1Submitted = 0;
-	reg ADSubmitted = 0;
-	reg CmdEnable = 0;
-	reg CmdSubmitted = 0;
-	reg CmdLEDEN = 0;
-	reg Cmdn8MEGEN = 0;
-	reg CmdDRCLK = 0;
-	reg CmdDRDIn = 0;
-	reg CmdUFMErase = 0; // Set by user command. Programs UFM
-	reg CmdUFMPrgm = 0; // Set by user command. Erases UFM
-	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
-	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
-	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
-	
-	/* State Counters */
-	reg InitReady = 0; // 1 if ready for init sequence
-	reg Ready = 0; // 1 if done with init sequence
-	reg [1:0] S = 0; // post-RAS State counter
-	reg [17:0] FS = 0; // Fast init state counter
-	reg [3:0] IS = 0; // Init state counter
-	reg WriteDone;
-	
-	/* Synchronize PHI2, RAS, CAS */
-	always @(posedge RCLK) begin
-		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
-		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
-		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
-	end
-	
-	/* Latch 65816 bank when PHI2 rises */
-	always @(posedge PHI2) begin
-		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
-		else RA11 <= 1'b0; // Reserved in mode register
-		Bank[7:0] <= Din[7:0]; // Latch bank
-	end
-	
-	/* Latch bank address, row address, WE, and CAS when RAS falls */
-	always @(negedge nCRAS) begin
-		if (Ready) begin
-			RBA[1:0] <= CROW[1:0];
-			RowA[9:0] <= MAin[9:0];
-		end else begin
-			RBA[1:0] <= 2'b00;		// Reserved in mode register
-			RowA[9] <= 1'b1;		// "1" for single write mode
-			RowA[8] <= 1'b0;		// Reserved
-			RowA[7] <= 1'b0;		// "0" for not test mode
-			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
-			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
-			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
-		end
-		FWEr <= ~nFWE;
-		CBR <= ~nCCAS;
-	end
-
-	/* Latch write data when CAS falls */
-	always @(negedge nCCAS) begin
-		WRD[7:0] <= Din[7:0];
-	end
-
-	/* State counter from RAS */
-	always @(posedge RCLK) begin
-		if (~RASr2) S <= 0;
-		else if (S==2'h3) S <= 2'h3;
-		else S <= S+1;
-	end
-	/* Init state counter */
-	always @(posedge RCLK) begin
-		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
-		FS <= FS+1;
-		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
-	end
-
-	/* SDRAM CKE */
-	always @(posedge RCLK) begin
-		// Only 1 LUT4 allowed for this function!
-		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
-	end
-
-	/* SDRAM command */
-	always @(posedge RCLK) begin
-		if (Ready) begin
-			if (S==0) begin
-				if (RASr2) begin
-					if (CBR) begin
-						// AREF
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b0;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // RA10 is don't care
-					end else begin
-						// ACT
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b1;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // Bank RA10 consistently "1"
-					end
-					// Enable clock only for reads
-					RCKEEN <= ~CBR & ~FWEr;
-				end else if (RCKE) begin
-					// PCall
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-					RCKEEN <= 1'b1;
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-					RCKEEN <= 1'b1;
-				end
-				nRowColSel <= 1'b0; // Select registered row addres
-			end else if (S==1) begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR; // Disable clock if refresh cycle
-			end else if (S==2) begin
-				if (~FWEr & ~CBR) begin
-					// RD
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
-			end else if (S==3) begin
-				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
-					// WR
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= ~(~FWEr | CASr3 | CBR);
-				RCKEEN <= ~(~FWEr | CASr2 | CBR);
-			end
-		end else if (InitReady) begin
-			if (S==0 & RASr2) begin
-				if (IS==0) begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end else if (IS==1) begin
-					// PC all
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-				end else if (IS==9) begin
-					// Load mode register
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b0; // Reserved in mode register
-				end else begin
-					// AREF
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				IS <= IS+1;
-			end else begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-			end
-			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b1;
-		end else begin
-			// NOP
-			nRCS <= 1'b1;
-			nRRAS <= 1'b1;
-			nRCAS <= 1'b1;
-			nRWE <= 1'b1;
-			RA10 <= 1'b1; // RA10 is don't care
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b0;
-		end
-	end
-	
-	/* Submit command when PHI2 falls */
-	always @(negedge PHI2) begin
-		// Magic number check
-		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
-			if (ADSubmitted) begin
-				CmdEnable <= 1'b1;
-				UFMOscEN <= 1'b1;
-			end
-			C1Submitted <= 1'b1;
-			ADSubmitted <= 1'b0;
-		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
-			if (C1Submitted) begin
-				CmdEnable <= 1'b1;
-				UFMOscEN <= 1'b1;
-			end
-			ADSubmitted <= 1'b1;
-			C1Submitted <= 1'b0;
-		end else if (C1WR | ADWR) begin // wrong magic number submitted
-			CmdEnable <= 1'b0;
-			C1Submitted <= 1'b0;
-			ADSubmitted <= 1'b0;
-		end else if (CMDWR) CmdEnable <= 1'b0;
-
-		// Submit command
-		if (CMDWR & CmdEnable) begin
-			if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin
-				// LCMXO, LCMXO2, iCE40 ignore this unless Din[2] and Din[1] set
-				// MAX w/ LED ignores this unless Din[2] set
-				// MAX w/o LED does not check Din[3:1].
-				XOR8MEG <= Din[0];
-			end else if (Din[7:4]==4'h1) begin
-				CmdLEDEN <= ~Din[1];
-				Cmdn8MEGEN <= ~Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h2) begin
-				// MAX commands
-				CmdLEDEN <= LEDEN;
-				Cmdn8MEGEN <= n8MEGEN;
-				CmdUFMErase <= Din[3];
-				CmdUFMPrgm <= Din[2];
-				CmdDRCLK <= Din[1];
-				CmdDRDIn <= Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h3 && ~Din[3]) begin
-				// Reserved for LCMXO2 commands
-				// Din[1] - Shift when high, execute when low
-				// Din[0] - Shift data
-			end else if (Din[7:4]==4'h3 && Din[3]) begin
-				// Reserved for SPI (LCMXO, iCE40) commands
-				// Din[2] - CS
-				// Din[1] - SCK
-				// Din[0] - SDI
-			end
-		end
-	end
-
-	/* UFM Control */
-	always @(posedge RCLK) begin
-		if (~Ready) begin
-			if (~UFMInitDone & FS[17:16]==2'b00) begin
-				// Shift 0 into address register
-				ARCLK <= FS[3]; // Clock address register
-				ARShift <= 1'b1; // Shift 0 into address register
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h0) begin
-				// Parallel transfer UFM data to shift register
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= FS[3]; // Clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // Parallel transfer to data register
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h4) begin
-				// Shift UFM data shift register
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= FS[3]; // Clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b1; // Shift data register
-				// Capture bit 15 of this UFM word in UFMD register
-				if (FS[3:0]==4'h7) UFMD[15] <= DRDOut;
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h5) begin
-				// Shift UFM data shift register
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= FS[3]; // Clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b1; // Shift data register
-				// If valid setting here, set capacity setting to UFMD[14]
-				if (FS[3:0]==4'h7 && ~UFMD[15]) n8MEGEN <= ~DRDOut;
-			end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h6) begin
-				if (UFMD[15]) UFMInitDone <= 1'b1; // If current spot erased, quit iterating
-				else begin // If valid setting here
-					LEDEN <= ~DRDOut; // LED enabled if UFMD[13]==0
-					// If last byte in sector, mark need to erase
-					if (FS[15:8]==8'hFF) begin
-						UFMReqErase <= 1'b1; // Mark need to wrap around
-						UFMInitDone <= 1'b1; // Quit iterating
-					end
-				end
-
-				// Increment UFM address
-				ARCLK <= FS[3]; // Clock address register
-				ARShift <= 1'b0; // Increment UFM address
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end else if (FS[17:16]==2'b10 & UFMReqErase) begin
-				// Shift 0 into address register
-				ARCLK <= FS[3]; // Clock address register
-				ARShift <= 1'b1; // Shift 0 into address register
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end else begin
-				// Don't do anything with UFM
-				ARCLK <= 1'b0; // Don't clock address register
-				ARShift <= 1'b0; // ARShift is don't care
-				DRCLK <= 1'b0; // Don't clock data register
-				DRDIn <= 1'b0; // DRDIn is don't care
-				DRShift <= 1'b0; // DRShift is don't care
-			end
-
-			// Don't erase or program UFM during initialization 
-			UFMErase <= 1'b0;
-			UFMProgram <= 1'b0;
-		end else begin
-			// Can only shift UFM data register now
-			ARCLK <= 1'b0;
-			ARShift <= 1'b0;
-			DRShift <= 1'b1;
-
-			// Set user command signals after PHI2 falls
-			if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
-				n8MEGEN <= Cmdn8MEGEN;
-				DRCLK <= CmdDRCLK;
-				DRDIn <= CmdDRDIn;
-			end
-
-			// UFM programming sequence
-			if (CmdUFMPrgm | CmdUFMErase) begin
-				if (~UFMBusyReg & ~RTPBusyReg) begin
-					if (UFMReqErase | CmdUFMErase) UFMErase <= 1'b1;
-					else if (CmdUFMPrgm) UFMProgram <= 1'b1;
-				end else if (UFMBusyReg) UFMReqErase <= 1'b0;
-			end
-		end
-	end
-endmodule
diff --git a/CPLD-old/MAX/greybox_tmp/cbx_args.txt b/CPLD-old/MAX/greybox_tmp/cbx_args.txt
deleted file mode 100644
index 941c71c..0000000
--- a/CPLD-old/MAX/greybox_tmp/cbx_args.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-ERASE_TIME=500000000
-INTENDED_DEVICE_FAMILY="MAX V"
-LPM_FILE=RAM2GS-MAX.mif
-LPM_HINT=UNUSED
-LPM_TYPE=altufm_none
-OSC_FREQUENCY=180000
-PORT_ARCLKENA=PORT_UNUSED
-PORT_DRCLKENA=PORT_UNUSED
-PROGRAM_TIME=1600000
-WIDTH_UFM_ADDRESS=9
-DEVICE_FAMILY="MAX V"
-CBX_AUTO_BLACKBOX=ALL
-arclk
-ardin
-arshft
-busy
-drclk
-drdin
-drdout
-drshft
-erase
-osc
-oscena
-program
-rtpbusy
diff --git a/CPLD-old/RAM4GS-AGM.v b/CPLD-old/RAM4GS-AGM.v
deleted file mode 100644
index c92dfd4..0000000
--- a/CPLD-old/RAM4GS-AGM.v
+++ /dev/null
@@ -1,402 +0,0 @@
-module RAM4GS(PHI2, MAin, CROW, Din, Dout,
-			  nCCAS, nCRAS, nFWE,
-			  RBA, RA, RD, nRCS, RCLK, RCKE,
-			  nRWE, nRRAS, nRCAS, RDQMH, RDQML,
-			  nUFMCSout, UFMCLKout, UFMSDIout, UFMSDOout, In);
-
-	/* 65816 Phase 2 Clock */
-	input PHI2;
-
-	/* Async. DRAM Control Inputs */
-	input nCCAS, nCRAS;
-
-	/* Synchronized PHI2 and DRAM signals */
-	reg PHI2r, PHI2r2, PHI2r3;
-	reg RASr, RASr2, RASr3;
-	reg CASr, CASr2, CASr3;
-	reg FWEr;
-	reg CBR;
-
-	/* 65816 Data */
-	input [7:0] Din;
-	output [7:0] Dout = RD[7:0];
-
-	/* Latched 65816 Bank Address */
-	reg [7:0] Bank;
-
-	/* Async. DRAM Address Bus */
-	input [1:0] CROW;
-	input [9:0] MAin;
-	input nFWE;
-	reg n8MEGEN = 0;
-	reg XOR8MEG = 0;
-	
-	/* SDRAM Clock */
-	input RCLK;
-	
-	/* SDRAM */
-	reg RCKEEN;
-	output reg RCKE = 0;
-	output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
-	output reg [1:0] RBA;
-	reg nRowColSel;
-	reg RA11;
-	reg RA10;
-	reg [9:0] RowA;
-	output [11:0] RA;
-	assign RA[11] = RA11;
-	assign RA[10] = RA10;
-	assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
-	output RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
-	output RDQMH = ~nRowColSel ? 1'b1 : MAin[9];
-	reg [7:0] WRD;
-	inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
-
-	/* UFM Interface */
-	reg nUFMCS = 1;
-	reg UFMCLK = 0;
-	reg UFMSDI = 0;
-	wire UFMSDO;
-	wire UFMOsc;
-	alta_ufms u_alta_ufms (
-		.i_ufm_set (1'b1), 
-		.i_osc_ena (1'b1), 
-		.i_ufm_flash_csn (nUFMCS), 
-		.i_ufm_flash_sclk (UFMCLK), 
-		.i_ufm_flash_sdi (UFMSDI), 
-		.o_ufm_flash_sdo (UFMSDO), 
-		.o_osc (UFMOsc) 
-	);
-
-	/* UFM Command Interface */
-	reg C1Submitted = 0;
-	reg ADSubmitted = 0;
-	reg CmdEnable = 0;
-	reg CmdSubmitted = 0;
-	reg Cmdn8MEGEN = 0;
-	reg CmdUFMCLK = 0;
-	reg CmdUFMSDI = 0;
-	reg CmdUFMCS = 0;
-	wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
-	wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
-	wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
-	
-	/* State Counters */
-	reg InitReady = 0; // 1 if ready for init sequence
-	reg Ready = 0; // 1 if done with init sequence
-	reg [1:0] S = 0; // post-RAS State counter
-	reg [17:0] FS = 0; // Fast init state counter
-	reg [3:0] IS = 0; // Init state counter
-	reg WriteDone;
-	
-	/* Synchronize PHI2, RAS, CAS */
-	always @(posedge RCLK) begin
-		PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
-		RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
-		CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
-	end
-	
-	/* Latch 65816 bank when PHI2 rises */
-	always @(posedge PHI2) begin
-		if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
-		else RA11 <= 1'b0; // Reserved in mode register
-		Bank[7:0] <= Din[7:0]; // Latch bank
-	end
-	
-	/* Latch bank address, row address, WE, and CAS when RAS falls */
-	always @(negedge nCRAS) begin
-		if (Ready) begin
-			RBA[1:0] <= CROW[1:0];
-			RowA[9:0] <= MAin[9:0];
-		end else begin
-			RBA[1:0] <= 2'b00;		// Reserved in mode register
-			RowA[9] <= 1'b1;		// "1" for single write mode
-			RowA[8] <= 1'b0;		// Reserved
-			RowA[7] <= 1'b0;		// "0" for not test mode
-			RowA[6:4] <= 3'b010;	// "2" for CAS latency 2
-			RowA[3] <= 1'b0;		// "0" for sequential burst (not used)
-			RowA[2:0] <= 3'b000;	// "0" for burst length 1 (no burst)
-		end
-		FWEr <= ~nFWE;
-		CBR <= ~nCCAS;
-	end
-
-	/* Latch write data when CAS falls */
-	always @(negedge nCCAS) begin
-		WRD[7:0] <= Din[7:0];
-	end
-
-	/* State counter from RAS */
-	always @(posedge RCLK) begin
-		if (~RASr2) S <= 0;
-		else if (S==2'h3) S <= 2'h3;
-		else S <= S+1;
-	end
-	/* Init state counter */
-	always @(posedge RCLK) begin
-		// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
-		FS <= FS+1;
-		if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
-	end
-
-	/* SDRAM CKE */
-	always @(posedge RCLK) begin
-		// Only 1 LUT4 allowed for this function!
-		RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
-	end
-
-	/* SDRAM command */
-	always @(posedge RCLK) begin
-		if (Ready) begin
-			if (S==0) begin
-				if (RASr2) begin
-					if (CBR) begin
-						// AREF
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b0;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // RA10 is don't care
-					end else begin
-						// ACT
-						nRCS <= 1'b0;
-						nRRAS <= 1'b0;
-						nRCAS <= 1'b1;
-						nRWE <= 1'b1;
-						RA10 <= 1'b1; // Bank RA10 consistently "1"
-					end
-					// Enable clock only for reads
-					RCKEEN <= ~CBR & ~FWEr;
-				end else if (RCKE) begin
-					// PCall
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-					RCKEEN <= 1'b1;
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-					RCKEEN <= 1'b1;
-				end
-				nRowColSel <= 1'b0; // Select registered row addres
-			end else if (S==1) begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR; // Disable clock if refresh cycle
-			end else if (S==2) begin
-				if (~FWEr & ~CBR) begin
-					// RD
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= 1'b1; // Select asynchronous column address
-				RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
-			end else if (S==3) begin
-				if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
-					// WR
-					nRCS <= 1'b0;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // Auto-precharge
-				end else begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				nRowColSel <= ~(~FWEr | CASr3 | CBR);
-				RCKEEN <= ~(~FWEr | CASr2 | CBR);
-			end
-		end else if (InitReady) begin
-			if (S==0 & RASr2) begin
-				if (IS==0) begin
-					// NOP
-					nRCS <= 1'b1;
-					nRRAS <= 1'b1;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end else if (IS==1) begin
-					// PC all
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b1;
-					nRWE <= 1'b0;
-					RA10 <= 1'b1; // "all"
-				end else if (IS==9) begin
-					// Load mode register
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b0;
-					RA10 <= 1'b0; // Reserved in mode register
-				end else begin
-					// AREF
-					nRCS <= 1'b0;
-					nRRAS <= 1'b0;
-					nRCAS <= 1'b0;
-					nRWE <= 1'b1;
-					RA10 <= 1'b1; // RA10 is don't care
-				end
-				IS <= IS+1;
-			end else begin
-				// NOP
-				nRCS <= 1'b1;
-				nRRAS <= 1'b1;
-				nRCAS <= 1'b1;
-				nRWE <= 1'b1;
-				RA10 <= 1'b1; // RA10 is don't care
-			end
-			if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b1;
-		end else begin
-			// NOP
-			nRCS <= 1'b1;
-			nRRAS <= 1'b1;
-			nRCAS <= 1'b1;
-			nRWE <= 1'b1;
-			RA10 <= 1'b1; // RA10 is don't care
-			nRowColSel <= 1'b0; // Select registered row address
-			RCKEEN <= 1'b0;
-		end
-	end
-	
-	/* Submit command when PHI2 falls */
-	always @(negedge PHI2) begin
-		// Magic number check
-		if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
-			if (ADSubmitted) begin
-				CmdEnable <= 1'b1;
-			end
-			C1Submitted <= 1'b1;
-			ADSubmitted <= 1'b0;
-		end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
-			if (C1Submitted) begin
-				CmdEnable <= 1'b1;
-			end
-			ADSubmitted <= 1'b1;
-			C1Submitted <= 1'b0;
-		end else if (C1WR | ADWR) begin // wrong magic number submitted
-			CmdEnable <= 1'b0;
-			C1Submitted <= 1'b0;
-			ADSubmitted <= 1'b0;
-		end else if (CMDWR) CmdEnable <= 1'b0;
-
-		// Submit command
-		if (CMDWR & CmdEnable) begin
-			if (Din[7:4]==4'h0) begin
-				XOR8MEG <= Din[0];
-			end else if (Din[7:4]==4'h1) begin
-				Cmdn8MEGEN <= ~Din[0];
-				CmdSubmitted <= 1'b1;
-			end else if (Din[7:4]==4'h3) begin
-				Cmdn8MEGEN <= n8MEGEN;
-				CmdUFMCS <= Din[2];
-				CmdUFMCLK <= Din[1];
-				CmdUFMSDI <= Din[0];
-				CmdSubmitted <= 1'b1;
-			end
-		end
-	end
-
-	/* UFM Control */
-	output nUFMCSout = nUFMCS;
-	output UFMCLKout = UFMCLK;
-	output UFMSDIout = UFMSDI;
-	output UFMSDOout = UFMSDO;
-	input [3:0] In;
-	always @(posedge RCLK) begin
-		if (~InitReady && FS[17:10]==8'h00) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h01) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~InitReady && FS[17:10]==8'h02) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[4];
-			case (FS[9:5]) // Shift out read data command (0x03)
-				5'h00: UFMSDI <= 1'b0; // command bit 7 (0)
-				5'h01: UFMSDI <= 1'b0; // command bit 6 (0)
-				5'h02: UFMSDI <= 1'b0; // command bit 5 (0)
-				5'h03: UFMSDI <= 1'b0; // command bit 4 (0)
-				5'h04: UFMSDI <= 1'b0; // command bit 3 (0)
-				5'h05: UFMSDI <= 1'b0; // command bit 2 (0)
-				5'h06: UFMSDI <= 1'b1; // command bit 1 (1)
-				5'h07: UFMSDI <= 1'b1; // command bit 0 (1)
-				5'h08: UFMSDI <= 1'b0; // address bit 23 (0)
-				5'h09: UFMSDI <= 1'b0; // address bit 22 (0)
-				5'h0A: UFMSDI <= 1'b0; // address bit 21 (0)
-				5'h0B: UFMSDI <= 1'b0; // address bit 20 (0)
-				5'h0C: UFMSDI <= 1'b0; // address bit 19 (0)
-				5'h0D: UFMSDI <= 1'b0; // address bit 18 (0)
-				5'h0E: UFMSDI <= 1'b0; // address bit 17 (0)
-				5'h0F: UFMSDI <= 1'b0; // address bit 16 (0)
-				5'h10: UFMSDI <= 1'b0; // address bit 15 (0)
-				5'h11: UFMSDI <= 1'b0; // address bit 14 (0)
-				5'h12: UFMSDI <= 1'b0; // address bit 13 (0)
-				5'h13: UFMSDI <= 1'b1; // address bit 12 (0)
-				5'h14: UFMSDI <= 1'b0; // address bit 11 (0)
-				5'h15: UFMSDI <= 1'b0; // address bit 10 (0)
-				5'h16: UFMSDI <= 1'b0; // address bit 09 (0)
-				5'h17: UFMSDI <= 1'b0; // address bit 08 (0)
-				5'h18: UFMSDI <= 1'b0; // address bit 07 (0)
-				5'h19: UFMSDI <= 1'b0; // address bit 06 (0)
-				5'h1A: UFMSDI <= 1'b0; // address bit 05 (0)
-				5'h1B: UFMSDI <= 1'b0; // address bit 04 (0)
-				5'h1C: UFMSDI <= 1'b0; // address bit 03 (0)
-				5'h1D: UFMSDI <= 1'b0; // address bit 02 (0)
-				5'h1E: UFMSDI <= 1'b0; // address bit 01 (0)
-				5'h1F: UFMSDI <= 1'b0; // address bit 00 (0)
-			endcase
-		end else if (~InitReady && FS[17:10]==8'h03) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-			// Latch n8MEGEN
-			if (FS[9:4]==6'h00 && FS[3:0]==4'hF) n8MEGEN <= ~UFMSDO;
-		end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
-			nUFMCS <= 1'b0;
-			UFMCLK <= FS[1];
-			UFMSDI <= 1'b0;
-		end else if (~InitReady) begin
-			nUFMCS <= 1'b1;
-			UFMCLK <= 1'b0;
-			UFMSDI <= 1'b0;
-		end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
-			// Set user command signals after PHI2 falls
-			// Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI
-			n8MEGEN <= Cmdn8MEGEN;
-			nUFMCS <= ~CmdUFMCS;
-			UFMCLK <= CmdUFMCLK;
-			UFMSDI <= CmdUFMSDI;
-		end
-	end
-endmodule
diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf
index c6d7112..fddf68b 100644
--- a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf
+++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf
@@ -13,5 +13,5 @@
             
         
     
-    
+    
 
diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC1.sty
similarity index 100%
rename from CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty
rename to CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC1.sty
diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815052235.tcr b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815052235.tcr
new file mode 100644
index 0000000..6049d67
--- /dev/null
+++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815052235.tcr
@@ -0,0 +1,5 @@
+#Start recording tcl command: 8/15/2023 05:22:04
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf"
+prj_run Export -impl impl1
+#Stop recording: 8/15/2023 05:22:35
diff --git a/CPLD/LCMXO2-1200HC/impl1/.build_status b/CPLD/LCMXO2-1200HC/impl1/.build_status
index 94e5b25..e131fe6 100644
--- a/CPLD/LCMXO2-1200HC/impl1/.build_status
+++ b/CPLD/LCMXO2-1200HC/impl1/.build_status
@@ -6,22 +6,22 @@
             
             
             
-            
+            
         
-        
-            
-            
-            
-            
+        
+            
+            
+            
+            
         
-        
-            
-            
-            
+        
+            
+            
+            
         
-        
-            
-            
+        
+            
+            
         
         
             
@@ -30,21 +30,21 @@
             
             
         
-        
+        
         
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
         
         
         
diff --git a/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb b/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb
index f28b48bf9a2e079ad9c17d968c531e2c78bb6968..20f45e5fc7c0eb948a503d13876a1f05c8109b05 100644
GIT binary patch
delta 431
zcmdn6l4Zk677?`^d1ejZB2a=Ps89#uiSSFCn
z=KD3iu4VfSqKeq7LDYNpWDpg?kqDx;b3}kBLCz!~wYij23an!y*KZKF
zkGqZyMDqzj=spQMDUj-OMsq>JxyCVnIOvKymzCxz9d^!i03PP{mFrnwi5$boBJf&`y?5+_enBUz6Jm?6%LdD

delta 42
ycmZqg;%V>VnIOt!AGc9lUy`lH`^!3g{mFrnwi5$boBJf&`y?5+_enBUz6Jm: -5.186ns/-468.418ns; real time: 7 secs 
+Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 6 secs 
 Level 2, iteration 1
 11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 7 secs 
 Level 3, iteration 1
 20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 7 secs 
 Level 4, iteration 1
 11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 7 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:39 08/15/23
+Start NBR section for normal routing at 05:22:15 08/15/23
 Level 1, iteration 1
 7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 7 secs 
 Level 4, iteration 1
 9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 7 secs 
 Level 4, iteration 2
 6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 7 secs 
 Level 4, iteration 3
 6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs 
 Level 4, iteration 4
 6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs 
 Level 4, iteration 5
 4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs 
 Level 4, iteration 6
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs 
 Level 4, iteration 7
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs 
 Level 4, iteration 8
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs 
 Level 4, iteration 9
 2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs 
 Level 4, iteration 10
 3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs 
 Level 4, iteration 11
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs 
 Level 4, iteration 12
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs 
 Level 4, iteration 13
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs 
 Level 4, iteration 14
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs 
 Level 4, iteration 15
 2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 16
 3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 17
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs 
 Level 4, iteration 18
 1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs 
 Level 4, iteration 19
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 20
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 21
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 22
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 23
 1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs 
 Level 4, iteration 24
 1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs 
 Level 4, iteration 25
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:15 08/15/23
 Level 4, iteration 1
 1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 7 secs 
 Level 4, iteration 2
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for re-routing at 05:03:39 08/15/23
+Start NBR section for re-routing at 05:22:15 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for post-routing at 05:03:39 08/15/23
+Start NBR section for post-routing at 05:22:15 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -264,8 +264,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=6 clock_loads=4
 
-Total CPU time 7 secs 
-Total REAL time: 8 secs 
+Total CPU time 6 secs 
+Total REAL time: 7 secs 
 Completely routed.
 End of route.  674 routed (100.00%); 0 unrouted.
 
@@ -287,8 +287,8 @@ PAR_SUMMARY::Worst  slack> = 0.304
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 8 secs 
-Total REAL time to completion: 8 secs 
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 7 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par
index 9d23cf4..7d91ea8 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par
@@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:31 2023
+Tue Aug 15 05:22:08 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
@@ -17,11 +17,11 @@ Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            -4.650       391939       0.304        0            08           Completed
+5_1   *      0            -4.650       391939       0.304        0            07           Completed
 
 * : Design saved.
 
-Total (real) run time for 1-seed: 8 secs 
+Total (real) run time for 1-seed: 7 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed
index 8ec6c65..80ddd6d 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed
@@ -2,7 +2,7 @@
 NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
 NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
 NOTE All Rights Reserved.*
-NOTE DATE CREATED:	Tue Aug 15 05:03:43 2023*
+NOTE DATE CREATED:	Tue Aug 15 05:22:19 2023*
 NOTE DESIGN NAME:	RAM2GS_LCMXO2_1200HC_impl1.ncd*
 NOTE DEVICE NAME:	LCMXO2-1200HC-4TQFP100*
 NOTE JEDEC FILE STATUS:	Final   Version 1.95*
@@ -2776,4 +2776,4 @@ E0000000000000000000000000000000000000000000000000000000000000000
 0000010001100000*
 NOTE User Electronic Signature Data*
 UH00000000*
-8380
+8384
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp
index 8e79120..934b075 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp
@@ -16,7 +16,7 @@ Target Vendor:  LATTICE
 Target Device:  LCMXO2-1200HCTQFP100
 Target Performance:   4
 Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/15/23  05:03:26
+Mapped on:  08/15/23  05:22:05
 
 Design Summary
 --------------
@@ -66,7 +66,7 @@ Design Summary
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:26
+Design:  RAM2GS                                        Date:  08/15/23  05:22:05
 
 Design Summary (cont)
 ---------------------
@@ -132,7 +132,7 @@ IO (PIO) Attributes
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:26
+Design:  RAM2GS                                        Date:  08/15/23  05:22:05
 
 IO (PIO) Attributes (cont)
 --------------------------
@@ -198,7 +198,7 @@ IO (PIO) Attributes (cont)
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:26
+Design:  RAM2GS                                        Date:  08/15/23  05:22:05
 
 IO (PIO) Attributes (cont)
 --------------------------
@@ -264,7 +264,7 @@ IO (PIO) Attributes (cont)
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:26
+Design:  RAM2GS                                        Date:  08/15/23  05:22:05
 
 IO (PIO) Attributes (cont)
 --------------------------
@@ -330,7 +330,7 @@ Run Time and Memory Usage
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:26
+Design:  RAM2GS                                        Date:  08/15/23  05:22:05
 
 Run Time and Memory Usage (cont)
 --------------------------------
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ncd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ncd
index c492e5d51d9f51a342f152faa3d9b82acc561858..1967c447327945754f26dadb5cf7ffc3a75a66db 100644
GIT binary patch
delta 42
ycmZqg;%V>VnIOvKymzCxz9d^!i03PP{mFrnwi5$boBJf&`y?5+_enBUz6Jm?6%LdD

delta 42
ycmZqg;%V>VnIOt!AGc9lUy`lH`^!3g{mFrnwi5$boBJf&`y?5+_enBUz6Jm: -5.186ns/-468.418ns; real time: 7 secs 
+Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 6 secs 
 Level 2, iteration 1
 11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 7 secs 
 Level 3, iteration 1
 20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 7 secs 
 Level 4, iteration 1
 11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 7 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:39 08/15/23
+Start NBR section for normal routing at 05:22:15 08/15/23
 Level 1, iteration 1
 7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 7 secs 
 Level 4, iteration 1
 9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 7 secs 
 Level 4, iteration 2
 6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 7 secs 
 Level 4, iteration 3
 6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs 
 Level 4, iteration 4
 6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs 
 Level 4, iteration 5
 4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs 
 Level 4, iteration 6
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs 
 Level 4, iteration 7
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs 
 Level 4, iteration 8
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs 
 Level 4, iteration 9
 2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs 
 Level 4, iteration 10
 3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs 
 Level 4, iteration 11
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs 
 Level 4, iteration 12
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs 
 Level 4, iteration 13
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs 
 Level 4, iteration 14
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs 
 Level 4, iteration 15
 2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 16
 3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 17
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs 
 Level 4, iteration 18
 1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs 
 Level 4, iteration 19
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 20
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 21
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 22
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 23
 1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs 
 Level 4, iteration 24
 1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs 
 Level 4, iteration 25
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:15 08/15/23
 Level 4, iteration 1
 1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 7 secs 
 Level 4, iteration 2
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for re-routing at 05:03:39 08/15/23
+Start NBR section for re-routing at 05:22:15 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for post-routing at 05:03:39 08/15/23
+Start NBR section for post-routing at 05:22:15 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -292,8 +292,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=6 clock_loads=4
 
-Total CPU time 7 secs 
-Total REAL time: 8 secs 
+Total CPU time 6 secs 
+Total REAL time: 7 secs 
 Completely routed.
 End of route.  674 routed (100.00%); 0 unrouted.
 
@@ -315,8 +315,8 @@ PAR_SUMMARY::Worst  slack> = 0.304
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 8 secs 
-Total REAL time to completion: 8 secs 
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 7 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
index 0fcb3d2..c80afd4 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
@@ -1,5 +1,5 @@
 SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:27 2023
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:22:06 2023
 
 SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
 LOCATE COMP "RD[7]" SITE "43" ;
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1
index 278d419..e13b3ff 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1
@@ -13,7 +13,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:07 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -188,7 +188,7 @@ Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:07 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr
index 7c6f2bd..97270c5 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr
@@ -13,7 +13,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:40 2023
+Tue Aug 15 05:22:16 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -1154,7 +1154,7 @@ Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:40 2023
+Tue Aug 15 05:22:16 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html
index e5f11b0..5f15130 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html
@@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:01:23 2023
+Tue Aug 15 05:03:42 2023
 
 
-Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
 
 Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
 Design name: RAM2GS
@@ -91,8 +91,8 @@ UFM Utilization: General Purpose Flash Memory.
 Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
 Initialized UFM Pages:                     0 Page.
  
-Total CPU Time: 1 secs 
-Total REAL Time: 2 secs 
+Total CPU Time: 2 secs 
+Total REAL Time: 3 secs 
 Peak Memory Usage: 253 MB
 
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html
index 1fddacf..7e2eb91 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html
@@ -38,7 +38,7 @@ Performance Hardware Data Status:   Final          Version 34.4.
 // Package: TQFP100
 // ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
 // Version: Diamond (64-bit) 3.12.1.454
-// Written on Tue Aug 15 05:03:41 2023
+// Written on Tue Aug 15 05:22:17 2023
 // M: Minimum Performance Grade
 // iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam
index 0e2396b..764d169 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam
@@ -15,7 +15,7 @@ FS_610_add_4_1/CI
 [ END CLIPPED ]
 [ START DESIGN PREFS ]
 SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:27 2023
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:22:06 2023
 
 SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
 LOCATE COMP "RD[7]" SITE "43" ;
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd
index 331614c53e06d54bef656752479767b37bc115ae..2f8eda47865862a99814b4c51fef644bc9ba6125 100644
GIT binary patch
delta 42
ycmcb1jN{rdjtQbn&U-hC>r1j#MP;4W*Pk3HX*)51wYg8Sy-$*Hd!HoJ2~GfAVGkPs

delta 42
ycmcb1jN{rdjtQbn_Hi4<^(EPALgd@^^(O~P+D;5$ZSIq7?~`QQ-Y3a)f)fBk8xA1=

diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf
index f178e30..1f53442 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf
@@ -1,7 +1,7 @@
 (DELAYFILE
   (SDFVERSION "3.0")
   (DESIGN "RAM2GS")
-  (DATE "Tue Aug 15 05:03:31 2023")
+  (DATE "Tue Aug 15 05:22:08 2023")
   (VENDOR "Lattice")
   (PROGRAM "ldbanno")
   (VERSION "Diamond (64-bit) 3.12.1.454")
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho
index 61a9bb6..c6d0c2c 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho
@@ -2,8 +2,8 @@
 -- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
 
 -- ldbanno -n VHDL -o RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd 
--- Netlist created on Tue Aug 15 05:03:26 2023
--- Netlist written on Tue Aug 15 05:03:31 2023
+-- Netlist created on Tue Aug 15 05:22:05 2023
+-- Netlist written on Tue Aug 15 05:22:08 2023
 -- Design is for device LCMXO2-1200HC
 -- Design is for package TQFP100
 -- Design is for performance grade 4
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf
index 357899e..d43baf3 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf
@@ -1,7 +1,7 @@
 (DELAYFILE
   (SDFVERSION "3.0")
   (DESIGN "RAM2GS")
-  (DATE "Tue Aug 15 05:03:30 2023")
+  (DATE "Tue Aug 15 05:22:08 2023")
   (VENDOR "Lattice")
   (PROGRAM "ldbanno")
   (VERSION "Diamond (64-bit) 3.12.1.454")
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo
index ec046df..cb54343 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo
@@ -2,8 +2,8 @@
 // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
 
 // ldbanno -n Verilog -o RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd 
-// Netlist created on Tue Aug 15 05:03:26 2023
-// Netlist written on Tue Aug 15 05:03:29 2023
+// Netlist created on Tue Aug 15 05:22:05 2023
+// Netlist written on Tue Aug 15 05:22:08 2023
 // Design is for device LCMXO2-1200HC
 // Design is for package TQFP100
 // Design is for performance grade 4
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html
index bf146ce..acc608c 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html
@@ -24,7 +24,7 @@ Target Vendor:  LATTICE
 Target Device:  LCMXO2-1200HCTQFP100
 Target Performance:   4
 Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/15/23  05:03:26
+Mapped on:  08/15/23  05:22:05
 
 
 Design Summary
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html
index b2d8069..232f92e 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html
@@ -14,7 +14,7 @@ Performance Grade:      4
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.44
 
-Tue Aug 15 05:03:35 2023
+Tue Aug 15 05:22:12 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
@@ -314,7 +314,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:38 2023
+Tue Aug 15 05:22:14 2023
 
 
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html
index 2db9546..0c0c85e 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html
@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:31 2023
+Tue Aug 15 05:22:08 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
@@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            -4.650       391939       0.304        0            08           Completed
+5_1   *      0            -4.650       391939       0.304        0            07           Completed
 * : Design saved.
 
-Total (real) run time for 1-seed: 8 secs 
+Total (real) run time for 1-seed: 7 secs 
 
 par done!
 
 Note: user must run 'Trace' for timing closure signoff.
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
-Tue Aug 15 05:03:31 2023
+Tue Aug 15 05:22:08 2023
 
 
 Best Par Run
@@ -145,7 +145,7 @@ I/O Bank Usage Summary:
 | 3        | 17 / 20 ( 85%) | 2.5V       | -         |
 +----------+----------------+------------+-----------+
 
-Total placer CPU time: 4 secs 
+Total placer CPU time: 3 secs 
 
 Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
 
@@ -157,9 +157,9 @@ WARNING - par: The driver of primary clock net PHI2_c is not placed on one of th
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=6 clock_loads=4
 
-Completed router resource preassignment. Real time: 7 secs 
+Completed router resource preassignment. Real time: 6 secs 
 
-Start NBR router at 05:03:38 08/15/23
+Start NBR router at 05:22:14 08/15/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -174,119 +174,119 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:03:38 08/15/23
+Start NBR special constraint process at 05:22:14 08/15/23
 
-Start NBR section for initial routing at 05:03:38 08/15/23
+Start NBR section for initial routing at 05:22:14 08/15/23
 Level 1, iteration 1
 2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -5.186ns/-468.418ns; real time: 7 secs 
+Estimated worst slack/total negative slack<setup>: -5.186ns/-468.418ns; real time: 6 secs 
 Level 2, iteration 1
 11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-377.051ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-377.051ns; real time: 7 secs 
 Level 3, iteration 1
 20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-373.496ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-373.496ns; real time: 7 secs 
 Level 4, iteration 1
 11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-386.255ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-386.255ns; real time: 7 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:39 08/15/23
+Start NBR section for normal routing at 05:22:15 08/15/23
 Level 1, iteration 1
 7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-379.537ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-379.537ns; real time: 7 secs 
 Level 4, iteration 1
 9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-380.800ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-380.800ns; real time: 7 secs 
 Level 4, iteration 2
 6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-390.587ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-390.587ns; real time: 7 secs 
 Level 4, iteration 3
 6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 7 secs 
 Level 4, iteration 4
 6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 7 secs 
 Level 4, iteration 5
 4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 7 secs 
 Level 4, iteration 6
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 7 secs 
 Level 4, iteration 7
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 7 secs 
 Level 4, iteration 8
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 7 secs 
 Level 4, iteration 9
 2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 7 secs 
 Level 4, iteration 10
 3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 7 secs 
 Level 4, iteration 11
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 7 secs 
 Level 4, iteration 12
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 7 secs 
 Level 4, iteration 13
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 7 secs 
 Level 4, iteration 14
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 7 secs 
 Level 4, iteration 15
 2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 16
 3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 17
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 7 secs 
 Level 4, iteration 18
 1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 7 secs 
 Level 4, iteration 19
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 20
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 21
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 22
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 23
 1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 7 secs 
 Level 4, iteration 24
 1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 7 secs 
 Level 4, iteration 25
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:15 08/15/23
 Level 4, iteration 1
 1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-405.830ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-405.830ns; real time: 7 secs 
 Level 4, iteration 2
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for re-routing at 05:03:39 08/15/23
+Start NBR section for re-routing at 05:22:15 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for post-routing at 05:03:39 08/15/23
+Start NBR section for post-routing at 05:22:15 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -304,8 +304,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=6 clock_loads=4
 
-Total CPU time 7 secs 
-Total REAL time: 8 secs 
+Total CPU time 6 secs 
+Total REAL time: 7 secs 
 Completely routed.
 End of route.  674 routed (100.00%); 0 unrouted.
 
@@ -327,8 +327,8 @@ PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 8 secs 
-Total REAL time to completion: 8 secs 
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 7 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html
index affe710..dfa4c74 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html
@@ -62,7 +62,7 @@
 
 
 Updated:
-2023/08/15 05:03:45
+2023/08/15 05:22:21
 
 
 Implementation Location:
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html
index 2254cfa..04d87c3 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:07 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -207,7 +207,7 @@ Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:07 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html
index eab0fb8..987f2af 100644
--- a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html
+++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:40 2023
+Tue Aug 15 05:22:16 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -1173,7 +1173,7 @@ Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:40 2023
+Tue Aug 15 05:22:16 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO2-1200HC/impl1/automake.log b/CPLD/LCMXO2-1200HC/impl1/automake.log
index bdf40a5..f56d09d 100644
--- a/CPLD/LCMXO2-1200HC/impl1/automake.log
+++ b/CPLD/LCMXO2-1200HC/impl1/automake.log
@@ -1,256 +1,4 @@
 
-synthesis -f "RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj"
-synthesis:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:25 2023
-
-
-Command Line:  synthesis -f RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml 
-
-    
-Synthesis options:
-The -a option is MachXO2.
-The -s option is 4.
-The -t option is TQFP100.
-The -d option is LCMXO2-1200HC.
-Using package TQFP100.
-Using performance grade 4.
-                                                          
-
-##########################################################
-
-### Lattice Family : MachXO2
-
-### Device  : LCMXO2-1200HC
-
-### Package : TQFP100
-
-### Speed   : 4
-
-##########################################################
-
-                                                          
-
-    
-Optimization goal = Balanced
-Top-level module name = RAM2GS.
-Target frequency = 200.000000 MHz.
-Maximum fanout = 1000.
-Timing path count = 3
-BRAM utilization = 100.000000 %
-DSP usage = true
-DSP utilization = 100.000000 %
-fsm_encoding_style = auto
-resolve_mixed_drivers = 0
-fix_gated_clocks = 1
-
-Mux style = Auto
-Use Carry Chain = true
-carry_chain_length = 0
-Loop Limit = 1950.
-Use IO Insertion = TRUE
-Use IO Reg = AUTO
-
-Resource Sharing = TRUE
-Propagate Constants = TRUE
-Remove Duplicate Registers = TRUE
-force_gsr = auto
-ROM style = auto
-RAM style = auto
-The -comp option is FALSE.
-The -syn option is FALSE.
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
--p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1 (searchpath added)
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
-Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
-NGD file = RAM2GS_LCMXO2_1200HC_impl1.ngd
--sdc option: SDC file input not used.
--lpf option: Output file option is ON.
-Hardtimer checking is enabled (default). The -dt option is not used.
-The -r option is OFF. [ Remove LOC Properties is OFF. ]
-Technology check ok...
-
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
-Compile design.
-Compile Design Begin
-Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
-Top module name (Verilog): RAM2GS
-    
-    
-    
-    
-Last elaborated design is RAM2GS()
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.44.
-Top-level module name = RAM2GS.
-    
-original encoding -> new encoding (one-hot encoding)
-
- 0000 -> 0000000000000001
-
- 0001 -> 0000000000000010
-
- 0010 -> 0000000000000100
-
- 0011 -> 0000000000001000
-
- 0100 -> 0000000000010000
-
- 0101 -> 0000000000100000
-
- 0110 -> 0000000001000000
-
- 0111 -> 0000000010000000
-
- 1000 -> 0000000100000000
-
- 1001 -> 0000001000000000
-
- 1010 -> 0000010000000000
-
- 1011 -> 0000100000000000
-
- 1100 -> 0001000000000000
-
- 1101 -> 0010000000000000
-
- 1110 -> 0100000000000000
-
- 1111 -> 1000000000000000
-
-    
-original encoding -> new encoding (one-hot encoding)
-
- 00 -> 0001
-
- 01 -> 0010
-
- 10 -> 0100
-
- 11 -> 1000
-
-
-
-
-GSR will not be inferred because no asynchronous signal was found in the netlist.
-    
-Applying 200.000000 MHz constraint to all clocks
-
-    
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-
-
-Running DRC...
-
-DRC complete with no errors or warnings
-
-Design Results:
-    309 blocks expanded
-completed the first expansion
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd.
-
-################### Begin Area Report (RAM2GS)######################
-Number of register bits => 102 of 1520 (6 % )
-BB => 8
-CCU2D => 10
-FD1P3AX => 29
-FD1P3AY => 5
-FD1P3IX => 3
-FD1S3AX => 47
-FD1S3IX => 14
-FD1S3JX => 4
-GSR => 1
-IB => 26
-INV => 3
-LUT4 => 122
-OB => 33
-PFUMX => 1
-################### End Area Report ##################
-
-################### Begin BlackBox Report ######################
-TSALL => 1
-################### End BlackBox Report ##################
-
-################### Begin Clock Report ######################
-Clock Nets
-Number of Clocks: 4
-  Net : RCLK_c, loads : 62
-  Net : PHI2_c, loads : 11
-  Net : nCCAS_c, loads : 2
-  Net : nCRAS_c, loads : 2
-Clock Enable Nets
-Number of Clock Enables: 14
-Top 10 highest fanout Clock Enables:
-  Net : RCLK_c_enable_27, loads : 16
-  Net : RCLK_c_enable_6, loads : 4
-  Net : PHI2_N_120_enable_8, loads : 3
-  Net : RCLK_c_enable_10, loads : 3
-  Net : RCLK_c_enable_5, loads : 2
-  Net : PHI2_N_120_enable_3, loads : 1
-  Net : Ready_N_292, loads : 1
-  Net : PHI2_N_120_enable_2, loads : 1
-  Net : RCLK_c_enable_15, loads : 1
-  Net : PHI2_N_120_enable_6, loads : 1
-Highest fanout non-clock nets
-Top 10 highest fanout non-clock nets:
-  Net : RCLK_c_enable_27, loads : 16
-  Net : InitReady, loads : 15
-  Net : nCRAS_c__inv, loads : 15
-  Net : RASr2, loads : 14
-  Net : nRowColSel_N_35, loads : 13
-  Net : n2380, loads : 13
-  Net : nRowColSel, loads : 12
-  Net : Ready, loads : 12
-  Net : Din_c_4, loads : 10
-  Net : MAin_c_1, loads : 10
-################### End Clock Report ##################
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |  200.000 MHz|   50.413 MHz|     6 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |  200.000 MHz|  120.207 MHz|     5 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
-
-Peak Memory Usage: 55.238  MB
-
---------------------------------------------------------------
-Elapsed CPU time for LSE flow : 0.891  secs
---------------------------------------------------------------
-
 map -a "MachXO2" -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial   "RAM2GS_LCMXO2_1200HC_impl1.ngd" -o "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_1200HC_impl1.prf" -mp "RAM2GS_LCMXO2_1200HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf"  -c 0           
 map:  version Diamond (64-bit) 3.12.1.454
 
@@ -400,7 +148,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:07 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -434,7 +182,7 @@ Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:07 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -507,9 +255,9 @@ Converting design RAM2GS_LCMXO2_1200HC_impl1_map.ncd into .ldb format.
 Writing Verilog netlist to file RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo
 Writing SDF timing to file RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf
     
-Total CPU Time: 1 secs 
-Total REAL Time: 2 secs 
-Peak Memory Usage: 41 MB
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 40 MB
 
 ldbanno "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho" -w -neg
 ldbanno: version Diamond (64-bit) 3.12.1.454
@@ -536,9 +284,9 @@ Converting design RAM2GS_LCMXO2_1200HC_impl1_map.ncd into .ldb format.
 Writing VHDL netlist to file RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho
 Writing SDF timing to file RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf
     
-Total CPU Time: 1 secs 
+Total CPU Time: 0 secs 
 Total REAL Time: 0 secs 
-Peak Memory Usage: 40 MB
+Peak Memory Usage: 41 MB
 
 mpartrce -p "RAM2GS_LCMXO2_1200HC_impl1.p2t" -f "RAM2GS_LCMXO2_1200HC_impl1.p3t" -tf "RAM2GS_LCMXO2_1200HC_impl1.pt" "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" "RAM2GS_LCMXO2_1200HC_impl1.ncd"
 
@@ -547,7 +295,7 @@ Removing old design directory at request of -rem command line option to this pro
 Running par. Please wait . . .
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
-Tue Aug 15 05:03:31 2023
+Tue Aug 15 05:22:08 2023
 
 PAR: Place And Route Diamond (64-bit) 3.12.1.454.
 Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
@@ -652,7 +400,7 @@ I/O Bank Usage Summary:
 | 3        | 17 / 20 ( 85%) | 2.5V       | -         |
 +----------+----------------+------------+-----------+
 
-Total placer CPU time: 4 secs 
+Total placer CPU time: 3 secs 
 
 Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
 
@@ -663,9 +411,9 @@ Starting router resource preassignment
 
     
 
-Completed router resource preassignment. Real time: 7 secs 
+Completed router resource preassignment. Real time: 6 secs 
 
-Start NBR router at 05:03:38 08/15/23
+Start NBR router at 05:22:14 08/15/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -680,119 +428,119 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:03:38 08/15/23
+Start NBR special constraint process at 05:22:14 08/15/23
 
-Start NBR section for initial routing at 05:03:38 08/15/23
+Start NBR section for initial routing at 05:22:14 08/15/23
 Level 1, iteration 1
 2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; 
-Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 7 secs 
+Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 6 secs 
 Level 2, iteration 1
 11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 7 secs 
 Level 3, iteration 1
 20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 7 secs 
 Level 4, iteration 1
 11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 7 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:39 08/15/23
+Start NBR section for normal routing at 05:22:15 08/15/23
 Level 1, iteration 1
 7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 7 secs 
 Level 4, iteration 1
 9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 7 secs 
 Level 4, iteration 2
 6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 7 secs 
 Level 4, iteration 3
 6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs 
 Level 4, iteration 4
 6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 7 secs 
 Level 4, iteration 5
 4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs 
 Level 4, iteration 6
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 7 secs 
 Level 4, iteration 7
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs 
 Level 4, iteration 8
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 7 secs 
 Level 4, iteration 9
 2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs 
 Level 4, iteration 10
 3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 7 secs 
 Level 4, iteration 11
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs 
 Level 4, iteration 12
 3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
-Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 7 secs 
 Level 4, iteration 13
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs 
 Level 4, iteration 14
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 7 secs 
 Level 4, iteration 15
 2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 16
 3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 17
 2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs 
 Level 4, iteration 18
 1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; 
-Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 7 secs 
 Level 4, iteration 19
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 20
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 21
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 22
 1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 7 secs 
 Level 4, iteration 23
 1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs 
 Level 4, iteration 24
 1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 7 secs 
 Level 4, iteration 25
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:15 08/15/23
 Level 4, iteration 1
 1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 7 secs 
 Level 4, iteration 2
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for re-routing at 05:03:39 08/15/23
+Start NBR section for re-routing at 05:22:15 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
-Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs 
+Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 7 secs 
 
-Start NBR section for post-routing at 05:03:39 08/15/23
+Start NBR section for post-routing at 05:22:15 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -809,8 +557,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 
     
 
-Total CPU time 7 secs 
-Total REAL time: 8 secs 
+Total CPU time 6 secs 
+Total REAL time: 7 secs 
 Completely routed.
 End of route.  674 routed (100.00%); 0 unrouted.
 
@@ -829,8 +577,8 @@ PAR_SUMMARY::Worst  slack> = 0.304
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 8 secs 
-Total REAL time to completion: 8 secs 
+Total CPU  time to completion: 6 secs 
+Total REAL time to completion: 7 secs 
 
 par done!
 
@@ -867,7 +615,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:40 2023
+Tue Aug 15 05:22:16 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -901,7 +649,7 @@ Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:40 2023
+Tue Aug 15 05:22:16 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -1106,6 +854,6 @@ UFM Utilization: General Purpose Flash Memory.
 Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
 Initialized UFM Pages:                     0 Page.
  
-Total CPU Time: 2 secs 
-Total REAL Time: 3 secs 
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
 Peak Memory Usage: 253 MB
diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior
index c8edb74..7695bfd 100644
--- a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior
+++ b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior
@@ -29,7 +29,7 @@ Performance Hardware Data Status:   Final          Version 34.4.
 // Package: TQFP100
 // ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
 // Version: Diamond (64-bit) 3.12.1.454
-// Written on Tue Aug 15 05:03:41 2023
+// Written on Tue Aug 15 05:22:17 2023
 // M: Minimum Performance Grade
 // iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
 
diff --git a/CPLD-old/LCMXO/LCMXO640C/.run_manager.ini b/CPLD/LCMXO2-640HC-old/.run_manager.ini
similarity index 100%
rename from CPLD-old/LCMXO/LCMXO640C/.run_manager.ini
rename to CPLD/LCMXO2-640HC-old/.run_manager.ini
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/.setting.ini b/CPLD/LCMXO2-640HC-old/.setting.ini
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/.setting.ini
rename to CPLD/LCMXO2-640HC-old/.setting.ini
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/EFB.edn b/CPLD/LCMXO2-640HC-old/EFB.edn
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/EFB.edn
rename to CPLD/LCMXO2-640HC-old/EFB.edn
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/EFB.ipx b/CPLD/LCMXO2-640HC-old/EFB.ipx
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/EFB.ipx
rename to CPLD/LCMXO2-640HC-old/EFB.ipx
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/EFB.lpc b/CPLD/LCMXO2-640HC-old/EFB.lpc
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/EFB.lpc
rename to CPLD/LCMXO2-640HC-old/EFB.lpc
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/EFB.naf b/CPLD/LCMXO2-640HC-old/EFB.naf
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/EFB.naf
rename to CPLD/LCMXO2-640HC-old/EFB.naf
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/EFB.sort b/CPLD/LCMXO2-640HC-old/EFB.sort
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/EFB.sort
rename to CPLD/LCMXO2-640HC-old/EFB.sort
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/EFB.srp b/CPLD/LCMXO2-640HC-old/EFB.srp
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/EFB.srp
rename to CPLD/LCMXO2-640HC-old/EFB.srp
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/EFB.sym b/CPLD/LCMXO2-640HC-old/EFB.sym
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/EFB.sym
rename to CPLD/LCMXO2-640HC-old/EFB.sym
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/EFB.v b/CPLD/LCMXO2-640HC-old/EFB.v
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/EFB.v
rename to CPLD/LCMXO2-640HC-old/EFB.v
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/EFB_generate.log b/CPLD/LCMXO2-640HC-old/EFB_generate.log
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/EFB_generate.log
rename to CPLD/LCMXO2-640HC-old/EFB_generate.log
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/EFB_tmpl.v b/CPLD/LCMXO2-640HC-old/EFB_tmpl.v
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/EFB_tmpl.v
rename to CPLD/LCMXO2-640HC-old/EFB_tmpl.v
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.ldf
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf
rename to CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.ldf
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.lpf
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf
rename to CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC.lpf
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC1.sty
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty
rename to CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC1.sty
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2-640HC-old/RAM2GS_LCMXO2_640HC_tcl.html
similarity index 100%
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rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam
rename to CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr
rename to CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd
rename to CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html
rename to CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html
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diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html
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diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html
rename to CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html
rename to CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
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diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_drc.log b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_drc.log
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_drc.log
rename to CPLD/LCMXO2-640HC-old/impl1/RAM2GS_drc.log
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse.twr b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_lse.twr
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse.twr
rename to CPLD/LCMXO2-640HC-old/impl1/RAM2GS_lse.twr
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_lse_lsetwr.html
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html
rename to CPLD/LCMXO2-640HC-old/impl1/RAM2GS_lse_lsetwr.html
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_prim.v b/CPLD/LCMXO2-640HC-old/impl1/RAM2GS_prim.v
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_prim.v
rename to CPLD/LCMXO2-640HC-old/impl1/RAM2GS_prim.v
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/automake.log b/CPLD/LCMXO2-640HC-old/impl1/automake.log
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/automake.log
rename to CPLD/LCMXO2-640HC-old/impl1/automake.log
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-640HC-old/impl1/hdla_gen_hierarchy.html
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
rename to CPLD/LCMXO2-640HC-old/impl1/hdla_gen_hierarchy.html
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2-640HC-old/impl1/ram2gs_lcmxo2_640hc_impl1.ior
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior
rename to CPLD/LCMXO2-640HC-old/impl1/ram2gs_lcmxo2_640hc_impl1.ior
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd b/CPLD/LCMXO2-640HC-old/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd
rename to CPLD/LCMXO2-640HC-old/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/synthesis.log b/CPLD/LCMXO2-640HC-old/impl1/synthesis.log
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/synthesis.log
rename to CPLD/LCMXO2-640HC-old/impl1/synthesis.log
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/synthesis_lse.html b/CPLD/LCMXO2-640HC-old/impl1/synthesis_lse.html
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/synthesis_lse.html
rename to CPLD/LCMXO2-640HC-old/impl1/synthesis_lse.html
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO2-640HC-old/impl1/xxx_lse_cp_file_list
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_cp_file_list
rename to CPLD/LCMXO2-640HC-old/impl1/xxx_lse_cp_file_list
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_sign_file b/CPLD/LCMXO2-640HC-old/impl1/xxx_lse_sign_file
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_sign_file
rename to CPLD/LCMXO2-640HC-old/impl1/xxx_lse_sign_file
diff --git a/CPLD-old/LCMXO2/LCMXO2-640HC/msg_file.log b/CPLD/LCMXO2-640HC-old/msg_file.log
similarity index 100%
rename from CPLD-old/LCMXO2/LCMXO2-640HC/msg_file.log
rename to CPLD/LCMXO2-640HC-old/msg_file.log
diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815052238.tcr b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815052238.tcr
new file mode 100644
index 0000000..96b7d9d
--- /dev/null
+++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815052238.tcr
@@ -0,0 +1,5 @@
+#Start recording tcl command: 8/15/2023 05:22:13
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+prj_run Export -impl impl1
+#Stop recording: 8/15/2023 05:22:38
diff --git a/CPLD/LCMXO256C/impl1/.build_status b/CPLD/LCMXO256C/impl1/.build_status
index 67a7f04..1a3ead0 100644
--- a/CPLD/LCMXO256C/impl1/.build_status
+++ b/CPLD/LCMXO256C/impl1/.build_status
@@ -5,23 +5,23 @@
             
             
             
-            
+            
         
-        
-            
-            
-            
-            
-            
+        
+            
+            
+            
+            
+            
         
-        
-            
-            
-            
+        
+            
+            
+            
         
-        
-            
-            
+        
+            
+            
         
         
             
@@ -30,20 +30,20 @@
             
             
         
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
     
 
diff --git a/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb b/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb
index b00bbf803d286f2dcabcdfbfc7b8f556ba8e5ca1..5d924f772adf7f55da08bd9dfe335cd15e21e7b6 100644
GIT binary patch
delta 270
zcmccriuwL4W)ZaZB0Fska7(txLI~db|
z)Mf>ynT#NMH*+$Go~*#S9Yoz^tp-tHY{?*MH(Mfzl4FkmQ5Eb-AnFeLJ|MMu4#!%s
z0p477Y#{z=0SN6aZXpFy)@s-b5*9J~$qJ(REx5t<$XLdLWUC?6EeK_4l?hU_#EO{-
uB)QTi0mS9D)dibu<$MIBb&@Mc(d2B`J`nZW737V{$!=9ZYV&=!hIIgMvSbSY

delta 270
zcmccriuwL4W)ZaiUoPgY>v4x(Vi$Say|mmI>{BJXmYk|ABg(x3i8I}WVb3HwfVkV!#V(PHdFZk

diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt
index deaaf52..c9fc183 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt
@@ -1,6 +1,6 @@
 NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
 NOTE All Rights Reserved *
-NOTE DATE CREATED: Tue Aug 15 05:03:33 2023 *
+NOTE DATE CREATED: Tue Aug 15 05:22:31 2023 *
 NOTE DESIGN NAME: RAM2GS *
 NOTE DEVICE NAME: LCMXO256C-3TQFP100 *
 NOTE PIN ASSIGNMENTS *
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn
index 63c7186..4ffdded 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn
@@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:33 2023
+Tue Aug 15 05:22:31 2023
 
 
 Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit
index 6a513fb480c97f9745ce69179aeb62a9f62bf5e7..8694a4c7dbf0f9c3a84b245ca0ae59eb0404587c 100644
GIT binary patch
delta 16
XcmeD5==7LyjMd1<%Ghw@X**>AG(`p7

delta 16
XcmeD5==7LyjMc!{%Gh}0X**>AG(`p8

diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd
index 113a28f9c6cae770047794648cfe230b6cdbc83c..50d19f6b3214d5d594ea97fb943a38eef6b3ac7e 100644
GIT binary patch
delta 42
ycmezIne)eI&IzJS&gV9YYfG|KD~LrW1pw44~g+1w@B-X+Pny-SiQF985qlMZ+Q

delta 42
ycmezIne)eI&IzJS_7NM!wI$hVG$i`<^(O~PT22h$Z0?e5?~-KP-X+PDmjD1&%np43

diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad
index 4582186..f23dc0b 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad
@@ -6,7 +6,7 @@ Performance Grade:      3
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.19
 
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:28 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+------+------------------------------+
@@ -267,5 +267,5 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:28 2023
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par
index 7c17e3d..65d9d69 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par
@@ -1,6 +1,6 @@
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:24 2023
 
 PAR: Place And Route Diamond (64-bit) 3.12.1.454.
 Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
@@ -51,12 +51,12 @@ Finished Placer Phase 0.  REAL time: 0 secs
 Starting Placer Phase 1.
 ..............
 Placer score = 831129.
-Finished Placer Phase 1.  REAL time: 5 secs 
+Finished Placer Phase 1.  REAL time: 4 secs 
 
 Starting Placer Phase 2.
 .
 Placer score =  828350
-Finished Placer Phase 2.  REAL time: 5 secs 
+Finished Placer Phase 2.  REAL time: 4 secs 
 
 
 ------------------ Clock Report ------------------
@@ -90,7 +90,7 @@ I/O Bank Usage Summary:
 | 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
 +----------+----------------+------------+------------+------------+
 
-Total placer CPU time: 4 secs 
+Total placer CPU time: 3 secs 
 
 Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
 
@@ -102,9 +102,9 @@ WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=7 clock_loads=4
 
-Completed router resource preassignment. Real time: 5 secs 
+Completed router resource preassignment. Real time: 4 secs 
 
-Start NBR router at 05:03:28 08/15/23
+Start NBR router at 05:22:28 08/15/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -119,68 +119,68 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:03:28 08/15/23
+Start NBR special constraint process at 05:22:28 08/15/23
 
-Start NBR section for initial routing at 05:03:28 08/15/23
+Start NBR section for initial routing at 05:22:28 08/15/23
 Level 1, iteration 1
 0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; 
-Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 4 secs 
 Level 2, iteration 1
 3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 4 secs 
 Level 3, iteration 1
 6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 4 secs 
 Level 4, iteration 1
 17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 4 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:28 08/15/23
+Start NBR section for normal routing at 05:22:28 08/15/23
 Level 4, iteration 1
 12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 4 secs 
 Level 4, iteration 2
 6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 4 secs 
 Level 4, iteration 3
 3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 4 secs 
 Level 4, iteration 4
 3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 4 secs 
 Level 4, iteration 5
 3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 4 secs 
 Level 4, iteration 6
 1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 4 secs 
 Level 4, iteration 7
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 8
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 9
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 10
 0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:28 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 
-Start NBR section for re-routing at 05:03:29 08/15/23
+Start NBR section for re-routing at 05:22:28 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 4 secs 
 
-Start NBR section for post-routing at 05:03:29 08/15/23
+Start NBR section for post-routing at 05:22:28 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -198,8 +198,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=7 clock_loads=4
 
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
+Total CPU time 4 secs 
+Total REAL time: 5 secs 
 Completely routed.
 End of route.  662 routed (100.00%); 0 unrouted.
 
@@ -221,8 +221,8 @@ PAR_SUMMARY::Worst  slack> = 0.273
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
+Total CPU  time to completion: 4 secs 
+Total REAL time to completion: 5 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par
index 1b6d169..78695b5 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par
@@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:24 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
@@ -17,11 +17,11 @@ Preference file: RAM2GS_LCMXO256C_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            -10.044      913247       0.273        0            06           Completed
+5_1   *      0            -10.044      913247       0.273        0            05           Completed
 
 * : Design saved.
 
-Total (real) run time for 1-seed: 6 secs 
+Total (real) run time for 1-seed: 5 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed
index 0472a9a..d3df95a 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed
@@ -6,7 +6,7 @@ NOTE Readback:       Off*
 NOTE Security:      Off*
 NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
 NOTE All Rights Reserved *
-NOTE DATE CREATED: Tue Aug 15 05:03:33 2023 *
+NOTE DATE CREATED: Tue Aug 15 05:22:31 2023 *
 NOTE DESIGN NAME: RAM2GS *
 NOTE DEVICE NAME: LCMXO256C-3TQFP100 *
 NOTE PIN ASSIGNMENTS *
@@ -974,4 +974,4 @@ L00000
 C8A2C*
 N User Electronic Signature Data*
 U00000000000000000000000000000000*
-203C
+203B
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp
index 348c341..6359386 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp
@@ -17,7 +17,7 @@ Target Vendor:  LATTICE
 Target Device:  LCMXO256CTQFP100
 Target Performance:   3
 Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/15/23  05:03:20
+Mapped on:  08/15/23  05:22:22
 
 Design Summary
 --------------
@@ -66,7 +66,7 @@ Design Summary
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:20
+Design:  RAM2GS                                        Date:  08/15/23  05:22:22
 
 Design Summary (cont)
 ---------------------
@@ -132,7 +132,7 @@ IO (PIO) Attributes
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:20
+Design:  RAM2GS                                        Date:  08/15/23  05:22:22
 
 IO (PIO) Attributes (cont)
 --------------------------
@@ -198,7 +198,7 @@ IO (PIO) Attributes (cont)
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:20
+Design:  RAM2GS                                        Date:  08/15/23  05:22:22
 
 IO (PIO) Attributes (cont)
 --------------------------
@@ -264,7 +264,7 @@ IO (PIO) Attributes (cont)
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:20
+Design:  RAM2GS                                        Date:  08/15/23  05:22:22
 
 IO (PIO) Attributes (cont)
 --------------------------
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd
index 113a28f9c6cae770047794648cfe230b6cdbc83c..50d19f6b3214d5d594ea97fb943a38eef6b3ac7e 100644
GIT binary patch
delta 42
ycmezIne)eI&IzJS&gV9YYfG|KD~LrW1pw44~g+1w@B-X+Pny-SiQF985qlMZ+Q

delta 42
ycmezIne)eI&IzJS_7NM!wI$hVG$i`<^(O~PT22h$Z0?e5?~-KP-X+PDmjD1&%np43

diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad
index 4582186..f23dc0b 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad
@@ -6,7 +6,7 @@ Performance Grade:      3
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.19
 
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:28 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+------+------------------------------+
@@ -267,5 +267,5 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:28 2023
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par
index e40d29a..1416167 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par
@@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:24 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
@@ -17,18 +17,18 @@ Preference file: RAM2GS_LCMXO256C_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            -10.044      913247       0.273        0            06           Completed
+5_1   *      0            -10.044      913247       0.273        0            05           Completed
 
 * : Design saved.
 
-Total (real) run time for 1-seed: 6 secs 
+Total (real) run time for 1-seed: 5 secs 
 
 par done!
 
 Note: user must run 'Trace' for timing closure signoff.
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:24 2023
 
 PAR: Place And Route Diamond (64-bit) 3.12.1.454.
 Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
@@ -79,12 +79,12 @@ Finished Placer Phase 0.  REAL time: 0 secs
 Starting Placer Phase 1.
 ..............
 Placer score = 831129.
-Finished Placer Phase 1.  REAL time: 5 secs 
+Finished Placer Phase 1.  REAL time: 4 secs 
 
 Starting Placer Phase 2.
 .
 Placer score =  828350
-Finished Placer Phase 2.  REAL time: 5 secs 
+Finished Placer Phase 2.  REAL time: 4 secs 
 
 
 ------------------ Clock Report ------------------
@@ -118,7 +118,7 @@ I/O Bank Usage Summary:
 | 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
 +----------+----------------+------------+------------+------------+
 
-Total placer CPU time: 4 secs 
+Total placer CPU time: 3 secs 
 
 Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
 
@@ -130,9 +130,9 @@ WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=7 clock_loads=4
 
-Completed router resource preassignment. Real time: 5 secs 
+Completed router resource preassignment. Real time: 4 secs 
 
-Start NBR router at 05:03:28 08/15/23
+Start NBR router at 05:22:28 08/15/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -147,68 +147,68 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:03:28 08/15/23
+Start NBR special constraint process at 05:22:28 08/15/23
 
-Start NBR section for initial routing at 05:03:28 08/15/23
+Start NBR section for initial routing at 05:22:28 08/15/23
 Level 1, iteration 1
 0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; 
-Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 4 secs 
 Level 2, iteration 1
 3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 4 secs 
 Level 3, iteration 1
 6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 4 secs 
 Level 4, iteration 1
 17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 4 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:28 08/15/23
+Start NBR section for normal routing at 05:22:28 08/15/23
 Level 4, iteration 1
 12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 4 secs 
 Level 4, iteration 2
 6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 4 secs 
 Level 4, iteration 3
 3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 4 secs 
 Level 4, iteration 4
 3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 4 secs 
 Level 4, iteration 5
 3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 4 secs 
 Level 4, iteration 6
 1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 4 secs 
 Level 4, iteration 7
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 8
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 9
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 10
 0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:28 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 
-Start NBR section for re-routing at 05:03:29 08/15/23
+Start NBR section for re-routing at 05:22:28 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 4 secs 
 
-Start NBR section for post-routing at 05:03:29 08/15/23
+Start NBR section for post-routing at 05:22:28 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -226,8 +226,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=7 clock_loads=4
 
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
+Total CPU time 4 secs 
+Total REAL time: 5 secs 
 Completely routed.
 End of route.  662 routed (100.00%); 0 unrouted.
 
@@ -249,8 +249,8 @@ PAR_SUMMARY::Worst  slack> = 0.273
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
+Total CPU  time to completion: 4 secs 
+Total REAL time to completion: 5 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf
index 881ee9b..c16502f 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf
@@ -1,5 +1,5 @@
 SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:20 2023
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:22:22 2023
 
 SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
 LOCATE COMP "RD[7]" SITE "71" ;
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1
index 2cd86e2..58cbf13 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1
@@ -13,7 +13,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:21 2023
+Tue Aug 15 05:22:23 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -192,7 +192,7 @@ Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:21 2023
+Tue Aug 15 05:22:23 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr
index 5fca6c6..9e2cf28 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr
@@ -13,7 +13,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:29 2023
+Tue Aug 15 05:22:29 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -1158,7 +1158,7 @@ Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:29 2023
+Tue Aug 15 05:22:29 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html
index 6117b69..6b01363 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html
@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:33 2023
+Tue Aug 15 05:22:31 2023
 
 
 Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html
index e3b9e75..ed7d0f2 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html
@@ -38,7 +38,7 @@ Performance Hardware Data Status: Version 1.124.
 // Package: TQFP100
 // ncd File: ram2gs_lcmxo256c_impl1.ncd
 // Version: Diamond (64-bit) 3.12.1.454
-// Written on Tue Aug 15 05:03:30 2023
+// Written on Tue Aug 15 05:22:30 2023
 // M: Minimum Performance Grade
 // iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam
index 91ebb0b..f54188e 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam
@@ -25,7 +25,7 @@ FS_610_add_4_8/CO0
 [ END CLIPPED ]
 [ START DESIGN PREFS ]
 SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:20 2023
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:22:22 2023
 
 SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
 LOCATE COMP "RD[7]" SITE "71" ;
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd
index 0a2beec11840943a318528230a92a464a40118f8..fafeb3b72edf84b3a8c6666d1e3459a8716d013a 100644
GIT binary patch
delta 38
ucmZoU#@2F-ZGtG1^SO=U+LCP5RR+xZ`jZ1CEhh$WHg`#G?~-J!>I4A$iVT$i

delta 38
ucmZoU#@2F-ZGtG1eZ)p_ZArEoJ&WV|`jZ1CEhh$WHg`#G?~-J!>I4AyGz^>o

diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf
index 92c0943..50660db 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf
@@ -1,7 +1,7 @@
 (DELAYFILE
   (SDFVERSION "3.0")
   (DESIGN "RAM2GS")
-  (DATE "Tue Aug 15 05:03:23 2023")
+  (DATE "Tue Aug 15 05:22:24 2023")
   (VENDOR "Lattice")
   (PROGRAM "ldbanno")
   (VERSION "Diamond (64-bit) 3.12.1.454")
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho
index ab79c11..3b937df 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho
@@ -2,8 +2,8 @@
 -- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
 
 -- ldbanno -n VHDL -o RAM2GS_LCMXO256C_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd 
--- Netlist created on Tue Aug 15 05:03:20 2023
--- Netlist written on Tue Aug 15 05:03:23 2023
+-- Netlist created on Tue Aug 15 05:22:22 2023
+-- Netlist written on Tue Aug 15 05:22:24 2023
 -- Design is for device LCMXO256C
 -- Design is for package TQFP100
 -- Design is for performance grade 3
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf
index 834db9e..abfbace 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf
@@ -1,7 +1,7 @@
 (DELAYFILE
   (SDFVERSION "3.0")
   (DESIGN "RAM2GS")
-  (DATE "Tue Aug 15 05:03:22 2023")
+  (DATE "Tue Aug 15 05:22:23 2023")
   (VENDOR "Lattice")
   (PROGRAM "ldbanno")
   (VERSION "Diamond (64-bit) 3.12.1.454")
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo
index d68e04c..4211e84 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo
@@ -2,8 +2,8 @@
 // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
 
 // ldbanno -n Verilog -o RAM2GS_LCMXO256C_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd 
-// Netlist created on Tue Aug 15 05:03:20 2023
-// Netlist written on Tue Aug 15 05:03:22 2023
+// Netlist created on Tue Aug 15 05:22:22 2023
+// Netlist written on Tue Aug 15 05:22:23 2023
 // Design is for device LCMXO256C
 // Design is for package TQFP100
 // Design is for performance grade 3
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html
index 56f2c31..da1f8bc 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html
@@ -25,7 +25,7 @@ Target Vendor:  LATTICE
 Target Device:  LCMXO256CTQFP100
 Target Performance:   3
 Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/15/23  05:03:20
+Mapped on:  08/15/23  05:22:22
 
 
 Design Summary
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html
index e31d039..a80e633 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html
@@ -14,7 +14,7 @@ Performance Grade:      3
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.19
 
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:28 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+------+------------------------------+
@@ -276,7 +276,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:28 2023
 
 
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html
index f78605b..ef212c8 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html
@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:24 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
@@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO256C_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            -10.044      913247       0.273        0            06           Completed
+5_1   *      0            -10.044      913247       0.273        0            05           Completed
 * : Design saved.
 
-Total (real) run time for 1-seed: 6 secs 
+Total (real) run time for 1-seed: 5 secs 
 
 par done!
 
 Note: user must run 'Trace' for timing closure signoff.
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:24 2023
 
 
 Best Par Run
@@ -90,12 +90,12 @@ Finished Placer Phase 0.  REAL time: 0 secs
 Starting Placer Phase 1.
 ..............
 Placer score = 831129.
-Finished Placer Phase 1.  REAL time: 5 secs 
+Finished Placer Phase 1.  REAL time: 4 secs 
 
 Starting Placer Phase 2.
 .
 Placer score =  828350
-Finished Placer Phase 2.  REAL time: 5 secs 
+Finished Placer Phase 2.  REAL time: 4 secs 
 
 
 
@@ -130,7 +130,7 @@ I/O Bank Usage Summary:
 | 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
 +----------+----------------+------------+------------+------------+
 
-Total placer CPU time: 4 secs 
+Total placer CPU time: 3 secs 
 
 Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
 
@@ -142,9 +142,9 @@ WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=7 clock_loads=4
 
-Completed router resource preassignment. Real time: 5 secs 
+Completed router resource preassignment. Real time: 4 secs 
 
-Start NBR router at 05:03:28 08/15/23
+Start NBR router at 05:22:28 08/15/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -159,68 +159,68 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:03:28 08/15/23
+Start NBR special constraint process at 05:22:28 08/15/23
 
-Start NBR section for initial routing at 05:03:28 08/15/23
+Start NBR section for initial routing at 05:22:28 08/15/23
 Level 1, iteration 1
 0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -9.968ns/-712.361ns; real time: 5 secs 
+Estimated worst slack/total negative slack<setup>: -9.968ns/-712.361ns; real time: 4 secs 
 Level 2, iteration 1
 3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-697.746ns; real time: 5 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-697.746ns; real time: 4 secs 
 Level 3, iteration 1
 6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-756.550ns; real time: 5 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-756.550ns; real time: 4 secs 
 Level 4, iteration 1
 17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-761.256ns; real time: 5 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-761.256ns; real time: 4 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:28 08/15/23
+Start NBR section for normal routing at 05:22:28 08/15/23
 Level 4, iteration 1
 12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-765.606ns; real time: 5 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-765.606ns; real time: 4 secs 
 Level 4, iteration 2
 6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-766.424ns; real time: 5 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-766.424ns; real time: 4 secs 
 Level 4, iteration 3
 3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-769.149ns; real time: 5 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-769.149ns; real time: 4 secs 
 Level 4, iteration 4
 3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-769.149ns; real time: 5 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-769.149ns; real time: 4 secs 
 Level 4, iteration 5
 3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-766.524ns; real time: 5 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-766.524ns; real time: 4 secs 
 Level 4, iteration 6
 1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-766.524ns; real time: 5 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-766.524ns; real time: 4 secs 
 Level 4, iteration 7
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 8
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 9
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 10
 0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 4 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:28 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 4 secs 
 
-Start NBR section for re-routing at 05:03:29 08/15/23
+Start NBR section for re-routing at 05:22:28 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -10.044ns/-768.049ns; real time: 6 secs 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-768.049ns; real time: 4 secs 
 
-Start NBR section for post-routing at 05:03:29 08/15/23
+Start NBR section for post-routing at 05:22:28 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -238,8 +238,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=7 clock_loads=4
 
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
+Total CPU time 4 secs 
+Total REAL time: 5 secs 
 Completely routed.
 End of route.  662 routed (100.00%); 0 unrouted.
 
@@ -261,8 +261,8 @@ PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.273
 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
+Total CPU  time to completion: 4 secs 
+Total REAL time to completion: 5 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html
index 3f88aa1..1c3f206 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html
@@ -62,7 +62,7 @@
 
 
 Updated:
-2023/08/15 05:03:37
+2023/08/15 05:22:34
 
 
 Implementation Location:
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html
index 40eaf8f..913ef1a 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:21 2023
+Tue Aug 15 05:22:23 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -211,7 +211,7 @@ Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:21 2023
+Tue Aug 15 05:22:23 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html
index d7e5a9f..db2edb1 100644
--- a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html
+++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:29 2023
+Tue Aug 15 05:22:29 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -1177,7 +1177,7 @@ Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:29 2023
+Tue Aug 15 05:22:29 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO256C/impl1/automake.log b/CPLD/LCMXO256C/impl1/automake.log
index 0229264..6f30e7a 100644
--- a/CPLD/LCMXO256C/impl1/automake.log
+++ b/CPLD/LCMXO256C/impl1/automake.log
@@ -1,255 +1,4 @@
 
-synthesis -f "RAM2GS_LCMXO256C_impl1_lattice.synproj"
-synthesis:  version Diamond (64-bit) 3.12.1.454
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:20 2023
-
-
-Command Line:  synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml 
-
-    
-Synthesis options:
-The -a option is MachXO.
-The -s option is 3.
-The -t option is TQFP100.
-The -d option is LCMXO256C.
-Using package TQFP100.
-Using performance grade 3.
-                                                          
-
-##########################################################
-
-### Lattice Family : MachXO
-
-### Device  : LCMXO256C
-
-### Package : TQFP100
-
-### Speed   : 3
-
-##########################################################
-
-                                                          
-
-    
-Optimization goal = Balanced
-Top-level module name = RAM2GS.
-Target frequency = 200.000000 MHz.
-Maximum fanout = 1000.
-Timing path count = 3
-BRAM utilization = 100.000000 %
-DSP usage = true
-DSP utilization = 100.000000 %
-fsm_encoding_style = auto
-resolve_mixed_drivers = 0
-fix_gated_clocks = 1
-
-Mux style = Auto
-Use Carry Chain = true
-carry_chain_length = 0
-Loop Limit = 1950.
-Use IO Insertion = TRUE
-Use IO Reg = AUTO
-
-Resource Sharing = TRUE
-Propagate Constants = TRUE
-Remove Duplicate Registers = TRUE
-force_gsr = auto
-ROM style = auto
-RAM style = auto
-The -comp option is FALSE.
-The -syn option is FALSE.
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added)
--p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1 (searchpath added)
--p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added)
-Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
-NGD file = RAM2GS_LCMXO256C_impl1.ngd
--sdc option: SDC file input not used.
--lpf option: Output file option is ON.
-Hardtimer checking is enabled (default). The -dt option is not used.
-The -r option is OFF. [ Remove LOC Properties is OFF. ]
-Technology check ok...
-
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
-Compile design.
-Compile Design Begin
-Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
-Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
-Top module name (Verilog): RAM2GS
-    
-    
-    
-    
-Last elaborated design is RAM2GS()
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Top-level module name = RAM2GS.
-    
-original encoding -> new encoding (one-hot encoding)
-
- 0000 -> 0000000000000001
-
- 0001 -> 0000000000000010
-
- 0010 -> 0000000000000100
-
- 0011 -> 0000000000001000
-
- 0100 -> 0000000000010000
-
- 0101 -> 0000000000100000
-
- 0110 -> 0000000001000000
-
- 0111 -> 0000000010000000
-
- 1000 -> 0000000100000000
-
- 1001 -> 0000001000000000
-
- 1010 -> 0000010000000000
-
- 1011 -> 0000100000000000
-
- 1100 -> 0001000000000000
-
- 1101 -> 0010000000000000
-
- 1110 -> 0100000000000000
-
- 1111 -> 1000000000000000
-
-    
-original encoding -> new encoding (one-hot encoding)
-
- 00 -> 0001
-
- 01 -> 0010
-
- 10 -> 0100
-
- 11 -> 1000
-
-
-
-
-GSR will not be inferred because no asynchronous signal was found in the netlist.
-    
-Applying 200.000000 MHz constraint to all clocks
-
-    
-Results of NGD DRC are available in RAM2GS_drc.log.
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
-
-
-Running DRC...
-
-DRC complete with no errors or warnings
-
-Design Results:
-    318 blocks expanded
-completed the first expansion
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
-
-################### Begin Area Report (RAM2GS)######################
-Number of register bits => 102 of 490 (20 % )
-BB => 8
-CCU2 => 9
-FD1P3AX => 28
-FD1P3AY => 3
-FD1P3IX => 2
-FD1S3AX => 47
-FD1S3AY => 1
-FD1S3IX => 16
-FD1S3JX => 5
-GSR => 1
-IB => 26
-INV => 3
-OB => 33
-ORCALUT4 => 127
-PFUMX => 6
-################### End Area Report ##################
-
-################### Begin BlackBox Report ######################
-TSALL => 1
-################### End BlackBox Report ##################
-
-################### Begin Clock Report ######################
-Clock Nets
-Number of Clocks: 4
-  Net : RCLK_c, loads : 62
-  Net : PHI2_c, loads : 11
-  Net : nCCAS_c, loads : 2
-  Net : nCRAS_c, loads : 2
-Clock Enable Nets
-Number of Clock Enables: 13
-Top 10 highest fanout Clock Enables:
-  Net : RCLK_c_enable_23, loads : 16
-  Net : RCLK_c_enable_4, loads : 3
-  Net : PHI2_N_120_enable_6, loads : 3
-  Net : RCLK_c_enable_24, loads : 2
-  Net : RCLK_c_enable_12, loads : 1
-  Net : PHI2_N_120_enable_1, loads : 1
-  Net : PHI2_N_120_enable_4, loads : 1
-  Net : RCLK_c_enable_3, loads : 1
-  Net : PHI2_N_120_enable_5, loads : 1
-  Net : RCLK_c_enable_11, loads : 1
-Highest fanout non-clock nets
-Top 10 highest fanout non-clock nets:
-  Net : InitReady, loads : 17
-  Net : Ready, loads : 17
-  Net : RCLK_c_enable_23, loads : 16
-  Net : nCRAS_N_9, loads : 15
-  Net : RASr2, loads : 13
-  Net : nRowColSel, loads : 13
-  Net : n2477, loads : 13
-  Net : MAin_c_0, loads : 12
-  Net : nRowColSel_N_35, loads : 12
-  Net : Din_c_6, loads : 11
-################### End Clock Report ##################
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk1 [get_nets PHI2_c]                  |  200.000 MHz|   45.147 MHz|     6 *
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets RCLK_c]                  |  200.000 MHz|  106.792 MHz|     5 *
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
-
-Peak Memory Usage: 50.672  MB
-
---------------------------------------------------------------
-Elapsed CPU time for LSE flow : 0.516  secs
---------------------------------------------------------------
-
 map -a "MachXO" -p LCMXO256C -t TQFP100 -s 3 -oc Commercial   "RAM2GS_LCMXO256C_impl1.ngd" -o "RAM2GS_LCMXO256C_impl1_map.ncd" -pr "RAM2GS_LCMXO256C_impl1.prf" -mp "RAM2GS_LCMXO256C_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf"  -c 0           
 map:  version Diamond (64-bit) 3.12.1.454
 
@@ -407,7 +156,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:21 2023
+Tue Aug 15 05:22:23 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -441,7 +190,7 @@ Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:21 2023
+Tue Aug 15 05:22:23 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -554,7 +303,7 @@ Removing old design directory at request of -rem command line option to this pro
 Running par. Please wait . . .
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:24 2023
 
 PAR: Place And Route Diamond (64-bit) 3.12.1.454.
 Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
@@ -605,12 +354,12 @@ Finished Placer Phase 0.  REAL time: 0 secs
 Starting Placer Phase 1.
 ..............
 Placer score = 831129.
-Finished Placer Phase 1.  REAL time: 5 secs 
+Finished Placer Phase 1.  REAL time: 4 secs 
 
 Starting Placer Phase 2.
 .
 Placer score =  828350
-Finished Placer Phase 2.  REAL time: 5 secs 
+Finished Placer Phase 2.  REAL time: 4 secs 
 
 
 ------------------ Clock Report ------------------
@@ -644,7 +393,7 @@ I/O Bank Usage Summary:
 | 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
 +----------+----------------+------------+------------+------------+
 
-Total placer CPU time: 4 secs 
+Total placer CPU time: 3 secs 
 
 Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
 
@@ -655,9 +404,9 @@ Starting router resource preassignment
 
     
 
-Completed router resource preassignment. Real time: 5 secs 
+Completed router resource preassignment. Real time: 4 secs 
 
-Start NBR router at 05:03:28 08/15/23
+Start NBR router at 05:22:28 08/15/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -672,68 +421,68 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:03:28 08/15/23
+Start NBR special constraint process at 05:22:28 08/15/23
 
-Start NBR section for initial routing at 05:03:28 08/15/23
+Start NBR section for initial routing at 05:22:28 08/15/23
 Level 1, iteration 1
 0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; 
-Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 4 secs 
 Level 2, iteration 1
 3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 4 secs 
 Level 3, iteration 1
 6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 4 secs 
 Level 4, iteration 1
 17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 4 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:28 08/15/23
+Start NBR section for normal routing at 05:22:28 08/15/23
 Level 4, iteration 1
 12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 4 secs 
 Level 4, iteration 2
 6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 4 secs 
 Level 4, iteration 3
 3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 4 secs 
 Level 4, iteration 4
 3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 4 secs 
 Level 4, iteration 5
 3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 4 secs 
 Level 4, iteration 6
 1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs 
+Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 4 secs 
 Level 4, iteration 7
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 8
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 9
 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 Level 4, iteration 10
 0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:28 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 4 secs 
 
-Start NBR section for re-routing at 05:03:29 08/15/23
+Start NBR section for re-routing at 05:22:28 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; 
-Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 6 secs 
+Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 4 secs 
 
-Start NBR section for post-routing at 05:03:29 08/15/23
+Start NBR section for post-routing at 05:22:28 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -750,8 +499,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 
     
 
-Total CPU time 5 secs 
-Total REAL time: 6 secs 
+Total CPU time 4 secs 
+Total REAL time: 5 secs 
 Completely routed.
 End of route.  662 routed (100.00%); 0 unrouted.
 
@@ -770,8 +519,8 @@ PAR_SUMMARY::Worst  slack> = 0.273
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 5 secs 
-Total REAL time to completion: 6 secs 
+Total CPU  time to completion: 4 secs 
+Total REAL time to completion: 5 secs 
 
 par done!
 
@@ -808,7 +557,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:29 2023
+Tue Aug 15 05:22:29 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -842,7 +591,7 @@ Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:29 2023
+Tue Aug 15 05:22:29 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -887,7 +636,7 @@ Cumulative negative slack: 638389 (638389+0)
 
 Total CPU Time: 0 secs 
 Total REAL Time: 0 secs 
-Peak Memory Usage: 31 MB
+Peak Memory Usage: 30 MB
 
 
 iotiming  "RAM2GS_LCMXO256C_impl1.ncd" "RAM2GS_LCMXO256C_impl1.prf"
diff --git a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
index 83e2eca..e6db8e8 100644
--- a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
+++ b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior
@@ -29,7 +29,7 @@ Performance Hardware Data Status: Version 1.124.
 // Package: TQFP100
 // ncd File: ram2gs_lcmxo256c_impl1.ncd
 // Version: Diamond (64-bit) 3.12.1.454
-// Written on Tue Aug 15 05:03:30 2023
+// Written on Tue Aug 15 05:22:30 2023
 // M: Minimum Performance Grade
 // iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
 
diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf
index 20835a0..aaf6357 100644
--- a/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf
+++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf
@@ -13,5 +13,5 @@
             
         
     
-    
+    
 
diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO256C1.sty b/CPLD/LCMXO640C/RAM2GS_LCMXO640C1.sty
similarity index 100%
rename from CPLD/LCMXO640C/RAM2GS_LCMXO256C1.sty
rename to CPLD/LCMXO640C/RAM2GS_LCMXO640C1.sty
diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230815052236.tcr b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230815052236.tcr
new file mode 100644
index 0000000..cf51d68
--- /dev/null
+++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230815052236.tcr
@@ -0,0 +1,5 @@
+#Start recording tcl command: 8/15/2023 05:21:29
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+prj_run Export -impl impl1
+#Stop recording: 8/15/2023 05:22:36
diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230815052239.tcr b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230815052239.tcr
new file mode 100644
index 0000000..2c943d2
--- /dev/null
+++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C_tcr.dir/pn230815052239.tcr
@@ -0,0 +1,7 @@
+#Start recording tcl command: 8/15/2023 05:22:18
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
+prj_run Export -impl impl1
+prj_run Export -impl impl1
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/15/2023 05:22:39
diff --git a/CPLD/LCMXO640C/impl1/.build_status b/CPLD/LCMXO640C/impl1/.build_status
index a3a7abe..73ea0de 100644
--- a/CPLD/LCMXO640C/impl1/.build_status
+++ b/CPLD/LCMXO640C/impl1/.build_status
@@ -5,23 +5,23 @@
             
             
             
-            
+            
         
-        
-            
-            
-            
-            
-            
+        
+            
+            
+            
+            
+            
         
-        
-            
-            
-            
+        
+            
+            
+            
         
-        
-            
-            
+        
+            
+            
         
         
             
@@ -31,7 +31,7 @@
             
         
         
-        
+        
         
         
         
@@ -42,19 +42,19 @@
         
         
         
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
     
 
diff --git a/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb b/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb
index 085d429eac00e43d373fed4d0f5e9df9fee0e707..faf0c974f641556250b697c1ff0693890c09ba68 100644
GIT binary patch
delta 270
zcmccriuwL4W)ZaZB0Fska7(txLI~db|
z)Mf>ynT#NMH*+$Go~*#S9Yoz^tp-tHY{?*MH(Mfzl4FkmQ5Eb-AnFeLJ|MMu4#!%s
z0p477Y#{z=0SN6aZXpFy)@s-b5*9J~$qJ(REx5t<$XLdLWUC?6EeK_4l?hU_#EO{-
uB)QTi0mS9D)dibu<$MIBb&@Mc(d2B`J`nZW737V{$!=9ZYV&=!hIIh5Vq}v5

delta 270
zcmccriuwL4W)ZaiUoPgY>v4x(Vi$Say|mmI>{BJXmYk|ABg(x3i8I}WVb3HwfVkV!#V(gB2*gy

diff --git a/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_rtl.vdb
index b71a278d29397168035966e95405b843027f4f00..4c69f53b6f127b93e913baba032b663155c98468 100644
GIT binary patch
delta 308
zcmaEIgyqQ*77?`^d1ejXjJy|}Z>RhRi83=VwoFzO)Sm3k
zq|bEGd2EwFm*)r4
zlgs=nLEMjiv0&kV)QyZFK683A2Z-*--wNj27aB4_9KgZA!Js(#p?%`!+r=$xAT^0q
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zyZz>F-a4=W+=6}}^P&YO@Pg>Ka`IqdKBY(yH&f{-h`ZT9?I{z87T2^91JR-O^87%0
za+zNxi2Knm7Azc)x{(pYXHIYC0MQ-!Tfuz$LPI8q12`Bs7!)Tzv`^f8ySRl7q$aUy
kJu8S7YA6QrfnKqgyuS_X729@|$pYSasHz6hGEk
zt4(1aY-5;l1``IgDh#F-Ymfd=@dG;CV4bvOKZJb{aoZ2UzZ-K{eb2ek&HLw`_q@+}
z&N5lRh?~tW$J)B*8*Rt&GfsYCdiq|
zzXVp<1~R`Y%g}GHGXjQlrEP9sG~4oX?_;7<9m@LsN({bdL#zMgfId
z0TX)!%(n#*7JN!~SX1$l`hU!C2?3*>8ope4mSc-?12u7r?UD2l_Ec3Vl=!>qAdFSl
z+2&Sa(mgserMf=B+um20UGW{_NPjd7_m|wIL{`WI%l9I*uP%pGVF6!PXqa1ihGAAH
z2`6@N0n#t<{Ic)aUyL8eYQIS~rUM_dFTLM{v9)e6^vmS_SC5pS+$$DpPbuYdq>Sot
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z-W&Xz%!NbONvsrW1pw44~g+1w@B-X+Pny-SkmRtf-LN)IOh

delta 42
ycmaFzhx5rF&IzJS_E8(fwI$hVG$i`<^(O~PT22h$Z0?e5?~-KP-X+O&D+K^kTMpR(

diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad
index 124dd5c..ea76665 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad
@@ -6,7 +6,7 @@ Performance Grade:      3
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.17
 
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:31 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+------------------------------+
@@ -349,5 +349,5 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:31 2023
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par
index ac4e203..7edc928 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par
@@ -1,6 +1,6 @@
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
-Tue Aug 15 05:03:25 2023
+Tue Aug 15 05:22:28 2023
 
 PAR: Place And Route Diamond (64-bit) 3.12.1.454.
 Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
@@ -92,7 +92,7 @@ I/O Bank Usage Summary:
 | 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
 +----------+----------------+------------+------------+------------+
 
-Total placer CPU time: 3 secs 
+Total placer CPU time: 2 secs 
 
 Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
 
@@ -106,7 +106,7 @@ WARNING - par: The following clock signals will be routed by using generic routi
 
 Completed router resource preassignment. Real time: 3 secs 
 
-Start NBR router at 05:03:28 08/15/23
+Start NBR router at 05:22:31 08/15/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -121,9 +121,9 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:03:28 08/15/23
+Start NBR special constraint process at 05:22:31 08/15/23
 
-Start NBR section for initial routing at 05:03:28 08/15/23
+Start NBR section for initial routing at 05:22:31 08/15/23
 Level 1, iteration 1
 0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; 
 Estimated worst slack/total negative slack: -9.776ns/-717.961ns; real time: 3 secs 
@@ -135,42 +135,42 @@ Level 3, iteration 1
 Estimated worst slack/total negative slack: -9.822ns/-765.746ns; real time: 3 secs 
 Level 4, iteration 1
 9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 3 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:29 08/15/23
+Start NBR section for normal routing at 05:22:31 08/15/23
 Level 4, iteration 1
 5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 3 secs 
 Level 4, iteration 2
 4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 3 secs 
 Level 4, iteration 3
 4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 3 secs 
 Level 4, iteration 4
 2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 3 secs 
 Level 4, iteration 5
 2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs 
 Level 4, iteration 6
 0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:31 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs 
 
-Start NBR section for re-routing at 05:03:29 08/15/23
+Start NBR section for re-routing at 05:22:31 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 3 secs 
 
-Start NBR section for post-routing at 05:03:29 08/15/23
+Start NBR section for post-routing at 05:22:31 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -188,8 +188,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=7 clock_loads=4
 
-Total CPU time 4 secs 
-Total REAL time: 4 secs 
+Total CPU time 2 secs 
+Total REAL time: 3 secs 
 Completely routed.
 End of route.  662 routed (100.00%); 0 unrouted.
 
@@ -211,8 +211,8 @@ PAR_SUMMARY::Worst  slack> = 0.273
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 4 secs 
-Total REAL time to completion: 4 secs 
+Total CPU  time to completion: 2 secs 
+Total REAL time to completion: 3 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
index cce2773..ded0f6a 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par
@@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:25 2023
+Tue Aug 15 05:22:28 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
@@ -17,11 +17,11 @@ Preference file: RAM2GS_LCMXO640C_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            -9.822       909228       0.273        0            04           Completed
+5_1   *      0            -9.822       909228       0.273        0            03           Completed
 
 * : Design saved.
 
-Total (real) run time for 1-seed: 4 secs 
+Total (real) run time for 1-seed: 3 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
index b2ff5f6..37c0f68 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed
@@ -6,7 +6,7 @@ NOTE Readback:       Off*
 NOTE Security:      Off*
 NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
 NOTE All Rights Reserved *
-NOTE DATE CREATED: Tue Aug 15 05:03:33 2023 *
+NOTE DATE CREATED: Tue Aug 15 05:22:34 2023 *
 NOTE DESIGN NAME: RAM2GS *
 NOTE DEVICE NAME: LCMXO640C-3TQFP100 *
 NOTE PIN ASSIGNMENTS *
@@ -1742,4 +1742,4 @@ L000000
 C2594*
 N User Electronic Signature Data*
 U00000000000000000000000000000000*
-451D
+451F
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
index e44642b..8b62220 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp
@@ -17,7 +17,7 @@ Target Vendor:  LATTICE
 Target Device:  LCMXO640CTQFP100
 Target Performance:   3
 Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  08/15/23  05:03:22
+Mapped on:  08/15/23  05:22:26
 
 Design Summary
 --------------
@@ -66,7 +66,7 @@ Design Summary
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:22
+Design:  RAM2GS                                        Date:  08/15/23  05:22:26
 
 Design Summary (cont)
 ---------------------
@@ -132,7 +132,7 @@ IO (PIO) Attributes
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:22
+Design:  RAM2GS                                        Date:  08/15/23  05:22:26
 
 IO (PIO) Attributes (cont)
 --------------------------
@@ -198,7 +198,7 @@ IO (PIO) Attributes (cont)
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:22
+Design:  RAM2GS                                        Date:  08/15/23  05:22:26
 
 IO (PIO) Attributes (cont)
 --------------------------
@@ -264,7 +264,7 @@ IO (PIO) Attributes (cont)
 
 
 
-Design:  RAM2GS                                        Date:  08/15/23  05:03:22
+Design:  RAM2GS                                        Date:  08/15/23  05:22:26
 
 IO (PIO) Attributes (cont)
 --------------------------
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd
index 405a3aa5b24a3654c262d61b46b40f69d2d492db..05a4ffee0693e8b4f1f1500338803a51b70b5b05 100644
GIT binary patch
delta 42
ycmaFzhx5rF&IzJS&X+cdYfG|Kmk7w|>rW1pw44~g+1w@B-X+Pny-SkmRtf-LN)IOh

delta 42
ycmaFzhx5rF&IzJS_E8(fwI$hVG$i`<^(O~PT22h$Z0?e5?~-KP-X+O&D+K^kTMpR(

diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd
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zlM}7e!M@fJt+`-d92c#5*vg648DMY7h}L|}m6gu~d!sAZ0hi`GK0SIgESu-B$I
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diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad
index 124dd5c..ea76665 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad
@@ -6,7 +6,7 @@ Performance Grade:      3
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.17
 
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:31 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+------------------------------+
@@ -349,5 +349,5 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:31 2023
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par
index ca08894..a861001 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par
@@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:25 2023
+Tue Aug 15 05:22:28 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
@@ -17,18 +17,18 @@ Preference file: RAM2GS_LCMXO640C_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            -9.822       909228       0.273        0            04           Completed
+5_1   *      0            -9.822       909228       0.273        0            03           Completed
 
 * : Design saved.
 
-Total (real) run time for 1-seed: 4 secs 
+Total (real) run time for 1-seed: 3 secs 
 
 par done!
 
 Note: user must run 'Trace' for timing closure signoff.
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
-Tue Aug 15 05:03:25 2023
+Tue Aug 15 05:22:28 2023
 
 PAR: Place And Route Diamond (64-bit) 3.12.1.454.
 Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
@@ -120,7 +120,7 @@ I/O Bank Usage Summary:
 | 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
 +----------+----------------+------------+------------+------------+
 
-Total placer CPU time: 3 secs 
+Total placer CPU time: 2 secs 
 
 Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
 
@@ -134,7 +134,7 @@ WARNING - par: The following clock signals will be routed by using generic routi
 
 Completed router resource preassignment. Real time: 3 secs 
 
-Start NBR router at 05:03:28 08/15/23
+Start NBR router at 05:22:31 08/15/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -149,9 +149,9 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:03:28 08/15/23
+Start NBR special constraint process at 05:22:31 08/15/23
 
-Start NBR section for initial routing at 05:03:28 08/15/23
+Start NBR section for initial routing at 05:22:31 08/15/23
 Level 1, iteration 1
 0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; 
 Estimated worst slack/total negative slack: -9.776ns/-717.961ns; real time: 3 secs 
@@ -163,42 +163,42 @@ Level 3, iteration 1
 Estimated worst slack/total negative slack: -9.822ns/-765.746ns; real time: 3 secs 
 Level 4, iteration 1
 9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 3 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:29 08/15/23
+Start NBR section for normal routing at 05:22:31 08/15/23
 Level 4, iteration 1
 5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 3 secs 
 Level 4, iteration 2
 4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 3 secs 
 Level 4, iteration 3
 4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 3 secs 
 Level 4, iteration 4
 2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 3 secs 
 Level 4, iteration 5
 2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs 
 Level 4, iteration 6
 0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:31 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs 
 
-Start NBR section for re-routing at 05:03:29 08/15/23
+Start NBR section for re-routing at 05:22:31 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 3 secs 
 
-Start NBR section for post-routing at 05:03:29 08/15/23
+Start NBR section for post-routing at 05:22:31 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -216,8 +216,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=7 clock_loads=4
 
-Total CPU time 4 secs 
-Total REAL time: 4 secs 
+Total CPU time 2 secs 
+Total REAL time: 3 secs 
 Completely routed.
 End of route.  662 routed (100.00%); 0 unrouted.
 
@@ -239,8 +239,8 @@ PAR_SUMMARY::Worst  slack> = 0.273
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 4 secs 
-Total REAL time to completion: 4 secs 
+Total CPU  time to completion: 2 secs 
+Total REAL time to completion: 3 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
index 5fdb83b..8539360 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf
@@ -1,5 +1,5 @@
 SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:22 2023
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:22:26 2023
 
 SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
 LOCATE COMP "RD[7]" SITE "71" ;
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
index f6f527e..9757fa0 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1
@@ -13,7 +13,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:27 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -192,7 +192,7 @@ Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:27 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
index 5ebed7c..2686699 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr
@@ -13,7 +13,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:29 2023
+Tue Aug 15 05:22:32 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -1149,7 +1149,7 @@ Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:30 2023
+Tue Aug 15 05:22:32 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
index c5459ef..04b8fde 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html
@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:32 2023
+Tue Aug 15 05:22:34 2023
 
 
 Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html
index 3bd2593..da47985 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html
@@ -38,7 +38,7 @@ Performance Hardware Data Status: Version 1.124.
 // Package: TQFP100
 // ncd File: ram2gs_lcmxo640c_impl1.ncd
 // Version: Diamond (64-bit) 3.12.1.454
-// Written on Tue Aug 15 05:03:31 2023
+// Written on Tue Aug 15 05:22:32 2023
 // M: Minimum Performance Grade
 // iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam
index 99dec6c..3b97902 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam
@@ -25,7 +25,7 @@ FS_610_add_4_8/CO0
 [ END CLIPPED ]
 [ START DESIGN PREFS ]
 SCHEMATIC START ;
-# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:22 2023
+# map:  version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:22:26 2023
 
 SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
 LOCATE COMP "RD[7]" SITE "71" ;
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd
index 43f5ab2073024f83d3e89b144bd43421e8eea0f6..6e41ec921d3806d31177a8a46b9e54421f86b038 100644
GIT binary patch
delta 38
ucmeA>#@2U?ZGtG1^QDdA+LCP5N=khC`jZ1CEhh$WHg`#G?~-I}=>!1xX$)Kd

delta 38
ucmeA>#@2U?ZGtG1ebh#AZArEoCc`p){mFrnmJDesign Summary
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
index 3b975e0..add4846 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html
@@ -14,7 +14,7 @@ Performance Grade:      3
 PACKAGE:          TQFP100
 Package Status:                     Final          Version 1.17
 
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:31 2023
 
 Pinout by Port Name:
 +-----------+----------+---------------+-------+------------------------------+
@@ -358,7 +358,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:28 2023
+Tue Aug 15 05:22:31 2023
 
 
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
index d480245..8960d78 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html
@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:25 2023
+Tue Aug 15 05:22:28 2023
 
 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
@@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO640C_impl1.prf.
 Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
 Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
 ----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            -9.822       909228       0.273        0            04           Completed
+5_1   *      0            -9.822       909228       0.273        0            03           Completed
 * : Design saved.
 
-Total (real) run time for 1-seed: 4 secs 
+Total (real) run time for 1-seed: 3 secs 
 
 par done!
 
 Note: user must run 'Trace' for timing closure signoff.
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
-Tue Aug 15 05:03:25 2023
+Tue Aug 15 05:22:28 2023
 
 
 Best Par Run
@@ -132,7 +132,7 @@ I/O Bank Usage Summary:
 | 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
 +----------+----------------+------------+------------+------------+
 
-Total placer CPU time: 3 secs 
+Total placer CPU time: 2 secs 
 
 Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
 
@@ -146,7 +146,7 @@ WARNING - par: The following clock signals will be routed by using generic routi
 
 Completed router resource preassignment. Real time: 3 secs 
 
-Start NBR router at 05:03:28 08/15/23
+Start NBR router at 05:22:31 08/15/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -161,9 +161,9 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:03:28 08/15/23
+Start NBR special constraint process at 05:22:31 08/15/23
 
-Start NBR section for initial routing at 05:03:28 08/15/23
+Start NBR section for initial routing at 05:22:31 08/15/23
 Level 1, iteration 1
 0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; 
 Estimated worst slack/total negative slack<setup>: -9.776ns/-717.961ns; real time: 3 secs 
@@ -175,42 +175,42 @@ Level 3, iteration 1
 Estimated worst slack/total negative slack<setup>: -9.822ns/-765.746ns; real time: 3 secs 
 Level 4, iteration 1
 9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -9.822ns/-781.821ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-781.821ns; real time: 3 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:29 08/15/23
+Start NBR section for normal routing at 05:22:31 08/15/23
 Level 4, iteration 1
 5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -9.822ns/-781.049ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-781.049ns; real time: 3 secs 
 Level 4, iteration 2
 4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -9.822ns/-780.691ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-780.691ns; real time: 3 secs 
 Level 4, iteration 3
 4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -9.822ns/-780.716ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-780.716ns; real time: 3 secs 
 Level 4, iteration 4
 2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -9.822ns/-780.716ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-780.716ns; real time: 3 secs 
 Level 4, iteration 5
 2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 3 secs 
 Level 4, iteration 6
 0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 3 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:31 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 3 secs 
 
-Start NBR section for re-routing at 05:03:29 08/15/23
+Start NBR section for re-routing at 05:22:31 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -9.822ns/-776.979ns; real time: 4 secs 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-776.979ns; real time: 3 secs 
 
-Start NBR section for post-routing at 05:03:29 08/15/23
+Start NBR section for post-routing at 05:22:31 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -228,8 +228,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
    Signal=nCCAS_c loads=7 clock_loads=4
 
-Total CPU time 4 secs 
-Total REAL time: 4 secs 
+Total CPU time 2 secs 
+Total REAL time: 3 secs 
 Completely routed.
 End of route.  662 routed (100.00%); 0 unrouted.
 
@@ -251,8 +251,8 @@ PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.273
 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 4 secs 
-Total REAL time to completion: 4 secs 
+Total CPU  time to completion: 2 secs 
+Total REAL time to completion: 3 secs 
 
 par done!
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
index e2f5eb9..01fe3e9 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html
@@ -62,7 +62,7 @@
 
 
 Updated:
-2023/08/15 05:03:36
+2023/08/15 05:22:37
 
 
 Implementation Location:
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
index 4f20fac..ae537eb 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:27 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -211,7 +211,7 @@ Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:27 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
index eb0175c..aa8741e 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
@@ -22,7 +22,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:29 2023
+Tue Aug 15 05:22:32 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -1168,7 +1168,7 @@ Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:30 2023
+Tue Aug 15 05:22:32 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_lse.twr b/CPLD/LCMXO640C/impl1/RAM2GS_lse.twr
index 4779f7d..7774bff 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_lse.twr
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_lse.twr
@@ -1,6 +1,6 @@
 --------------------------------------------------------------------------------
 Lattice Synthesis Timing Report, Version  
-Tue Aug 15 05:03:22 2023
+Tue Aug 15 05:22:26 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -287,5 +287,5 @@ Timing errors: 346  Score: 1874657
 Constraints cover  476 paths, 187 nets, and 480 connections (64.3% coverage)
 
 
-Peak memory: 53284864 bytes, TRCE: 1122304 bytes, DLYMAN: 167936 bytes
+Peak memory: 53297152 bytes, TRCE: 1138688 bytes, DLYMAN: 167936 bytes
 CPU_TIME_REPORT: 0 secs 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html
index d5f78c7..5b0fd29 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html
@@ -9,7 +9,7 @@
 
    Lattice Synthesis Timing Report
 --------------------------------------------------------------------------------
 Lattice Synthesis Timing Report, Version  
-Tue Aug 15 05:03:22 2023
+Tue Aug 15 05:22:26 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -296,7 +296,7 @@ Timing errors: 346  Score: 1874657
 Constraints cover  476 paths, 187 nets, and 480 connections (64.3% coverage)
 
 
-Peak memory: 53284864 bytes, TRCE: 1122304 bytes, DLYMAN: 167936 bytes
+Peak memory: 53297152 bytes, TRCE: 1138688 bytes, DLYMAN: 167936 bytes
 CPU_TIME_REPORT: 0 secs 
 
 
diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_prim.v b/CPLD/LCMXO640C/impl1/RAM2GS_prim.v
index d45f192..5a8f76b 100644
--- a/CPLD/LCMXO640C/impl1/RAM2GS_prim.v
+++ b/CPLD/LCMXO640C/impl1/RAM2GS_prim.v
@@ -1,5 +1,5 @@
 // Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.1.454
-// Netlist written on Tue Aug 15 05:03:22 2023
+// Netlist written on Tue Aug 15 05:22:26 2023
 //
 // Verilog Description of module RAM2GS
 //
diff --git a/CPLD/LCMXO640C/impl1/automake.log b/CPLD/LCMXO640C/impl1/automake.log
index ba3df24..64bbc02 100644
--- a/CPLD/LCMXO640C/impl1/automake.log
+++ b/CPLD/LCMXO640C/impl1/automake.log
@@ -7,7 +7,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:21 2023
+Tue Aug 15 05:22:25 2023
 
 
 Command Line:  synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml 
@@ -244,7 +244,7 @@ clk0 [get_nets RCLK_c]                  |  200.000 MHz|  106.792 MHz|     5 *
 2 constraints not met.
 
 
-Peak Memory Usage: 51.215  MB
+Peak Memory Usage: 51.176  MB
 
 --------------------------------------------------------------
 Elapsed CPU time for LSE flow : 0.609  secs
@@ -407,7 +407,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:27 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -441,7 +441,7 @@ Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:23 2023
+Tue Aug 15 05:22:27 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -554,7 +554,7 @@ Removing old design directory at request of -rem command line option to this pro
 Running par. Please wait . . .
 
 Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
-Tue Aug 15 05:03:25 2023
+Tue Aug 15 05:22:28 2023
 
 PAR: Place And Route Diamond (64-bit) 3.12.1.454.
 Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
@@ -646,7 +646,7 @@ I/O Bank Usage Summary:
 | 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
 +----------+----------------+------------+------------+------------+
 
-Total placer CPU time: 3 secs 
+Total placer CPU time: 2 secs 
 
 Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
 
@@ -659,7 +659,7 @@ Starting router resource preassignment
 
 Completed router resource preassignment. Real time: 3 secs 
 
-Start NBR router at 05:03:28 08/15/23
+Start NBR router at 05:22:31 08/15/23
 
 *****************************************************************
 Info: NBR allows conflicts(one node used by more than one signal)
@@ -674,9 +674,9 @@ Note: NBR uses a different method to calculate timing slacks. The
       your design.                                               
 *****************************************************************
 
-Start NBR special constraint process at 05:03:28 08/15/23
+Start NBR special constraint process at 05:22:31 08/15/23
 
-Start NBR section for initial routing at 05:03:28 08/15/23
+Start NBR section for initial routing at 05:22:31 08/15/23
 Level 1, iteration 1
 0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; 
 Estimated worst slack/total negative slack: -9.776ns/-717.961ns; real time: 3 secs 
@@ -688,42 +688,42 @@ Level 3, iteration 1
 Estimated worst slack/total negative slack: -9.822ns/-765.746ns; real time: 3 secs 
 Level 4, iteration 1
 9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 3 secs 
 
 Info: Initial congestion level at 75% usage is 0
 Info: Initial congestion area  at 75% usage is 0 (0.00%)
 
-Start NBR section for normal routing at 05:03:29 08/15/23
+Start NBR section for normal routing at 05:22:31 08/15/23
 Level 4, iteration 1
 5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 3 secs 
 Level 4, iteration 2
 4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 3 secs 
 Level 4, iteration 3
 4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 3 secs 
 Level 4, iteration 4
 2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 3 secs 
 Level 4, iteration 5
 2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs 
 Level 4, iteration 6
 0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs 
 
-Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Start NBR section for performance tuning (iteration 1) at 05:22:31 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 3 secs 
 
-Start NBR section for re-routing at 05:03:29 08/15/23
+Start NBR section for re-routing at 05:22:31 08/15/23
 Level 4, iteration 1
 0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; 
-Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 4 secs 
+Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 3 secs 
 
-Start NBR section for post-routing at 05:03:29 08/15/23
+Start NBR section for post-routing at 05:22:31 08/15/23
 
 End NBR router with 0 unrouted connection
 
@@ -740,8 +740,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
 
     
 
-Total CPU time 4 secs 
-Total REAL time: 4 secs 
+Total CPU time 2 secs 
+Total REAL time: 3 secs 
 Completely routed.
 End of route.  662 routed (100.00%); 0 unrouted.
 
@@ -760,8 +760,8 @@ PAR_SUMMARY::Worst  slack> = 0.273
 PAR_SUMMARY::Timing score> = 0.000
 PAR_SUMMARY::Number of errors = 0
 
-Total CPU  time to completion: 4 secs 
-Total REAL time to completion: 4 secs 
+Total CPU  time to completion: 2 secs 
+Total REAL time to completion: 3 secs 
 
 par done!
 
@@ -798,7 +798,7 @@ Setup and Hold Report
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:29 2023
+Tue Aug 15 05:22:32 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -832,7 +832,7 @@ Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage)
 
 --------------------------------------------------------------------------------
 Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Tue Aug 15 05:03:30 2023
+Tue Aug 15 05:22:32 2023
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
diff --git a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
index bf3668f..aa1e0d3 100644
--- a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
+++ b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior
@@ -29,7 +29,7 @@ Performance Hardware Data Status: Version 1.124.
 // Package: TQFP100
 // ncd File: ram2gs_lcmxo640c_impl1.ncd
 // Version: Diamond (64-bit) 3.12.1.454
-// Written on Tue Aug 15 05:03:31 2023
+// Written on Tue Aug 15 05:22:32 2023
 // M: Minimum Performance Grade
 // iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml
 
diff --git a/CPLD/LCMXO640C/impl1/synthesis.log b/CPLD/LCMXO640C/impl1/synthesis.log
index ece5a9b..cfd0c9d 100644
--- a/CPLD/LCMXO640C/impl1/synthesis.log
+++ b/CPLD/LCMXO640C/impl1/synthesis.log
@@ -5,7 +5,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:21 2023
+Tue Aug 15 05:22:25 2023
 
 
 Command Line:  synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml 
@@ -231,7 +231,7 @@ clk0 [get_nets RCLK_c]                  |  200.000 MHz|  106.792 MHz|     5 *
 2 constraints not met.
 
 
-Peak Memory Usage: 51.215  MB
+Peak Memory Usage: 51.176  MB
 
 --------------------------------------------------------------
 Elapsed CPU time for LSE flow : 0.609  secs
diff --git a/CPLD/LCMXO640C/impl1/synthesis_lse.html b/CPLD/LCMXO640C/impl1/synthesis_lse.html
index 5a4ea61..0fd8a3e 100644
--- a/CPLD/LCMXO640C/impl1/synthesis_lse.html
+++ b/CPLD/LCMXO640C/impl1/synthesis_lse.html
@@ -14,7 +14,7 @@ Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
 Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Tue Aug 15 05:03:21 2023
+Tue Aug 15 05:22:25 2023
 
 
 Command Line:  synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml 
@@ -240,7 +240,7 @@ clk0 [get_nets RCLK_c]                  |  200.000 MHz|  106.792 MHz|     5 *
 2 constraints not met.
 
 
-Peak Memory Usage: 51.215  MB
+Peak Memory Usage: 51.176  MB
 
 --------------------------------------------------------------
 Elapsed CPU time for LSE flow : 0.609  secs
diff --git a/CPLD-old/LCMXO2/RAM2GS-LCMXO2.v b/CPLD/RAM2GS-LCMXO2.v
similarity index 100%
rename from CPLD-old/LCMXO2/RAM2GS-LCMXO2.v
rename to CPLD/RAM2GS-LCMXO2.v

    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Mon Aug 16 21:36:33 2021
-
-
-Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
-
-Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO640C
-Package:     TQFP100
-Performance: 3
-Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.17.
-Performance Hardware Data Status: Version 1.124.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
-
-
-Preference Summary:
-
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                             ES  |                           No**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
-Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 46 MB
-
-
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-
    
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    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Mon Aug 16 21:36:25 2021
-
-
-Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
-
-Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
-Design name: RAM2GS
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO256C
-Package:     TQFP100
-Performance: 3
-Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.19.
-Performance Hardware Data Status: Version 1.124.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
-
-
-Preference Summary:
-
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                             ES  |                           No**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
-Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
-Total CPU Time: 0 secs 
-Total REAL Time: 0 secs 
-Peak Memory Usage: 44 MB
-
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